1/* 2 * New-style TCG opcode generator for i386 instructions 3 * 4 * Copyright (c) 2022 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22/* 23 * Sometimes, knowing what the backend has can produce better code. 24 * The exact opcode to check depends on 32- vs. 64-bit. 25 */ 26#ifdef TARGET_X86_64 27#define TCG_TARGET_HAS_extract2_tl TCG_TARGET_HAS_extract2_i64 28#define TCG_TARGET_deposit_tl_valid TCG_TARGET_deposit_i64_valid 29#define TCG_TARGET_extract_tl_valid TCG_TARGET_extract_i64_valid 30#else 31#define TCG_TARGET_HAS_extract2_tl TCG_TARGET_HAS_extract2_i32 32#define TCG_TARGET_deposit_tl_valid TCG_TARGET_deposit_i32_valid 33#define TCG_TARGET_extract_tl_valid TCG_TARGET_extract_i32_valid 34#endif 35 36 37#define ZMM_OFFSET(reg) offsetof(CPUX86State, xmm_regs[reg]) 38 39typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); 40typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); 41typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); 42typedef void (*SSEFunc_0_eppp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 43 TCGv_ptr reg_c); 44typedef void (*SSEFunc_0_epppp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 45 TCGv_ptr reg_c, TCGv_ptr reg_d); 46typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 47 TCGv_i32 val); 48typedef void (*SSEFunc_0_epppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 49 TCGv_ptr reg_c, TCGv_i32 val); 50typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); 51typedef void (*SSEFunc_0_pppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_ptr reg_c, 52 TCGv_i32 val); 53typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 54 TCGv val); 55typedef void (*SSEFunc_0_epppti)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 56 TCGv_ptr reg_c, TCGv a0, TCGv_i32 scale); 57typedef void (*SSEFunc_0_eppppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 58 TCGv_ptr reg_c, TCGv_ptr reg_d, TCGv_i32 flags); 59typedef void (*SSEFunc_0_eppppii)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 60 TCGv_ptr reg_c, TCGv_ptr reg_d, TCGv_i32 even, 61 TCGv_i32 odd); 62 63static void gen_JMP_m(DisasContext *s, X86DecodedInsn *decode); 64static void gen_JMP(DisasContext *s, X86DecodedInsn *decode); 65 66static inline TCGv_i32 tcg_constant8u_i32(uint8_t val) 67{ 68 return tcg_constant_i32(val); 69} 70 71static void gen_NM_exception(DisasContext *s) 72{ 73 gen_exception(s, EXCP07_PREX); 74} 75 76static void gen_load_ea(DisasContext *s, AddressParts *mem, bool is_vsib) 77{ 78 TCGv ea = gen_lea_modrm_1(s, *mem, is_vsib); 79 gen_lea_v_seg(s, ea, mem->def_seg, s->override); 80} 81 82static inline int mmx_offset(MemOp ot) 83{ 84 switch (ot) { 85 case MO_8: 86 return offsetof(MMXReg, MMX_B(0)); 87 case MO_16: 88 return offsetof(MMXReg, MMX_W(0)); 89 case MO_32: 90 return offsetof(MMXReg, MMX_L(0)); 91 case MO_64: 92 return offsetof(MMXReg, MMX_Q(0)); 93 default: 94 g_assert_not_reached(); 95 } 96} 97 98static inline int xmm_offset(MemOp ot) 99{ 100 switch (ot) { 101 case MO_8: 102 return offsetof(ZMMReg, ZMM_B(0)); 103 case MO_16: 104 return offsetof(ZMMReg, ZMM_W(0)); 105 case MO_32: 106 return offsetof(ZMMReg, ZMM_L(0)); 107 case MO_64: 108 return offsetof(ZMMReg, ZMM_Q(0)); 109 case MO_128: 110 return offsetof(ZMMReg, ZMM_X(0)); 111 case MO_256: 112 return offsetof(ZMMReg, ZMM_Y(0)); 113 default: 114 g_assert_not_reached(); 115 } 116} 117 118static int vector_reg_offset(X86DecodedOp *op) 119{ 120 assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE); 121 122 if (op->unit == X86_OP_MMX) { 123 return op->offset - mmx_offset(op->ot); 124 } else { 125 return op->offset - xmm_offset(op->ot); 126 } 127} 128 129static int vector_elem_offset(X86DecodedOp *op, MemOp ot, int n) 130{ 131 int base_ofs = vector_reg_offset(op); 132 switch(ot) { 133 case MO_8: 134 if (op->unit == X86_OP_MMX) { 135 return base_ofs + offsetof(MMXReg, MMX_B(n)); 136 } else { 137 return base_ofs + offsetof(ZMMReg, ZMM_B(n)); 138 } 139 case MO_16: 140 if (op->unit == X86_OP_MMX) { 141 return base_ofs + offsetof(MMXReg, MMX_W(n)); 142 } else { 143 return base_ofs + offsetof(ZMMReg, ZMM_W(n)); 144 } 145 case MO_32: 146 if (op->unit == X86_OP_MMX) { 147 return base_ofs + offsetof(MMXReg, MMX_L(n)); 148 } else { 149 return base_ofs + offsetof(ZMMReg, ZMM_L(n)); 150 } 151 case MO_64: 152 if (op->unit == X86_OP_MMX) { 153 return base_ofs; 154 } else { 155 return base_ofs + offsetof(ZMMReg, ZMM_Q(n)); 156 } 157 case MO_128: 158 assert(op->unit == X86_OP_SSE); 159 return base_ofs + offsetof(ZMMReg, ZMM_X(n)); 160 case MO_256: 161 assert(op->unit == X86_OP_SSE); 162 return base_ofs + offsetof(ZMMReg, ZMM_Y(n)); 163 default: 164 g_assert_not_reached(); 165 } 166} 167 168static void compute_mmx_offset(X86DecodedOp *op) 169{ 170 if (!op->has_ea) { 171 op->offset = offsetof(CPUX86State, fpregs[op->n].mmx) + mmx_offset(op->ot); 172 } else { 173 op->offset = offsetof(CPUX86State, mmx_t0) + mmx_offset(op->ot); 174 } 175} 176 177static void compute_xmm_offset(X86DecodedOp *op) 178{ 179 if (!op->has_ea) { 180 op->offset = ZMM_OFFSET(op->n) + xmm_offset(op->ot); 181 } else { 182 op->offset = offsetof(CPUX86State, xmm_t0) + xmm_offset(op->ot); 183 } 184} 185 186static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs, bool aligned) 187{ 188 switch(ot) { 189 case MO_8: 190 gen_op_ld_v(s, MO_8, temp, s->A0); 191 tcg_gen_st8_tl(temp, tcg_env, dest_ofs); 192 break; 193 case MO_16: 194 gen_op_ld_v(s, MO_16, temp, s->A0); 195 tcg_gen_st16_tl(temp, tcg_env, dest_ofs); 196 break; 197 case MO_32: 198 gen_op_ld_v(s, MO_32, temp, s->A0); 199 tcg_gen_st32_tl(temp, tcg_env, dest_ofs); 200 break; 201 case MO_64: 202 gen_ldq_env_A0(s, dest_ofs); 203 break; 204 case MO_128: 205 gen_ldo_env_A0(s, dest_ofs, aligned); 206 break; 207 case MO_256: 208 gen_ldy_env_A0(s, dest_ofs, aligned); 209 break; 210 default: 211 g_assert_not_reached(); 212 } 213} 214 215static bool sse_needs_alignment(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 216{ 217 switch (decode->e.vex_class) { 218 case 2: 219 case 4: 220 if ((s->prefix & PREFIX_VEX) || 221 decode->e.vex_special == X86_VEX_SSEUnaligned) { 222 /* MOST legacy SSE instructions require aligned memory operands, but not all. */ 223 return false; 224 } 225 /* fall through */ 226 case 1: 227 return ot >= MO_128; 228 229 default: 230 return false; 231 } 232} 233 234static void gen_load(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v) 235{ 236 X86DecodedOp *op = &decode->op[opn]; 237 238 switch (op->unit) { 239 case X86_OP_SKIP: 240 return; 241 case X86_OP_SEG: 242 tcg_gen_ld32u_tl(v, tcg_env, 243 offsetof(CPUX86State,segs[op->n].selector)); 244 break; 245#ifndef CONFIG_USER_ONLY 246 case X86_OP_CR: 247 if (op->n == 8) { 248 translator_io_start(&s->base); 249 gen_helper_read_cr8(v, tcg_env); 250 } else { 251 tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, cr[op->n])); 252 } 253 break; 254 case X86_OP_DR: 255 /* CR4.DE tested in the helper. */ 256 gen_helper_get_dr(v, tcg_env, tcg_constant_i32(op->n)); 257 break; 258#endif 259 case X86_OP_INT: 260 if (op->has_ea) { 261 if (v == s->T0 && decode->e.special == X86_SPECIAL_SExtT0) { 262 gen_op_ld_v(s, op->ot | MO_SIGN, v, s->A0); 263 } else { 264 gen_op_ld_v(s, op->ot, v, s->A0); 265 } 266 267 } else if (op->ot == MO_8 && byte_reg_is_xH(s, op->n)) { 268 if (v == s->T0 && decode->e.special == X86_SPECIAL_SExtT0) { 269 tcg_gen_sextract_tl(v, cpu_regs[op->n - 4], 8, 8); 270 } else { 271 tcg_gen_extract_tl(v, cpu_regs[op->n - 4], 8, 8); 272 } 273 274 } else if (op->ot < MO_TL && v == s->T0 && 275 (decode->e.special == X86_SPECIAL_SExtT0 || 276 decode->e.special == X86_SPECIAL_ZExtT0)) { 277 if (decode->e.special == X86_SPECIAL_SExtT0) { 278 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot | MO_SIGN); 279 } else { 280 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot); 281 } 282 283 } else { 284 tcg_gen_mov_tl(v, cpu_regs[op->n]); 285 } 286 break; 287 case X86_OP_IMM: 288 tcg_gen_movi_tl(v, op->imm); 289 break; 290 291 case X86_OP_MMX: 292 compute_mmx_offset(op); 293 goto load_vector; 294 295 case X86_OP_SSE: 296 compute_xmm_offset(op); 297 load_vector: 298 if (op->has_ea) { 299 bool aligned = sse_needs_alignment(s, decode, op->ot); 300 gen_load_sse(s, v, op->ot, op->offset, aligned); 301 } 302 break; 303 304 default: 305 g_assert_not_reached(); 306 } 307} 308 309static TCGv_ptr op_ptr(X86DecodedInsn *decode, int opn) 310{ 311 X86DecodedOp *op = &decode->op[opn]; 312 313 assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE); 314 if (op->v_ptr) { 315 return op->v_ptr; 316 } 317 op->v_ptr = tcg_temp_new_ptr(); 318 319 /* The temporary points to the MMXReg or ZMMReg. */ 320 tcg_gen_addi_ptr(op->v_ptr, tcg_env, vector_reg_offset(op)); 321 return op->v_ptr; 322} 323 324#define OP_PTR0 op_ptr(decode, 0) 325#define OP_PTR1 op_ptr(decode, 1) 326#define OP_PTR2 op_ptr(decode, 2) 327 328static void gen_writeback(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v) 329{ 330 X86DecodedOp *op = &decode->op[opn]; 331 switch (op->unit) { 332 case X86_OP_SKIP: 333 break; 334 case X86_OP_SEG: 335 /* Note that gen_movl_seg takes care of interrupt shadow and TF. */ 336 gen_movl_seg(s, op->n, s->T0); 337 break; 338 case X86_OP_INT: 339 if (op->has_ea) { 340 gen_op_st_v(s, op->ot, v, s->A0); 341 } else { 342 gen_op_mov_reg_v(s, op->ot, op->n, v); 343 } 344 break; 345 case X86_OP_MMX: 346 break; 347 case X86_OP_SSE: 348 if (!op->has_ea && (s->prefix & PREFIX_VEX) && op->ot <= MO_128) { 349 tcg_gen_gvec_dup_imm(MO_64, 350 offsetof(CPUX86State, xmm_regs[op->n].ZMM_X(1)), 351 16, 16, 0); 352 } 353 break; 354#ifndef CONFIG_USER_ONLY 355 case X86_OP_CR: 356 if (op->n == 8) { 357 translator_io_start(&s->base); 358 } 359 gen_helper_write_crN(tcg_env, tcg_constant_i32(op->n), v); 360 s->base.is_jmp = DISAS_EOB_NEXT; 361 break; 362 case X86_OP_DR: 363 /* CR4.DE tested in the helper. */ 364 gen_helper_set_dr(tcg_env, tcg_constant_i32(op->n), v); 365 s->base.is_jmp = DISAS_EOB_NEXT; 366 break; 367#endif 368 default: 369 g_assert_not_reached(); 370 } 371 op->unit = X86_OP_SKIP; 372} 373 374static inline int vector_len(DisasContext *s, X86DecodedInsn *decode) 375{ 376 if (decode->e.special == X86_SPECIAL_MMX && 377 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 378 return 8; 379 } 380 return s->vex_l ? 32 : 16; 381} 382 383static void prepare_update1_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op) 384{ 385 decode->cc_dst = s->T0; 386 decode->cc_op = op; 387} 388 389static void prepare_update2_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op) 390{ 391 decode->cc_src = s->T1; 392 decode->cc_dst = s->T0; 393 decode->cc_op = op; 394} 395 396static void prepare_update_cc_incdec(X86DecodedInsn *decode, DisasContext *s, CCOp op) 397{ 398 gen_compute_eflags_c(s, s->T1); 399 prepare_update2_cc(decode, s, op); 400} 401 402static void prepare_update3_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op, TCGv reg) 403{ 404 decode->cc_src2 = reg; 405 decode->cc_src = s->T1; 406 decode->cc_dst = s->T0; 407 decode->cc_op = op; 408} 409 410static void gen_store_sse(DisasContext *s, X86DecodedInsn *decode, int src_ofs) 411{ 412 MemOp ot = decode->op[0].ot; 413 int vec_len = vector_len(s, decode); 414 bool aligned = sse_needs_alignment(s, decode, ot); 415 416 if (!decode->op[0].has_ea) { 417 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, vec_len, vec_len); 418 return; 419 } 420 421 switch (ot) { 422 case MO_64: 423 gen_stq_env_A0(s, src_ofs); 424 break; 425 case MO_128: 426 gen_sto_env_A0(s, src_ofs, aligned); 427 break; 428 case MO_256: 429 gen_sty_env_A0(s, src_ofs, aligned); 430 break; 431 default: 432 g_assert_not_reached(); 433 } 434} 435 436static void gen_helper_pavgusb(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b) 437{ 438 gen_helper_pavgb_mmx(env, reg_a, reg_a, reg_b); 439} 440 441#define FN_3DNOW_MOVE ((SSEFunc_0_epp) (uintptr_t) 1) 442static const SSEFunc_0_epp fns_3dnow[] = { 443 [0x0c] = gen_helper_pi2fw, 444 [0x0d] = gen_helper_pi2fd, 445 [0x1c] = gen_helper_pf2iw, 446 [0x1d] = gen_helper_pf2id, 447 [0x8a] = gen_helper_pfnacc, 448 [0x8e] = gen_helper_pfpnacc, 449 [0x90] = gen_helper_pfcmpge, 450 [0x94] = gen_helper_pfmin, 451 [0x96] = gen_helper_pfrcp, 452 [0x97] = gen_helper_pfrsqrt, 453 [0x9a] = gen_helper_pfsub, 454 [0x9e] = gen_helper_pfadd, 455 [0xa0] = gen_helper_pfcmpgt, 456 [0xa4] = gen_helper_pfmax, 457 [0xa6] = FN_3DNOW_MOVE, /* PFRCPIT1; no need to actually increase precision */ 458 [0xa7] = FN_3DNOW_MOVE, /* PFRSQIT1 */ 459 [0xb6] = FN_3DNOW_MOVE, /* PFRCPIT2 */ 460 [0xaa] = gen_helper_pfsubr, 461 [0xae] = gen_helper_pfacc, 462 [0xb0] = gen_helper_pfcmpeq, 463 [0xb4] = gen_helper_pfmul, 464 [0xb7] = gen_helper_pmulhrw_mmx, 465 [0xbb] = gen_helper_pswapd, 466 [0xbf] = gen_helper_pavgusb, 467}; 468 469static void gen_3dnow(DisasContext *s, X86DecodedInsn *decode) 470{ 471 uint8_t b = decode->immediate; 472 SSEFunc_0_epp fn = b < ARRAY_SIZE(fns_3dnow) ? fns_3dnow[b] : NULL; 473 474 if (!fn) { 475 gen_illegal_opcode(s); 476 return; 477 } 478 if (s->flags & HF_TS_MASK) { 479 gen_NM_exception(s); 480 return; 481 } 482 if (s->flags & HF_EM_MASK) { 483 gen_illegal_opcode(s); 484 return; 485 } 486 487 gen_helper_enter_mmx(tcg_env); 488 if (fn == FN_3DNOW_MOVE) { 489 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset); 490 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset); 491 } else { 492 fn(tcg_env, OP_PTR0, OP_PTR1); 493 } 494} 495 496/* 497 * 00 = v*ps Vps, Hps, Wpd 498 * 66 = v*pd Vpd, Hpd, Wps 499 * f3 = v*ss Vss, Hss, Wps 500 * f2 = v*sd Vsd, Hsd, Wps 501 */ 502static inline void gen_unary_fp_sse(DisasContext *s, X86DecodedInsn *decode, 503 SSEFunc_0_epp pd_xmm, SSEFunc_0_epp ps_xmm, 504 SSEFunc_0_epp pd_ymm, SSEFunc_0_epp ps_ymm, 505 SSEFunc_0_eppp sd, SSEFunc_0_eppp ss) 506{ 507 if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) { 508 SSEFunc_0_eppp fn = s->prefix & PREFIX_REPZ ? ss : sd; 509 if (!fn) { 510 gen_illegal_opcode(s); 511 return; 512 } 513 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 514 } else { 515 SSEFunc_0_epp ps, pd, fn; 516 ps = s->vex_l ? ps_ymm : ps_xmm; 517 pd = s->vex_l ? pd_ymm : pd_xmm; 518 fn = s->prefix & PREFIX_DATA ? pd : ps; 519 if (!fn) { 520 gen_illegal_opcode(s); 521 return; 522 } 523 fn(tcg_env, OP_PTR0, OP_PTR2); 524 } 525} 526#define UNARY_FP_SSE(uname, lname) \ 527static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 528{ \ 529 gen_unary_fp_sse(s, decode, \ 530 gen_helper_##lname##pd_xmm, \ 531 gen_helper_##lname##ps_xmm, \ 532 gen_helper_##lname##pd_ymm, \ 533 gen_helper_##lname##ps_ymm, \ 534 gen_helper_##lname##sd, \ 535 gen_helper_##lname##ss); \ 536} 537UNARY_FP_SSE(VSQRT, sqrt) 538 539/* 540 * 00 = v*ps Vps, Hps, Wpd 541 * 66 = v*pd Vpd, Hpd, Wps 542 * f3 = v*ss Vss, Hss, Wps 543 * f2 = v*sd Vsd, Hsd, Wps 544 */ 545static inline void gen_fp_sse(DisasContext *s, X86DecodedInsn *decode, 546 SSEFunc_0_eppp pd_xmm, SSEFunc_0_eppp ps_xmm, 547 SSEFunc_0_eppp pd_ymm, SSEFunc_0_eppp ps_ymm, 548 SSEFunc_0_eppp sd, SSEFunc_0_eppp ss) 549{ 550 SSEFunc_0_eppp ps, pd, fn; 551 if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) { 552 fn = s->prefix & PREFIX_REPZ ? ss : sd; 553 } else { 554 ps = s->vex_l ? ps_ymm : ps_xmm; 555 pd = s->vex_l ? pd_ymm : pd_xmm; 556 fn = s->prefix & PREFIX_DATA ? pd : ps; 557 } 558 if (fn) { 559 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 560 } else { 561 gen_illegal_opcode(s); 562 } 563} 564 565#define FP_SSE(uname, lname) \ 566static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 567{ \ 568 gen_fp_sse(s, decode, \ 569 gen_helper_##lname##pd_xmm, \ 570 gen_helper_##lname##ps_xmm, \ 571 gen_helper_##lname##pd_ymm, \ 572 gen_helper_##lname##ps_ymm, \ 573 gen_helper_##lname##sd, \ 574 gen_helper_##lname##ss); \ 575} 576FP_SSE(VADD, add) 577FP_SSE(VMUL, mul) 578FP_SSE(VSUB, sub) 579FP_SSE(VMIN, min) 580FP_SSE(VDIV, div) 581FP_SSE(VMAX, max) 582 583#define FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, even, odd) \ 584static void gen_##uname##Px(DisasContext *s, X86DecodedInsn *decode) \ 585{ \ 586 SSEFunc_0_eppppii xmm = s->vex_w ? gen_helper_fma4pd_xmm : gen_helper_fma4ps_xmm; \ 587 SSEFunc_0_eppppii ymm = s->vex_w ? gen_helper_fma4pd_ymm : gen_helper_fma4ps_ymm; \ 588 SSEFunc_0_eppppii fn = s->vex_l ? ymm : xmm; \ 589 \ 590 fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \ 591 tcg_constant_i32(even), \ 592 tcg_constant_i32((even) ^ (odd))); \ 593} 594 595#define FMA_SSE(uname, ptr0, ptr1, ptr2, flags) \ 596FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, flags, flags) \ 597static void gen_##uname##Sx(DisasContext *s, X86DecodedInsn *decode) \ 598{ \ 599 SSEFunc_0_eppppi fn = s->vex_w ? gen_helper_fma4sd : gen_helper_fma4ss; \ 600 \ 601 fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \ 602 tcg_constant_i32(flags)); \ 603} \ 604 605FMA_SSE(VFMADD231, OP_PTR1, OP_PTR2, OP_PTR0, 0) 606FMA_SSE(VFMADD213, OP_PTR1, OP_PTR0, OP_PTR2, 0) 607FMA_SSE(VFMADD132, OP_PTR0, OP_PTR2, OP_PTR1, 0) 608 609FMA_SSE(VFNMADD231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_product) 610FMA_SSE(VFNMADD213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_product) 611FMA_SSE(VFNMADD132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_product) 612 613FMA_SSE(VFMSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c) 614FMA_SSE(VFMSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c) 615FMA_SSE(VFMSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c) 616 617FMA_SSE(VFNMSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c|float_muladd_negate_product) 618FMA_SSE(VFNMSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c|float_muladd_negate_product) 619FMA_SSE(VFNMSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c|float_muladd_negate_product) 620 621FMA_SSE_PACKED(VFMADDSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c, 0) 622FMA_SSE_PACKED(VFMADDSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c, 0) 623FMA_SSE_PACKED(VFMADDSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c, 0) 624 625FMA_SSE_PACKED(VFMSUBADD231, OP_PTR1, OP_PTR2, OP_PTR0, 0, float_muladd_negate_c) 626FMA_SSE_PACKED(VFMSUBADD213, OP_PTR1, OP_PTR0, OP_PTR2, 0, float_muladd_negate_c) 627FMA_SSE_PACKED(VFMSUBADD132, OP_PTR0, OP_PTR2, OP_PTR1, 0, float_muladd_negate_c) 628 629#define FP_UNPACK_SSE(uname, lname) \ 630static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 631{ \ 632 /* PS maps to the DQ integer instruction, PD maps to QDQ. */ \ 633 gen_fp_sse(s, decode, \ 634 gen_helper_##lname##qdq_xmm, \ 635 gen_helper_##lname##dq_xmm, \ 636 gen_helper_##lname##qdq_ymm, \ 637 gen_helper_##lname##dq_ymm, \ 638 NULL, NULL); \ 639} 640FP_UNPACK_SSE(VUNPCKLPx, punpckl) 641FP_UNPACK_SSE(VUNPCKHPx, punpckh) 642 643/* 644 * 00 = v*ps Vps, Wpd 645 * f3 = v*ss Vss, Wps 646 */ 647static inline void gen_unary_fp32_sse(DisasContext *s, X86DecodedInsn *decode, 648 SSEFunc_0_epp ps_xmm, 649 SSEFunc_0_epp ps_ymm, 650 SSEFunc_0_eppp ss) 651{ 652 if ((s->prefix & (PREFIX_DATA | PREFIX_REPNZ)) != 0) { 653 goto illegal_op; 654 } else if (s->prefix & PREFIX_REPZ) { 655 if (!ss) { 656 goto illegal_op; 657 } 658 ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 659 } else { 660 SSEFunc_0_epp fn = s->vex_l ? ps_ymm : ps_xmm; 661 if (!fn) { 662 goto illegal_op; 663 } 664 fn(tcg_env, OP_PTR0, OP_PTR2); 665 } 666 return; 667 668illegal_op: 669 gen_illegal_opcode(s); 670} 671#define UNARY_FP32_SSE(uname, lname) \ 672static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 673{ \ 674 gen_unary_fp32_sse(s, decode, \ 675 gen_helper_##lname##ps_xmm, \ 676 gen_helper_##lname##ps_ymm, \ 677 gen_helper_##lname##ss); \ 678} 679UNARY_FP32_SSE(VRSQRT, rsqrt) 680UNARY_FP32_SSE(VRCP, rcp) 681 682/* 683 * 66 = v*pd Vpd, Hpd, Wpd 684 * f2 = v*ps Vps, Hps, Wps 685 */ 686static inline void gen_horizontal_fp_sse(DisasContext *s, X86DecodedInsn *decode, 687 SSEFunc_0_eppp pd_xmm, SSEFunc_0_eppp ps_xmm, 688 SSEFunc_0_eppp pd_ymm, SSEFunc_0_eppp ps_ymm) 689{ 690 SSEFunc_0_eppp ps, pd, fn; 691 ps = s->vex_l ? ps_ymm : ps_xmm; 692 pd = s->vex_l ? pd_ymm : pd_xmm; 693 fn = s->prefix & PREFIX_DATA ? pd : ps; 694 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 695} 696#define HORIZONTAL_FP_SSE(uname, lname) \ 697static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 698{ \ 699 gen_horizontal_fp_sse(s, decode, \ 700 gen_helper_##lname##pd_xmm, gen_helper_##lname##ps_xmm, \ 701 gen_helper_##lname##pd_ymm, gen_helper_##lname##ps_ymm); \ 702} 703HORIZONTAL_FP_SSE(VHADD, hadd) 704HORIZONTAL_FP_SSE(VHSUB, hsub) 705HORIZONTAL_FP_SSE(VADDSUB, addsub) 706 707static inline void gen_ternary_sse(DisasContext *s, X86DecodedInsn *decode, 708 int op3, SSEFunc_0_epppp xmm, SSEFunc_0_epppp ymm) 709{ 710 SSEFunc_0_epppp fn = s->vex_l ? ymm : xmm; 711 TCGv_ptr ptr3 = tcg_temp_new_ptr(); 712 713 /* The format of the fourth input is Lx */ 714 tcg_gen_addi_ptr(ptr3, tcg_env, ZMM_OFFSET(op3)); 715 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3); 716} 717#define TERNARY_SSE(uname, uvname, lname) \ 718static void gen_##uvname(DisasContext *s, X86DecodedInsn *decode) \ 719{ \ 720 gen_ternary_sse(s, decode, (uint8_t)decode->immediate >> 4, \ 721 gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \ 722} \ 723static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 724{ \ 725 gen_ternary_sse(s, decode, 0, \ 726 gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \ 727} 728TERNARY_SSE(BLENDVPS, VBLENDVPS, blendvps) 729TERNARY_SSE(BLENDVPD, VBLENDVPD, blendvpd) 730TERNARY_SSE(PBLENDVB, VPBLENDVB, pblendvb) 731 732static inline void gen_binary_imm_sse(DisasContext *s, X86DecodedInsn *decode, 733 SSEFunc_0_epppi xmm, SSEFunc_0_epppi ymm) 734{ 735 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 736 if (!s->vex_l) { 737 xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 738 } else { 739 ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 740 } 741} 742 743#define BINARY_IMM_SSE(uname, lname) \ 744static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 745{ \ 746 gen_binary_imm_sse(s, decode, \ 747 gen_helper_##lname##_xmm, \ 748 gen_helper_##lname##_ymm); \ 749} 750 751BINARY_IMM_SSE(VBLENDPD, blendpd) 752BINARY_IMM_SSE(VBLENDPS, blendps) 753BINARY_IMM_SSE(VPBLENDW, pblendw) 754BINARY_IMM_SSE(VDDPS, dpps) 755#define gen_helper_dppd_ymm NULL 756BINARY_IMM_SSE(VDDPD, dppd) 757BINARY_IMM_SSE(VMPSADBW, mpsadbw) 758BINARY_IMM_SSE(PCLMULQDQ, pclmulqdq) 759 760 761#define UNARY_INT_GVEC(uname, func, ...) \ 762static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 763{ \ 764 int vec_len = vector_len(s, decode); \ 765 \ 766 func(__VA_ARGS__, decode->op[0].offset, \ 767 decode->op[2].offset, vec_len, vec_len); \ 768} 769UNARY_INT_GVEC(PABSB, tcg_gen_gvec_abs, MO_8) 770UNARY_INT_GVEC(PABSW, tcg_gen_gvec_abs, MO_16) 771UNARY_INT_GVEC(PABSD, tcg_gen_gvec_abs, MO_32) 772UNARY_INT_GVEC(VBROADCASTx128, tcg_gen_gvec_dup_mem, MO_128) 773UNARY_INT_GVEC(VPBROADCASTB, tcg_gen_gvec_dup_mem, MO_8) 774UNARY_INT_GVEC(VPBROADCASTW, tcg_gen_gvec_dup_mem, MO_16) 775UNARY_INT_GVEC(VPBROADCASTD, tcg_gen_gvec_dup_mem, MO_32) 776UNARY_INT_GVEC(VPBROADCASTQ, tcg_gen_gvec_dup_mem, MO_64) 777 778 779#define BINARY_INT_GVEC(uname, func, ...) \ 780static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 781{ \ 782 int vec_len = vector_len(s, decode); \ 783 \ 784 func(__VA_ARGS__, \ 785 decode->op[0].offset, decode->op[1].offset, \ 786 decode->op[2].offset, vec_len, vec_len); \ 787} 788 789BINARY_INT_GVEC(PADDB, tcg_gen_gvec_add, MO_8) 790BINARY_INT_GVEC(PADDW, tcg_gen_gvec_add, MO_16) 791BINARY_INT_GVEC(PADDD, tcg_gen_gvec_add, MO_32) 792BINARY_INT_GVEC(PADDQ, tcg_gen_gvec_add, MO_64) 793BINARY_INT_GVEC(PADDSB, tcg_gen_gvec_ssadd, MO_8) 794BINARY_INT_GVEC(PADDSW, tcg_gen_gvec_ssadd, MO_16) 795BINARY_INT_GVEC(PADDUSB, tcg_gen_gvec_usadd, MO_8) 796BINARY_INT_GVEC(PADDUSW, tcg_gen_gvec_usadd, MO_16) 797BINARY_INT_GVEC(PAND, tcg_gen_gvec_and, MO_64) 798BINARY_INT_GVEC(PCMPEQB, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_8) 799BINARY_INT_GVEC(PCMPEQD, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_32) 800BINARY_INT_GVEC(PCMPEQW, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_16) 801BINARY_INT_GVEC(PCMPEQQ, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_64) 802BINARY_INT_GVEC(PCMPGTB, tcg_gen_gvec_cmp, TCG_COND_GT, MO_8) 803BINARY_INT_GVEC(PCMPGTW, tcg_gen_gvec_cmp, TCG_COND_GT, MO_16) 804BINARY_INT_GVEC(PCMPGTD, tcg_gen_gvec_cmp, TCG_COND_GT, MO_32) 805BINARY_INT_GVEC(PCMPGTQ, tcg_gen_gvec_cmp, TCG_COND_GT, MO_64) 806BINARY_INT_GVEC(PMAXSB, tcg_gen_gvec_smax, MO_8) 807BINARY_INT_GVEC(PMAXSW, tcg_gen_gvec_smax, MO_16) 808BINARY_INT_GVEC(PMAXSD, tcg_gen_gvec_smax, MO_32) 809BINARY_INT_GVEC(PMAXUB, tcg_gen_gvec_umax, MO_8) 810BINARY_INT_GVEC(PMAXUW, tcg_gen_gvec_umax, MO_16) 811BINARY_INT_GVEC(PMAXUD, tcg_gen_gvec_umax, MO_32) 812BINARY_INT_GVEC(PMINSB, tcg_gen_gvec_smin, MO_8) 813BINARY_INT_GVEC(PMINSW, tcg_gen_gvec_smin, MO_16) 814BINARY_INT_GVEC(PMINSD, tcg_gen_gvec_smin, MO_32) 815BINARY_INT_GVEC(PMINUB, tcg_gen_gvec_umin, MO_8) 816BINARY_INT_GVEC(PMINUW, tcg_gen_gvec_umin, MO_16) 817BINARY_INT_GVEC(PMINUD, tcg_gen_gvec_umin, MO_32) 818BINARY_INT_GVEC(PMULLW, tcg_gen_gvec_mul, MO_16) 819BINARY_INT_GVEC(PMULLD, tcg_gen_gvec_mul, MO_32) 820BINARY_INT_GVEC(POR, tcg_gen_gvec_or, MO_64) 821BINARY_INT_GVEC(PSUBB, tcg_gen_gvec_sub, MO_8) 822BINARY_INT_GVEC(PSUBW, tcg_gen_gvec_sub, MO_16) 823BINARY_INT_GVEC(PSUBD, tcg_gen_gvec_sub, MO_32) 824BINARY_INT_GVEC(PSUBQ, tcg_gen_gvec_sub, MO_64) 825BINARY_INT_GVEC(PSUBSB, tcg_gen_gvec_sssub, MO_8) 826BINARY_INT_GVEC(PSUBSW, tcg_gen_gvec_sssub, MO_16) 827BINARY_INT_GVEC(PSUBUSB, tcg_gen_gvec_ussub, MO_8) 828BINARY_INT_GVEC(PSUBUSW, tcg_gen_gvec_ussub, MO_16) 829BINARY_INT_GVEC(PXOR, tcg_gen_gvec_xor, MO_64) 830 831 832/* 833 * 00 = p* Pq, Qq (if mmx not NULL; no VEX) 834 * 66 = vp* Vx, Hx, Wx 835 * 836 * These are really the same encoding, because 1) V is the same as P when VEX.V 837 * is not present 2) P and Q are the same as H and W apart from MM/XMM 838 */ 839static inline void gen_binary_int_sse(DisasContext *s, X86DecodedInsn *decode, 840 SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm) 841{ 842 assert(!!mmx == !!(decode->e.special == X86_SPECIAL_MMX)); 843 844 if (mmx && (s->prefix & PREFIX_VEX) && !(s->prefix & PREFIX_DATA)) { 845 /* VEX encoding is not applicable to MMX instructions. */ 846 gen_illegal_opcode(s); 847 return; 848 } 849 if (!(s->prefix & PREFIX_DATA)) { 850 mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 851 } else if (!s->vex_l) { 852 xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 853 } else { 854 ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 855 } 856} 857 858 859#define BINARY_INT_MMX(uname, lname) \ 860static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 861{ \ 862 gen_binary_int_sse(s, decode, \ 863 gen_helper_##lname##_mmx, \ 864 gen_helper_##lname##_xmm, \ 865 gen_helper_##lname##_ymm); \ 866} 867BINARY_INT_MMX(PUNPCKLBW, punpcklbw) 868BINARY_INT_MMX(PUNPCKLWD, punpcklwd) 869BINARY_INT_MMX(PUNPCKLDQ, punpckldq) 870BINARY_INT_MMX(PACKSSWB, packsswb) 871BINARY_INT_MMX(PACKUSWB, packuswb) 872BINARY_INT_MMX(PUNPCKHBW, punpckhbw) 873BINARY_INT_MMX(PUNPCKHWD, punpckhwd) 874BINARY_INT_MMX(PUNPCKHDQ, punpckhdq) 875BINARY_INT_MMX(PACKSSDW, packssdw) 876 877BINARY_INT_MMX(PAVGB, pavgb) 878BINARY_INT_MMX(PAVGW, pavgw) 879BINARY_INT_MMX(PMADDWD, pmaddwd) 880BINARY_INT_MMX(PMULHUW, pmulhuw) 881BINARY_INT_MMX(PMULHW, pmulhw) 882BINARY_INT_MMX(PMULUDQ, pmuludq) 883BINARY_INT_MMX(PSADBW, psadbw) 884 885BINARY_INT_MMX(PSLLW_r, psllw) 886BINARY_INT_MMX(PSLLD_r, pslld) 887BINARY_INT_MMX(PSLLQ_r, psllq) 888BINARY_INT_MMX(PSRLW_r, psrlw) 889BINARY_INT_MMX(PSRLD_r, psrld) 890BINARY_INT_MMX(PSRLQ_r, psrlq) 891BINARY_INT_MMX(PSRAW_r, psraw) 892BINARY_INT_MMX(PSRAD_r, psrad) 893 894BINARY_INT_MMX(PHADDW, phaddw) 895BINARY_INT_MMX(PHADDSW, phaddsw) 896BINARY_INT_MMX(PHADDD, phaddd) 897BINARY_INT_MMX(PHSUBW, phsubw) 898BINARY_INT_MMX(PHSUBSW, phsubsw) 899BINARY_INT_MMX(PHSUBD, phsubd) 900BINARY_INT_MMX(PMADDUBSW, pmaddubsw) 901BINARY_INT_MMX(PSHUFB, pshufb) 902BINARY_INT_MMX(PSIGNB, psignb) 903BINARY_INT_MMX(PSIGNW, psignw) 904BINARY_INT_MMX(PSIGND, psignd) 905BINARY_INT_MMX(PMULHRSW, pmulhrsw) 906 907/* Instructions with no MMX equivalent. */ 908#define BINARY_INT_SSE(uname, lname) \ 909static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 910{ \ 911 gen_binary_int_sse(s, decode, \ 912 NULL, \ 913 gen_helper_##lname##_xmm, \ 914 gen_helper_##lname##_ymm); \ 915} 916 917/* Instructions with no MMX equivalent. */ 918BINARY_INT_SSE(PUNPCKLQDQ, punpcklqdq) 919BINARY_INT_SSE(PUNPCKHQDQ, punpckhqdq) 920BINARY_INT_SSE(VPACKUSDW, packusdw) 921BINARY_INT_SSE(VPERMILPS, vpermilps) 922BINARY_INT_SSE(VPERMILPD, vpermilpd) 923BINARY_INT_SSE(VMASKMOVPS, vpmaskmovd) 924BINARY_INT_SSE(VMASKMOVPD, vpmaskmovq) 925 926BINARY_INT_SSE(PMULDQ, pmuldq) 927 928BINARY_INT_SSE(VAESDEC, aesdec) 929BINARY_INT_SSE(VAESDECLAST, aesdeclast) 930BINARY_INT_SSE(VAESENC, aesenc) 931BINARY_INT_SSE(VAESENCLAST, aesenclast) 932 933#define UNARY_CMP_SSE(uname, lname) \ 934static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 935{ \ 936 if (!s->vex_l) { \ 937 gen_helper_##lname##_xmm(tcg_env, OP_PTR1, OP_PTR2); \ 938 } else { \ 939 gen_helper_##lname##_ymm(tcg_env, OP_PTR1, OP_PTR2); \ 940 } \ 941 assume_cc_op(s, CC_OP_EFLAGS); \ 942} 943UNARY_CMP_SSE(VPTEST, ptest) 944UNARY_CMP_SSE(VTESTPS, vtestps) 945UNARY_CMP_SSE(VTESTPD, vtestpd) 946 947static inline void gen_unary_int_sse(DisasContext *s, X86DecodedInsn *decode, 948 SSEFunc_0_epp xmm, SSEFunc_0_epp ymm) 949{ 950 if (!s->vex_l) { 951 xmm(tcg_env, OP_PTR0, OP_PTR2); 952 } else { 953 ymm(tcg_env, OP_PTR0, OP_PTR2); 954 } 955} 956 957#define UNARY_INT_SSE(uname, lname) \ 958static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 959{ \ 960 gen_unary_int_sse(s, decode, \ 961 gen_helper_##lname##_xmm, \ 962 gen_helper_##lname##_ymm); \ 963} 964 965UNARY_INT_SSE(VPMOVSXBW, pmovsxbw) 966UNARY_INT_SSE(VPMOVSXBD, pmovsxbd) 967UNARY_INT_SSE(VPMOVSXBQ, pmovsxbq) 968UNARY_INT_SSE(VPMOVSXWD, pmovsxwd) 969UNARY_INT_SSE(VPMOVSXWQ, pmovsxwq) 970UNARY_INT_SSE(VPMOVSXDQ, pmovsxdq) 971 972UNARY_INT_SSE(VPMOVZXBW, pmovzxbw) 973UNARY_INT_SSE(VPMOVZXBD, pmovzxbd) 974UNARY_INT_SSE(VPMOVZXBQ, pmovzxbq) 975UNARY_INT_SSE(VPMOVZXWD, pmovzxwd) 976UNARY_INT_SSE(VPMOVZXWQ, pmovzxwq) 977UNARY_INT_SSE(VPMOVZXDQ, pmovzxdq) 978 979UNARY_INT_SSE(VMOVSLDUP, pmovsldup) 980UNARY_INT_SSE(VMOVSHDUP, pmovshdup) 981UNARY_INT_SSE(VMOVDDUP, pmovdldup) 982 983UNARY_INT_SSE(VCVTDQ2PD, cvtdq2pd) 984UNARY_INT_SSE(VCVTPD2DQ, cvtpd2dq) 985UNARY_INT_SSE(VCVTTPD2DQ, cvttpd2dq) 986UNARY_INT_SSE(VCVTDQ2PS, cvtdq2ps) 987UNARY_INT_SSE(VCVTPS2DQ, cvtps2dq) 988UNARY_INT_SSE(VCVTTPS2DQ, cvttps2dq) 989UNARY_INT_SSE(VCVTPH2PS, cvtph2ps) 990 991 992static inline void gen_unary_imm_sse(DisasContext *s, X86DecodedInsn *decode, 993 SSEFunc_0_ppi xmm, SSEFunc_0_ppi ymm) 994{ 995 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 996 if (!s->vex_l) { 997 xmm(OP_PTR0, OP_PTR1, imm); 998 } else { 999 ymm(OP_PTR0, OP_PTR1, imm); 1000 } 1001} 1002 1003#define UNARY_IMM_SSE(uname, lname) \ 1004static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1005{ \ 1006 gen_unary_imm_sse(s, decode, \ 1007 gen_helper_##lname##_xmm, \ 1008 gen_helper_##lname##_ymm); \ 1009} 1010 1011UNARY_IMM_SSE(PSHUFD, pshufd) 1012UNARY_IMM_SSE(PSHUFHW, pshufhw) 1013UNARY_IMM_SSE(PSHUFLW, pshuflw) 1014#define gen_helper_vpermq_xmm NULL 1015UNARY_IMM_SSE(VPERMQ, vpermq) 1016UNARY_IMM_SSE(VPERMILPS_i, vpermilps_imm) 1017UNARY_IMM_SSE(VPERMILPD_i, vpermilpd_imm) 1018 1019static inline void gen_unary_imm_fp_sse(DisasContext *s, X86DecodedInsn *decode, 1020 SSEFunc_0_eppi xmm, SSEFunc_0_eppi ymm) 1021{ 1022 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 1023 if (!s->vex_l) { 1024 xmm(tcg_env, OP_PTR0, OP_PTR1, imm); 1025 } else { 1026 ymm(tcg_env, OP_PTR0, OP_PTR1, imm); 1027 } 1028} 1029 1030#define UNARY_IMM_FP_SSE(uname, lname) \ 1031static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1032{ \ 1033 gen_unary_imm_fp_sse(s, decode, \ 1034 gen_helper_##lname##_xmm, \ 1035 gen_helper_##lname##_ymm); \ 1036} 1037 1038UNARY_IMM_FP_SSE(VROUNDPS, roundps) 1039UNARY_IMM_FP_SSE(VROUNDPD, roundpd) 1040 1041static inline void gen_vexw_avx(DisasContext *s, X86DecodedInsn *decode, 1042 SSEFunc_0_eppp d_xmm, SSEFunc_0_eppp q_xmm, 1043 SSEFunc_0_eppp d_ymm, SSEFunc_0_eppp q_ymm) 1044{ 1045 SSEFunc_0_eppp d = s->vex_l ? d_ymm : d_xmm; 1046 SSEFunc_0_eppp q = s->vex_l ? q_ymm : q_xmm; 1047 SSEFunc_0_eppp fn = s->vex_w ? q : d; 1048 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 1049} 1050 1051/* VEX.W affects whether to operate on 32- or 64-bit elements. */ 1052#define VEXW_AVX(uname, lname) \ 1053static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1054{ \ 1055 gen_vexw_avx(s, decode, \ 1056 gen_helper_##lname##d_xmm, gen_helper_##lname##q_xmm, \ 1057 gen_helper_##lname##d_ymm, gen_helper_##lname##q_ymm); \ 1058} 1059VEXW_AVX(VPSLLV, vpsllv) 1060VEXW_AVX(VPSRLV, vpsrlv) 1061VEXW_AVX(VPSRAV, vpsrav) 1062VEXW_AVX(VPMASKMOV, vpmaskmov) 1063 1064/* Same as above, but with extra arguments to the helper. */ 1065static inline void gen_vsib_avx(DisasContext *s, X86DecodedInsn *decode, 1066 SSEFunc_0_epppti d_xmm, SSEFunc_0_epppti q_xmm, 1067 SSEFunc_0_epppti d_ymm, SSEFunc_0_epppti q_ymm) 1068{ 1069 SSEFunc_0_epppti d = s->vex_l ? d_ymm : d_xmm; 1070 SSEFunc_0_epppti q = s->vex_l ? q_ymm : q_xmm; 1071 SSEFunc_0_epppti fn = s->vex_w ? q : d; 1072 TCGv_i32 scale = tcg_constant_i32(decode->mem.scale); 1073 TCGv_ptr index = tcg_temp_new_ptr(); 1074 1075 /* Pass third input as (index, base, scale) */ 1076 tcg_gen_addi_ptr(index, tcg_env, ZMM_OFFSET(decode->mem.index)); 1077 fn(tcg_env, OP_PTR0, OP_PTR1, index, s->A0, scale); 1078 1079 /* 1080 * There are two output operands, so zero OP1's high 128 bits 1081 * in the VEX.128 case. 1082 */ 1083 if (!s->vex_l) { 1084 int ymmh_ofs = vector_elem_offset(&decode->op[1], MO_128, 1); 1085 tcg_gen_gvec_dup_imm(MO_64, ymmh_ofs, 16, 16, 0); 1086 } 1087} 1088#define VSIB_AVX(uname, lname) \ 1089static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1090{ \ 1091 gen_vsib_avx(s, decode, \ 1092 gen_helper_##lname##d_xmm, gen_helper_##lname##q_xmm, \ 1093 gen_helper_##lname##d_ymm, gen_helper_##lname##q_ymm); \ 1094} 1095VSIB_AVX(VPGATHERD, vpgatherd) 1096VSIB_AVX(VPGATHERQ, vpgatherq) 1097 1098static void gen_AAA(DisasContext *s, X86DecodedInsn *decode) 1099{ 1100 gen_update_cc_op(s); 1101 gen_helper_aaa(tcg_env); 1102 assume_cc_op(s, CC_OP_EFLAGS); 1103} 1104 1105static void gen_AAD(DisasContext *s, X86DecodedInsn *decode) 1106{ 1107 gen_helper_aad(s->T0, s->T0, s->T1); 1108 prepare_update1_cc(decode, s, CC_OP_LOGICB); 1109} 1110 1111static void gen_AAM(DisasContext *s, X86DecodedInsn *decode) 1112{ 1113 if (decode->immediate == 0) { 1114 gen_exception(s, EXCP00_DIVZ); 1115 } else { 1116 gen_helper_aam(s->T0, s->T0, s->T1); 1117 prepare_update1_cc(decode, s, CC_OP_LOGICB); 1118 } 1119} 1120 1121static void gen_AAS(DisasContext *s, X86DecodedInsn *decode) 1122{ 1123 gen_update_cc_op(s); 1124 gen_helper_aas(tcg_env); 1125 assume_cc_op(s, CC_OP_EFLAGS); 1126} 1127 1128static void gen_ADC(DisasContext *s, X86DecodedInsn *decode) 1129{ 1130 MemOp ot = decode->op[1].ot; 1131 TCGv c_in = tcg_temp_new(); 1132 1133 gen_compute_eflags_c(s, c_in); 1134 if (s->prefix & PREFIX_LOCK) { 1135 tcg_gen_add_tl(s->T0, c_in, s->T1); 1136 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T0, 1137 s->mem_index, ot | MO_LE); 1138 } else { 1139 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1140 tcg_gen_add_tl(s->T0, s->T0, c_in); 1141 } 1142 prepare_update3_cc(decode, s, CC_OP_ADCB + ot, c_in); 1143} 1144 1145static void gen_ADCOX(DisasContext *s, X86DecodedInsn *decode, int cc_op) 1146{ 1147 MemOp ot = decode->op[0].ot; 1148 TCGv carry_in = NULL; 1149 TCGv *carry_out = (cc_op == CC_OP_ADCX ? &decode->cc_dst : &decode->cc_src2); 1150 TCGv zero; 1151 1152 decode->cc_op = cc_op; 1153 *carry_out = tcg_temp_new(); 1154 if (CC_OP_HAS_EFLAGS(s->cc_op)) { 1155 decode->cc_src = cpu_cc_src; 1156 1157 /* Re-use the carry-out from a previous round? */ 1158 if (s->cc_op == cc_op || s->cc_op == CC_OP_ADCOX) { 1159 carry_in = (cc_op == CC_OP_ADCX ? cpu_cc_dst : cpu_cc_src2); 1160 } 1161 1162 /* Preserve the opposite carry from previous rounds? */ 1163 if (s->cc_op != cc_op && s->cc_op != CC_OP_EFLAGS) { 1164 decode->cc_op = CC_OP_ADCOX; 1165 if (carry_out == &decode->cc_dst) { 1166 decode->cc_src2 = cpu_cc_src2; 1167 } else { 1168 decode->cc_dst = cpu_cc_dst; 1169 } 1170 } 1171 } else { 1172 decode->cc_src = tcg_temp_new(); 1173 gen_mov_eflags(s, decode->cc_src); 1174 } 1175 1176 if (!carry_in) { 1177 /* Get carry_in out of EFLAGS. */ 1178 carry_in = tcg_temp_new(); 1179 tcg_gen_extract_tl(carry_in, decode->cc_src, 1180 ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1); 1181 } 1182 1183 switch (ot) { 1184#ifdef TARGET_X86_64 1185 case MO_32: 1186 /* If TL is 64-bit just do everything in 64-bit arithmetic. */ 1187 tcg_gen_ext32u_tl(s->T0, s->T0); 1188 tcg_gen_ext32u_tl(s->T1, s->T1); 1189 tcg_gen_add_i64(s->T0, s->T0, s->T1); 1190 tcg_gen_add_i64(s->T0, s->T0, carry_in); 1191 tcg_gen_shri_i64(*carry_out, s->T0, 32); 1192 break; 1193#endif 1194 default: 1195 zero = tcg_constant_tl(0); 1196 tcg_gen_add2_tl(s->T0, *carry_out, s->T0, zero, carry_in, zero); 1197 tcg_gen_add2_tl(s->T0, *carry_out, s->T0, *carry_out, s->T1, zero); 1198 break; 1199 } 1200} 1201 1202static void gen_ADCX(DisasContext *s, X86DecodedInsn *decode) 1203{ 1204 gen_ADCOX(s, decode, CC_OP_ADCX); 1205} 1206 1207static void gen_ADD(DisasContext *s, X86DecodedInsn *decode) 1208{ 1209 MemOp ot = decode->op[1].ot; 1210 1211 if (s->prefix & PREFIX_LOCK) { 1212 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 1213 s->mem_index, ot | MO_LE); 1214 } else { 1215 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1216 } 1217 prepare_update2_cc(decode, s, CC_OP_ADDB + ot); 1218} 1219 1220static void gen_ADOX(DisasContext *s, X86DecodedInsn *decode) 1221{ 1222 gen_ADCOX(s, decode, CC_OP_ADOX); 1223} 1224 1225static void gen_AND(DisasContext *s, X86DecodedInsn *decode) 1226{ 1227 MemOp ot = decode->op[1].ot; 1228 1229 if (s->prefix & PREFIX_LOCK) { 1230 tcg_gen_atomic_and_fetch_tl(s->T0, s->A0, s->T1, 1231 s->mem_index, ot | MO_LE); 1232 } else { 1233 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1234 } 1235 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1236} 1237 1238static void gen_ANDN(DisasContext *s, X86DecodedInsn *decode) 1239{ 1240 MemOp ot = decode->op[0].ot; 1241 1242 tcg_gen_andc_tl(s->T0, s->T1, s->T0); 1243 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1244} 1245 1246static void gen_ARPL(DisasContext *s, X86DecodedInsn *decode) 1247{ 1248 TCGv zf = tcg_temp_new(); 1249 TCGv flags = tcg_temp_new(); 1250 1251 gen_mov_eflags(s, flags); 1252 1253 /* Compute adjusted DST in T1, merging in SRC[RPL]. */ 1254 tcg_gen_deposit_tl(s->T1, s->T0, s->T1, 0, 2); 1255 1256 /* Z flag set if DST[RPL] < SRC[RPL] */ 1257 tcg_gen_setcond_tl(TCG_COND_LTU, zf, s->T0, s->T1); 1258 tcg_gen_deposit_tl(flags, flags, zf, ctz32(CC_Z), 1); 1259 1260 /* Place maximum RPL in DST */ 1261 tcg_gen_umax_tl(s->T0, s->T0, s->T1); 1262 1263 decode->cc_src = flags; 1264 decode->cc_op = CC_OP_EFLAGS; 1265} 1266 1267static void gen_BEXTR(DisasContext *s, X86DecodedInsn *decode) 1268{ 1269 MemOp ot = decode->op[0].ot; 1270 TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); 1271 TCGv zero = tcg_constant_tl(0); 1272 TCGv mone = tcg_constant_tl(-1); 1273 1274 /* 1275 * Extract START, and shift the operand. 1276 * Shifts larger than operand size get zeros. 1277 */ 1278 tcg_gen_ext8u_tl(s->A0, s->T1); 1279 tcg_gen_shr_tl(s->T0, s->T0, s->A0); 1280 1281 tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound, s->T0, zero); 1282 1283 /* 1284 * Extract the LEN into an inverse mask. Lengths larger than 1285 * operand size get all zeros, length 0 gets all ones. 1286 */ 1287 tcg_gen_extract_tl(s->A0, s->T1, 8, 8); 1288 tcg_gen_shl_tl(s->T1, mone, s->A0); 1289 tcg_gen_movcond_tl(TCG_COND_LEU, s->T1, s->A0, bound, s->T1, zero); 1290 tcg_gen_andc_tl(s->T0, s->T0, s->T1); 1291 1292 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1293} 1294 1295static void gen_BLSI(DisasContext *s, X86DecodedInsn *decode) 1296{ 1297 MemOp ot = decode->op[0].ot; 1298 1299 /* input in T1, which is ready for prepare_update2_cc */ 1300 tcg_gen_neg_tl(s->T0, s->T1); 1301 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1302 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1303} 1304 1305static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode) 1306{ 1307 MemOp ot = decode->op[0].ot; 1308 1309 /* input in T1, which is ready for prepare_update2_cc */ 1310 tcg_gen_subi_tl(s->T0, s->T1, 1); 1311 tcg_gen_xor_tl(s->T0, s->T0, s->T1); 1312 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1313} 1314 1315static void gen_BLSR(DisasContext *s, X86DecodedInsn *decode) 1316{ 1317 MemOp ot = decode->op[0].ot; 1318 1319 /* input in T1, which is ready for prepare_update2_cc */ 1320 tcg_gen_subi_tl(s->T0, s->T1, 1); 1321 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1322 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1323} 1324 1325static void gen_BOUND(DisasContext *s, X86DecodedInsn *decode) 1326{ 1327 TCGv_i32 op = tcg_temp_new_i32(); 1328 tcg_gen_trunc_tl_i32(op, s->T0); 1329 if (decode->op[1].ot == MO_16) { 1330 gen_helper_boundw(tcg_env, s->A0, op); 1331 } else { 1332 gen_helper_boundl(tcg_env, s->A0, op); 1333 } 1334} 1335 1336/* Non-standard convention - on entry T0 is zero-extended input, T1 is the output. */ 1337static void gen_BSF(DisasContext *s, X86DecodedInsn *decode) 1338{ 1339 MemOp ot = decode->op[0].ot; 1340 1341 /* Only the Z bit is defined and it is related to the input. */ 1342 decode->cc_dst = tcg_temp_new(); 1343 decode->cc_op = CC_OP_LOGICB + ot; 1344 tcg_gen_mov_tl(decode->cc_dst, s->T0); 1345 1346 /* 1347 * The manual says that the output is undefined when the 1348 * input is zero, but real hardware leaves it unchanged, and 1349 * real programs appear to depend on that. Accomplish this 1350 * by passing the output as the value to return upon zero. 1351 */ 1352 tcg_gen_ctz_tl(s->T0, s->T0, s->T1); 1353} 1354 1355/* Non-standard convention - on entry T0 is zero-extended input, T1 is the output. */ 1356static void gen_BSR(DisasContext *s, X86DecodedInsn *decode) 1357{ 1358 MemOp ot = decode->op[0].ot; 1359 1360 /* Only the Z bit is defined and it is related to the input. */ 1361 decode->cc_dst = tcg_temp_new(); 1362 decode->cc_op = CC_OP_LOGICB + ot; 1363 tcg_gen_mov_tl(decode->cc_dst, s->T0); 1364 1365 /* 1366 * The manual says that the output is undefined when the 1367 * input is zero, but real hardware leaves it unchanged, and 1368 * real programs appear to depend on that. Accomplish this 1369 * by passing the output as the value to return upon zero. 1370 * Plus, return the bit index of the first 1 bit. 1371 */ 1372 tcg_gen_xori_tl(s->T1, s->T1, TARGET_LONG_BITS - 1); 1373 tcg_gen_clz_tl(s->T0, s->T0, s->T1); 1374 tcg_gen_xori_tl(s->T0, s->T0, TARGET_LONG_BITS - 1); 1375} 1376 1377static void gen_BSWAP(DisasContext *s, X86DecodedInsn *decode) 1378{ 1379#ifdef TARGET_X86_64 1380 if (s->dflag == MO_64) { 1381 tcg_gen_bswap64_i64(s->T0, s->T0); 1382 return; 1383 } 1384#endif 1385 tcg_gen_bswap32_tl(s->T0, s->T0, TCG_BSWAP_OZ); 1386} 1387 1388static void gen_BZHI(DisasContext *s, X86DecodedInsn *decode) 1389{ 1390 MemOp ot = decode->op[0].ot; 1391 TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); 1392 TCGv zero = tcg_constant_tl(0); 1393 TCGv mone = tcg_constant_tl(-1); 1394 1395 tcg_gen_ext8u_tl(s->T1, s->T1); 1396 1397 tcg_gen_shl_tl(s->A0, mone, s->T1); 1398 tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->T1, bound, s->A0, zero); 1399 tcg_gen_andc_tl(s->T0, s->T0, s->A0); 1400 /* 1401 * Note that since we're using BMILG (in order to get O 1402 * cleared) we need to store the inverse into C. 1403 */ 1404 tcg_gen_setcond_tl(TCG_COND_LEU, s->T1, s->T1, bound); 1405 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1406} 1407 1408static void gen_CALL(DisasContext *s, X86DecodedInsn *decode) 1409{ 1410 gen_push_v(s, eip_next_tl(s)); 1411 gen_JMP(s, decode); 1412} 1413 1414static void gen_CALL_m(DisasContext *s, X86DecodedInsn *decode) 1415{ 1416 gen_push_v(s, eip_next_tl(s)); 1417 gen_JMP_m(s, decode); 1418} 1419 1420static void gen_CALLF(DisasContext *s, X86DecodedInsn *decode) 1421{ 1422 gen_far_call(s); 1423} 1424 1425static void gen_CALLF_m(DisasContext *s, X86DecodedInsn *decode) 1426{ 1427 MemOp ot = decode->op[1].ot; 1428 1429 gen_op_ld_v(s, ot, s->T0, s->A0); 1430 gen_add_A0_im(s, 1 << ot); 1431 gen_op_ld_v(s, MO_16, s->T1, s->A0); 1432 gen_far_call(s); 1433} 1434 1435static void gen_CBW(DisasContext *s, X86DecodedInsn *decode) 1436{ 1437 MemOp src_ot = decode->op[0].ot - 1; 1438 1439 tcg_gen_ext_tl(s->T0, s->T0, src_ot | MO_SIGN); 1440} 1441 1442static void gen_CLC(DisasContext *s, X86DecodedInsn *decode) 1443{ 1444 gen_compute_eflags(s); 1445 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); 1446} 1447 1448static void gen_CLD(DisasContext *s, X86DecodedInsn *decode) 1449{ 1450 tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, offsetof(CPUX86State, df)); 1451} 1452 1453static void gen_CLI(DisasContext *s, X86DecodedInsn *decode) 1454{ 1455 gen_reset_eflags(s, IF_MASK); 1456} 1457 1458static void gen_CLTS(DisasContext *s, X86DecodedInsn *decode) 1459{ 1460 gen_helper_clts(tcg_env); 1461 /* abort block because static cpu state changed */ 1462 s->base.is_jmp = DISAS_EOB_NEXT; 1463} 1464 1465static void gen_CMC(DisasContext *s, X86DecodedInsn *decode) 1466{ 1467 gen_compute_eflags(s); 1468 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); 1469} 1470 1471static void gen_CMOVcc(DisasContext *s, X86DecodedInsn *decode) 1472{ 1473 gen_cmovcc1(s, decode->b & 0xf, s->T0, s->T1); 1474} 1475 1476static void gen_CMPccXADD(DisasContext *s, X86DecodedInsn *decode) 1477{ 1478 TCGLabel *label_top = gen_new_label(); 1479 TCGLabel *label_bottom = gen_new_label(); 1480 TCGv oldv = tcg_temp_new(); 1481 TCGv newv = tcg_temp_new(); 1482 TCGv cmpv = tcg_temp_new(); 1483 TCGCond cond; 1484 1485 TCGv cmp_lhs, cmp_rhs; 1486 MemOp ot, ot_full; 1487 1488 int jcc_op = (decode->b >> 1) & 7; 1489 static const TCGCond cond_table[8] = { 1490 [JCC_O] = TCG_COND_LT, /* test sign bit by comparing against 0 */ 1491 [JCC_B] = TCG_COND_LTU, 1492 [JCC_Z] = TCG_COND_EQ, 1493 [JCC_BE] = TCG_COND_LEU, 1494 [JCC_S] = TCG_COND_LT, /* test sign bit by comparing against 0 */ 1495 [JCC_P] = TCG_COND_TSTEQ, /* even parity - tests low bit of popcount */ 1496 [JCC_L] = TCG_COND_LT, 1497 [JCC_LE] = TCG_COND_LE, 1498 }; 1499 1500 cond = cond_table[jcc_op]; 1501 if (decode->b & 1) { 1502 cond = tcg_invert_cond(cond); 1503 } 1504 1505 ot = decode->op[0].ot; 1506 ot_full = ot | MO_LE; 1507 if (jcc_op >= JCC_S) { 1508 /* 1509 * Sign-extend values before subtracting for S, P (zero/sign extension 1510 * does not matter there) L, LE and their inverses. 1511 */ 1512 ot_full |= MO_SIGN; 1513 } 1514 1515 /* 1516 * cmpv will be moved to cc_src *after* cpu_regs[] is written back, so use 1517 * tcg_gen_ext_tl instead of gen_ext_tl. 1518 */ 1519 tcg_gen_ext_tl(cmpv, cpu_regs[decode->op[1].n], ot_full); 1520 1521 /* 1522 * Cmpxchg loop starts here. 1523 * - s->T1: addition operand (from decoder) 1524 * - s->A0: dest address (from decoder) 1525 * - s->cc_srcT: memory operand (lhs for comparison) 1526 * - cmpv: rhs for comparison 1527 */ 1528 gen_set_label(label_top); 1529 gen_op_ld_v(s, ot_full, s->cc_srcT, s->A0); 1530 tcg_gen_sub_tl(s->T0, s->cc_srcT, cmpv); 1531 1532 /* Compute the comparison result by hand, to avoid clobbering cc_*. */ 1533 switch (jcc_op) { 1534 case JCC_O: 1535 /* (src1 ^ src2) & (src1 ^ dst). newv is only used here for a moment */ 1536 tcg_gen_xor_tl(newv, s->cc_srcT, s->T0); 1537 tcg_gen_xor_tl(s->tmp0, s->cc_srcT, cmpv); 1538 tcg_gen_and_tl(s->tmp0, s->tmp0, newv); 1539 tcg_gen_sextract_tl(s->tmp0, s->tmp0, 0, 8 << ot); 1540 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(0); 1541 break; 1542 1543 case JCC_P: 1544 tcg_gen_ext8u_tl(s->tmp0, s->T0); 1545 tcg_gen_ctpop_tl(s->tmp0, s->tmp0); 1546 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(1); 1547 break; 1548 1549 case JCC_S: 1550 tcg_gen_sextract_tl(s->tmp0, s->T0, 0, 8 << ot); 1551 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(0); 1552 break; 1553 1554 default: 1555 cmp_lhs = s->cc_srcT, cmp_rhs = cmpv; 1556 break; 1557 } 1558 1559 /* Compute new value: if condition does not hold, just store back s->cc_srcT */ 1560 tcg_gen_add_tl(newv, s->cc_srcT, s->T1); 1561 tcg_gen_movcond_tl(cond, newv, cmp_lhs, cmp_rhs, newv, s->cc_srcT); 1562 tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, s->cc_srcT, newv, s->mem_index, ot_full); 1563 1564 /* Exit unconditionally if cmpxchg succeeded. */ 1565 tcg_gen_brcond_tl(TCG_COND_EQ, oldv, s->cc_srcT, label_bottom); 1566 1567 /* Try again if there was actually a store to make. */ 1568 tcg_gen_brcond_tl(cond, cmp_lhs, cmp_rhs, label_top); 1569 gen_set_label(label_bottom); 1570 1571 /* Store old value to registers only after a successful store. */ 1572 gen_writeback(s, decode, 1, s->cc_srcT); 1573 1574 decode->cc_dst = s->T0; 1575 decode->cc_src = cmpv; 1576 decode->cc_op = CC_OP_SUBB + ot; 1577} 1578 1579static void gen_CMPS(DisasContext *s, X86DecodedInsn *decode) 1580{ 1581 MemOp ot = decode->op[2].ot; 1582 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 1583 gen_repz_nz(s, ot, gen_cmps); 1584 } else { 1585 gen_cmps(s, ot); 1586 } 1587} 1588 1589static void gen_CMPXCHG(DisasContext *s, X86DecodedInsn *decode) 1590{ 1591 MemOp ot = decode->op[2].ot; 1592 TCGv cmpv = tcg_temp_new(); 1593 TCGv oldv = tcg_temp_new(); 1594 TCGv newv = tcg_temp_new(); 1595 TCGv dest; 1596 1597 tcg_gen_ext_tl(cmpv, cpu_regs[R_EAX], ot); 1598 tcg_gen_ext_tl(newv, s->T1, ot); 1599 if (s->prefix & PREFIX_LOCK) { 1600 tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, cmpv, newv, 1601 s->mem_index, ot | MO_LE); 1602 } else { 1603 tcg_gen_ext_tl(oldv, s->T0, ot); 1604 if (decode->op[0].has_ea) { 1605 /* 1606 * Perform an unconditional store cycle like physical cpu; 1607 * must be before changing accumulator to ensure 1608 * idempotency if the store faults and the instruction 1609 * is restarted 1610 */ 1611 tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, oldv); 1612 gen_op_st_v(s, ot, newv, s->A0); 1613 } else { 1614 /* 1615 * Unlike the memory case, where "the destination operand receives 1616 * a write cycle without regard to the result of the comparison", 1617 * rm must not be touched altogether if the write fails, including 1618 * not zero-extending it on 64-bit processors. So, precompute 1619 * the result of a successful writeback and perform the movcond 1620 * directly on cpu_regs. In case rm is part of RAX, note that this 1621 * movcond and the one below are mutually exclusive is executed. 1622 */ 1623 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, newv, newv); 1624 tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, newv, dest); 1625 } 1626 decode->op[0].unit = X86_OP_SKIP; 1627 } 1628 1629 /* Write RAX only if the cmpxchg fails. */ 1630 dest = gen_op_deposit_reg_v(s, ot, R_EAX, s->T0, oldv); 1631 tcg_gen_movcond_tl(TCG_COND_NE, dest, oldv, cmpv, s->T0, dest); 1632 1633 tcg_gen_mov_tl(s->cc_srcT, cmpv); 1634 tcg_gen_sub_tl(cmpv, cmpv, oldv); 1635 decode->cc_dst = cmpv; 1636 decode->cc_src = oldv; 1637 decode->cc_op = CC_OP_SUBB + ot; 1638} 1639 1640static void gen_CPUID(DisasContext *s, X86DecodedInsn *decode) 1641{ 1642 gen_update_cc_op(s); 1643 gen_update_eip_cur(s); 1644 gen_helper_cpuid(tcg_env); 1645} 1646 1647static void gen_CRC32(DisasContext *s, X86DecodedInsn *decode) 1648{ 1649 MemOp ot = decode->op[2].ot; 1650 1651 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 1652 gen_helper_crc32(s->T0, s->tmp2_i32, s->T1, tcg_constant_i32(8 << ot)); 1653} 1654 1655static void gen_CVTPI2Px(DisasContext *s, X86DecodedInsn *decode) 1656{ 1657 gen_helper_enter_mmx(tcg_env); 1658 if (s->prefix & PREFIX_DATA) { 1659 gen_helper_cvtpi2pd(tcg_env, OP_PTR0, OP_PTR2); 1660 } else { 1661 gen_helper_cvtpi2ps(tcg_env, OP_PTR0, OP_PTR2); 1662 } 1663} 1664 1665static void gen_CVTPx2PI(DisasContext *s, X86DecodedInsn *decode) 1666{ 1667 gen_helper_enter_mmx(tcg_env); 1668 if (s->prefix & PREFIX_DATA) { 1669 gen_helper_cvtpd2pi(tcg_env, OP_PTR0, OP_PTR2); 1670 } else { 1671 gen_helper_cvtps2pi(tcg_env, OP_PTR0, OP_PTR2); 1672 } 1673} 1674 1675static void gen_CVTTPx2PI(DisasContext *s, X86DecodedInsn *decode) 1676{ 1677 gen_helper_enter_mmx(tcg_env); 1678 if (s->prefix & PREFIX_DATA) { 1679 gen_helper_cvttpd2pi(tcg_env, OP_PTR0, OP_PTR2); 1680 } else { 1681 gen_helper_cvttps2pi(tcg_env, OP_PTR0, OP_PTR2); 1682 } 1683} 1684 1685static void gen_CWD(DisasContext *s, X86DecodedInsn *decode) 1686{ 1687 int shift = 8 << decode->op[0].ot; 1688 1689 tcg_gen_sextract_tl(s->T0, s->T0, shift - 1, 1); 1690} 1691 1692static void gen_DAA(DisasContext *s, X86DecodedInsn *decode) 1693{ 1694 gen_update_cc_op(s); 1695 gen_helper_daa(tcg_env); 1696 assume_cc_op(s, CC_OP_EFLAGS); 1697} 1698 1699static void gen_DAS(DisasContext *s, X86DecodedInsn *decode) 1700{ 1701 gen_update_cc_op(s); 1702 gen_helper_das(tcg_env); 1703 assume_cc_op(s, CC_OP_EFLAGS); 1704} 1705 1706static void gen_DEC(DisasContext *s, X86DecodedInsn *decode) 1707{ 1708 MemOp ot = decode->op[1].ot; 1709 1710 tcg_gen_movi_tl(s->T1, -1); 1711 if (s->prefix & PREFIX_LOCK) { 1712 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 1713 s->mem_index, ot | MO_LE); 1714 } else { 1715 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1716 } 1717 prepare_update_cc_incdec(decode, s, CC_OP_DECB + ot); 1718} 1719 1720static void gen_DIV(DisasContext *s, X86DecodedInsn *decode) 1721{ 1722 MemOp ot = decode->op[1].ot; 1723 1724 switch(ot) { 1725 case MO_8: 1726 gen_helper_divb_AL(tcg_env, s->T0); 1727 break; 1728 case MO_16: 1729 gen_helper_divw_AX(tcg_env, s->T0); 1730 break; 1731 default: 1732 case MO_32: 1733 gen_helper_divl_EAX(tcg_env, s->T0); 1734 break; 1735#ifdef TARGET_X86_64 1736 case MO_64: 1737 gen_helper_divq_EAX(tcg_env, s->T0); 1738 break; 1739#endif 1740 } 1741} 1742 1743static void gen_EMMS(DisasContext *s, X86DecodedInsn *decode) 1744{ 1745 gen_helper_emms(tcg_env); 1746} 1747 1748static void gen_ENTER(DisasContext *s, X86DecodedInsn *decode) 1749{ 1750 gen_enter(s, decode->op[1].imm, decode->op[2].imm); 1751} 1752 1753static void gen_EXTRQ_i(DisasContext *s, X86DecodedInsn *decode) 1754{ 1755 TCGv_i32 length = tcg_constant_i32(decode->immediate & 63); 1756 TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63); 1757 1758 gen_helper_extrq_i(tcg_env, OP_PTR0, index, length); 1759} 1760 1761static void gen_EXTRQ_r(DisasContext *s, X86DecodedInsn *decode) 1762{ 1763 gen_helper_extrq_r(tcg_env, OP_PTR0, OP_PTR2); 1764} 1765 1766static void gen_FXRSTOR(DisasContext *s, X86DecodedInsn *decode) 1767{ 1768 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { 1769 gen_NM_exception(s); 1770 } else { 1771 gen_helper_fxrstor(tcg_env, s->A0); 1772 } 1773} 1774 1775static void gen_FXSAVE(DisasContext *s, X86DecodedInsn *decode) 1776{ 1777 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { 1778 gen_NM_exception(s); 1779 } else { 1780 gen_helper_fxsave(tcg_env, s->A0); 1781 } 1782} 1783 1784static void gen_HLT(DisasContext *s, X86DecodedInsn *decode) 1785{ 1786#ifdef CONFIG_SYSTEM_ONLY 1787 gen_update_cc_op(s); 1788 gen_update_eip_next(s); 1789 gen_helper_hlt(tcg_env); 1790 s->base.is_jmp = DISAS_NORETURN; 1791#endif 1792} 1793 1794static void gen_IDIV(DisasContext *s, X86DecodedInsn *decode) 1795{ 1796 MemOp ot = decode->op[1].ot; 1797 1798 switch(ot) { 1799 case MO_8: 1800 gen_helper_idivb_AL(tcg_env, s->T0); 1801 break; 1802 case MO_16: 1803 gen_helper_idivw_AX(tcg_env, s->T0); 1804 break; 1805 default: 1806 case MO_32: 1807 gen_helper_idivl_EAX(tcg_env, s->T0); 1808 break; 1809#ifdef TARGET_X86_64 1810 case MO_64: 1811 gen_helper_idivq_EAX(tcg_env, s->T0); 1812 break; 1813#endif 1814 } 1815} 1816 1817static void gen_IMUL3(DisasContext *s, X86DecodedInsn *decode) 1818{ 1819 MemOp ot = decode->op[0].ot; 1820 TCGv cc_src_rhs; 1821 1822 switch (ot) { 1823 case MO_16: 1824 /* s->T0 already sign-extended */ 1825 tcg_gen_ext16s_tl(s->T1, s->T1); 1826 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 1827 /* Compare the full result to the extension of the truncated result. */ 1828 tcg_gen_ext16s_tl(s->T1, s->T0); 1829 cc_src_rhs = s->T0; 1830 break; 1831 1832 case MO_32: 1833#ifdef TARGET_X86_64 1834 if (TCG_TARGET_REG_BITS == 64) { 1835 /* 1836 * This produces fewer TCG ops, and better code if flags are needed, 1837 * but it requires a 64-bit multiply even if they are not. Use it 1838 * only if the target has 64-bits registers. 1839 * 1840 * s->T0 is already sign-extended. 1841 */ 1842 tcg_gen_ext32s_tl(s->T1, s->T1); 1843 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 1844 /* Compare the full result to the extension of the truncated result. */ 1845 tcg_gen_ext32s_tl(s->T1, s->T0); 1846 cc_src_rhs = s->T0; 1847 } else { 1848 /* Variant that only needs a 32-bit widening multiply. */ 1849 TCGv_i32 hi = tcg_temp_new_i32(); 1850 TCGv_i32 lo = tcg_temp_new_i32(); 1851 tcg_gen_trunc_tl_i32(lo, s->T0); 1852 tcg_gen_trunc_tl_i32(hi, s->T1); 1853 tcg_gen_muls2_i32(lo, hi, lo, hi); 1854 tcg_gen_extu_i32_tl(s->T0, lo); 1855 1856 cc_src_rhs = tcg_temp_new(); 1857 tcg_gen_extu_i32_tl(cc_src_rhs, hi); 1858 /* Compare the high part to the sign bit of the truncated result */ 1859 tcg_gen_sari_i32(lo, lo, 31); 1860 tcg_gen_extu_i32_tl(s->T1, lo); 1861 } 1862 break; 1863 1864 case MO_64: 1865#endif 1866 cc_src_rhs = tcg_temp_new(); 1867 tcg_gen_muls2_tl(s->T0, cc_src_rhs, s->T0, s->T1); 1868 /* Compare the high part to the sign bit of the truncated result */ 1869 tcg_gen_sari_tl(s->T1, s->T0, TARGET_LONG_BITS - 1); 1870 break; 1871 1872 default: 1873 g_assert_not_reached(); 1874 } 1875 1876 tcg_gen_sub_tl(s->T1, s->T1, cc_src_rhs); 1877 prepare_update2_cc(decode, s, CC_OP_MULB + ot); 1878} 1879 1880static void gen_IMUL(DisasContext *s, X86DecodedInsn *decode) 1881{ 1882 MemOp ot = decode->op[1].ot; 1883 TCGv cc_src_rhs; 1884 1885 switch (ot) { 1886 case MO_8: 1887 /* s->T0 already sign-extended */ 1888 tcg_gen_ext8s_tl(s->T1, s->T1); 1889 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 1890 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 1891 /* Compare the full result to the extension of the truncated result. */ 1892 tcg_gen_ext8s_tl(s->T1, s->T0); 1893 cc_src_rhs = s->T0; 1894 break; 1895 1896 case MO_16: 1897 /* s->T0 already sign-extended */ 1898 tcg_gen_ext16s_tl(s->T1, s->T1); 1899 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 1900 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 1901 tcg_gen_shri_tl(s->T1, s->T0, 16); 1902 gen_op_mov_reg_v(s, MO_16, R_EDX, s->T1); 1903 /* Compare the full result to the extension of the truncated result. */ 1904 tcg_gen_ext16s_tl(s->T1, s->T0); 1905 cc_src_rhs = s->T0; 1906 break; 1907 1908 case MO_32: 1909#ifdef TARGET_X86_64 1910 /* s->T0 already sign-extended */ 1911 tcg_gen_ext32s_tl(s->T1, s->T1); 1912 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 1913 tcg_gen_ext32u_tl(cpu_regs[R_EAX], s->T0); 1914 tcg_gen_shri_tl(cpu_regs[R_EDX], s->T0, 32); 1915 /* Compare the full result to the extension of the truncated result. */ 1916 tcg_gen_ext32s_tl(s->T1, s->T0); 1917 cc_src_rhs = s->T0; 1918 break; 1919 1920 case MO_64: 1921#endif 1922 tcg_gen_muls2_tl(s->T0, cpu_regs[R_EDX], s->T0, s->T1); 1923 tcg_gen_mov_tl(cpu_regs[R_EAX], s->T0); 1924 1925 /* Compare the high part to the sign bit of the truncated result */ 1926 tcg_gen_negsetcondi_tl(TCG_COND_LT, s->T1, s->T0, 0); 1927 cc_src_rhs = cpu_regs[R_EDX]; 1928 break; 1929 1930 default: 1931 g_assert_not_reached(); 1932 } 1933 1934 tcg_gen_sub_tl(s->T1, s->T1, cc_src_rhs); 1935 prepare_update2_cc(decode, s, CC_OP_MULB + ot); 1936} 1937 1938static void gen_IN(DisasContext *s, X86DecodedInsn *decode) 1939{ 1940 MemOp ot = decode->op[0].ot; 1941 TCGv_i32 port = tcg_temp_new_i32(); 1942 1943 tcg_gen_trunc_tl_i32(port, s->T0); 1944 tcg_gen_ext16u_i32(port, port); 1945 if (!gen_check_io(s, ot, port, SVM_IOIO_TYPE_MASK)) { 1946 return; 1947 } 1948 translator_io_start(&s->base); 1949 gen_helper_in_func(ot, s->T0, port); 1950 gen_writeback(s, decode, 0, s->T0); 1951 gen_bpt_io(s, port, ot); 1952} 1953 1954static void gen_INC(DisasContext *s, X86DecodedInsn *decode) 1955{ 1956 MemOp ot = decode->op[1].ot; 1957 1958 tcg_gen_movi_tl(s->T1, 1); 1959 if (s->prefix & PREFIX_LOCK) { 1960 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 1961 s->mem_index, ot | MO_LE); 1962 } else { 1963 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1964 } 1965 prepare_update_cc_incdec(decode, s, CC_OP_INCB + ot); 1966} 1967 1968static void gen_INS(DisasContext *s, X86DecodedInsn *decode) 1969{ 1970 MemOp ot = decode->op[1].ot; 1971 TCGv_i32 port = tcg_temp_new_i32(); 1972 1973 tcg_gen_trunc_tl_i32(port, s->T1); 1974 tcg_gen_ext16u_i32(port, port); 1975 if (!gen_check_io(s, ot, port, 1976 SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { 1977 return; 1978 } 1979 1980 translator_io_start(&s->base); 1981 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 1982 gen_repz(s, ot, gen_ins); 1983 } else { 1984 gen_ins(s, ot); 1985 } 1986} 1987 1988static void gen_INSERTQ_i(DisasContext *s, X86DecodedInsn *decode) 1989{ 1990 TCGv_i32 length = tcg_constant_i32(decode->immediate & 63); 1991 TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63); 1992 1993 gen_helper_insertq_i(tcg_env, OP_PTR0, OP_PTR1, index, length); 1994} 1995 1996static void gen_INSERTQ_r(DisasContext *s, X86DecodedInsn *decode) 1997{ 1998 gen_helper_insertq_r(tcg_env, OP_PTR0, OP_PTR2); 1999} 2000 2001static void gen_INT(DisasContext *s, X86DecodedInsn *decode) 2002{ 2003 gen_interrupt(s, decode->immediate); 2004} 2005 2006static void gen_INT1(DisasContext *s, X86DecodedInsn *decode) 2007{ 2008 gen_update_cc_op(s); 2009 gen_update_eip_next(s); 2010 gen_helper_icebp(tcg_env); 2011 s->base.is_jmp = DISAS_NORETURN; 2012} 2013 2014static void gen_INT3(DisasContext *s, X86DecodedInsn *decode) 2015{ 2016 gen_interrupt(s, EXCP03_INT3); 2017} 2018 2019static void gen_INTO(DisasContext *s, X86DecodedInsn *decode) 2020{ 2021 gen_update_cc_op(s); 2022 gen_update_eip_cur(s); 2023 gen_helper_into(tcg_env, cur_insn_len_i32(s)); 2024} 2025 2026static void gen_IRET(DisasContext *s, X86DecodedInsn *decode) 2027{ 2028 if (!PE(s) || VM86(s)) { 2029 gen_helper_iret_real(tcg_env, tcg_constant_i32(s->dflag - 1)); 2030 } else { 2031 gen_helper_iret_protected(tcg_env, tcg_constant_i32(s->dflag - 1), 2032 eip_next_i32(s)); 2033 } 2034 assume_cc_op(s, CC_OP_EFLAGS); 2035 s->base.is_jmp = DISAS_EOB_ONLY; 2036} 2037 2038static void gen_Jcc(DisasContext *s, X86DecodedInsn *decode) 2039{ 2040 gen_bnd_jmp(s); 2041 gen_jcc(s, decode->b & 0xf, decode->immediate); 2042} 2043 2044static void gen_JCXZ(DisasContext *s, X86DecodedInsn *decode) 2045{ 2046 TCGLabel *taken = gen_new_label(); 2047 2048 gen_update_cc_op(s); 2049 gen_op_jz_ecx(s, taken); 2050 gen_conditional_jump_labels(s, decode->immediate, NULL, taken); 2051} 2052 2053static void gen_JMP(DisasContext *s, X86DecodedInsn *decode) 2054{ 2055 gen_update_cc_op(s); 2056 gen_jmp_rel(s, s->dflag, decode->immediate, 0); 2057} 2058 2059static void gen_JMP_m(DisasContext *s, X86DecodedInsn *decode) 2060{ 2061 gen_op_jmp_v(s, s->T0); 2062 gen_bnd_jmp(s); 2063 s->base.is_jmp = DISAS_JUMP; 2064} 2065 2066static void gen_JMPF(DisasContext *s, X86DecodedInsn *decode) 2067{ 2068 gen_far_jmp(s); 2069} 2070 2071static void gen_JMPF_m(DisasContext *s, X86DecodedInsn *decode) 2072{ 2073 MemOp ot = decode->op[1].ot; 2074 2075 gen_op_ld_v(s, ot, s->T0, s->A0); 2076 gen_add_A0_im(s, 1 << ot); 2077 gen_op_ld_v(s, MO_16, s->T1, s->A0); 2078 gen_far_jmp(s); 2079} 2080 2081static void gen_LAHF(DisasContext *s, X86DecodedInsn *decode) 2082{ 2083 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) { 2084 return gen_illegal_opcode(s); 2085 } 2086 gen_compute_eflags(s); 2087 /* Note: gen_compute_eflags() only gives the condition codes */ 2088 tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02); 2089 tcg_gen_deposit_tl(cpu_regs[R_EAX], cpu_regs[R_EAX], s->T0, 8, 8); 2090} 2091 2092static void gen_LAR(DisasContext *s, X86DecodedInsn *decode) 2093{ 2094 MemOp ot = decode->op[0].ot; 2095 TCGv result = tcg_temp_new(); 2096 TCGv dest; 2097 2098 gen_compute_eflags(s); 2099 gen_update_cc_op(s); 2100 gen_helper_lar(result, tcg_env, s->T0); 2101 2102 /* Perform writeback here to skip it if ZF=0. */ 2103 decode->op[0].unit = X86_OP_SKIP; 2104 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, result, result); 2105 tcg_gen_movcond_tl(TCG_COND_TSTNE, dest, cpu_cc_src, tcg_constant_tl(CC_Z), 2106 result, dest); 2107} 2108 2109static void gen_LDMXCSR(DisasContext *s, X86DecodedInsn *decode) 2110{ 2111 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 2112 gen_helper_ldmxcsr(tcg_env, s->tmp2_i32); 2113} 2114 2115static void gen_lxx_seg(DisasContext *s, X86DecodedInsn *decode, int seg) 2116{ 2117 MemOp ot = decode->op[0].ot; 2118 2119 /* Offset already in s->T0. */ 2120 gen_add_A0_im(s, 1 << ot); 2121 gen_op_ld_v(s, MO_16, s->T1, s->A0); 2122 2123 /* load the segment here to handle exceptions properly */ 2124 gen_movl_seg(s, seg, s->T1); 2125} 2126 2127static void gen_LDS(DisasContext *s, X86DecodedInsn *decode) 2128{ 2129 gen_lxx_seg(s, decode, R_DS); 2130} 2131 2132static void gen_LEA(DisasContext *s, X86DecodedInsn *decode) 2133{ 2134 TCGv ea = gen_lea_modrm_1(s, decode->mem, false); 2135 gen_lea_v_seg_dest(s, s->aflag, s->T0, ea, -1, -1); 2136} 2137 2138static void gen_LEAVE(DisasContext *s, X86DecodedInsn *decode) 2139{ 2140 gen_leave(s); 2141} 2142 2143static void gen_LES(DisasContext *s, X86DecodedInsn *decode) 2144{ 2145 gen_lxx_seg(s, decode, R_ES); 2146} 2147 2148static void gen_LFENCE(DisasContext *s, X86DecodedInsn *decode) 2149{ 2150 tcg_gen_mb(TCG_MO_LD_LD | TCG_BAR_SC); 2151} 2152 2153static void gen_LFS(DisasContext *s, X86DecodedInsn *decode) 2154{ 2155 gen_lxx_seg(s, decode, R_FS); 2156} 2157 2158static void gen_LGS(DisasContext *s, X86DecodedInsn *decode) 2159{ 2160 gen_lxx_seg(s, decode, R_GS); 2161} 2162 2163static void gen_LODS(DisasContext *s, X86DecodedInsn *decode) 2164{ 2165 MemOp ot = decode->op[1].ot; 2166 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2167 gen_repz(s, ot, gen_lods); 2168 } else { 2169 gen_lods(s, ot); 2170 } 2171} 2172 2173static void gen_LOOP(DisasContext *s, X86DecodedInsn *decode) 2174{ 2175 TCGLabel *taken = gen_new_label(); 2176 2177 gen_update_cc_op(s); 2178 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2179 gen_op_jnz_ecx(s, taken); 2180 gen_conditional_jump_labels(s, decode->immediate, NULL, taken); 2181} 2182 2183static void gen_LOOPE(DisasContext *s, X86DecodedInsn *decode) 2184{ 2185 TCGLabel *taken = gen_new_label(); 2186 TCGLabel *not_taken = gen_new_label(); 2187 2188 gen_update_cc_op(s); 2189 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2190 gen_op_jz_ecx(s, not_taken); 2191 gen_jcc1(s, (JCC_Z << 1), taken); /* jz taken */ 2192 gen_conditional_jump_labels(s, decode->immediate, not_taken, taken); 2193} 2194 2195static void gen_LOOPNE(DisasContext *s, X86DecodedInsn *decode) 2196{ 2197 TCGLabel *taken = gen_new_label(); 2198 TCGLabel *not_taken = gen_new_label(); 2199 2200 gen_update_cc_op(s); 2201 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2202 gen_op_jz_ecx(s, not_taken); 2203 gen_jcc1(s, (JCC_Z << 1) | 1, taken); /* jnz taken */ 2204 gen_conditional_jump_labels(s, decode->immediate, not_taken, taken); 2205} 2206 2207static void gen_LSL(DisasContext *s, X86DecodedInsn *decode) 2208{ 2209 MemOp ot = decode->op[0].ot; 2210 TCGv result = tcg_temp_new(); 2211 TCGv dest; 2212 2213 gen_compute_eflags(s); 2214 gen_update_cc_op(s); 2215 gen_helper_lsl(result, tcg_env, s->T0); 2216 2217 /* Perform writeback here to skip it if ZF=0. */ 2218 decode->op[0].unit = X86_OP_SKIP; 2219 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, result, result); 2220 tcg_gen_movcond_tl(TCG_COND_TSTNE, dest, cpu_cc_src, tcg_constant_tl(CC_Z), 2221 result, dest); 2222} 2223 2224static void gen_LSS(DisasContext *s, X86DecodedInsn *decode) 2225{ 2226 gen_lxx_seg(s, decode, R_SS); 2227} 2228 2229static void gen_LZCNT(DisasContext *s, X86DecodedInsn *decode) 2230{ 2231 MemOp ot = decode->op[0].ot; 2232 2233 /* C bit (cc_src) is defined related to the input. */ 2234 decode->cc_src = tcg_temp_new(); 2235 decode->cc_dst = s->T0; 2236 decode->cc_op = CC_OP_BMILGB + ot; 2237 tcg_gen_mov_tl(decode->cc_src, s->T0); 2238 2239 /* 2240 * Reduce the target_ulong result by the number of zeros that 2241 * we expect to find at the top. 2242 */ 2243 tcg_gen_clzi_tl(s->T0, s->T0, TARGET_LONG_BITS); 2244 tcg_gen_subi_tl(s->T0, s->T0, TARGET_LONG_BITS - (8 << ot)); 2245} 2246 2247static void gen_MFENCE(DisasContext *s, X86DecodedInsn *decode) 2248{ 2249 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 2250} 2251 2252static void gen_MOV(DisasContext *s, X86DecodedInsn *decode) 2253{ 2254 /* nothing to do! */ 2255} 2256#define gen_NOP gen_MOV 2257 2258static void gen_MASKMOV(DisasContext *s, X86DecodedInsn *decode) 2259{ 2260 gen_lea_v_seg(s, cpu_regs[R_EDI], R_DS, s->override); 2261 2262 if (s->prefix & PREFIX_DATA) { 2263 gen_helper_maskmov_xmm(tcg_env, OP_PTR1, OP_PTR2, s->A0); 2264 } else { 2265 gen_helper_maskmov_mmx(tcg_env, OP_PTR1, OP_PTR2, s->A0); 2266 } 2267} 2268 2269static void gen_MOVBE(DisasContext *s, X86DecodedInsn *decode) 2270{ 2271 MemOp ot = decode->op[0].ot; 2272 2273 /* M operand type does not load/store */ 2274 if (decode->e.op0 == X86_TYPE_M) { 2275 tcg_gen_qemu_st_tl(s->T0, s->A0, s->mem_index, ot | MO_BE); 2276 } else { 2277 tcg_gen_qemu_ld_tl(s->T0, s->A0, s->mem_index, ot | MO_BE); 2278 } 2279} 2280 2281static void gen_MOVD_from(DisasContext *s, X86DecodedInsn *decode) 2282{ 2283 MemOp ot = decode->op[2].ot; 2284 2285 switch (ot) { 2286 case MO_32: 2287#ifdef TARGET_X86_64 2288 tcg_gen_ld32u_tl(s->T0, tcg_env, decode->op[2].offset); 2289 break; 2290 case MO_64: 2291#endif 2292 tcg_gen_ld_tl(s->T0, tcg_env, decode->op[2].offset); 2293 break; 2294 default: 2295 abort(); 2296 } 2297} 2298 2299static void gen_MOVD_to(DisasContext *s, X86DecodedInsn *decode) 2300{ 2301 MemOp ot = decode->op[2].ot; 2302 int vec_len = vector_len(s, decode); 2303 int lo_ofs = vector_elem_offset(&decode->op[0], ot, 0); 2304 2305 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2306 2307 switch (ot) { 2308 case MO_32: 2309#ifdef TARGET_X86_64 2310 tcg_gen_st32_tl(s->T1, tcg_env, lo_ofs); 2311 break; 2312 case MO_64: 2313#endif 2314 tcg_gen_st_tl(s->T1, tcg_env, lo_ofs); 2315 break; 2316 default: 2317 g_assert_not_reached(); 2318 } 2319} 2320 2321static void gen_MOVDQ(DisasContext *s, X86DecodedInsn *decode) 2322{ 2323 gen_store_sse(s, decode, decode->op[2].offset); 2324} 2325 2326static void gen_MOVMSK(DisasContext *s, X86DecodedInsn *decode) 2327{ 2328 typeof(gen_helper_movmskps_ymm) *ps, *pd, *fn; 2329 ps = s->vex_l ? gen_helper_movmskps_ymm : gen_helper_movmskps_xmm; 2330 pd = s->vex_l ? gen_helper_movmskpd_ymm : gen_helper_movmskpd_xmm; 2331 fn = s->prefix & PREFIX_DATA ? pd : ps; 2332 fn(s->tmp2_i32, tcg_env, OP_PTR2); 2333 tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); 2334} 2335 2336static void gen_MOVQ(DisasContext *s, X86DecodedInsn *decode) 2337{ 2338 int vec_len = vector_len(s, decode); 2339 int lo_ofs = vector_elem_offset(&decode->op[0], MO_64, 0); 2340 2341 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset); 2342 if (decode->op[0].has_ea) { 2343 tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 2344 } else { 2345 /* 2346 * tcg_gen_gvec_dup_i64(MO_64, op0.offset, 8, vec_len, s->tmp1_64) would 2347 * seem to work, but it does not on big-endian platforms; the cleared parts 2348 * are always at higher addresses, but cross-endian emulation inverts the 2349 * byte order so that the cleared parts need to be at *lower* addresses. 2350 * Because oprsz is 8, we see this here even for SSE; but more in general, 2351 * it disqualifies using oprsz < maxsz to emulate VEX128. 2352 */ 2353 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2354 tcg_gen_st_i64(s->tmp1_i64, tcg_env, lo_ofs); 2355 } 2356} 2357 2358static void gen_MOVq_dq(DisasContext *s, X86DecodedInsn *decode) 2359{ 2360 gen_helper_enter_mmx(tcg_env); 2361 /* Otherwise the same as any other movq. */ 2362 return gen_MOVQ(s, decode); 2363} 2364 2365static void gen_MOVS(DisasContext *s, X86DecodedInsn *decode) 2366{ 2367 MemOp ot = decode->op[2].ot; 2368 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2369 gen_repz(s, ot, gen_movs); 2370 } else { 2371 gen_movs(s, ot); 2372 } 2373} 2374 2375static void gen_MUL(DisasContext *s, X86DecodedInsn *decode) 2376{ 2377 MemOp ot = decode->op[1].ot; 2378 2379 switch (ot) { 2380 case MO_8: 2381 /* s->T0 already zero-extended */ 2382 tcg_gen_ext8u_tl(s->T1, s->T1); 2383 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2384 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2385 tcg_gen_andi_tl(s->T1, s->T0, 0xff00); 2386 decode->cc_dst = s->T0; 2387 decode->cc_src = s->T1; 2388 break; 2389 2390 case MO_16: 2391 /* s->T0 already zero-extended */ 2392 tcg_gen_ext16u_tl(s->T1, s->T1); 2393 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2394 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2395 tcg_gen_shri_tl(s->T1, s->T0, 16); 2396 gen_op_mov_reg_v(s, MO_16, R_EDX, s->T1); 2397 decode->cc_dst = s->T0; 2398 decode->cc_src = s->T1; 2399 break; 2400 2401 case MO_32: 2402#ifdef TARGET_X86_64 2403 /* s->T0 already zero-extended */ 2404 tcg_gen_ext32u_tl(s->T1, s->T1); 2405 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2406 tcg_gen_ext32u_tl(cpu_regs[R_EAX], s->T0); 2407 tcg_gen_shri_tl(cpu_regs[R_EDX], s->T0, 32); 2408 decode->cc_dst = cpu_regs[R_EAX]; 2409 decode->cc_src = cpu_regs[R_EDX]; 2410 break; 2411 2412 case MO_64: 2413#endif 2414 tcg_gen_mulu2_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->T0, s->T1); 2415 decode->cc_dst = cpu_regs[R_EAX]; 2416 decode->cc_src = cpu_regs[R_EDX]; 2417 break; 2418 2419 default: 2420 g_assert_not_reached(); 2421 } 2422 2423 decode->cc_op = CC_OP_MULB + ot; 2424} 2425 2426static void gen_MULX(DisasContext *s, X86DecodedInsn *decode) 2427{ 2428 MemOp ot = decode->op[0].ot; 2429 2430 /* low part of result in VEX.vvvv, high in MODRM */ 2431 switch (ot) { 2432 case MO_32: 2433#ifdef TARGET_X86_64 2434 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 2435 tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); 2436 tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32, 2437 s->tmp2_i32, s->tmp3_i32); 2438 tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], s->tmp2_i32); 2439 tcg_gen_extu_i32_tl(s->T0, s->tmp3_i32); 2440 break; 2441 2442 case MO_64: 2443#endif 2444 tcg_gen_mulu2_tl(cpu_regs[s->vex_v], s->T0, s->T0, s->T1); 2445 break; 2446 2447 default: 2448 g_assert_not_reached(); 2449 } 2450} 2451 2452static void gen_NEG(DisasContext *s, X86DecodedInsn *decode) 2453{ 2454 MemOp ot = decode->op[0].ot; 2455 TCGv oldv = tcg_temp_new(); 2456 2457 if (s->prefix & PREFIX_LOCK) { 2458 TCGv newv = tcg_temp_new(); 2459 TCGv cmpv = tcg_temp_new(); 2460 TCGLabel *label1 = gen_new_label(); 2461 2462 gen_set_label(label1); 2463 gen_op_ld_v(s, ot, oldv, s->A0); 2464 tcg_gen_neg_tl(newv, oldv); 2465 tcg_gen_atomic_cmpxchg_tl(cmpv, s->A0, oldv, newv, 2466 s->mem_index, ot | MO_LE); 2467 tcg_gen_brcond_tl(TCG_COND_NE, oldv, cmpv, label1); 2468 } else { 2469 tcg_gen_mov_tl(oldv, s->T0); 2470 } 2471 tcg_gen_neg_tl(s->T0, oldv); 2472 2473 decode->cc_dst = s->T0; 2474 decode->cc_src = oldv; 2475 tcg_gen_movi_tl(s->cc_srcT, 0); 2476 decode->cc_op = CC_OP_SUBB + ot; 2477} 2478 2479static void gen_NOT(DisasContext *s, X86DecodedInsn *decode) 2480{ 2481 MemOp ot = decode->op[0].ot; 2482 2483 if (s->prefix & PREFIX_LOCK) { 2484 tcg_gen_movi_tl(s->T0, ~0); 2485 tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T0, 2486 s->mem_index, ot | MO_LE); 2487 } else { 2488 tcg_gen_not_tl(s->T0, s->T0); 2489 } 2490} 2491 2492static void gen_OR(DisasContext *s, X86DecodedInsn *decode) 2493{ 2494 MemOp ot = decode->op[1].ot; 2495 2496 if (s->prefix & PREFIX_LOCK) { 2497 tcg_gen_atomic_or_fetch_tl(s->T0, s->A0, s->T1, 2498 s->mem_index, ot | MO_LE); 2499 } else { 2500 tcg_gen_or_tl(s->T0, s->T0, s->T1); 2501 } 2502 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 2503} 2504 2505static void gen_OUT(DisasContext *s, X86DecodedInsn *decode) 2506{ 2507 MemOp ot = decode->op[1].ot; 2508 TCGv_i32 port = tcg_temp_new_i32(); 2509 TCGv_i32 value = tcg_temp_new_i32(); 2510 2511 tcg_gen_trunc_tl_i32(port, s->T1); 2512 tcg_gen_ext16u_i32(port, port); 2513 if (!gen_check_io(s, ot, port, 0)) { 2514 return; 2515 } 2516 tcg_gen_trunc_tl_i32(value, s->T0); 2517 translator_io_start(&s->base); 2518 gen_helper_out_func(ot, port, value); 2519 gen_bpt_io(s, port, ot); 2520} 2521 2522static void gen_OUTS(DisasContext *s, X86DecodedInsn *decode) 2523{ 2524 MemOp ot = decode->op[1].ot; 2525 TCGv_i32 port = tcg_temp_new_i32(); 2526 2527 tcg_gen_trunc_tl_i32(port, s->T1); 2528 tcg_gen_ext16u_i32(port, port); 2529 if (!gen_check_io(s, ot, port, SVM_IOIO_STR_MASK)) { 2530 return; 2531 } 2532 2533 translator_io_start(&s->base); 2534 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2535 gen_repz(s, ot, gen_outs); 2536 } else { 2537 gen_outs(s, ot); 2538 } 2539} 2540 2541static void gen_PALIGNR(DisasContext *s, X86DecodedInsn *decode) 2542{ 2543 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2544 if (!(s->prefix & PREFIX_DATA)) { 2545 gen_helper_palignr_mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2546 } else if (!s->vex_l) { 2547 gen_helper_palignr_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2548 } else { 2549 gen_helper_palignr_ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2550 } 2551} 2552 2553static void gen_PANDN(DisasContext *s, X86DecodedInsn *decode) 2554{ 2555 int vec_len = vector_len(s, decode); 2556 2557 /* Careful, operand order is reversed! */ 2558 tcg_gen_gvec_andc(MO_64, 2559 decode->op[0].offset, decode->op[2].offset, 2560 decode->op[1].offset, vec_len, vec_len); 2561} 2562 2563static void gen_PAUSE(DisasContext *s, X86DecodedInsn *decode) 2564{ 2565 gen_update_cc_op(s); 2566 gen_update_eip_next(s); 2567 gen_helper_pause(tcg_env); 2568 s->base.is_jmp = DISAS_NORETURN; 2569} 2570 2571static void gen_PCMPESTRI(DisasContext *s, X86DecodedInsn *decode) 2572{ 2573 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2574 gen_helper_pcmpestri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2575 assume_cc_op(s, CC_OP_EFLAGS); 2576} 2577 2578static void gen_PCMPESTRM(DisasContext *s, X86DecodedInsn *decode) 2579{ 2580 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2581 gen_helper_pcmpestrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2582 assume_cc_op(s, CC_OP_EFLAGS); 2583 if ((s->prefix & PREFIX_VEX) && !s->vex_l) { 2584 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)), 2585 16, 16, 0); 2586 } 2587} 2588 2589static void gen_PCMPISTRI(DisasContext *s, X86DecodedInsn *decode) 2590{ 2591 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2592 gen_helper_pcmpistri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2593 assume_cc_op(s, CC_OP_EFLAGS); 2594} 2595 2596static void gen_PCMPISTRM(DisasContext *s, X86DecodedInsn *decode) 2597{ 2598 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2599 gen_helper_pcmpistrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2600 assume_cc_op(s, CC_OP_EFLAGS); 2601 if ((s->prefix & PREFIX_VEX) && !s->vex_l) { 2602 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)), 2603 16, 16, 0); 2604 } 2605} 2606 2607static void gen_PDEP(DisasContext *s, X86DecodedInsn *decode) 2608{ 2609 gen_helper_pdep(s->T0, s->T0, s->T1); 2610} 2611 2612static void gen_PEXT(DisasContext *s, X86DecodedInsn *decode) 2613{ 2614 gen_helper_pext(s->T0, s->T0, s->T1); 2615} 2616 2617static inline void gen_pextr(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 2618{ 2619 int vec_len = vector_len(s, decode); 2620 int mask = (vec_len >> ot) - 1; 2621 int val = decode->immediate & mask; 2622 2623 switch (ot) { 2624 case MO_8: 2625 tcg_gen_ld8u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2626 break; 2627 case MO_16: 2628 tcg_gen_ld16u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2629 break; 2630 case MO_32: 2631#ifdef TARGET_X86_64 2632 tcg_gen_ld32u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2633 break; 2634 case MO_64: 2635#endif 2636 tcg_gen_ld_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2637 break; 2638 default: 2639 abort(); 2640 } 2641} 2642 2643static void gen_PEXTRB(DisasContext *s, X86DecodedInsn *decode) 2644{ 2645 gen_pextr(s, decode, MO_8); 2646} 2647 2648static void gen_PEXTRW(DisasContext *s, X86DecodedInsn *decode) 2649{ 2650 gen_pextr(s, decode, MO_16); 2651} 2652 2653static void gen_PEXTR(DisasContext *s, X86DecodedInsn *decode) 2654{ 2655 MemOp ot = decode->op[0].ot; 2656 gen_pextr(s, decode, ot); 2657} 2658 2659static inline void gen_pinsr(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 2660{ 2661 int vec_len = vector_len(s, decode); 2662 int mask = (vec_len >> ot) - 1; 2663 int val = decode->immediate & mask; 2664 2665 if (decode->op[1].offset != decode->op[0].offset) { 2666 assert(vec_len == 16); 2667 gen_store_sse(s, decode, decode->op[1].offset); 2668 } 2669 2670 switch (ot) { 2671 case MO_8: 2672 tcg_gen_st8_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2673 break; 2674 case MO_16: 2675 tcg_gen_st16_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2676 break; 2677 case MO_32: 2678#ifdef TARGET_X86_64 2679 tcg_gen_st32_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2680 break; 2681 case MO_64: 2682#endif 2683 tcg_gen_st_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2684 break; 2685 default: 2686 abort(); 2687 } 2688} 2689 2690static void gen_PINSRB(DisasContext *s, X86DecodedInsn *decode) 2691{ 2692 gen_pinsr(s, decode, MO_8); 2693} 2694 2695static void gen_PINSRW(DisasContext *s, X86DecodedInsn *decode) 2696{ 2697 gen_pinsr(s, decode, MO_16); 2698} 2699 2700static void gen_PINSR(DisasContext *s, X86DecodedInsn *decode) 2701{ 2702 gen_pinsr(s, decode, decode->op[2].ot); 2703} 2704 2705static void gen_pmovmskb_i64(TCGv_i64 d, TCGv_i64 s) 2706{ 2707 TCGv_i64 t = tcg_temp_new_i64(); 2708 2709 tcg_gen_andi_i64(d, s, 0x8080808080808080ull); 2710 2711 /* 2712 * After each shift+or pair: 2713 * 0: a.......b.......c.......d.......e.......f.......g.......h....... 2714 * 7: ab......bc......cd......de......ef......fg......gh......h....... 2715 * 14: abcd....bcde....cdef....defg....efgh....fgh.....gh......h....... 2716 * 28: abcdefghbcdefgh.cdefgh..defgh...efgh....fgh.....gh......h....... 2717 * The result is left in the high bits of the word. 2718 */ 2719 tcg_gen_shli_i64(t, d, 7); 2720 tcg_gen_or_i64(d, d, t); 2721 tcg_gen_shli_i64(t, d, 14); 2722 tcg_gen_or_i64(d, d, t); 2723 tcg_gen_shli_i64(t, d, 28); 2724 tcg_gen_or_i64(d, d, t); 2725} 2726 2727static void gen_pmovmskb_vec(unsigned vece, TCGv_vec d, TCGv_vec s) 2728{ 2729 TCGv_vec t = tcg_temp_new_vec_matching(d); 2730 TCGv_vec m = tcg_constant_vec_matching(d, MO_8, 0x80); 2731 2732 /* See above */ 2733 tcg_gen_and_vec(vece, d, s, m); 2734 tcg_gen_shli_vec(vece, t, d, 7); 2735 tcg_gen_or_vec(vece, d, d, t); 2736 tcg_gen_shli_vec(vece, t, d, 14); 2737 tcg_gen_or_vec(vece, d, d, t); 2738 tcg_gen_shli_vec(vece, t, d, 28); 2739 tcg_gen_or_vec(vece, d, d, t); 2740} 2741 2742static void gen_PMOVMSKB(DisasContext *s, X86DecodedInsn *decode) 2743{ 2744 static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 }; 2745 static const GVecGen2 g = { 2746 .fni8 = gen_pmovmskb_i64, 2747 .fniv = gen_pmovmskb_vec, 2748 .opt_opc = vecop_list, 2749 .vece = MO_64, 2750 .prefer_i64 = TCG_TARGET_REG_BITS == 64 2751 }; 2752 MemOp ot = decode->op[2].ot; 2753 int vec_len = vector_len(s, decode); 2754 TCGv t = tcg_temp_new(); 2755 2756 tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode->op[2].offset, 2757 vec_len, vec_len, &g); 2758 tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); 2759 while (vec_len > 8) { 2760 vec_len -= 8; 2761 if (TCG_TARGET_HAS_extract2_tl) { 2762 /* 2763 * Load the next byte of the result into the high byte of T. 2764 * TCG does a similar expansion of deposit to shl+extract2; by 2765 * loading the whole word, the shift left is avoided. 2766 */ 2767#ifdef TARGET_X86_64 2768 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8))); 2769#else 2770 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L((vec_len - 1) / 4))); 2771#endif 2772 2773 tcg_gen_extract2_tl(s->T0, t, s->T0, TARGET_LONG_BITS - 8); 2774 } else { 2775 /* 2776 * The _previous_ value is deposited into bits 8 and higher of t. Because 2777 * those bits are known to be zero after ld8u, this becomes a shift+or 2778 * if deposit is not available. 2779 */ 2780 tcg_gen_ld8u_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); 2781 tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8); 2782 } 2783 } 2784} 2785 2786static void gen_POP(DisasContext *s, X86DecodedInsn *decode) 2787{ 2788 X86DecodedOp *op = &decode->op[0]; 2789 MemOp ot = gen_pop_T0(s); 2790 2791 if (op->has_ea || op->unit == X86_OP_SEG) { 2792 /* NOTE: order is important for MMU exceptions */ 2793 gen_writeback(s, decode, 0, s->T0); 2794 } 2795 2796 /* NOTE: writing back registers after update is important for pop %sp */ 2797 gen_pop_update(s, ot); 2798} 2799 2800static void gen_POPA(DisasContext *s, X86DecodedInsn *decode) 2801{ 2802 gen_popa(s); 2803} 2804 2805static void gen_POPCNT(DisasContext *s, X86DecodedInsn *decode) 2806{ 2807 decode->cc_dst = tcg_temp_new(); 2808 decode->cc_op = CC_OP_POPCNT; 2809 2810 tcg_gen_mov_tl(decode->cc_dst, s->T0); 2811 tcg_gen_ctpop_tl(s->T0, s->T0); 2812} 2813 2814static void gen_POPF(DisasContext *s, X86DecodedInsn *decode) 2815{ 2816 MemOp ot; 2817 int mask = TF_MASK | AC_MASK | ID_MASK | NT_MASK; 2818 2819 if (CPL(s) == 0) { 2820 mask |= IF_MASK | IOPL_MASK; 2821 } else if (CPL(s) <= IOPL(s)) { 2822 mask |= IF_MASK; 2823 } 2824 if (s->dflag == MO_16) { 2825 mask &= 0xffff; 2826 } 2827 2828 ot = gen_pop_T0(s); 2829 gen_helper_write_eflags(tcg_env, s->T0, tcg_constant_i32(mask)); 2830 gen_pop_update(s, ot); 2831 set_cc_op(s, CC_OP_EFLAGS); 2832 /* abort translation because TF/AC flag may change */ 2833 s->base.is_jmp = DISAS_EOB_NEXT; 2834} 2835 2836static void gen_PSHUFW(DisasContext *s, X86DecodedInsn *decode) 2837{ 2838 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2839 gen_helper_pshufw_mmx(OP_PTR0, OP_PTR1, imm); 2840} 2841 2842static void gen_PSRLW_i(DisasContext *s, X86DecodedInsn *decode) 2843{ 2844 int vec_len = vector_len(s, decode); 2845 2846 if (decode->immediate >= 16) { 2847 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2848 } else { 2849 tcg_gen_gvec_shri(MO_16, 2850 decode->op[0].offset, decode->op[1].offset, 2851 decode->immediate, vec_len, vec_len); 2852 } 2853} 2854 2855static void gen_PSLLW_i(DisasContext *s, X86DecodedInsn *decode) 2856{ 2857 int vec_len = vector_len(s, decode); 2858 2859 if (decode->immediate >= 16) { 2860 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2861 } else { 2862 tcg_gen_gvec_shli(MO_16, 2863 decode->op[0].offset, decode->op[1].offset, 2864 decode->immediate, vec_len, vec_len); 2865 } 2866} 2867 2868static void gen_PSRAW_i(DisasContext *s, X86DecodedInsn *decode) 2869{ 2870 int vec_len = vector_len(s, decode); 2871 2872 if (decode->immediate >= 16) { 2873 decode->immediate = 15; 2874 } 2875 tcg_gen_gvec_sari(MO_16, 2876 decode->op[0].offset, decode->op[1].offset, 2877 decode->immediate, vec_len, vec_len); 2878} 2879 2880static void gen_PSRLD_i(DisasContext *s, X86DecodedInsn *decode) 2881{ 2882 int vec_len = vector_len(s, decode); 2883 2884 if (decode->immediate >= 32) { 2885 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2886 } else { 2887 tcg_gen_gvec_shri(MO_32, 2888 decode->op[0].offset, decode->op[1].offset, 2889 decode->immediate, vec_len, vec_len); 2890 } 2891} 2892 2893static void gen_PSLLD_i(DisasContext *s, X86DecodedInsn *decode) 2894{ 2895 int vec_len = vector_len(s, decode); 2896 2897 if (decode->immediate >= 32) { 2898 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2899 } else { 2900 tcg_gen_gvec_shli(MO_32, 2901 decode->op[0].offset, decode->op[1].offset, 2902 decode->immediate, vec_len, vec_len); 2903 } 2904} 2905 2906static void gen_PSRAD_i(DisasContext *s, X86DecodedInsn *decode) 2907{ 2908 int vec_len = vector_len(s, decode); 2909 2910 if (decode->immediate >= 32) { 2911 decode->immediate = 31; 2912 } 2913 tcg_gen_gvec_sari(MO_32, 2914 decode->op[0].offset, decode->op[1].offset, 2915 decode->immediate, vec_len, vec_len); 2916} 2917 2918static void gen_PSRLQ_i(DisasContext *s, X86DecodedInsn *decode) 2919{ 2920 int vec_len = vector_len(s, decode); 2921 2922 if (decode->immediate >= 64) { 2923 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2924 } else { 2925 tcg_gen_gvec_shri(MO_64, 2926 decode->op[0].offset, decode->op[1].offset, 2927 decode->immediate, vec_len, vec_len); 2928 } 2929} 2930 2931static void gen_PSLLQ_i(DisasContext *s, X86DecodedInsn *decode) 2932{ 2933 int vec_len = vector_len(s, decode); 2934 2935 if (decode->immediate >= 64) { 2936 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2937 } else { 2938 tcg_gen_gvec_shli(MO_64, 2939 decode->op[0].offset, decode->op[1].offset, 2940 decode->immediate, vec_len, vec_len); 2941 } 2942} 2943 2944static TCGv_ptr make_imm8u_xmm_vec(uint8_t imm, int vec_len) 2945{ 2946 MemOp ot = vec_len == 16 ? MO_128 : MO_256; 2947 TCGv_i32 imm_v = tcg_constant8u_i32(imm); 2948 TCGv_ptr ptr = tcg_temp_new_ptr(); 2949 2950 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), 2951 vec_len, vec_len, 0); 2952 2953 tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_t0)); 2954 tcg_gen_st_i32(imm_v, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0))); 2955 return ptr; 2956} 2957 2958static void gen_PSRLDQ_i(DisasContext *s, X86DecodedInsn *decode) 2959{ 2960 int vec_len = vector_len(s, decode); 2961 TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len); 2962 2963 if (s->vex_l) { 2964 gen_helper_psrldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 2965 } else { 2966 gen_helper_psrldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 2967 } 2968} 2969 2970static void gen_PSLLDQ_i(DisasContext *s, X86DecodedInsn *decode) 2971{ 2972 int vec_len = vector_len(s, decode); 2973 TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len); 2974 2975 if (s->vex_l) { 2976 gen_helper_pslldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 2977 } else { 2978 gen_helper_pslldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 2979 } 2980} 2981 2982static void gen_PUSH(DisasContext *s, X86DecodedInsn *decode) 2983{ 2984 gen_push_v(s, s->T0); 2985} 2986 2987static void gen_PUSHA(DisasContext *s, X86DecodedInsn *decode) 2988{ 2989 gen_pusha(s); 2990} 2991 2992static void gen_PUSHF(DisasContext *s, X86DecodedInsn *decode) 2993{ 2994 gen_update_cc_op(s); 2995 gen_helper_read_eflags(s->T0, tcg_env); 2996 gen_push_v(s, s->T0); 2997} 2998 2999static MemOp gen_shift_count(DisasContext *s, X86DecodedInsn *decode, 3000 bool *can_be_zero, TCGv *count, int unit) 3001{ 3002 MemOp ot = decode->op[0].ot; 3003 int mask = (ot <= MO_32 ? 0x1f : 0x3f); 3004 3005 *can_be_zero = false; 3006 switch (unit) { 3007 case X86_OP_INT: 3008 *count = tcg_temp_new(); 3009 tcg_gen_andi_tl(*count, cpu_regs[R_ECX], mask); 3010 *can_be_zero = true; 3011 break; 3012 3013 case X86_OP_IMM: 3014 if ((decode->immediate & mask) == 0) { 3015 *count = NULL; 3016 break; 3017 } 3018 *count = tcg_temp_new(); 3019 tcg_gen_movi_tl(*count, decode->immediate & mask); 3020 break; 3021 3022 case X86_OP_SKIP: 3023 *count = tcg_temp_new(); 3024 tcg_gen_movi_tl(*count, 1); 3025 break; 3026 3027 default: 3028 g_assert_not_reached(); 3029 } 3030 3031 return ot; 3032} 3033 3034/* 3035 * Compute existing flags in decode->cc_src, for gen_* functions that wants 3036 * to set the cc_op set to CC_OP_ADCOX. In particular, this allows rotate 3037 * operations to compute the carry in decode->cc_dst and the overflow in 3038 * decode->cc_src2. 3039 * 3040 * If need_flags is true, decode->cc_dst and decode->cc_src2 are preloaded 3041 * with the value of CF and OF before the instruction, so that it is possible 3042 * to keep the flags unmodified. 3043 * 3044 * Return true if carry could be made available cheaply as a 1-bit value in 3045 * decode->cc_dst (trying a bit harder if want_carry is true). If false is 3046 * returned, decode->cc_dst is uninitialized and the carry is only available 3047 * as bit 0 of decode->cc_src. 3048 */ 3049static bool gen_eflags_adcox(DisasContext *s, X86DecodedInsn *decode, bool want_carry, bool need_flags) 3050{ 3051 bool got_cf = false; 3052 bool got_of = false; 3053 3054 decode->cc_dst = tcg_temp_new(); 3055 decode->cc_src = tcg_temp_new(); 3056 decode->cc_src2 = tcg_temp_new(); 3057 decode->cc_op = CC_OP_ADCOX; 3058 3059 /* A lot more cc_ops could be "optimized" to avoid the extracts at 3060 * the end (INC/DEC, BMILG, MUL), but they are all really unlikely 3061 * to be followed by rotations within the same basic block. 3062 */ 3063 switch (s->cc_op) { 3064 case CC_OP_ADCOX: 3065 /* No need to compute the full EFLAGS, CF/OF are already isolated. */ 3066 tcg_gen_mov_tl(decode->cc_src, cpu_cc_src); 3067 if (need_flags) { 3068 tcg_gen_mov_tl(decode->cc_src2, cpu_cc_src2); 3069 got_of = true; 3070 } 3071 if (want_carry || need_flags) { 3072 tcg_gen_mov_tl(decode->cc_dst, cpu_cc_dst); 3073 got_cf = true; 3074 } 3075 break; 3076 3077 case CC_OP_LOGICB ... CC_OP_LOGICQ: 3078 /* CF and OF are zero, do it just because it's easy. */ 3079 gen_mov_eflags(s, decode->cc_src); 3080 if (need_flags) { 3081 tcg_gen_movi_tl(decode->cc_src2, 0); 3082 got_of = true; 3083 } 3084 if (want_carry || need_flags) { 3085 tcg_gen_movi_tl(decode->cc_dst, 0); 3086 got_cf = true; 3087 } 3088 break; 3089 3090 case CC_OP_SARB ... CC_OP_SARQ: 3091 /* 3092 * SHR/RCR/SHR/RCR/... is a relatively common occurrence of RCR. 3093 * By computing CF without using eflags, the calls to cc_compute_all 3094 * can be eliminated as dead code (except for the last RCR). 3095 */ 3096 if (want_carry || need_flags) { 3097 tcg_gen_andi_tl(decode->cc_dst, cpu_cc_src, 1); 3098 got_cf = true; 3099 } 3100 gen_mov_eflags(s, decode->cc_src); 3101 break; 3102 3103 case CC_OP_SHLB ... CC_OP_SHLQ: 3104 /* 3105 * Likewise for SHL/RCL/SHL/RCL/... but, if CF is not in the sign 3106 * bit, we might as well fish CF out of EFLAGS and save a shift. 3107 */ 3108 if (want_carry && (!need_flags || s->cc_op == CC_OP_SHLB + MO_TL)) { 3109 tcg_gen_shri_tl(decode->cc_dst, cpu_cc_src, (8 << (s->cc_op - CC_OP_SHLB)) - 1); 3110 got_cf = true; 3111 } 3112 gen_mov_eflags(s, decode->cc_src); 3113 break; 3114 3115 default: 3116 gen_mov_eflags(s, decode->cc_src); 3117 break; 3118 } 3119 3120 if (need_flags) { 3121 /* If the flags could be left unmodified, always load them. */ 3122 if (!got_of) { 3123 tcg_gen_extract_tl(decode->cc_src2, decode->cc_src, ctz32(CC_O), 1); 3124 got_of = true; 3125 } 3126 if (!got_cf) { 3127 tcg_gen_extract_tl(decode->cc_dst, decode->cc_src, ctz32(CC_C), 1); 3128 got_cf = true; 3129 } 3130 } 3131 return got_cf; 3132} 3133 3134static void gen_rot_overflow(X86DecodedInsn *decode, TCGv result, TCGv old, 3135 bool can_be_zero, TCGv count) 3136{ 3137 MemOp ot = decode->op[0].ot; 3138 TCGv temp = can_be_zero ? tcg_temp_new() : decode->cc_src2; 3139 3140 tcg_gen_xor_tl(temp, old, result); 3141 tcg_gen_extract_tl(temp, temp, (8 << ot) - 1, 1); 3142 if (can_be_zero) { 3143 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src2, count, tcg_constant_tl(0), 3144 decode->cc_src2, temp); 3145 } 3146} 3147 3148/* 3149 * RCx operations are invariant modulo 8*operand_size+1. For 8 and 16-bit operands, 3150 * this is less than 0x1f (the mask applied by gen_shift_count) so reduce further. 3151 */ 3152static void gen_rotc_mod(MemOp ot, TCGv count) 3153{ 3154 TCGv temp; 3155 3156 switch (ot) { 3157 case MO_8: 3158 temp = tcg_temp_new(); 3159 tcg_gen_subi_tl(temp, count, 18); 3160 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3161 tcg_gen_subi_tl(temp, count, 9); 3162 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3163 break; 3164 3165 case MO_16: 3166 temp = tcg_temp_new(); 3167 tcg_gen_subi_tl(temp, count, 17); 3168 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3169 break; 3170 3171 default: 3172 break; 3173 } 3174} 3175 3176/* 3177 * The idea here is that the bit to the right of the new bit 0 is the 3178 * new carry, and the bit to the right of the old bit 0 is the old carry. 3179 * Just like a regular rotation, the result of the rotation is composed 3180 * from a right shifted part and a left shifted part of s->T0. The new carry 3181 * is extracted from the right-shifted portion, and the old carry is 3182 * inserted at the end of the left-shifted portion. 3183 * 3184 * Because of the separate shifts involving the carry, gen_RCL and gen_RCR 3185 * mostly operate on count-1. This also comes in handy when computing 3186 * length - count, because (length-1) - (count-1) can be computed with 3187 * a XOR, and that is commutative unlike subtraction. 3188 */ 3189static void gen_RCL(DisasContext *s, X86DecodedInsn *decode) 3190{ 3191 bool have_1bit_cin, can_be_zero; 3192 TCGv count; 3193 TCGLabel *zero_label = NULL; 3194 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3195 TCGv low, high, low_count; 3196 3197 if (!count) { 3198 return; 3199 } 3200 3201 low = tcg_temp_new(); 3202 high = tcg_temp_new(); 3203 low_count = tcg_temp_new(); 3204 3205 gen_rotc_mod(ot, count); 3206 have_1bit_cin = gen_eflags_adcox(s, decode, true, can_be_zero); 3207 if (can_be_zero) { 3208 zero_label = gen_new_label(); 3209 tcg_gen_brcondi_tl(TCG_COND_EQ, count, 0, zero_label); 3210 } 3211 3212 /* Compute high part, including incoming carry. */ 3213 if (!have_1bit_cin || TCG_TARGET_deposit_tl_valid(1, TARGET_LONG_BITS - 1)) { 3214 /* high = (T0 << 1) | cin */ 3215 TCGv cin = have_1bit_cin ? decode->cc_dst : decode->cc_src; 3216 tcg_gen_deposit_tl(high, cin, s->T0, 1, TARGET_LONG_BITS - 1); 3217 } else { 3218 /* Same as above but without deposit; cin in cc_dst. */ 3219 tcg_gen_add_tl(high, s->T0, decode->cc_dst); 3220 tcg_gen_add_tl(high, high, s->T0); 3221 } 3222 tcg_gen_subi_tl(count, count, 1); 3223 tcg_gen_shl_tl(high, high, count); 3224 3225 /* Compute low part and outgoing carry, incoming s->T0 is zero extended */ 3226 tcg_gen_xori_tl(low_count, count, (8 << ot) - 1); /* LENGTH - 1 - (count - 1) */ 3227 tcg_gen_shr_tl(low, s->T0, low_count); 3228 tcg_gen_andi_tl(decode->cc_dst, low, 1); 3229 tcg_gen_shri_tl(low, low, 1); 3230 3231 /* Compute result and outgoing overflow */ 3232 tcg_gen_mov_tl(decode->cc_src2, s->T0); 3233 tcg_gen_or_tl(s->T0, low, high); 3234 gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); 3235 3236 if (zero_label) { 3237 gen_set_label(zero_label); 3238 } 3239} 3240 3241static void gen_RCR(DisasContext *s, X86DecodedInsn *decode) 3242{ 3243 bool have_1bit_cin, can_be_zero; 3244 TCGv count; 3245 TCGLabel *zero_label = NULL; 3246 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3247 TCGv low, high, high_count; 3248 3249 if (!count) { 3250 return; 3251 } 3252 3253 low = tcg_temp_new(); 3254 high = tcg_temp_new(); 3255 high_count = tcg_temp_new(); 3256 3257 gen_rotc_mod(ot, count); 3258 have_1bit_cin = gen_eflags_adcox(s, decode, true, can_be_zero); 3259 if (can_be_zero) { 3260 zero_label = gen_new_label(); 3261 tcg_gen_brcondi_tl(TCG_COND_EQ, count, 0, zero_label); 3262 } 3263 3264 /* Save incoming carry into high, it will be shifted later. */ 3265 if (!have_1bit_cin || TCG_TARGET_deposit_tl_valid(1, TARGET_LONG_BITS - 1)) { 3266 TCGv cin = have_1bit_cin ? decode->cc_dst : decode->cc_src; 3267 tcg_gen_deposit_tl(high, cin, s->T0, 1, TARGET_LONG_BITS - 1); 3268 } else { 3269 /* Same as above but without deposit; cin in cc_dst. */ 3270 tcg_gen_add_tl(high, s->T0, decode->cc_dst); 3271 tcg_gen_add_tl(high, high, s->T0); 3272 } 3273 3274 /* Compute low part and outgoing carry, incoming s->T0 is zero extended */ 3275 tcg_gen_subi_tl(count, count, 1); 3276 tcg_gen_shr_tl(low, s->T0, count); 3277 tcg_gen_andi_tl(decode->cc_dst, low, 1); 3278 tcg_gen_shri_tl(low, low, 1); 3279 3280 /* Move high part to the right position */ 3281 tcg_gen_xori_tl(high_count, count, (8 << ot) - 1); /* LENGTH - 1 - (count - 1) */ 3282 tcg_gen_shl_tl(high, high, high_count); 3283 3284 /* Compute result and outgoing overflow */ 3285 tcg_gen_mov_tl(decode->cc_src2, s->T0); 3286 tcg_gen_or_tl(s->T0, low, high); 3287 gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); 3288 3289 if (zero_label) { 3290 gen_set_label(zero_label); 3291 } 3292} 3293 3294#ifdef CONFIG_USER_ONLY 3295static void gen_unreachable(DisasContext *s, X86DecodedInsn *decode) 3296{ 3297 g_assert_not_reached(); 3298} 3299#endif 3300 3301#ifndef CONFIG_USER_ONLY 3302static void gen_RDMSR(DisasContext *s, X86DecodedInsn *decode) 3303{ 3304 gen_update_cc_op(s); 3305 gen_update_eip_cur(s); 3306 gen_helper_rdmsr(tcg_env); 3307} 3308#else 3309#define gen_RDMSR gen_unreachable 3310#endif 3311 3312static void gen_RDPMC(DisasContext *s, X86DecodedInsn *decode) 3313{ 3314 gen_update_cc_op(s); 3315 gen_update_eip_cur(s); 3316 translator_io_start(&s->base); 3317 gen_helper_rdpmc(tcg_env); 3318 s->base.is_jmp = DISAS_NORETURN; 3319} 3320 3321static void gen_RDTSC(DisasContext *s, X86DecodedInsn *decode) 3322{ 3323 gen_update_cc_op(s); 3324 gen_update_eip_cur(s); 3325 translator_io_start(&s->base); 3326 gen_helper_rdtsc(tcg_env); 3327} 3328 3329static void gen_RDxxBASE(DisasContext *s, X86DecodedInsn *decode) 3330{ 3331 TCGv base = cpu_seg_base[s->modrm & 8 ? R_GS : R_FS]; 3332 3333 /* Preserve hflags bits by testing CR4 at runtime. */ 3334 gen_helper_cr4_testbit(tcg_env, tcg_constant_i32(CR4_FSGSBASE_MASK)); 3335 tcg_gen_mov_tl(s->T0, base); 3336} 3337 3338static void gen_RET(DisasContext *s, X86DecodedInsn *decode) 3339{ 3340 int16_t adjust = decode->e.op1 == X86_TYPE_I ? decode->immediate : 0; 3341 3342 MemOp ot = gen_pop_T0(s); 3343 gen_stack_update(s, adjust + (1 << ot)); 3344 gen_op_jmp_v(s, s->T0); 3345 gen_bnd_jmp(s); 3346 s->base.is_jmp = DISAS_JUMP; 3347} 3348 3349static void gen_RETF(DisasContext *s, X86DecodedInsn *decode) 3350{ 3351 int16_t adjust = decode->e.op1 == X86_TYPE_I ? decode->immediate : 0; 3352 3353 if (!PE(s) || VM86(s)) { 3354 gen_lea_ss_ofs(s, s->A0, cpu_regs[R_ESP], 0); 3355 /* pop offset */ 3356 gen_op_ld_v(s, s->dflag, s->T0, s->A0); 3357 /* NOTE: keeping EIP updated is not a problem in case of 3358 exception */ 3359 gen_op_jmp_v(s, s->T0); 3360 /* pop selector */ 3361 gen_add_A0_im(s, 1 << s->dflag); 3362 gen_op_ld_v(s, s->dflag, s->T0, s->A0); 3363 gen_op_movl_seg_real(s, R_CS, s->T0); 3364 /* add stack offset */ 3365 gen_stack_update(s, adjust + (2 << s->dflag)); 3366 } else { 3367 gen_update_cc_op(s); 3368 gen_update_eip_cur(s); 3369 gen_helper_lret_protected(tcg_env, tcg_constant_i32(s->dflag - 1), 3370 tcg_constant_i32(adjust)); 3371 } 3372 s->base.is_jmp = DISAS_EOB_ONLY; 3373} 3374 3375/* 3376 * Return non-NULL if a 32-bit rotate works, after possibly replicating the input. 3377 * The input has already been zero-extended upon operand decode. 3378 */ 3379static TCGv_i32 gen_rot_replicate(MemOp ot, TCGv in) 3380{ 3381 TCGv_i32 temp; 3382 switch (ot) { 3383 case MO_8: 3384 temp = tcg_temp_new_i32(); 3385 tcg_gen_trunc_tl_i32(temp, in); 3386 tcg_gen_muli_i32(temp, temp, 0x01010101); 3387 return temp; 3388 3389 case MO_16: 3390 temp = tcg_temp_new_i32(); 3391 tcg_gen_trunc_tl_i32(temp, in); 3392 tcg_gen_deposit_i32(temp, temp, temp, 16, 16); 3393 return temp; 3394 3395#ifdef TARGET_X86_64 3396 case MO_32: 3397 temp = tcg_temp_new_i32(); 3398 tcg_gen_trunc_tl_i32(temp, in); 3399 return temp; 3400#endif 3401 3402 default: 3403 return NULL; 3404 } 3405} 3406 3407static void gen_rot_carry(X86DecodedInsn *decode, TCGv result, 3408 bool can_be_zero, TCGv count, int bit) 3409{ 3410 if (!can_be_zero) { 3411 tcg_gen_extract_tl(decode->cc_dst, result, bit, 1); 3412 } else { 3413 TCGv temp = tcg_temp_new(); 3414 tcg_gen_extract_tl(temp, result, bit, 1); 3415 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_dst, count, tcg_constant_tl(0), 3416 decode->cc_dst, temp); 3417 } 3418} 3419 3420static void gen_ROL(DisasContext *s, X86DecodedInsn *decode) 3421{ 3422 bool can_be_zero; 3423 TCGv count; 3424 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3425 TCGv_i32 temp32, count32; 3426 TCGv old = tcg_temp_new(); 3427 3428 if (!count) { 3429 return; 3430 } 3431 3432 gen_eflags_adcox(s, decode, false, can_be_zero); 3433 tcg_gen_mov_tl(old, s->T0); 3434 temp32 = gen_rot_replicate(ot, s->T0); 3435 if (temp32) { 3436 count32 = tcg_temp_new_i32(); 3437 tcg_gen_trunc_tl_i32(count32, count); 3438 tcg_gen_rotl_i32(temp32, temp32, count32); 3439 /* Zero extend to facilitate later optimization. */ 3440 tcg_gen_extu_i32_tl(s->T0, temp32); 3441 } else { 3442 tcg_gen_rotl_tl(s->T0, s->T0, count); 3443 } 3444 gen_rot_carry(decode, s->T0, can_be_zero, count, 0); 3445 gen_rot_overflow(decode, s->T0, old, can_be_zero, count); 3446} 3447 3448static void gen_ROR(DisasContext *s, X86DecodedInsn *decode) 3449{ 3450 bool can_be_zero; 3451 TCGv count; 3452 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3453 TCGv_i32 temp32, count32; 3454 TCGv old = tcg_temp_new(); 3455 3456 if (!count) { 3457 return; 3458 } 3459 3460 gen_eflags_adcox(s, decode, false, can_be_zero); 3461 tcg_gen_mov_tl(old, s->T0); 3462 temp32 = gen_rot_replicate(ot, s->T0); 3463 if (temp32) { 3464 count32 = tcg_temp_new_i32(); 3465 tcg_gen_trunc_tl_i32(count32, count); 3466 tcg_gen_rotr_i32(temp32, temp32, count32); 3467 /* Zero extend to facilitate later optimization. */ 3468 tcg_gen_extu_i32_tl(s->T0, temp32); 3469 gen_rot_carry(decode, s->T0, can_be_zero, count, 31); 3470 } else { 3471 tcg_gen_rotr_tl(s->T0, s->T0, count); 3472 gen_rot_carry(decode, s->T0, can_be_zero, count, TARGET_LONG_BITS - 1); 3473 } 3474 gen_rot_overflow(decode, s->T0, old, can_be_zero, count); 3475} 3476 3477static void gen_RORX(DisasContext *s, X86DecodedInsn *decode) 3478{ 3479 MemOp ot = decode->op[0].ot; 3480 int mask = ot == MO_64 ? 63 : 31; 3481 int b = decode->immediate & mask; 3482 3483 switch (ot) { 3484 case MO_32: 3485#ifdef TARGET_X86_64 3486 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 3487 tcg_gen_rotri_i32(s->tmp2_i32, s->tmp2_i32, b); 3488 tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); 3489 break; 3490 3491 case MO_64: 3492#endif 3493 tcg_gen_rotri_tl(s->T0, s->T0, b); 3494 break; 3495 3496 default: 3497 g_assert_not_reached(); 3498 } 3499} 3500 3501#ifndef CONFIG_USER_ONLY 3502static void gen_RSM(DisasContext *s, X86DecodedInsn *decode) 3503{ 3504 gen_helper_rsm(tcg_env); 3505 assume_cc_op(s, CC_OP_EFLAGS); 3506 s->base.is_jmp = DISAS_EOB_ONLY; 3507} 3508#else 3509#define gen_RSM gen_UD 3510#endif 3511 3512static void gen_SAHF(DisasContext *s, X86DecodedInsn *decode) 3513{ 3514 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) { 3515 return gen_illegal_opcode(s); 3516 } 3517 tcg_gen_shri_tl(s->T0, cpu_regs[R_EAX], 8); 3518 gen_compute_eflags(s); 3519 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); 3520 tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C); 3521 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, s->T0); 3522} 3523 3524static void gen_SALC(DisasContext *s, X86DecodedInsn *decode) 3525{ 3526 gen_compute_eflags_c(s, s->T0); 3527 tcg_gen_neg_tl(s->T0, s->T0); 3528} 3529 3530static void gen_shift_dynamic_flags(DisasContext *s, X86DecodedInsn *decode, TCGv count, CCOp cc_op) 3531{ 3532 TCGv_i32 count32 = tcg_temp_new_i32(); 3533 TCGv_i32 old_cc_op; 3534 3535 decode->cc_op = CC_OP_DYNAMIC; 3536 decode->cc_op_dynamic = tcg_temp_new_i32(); 3537 3538 assert(decode->cc_dst == s->T0); 3539 if (cc_op_live[s->cc_op] & USES_CC_DST) { 3540 decode->cc_dst = tcg_temp_new(); 3541 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_dst, count, tcg_constant_tl(0), 3542 cpu_cc_dst, s->T0); 3543 } 3544 3545 if (cc_op_live[s->cc_op] & USES_CC_SRC) { 3546 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src, count, tcg_constant_tl(0), 3547 cpu_cc_src, decode->cc_src); 3548 } 3549 3550 tcg_gen_trunc_tl_i32(count32, count); 3551 if (s->cc_op == CC_OP_DYNAMIC) { 3552 old_cc_op = cpu_cc_op; 3553 } else { 3554 old_cc_op = tcg_constant_i32(s->cc_op); 3555 } 3556 tcg_gen_movcond_i32(TCG_COND_EQ, decode->cc_op_dynamic, count32, tcg_constant_i32(0), 3557 old_cc_op, tcg_constant_i32(cc_op)); 3558} 3559 3560static void gen_SAR(DisasContext *s, X86DecodedInsn *decode) 3561{ 3562 bool can_be_zero; 3563 TCGv count; 3564 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3565 3566 if (!count) { 3567 return; 3568 } 3569 3570 decode->cc_dst = s->T0; 3571 decode->cc_src = tcg_temp_new(); 3572 tcg_gen_subi_tl(decode->cc_src, count, 1); 3573 tcg_gen_sar_tl(decode->cc_src, s->T0, decode->cc_src); 3574 tcg_gen_sar_tl(s->T0, s->T0, count); 3575 if (can_be_zero) { 3576 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 3577 } else { 3578 decode->cc_op = CC_OP_SARB + ot; 3579 } 3580} 3581 3582static void gen_SARX(DisasContext *s, X86DecodedInsn *decode) 3583{ 3584 MemOp ot = decode->op[0].ot; 3585 int mask; 3586 3587 mask = ot == MO_64 ? 63 : 31; 3588 tcg_gen_andi_tl(s->T1, s->T1, mask); 3589 tcg_gen_sar_tl(s->T0, s->T0, s->T1); 3590} 3591 3592static void gen_SBB(DisasContext *s, X86DecodedInsn *decode) 3593{ 3594 MemOp ot = decode->op[0].ot; 3595 TCGv c_in = tcg_temp_new(); 3596 3597 gen_compute_eflags_c(s, c_in); 3598 if (s->prefix & PREFIX_LOCK) { 3599 tcg_gen_add_tl(s->T0, s->T1, c_in); 3600 tcg_gen_neg_tl(s->T0, s->T0); 3601 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T0, 3602 s->mem_index, ot | MO_LE); 3603 } else { 3604 /* 3605 * TODO: SBB reg, reg could use gen_prepare_eflags_c followed by 3606 * negsetcond, and CC_OP_SUBB as the cc_op. 3607 */ 3608 tcg_gen_sub_tl(s->T0, s->T0, s->T1); 3609 tcg_gen_sub_tl(s->T0, s->T0, c_in); 3610 } 3611 prepare_update3_cc(decode, s, CC_OP_SBBB + ot, c_in); 3612} 3613 3614static void gen_SCAS(DisasContext *s, X86DecodedInsn *decode) 3615{ 3616 MemOp ot = decode->op[2].ot; 3617 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 3618 gen_repz_nz(s, ot, gen_scas); 3619 } else { 3620 gen_scas(s, ot); 3621 } 3622} 3623 3624static void gen_SETcc(DisasContext *s, X86DecodedInsn *decode) 3625{ 3626 gen_setcc1(s, decode->b & 0xf, s->T0); 3627} 3628 3629static void gen_SFENCE(DisasContext *s, X86DecodedInsn *decode) 3630{ 3631 tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC); 3632} 3633 3634static void gen_SHA1NEXTE(DisasContext *s, X86DecodedInsn *decode) 3635{ 3636 gen_helper_sha1nexte(OP_PTR0, OP_PTR1, OP_PTR2); 3637} 3638 3639static void gen_SHA1MSG1(DisasContext *s, X86DecodedInsn *decode) 3640{ 3641 gen_helper_sha1msg1(OP_PTR0, OP_PTR1, OP_PTR2); 3642} 3643 3644static void gen_SHA1MSG2(DisasContext *s, X86DecodedInsn *decode) 3645{ 3646 gen_helper_sha1msg2(OP_PTR0, OP_PTR1, OP_PTR2); 3647} 3648 3649static void gen_SHA1RNDS4(DisasContext *s, X86DecodedInsn *decode) 3650{ 3651 switch(decode->immediate & 3) { 3652 case 0: 3653 gen_helper_sha1rnds4_f0(OP_PTR0, OP_PTR0, OP_PTR1); 3654 break; 3655 case 1: 3656 gen_helper_sha1rnds4_f1(OP_PTR0, OP_PTR0, OP_PTR1); 3657 break; 3658 case 2: 3659 gen_helper_sha1rnds4_f2(OP_PTR0, OP_PTR0, OP_PTR1); 3660 break; 3661 case 3: 3662 gen_helper_sha1rnds4_f3(OP_PTR0, OP_PTR0, OP_PTR1); 3663 break; 3664 } 3665} 3666 3667static void gen_SHA256MSG1(DisasContext *s, X86DecodedInsn *decode) 3668{ 3669 gen_helper_sha256msg1(OP_PTR0, OP_PTR1, OP_PTR2); 3670} 3671 3672static void gen_SHA256MSG2(DisasContext *s, X86DecodedInsn *decode) 3673{ 3674 gen_helper_sha256msg2(OP_PTR0, OP_PTR1, OP_PTR2); 3675} 3676 3677static void gen_SHA256RNDS2(DisasContext *s, X86DecodedInsn *decode) 3678{ 3679 TCGv_i32 wk0 = tcg_temp_new_i32(); 3680 TCGv_i32 wk1 = tcg_temp_new_i32(); 3681 3682 tcg_gen_ld_i32(wk0, tcg_env, ZMM_OFFSET(0) + offsetof(ZMMReg, ZMM_L(0))); 3683 tcg_gen_ld_i32(wk1, tcg_env, ZMM_OFFSET(0) + offsetof(ZMMReg, ZMM_L(1))); 3684 3685 gen_helper_sha256rnds2(OP_PTR0, OP_PTR1, OP_PTR2, wk0, wk1); 3686} 3687 3688static void gen_SHL(DisasContext *s, X86DecodedInsn *decode) 3689{ 3690 bool can_be_zero; 3691 TCGv count; 3692 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3693 3694 if (!count) { 3695 return; 3696 } 3697 3698 decode->cc_dst = s->T0; 3699 decode->cc_src = tcg_temp_new(); 3700 tcg_gen_subi_tl(decode->cc_src, count, 1); 3701 tcg_gen_shl_tl(decode->cc_src, s->T0, decode->cc_src); 3702 tcg_gen_shl_tl(s->T0, s->T0, count); 3703 if (can_be_zero) { 3704 gen_shift_dynamic_flags(s, decode, count, CC_OP_SHLB + ot); 3705 } else { 3706 decode->cc_op = CC_OP_SHLB + ot; 3707 } 3708} 3709 3710static void gen_SHLD(DisasContext *s, X86DecodedInsn *decode) 3711{ 3712 bool can_be_zero; 3713 TCGv count; 3714 int unit = decode->e.op3 == X86_TYPE_I ? X86_OP_IMM : X86_OP_INT; 3715 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, unit); 3716 3717 if (!count) { 3718 return; 3719 } 3720 3721 decode->cc_dst = s->T0; 3722 decode->cc_src = s->tmp0; 3723 gen_shiftd_rm_T1(s, ot, false, count); 3724 if (can_be_zero) { 3725 gen_shift_dynamic_flags(s, decode, count, CC_OP_SHLB + ot); 3726 } else { 3727 decode->cc_op = CC_OP_SHLB + ot; 3728 } 3729} 3730 3731static void gen_SHLX(DisasContext *s, X86DecodedInsn *decode) 3732{ 3733 MemOp ot = decode->op[0].ot; 3734 int mask; 3735 3736 mask = ot == MO_64 ? 63 : 31; 3737 tcg_gen_andi_tl(s->T1, s->T1, mask); 3738 tcg_gen_shl_tl(s->T0, s->T0, s->T1); 3739} 3740 3741static void gen_SHR(DisasContext *s, X86DecodedInsn *decode) 3742{ 3743 bool can_be_zero; 3744 TCGv count; 3745 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3746 3747 if (!count) { 3748 return; 3749 } 3750 3751 decode->cc_dst = s->T0; 3752 decode->cc_src = tcg_temp_new(); 3753 tcg_gen_subi_tl(decode->cc_src, count, 1); 3754 tcg_gen_shr_tl(decode->cc_src, s->T0, decode->cc_src); 3755 tcg_gen_shr_tl(s->T0, s->T0, count); 3756 if (can_be_zero) { 3757 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 3758 } else { 3759 decode->cc_op = CC_OP_SARB + ot; 3760 } 3761} 3762 3763static void gen_SHRD(DisasContext *s, X86DecodedInsn *decode) 3764{ 3765 bool can_be_zero; 3766 TCGv count; 3767 int unit = decode->e.op3 == X86_TYPE_I ? X86_OP_IMM : X86_OP_INT; 3768 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, unit); 3769 3770 if (!count) { 3771 return; 3772 } 3773 3774 decode->cc_dst = s->T0; 3775 decode->cc_src = s->tmp0; 3776 gen_shiftd_rm_T1(s, ot, true, count); 3777 if (can_be_zero) { 3778 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 3779 } else { 3780 decode->cc_op = CC_OP_SARB + ot; 3781 } 3782} 3783 3784static void gen_SHRX(DisasContext *s, X86DecodedInsn *decode) 3785{ 3786 MemOp ot = decode->op[0].ot; 3787 int mask; 3788 3789 mask = ot == MO_64 ? 63 : 31; 3790 tcg_gen_andi_tl(s->T1, s->T1, mask); 3791 tcg_gen_shr_tl(s->T0, s->T0, s->T1); 3792} 3793 3794static void gen_STC(DisasContext *s, X86DecodedInsn *decode) 3795{ 3796 gen_compute_eflags(s); 3797 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); 3798} 3799 3800static void gen_STD(DisasContext *s, X86DecodedInsn *decode) 3801{ 3802 tcg_gen_st_i32(tcg_constant_i32(-1), tcg_env, offsetof(CPUX86State, df)); 3803} 3804 3805static void gen_STI(DisasContext *s, X86DecodedInsn *decode) 3806{ 3807 gen_set_eflags(s, IF_MASK); 3808 s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ; 3809} 3810 3811static void gen_VAESKEYGEN(DisasContext *s, X86DecodedInsn *decode) 3812{ 3813 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 3814 assert(!s->vex_l); 3815 gen_helper_aeskeygenassist_xmm(tcg_env, OP_PTR0, OP_PTR1, imm); 3816} 3817 3818static void gen_STMXCSR(DisasContext *s, X86DecodedInsn *decode) 3819{ 3820 gen_helper_update_mxcsr(tcg_env); 3821 tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr)); 3822} 3823 3824static void gen_STOS(DisasContext *s, X86DecodedInsn *decode) 3825{ 3826 MemOp ot = decode->op[1].ot; 3827 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 3828 gen_repz(s, ot, gen_stos); 3829 } else { 3830 gen_stos(s, ot); 3831 } 3832} 3833 3834static void gen_SUB(DisasContext *s, X86DecodedInsn *decode) 3835{ 3836 MemOp ot = decode->op[1].ot; 3837 3838 if (s->prefix & PREFIX_LOCK) { 3839 tcg_gen_neg_tl(s->T0, s->T1); 3840 tcg_gen_atomic_fetch_add_tl(s->cc_srcT, s->A0, s->T0, 3841 s->mem_index, ot | MO_LE); 3842 tcg_gen_sub_tl(s->T0, s->cc_srcT, s->T1); 3843 } else { 3844 tcg_gen_mov_tl(s->cc_srcT, s->T0); 3845 tcg_gen_sub_tl(s->T0, s->T0, s->T1); 3846 } 3847 prepare_update2_cc(decode, s, CC_OP_SUBB + ot); 3848} 3849 3850static void gen_SYSCALL(DisasContext *s, X86DecodedInsn *decode) 3851{ 3852 gen_update_cc_op(s); 3853 gen_update_eip_cur(s); 3854 gen_helper_syscall(tcg_env, cur_insn_len_i32(s)); 3855 if (LMA(s)) { 3856 assume_cc_op(s, CC_OP_EFLAGS); 3857 } 3858 3859 /* 3860 * TF handling for the syscall insn is different. The TF bit is checked 3861 * after the syscall insn completes. This allows #DB to not be 3862 * generated after one has entered CPL0 if TF is set in FMASK. 3863 */ 3864 s->base.is_jmp = DISAS_EOB_RECHECK_TF; 3865} 3866 3867static void gen_SYSENTER(DisasContext *s, X86DecodedInsn *decode) 3868{ 3869 gen_helper_sysenter(tcg_env); 3870 s->base.is_jmp = DISAS_EOB_ONLY; 3871} 3872 3873static void gen_SYSEXIT(DisasContext *s, X86DecodedInsn *decode) 3874{ 3875 gen_helper_sysexit(tcg_env, tcg_constant_i32(s->dflag - 1)); 3876 s->base.is_jmp = DISAS_EOB_ONLY; 3877} 3878 3879static void gen_SYSRET(DisasContext *s, X86DecodedInsn *decode) 3880{ 3881 gen_helper_sysret(tcg_env, tcg_constant_i32(s->dflag - 1)); 3882 if (LMA(s)) { 3883 assume_cc_op(s, CC_OP_EFLAGS); 3884 } 3885 3886 /* 3887 * TF handling for the sysret insn is different. The TF bit is checked 3888 * after the sysret insn completes. This allows #DB to be 3889 * generated "as if" the syscall insn in userspace has just 3890 * completed. 3891 */ 3892 s->base.is_jmp = DISAS_EOB_RECHECK_TF; 3893} 3894 3895static void gen_TZCNT(DisasContext *s, X86DecodedInsn *decode) 3896{ 3897 MemOp ot = decode->op[0].ot; 3898 3899 /* C bit (cc_src) is defined related to the input. */ 3900 decode->cc_src = tcg_temp_new(); 3901 decode->cc_dst = s->T0; 3902 decode->cc_op = CC_OP_BMILGB + ot; 3903 tcg_gen_mov_tl(decode->cc_src, s->T0); 3904 3905 /* A zero input returns the operand size. */ 3906 tcg_gen_ctzi_tl(s->T0, s->T0, 8 << ot); 3907} 3908 3909static void gen_UD(DisasContext *s, X86DecodedInsn *decode) 3910{ 3911 gen_illegal_opcode(s); 3912} 3913 3914static void gen_VAESIMC(DisasContext *s, X86DecodedInsn *decode) 3915{ 3916 assert(!s->vex_l); 3917 gen_helper_aesimc_xmm(tcg_env, OP_PTR0, OP_PTR2); 3918} 3919 3920/* 3921 * 00 = v*ps Vps, Hps, Wpd 3922 * 66 = v*pd Vpd, Hpd, Wps 3923 * f3 = v*ss Vss, Hss, Wps 3924 * f2 = v*sd Vsd, Hsd, Wps 3925 */ 3926#define SSE_CMP(x) { \ 3927 gen_helper_ ## x ## ps ## _xmm, gen_helper_ ## x ## pd ## _xmm, \ 3928 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, \ 3929 gen_helper_ ## x ## ps ## _ymm, gen_helper_ ## x ## pd ## _ymm} 3930static const SSEFunc_0_eppp gen_helper_cmp_funcs[32][6] = { 3931 SSE_CMP(cmpeq), 3932 SSE_CMP(cmplt), 3933 SSE_CMP(cmple), 3934 SSE_CMP(cmpunord), 3935 SSE_CMP(cmpneq), 3936 SSE_CMP(cmpnlt), 3937 SSE_CMP(cmpnle), 3938 SSE_CMP(cmpord), 3939 3940 SSE_CMP(cmpequ), 3941 SSE_CMP(cmpnge), 3942 SSE_CMP(cmpngt), 3943 SSE_CMP(cmpfalse), 3944 SSE_CMP(cmpnequ), 3945 SSE_CMP(cmpge), 3946 SSE_CMP(cmpgt), 3947 SSE_CMP(cmptrue), 3948 3949 SSE_CMP(cmpeqs), 3950 SSE_CMP(cmpltq), 3951 SSE_CMP(cmpleq), 3952 SSE_CMP(cmpunords), 3953 SSE_CMP(cmpneqq), 3954 SSE_CMP(cmpnltq), 3955 SSE_CMP(cmpnleq), 3956 SSE_CMP(cmpords), 3957 3958 SSE_CMP(cmpequs), 3959 SSE_CMP(cmpngeq), 3960 SSE_CMP(cmpngtq), 3961 SSE_CMP(cmpfalses), 3962 SSE_CMP(cmpnequs), 3963 SSE_CMP(cmpgeq), 3964 SSE_CMP(cmpgtq), 3965 SSE_CMP(cmptrues), 3966}; 3967#undef SSE_CMP 3968 3969static void gen_VCMP(DisasContext *s, X86DecodedInsn *decode) 3970{ 3971 int index = decode->immediate & (s->prefix & PREFIX_VEX ? 31 : 7); 3972 int b = 3973 s->prefix & PREFIX_REPZ ? 2 /* ss */ : 3974 s->prefix & PREFIX_REPNZ ? 3 /* sd */ : 3975 !!(s->prefix & PREFIX_DATA) /* pd */ + (s->vex_l << 2); 3976 3977 gen_helper_cmp_funcs[index][b](tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 3978} 3979 3980static void gen_VCOMI(DisasContext *s, X86DecodedInsn *decode) 3981{ 3982 SSEFunc_0_epp fn; 3983 fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss; 3984 fn(tcg_env, OP_PTR1, OP_PTR2); 3985 assume_cc_op(s, CC_OP_EFLAGS); 3986} 3987 3988static void gen_VCVTPD2PS(DisasContext *s, X86DecodedInsn *decode) 3989{ 3990 if (s->vex_l) { 3991 gen_helper_cvtpd2ps_ymm(tcg_env, OP_PTR0, OP_PTR2); 3992 } else { 3993 gen_helper_cvtpd2ps_xmm(tcg_env, OP_PTR0, OP_PTR2); 3994 } 3995} 3996 3997static void gen_VCVTPS2PD(DisasContext *s, X86DecodedInsn *decode) 3998{ 3999 if (s->vex_l) { 4000 gen_helper_cvtps2pd_ymm(tcg_env, OP_PTR0, OP_PTR2); 4001 } else { 4002 gen_helper_cvtps2pd_xmm(tcg_env, OP_PTR0, OP_PTR2); 4003 } 4004} 4005 4006static void gen_VCVTPS2PH(DisasContext *s, X86DecodedInsn *decode) 4007{ 4008 gen_unary_imm_fp_sse(s, decode, 4009 gen_helper_cvtps2ph_xmm, 4010 gen_helper_cvtps2ph_ymm); 4011 /* 4012 * VCVTPS2PH is the only instruction that performs an operation on a 4013 * register source and then *stores* into memory. 4014 */ 4015 if (decode->op[0].has_ea) { 4016 gen_store_sse(s, decode, decode->op[0].offset); 4017 } 4018} 4019 4020static void gen_VCVTSD2SS(DisasContext *s, X86DecodedInsn *decode) 4021{ 4022 gen_helper_cvtsd2ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 4023} 4024 4025static void gen_VCVTSS2SD(DisasContext *s, X86DecodedInsn *decode) 4026{ 4027 gen_helper_cvtss2sd(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 4028} 4029 4030static void gen_VCVTSI2Sx(DisasContext *s, X86DecodedInsn *decode) 4031{ 4032 int vec_len = vector_len(s, decode); 4033 TCGv_i32 in; 4034 4035 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4036 4037#ifdef TARGET_X86_64 4038 MemOp ot = decode->op[2].ot; 4039 if (ot == MO_64) { 4040 if (s->prefix & PREFIX_REPNZ) { 4041 gen_helper_cvtsq2sd(tcg_env, OP_PTR0, s->T1); 4042 } else { 4043 gen_helper_cvtsq2ss(tcg_env, OP_PTR0, s->T1); 4044 } 4045 return; 4046 } 4047 in = s->tmp2_i32; 4048 tcg_gen_trunc_tl_i32(in, s->T1); 4049#else 4050 in = s->T1; 4051#endif 4052 4053 if (s->prefix & PREFIX_REPNZ) { 4054 gen_helper_cvtsi2sd(tcg_env, OP_PTR0, in); 4055 } else { 4056 gen_helper_cvtsi2ss(tcg_env, OP_PTR0, in); 4057 } 4058} 4059 4060static inline void gen_VCVTtSx2SI(DisasContext *s, X86DecodedInsn *decode, 4061 SSEFunc_i_ep ss2si, SSEFunc_l_ep ss2sq, 4062 SSEFunc_i_ep sd2si, SSEFunc_l_ep sd2sq) 4063{ 4064 TCGv_i32 out; 4065 4066#ifdef TARGET_X86_64 4067 MemOp ot = decode->op[0].ot; 4068 if (ot == MO_64) { 4069 if (s->prefix & PREFIX_REPNZ) { 4070 sd2sq(s->T0, tcg_env, OP_PTR2); 4071 } else { 4072 ss2sq(s->T0, tcg_env, OP_PTR2); 4073 } 4074 return; 4075 } 4076 4077 out = s->tmp2_i32; 4078#else 4079 out = s->T0; 4080#endif 4081 if (s->prefix & PREFIX_REPNZ) { 4082 sd2si(out, tcg_env, OP_PTR2); 4083 } else { 4084 ss2si(out, tcg_env, OP_PTR2); 4085 } 4086#ifdef TARGET_X86_64 4087 tcg_gen_extu_i32_tl(s->T0, out); 4088#endif 4089} 4090 4091#ifndef TARGET_X86_64 4092#define gen_helper_cvtss2sq NULL 4093#define gen_helper_cvtsd2sq NULL 4094#define gen_helper_cvttss2sq NULL 4095#define gen_helper_cvttsd2sq NULL 4096#endif 4097 4098static void gen_VCVTSx2SI(DisasContext *s, X86DecodedInsn *decode) 4099{ 4100 gen_VCVTtSx2SI(s, decode, 4101 gen_helper_cvtss2si, gen_helper_cvtss2sq, 4102 gen_helper_cvtsd2si, gen_helper_cvtsd2sq); 4103} 4104 4105static void gen_VCVTTSx2SI(DisasContext *s, X86DecodedInsn *decode) 4106{ 4107 gen_VCVTtSx2SI(s, decode, 4108 gen_helper_cvttss2si, gen_helper_cvttss2sq, 4109 gen_helper_cvttsd2si, gen_helper_cvttsd2sq); 4110} 4111 4112static void gen_VEXTRACTx128(DisasContext *s, X86DecodedInsn *decode) 4113{ 4114 int mask = decode->immediate & 1; 4115 int src_ofs = vector_elem_offset(&decode->op[1], MO_128, mask); 4116 if (decode->op[0].has_ea) { 4117 /* VEX-only instruction, no alignment requirements. */ 4118 gen_sto_env_A0(s, src_ofs, false); 4119 } else { 4120 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, 16, 16); 4121 } 4122} 4123 4124static void gen_VEXTRACTPS(DisasContext *s, X86DecodedInsn *decode) 4125{ 4126 gen_pextr(s, decode, MO_32); 4127} 4128 4129static void gen_vinsertps(DisasContext *s, X86DecodedInsn *decode) 4130{ 4131 int val = decode->immediate; 4132 int dest_word = (val >> 4) & 3; 4133 int new_mask = (val & 15) | (1 << dest_word); 4134 int vec_len = 16; 4135 4136 assert(!s->vex_l); 4137 4138 if (new_mask == 15) { 4139 /* All zeroes except possibly for the inserted element */ 4140 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 4141 } else if (decode->op[1].offset != decode->op[0].offset) { 4142 gen_store_sse(s, decode, decode->op[1].offset); 4143 } 4144 4145 if (new_mask != (val & 15)) { 4146 tcg_gen_st_i32(s->tmp2_i32, tcg_env, 4147 vector_elem_offset(&decode->op[0], MO_32, dest_word)); 4148 } 4149 4150 if (new_mask != 15) { 4151 TCGv_i32 zero = tcg_constant_i32(0); /* float32_zero */ 4152 int i; 4153 for (i = 0; i < 4; i++) { 4154 if ((val >> i) & 1) { 4155 tcg_gen_st_i32(zero, tcg_env, 4156 vector_elem_offset(&decode->op[0], MO_32, i)); 4157 } 4158 } 4159 } 4160} 4161 4162static void gen_VINSERTPS_r(DisasContext *s, X86DecodedInsn *decode) 4163{ 4164 int val = decode->immediate; 4165 tcg_gen_ld_i32(s->tmp2_i32, tcg_env, 4166 vector_elem_offset(&decode->op[2], MO_32, (val >> 6) & 3)); 4167 gen_vinsertps(s, decode); 4168} 4169 4170static void gen_VINSERTPS_m(DisasContext *s, X86DecodedInsn *decode) 4171{ 4172 tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4173 gen_vinsertps(s, decode); 4174} 4175 4176static void gen_VINSERTx128(DisasContext *s, X86DecodedInsn *decode) 4177{ 4178 int mask = decode->immediate & 1; 4179 tcg_gen_gvec_mov(MO_64, 4180 decode->op[0].offset + offsetof(YMMReg, YMM_X(mask)), 4181 decode->op[2].offset + offsetof(YMMReg, YMM_X(0)), 16, 16); 4182 tcg_gen_gvec_mov(MO_64, 4183 decode->op[0].offset + offsetof(YMMReg, YMM_X(!mask)), 4184 decode->op[1].offset + offsetof(YMMReg, YMM_X(!mask)), 16, 16); 4185} 4186 4187static inline void gen_maskmov(DisasContext *s, X86DecodedInsn *decode, 4188 SSEFunc_0_eppt xmm, SSEFunc_0_eppt ymm) 4189{ 4190 if (!s->vex_l) { 4191 xmm(tcg_env, OP_PTR2, OP_PTR1, s->A0); 4192 } else { 4193 ymm(tcg_env, OP_PTR2, OP_PTR1, s->A0); 4194 } 4195} 4196 4197static void gen_VMASKMOVPD_st(DisasContext *s, X86DecodedInsn *decode) 4198{ 4199 gen_maskmov(s, decode, gen_helper_vpmaskmovq_st_xmm, gen_helper_vpmaskmovq_st_ymm); 4200} 4201 4202static void gen_VMASKMOVPS_st(DisasContext *s, X86DecodedInsn *decode) 4203{ 4204 gen_maskmov(s, decode, gen_helper_vpmaskmovd_st_xmm, gen_helper_vpmaskmovd_st_ymm); 4205} 4206 4207static void gen_VMOVHPx_ld(DisasContext *s, X86DecodedInsn *decode) 4208{ 4209 gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4210 if (decode->op[0].offset != decode->op[1].offset) { 4211 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4212 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4213 } 4214} 4215 4216static void gen_VMOVHPx_st(DisasContext *s, X86DecodedInsn *decode) 4217{ 4218 gen_stq_env_A0(s, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4219} 4220 4221static void gen_VMOVHPx(DisasContext *s, X86DecodedInsn *decode) 4222{ 4223 if (decode->op[0].offset != decode->op[2].offset) { 4224 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4225 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4226 } 4227 if (decode->op[0].offset != decode->op[1].offset) { 4228 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4229 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4230 } 4231} 4232 4233static void gen_VMOVHLPS(DisasContext *s, X86DecodedInsn *decode) 4234{ 4235 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4236 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4237 if (decode->op[0].offset != decode->op[1].offset) { 4238 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1))); 4239 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4240 } 4241} 4242 4243static void gen_VMOVLHPS(DisasContext *s, X86DecodedInsn *decode) 4244{ 4245 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset); 4246 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4247 if (decode->op[0].offset != decode->op[1].offset) { 4248 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4249 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4250 } 4251} 4252 4253/* 4254 * Note that MOVLPx supports 256-bit operation unlike MOVHLPx, MOVLHPx, MOXHPx. 4255 * Use a gvec move to move everything above the bottom 64 bits. 4256 */ 4257 4258static void gen_VMOVLPx(DisasContext *s, X86DecodedInsn *decode) 4259{ 4260 int vec_len = vector_len(s, decode); 4261 4262 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0))); 4263 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4264 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4265} 4266 4267static void gen_VMOVLPx_ld(DisasContext *s, X86DecodedInsn *decode) 4268{ 4269 int vec_len = vector_len(s, decode); 4270 4271 tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4272 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4273 tcg_gen_st_i64(s->tmp1_i64, OP_PTR0, offsetof(ZMMReg, ZMM_Q(0))); 4274} 4275 4276static void gen_VMOVLPx_st(DisasContext *s, X86DecodedInsn *decode) 4277{ 4278 tcg_gen_ld_i64(s->tmp1_i64, OP_PTR2, offsetof(ZMMReg, ZMM_Q(0))); 4279 tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4280} 4281 4282static void gen_VMOVSD_ld(DisasContext *s, X86DecodedInsn *decode) 4283{ 4284 TCGv_i64 zero = tcg_constant_i64(0); 4285 4286 tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4287 tcg_gen_st_i64(zero, OP_PTR0, offsetof(ZMMReg, ZMM_Q(1))); 4288 tcg_gen_st_i64(s->tmp1_i64, OP_PTR0, offsetof(ZMMReg, ZMM_Q(0))); 4289} 4290 4291static void gen_VMOVSS(DisasContext *s, X86DecodedInsn *decode) 4292{ 4293 int vec_len = vector_len(s, decode); 4294 4295 tcg_gen_ld_i32(s->tmp2_i32, OP_PTR2, offsetof(ZMMReg, ZMM_L(0))); 4296 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4297 tcg_gen_st_i32(s->tmp2_i32, OP_PTR0, offsetof(ZMMReg, ZMM_L(0))); 4298} 4299 4300static void gen_VMOVSS_ld(DisasContext *s, X86DecodedInsn *decode) 4301{ 4302 int vec_len = vector_len(s, decode); 4303 4304 tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4305 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 4306 tcg_gen_st_i32(s->tmp2_i32, OP_PTR0, offsetof(ZMMReg, ZMM_L(0))); 4307} 4308 4309static void gen_VMOVSS_st(DisasContext *s, X86DecodedInsn *decode) 4310{ 4311 tcg_gen_ld_i32(s->tmp2_i32, OP_PTR2, offsetof(ZMMReg, ZMM_L(0))); 4312 tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4313} 4314 4315static void gen_VPMASKMOV_st(DisasContext *s, X86DecodedInsn *decode) 4316{ 4317 if (s->vex_w) { 4318 gen_VMASKMOVPD_st(s, decode); 4319 } else { 4320 gen_VMASKMOVPS_st(s, decode); 4321 } 4322} 4323 4324static void gen_VPERMD(DisasContext *s, X86DecodedInsn *decode) 4325{ 4326 assert(s->vex_l); 4327 gen_helper_vpermd_ymm(OP_PTR0, OP_PTR1, OP_PTR2); 4328} 4329 4330static void gen_VPERM2x128(DisasContext *s, X86DecodedInsn *decode) 4331{ 4332 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4333 assert(s->vex_l); 4334 gen_helper_vpermdq_ymm(OP_PTR0, OP_PTR1, OP_PTR2, imm); 4335} 4336 4337static void gen_VPHMINPOSUW(DisasContext *s, X86DecodedInsn *decode) 4338{ 4339 assert(!s->vex_l); 4340 gen_helper_phminposuw_xmm(tcg_env, OP_PTR0, OP_PTR2); 4341} 4342 4343static void gen_VROUNDSD(DisasContext *s, X86DecodedInsn *decode) 4344{ 4345 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4346 assert(!s->vex_l); 4347 gen_helper_roundsd_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 4348} 4349 4350static void gen_VROUNDSS(DisasContext *s, X86DecodedInsn *decode) 4351{ 4352 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4353 assert(!s->vex_l); 4354 gen_helper_roundss_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 4355} 4356 4357static void gen_VSHUF(DisasContext *s, X86DecodedInsn *decode) 4358{ 4359 TCGv_i32 imm = tcg_constant_i32(decode->immediate); 4360 SSEFunc_0_pppi ps, pd, fn; 4361 ps = s->vex_l ? gen_helper_shufps_ymm : gen_helper_shufps_xmm; 4362 pd = s->vex_l ? gen_helper_shufpd_ymm : gen_helper_shufpd_xmm; 4363 fn = s->prefix & PREFIX_DATA ? pd : ps; 4364 fn(OP_PTR0, OP_PTR1, OP_PTR2, imm); 4365} 4366 4367static void gen_VUCOMI(DisasContext *s, X86DecodedInsn *decode) 4368{ 4369 SSEFunc_0_epp fn; 4370 fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss; 4371 fn(tcg_env, OP_PTR1, OP_PTR2); 4372 assume_cc_op(s, CC_OP_EFLAGS); 4373} 4374 4375static void gen_VZEROALL(DisasContext *s, X86DecodedInsn *decode) 4376{ 4377 TCGv_ptr ptr = tcg_temp_new_ptr(); 4378 4379 tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_regs)); 4380 gen_helper_memset(ptr, ptr, tcg_constant_i32(0), 4381 tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg))); 4382} 4383 4384static void gen_VZEROUPPER(DisasContext *s, X86DecodedInsn *decode) 4385{ 4386 int i; 4387 4388 for (i = 0; i < CPU_NB_REGS; i++) { 4389 int offset = offsetof(CPUX86State, xmm_regs[i].ZMM_X(1)); 4390 tcg_gen_gvec_dup_imm(MO_64, offset, 16, 16, 0); 4391 } 4392} 4393 4394static void gen_WAIT(DisasContext *s, X86DecodedInsn *decode) 4395{ 4396 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == (HF_MP_MASK | HF_TS_MASK)) { 4397 gen_NM_exception(s); 4398 } else { 4399 /* needs to be treated as I/O because of ferr_irq */ 4400 translator_io_start(&s->base); 4401 gen_helper_fwait(tcg_env); 4402 } 4403} 4404 4405#ifndef CONFIG_USER_ONLY 4406static void gen_WRMSR(DisasContext *s, X86DecodedInsn *decode) 4407{ 4408 gen_update_cc_op(s); 4409 gen_update_eip_cur(s); 4410 gen_helper_wrmsr(tcg_env); 4411 s->base.is_jmp = DISAS_EOB_NEXT; 4412} 4413#else 4414#define gen_WRMSR gen_unreachable 4415#endif 4416 4417static void gen_WRxxBASE(DisasContext *s, X86DecodedInsn *decode) 4418{ 4419 TCGv base = cpu_seg_base[s->modrm & 8 ? R_GS : R_FS]; 4420 4421 /* Preserve hflags bits by testing CR4 at runtime. */ 4422 gen_helper_cr4_testbit(tcg_env, tcg_constant_i32(CR4_FSGSBASE_MASK)); 4423 tcg_gen_mov_tl(base, s->T0); 4424} 4425 4426static void gen_XADD(DisasContext *s, X86DecodedInsn *decode) 4427{ 4428 MemOp ot = decode->op[1].ot; 4429 4430 decode->cc_dst = tcg_temp_new(); 4431 decode->cc_src = s->T1; 4432 decode->cc_op = CC_OP_ADDB + ot; 4433 4434 if (s->prefix & PREFIX_LOCK) { 4435 tcg_gen_atomic_fetch_add_tl(s->T0, s->A0, s->T1, s->mem_index, ot | MO_LE); 4436 tcg_gen_add_tl(decode->cc_dst, s->T0, s->T1); 4437 } else { 4438 tcg_gen_add_tl(decode->cc_dst, s->T0, s->T1); 4439 /* 4440 * NOTE: writing memory first is important for MMU exceptions, 4441 * but "new result" wins for XADD AX, AX. 4442 */ 4443 gen_writeback(s, decode, 0, decode->cc_dst); 4444 } 4445 if (decode->op[0].has_ea || decode->op[2].n != decode->op[0].n) { 4446 gen_writeback(s, decode, 2, s->T0); 4447 } 4448} 4449 4450static void gen_XCHG(DisasContext *s, X86DecodedInsn *decode) 4451{ 4452 if (s->prefix & PREFIX_LOCK) { 4453 tcg_gen_atomic_xchg_tl(s->T0, s->A0, s->T1, 4454 s->mem_index, decode->op[0].ot | MO_LE); 4455 /* now store old value into register operand */ 4456 gen_op_mov_reg_v(s, decode->op[2].ot, decode->op[2].n, s->T0); 4457 } else { 4458 /* move destination value into source operand, source preserved in T1 */ 4459 gen_op_mov_reg_v(s, decode->op[2].ot, decode->op[2].n, s->T0); 4460 tcg_gen_mov_tl(s->T0, s->T1); 4461 } 4462} 4463 4464static void gen_XLAT(DisasContext *s, X86DecodedInsn *decode) 4465{ 4466 /* AL is already zero-extended into s->T0. */ 4467 tcg_gen_add_tl(s->A0, cpu_regs[R_EBX], s->T0); 4468 gen_lea_v_seg(s, s->A0, R_DS, s->override); 4469 gen_op_ld_v(s, MO_8, s->T0, s->A0); 4470} 4471 4472static void gen_XOR(DisasContext *s, X86DecodedInsn *decode) 4473{ 4474 /* special case XOR reg, reg */ 4475 if (decode->op[1].unit == X86_OP_INT && 4476 decode->op[2].unit == X86_OP_INT && 4477 decode->op[1].n == decode->op[2].n) { 4478 tcg_gen_movi_tl(s->T0, 0); 4479 decode->cc_op = CC_OP_CLR; 4480 } else { 4481 MemOp ot = decode->op[1].ot; 4482 4483 if (s->prefix & PREFIX_LOCK) { 4484 tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T1, 4485 s->mem_index, ot | MO_LE); 4486 } else { 4487 tcg_gen_xor_tl(s->T0, s->T0, s->T1); 4488 } 4489 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 4490 } 4491} 4492 4493static void gen_XRSTOR(DisasContext *s, X86DecodedInsn *decode) 4494{ 4495 TCGv_i64 features = tcg_temp_new_i64(); 4496 4497 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4498 gen_helper_xrstor(tcg_env, s->A0, features); 4499 if (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_MPX) { 4500 /* 4501 * XRSTOR is how MPX is enabled, which changes how 4502 * we translate. Thus we need to end the TB. 4503 */ 4504 s->base.is_jmp = DISAS_EOB_NEXT; 4505 } 4506} 4507 4508static void gen_XSAVE(DisasContext *s, X86DecodedInsn *decode) 4509{ 4510 TCGv_i64 features = tcg_temp_new_i64(); 4511 4512 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4513 gen_helper_xsave(tcg_env, s->A0, features); 4514} 4515 4516static void gen_XSAVEOPT(DisasContext *s, X86DecodedInsn *decode) 4517{ 4518 TCGv_i64 features = tcg_temp_new_i64(); 4519 4520 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4521 gen_helper_xsave(tcg_env, s->A0, features); 4522} 4523