1/* 2 * New-style TCG opcode generator for i386 instructions 3 * 4 * Copyright (c) 2022 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22/* 23 * Sometimes, knowing what the backend has can produce better code. 24 * The exact opcode to check depends on 32- vs. 64-bit. 25 */ 26#ifdef TARGET_X86_64 27#define INDEX_op_extract2_tl INDEX_op_extract2_i64 28#else 29#define INDEX_op_extract2_tl INDEX_op_extract2_i32 30#endif 31 32#define MMX_OFFSET(reg) \ 33 ({ assert((reg) >= 0 && (reg) <= 7); \ 34 offsetof(CPUX86State, fpregs[reg].mmx); }) 35 36#define ZMM_OFFSET(reg) \ 37 ({ assert((reg) >= 0 && (reg) <= 15); \ 38 offsetof(CPUX86State, xmm_regs[reg]); }) 39 40typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); 41typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); 42typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); 43typedef void (*SSEFunc_0_eppp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 44 TCGv_ptr reg_c); 45typedef void (*SSEFunc_0_epppp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 46 TCGv_ptr reg_c, TCGv_ptr reg_d); 47typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 48 TCGv_i32 val); 49typedef void (*SSEFunc_0_epppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 50 TCGv_ptr reg_c, TCGv_i32 val); 51typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); 52typedef void (*SSEFunc_0_pppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_ptr reg_c, 53 TCGv_i32 val); 54typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 55 TCGv val); 56typedef void (*SSEFunc_0_epppti)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 57 TCGv_ptr reg_c, TCGv a0, TCGv_i32 scale); 58typedef void (*SSEFunc_0_eppppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 59 TCGv_ptr reg_c, TCGv_ptr reg_d, TCGv_i32 flags); 60typedef void (*SSEFunc_0_eppppii)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 61 TCGv_ptr reg_c, TCGv_ptr reg_d, TCGv_i32 even, 62 TCGv_i32 odd); 63 64static void gen_JMP_m(DisasContext *s, X86DecodedInsn *decode); 65static void gen_JMP(DisasContext *s, X86DecodedInsn *decode); 66 67static inline TCGv_i32 tcg_constant8u_i32(uint8_t val) 68{ 69 return tcg_constant_i32(val); 70} 71 72static void gen_NM_exception(DisasContext *s) 73{ 74 gen_exception(s, EXCP07_PREX); 75} 76 77static void gen_lea_modrm(DisasContext *s, X86DecodedInsn *decode) 78{ 79 AddressParts *mem = &decode->mem; 80 TCGv ea; 81 82 ea = gen_lea_modrm_1(s, *mem, decode->e.vex_class == 12); 83 if (decode->e.special == X86_SPECIAL_BitTest) { 84 MemOp ot = decode->op[1].ot; 85 int poslen = 8 << ot; 86 int opn = decode->op[2].n; 87 TCGv ofs = tcg_temp_new(); 88 89 /* Extract memory displacement from the second operand. */ 90 assert(decode->op[2].unit == X86_OP_INT && decode->op[2].ot != MO_8); 91 tcg_gen_sextract_tl(ofs, cpu_regs[opn], 3, poslen - 3); 92 tcg_gen_andi_tl(ofs, ofs, -1 << ot); 93 tcg_gen_add_tl(s->A0, ea, ofs); 94 ea = s->A0; 95 } 96 97 gen_lea_v_seg(s, ea, mem->def_seg, s->override); 98} 99 100static inline int mmx_offset(MemOp ot) 101{ 102 switch (ot) { 103 case MO_8: 104 return offsetof(MMXReg, MMX_B(0)); 105 case MO_16: 106 return offsetof(MMXReg, MMX_W(0)); 107 case MO_32: 108 return offsetof(MMXReg, MMX_L(0)); 109 case MO_64: 110 return offsetof(MMXReg, MMX_Q(0)); 111 default: 112 g_assert_not_reached(); 113 } 114} 115 116static inline int xmm_offset(MemOp ot) 117{ 118 switch (ot) { 119 case MO_8: 120 return offsetof(ZMMReg, ZMM_B(0)); 121 case MO_16: 122 return offsetof(ZMMReg, ZMM_W(0)); 123 case MO_32: 124 return offsetof(ZMMReg, ZMM_L(0)); 125 case MO_64: 126 return offsetof(ZMMReg, ZMM_Q(0)); 127 case MO_128: 128 return offsetof(ZMMReg, ZMM_X(0)); 129 case MO_256: 130 return offsetof(ZMMReg, ZMM_Y(0)); 131 default: 132 g_assert_not_reached(); 133 } 134} 135 136static int vector_reg_offset(X86DecodedOp *op) 137{ 138 assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE); 139 140 if (op->unit == X86_OP_MMX) { 141 return op->offset - mmx_offset(op->ot); 142 } else { 143 return op->offset - xmm_offset(op->ot); 144 } 145} 146 147static int vector_elem_offset(X86DecodedOp *op, MemOp ot, int n) 148{ 149 int base_ofs = vector_reg_offset(op); 150 switch(ot) { 151 case MO_8: 152 if (op->unit == X86_OP_MMX) { 153 return base_ofs + offsetof(MMXReg, MMX_B(n)); 154 } else { 155 return base_ofs + offsetof(ZMMReg, ZMM_B(n)); 156 } 157 case MO_16: 158 if (op->unit == X86_OP_MMX) { 159 return base_ofs + offsetof(MMXReg, MMX_W(n)); 160 } else { 161 return base_ofs + offsetof(ZMMReg, ZMM_W(n)); 162 } 163 case MO_32: 164 if (op->unit == X86_OP_MMX) { 165 return base_ofs + offsetof(MMXReg, MMX_L(n)); 166 } else { 167 return base_ofs + offsetof(ZMMReg, ZMM_L(n)); 168 } 169 case MO_64: 170 if (op->unit == X86_OP_MMX) { 171 return base_ofs; 172 } else { 173 return base_ofs + offsetof(ZMMReg, ZMM_Q(n)); 174 } 175 case MO_128: 176 assert(op->unit == X86_OP_SSE); 177 return base_ofs + offsetof(ZMMReg, ZMM_X(n)); 178 case MO_256: 179 assert(op->unit == X86_OP_SSE); 180 return base_ofs + offsetof(ZMMReg, ZMM_Y(n)); 181 default: 182 g_assert_not_reached(); 183 } 184} 185 186static void compute_mmx_offset(X86DecodedOp *op) 187{ 188 if (!op->has_ea) { 189 op->offset = MMX_OFFSET(op->n) + mmx_offset(op->ot); 190 } else { 191 op->offset = offsetof(CPUX86State, mmx_t0) + mmx_offset(op->ot); 192 } 193} 194 195static void compute_xmm_offset(X86DecodedOp *op) 196{ 197 if (!op->has_ea) { 198 op->offset = ZMM_OFFSET(op->n) + xmm_offset(op->ot); 199 } else { 200 op->offset = offsetof(CPUX86State, xmm_t0) + xmm_offset(op->ot); 201 } 202} 203 204static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs, bool aligned) 205{ 206 switch(ot) { 207 case MO_8: 208 gen_op_ld_v(s, MO_8, temp, s->A0); 209 tcg_gen_st8_tl(temp, tcg_env, dest_ofs); 210 break; 211 case MO_16: 212 gen_op_ld_v(s, MO_16, temp, s->A0); 213 tcg_gen_st16_tl(temp, tcg_env, dest_ofs); 214 break; 215 case MO_32: 216 gen_op_ld_v(s, MO_32, temp, s->A0); 217 tcg_gen_st32_tl(temp, tcg_env, dest_ofs); 218 break; 219 case MO_64: 220 gen_ldq_env_A0(s, dest_ofs); 221 break; 222 case MO_128: 223 gen_ldo_env_A0(s, dest_ofs, aligned); 224 break; 225 case MO_256: 226 gen_ldy_env_A0(s, dest_ofs, aligned); 227 break; 228 default: 229 g_assert_not_reached(); 230 } 231} 232 233static bool sse_needs_alignment(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 234{ 235 switch (decode->e.vex_class) { 236 case 2: 237 case 4: 238 if ((s->prefix & PREFIX_VEX) || 239 decode->e.vex_special == X86_VEX_SSEUnaligned) { 240 /* MOST legacy SSE instructions require aligned memory operands, but not all. */ 241 return false; 242 } 243 /* fall through */ 244 case 1: 245 return ot >= MO_128; 246 247 default: 248 return false; 249 } 250} 251 252static void gen_load(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v) 253{ 254 X86DecodedOp *op = &decode->op[opn]; 255 256 switch (op->unit) { 257 case X86_OP_SKIP: 258 return; 259 case X86_OP_SEG: 260 tcg_gen_ld32u_tl(v, tcg_env, 261 offsetof(CPUX86State,segs[op->n].selector)); 262 break; 263#ifndef CONFIG_USER_ONLY 264 case X86_OP_CR: 265 if (op->n == 8) { 266 translator_io_start(&s->base); 267 gen_helper_read_cr8(v, tcg_env); 268 } else { 269 tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, cr[op->n])); 270 } 271 break; 272 case X86_OP_DR: 273 /* CR4.DE tested in the helper. */ 274 gen_helper_get_dr(v, tcg_env, tcg_constant_i32(op->n)); 275 break; 276#endif 277 case X86_OP_INT: 278 if (op->has_ea) { 279 if (v == s->T0 && decode->e.special == X86_SPECIAL_SExtT0) { 280 gen_op_ld_v(s, op->ot | MO_SIGN, v, s->A0); 281 } else { 282 gen_op_ld_v(s, op->ot, v, s->A0); 283 } 284 285 } else if (op->ot < MO_TL && v == s->T0 && 286 (decode->e.special == X86_SPECIAL_SExtT0 || 287 decode->e.special == X86_SPECIAL_ZExtT0)) { 288 if (op->ot == MO_8 && byte_reg_is_xH(s, op->n)) { 289 if (decode->e.special == X86_SPECIAL_SExtT0) { 290 tcg_gen_sextract_tl(v, cpu_regs[op->n - 4], 8, 8); 291 } else { 292 tcg_gen_extract_tl(v, cpu_regs[op->n - 4], 8, 8); 293 } 294 } else { 295 if (decode->e.special == X86_SPECIAL_SExtT0) { 296 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot | MO_SIGN); 297 } else { 298 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot); 299 } 300 } 301 302 } else { 303 gen_op_mov_v_reg(s, op->ot, v, op->n); 304 } 305 break; 306 case X86_OP_IMM: 307 tcg_gen_movi_tl(v, op->imm); 308 break; 309 310 case X86_OP_MMX: 311 compute_mmx_offset(op); 312 goto load_vector; 313 314 case X86_OP_SSE: 315 compute_xmm_offset(op); 316 load_vector: 317 if (op->has_ea) { 318 bool aligned = sse_needs_alignment(s, decode, op->ot); 319 gen_load_sse(s, v, op->ot, op->offset, aligned); 320 } 321 break; 322 323 default: 324 g_assert_not_reached(); 325 } 326} 327 328static TCGv_ptr op_ptr(X86DecodedInsn *decode, int opn) 329{ 330 X86DecodedOp *op = &decode->op[opn]; 331 332 assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE); 333 if (op->v_ptr) { 334 return op->v_ptr; 335 } 336 op->v_ptr = tcg_temp_new_ptr(); 337 338 /* The temporary points to the MMXReg or ZMMReg. */ 339 tcg_gen_addi_ptr(op->v_ptr, tcg_env, vector_reg_offset(op)); 340 return op->v_ptr; 341} 342 343#define OP_PTR0 op_ptr(decode, 0) 344#define OP_PTR1 op_ptr(decode, 1) 345#define OP_PTR2 op_ptr(decode, 2) 346 347static void gen_writeback(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v) 348{ 349 X86DecodedOp *op = &decode->op[opn]; 350 switch (op->unit) { 351 case X86_OP_SKIP: 352 break; 353 case X86_OP_SEG: 354 /* Note that gen_movl_seg takes care of interrupt shadow and TF. */ 355 gen_movl_seg(s, op->n, s->T0); 356 break; 357 case X86_OP_INT: 358 if (op->has_ea) { 359 gen_op_st_v(s, op->ot, v, s->A0); 360 } else { 361 gen_op_mov_reg_v(s, op->ot, op->n, v); 362 } 363 break; 364 case X86_OP_MMX: 365 break; 366 case X86_OP_SSE: 367 if (!op->has_ea && (s->prefix & PREFIX_VEX) && op->ot <= MO_128) { 368 tcg_gen_gvec_dup_imm(MO_64, 369 offsetof(CPUX86State, xmm_regs[op->n].ZMM_X(1)), 370 16, 16, 0); 371 } 372 break; 373#ifndef CONFIG_USER_ONLY 374 case X86_OP_CR: 375 if (op->n == 8) { 376 translator_io_start(&s->base); 377 } 378 gen_helper_write_crN(tcg_env, tcg_constant_i32(op->n), v); 379 s->base.is_jmp = DISAS_EOB_NEXT; 380 break; 381 case X86_OP_DR: 382 /* CR4.DE tested in the helper. */ 383 gen_helper_set_dr(tcg_env, tcg_constant_i32(op->n), v); 384 s->base.is_jmp = DISAS_EOB_NEXT; 385 break; 386#endif 387 default: 388 g_assert_not_reached(); 389 } 390 op->unit = X86_OP_SKIP; 391} 392 393static inline int vector_len(DisasContext *s, X86DecodedInsn *decode) 394{ 395 if (decode->e.special == X86_SPECIAL_MMX && 396 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 397 return 8; 398 } 399 return s->vex_l ? 32 : 16; 400} 401 402static void prepare_update1_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op) 403{ 404 decode->cc_dst = s->T0; 405 decode->cc_op = op; 406} 407 408static void prepare_update2_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op) 409{ 410 decode->cc_src = s->T1; 411 decode->cc_dst = s->T0; 412 decode->cc_op = op; 413} 414 415static void prepare_update_cc_incdec(X86DecodedInsn *decode, DisasContext *s, CCOp op) 416{ 417 gen_compute_eflags_c(s, s->T1); 418 prepare_update2_cc(decode, s, op); 419} 420 421static void prepare_update3_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op, TCGv reg) 422{ 423 decode->cc_src2 = reg; 424 decode->cc_src = s->T1; 425 decode->cc_dst = s->T0; 426 decode->cc_op = op; 427} 428 429/* Set up decode->cc_* to modify CF while keeping other flags unchanged. */ 430static void prepare_update_cf(X86DecodedInsn *decode, DisasContext *s, TCGv cf) 431{ 432 switch (s->cc_op) { 433 case CC_OP_ADOX: 434 case CC_OP_ADCOX: 435 decode->cc_src2 = cpu_cc_src2; 436 decode->cc_src = cpu_cc_src; 437 decode->cc_op = CC_OP_ADCOX; 438 break; 439 440 case CC_OP_EFLAGS: 441 case CC_OP_ADCX: 442 decode->cc_src = cpu_cc_src; 443 decode->cc_op = CC_OP_ADCX; 444 break; 445 446 default: 447 decode->cc_src = tcg_temp_new(); 448 gen_mov_eflags(s, decode->cc_src); 449 decode->cc_op = CC_OP_ADCX; 450 break; 451 } 452 decode->cc_dst = cf; 453} 454 455static void gen_store_sse(DisasContext *s, X86DecodedInsn *decode, int src_ofs) 456{ 457 MemOp ot = decode->op[0].ot; 458 int vec_len = vector_len(s, decode); 459 bool aligned = sse_needs_alignment(s, decode, ot); 460 461 if (!decode->op[0].has_ea) { 462 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, vec_len, vec_len); 463 return; 464 } 465 466 switch (ot) { 467 case MO_64: 468 gen_stq_env_A0(s, src_ofs); 469 break; 470 case MO_128: 471 gen_sto_env_A0(s, src_ofs, aligned); 472 break; 473 case MO_256: 474 gen_sty_env_A0(s, src_ofs, aligned); 475 break; 476 default: 477 g_assert_not_reached(); 478 } 479} 480 481static void gen_helper_pavgusb(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b) 482{ 483 gen_helper_pavgb_mmx(env, reg_a, reg_a, reg_b); 484} 485 486#define FN_3DNOW_MOVE ((SSEFunc_0_epp) (uintptr_t) 1) 487static const SSEFunc_0_epp fns_3dnow[] = { 488 [0x0c] = gen_helper_pi2fw, 489 [0x0d] = gen_helper_pi2fd, 490 [0x1c] = gen_helper_pf2iw, 491 [0x1d] = gen_helper_pf2id, 492 [0x8a] = gen_helper_pfnacc, 493 [0x8e] = gen_helper_pfpnacc, 494 [0x90] = gen_helper_pfcmpge, 495 [0x94] = gen_helper_pfmin, 496 [0x96] = gen_helper_pfrcp, 497 [0x97] = gen_helper_pfrsqrt, 498 [0x9a] = gen_helper_pfsub, 499 [0x9e] = gen_helper_pfadd, 500 [0xa0] = gen_helper_pfcmpgt, 501 [0xa4] = gen_helper_pfmax, 502 [0xa6] = FN_3DNOW_MOVE, /* PFRCPIT1; no need to actually increase precision */ 503 [0xa7] = FN_3DNOW_MOVE, /* PFRSQIT1 */ 504 [0xb6] = FN_3DNOW_MOVE, /* PFRCPIT2 */ 505 [0xaa] = gen_helper_pfsubr, 506 [0xae] = gen_helper_pfacc, 507 [0xb0] = gen_helper_pfcmpeq, 508 [0xb4] = gen_helper_pfmul, 509 [0xb7] = gen_helper_pmulhrw_mmx, 510 [0xbb] = gen_helper_pswapd, 511 [0xbf] = gen_helper_pavgusb, 512}; 513 514static void gen_3dnow(DisasContext *s, X86DecodedInsn *decode) 515{ 516 uint8_t b = decode->immediate; 517 SSEFunc_0_epp fn = b < ARRAY_SIZE(fns_3dnow) ? fns_3dnow[b] : NULL; 518 519 if (!fn) { 520 gen_illegal_opcode(s); 521 return; 522 } 523 if (s->flags & HF_TS_MASK) { 524 gen_NM_exception(s); 525 return; 526 } 527 if (s->flags & HF_EM_MASK) { 528 gen_illegal_opcode(s); 529 return; 530 } 531 532 gen_helper_enter_mmx(tcg_env); 533 if (fn == FN_3DNOW_MOVE) { 534 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset); 535 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset); 536 } else { 537 fn(tcg_env, OP_PTR0, OP_PTR1); 538 } 539} 540 541/* 542 * 00 = v*ps Vps, Hps, Wpd 543 * 66 = v*pd Vpd, Hpd, Wps 544 * f3 = v*ss Vss, Hss, Wps 545 * f2 = v*sd Vsd, Hsd, Wps 546 */ 547static inline void gen_unary_fp_sse(DisasContext *s, X86DecodedInsn *decode, 548 SSEFunc_0_epp pd_xmm, SSEFunc_0_epp ps_xmm, 549 SSEFunc_0_epp pd_ymm, SSEFunc_0_epp ps_ymm, 550 SSEFunc_0_eppp sd, SSEFunc_0_eppp ss) 551{ 552 if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) { 553 SSEFunc_0_eppp fn = s->prefix & PREFIX_REPZ ? ss : sd; 554 if (!fn) { 555 gen_illegal_opcode(s); 556 return; 557 } 558 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 559 } else { 560 SSEFunc_0_epp ps, pd, fn; 561 ps = s->vex_l ? ps_ymm : ps_xmm; 562 pd = s->vex_l ? pd_ymm : pd_xmm; 563 fn = s->prefix & PREFIX_DATA ? pd : ps; 564 if (!fn) { 565 gen_illegal_opcode(s); 566 return; 567 } 568 fn(tcg_env, OP_PTR0, OP_PTR2); 569 } 570} 571#define UNARY_FP_SSE(uname, lname) \ 572static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 573{ \ 574 gen_unary_fp_sse(s, decode, \ 575 gen_helper_##lname##pd_xmm, \ 576 gen_helper_##lname##ps_xmm, \ 577 gen_helper_##lname##pd_ymm, \ 578 gen_helper_##lname##ps_ymm, \ 579 gen_helper_##lname##sd, \ 580 gen_helper_##lname##ss); \ 581} 582UNARY_FP_SSE(VSQRT, sqrt) 583 584/* 585 * 00 = v*ps Vps, Hps, Wpd 586 * 66 = v*pd Vpd, Hpd, Wps 587 * f3 = v*ss Vss, Hss, Wps 588 * f2 = v*sd Vsd, Hsd, Wps 589 */ 590static inline void gen_fp_sse(DisasContext *s, X86DecodedInsn *decode, 591 SSEFunc_0_eppp pd_xmm, SSEFunc_0_eppp ps_xmm, 592 SSEFunc_0_eppp pd_ymm, SSEFunc_0_eppp ps_ymm, 593 SSEFunc_0_eppp sd, SSEFunc_0_eppp ss) 594{ 595 SSEFunc_0_eppp ps, pd, fn; 596 if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) { 597 fn = s->prefix & PREFIX_REPZ ? ss : sd; 598 } else { 599 ps = s->vex_l ? ps_ymm : ps_xmm; 600 pd = s->vex_l ? pd_ymm : pd_xmm; 601 fn = s->prefix & PREFIX_DATA ? pd : ps; 602 } 603 if (fn) { 604 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 605 } else { 606 gen_illegal_opcode(s); 607 } 608} 609 610#define FP_SSE(uname, lname) \ 611static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 612{ \ 613 gen_fp_sse(s, decode, \ 614 gen_helper_##lname##pd_xmm, \ 615 gen_helper_##lname##ps_xmm, \ 616 gen_helper_##lname##pd_ymm, \ 617 gen_helper_##lname##ps_ymm, \ 618 gen_helper_##lname##sd, \ 619 gen_helper_##lname##ss); \ 620} 621FP_SSE(VADD, add) 622FP_SSE(VMUL, mul) 623FP_SSE(VSUB, sub) 624FP_SSE(VMIN, min) 625FP_SSE(VDIV, div) 626FP_SSE(VMAX, max) 627 628#define FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, even, odd) \ 629static void gen_##uname##Px(DisasContext *s, X86DecodedInsn *decode) \ 630{ \ 631 SSEFunc_0_eppppii xmm = s->vex_w ? gen_helper_fma4pd_xmm : gen_helper_fma4ps_xmm; \ 632 SSEFunc_0_eppppii ymm = s->vex_w ? gen_helper_fma4pd_ymm : gen_helper_fma4ps_ymm; \ 633 SSEFunc_0_eppppii fn = s->vex_l ? ymm : xmm; \ 634 \ 635 fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \ 636 tcg_constant_i32(even), \ 637 tcg_constant_i32((even) ^ (odd))); \ 638} 639 640#define FMA_SSE(uname, ptr0, ptr1, ptr2, flags) \ 641FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, flags, flags) \ 642static void gen_##uname##Sx(DisasContext *s, X86DecodedInsn *decode) \ 643{ \ 644 SSEFunc_0_eppppi fn = s->vex_w ? gen_helper_fma4sd : gen_helper_fma4ss; \ 645 \ 646 fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \ 647 tcg_constant_i32(flags)); \ 648} \ 649 650FMA_SSE(VFMADD231, OP_PTR1, OP_PTR2, OP_PTR0, 0) 651FMA_SSE(VFMADD213, OP_PTR1, OP_PTR0, OP_PTR2, 0) 652FMA_SSE(VFMADD132, OP_PTR0, OP_PTR2, OP_PTR1, 0) 653 654FMA_SSE(VFNMADD231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_product) 655FMA_SSE(VFNMADD213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_product) 656FMA_SSE(VFNMADD132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_product) 657 658FMA_SSE(VFMSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c) 659FMA_SSE(VFMSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c) 660FMA_SSE(VFMSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c) 661 662FMA_SSE(VFNMSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c|float_muladd_negate_product) 663FMA_SSE(VFNMSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c|float_muladd_negate_product) 664FMA_SSE(VFNMSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c|float_muladd_negate_product) 665 666FMA_SSE_PACKED(VFMADDSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c, 0) 667FMA_SSE_PACKED(VFMADDSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c, 0) 668FMA_SSE_PACKED(VFMADDSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c, 0) 669 670FMA_SSE_PACKED(VFMSUBADD231, OP_PTR1, OP_PTR2, OP_PTR0, 0, float_muladd_negate_c) 671FMA_SSE_PACKED(VFMSUBADD213, OP_PTR1, OP_PTR0, OP_PTR2, 0, float_muladd_negate_c) 672FMA_SSE_PACKED(VFMSUBADD132, OP_PTR0, OP_PTR2, OP_PTR1, 0, float_muladd_negate_c) 673 674#define FP_UNPACK_SSE(uname, lname) \ 675static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 676{ \ 677 /* PS maps to the DQ integer instruction, PD maps to QDQ. */ \ 678 gen_fp_sse(s, decode, \ 679 gen_helper_##lname##qdq_xmm, \ 680 gen_helper_##lname##dq_xmm, \ 681 gen_helper_##lname##qdq_ymm, \ 682 gen_helper_##lname##dq_ymm, \ 683 NULL, NULL); \ 684} 685FP_UNPACK_SSE(VUNPCKLPx, punpckl) 686FP_UNPACK_SSE(VUNPCKHPx, punpckh) 687 688/* 689 * 00 = v*ps Vps, Wpd 690 * f3 = v*ss Vss, Wps 691 */ 692static inline void gen_unary_fp32_sse(DisasContext *s, X86DecodedInsn *decode, 693 SSEFunc_0_epp ps_xmm, 694 SSEFunc_0_epp ps_ymm, 695 SSEFunc_0_eppp ss) 696{ 697 if ((s->prefix & (PREFIX_DATA | PREFIX_REPNZ)) != 0) { 698 goto illegal_op; 699 } else if (s->prefix & PREFIX_REPZ) { 700 if (!ss) { 701 goto illegal_op; 702 } 703 ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 704 } else { 705 SSEFunc_0_epp fn = s->vex_l ? ps_ymm : ps_xmm; 706 if (!fn) { 707 goto illegal_op; 708 } 709 fn(tcg_env, OP_PTR0, OP_PTR2); 710 } 711 return; 712 713illegal_op: 714 gen_illegal_opcode(s); 715} 716#define UNARY_FP32_SSE(uname, lname) \ 717static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 718{ \ 719 gen_unary_fp32_sse(s, decode, \ 720 gen_helper_##lname##ps_xmm, \ 721 gen_helper_##lname##ps_ymm, \ 722 gen_helper_##lname##ss); \ 723} 724UNARY_FP32_SSE(VRSQRT, rsqrt) 725UNARY_FP32_SSE(VRCP, rcp) 726 727/* 728 * 66 = v*pd Vpd, Hpd, Wpd 729 * f2 = v*ps Vps, Hps, Wps 730 */ 731static inline void gen_horizontal_fp_sse(DisasContext *s, X86DecodedInsn *decode, 732 SSEFunc_0_eppp pd_xmm, SSEFunc_0_eppp ps_xmm, 733 SSEFunc_0_eppp pd_ymm, SSEFunc_0_eppp ps_ymm) 734{ 735 SSEFunc_0_eppp ps, pd, fn; 736 ps = s->vex_l ? ps_ymm : ps_xmm; 737 pd = s->vex_l ? pd_ymm : pd_xmm; 738 fn = s->prefix & PREFIX_DATA ? pd : ps; 739 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 740} 741#define HORIZONTAL_FP_SSE(uname, lname) \ 742static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 743{ \ 744 gen_horizontal_fp_sse(s, decode, \ 745 gen_helper_##lname##pd_xmm, gen_helper_##lname##ps_xmm, \ 746 gen_helper_##lname##pd_ymm, gen_helper_##lname##ps_ymm); \ 747} 748HORIZONTAL_FP_SSE(VHADD, hadd) 749HORIZONTAL_FP_SSE(VHSUB, hsub) 750HORIZONTAL_FP_SSE(VADDSUB, addsub) 751 752static inline void gen_ternary_sse(DisasContext *s, X86DecodedInsn *decode, 753 int op3, SSEFunc_0_epppp xmm, SSEFunc_0_epppp ymm) 754{ 755 SSEFunc_0_epppp fn = s->vex_l ? ymm : xmm; 756 TCGv_ptr ptr3 = tcg_temp_new_ptr(); 757 758 /* The format of the fourth input is Lx */ 759 tcg_gen_addi_ptr(ptr3, tcg_env, ZMM_OFFSET(op3)); 760 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3); 761} 762#define TERNARY_SSE(uname, uvname, lname) \ 763static void gen_##uvname(DisasContext *s, X86DecodedInsn *decode) \ 764{ \ 765 gen_ternary_sse(s, decode, (uint8_t)decode->immediate >> 4, \ 766 gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \ 767} \ 768static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 769{ \ 770 gen_ternary_sse(s, decode, 0, \ 771 gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \ 772} 773TERNARY_SSE(BLENDVPS, VBLENDVPS, blendvps) 774TERNARY_SSE(BLENDVPD, VBLENDVPD, blendvpd) 775TERNARY_SSE(PBLENDVB, VPBLENDVB, pblendvb) 776 777static inline void gen_binary_imm_sse(DisasContext *s, X86DecodedInsn *decode, 778 SSEFunc_0_epppi xmm, SSEFunc_0_epppi ymm) 779{ 780 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 781 if (!s->vex_l) { 782 xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 783 } else { 784 ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 785 } 786} 787 788#define BINARY_IMM_SSE(uname, lname) \ 789static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 790{ \ 791 gen_binary_imm_sse(s, decode, \ 792 gen_helper_##lname##_xmm, \ 793 gen_helper_##lname##_ymm); \ 794} 795 796BINARY_IMM_SSE(VBLENDPD, blendpd) 797BINARY_IMM_SSE(VBLENDPS, blendps) 798BINARY_IMM_SSE(VPBLENDW, pblendw) 799BINARY_IMM_SSE(VDDPS, dpps) 800#define gen_helper_dppd_ymm NULL 801BINARY_IMM_SSE(VDDPD, dppd) 802BINARY_IMM_SSE(VMPSADBW, mpsadbw) 803BINARY_IMM_SSE(PCLMULQDQ, pclmulqdq) 804 805 806#define UNARY_INT_GVEC(uname, func, ...) \ 807static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 808{ \ 809 int vec_len = vector_len(s, decode); \ 810 \ 811 func(__VA_ARGS__, decode->op[0].offset, \ 812 decode->op[2].offset, vec_len, vec_len); \ 813} 814UNARY_INT_GVEC(PABSB, tcg_gen_gvec_abs, MO_8) 815UNARY_INT_GVEC(PABSW, tcg_gen_gvec_abs, MO_16) 816UNARY_INT_GVEC(PABSD, tcg_gen_gvec_abs, MO_32) 817UNARY_INT_GVEC(VBROADCASTx128, tcg_gen_gvec_dup_mem, MO_128) 818UNARY_INT_GVEC(VPBROADCASTB, tcg_gen_gvec_dup_mem, MO_8) 819UNARY_INT_GVEC(VPBROADCASTW, tcg_gen_gvec_dup_mem, MO_16) 820UNARY_INT_GVEC(VPBROADCASTD, tcg_gen_gvec_dup_mem, MO_32) 821UNARY_INT_GVEC(VPBROADCASTQ, tcg_gen_gvec_dup_mem, MO_64) 822 823 824#define BINARY_INT_GVEC(uname, func, ...) \ 825static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 826{ \ 827 int vec_len = vector_len(s, decode); \ 828 \ 829 func(__VA_ARGS__, \ 830 decode->op[0].offset, decode->op[1].offset, \ 831 decode->op[2].offset, vec_len, vec_len); \ 832} 833 834BINARY_INT_GVEC(PADDB, tcg_gen_gvec_add, MO_8) 835BINARY_INT_GVEC(PADDW, tcg_gen_gvec_add, MO_16) 836BINARY_INT_GVEC(PADDD, tcg_gen_gvec_add, MO_32) 837BINARY_INT_GVEC(PADDQ, tcg_gen_gvec_add, MO_64) 838BINARY_INT_GVEC(PADDSB, tcg_gen_gvec_ssadd, MO_8) 839BINARY_INT_GVEC(PADDSW, tcg_gen_gvec_ssadd, MO_16) 840BINARY_INT_GVEC(PADDUSB, tcg_gen_gvec_usadd, MO_8) 841BINARY_INT_GVEC(PADDUSW, tcg_gen_gvec_usadd, MO_16) 842BINARY_INT_GVEC(PAND, tcg_gen_gvec_and, MO_64) 843BINARY_INT_GVEC(PCMPEQB, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_8) 844BINARY_INT_GVEC(PCMPEQD, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_32) 845BINARY_INT_GVEC(PCMPEQW, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_16) 846BINARY_INT_GVEC(PCMPEQQ, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_64) 847BINARY_INT_GVEC(PCMPGTB, tcg_gen_gvec_cmp, TCG_COND_GT, MO_8) 848BINARY_INT_GVEC(PCMPGTW, tcg_gen_gvec_cmp, TCG_COND_GT, MO_16) 849BINARY_INT_GVEC(PCMPGTD, tcg_gen_gvec_cmp, TCG_COND_GT, MO_32) 850BINARY_INT_GVEC(PCMPGTQ, tcg_gen_gvec_cmp, TCG_COND_GT, MO_64) 851BINARY_INT_GVEC(PMAXSB, tcg_gen_gvec_smax, MO_8) 852BINARY_INT_GVEC(PMAXSW, tcg_gen_gvec_smax, MO_16) 853BINARY_INT_GVEC(PMAXSD, tcg_gen_gvec_smax, MO_32) 854BINARY_INT_GVEC(PMAXUB, tcg_gen_gvec_umax, MO_8) 855BINARY_INT_GVEC(PMAXUW, tcg_gen_gvec_umax, MO_16) 856BINARY_INT_GVEC(PMAXUD, tcg_gen_gvec_umax, MO_32) 857BINARY_INT_GVEC(PMINSB, tcg_gen_gvec_smin, MO_8) 858BINARY_INT_GVEC(PMINSW, tcg_gen_gvec_smin, MO_16) 859BINARY_INT_GVEC(PMINSD, tcg_gen_gvec_smin, MO_32) 860BINARY_INT_GVEC(PMINUB, tcg_gen_gvec_umin, MO_8) 861BINARY_INT_GVEC(PMINUW, tcg_gen_gvec_umin, MO_16) 862BINARY_INT_GVEC(PMINUD, tcg_gen_gvec_umin, MO_32) 863BINARY_INT_GVEC(PMULLW, tcg_gen_gvec_mul, MO_16) 864BINARY_INT_GVEC(PMULLD, tcg_gen_gvec_mul, MO_32) 865BINARY_INT_GVEC(POR, tcg_gen_gvec_or, MO_64) 866BINARY_INT_GVEC(PSUBB, tcg_gen_gvec_sub, MO_8) 867BINARY_INT_GVEC(PSUBW, tcg_gen_gvec_sub, MO_16) 868BINARY_INT_GVEC(PSUBD, tcg_gen_gvec_sub, MO_32) 869BINARY_INT_GVEC(PSUBQ, tcg_gen_gvec_sub, MO_64) 870BINARY_INT_GVEC(PSUBSB, tcg_gen_gvec_sssub, MO_8) 871BINARY_INT_GVEC(PSUBSW, tcg_gen_gvec_sssub, MO_16) 872BINARY_INT_GVEC(PSUBUSB, tcg_gen_gvec_ussub, MO_8) 873BINARY_INT_GVEC(PSUBUSW, tcg_gen_gvec_ussub, MO_16) 874BINARY_INT_GVEC(PXOR, tcg_gen_gvec_xor, MO_64) 875 876 877/* 878 * 00 = p* Pq, Qq (if mmx not NULL; no VEX) 879 * 66 = vp* Vx, Hx, Wx 880 * 881 * These are really the same encoding, because 1) V is the same as P when VEX.V 882 * is not present 2) P and Q are the same as H and W apart from MM/XMM 883 */ 884static inline void gen_binary_int_sse(DisasContext *s, X86DecodedInsn *decode, 885 SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm) 886{ 887 assert(!!mmx == !!(decode->e.special == X86_SPECIAL_MMX)); 888 889 if (mmx && (s->prefix & PREFIX_VEX) && !(s->prefix & PREFIX_DATA)) { 890 /* VEX encoding is not applicable to MMX instructions. */ 891 gen_illegal_opcode(s); 892 return; 893 } 894 if (!(s->prefix & PREFIX_DATA)) { 895 mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 896 } else if (!s->vex_l) { 897 xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 898 } else { 899 ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 900 } 901} 902 903 904#define BINARY_INT_MMX(uname, lname) \ 905static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 906{ \ 907 gen_binary_int_sse(s, decode, \ 908 gen_helper_##lname##_mmx, \ 909 gen_helper_##lname##_xmm, \ 910 gen_helper_##lname##_ymm); \ 911} 912BINARY_INT_MMX(PUNPCKLBW, punpcklbw) 913BINARY_INT_MMX(PUNPCKLWD, punpcklwd) 914BINARY_INT_MMX(PUNPCKLDQ, punpckldq) 915BINARY_INT_MMX(PACKSSWB, packsswb) 916BINARY_INT_MMX(PACKUSWB, packuswb) 917BINARY_INT_MMX(PUNPCKHBW, punpckhbw) 918BINARY_INT_MMX(PUNPCKHWD, punpckhwd) 919BINARY_INT_MMX(PUNPCKHDQ, punpckhdq) 920BINARY_INT_MMX(PACKSSDW, packssdw) 921 922BINARY_INT_MMX(PAVGB, pavgb) 923BINARY_INT_MMX(PAVGW, pavgw) 924BINARY_INT_MMX(PMADDWD, pmaddwd) 925BINARY_INT_MMX(PMULHUW, pmulhuw) 926BINARY_INT_MMX(PMULHW, pmulhw) 927BINARY_INT_MMX(PMULUDQ, pmuludq) 928BINARY_INT_MMX(PSADBW, psadbw) 929 930BINARY_INT_MMX(PSLLW_r, psllw) 931BINARY_INT_MMX(PSLLD_r, pslld) 932BINARY_INT_MMX(PSLLQ_r, psllq) 933BINARY_INT_MMX(PSRLW_r, psrlw) 934BINARY_INT_MMX(PSRLD_r, psrld) 935BINARY_INT_MMX(PSRLQ_r, psrlq) 936BINARY_INT_MMX(PSRAW_r, psraw) 937BINARY_INT_MMX(PSRAD_r, psrad) 938 939BINARY_INT_MMX(PHADDW, phaddw) 940BINARY_INT_MMX(PHADDSW, phaddsw) 941BINARY_INT_MMX(PHADDD, phaddd) 942BINARY_INT_MMX(PHSUBW, phsubw) 943BINARY_INT_MMX(PHSUBSW, phsubsw) 944BINARY_INT_MMX(PHSUBD, phsubd) 945BINARY_INT_MMX(PMADDUBSW, pmaddubsw) 946BINARY_INT_MMX(PSHUFB, pshufb) 947BINARY_INT_MMX(PSIGNB, psignb) 948BINARY_INT_MMX(PSIGNW, psignw) 949BINARY_INT_MMX(PSIGND, psignd) 950BINARY_INT_MMX(PMULHRSW, pmulhrsw) 951 952/* Instructions with no MMX equivalent. */ 953#define BINARY_INT_SSE(uname, lname) \ 954static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 955{ \ 956 gen_binary_int_sse(s, decode, \ 957 NULL, \ 958 gen_helper_##lname##_xmm, \ 959 gen_helper_##lname##_ymm); \ 960} 961 962/* Instructions with no MMX equivalent. */ 963BINARY_INT_SSE(PUNPCKLQDQ, punpcklqdq) 964BINARY_INT_SSE(PUNPCKHQDQ, punpckhqdq) 965BINARY_INT_SSE(VPACKUSDW, packusdw) 966BINARY_INT_SSE(VPERMILPS, vpermilps) 967BINARY_INT_SSE(VPERMILPD, vpermilpd) 968BINARY_INT_SSE(VMASKMOVPS, vpmaskmovd) 969BINARY_INT_SSE(VMASKMOVPD, vpmaskmovq) 970 971BINARY_INT_SSE(PMULDQ, pmuldq) 972 973BINARY_INT_SSE(VAESDEC, aesdec) 974BINARY_INT_SSE(VAESDECLAST, aesdeclast) 975BINARY_INT_SSE(VAESENC, aesenc) 976BINARY_INT_SSE(VAESENCLAST, aesenclast) 977 978#define UNARY_CMP_SSE(uname, lname) \ 979static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 980{ \ 981 if (!s->vex_l) { \ 982 gen_helper_##lname##_xmm(tcg_env, OP_PTR1, OP_PTR2); \ 983 } else { \ 984 gen_helper_##lname##_ymm(tcg_env, OP_PTR1, OP_PTR2); \ 985 } \ 986 assume_cc_op(s, CC_OP_EFLAGS); \ 987} 988UNARY_CMP_SSE(VPTEST, ptest) 989UNARY_CMP_SSE(VTESTPS, vtestps) 990UNARY_CMP_SSE(VTESTPD, vtestpd) 991 992static inline void gen_unary_int_sse(DisasContext *s, X86DecodedInsn *decode, 993 SSEFunc_0_epp xmm, SSEFunc_0_epp ymm) 994{ 995 if (!s->vex_l) { 996 xmm(tcg_env, OP_PTR0, OP_PTR2); 997 } else { 998 ymm(tcg_env, OP_PTR0, OP_PTR2); 999 } 1000} 1001 1002#define UNARY_INT_SSE(uname, lname) \ 1003static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1004{ \ 1005 gen_unary_int_sse(s, decode, \ 1006 gen_helper_##lname##_xmm, \ 1007 gen_helper_##lname##_ymm); \ 1008} 1009 1010UNARY_INT_SSE(VPMOVSXBW, pmovsxbw) 1011UNARY_INT_SSE(VPMOVSXBD, pmovsxbd) 1012UNARY_INT_SSE(VPMOVSXBQ, pmovsxbq) 1013UNARY_INT_SSE(VPMOVSXWD, pmovsxwd) 1014UNARY_INT_SSE(VPMOVSXWQ, pmovsxwq) 1015UNARY_INT_SSE(VPMOVSXDQ, pmovsxdq) 1016 1017UNARY_INT_SSE(VPMOVZXBW, pmovzxbw) 1018UNARY_INT_SSE(VPMOVZXBD, pmovzxbd) 1019UNARY_INT_SSE(VPMOVZXBQ, pmovzxbq) 1020UNARY_INT_SSE(VPMOVZXWD, pmovzxwd) 1021UNARY_INT_SSE(VPMOVZXWQ, pmovzxwq) 1022UNARY_INT_SSE(VPMOVZXDQ, pmovzxdq) 1023 1024UNARY_INT_SSE(VMOVSLDUP, pmovsldup) 1025UNARY_INT_SSE(VMOVSHDUP, pmovshdup) 1026UNARY_INT_SSE(VMOVDDUP, pmovdldup) 1027 1028UNARY_INT_SSE(VCVTDQ2PD, cvtdq2pd) 1029UNARY_INT_SSE(VCVTPD2DQ, cvtpd2dq) 1030UNARY_INT_SSE(VCVTTPD2DQ, cvttpd2dq) 1031UNARY_INT_SSE(VCVTDQ2PS, cvtdq2ps) 1032UNARY_INT_SSE(VCVTPS2DQ, cvtps2dq) 1033UNARY_INT_SSE(VCVTTPS2DQ, cvttps2dq) 1034UNARY_INT_SSE(VCVTPH2PS, cvtph2ps) 1035 1036 1037static inline void gen_unary_imm_sse(DisasContext *s, X86DecodedInsn *decode, 1038 SSEFunc_0_ppi xmm, SSEFunc_0_ppi ymm) 1039{ 1040 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 1041 if (!s->vex_l) { 1042 xmm(OP_PTR0, OP_PTR1, imm); 1043 } else { 1044 ymm(OP_PTR0, OP_PTR1, imm); 1045 } 1046} 1047 1048#define UNARY_IMM_SSE(uname, lname) \ 1049static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1050{ \ 1051 gen_unary_imm_sse(s, decode, \ 1052 gen_helper_##lname##_xmm, \ 1053 gen_helper_##lname##_ymm); \ 1054} 1055 1056UNARY_IMM_SSE(PSHUFD, pshufd) 1057UNARY_IMM_SSE(PSHUFHW, pshufhw) 1058UNARY_IMM_SSE(PSHUFLW, pshuflw) 1059#define gen_helper_vpermq_xmm NULL 1060UNARY_IMM_SSE(VPERMQ, vpermq) 1061UNARY_IMM_SSE(VPERMILPS_i, vpermilps_imm) 1062UNARY_IMM_SSE(VPERMILPD_i, vpermilpd_imm) 1063 1064static inline void gen_unary_imm_fp_sse(DisasContext *s, X86DecodedInsn *decode, 1065 SSEFunc_0_eppi xmm, SSEFunc_0_eppi ymm) 1066{ 1067 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 1068 if (!s->vex_l) { 1069 xmm(tcg_env, OP_PTR0, OP_PTR1, imm); 1070 } else { 1071 ymm(tcg_env, OP_PTR0, OP_PTR1, imm); 1072 } 1073} 1074 1075#define UNARY_IMM_FP_SSE(uname, lname) \ 1076static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1077{ \ 1078 gen_unary_imm_fp_sse(s, decode, \ 1079 gen_helper_##lname##_xmm, \ 1080 gen_helper_##lname##_ymm); \ 1081} 1082 1083UNARY_IMM_FP_SSE(VROUNDPS, roundps) 1084UNARY_IMM_FP_SSE(VROUNDPD, roundpd) 1085 1086static inline void gen_vexw_avx(DisasContext *s, X86DecodedInsn *decode, 1087 SSEFunc_0_eppp d_xmm, SSEFunc_0_eppp q_xmm, 1088 SSEFunc_0_eppp d_ymm, SSEFunc_0_eppp q_ymm) 1089{ 1090 SSEFunc_0_eppp d = s->vex_l ? d_ymm : d_xmm; 1091 SSEFunc_0_eppp q = s->vex_l ? q_ymm : q_xmm; 1092 SSEFunc_0_eppp fn = s->vex_w ? q : d; 1093 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 1094} 1095 1096/* VEX.W affects whether to operate on 32- or 64-bit elements. */ 1097#define VEXW_AVX(uname, lname) \ 1098static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1099{ \ 1100 gen_vexw_avx(s, decode, \ 1101 gen_helper_##lname##d_xmm, gen_helper_##lname##q_xmm, \ 1102 gen_helper_##lname##d_ymm, gen_helper_##lname##q_ymm); \ 1103} 1104VEXW_AVX(VPSLLV, vpsllv) 1105VEXW_AVX(VPSRLV, vpsrlv) 1106VEXW_AVX(VPSRAV, vpsrav) 1107VEXW_AVX(VPMASKMOV, vpmaskmov) 1108 1109/* Same as above, but with extra arguments to the helper. */ 1110static inline void gen_vsib_avx(DisasContext *s, X86DecodedInsn *decode, 1111 SSEFunc_0_epppti d_xmm, SSEFunc_0_epppti q_xmm, 1112 SSEFunc_0_epppti d_ymm, SSEFunc_0_epppti q_ymm) 1113{ 1114 SSEFunc_0_epppti d = s->vex_l ? d_ymm : d_xmm; 1115 SSEFunc_0_epppti q = s->vex_l ? q_ymm : q_xmm; 1116 SSEFunc_0_epppti fn = s->vex_w ? q : d; 1117 TCGv_i32 scale = tcg_constant_i32(decode->mem.scale); 1118 TCGv_ptr index = tcg_temp_new_ptr(); 1119 1120 /* Pass third input as (index, base, scale) */ 1121 tcg_gen_addi_ptr(index, tcg_env, ZMM_OFFSET(decode->mem.index)); 1122 fn(tcg_env, OP_PTR0, OP_PTR1, index, s->A0, scale); 1123 1124 /* 1125 * There are two output operands, so zero OP1's high 128 bits 1126 * in the VEX.128 case. 1127 */ 1128 if (!s->vex_l) { 1129 int ymmh_ofs = vector_elem_offset(&decode->op[1], MO_128, 1); 1130 tcg_gen_gvec_dup_imm(MO_64, ymmh_ofs, 16, 16, 0); 1131 } 1132} 1133#define VSIB_AVX(uname, lname) \ 1134static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1135{ \ 1136 gen_vsib_avx(s, decode, \ 1137 gen_helper_##lname##d_xmm, gen_helper_##lname##q_xmm, \ 1138 gen_helper_##lname##d_ymm, gen_helper_##lname##q_ymm); \ 1139} 1140VSIB_AVX(VPGATHERD, vpgatherd) 1141VSIB_AVX(VPGATHERQ, vpgatherq) 1142 1143static void gen_AAA(DisasContext *s, X86DecodedInsn *decode) 1144{ 1145 gen_update_cc_op(s); 1146 gen_helper_aaa(tcg_env); 1147 assume_cc_op(s, CC_OP_EFLAGS); 1148} 1149 1150static void gen_AAD(DisasContext *s, X86DecodedInsn *decode) 1151{ 1152 gen_helper_aad(s->T0, s->T0, s->T1); 1153 prepare_update1_cc(decode, s, CC_OP_LOGICB); 1154} 1155 1156static void gen_AAM(DisasContext *s, X86DecodedInsn *decode) 1157{ 1158 if (decode->immediate == 0) { 1159 gen_exception(s, EXCP00_DIVZ); 1160 } else { 1161 gen_helper_aam(s->T0, s->T0, s->T1); 1162 prepare_update1_cc(decode, s, CC_OP_LOGICB); 1163 } 1164} 1165 1166static void gen_AAS(DisasContext *s, X86DecodedInsn *decode) 1167{ 1168 gen_update_cc_op(s); 1169 gen_helper_aas(tcg_env); 1170 assume_cc_op(s, CC_OP_EFLAGS); 1171} 1172 1173static void gen_ADC(DisasContext *s, X86DecodedInsn *decode) 1174{ 1175 MemOp ot = decode->op[1].ot; 1176 TCGv c_in = tcg_temp_new(); 1177 1178 gen_compute_eflags_c(s, c_in); 1179 if (s->prefix & PREFIX_LOCK) { 1180 tcg_gen_add_tl(s->T0, c_in, s->T1); 1181 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T0, 1182 s->mem_index, ot | MO_LE); 1183 } else { 1184 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1185 tcg_gen_add_tl(s->T0, s->T0, c_in); 1186 } 1187 prepare_update3_cc(decode, s, CC_OP_ADCB + ot, c_in); 1188} 1189 1190static void gen_ADCOX(DisasContext *s, X86DecodedInsn *decode, int cc_op) 1191{ 1192 MemOp ot = decode->op[0].ot; 1193 TCGv carry_in = NULL; 1194 TCGv *carry_out = (cc_op == CC_OP_ADCX ? &decode->cc_dst : &decode->cc_src2); 1195 TCGv zero; 1196 1197 decode->cc_op = cc_op; 1198 *carry_out = tcg_temp_new(); 1199 if (CC_OP_HAS_EFLAGS(s->cc_op)) { 1200 decode->cc_src = cpu_cc_src; 1201 1202 /* Re-use the carry-out from a previous round? */ 1203 if (s->cc_op == cc_op || s->cc_op == CC_OP_ADCOX) { 1204 carry_in = (cc_op == CC_OP_ADCX ? cpu_cc_dst : cpu_cc_src2); 1205 } 1206 1207 /* Preserve the opposite carry from previous rounds? */ 1208 if (s->cc_op != cc_op && s->cc_op != CC_OP_EFLAGS) { 1209 decode->cc_op = CC_OP_ADCOX; 1210 if (carry_out == &decode->cc_dst) { 1211 decode->cc_src2 = cpu_cc_src2; 1212 } else { 1213 decode->cc_dst = cpu_cc_dst; 1214 } 1215 } 1216 } else { 1217 decode->cc_src = tcg_temp_new(); 1218 gen_mov_eflags(s, decode->cc_src); 1219 } 1220 1221 if (!carry_in) { 1222 /* Get carry_in out of EFLAGS. */ 1223 carry_in = tcg_temp_new(); 1224 tcg_gen_extract_tl(carry_in, decode->cc_src, 1225 ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1); 1226 } 1227 1228 switch (ot) { 1229#ifdef TARGET_X86_64 1230 case MO_32: 1231 /* If TL is 64-bit just do everything in 64-bit arithmetic. */ 1232 tcg_gen_ext32u_tl(s->T0, s->T0); 1233 tcg_gen_ext32u_tl(s->T1, s->T1); 1234 tcg_gen_add_i64(s->T0, s->T0, s->T1); 1235 tcg_gen_add_i64(s->T0, s->T0, carry_in); 1236 tcg_gen_shri_i64(*carry_out, s->T0, 32); 1237 break; 1238#endif 1239 default: 1240 zero = tcg_constant_tl(0); 1241 tcg_gen_add2_tl(s->T0, *carry_out, s->T0, zero, carry_in, zero); 1242 tcg_gen_add2_tl(s->T0, *carry_out, s->T0, *carry_out, s->T1, zero); 1243 break; 1244 } 1245} 1246 1247static void gen_ADCX(DisasContext *s, X86DecodedInsn *decode) 1248{ 1249 gen_ADCOX(s, decode, CC_OP_ADCX); 1250} 1251 1252static void gen_ADD(DisasContext *s, X86DecodedInsn *decode) 1253{ 1254 MemOp ot = decode->op[1].ot; 1255 1256 if (s->prefix & PREFIX_LOCK) { 1257 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 1258 s->mem_index, ot | MO_LE); 1259 } else { 1260 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1261 } 1262 prepare_update2_cc(decode, s, CC_OP_ADDB + ot); 1263} 1264 1265static void gen_ADOX(DisasContext *s, X86DecodedInsn *decode) 1266{ 1267 gen_ADCOX(s, decode, CC_OP_ADOX); 1268} 1269 1270static void gen_AND(DisasContext *s, X86DecodedInsn *decode) 1271{ 1272 MemOp ot = decode->op[1].ot; 1273 1274 if (s->prefix & PREFIX_LOCK) { 1275 tcg_gen_atomic_and_fetch_tl(s->T0, s->A0, s->T1, 1276 s->mem_index, ot | MO_LE); 1277 } else { 1278 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1279 } 1280 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1281} 1282 1283static void gen_ANDN(DisasContext *s, X86DecodedInsn *decode) 1284{ 1285 MemOp ot = decode->op[0].ot; 1286 1287 tcg_gen_andc_tl(s->T0, s->T1, s->T0); 1288 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1289} 1290 1291static void gen_ARPL(DisasContext *s, X86DecodedInsn *decode) 1292{ 1293 TCGv zf = tcg_temp_new(); 1294 TCGv flags = tcg_temp_new(); 1295 1296 gen_mov_eflags(s, flags); 1297 1298 /* Compute adjusted DST in T1, merging in SRC[RPL]. */ 1299 tcg_gen_deposit_tl(s->T1, s->T0, s->T1, 0, 2); 1300 1301 /* Z flag set if DST[RPL] < SRC[RPL] */ 1302 tcg_gen_setcond_tl(TCG_COND_LTU, zf, s->T0, s->T1); 1303 tcg_gen_deposit_tl(flags, flags, zf, ctz32(CC_Z), 1); 1304 1305 /* Place maximum RPL in DST */ 1306 tcg_gen_umax_tl(s->T0, s->T0, s->T1); 1307 1308 decode->cc_src = flags; 1309 decode->cc_op = CC_OP_EFLAGS; 1310} 1311 1312static void gen_BEXTR(DisasContext *s, X86DecodedInsn *decode) 1313{ 1314 MemOp ot = decode->op[0].ot; 1315 TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); 1316 TCGv zero = tcg_constant_tl(0); 1317 TCGv mone = tcg_constant_tl(-1); 1318 1319 /* 1320 * Extract START, and shift the operand. 1321 * Shifts larger than operand size get zeros. 1322 */ 1323 tcg_gen_ext8u_tl(s->A0, s->T1); 1324 tcg_gen_shr_tl(s->T0, s->T0, s->A0); 1325 1326 tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound, s->T0, zero); 1327 1328 /* 1329 * Extract the LEN into an inverse mask. Lengths larger than 1330 * operand size get all zeros, length 0 gets all ones. 1331 */ 1332 tcg_gen_extract_tl(s->A0, s->T1, 8, 8); 1333 tcg_gen_shl_tl(s->T1, mone, s->A0); 1334 tcg_gen_movcond_tl(TCG_COND_LEU, s->T1, s->A0, bound, s->T1, zero); 1335 tcg_gen_andc_tl(s->T0, s->T0, s->T1); 1336 1337 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1338} 1339 1340static void gen_BLSI(DisasContext *s, X86DecodedInsn *decode) 1341{ 1342 MemOp ot = decode->op[0].ot; 1343 1344 /* input in T1, which is ready for prepare_update2_cc */ 1345 tcg_gen_neg_tl(s->T0, s->T1); 1346 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1347 prepare_update2_cc(decode, s, CC_OP_BLSIB + ot); 1348} 1349 1350static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode) 1351{ 1352 MemOp ot = decode->op[0].ot; 1353 1354 /* input in T1, which is ready for prepare_update2_cc */ 1355 tcg_gen_subi_tl(s->T0, s->T1, 1); 1356 tcg_gen_xor_tl(s->T0, s->T0, s->T1); 1357 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1358} 1359 1360static void gen_BLSR(DisasContext *s, X86DecodedInsn *decode) 1361{ 1362 MemOp ot = decode->op[0].ot; 1363 1364 /* input in T1, which is ready for prepare_update2_cc */ 1365 tcg_gen_subi_tl(s->T0, s->T1, 1); 1366 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1367 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1368} 1369 1370static void gen_BOUND(DisasContext *s, X86DecodedInsn *decode) 1371{ 1372 TCGv_i32 op = tcg_temp_new_i32(); 1373 tcg_gen_trunc_tl_i32(op, s->T0); 1374 if (decode->op[1].ot == MO_16) { 1375 gen_helper_boundw(tcg_env, s->A0, op); 1376 } else { 1377 gen_helper_boundl(tcg_env, s->A0, op); 1378 } 1379} 1380 1381/* Non-standard convention - on entry T0 is zero-extended input, T1 is the output. */ 1382static void gen_BSF(DisasContext *s, X86DecodedInsn *decode) 1383{ 1384 MemOp ot = decode->op[0].ot; 1385 1386 /* Only the Z bit is defined and it is related to the input. */ 1387 decode->cc_dst = tcg_temp_new(); 1388 decode->cc_op = CC_OP_LOGICB + ot; 1389 tcg_gen_mov_tl(decode->cc_dst, s->T0); 1390 1391 /* 1392 * The manual says that the output is undefined when the 1393 * input is zero, but real hardware leaves it unchanged, and 1394 * real programs appear to depend on that. Accomplish this 1395 * by passing the output as the value to return upon zero. 1396 */ 1397 tcg_gen_ctz_tl(s->T0, s->T0, s->T1); 1398} 1399 1400/* Non-standard convention - on entry T0 is zero-extended input, T1 is the output. */ 1401static void gen_BSR(DisasContext *s, X86DecodedInsn *decode) 1402{ 1403 MemOp ot = decode->op[0].ot; 1404 1405 /* Only the Z bit is defined and it is related to the input. */ 1406 decode->cc_dst = tcg_temp_new(); 1407 decode->cc_op = CC_OP_LOGICB + ot; 1408 tcg_gen_mov_tl(decode->cc_dst, s->T0); 1409 1410 /* 1411 * The manual says that the output is undefined when the 1412 * input is zero, but real hardware leaves it unchanged, and 1413 * real programs appear to depend on that. Accomplish this 1414 * by passing the output as the value to return upon zero. 1415 * Plus, return the bit index of the first 1 bit. 1416 */ 1417 tcg_gen_xori_tl(s->T1, s->T1, TARGET_LONG_BITS - 1); 1418 tcg_gen_clz_tl(s->T0, s->T0, s->T1); 1419 tcg_gen_xori_tl(s->T0, s->T0, TARGET_LONG_BITS - 1); 1420} 1421 1422static void gen_BSWAP(DisasContext *s, X86DecodedInsn *decode) 1423{ 1424#ifdef TARGET_X86_64 1425 if (s->dflag == MO_64) { 1426 tcg_gen_bswap64_i64(s->T0, s->T0); 1427 return; 1428 } 1429#endif 1430 tcg_gen_bswap32_tl(s->T0, s->T0, TCG_BSWAP_OZ); 1431} 1432 1433static TCGv gen_bt_mask(DisasContext *s, X86DecodedInsn *decode) 1434{ 1435 MemOp ot = decode->op[1].ot; 1436 TCGv mask = tcg_temp_new(); 1437 1438 tcg_gen_andi_tl(s->T1, s->T1, (8 << ot) - 1); 1439 tcg_gen_shl_tl(mask, tcg_constant_tl(1), s->T1); 1440 return mask; 1441} 1442 1443/* Expects truncated bit index in COUNT, 1 << COUNT in MASK. */ 1444static void gen_bt_flags(DisasContext *s, X86DecodedInsn *decode, TCGv src, 1445 TCGv count, TCGv mask) 1446{ 1447 TCGv cf; 1448 1449 /* 1450 * C is the result of the test, Z is unchanged, and the others 1451 * are all undefined. 1452 */ 1453 if (s->cc_op == CC_OP_DYNAMIC || CC_OP_HAS_EFLAGS(s->cc_op)) { 1454 /* Generate EFLAGS and replace the C bit. */ 1455 cf = tcg_temp_new(); 1456 tcg_gen_setcond_tl(TCG_COND_TSTNE, cf, src, mask); 1457 prepare_update_cf(decode, s, cf); 1458 } else { 1459 /* 1460 * Z was going to be computed from the non-zero status of CC_DST. 1461 * We can get that same Z value (and the new C value) by leaving 1462 * CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the 1463 * same width. 1464 */ 1465 decode->cc_src = tcg_temp_new(); 1466 decode->cc_dst = cpu_cc_dst; 1467 decode->cc_op = CC_OP_SARB + cc_op_size(s->cc_op); 1468 tcg_gen_shr_tl(decode->cc_src, src, count); 1469 } 1470} 1471 1472static void gen_BT(DisasContext *s, X86DecodedInsn *decode) 1473{ 1474 TCGv count = s->T1; 1475 TCGv mask; 1476 1477 /* 1478 * Try to ensure that the rhs of the TSTNE condition is a constant (and a 1479 * power of two), as that is more readily available on most TCG backends. 1480 * 1481 * For immediate bit number gen_bt_mask()'s output is already a constant; 1482 * for register bit number, shift the source right and check bit 0. 1483 */ 1484 if (decode->e.op2 == X86_TYPE_I) { 1485 mask = gen_bt_mask(s, decode); 1486 } else { 1487 MemOp ot = decode->op[1].ot; 1488 1489 tcg_gen_andi_tl(s->T1, s->T1, (8 << ot) - 1); 1490 tcg_gen_shr_tl(s->T0, s->T0, s->T1); 1491 1492 count = tcg_constant_tl(0); 1493 mask = tcg_constant_tl(1); 1494 } 1495 gen_bt_flags(s, decode, s->T0, count, mask); 1496} 1497 1498static void gen_BTC(DisasContext *s, X86DecodedInsn *decode) 1499{ 1500 MemOp ot = decode->op[0].ot; 1501 TCGv old = tcg_temp_new(); 1502 TCGv mask = gen_bt_mask(s, decode); 1503 1504 if (s->prefix & PREFIX_LOCK) { 1505 tcg_gen_atomic_fetch_xor_tl(old, s->A0, mask, s->mem_index, ot | MO_LE); 1506 } else { 1507 tcg_gen_mov_tl(old, s->T0); 1508 tcg_gen_xor_tl(s->T0, s->T0, mask); 1509 } 1510 1511 gen_bt_flags(s, decode, old, s->T1, mask); 1512} 1513 1514static void gen_BTR(DisasContext *s, X86DecodedInsn *decode) 1515{ 1516 MemOp ot = decode->op[0].ot; 1517 TCGv old = tcg_temp_new(); 1518 TCGv mask = gen_bt_mask(s, decode); 1519 1520 if (s->prefix & PREFIX_LOCK) { 1521 TCGv maskc = tcg_temp_new(); 1522 tcg_gen_not_tl(maskc, mask); 1523 tcg_gen_atomic_fetch_and_tl(old, s->A0, maskc, s->mem_index, ot | MO_LE); 1524 } else { 1525 tcg_gen_mov_tl(old, s->T0); 1526 tcg_gen_andc_tl(s->T0, s->T0, mask); 1527 } 1528 1529 gen_bt_flags(s, decode, old, s->T1, mask); 1530} 1531 1532static void gen_BTS(DisasContext *s, X86DecodedInsn *decode) 1533{ 1534 MemOp ot = decode->op[0].ot; 1535 TCGv old = tcg_temp_new(); 1536 TCGv mask = gen_bt_mask(s, decode); 1537 1538 if (s->prefix & PREFIX_LOCK) { 1539 tcg_gen_atomic_fetch_or_tl(old, s->A0, mask, s->mem_index, ot | MO_LE); 1540 } else { 1541 tcg_gen_mov_tl(old, s->T0); 1542 tcg_gen_or_tl(s->T0, s->T0, mask); 1543 } 1544 1545 gen_bt_flags(s, decode, old, s->T1, mask); 1546} 1547 1548static void gen_BZHI(DisasContext *s, X86DecodedInsn *decode) 1549{ 1550 MemOp ot = decode->op[0].ot; 1551 TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); 1552 TCGv zero = tcg_constant_tl(0); 1553 TCGv mone = tcg_constant_tl(-1); 1554 1555 tcg_gen_ext8u_tl(s->T1, s->T1); 1556 1557 tcg_gen_shl_tl(s->A0, mone, s->T1); 1558 tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->T1, bound, s->A0, zero); 1559 tcg_gen_andc_tl(s->T0, s->T0, s->A0); 1560 /* 1561 * Note that since we're using BMILG (in order to get O 1562 * cleared) we need to store the inverse into C. 1563 */ 1564 tcg_gen_setcond_tl(TCG_COND_LEU, s->T1, s->T1, bound); 1565 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1566} 1567 1568static void gen_CALL(DisasContext *s, X86DecodedInsn *decode) 1569{ 1570 gen_push_v(s, eip_next_tl(s)); 1571 gen_JMP(s, decode); 1572} 1573 1574static void gen_CALL_m(DisasContext *s, X86DecodedInsn *decode) 1575{ 1576 gen_push_v(s, eip_next_tl(s)); 1577 gen_JMP_m(s, decode); 1578} 1579 1580static void gen_CALLF(DisasContext *s, X86DecodedInsn *decode) 1581{ 1582 gen_far_call(s); 1583} 1584 1585static void gen_CALLF_m(DisasContext *s, X86DecodedInsn *decode) 1586{ 1587 MemOp ot = decode->op[1].ot; 1588 1589 gen_op_ld_v(s, ot, s->T0, s->A0); 1590 gen_add_A0_im(s, 1 << ot); 1591 gen_op_ld_v(s, MO_16, s->T1, s->A0); 1592 gen_far_call(s); 1593} 1594 1595static void gen_CBW(DisasContext *s, X86DecodedInsn *decode) 1596{ 1597 MemOp src_ot = decode->op[0].ot - 1; 1598 1599 tcg_gen_ext_tl(s->T0, s->T0, src_ot | MO_SIGN); 1600} 1601 1602static void gen_CLC(DisasContext *s, X86DecodedInsn *decode) 1603{ 1604 gen_compute_eflags(s); 1605 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); 1606} 1607 1608static void gen_CLD(DisasContext *s, X86DecodedInsn *decode) 1609{ 1610 tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, offsetof(CPUX86State, df)); 1611} 1612 1613static void gen_CLI(DisasContext *s, X86DecodedInsn *decode) 1614{ 1615 gen_reset_eflags(s, IF_MASK); 1616} 1617 1618static void gen_CLTS(DisasContext *s, X86DecodedInsn *decode) 1619{ 1620 gen_helper_clts(tcg_env); 1621 /* abort block because static cpu state changed */ 1622 s->base.is_jmp = DISAS_EOB_NEXT; 1623} 1624 1625static void gen_CMC(DisasContext *s, X86DecodedInsn *decode) 1626{ 1627 gen_compute_eflags(s); 1628 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); 1629} 1630 1631static void gen_CMOVcc(DisasContext *s, X86DecodedInsn *decode) 1632{ 1633 gen_cmovcc1(s, decode->b & 0xf, s->T0, s->T1); 1634} 1635 1636static void gen_CMPccXADD(DisasContext *s, X86DecodedInsn *decode) 1637{ 1638 TCGLabel *label_top = gen_new_label(); 1639 TCGLabel *label_bottom = gen_new_label(); 1640 TCGv oldv = tcg_temp_new(); 1641 TCGv newv = tcg_temp_new(); 1642 TCGv cmpv = tcg_temp_new(); 1643 TCGCond cond; 1644 1645 TCGv cmp_lhs, cmp_rhs; 1646 MemOp ot, ot_full; 1647 1648 int jcc_op = (decode->b >> 1) & 7; 1649 static const TCGCond cond_table[8] = { 1650 [JCC_O] = TCG_COND_LT, /* test sign bit by comparing against 0 */ 1651 [JCC_B] = TCG_COND_LTU, 1652 [JCC_Z] = TCG_COND_EQ, 1653 [JCC_BE] = TCG_COND_LEU, 1654 [JCC_S] = TCG_COND_LT, /* test sign bit by comparing against 0 */ 1655 [JCC_P] = TCG_COND_TSTEQ, /* even parity - tests low bit of popcount */ 1656 [JCC_L] = TCG_COND_LT, 1657 [JCC_LE] = TCG_COND_LE, 1658 }; 1659 1660 cond = cond_table[jcc_op]; 1661 if (decode->b & 1) { 1662 cond = tcg_invert_cond(cond); 1663 } 1664 1665 ot = decode->op[0].ot; 1666 ot_full = ot | MO_LE; 1667 if (jcc_op >= JCC_S) { 1668 /* 1669 * Sign-extend values before subtracting for S, P (zero/sign extension 1670 * does not matter there) L, LE and their inverses. 1671 */ 1672 ot_full |= MO_SIGN; 1673 } 1674 1675 /* 1676 * cmpv will be moved to cc_src *after* cpu_regs[] is written back, so use 1677 * tcg_gen_ext_tl instead of gen_ext_tl. 1678 */ 1679 tcg_gen_ext_tl(cmpv, cpu_regs[decode->op[1].n], ot_full); 1680 1681 /* 1682 * Cmpxchg loop starts here. 1683 * - s->T1: addition operand (from decoder) 1684 * - s->A0: dest address (from decoder) 1685 * - s->cc_srcT: memory operand (lhs for comparison) 1686 * - cmpv: rhs for comparison 1687 */ 1688 gen_set_label(label_top); 1689 gen_op_ld_v(s, ot_full, s->cc_srcT, s->A0); 1690 tcg_gen_sub_tl(s->T0, s->cc_srcT, cmpv); 1691 1692 /* Compute the comparison result by hand, to avoid clobbering cc_*. */ 1693 switch (jcc_op) { 1694 case JCC_O: 1695 /* (src1 ^ src2) & (src1 ^ dst). newv is only used here for a moment */ 1696 tcg_gen_xor_tl(newv, s->cc_srcT, s->T0); 1697 tcg_gen_xor_tl(s->tmp0, s->cc_srcT, cmpv); 1698 tcg_gen_and_tl(s->tmp0, s->tmp0, newv); 1699 tcg_gen_sextract_tl(s->tmp0, s->tmp0, 0, 8 << ot); 1700 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(0); 1701 break; 1702 1703 case JCC_P: 1704 tcg_gen_ext8u_tl(s->tmp0, s->T0); 1705 tcg_gen_ctpop_tl(s->tmp0, s->tmp0); 1706 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(1); 1707 break; 1708 1709 case JCC_S: 1710 tcg_gen_sextract_tl(s->tmp0, s->T0, 0, 8 << ot); 1711 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(0); 1712 break; 1713 1714 default: 1715 cmp_lhs = s->cc_srcT, cmp_rhs = cmpv; 1716 break; 1717 } 1718 1719 /* Compute new value: if condition does not hold, just store back s->cc_srcT */ 1720 tcg_gen_add_tl(newv, s->cc_srcT, s->T1); 1721 tcg_gen_movcond_tl(cond, newv, cmp_lhs, cmp_rhs, newv, s->cc_srcT); 1722 tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, s->cc_srcT, newv, s->mem_index, ot_full); 1723 1724 /* Exit unconditionally if cmpxchg succeeded. */ 1725 tcg_gen_brcond_tl(TCG_COND_EQ, oldv, s->cc_srcT, label_bottom); 1726 1727 /* Try again if there was actually a store to make. */ 1728 tcg_gen_brcond_tl(cond, cmp_lhs, cmp_rhs, label_top); 1729 gen_set_label(label_bottom); 1730 1731 /* Store old value to registers only after a successful store. */ 1732 gen_writeback(s, decode, 1, s->cc_srcT); 1733 1734 decode->cc_dst = s->T0; 1735 decode->cc_src = cmpv; 1736 decode->cc_op = CC_OP_SUBB + ot; 1737} 1738 1739static void gen_CMPS(DisasContext *s, X86DecodedInsn *decode) 1740{ 1741 MemOp ot = decode->op[2].ot; 1742 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 1743 gen_repz_nz(s, ot, gen_cmps); 1744 } else { 1745 gen_cmps(s, ot); 1746 } 1747} 1748 1749static void gen_CMPXCHG(DisasContext *s, X86DecodedInsn *decode) 1750{ 1751 MemOp ot = decode->op[2].ot; 1752 TCGv cmpv = tcg_temp_new(); 1753 TCGv oldv = tcg_temp_new(); 1754 TCGv newv = tcg_temp_new(); 1755 TCGv dest; 1756 1757 tcg_gen_ext_tl(cmpv, cpu_regs[R_EAX], ot); 1758 tcg_gen_ext_tl(newv, s->T1, ot); 1759 if (s->prefix & PREFIX_LOCK) { 1760 tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, cmpv, newv, 1761 s->mem_index, ot | MO_LE); 1762 } else { 1763 tcg_gen_ext_tl(oldv, s->T0, ot); 1764 if (decode->op[0].has_ea) { 1765 /* 1766 * Perform an unconditional store cycle like physical cpu; 1767 * must be before changing accumulator to ensure 1768 * idempotency if the store faults and the instruction 1769 * is restarted 1770 */ 1771 tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, oldv); 1772 gen_op_st_v(s, ot, newv, s->A0); 1773 } else { 1774 /* 1775 * Unlike the memory case, where "the destination operand receives 1776 * a write cycle without regard to the result of the comparison", 1777 * rm must not be touched altogether if the write fails, including 1778 * not zero-extending it on 64-bit processors. So, precompute 1779 * the result of a successful writeback and perform the movcond 1780 * directly on cpu_regs. In case rm is part of RAX, note that this 1781 * movcond and the one below are mutually exclusive is executed. 1782 */ 1783 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, newv, newv); 1784 tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, newv, dest); 1785 } 1786 decode->op[0].unit = X86_OP_SKIP; 1787 } 1788 1789 /* Write RAX only if the cmpxchg fails. */ 1790 dest = gen_op_deposit_reg_v(s, ot, R_EAX, s->T0, oldv); 1791 tcg_gen_movcond_tl(TCG_COND_NE, dest, oldv, cmpv, s->T0, dest); 1792 1793 tcg_gen_mov_tl(s->cc_srcT, cmpv); 1794 tcg_gen_sub_tl(cmpv, cmpv, oldv); 1795 decode->cc_dst = cmpv; 1796 decode->cc_src = oldv; 1797 decode->cc_op = CC_OP_SUBB + ot; 1798} 1799 1800static void gen_CMPXCHG16B(DisasContext *s, X86DecodedInsn *decode) 1801{ 1802#ifdef TARGET_X86_64 1803 MemOp mop = MO_TE | MO_128 | MO_ALIGN; 1804 TCGv_i64 t0, t1; 1805 TCGv_i128 cmp, val; 1806 1807 cmp = tcg_temp_new_i128(); 1808 val = tcg_temp_new_i128(); 1809 tcg_gen_concat_i64_i128(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); 1810 tcg_gen_concat_i64_i128(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); 1811 1812 /* Only require atomic with LOCK; non-parallel handled in generator. */ 1813 if (s->prefix & PREFIX_LOCK) { 1814 tcg_gen_atomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mop); 1815 } else { 1816 tcg_gen_nonatomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mop); 1817 } 1818 1819 tcg_gen_extr_i128_i64(s->T0, s->T1, val); 1820 1821 /* Determine success after the fact. */ 1822 t0 = tcg_temp_new_i64(); 1823 t1 = tcg_temp_new_i64(); 1824 tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); 1825 tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); 1826 tcg_gen_or_i64(t0, t0, t1); 1827 1828 /* Update Z. */ 1829 gen_compute_eflags(s); 1830 tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); 1831 tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); 1832 1833 /* 1834 * Extract the result values for the register pair. We may do this 1835 * unconditionally, because on success (Z=1), the old value matches 1836 * the previous value in RDX:RAX. 1837 */ 1838 tcg_gen_mov_i64(cpu_regs[R_EAX], s->T0); 1839 tcg_gen_mov_i64(cpu_regs[R_EDX], s->T1); 1840#else 1841 abort(); 1842#endif 1843} 1844 1845static void gen_CMPXCHG8B(DisasContext *s, X86DecodedInsn *decode) 1846{ 1847 TCGv_i64 cmp, val, old; 1848 TCGv Z; 1849 1850 cmp = tcg_temp_new_i64(); 1851 val = tcg_temp_new_i64(); 1852 old = tcg_temp_new_i64(); 1853 1854 /* Construct the comparison values from the register pair. */ 1855 tcg_gen_concat_tl_i64(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); 1856 tcg_gen_concat_tl_i64(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); 1857 1858 /* Only require atomic with LOCK; non-parallel handled in generator. */ 1859 if (s->prefix & PREFIX_LOCK) { 1860 tcg_gen_atomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_TEUQ); 1861 } else { 1862 tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, 1863 s->mem_index, MO_TEUQ); 1864 } 1865 1866 /* Set tmp0 to match the required value of Z. */ 1867 tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); 1868 Z = tcg_temp_new(); 1869 tcg_gen_trunc_i64_tl(Z, cmp); 1870 1871 /* 1872 * Extract the result values for the register pair. 1873 * For 32-bit, we may do this unconditionally, because on success (Z=1), 1874 * the old value matches the previous value in EDX:EAX. For x86_64, 1875 * the store must be conditional, because we must leave the source 1876 * registers unchanged on success, and zero-extend the writeback 1877 * on failure (Z=0). 1878 */ 1879 if (TARGET_LONG_BITS == 32) { 1880 tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], old); 1881 } else { 1882 TCGv zero = tcg_constant_tl(0); 1883 1884 tcg_gen_extr_i64_tl(s->T0, s->T1, old); 1885 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EAX], Z, zero, 1886 s->T0, cpu_regs[R_EAX]); 1887 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, 1888 s->T1, cpu_regs[R_EDX]); 1889 } 1890 1891 /* Update Z. */ 1892 gen_compute_eflags(s); 1893 tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); 1894} 1895 1896static void gen_CPUID(DisasContext *s, X86DecodedInsn *decode) 1897{ 1898 gen_update_cc_op(s); 1899 gen_update_eip_cur(s); 1900 gen_helper_cpuid(tcg_env); 1901} 1902 1903static void gen_CRC32(DisasContext *s, X86DecodedInsn *decode) 1904{ 1905 MemOp ot = decode->op[2].ot; 1906 1907 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 1908 gen_helper_crc32(s->T0, s->tmp2_i32, s->T1, tcg_constant_i32(8 << ot)); 1909} 1910 1911static void gen_CVTPI2Px(DisasContext *s, X86DecodedInsn *decode) 1912{ 1913 gen_helper_enter_mmx(tcg_env); 1914 if (s->prefix & PREFIX_DATA) { 1915 gen_helper_cvtpi2pd(tcg_env, OP_PTR0, OP_PTR2); 1916 } else { 1917 gen_helper_cvtpi2ps(tcg_env, OP_PTR0, OP_PTR2); 1918 } 1919} 1920 1921static void gen_CVTPx2PI(DisasContext *s, X86DecodedInsn *decode) 1922{ 1923 gen_helper_enter_mmx(tcg_env); 1924 if (s->prefix & PREFIX_DATA) { 1925 gen_helper_cvtpd2pi(tcg_env, OP_PTR0, OP_PTR2); 1926 } else { 1927 gen_helper_cvtps2pi(tcg_env, OP_PTR0, OP_PTR2); 1928 } 1929} 1930 1931static void gen_CVTTPx2PI(DisasContext *s, X86DecodedInsn *decode) 1932{ 1933 gen_helper_enter_mmx(tcg_env); 1934 if (s->prefix & PREFIX_DATA) { 1935 gen_helper_cvttpd2pi(tcg_env, OP_PTR0, OP_PTR2); 1936 } else { 1937 gen_helper_cvttps2pi(tcg_env, OP_PTR0, OP_PTR2); 1938 } 1939} 1940 1941static void gen_CWD(DisasContext *s, X86DecodedInsn *decode) 1942{ 1943 int shift = 8 << decode->op[0].ot; 1944 1945 tcg_gen_sextract_tl(s->T0, s->T0, shift - 1, 1); 1946} 1947 1948static void gen_DAA(DisasContext *s, X86DecodedInsn *decode) 1949{ 1950 gen_update_cc_op(s); 1951 gen_helper_daa(tcg_env); 1952 assume_cc_op(s, CC_OP_EFLAGS); 1953} 1954 1955static void gen_DAS(DisasContext *s, X86DecodedInsn *decode) 1956{ 1957 gen_update_cc_op(s); 1958 gen_helper_das(tcg_env); 1959 assume_cc_op(s, CC_OP_EFLAGS); 1960} 1961 1962static void gen_DEC(DisasContext *s, X86DecodedInsn *decode) 1963{ 1964 MemOp ot = decode->op[1].ot; 1965 1966 tcg_gen_movi_tl(s->T1, -1); 1967 if (s->prefix & PREFIX_LOCK) { 1968 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 1969 s->mem_index, ot | MO_LE); 1970 } else { 1971 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1972 } 1973 prepare_update_cc_incdec(decode, s, CC_OP_DECB + ot); 1974} 1975 1976static void gen_DIV(DisasContext *s, X86DecodedInsn *decode) 1977{ 1978 MemOp ot = decode->op[1].ot; 1979 1980 switch(ot) { 1981 case MO_8: 1982 gen_helper_divb_AL(tcg_env, s->T0); 1983 break; 1984 case MO_16: 1985 gen_helper_divw_AX(tcg_env, s->T0); 1986 break; 1987 default: 1988 case MO_32: 1989 gen_helper_divl_EAX(tcg_env, s->T0); 1990 break; 1991#ifdef TARGET_X86_64 1992 case MO_64: 1993 gen_helper_divq_EAX(tcg_env, s->T0); 1994 break; 1995#endif 1996 } 1997} 1998 1999static void gen_EMMS(DisasContext *s, X86DecodedInsn *decode) 2000{ 2001 gen_helper_emms(tcg_env); 2002} 2003 2004static void gen_ENTER(DisasContext *s, X86DecodedInsn *decode) 2005{ 2006 gen_enter(s, decode->op[1].imm, decode->op[2].imm); 2007} 2008 2009static void gen_EXTRQ_i(DisasContext *s, X86DecodedInsn *decode) 2010{ 2011 TCGv_i32 length = tcg_constant_i32(decode->immediate & 63); 2012 TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63); 2013 2014 gen_helper_extrq_i(tcg_env, OP_PTR0, index, length); 2015} 2016 2017static void gen_EXTRQ_r(DisasContext *s, X86DecodedInsn *decode) 2018{ 2019 gen_helper_extrq_r(tcg_env, OP_PTR0, OP_PTR2); 2020} 2021 2022static void gen_FXRSTOR(DisasContext *s, X86DecodedInsn *decode) 2023{ 2024 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { 2025 gen_NM_exception(s); 2026 } else { 2027 gen_helper_fxrstor(tcg_env, s->A0); 2028 } 2029} 2030 2031static void gen_FXSAVE(DisasContext *s, X86DecodedInsn *decode) 2032{ 2033 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { 2034 gen_NM_exception(s); 2035 } else { 2036 gen_helper_fxsave(tcg_env, s->A0); 2037 } 2038} 2039 2040static void gen_HLT(DisasContext *s, X86DecodedInsn *decode) 2041{ 2042#ifdef CONFIG_SYSTEM_ONLY 2043 gen_update_cc_op(s); 2044 gen_update_eip_next(s); 2045 gen_helper_hlt(tcg_env); 2046 s->base.is_jmp = DISAS_NORETURN; 2047#endif 2048} 2049 2050static void gen_IDIV(DisasContext *s, X86DecodedInsn *decode) 2051{ 2052 MemOp ot = decode->op[1].ot; 2053 2054 switch(ot) { 2055 case MO_8: 2056 gen_helper_idivb_AL(tcg_env, s->T0); 2057 break; 2058 case MO_16: 2059 gen_helper_idivw_AX(tcg_env, s->T0); 2060 break; 2061 default: 2062 case MO_32: 2063 gen_helper_idivl_EAX(tcg_env, s->T0); 2064 break; 2065#ifdef TARGET_X86_64 2066 case MO_64: 2067 gen_helper_idivq_EAX(tcg_env, s->T0); 2068 break; 2069#endif 2070 } 2071} 2072 2073static void gen_IMUL3(DisasContext *s, X86DecodedInsn *decode) 2074{ 2075 MemOp ot = decode->op[0].ot; 2076 TCGv cc_src_rhs; 2077 2078 switch (ot) { 2079 case MO_16: 2080 /* s->T0 already sign-extended */ 2081 tcg_gen_ext16s_tl(s->T1, s->T1); 2082 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2083 /* Compare the full result to the extension of the truncated result. */ 2084 tcg_gen_ext16s_tl(s->T1, s->T0); 2085 cc_src_rhs = s->T0; 2086 break; 2087 2088 case MO_32: 2089#ifdef TARGET_X86_64 2090 if (TCG_TARGET_REG_BITS == 64) { 2091 /* 2092 * This produces fewer TCG ops, and better code if flags are needed, 2093 * but it requires a 64-bit multiply even if they are not. Use it 2094 * only if the target has 64-bits registers. 2095 * 2096 * s->T0 is already sign-extended. 2097 */ 2098 tcg_gen_ext32s_tl(s->T1, s->T1); 2099 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2100 /* Compare the full result to the extension of the truncated result. */ 2101 tcg_gen_ext32s_tl(s->T1, s->T0); 2102 cc_src_rhs = s->T0; 2103 } else { 2104 /* Variant that only needs a 32-bit widening multiply. */ 2105 TCGv_i32 hi = tcg_temp_new_i32(); 2106 TCGv_i32 lo = tcg_temp_new_i32(); 2107 tcg_gen_trunc_tl_i32(lo, s->T0); 2108 tcg_gen_trunc_tl_i32(hi, s->T1); 2109 tcg_gen_muls2_i32(lo, hi, lo, hi); 2110 tcg_gen_extu_i32_tl(s->T0, lo); 2111 2112 cc_src_rhs = tcg_temp_new(); 2113 tcg_gen_extu_i32_tl(cc_src_rhs, hi); 2114 /* Compare the high part to the sign bit of the truncated result */ 2115 tcg_gen_sari_i32(lo, lo, 31); 2116 tcg_gen_extu_i32_tl(s->T1, lo); 2117 } 2118 break; 2119 2120 case MO_64: 2121#endif 2122 cc_src_rhs = tcg_temp_new(); 2123 tcg_gen_muls2_tl(s->T0, cc_src_rhs, s->T0, s->T1); 2124 /* Compare the high part to the sign bit of the truncated result */ 2125 tcg_gen_sari_tl(s->T1, s->T0, TARGET_LONG_BITS - 1); 2126 break; 2127 2128 default: 2129 g_assert_not_reached(); 2130 } 2131 2132 tcg_gen_sub_tl(s->T1, s->T1, cc_src_rhs); 2133 prepare_update2_cc(decode, s, CC_OP_MULB + ot); 2134} 2135 2136static void gen_IMUL(DisasContext *s, X86DecodedInsn *decode) 2137{ 2138 MemOp ot = decode->op[1].ot; 2139 TCGv cc_src_rhs; 2140 2141 switch (ot) { 2142 case MO_8: 2143 /* s->T0 already sign-extended */ 2144 tcg_gen_ext8s_tl(s->T1, s->T1); 2145 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2146 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2147 /* Compare the full result to the extension of the truncated result. */ 2148 tcg_gen_ext8s_tl(s->T1, s->T0); 2149 cc_src_rhs = s->T0; 2150 break; 2151 2152 case MO_16: 2153 /* s->T0 already sign-extended */ 2154 tcg_gen_ext16s_tl(s->T1, s->T1); 2155 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2156 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2157 tcg_gen_shri_tl(s->T1, s->T0, 16); 2158 gen_op_mov_reg_v(s, MO_16, R_EDX, s->T1); 2159 /* Compare the full result to the extension of the truncated result. */ 2160 tcg_gen_ext16s_tl(s->T1, s->T0); 2161 cc_src_rhs = s->T0; 2162 break; 2163 2164 case MO_32: 2165#ifdef TARGET_X86_64 2166 /* s->T0 already sign-extended */ 2167 tcg_gen_ext32s_tl(s->T1, s->T1); 2168 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2169 tcg_gen_ext32u_tl(cpu_regs[R_EAX], s->T0); 2170 tcg_gen_shri_tl(cpu_regs[R_EDX], s->T0, 32); 2171 /* Compare the full result to the extension of the truncated result. */ 2172 tcg_gen_ext32s_tl(s->T1, s->T0); 2173 cc_src_rhs = s->T0; 2174 break; 2175 2176 case MO_64: 2177#endif 2178 tcg_gen_muls2_tl(s->T0, cpu_regs[R_EDX], s->T0, s->T1); 2179 tcg_gen_mov_tl(cpu_regs[R_EAX], s->T0); 2180 2181 /* Compare the high part to the sign bit of the truncated result */ 2182 tcg_gen_negsetcondi_tl(TCG_COND_LT, s->T1, s->T0, 0); 2183 cc_src_rhs = cpu_regs[R_EDX]; 2184 break; 2185 2186 default: 2187 g_assert_not_reached(); 2188 } 2189 2190 tcg_gen_sub_tl(s->T1, s->T1, cc_src_rhs); 2191 prepare_update2_cc(decode, s, CC_OP_MULB + ot); 2192} 2193 2194static void gen_IN(DisasContext *s, X86DecodedInsn *decode) 2195{ 2196 MemOp ot = decode->op[0].ot; 2197 TCGv_i32 port = tcg_temp_new_i32(); 2198 2199 tcg_gen_trunc_tl_i32(port, s->T0); 2200 tcg_gen_ext16u_i32(port, port); 2201 if (!gen_check_io(s, ot, port, SVM_IOIO_TYPE_MASK)) { 2202 return; 2203 } 2204 translator_io_start(&s->base); 2205 gen_helper_in_func(ot, s->T0, port); 2206 gen_writeback(s, decode, 0, s->T0); 2207 gen_bpt_io(s, port, ot); 2208} 2209 2210static void gen_INC(DisasContext *s, X86DecodedInsn *decode) 2211{ 2212 MemOp ot = decode->op[1].ot; 2213 2214 tcg_gen_movi_tl(s->T1, 1); 2215 if (s->prefix & PREFIX_LOCK) { 2216 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 2217 s->mem_index, ot | MO_LE); 2218 } else { 2219 tcg_gen_add_tl(s->T0, s->T0, s->T1); 2220 } 2221 prepare_update_cc_incdec(decode, s, CC_OP_INCB + ot); 2222} 2223 2224static void gen_INS(DisasContext *s, X86DecodedInsn *decode) 2225{ 2226 MemOp ot = decode->op[1].ot; 2227 TCGv_i32 port = tcg_temp_new_i32(); 2228 2229 tcg_gen_trunc_tl_i32(port, s->T1); 2230 tcg_gen_ext16u_i32(port, port); 2231 if (!gen_check_io(s, ot, port, 2232 SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { 2233 return; 2234 } 2235 2236 translator_io_start(&s->base); 2237 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2238 gen_repz(s, ot, gen_ins); 2239 } else { 2240 gen_ins(s, ot); 2241 } 2242} 2243 2244static void gen_INSERTQ_i(DisasContext *s, X86DecodedInsn *decode) 2245{ 2246 TCGv_i32 length = tcg_constant_i32(decode->immediate & 63); 2247 TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63); 2248 2249 gen_helper_insertq_i(tcg_env, OP_PTR0, OP_PTR1, index, length); 2250} 2251 2252static void gen_INSERTQ_r(DisasContext *s, X86DecodedInsn *decode) 2253{ 2254 gen_helper_insertq_r(tcg_env, OP_PTR0, OP_PTR2); 2255} 2256 2257static void gen_INT(DisasContext *s, X86DecodedInsn *decode) 2258{ 2259 gen_interrupt(s, decode->immediate); 2260} 2261 2262static void gen_INT1(DisasContext *s, X86DecodedInsn *decode) 2263{ 2264 gen_update_cc_op(s); 2265 gen_update_eip_next(s); 2266 gen_helper_icebp(tcg_env); 2267 s->base.is_jmp = DISAS_NORETURN; 2268} 2269 2270static void gen_INT3(DisasContext *s, X86DecodedInsn *decode) 2271{ 2272 gen_interrupt(s, EXCP03_INT3); 2273} 2274 2275static void gen_INTO(DisasContext *s, X86DecodedInsn *decode) 2276{ 2277 gen_update_cc_op(s); 2278 gen_update_eip_cur(s); 2279 gen_helper_into(tcg_env, cur_insn_len_i32(s)); 2280} 2281 2282static void gen_IRET(DisasContext *s, X86DecodedInsn *decode) 2283{ 2284 if (!PE(s) || VM86(s)) { 2285 gen_helper_iret_real(tcg_env, tcg_constant_i32(s->dflag - 1)); 2286 } else { 2287 gen_helper_iret_protected(tcg_env, tcg_constant_i32(s->dflag - 1), 2288 eip_next_i32(s)); 2289 } 2290 assume_cc_op(s, CC_OP_EFLAGS); 2291 s->base.is_jmp = DISAS_EOB_ONLY; 2292} 2293 2294static void gen_Jcc(DisasContext *s, X86DecodedInsn *decode) 2295{ 2296 gen_bnd_jmp(s); 2297 gen_jcc(s, decode->b & 0xf, decode->immediate); 2298} 2299 2300static void gen_JCXZ(DisasContext *s, X86DecodedInsn *decode) 2301{ 2302 TCGLabel *taken = gen_new_label(); 2303 2304 gen_update_cc_op(s); 2305 gen_op_jz_ecx(s, taken); 2306 gen_conditional_jump_labels(s, decode->immediate, NULL, taken); 2307} 2308 2309static void gen_JMP(DisasContext *s, X86DecodedInsn *decode) 2310{ 2311 gen_update_cc_op(s); 2312 gen_jmp_rel(s, s->dflag, decode->immediate, 0); 2313} 2314 2315static void gen_JMP_m(DisasContext *s, X86DecodedInsn *decode) 2316{ 2317 gen_op_jmp_v(s, s->T0); 2318 gen_bnd_jmp(s); 2319 s->base.is_jmp = DISAS_JUMP; 2320} 2321 2322static void gen_JMPF(DisasContext *s, X86DecodedInsn *decode) 2323{ 2324 gen_far_jmp(s); 2325} 2326 2327static void gen_JMPF_m(DisasContext *s, X86DecodedInsn *decode) 2328{ 2329 MemOp ot = decode->op[1].ot; 2330 2331 gen_op_ld_v(s, ot, s->T0, s->A0); 2332 gen_add_A0_im(s, 1 << ot); 2333 gen_op_ld_v(s, MO_16, s->T1, s->A0); 2334 gen_far_jmp(s); 2335} 2336 2337static void gen_LAHF(DisasContext *s, X86DecodedInsn *decode) 2338{ 2339 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) { 2340 return gen_illegal_opcode(s); 2341 } 2342 gen_compute_eflags(s); 2343 /* Note: gen_compute_eflags() only gives the condition codes */ 2344 tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02); 2345 tcg_gen_deposit_tl(cpu_regs[R_EAX], cpu_regs[R_EAX], s->T0, 8, 8); 2346} 2347 2348static void gen_LAR(DisasContext *s, X86DecodedInsn *decode) 2349{ 2350 MemOp ot = decode->op[0].ot; 2351 TCGv result = tcg_temp_new(); 2352 TCGv dest; 2353 2354 gen_compute_eflags(s); 2355 gen_update_cc_op(s); 2356 gen_helper_lar(result, tcg_env, s->T0); 2357 2358 /* Perform writeback here to skip it if ZF=0. */ 2359 decode->op[0].unit = X86_OP_SKIP; 2360 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, result, result); 2361 tcg_gen_movcond_tl(TCG_COND_TSTNE, dest, cpu_cc_src, tcg_constant_tl(CC_Z), 2362 result, dest); 2363} 2364 2365static void gen_LDMXCSR(DisasContext *s, X86DecodedInsn *decode) 2366{ 2367 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 2368 gen_helper_ldmxcsr(tcg_env, s->tmp2_i32); 2369} 2370 2371static void gen_lxx_seg(DisasContext *s, X86DecodedInsn *decode, int seg) 2372{ 2373 MemOp ot = decode->op[0].ot; 2374 2375 /* Offset already in s->T0. */ 2376 gen_add_A0_im(s, 1 << ot); 2377 gen_op_ld_v(s, MO_16, s->T1, s->A0); 2378 2379 /* load the segment here to handle exceptions properly */ 2380 gen_movl_seg(s, seg, s->T1); 2381} 2382 2383static void gen_LDS(DisasContext *s, X86DecodedInsn *decode) 2384{ 2385 gen_lxx_seg(s, decode, R_DS); 2386} 2387 2388static void gen_LEA(DisasContext *s, X86DecodedInsn *decode) 2389{ 2390 TCGv ea = gen_lea_modrm_1(s, decode->mem, false); 2391 gen_lea_v_seg_dest(s, s->aflag, s->T0, ea, -1, -1); 2392} 2393 2394static void gen_LEAVE(DisasContext *s, X86DecodedInsn *decode) 2395{ 2396 gen_leave(s); 2397} 2398 2399static void gen_LES(DisasContext *s, X86DecodedInsn *decode) 2400{ 2401 gen_lxx_seg(s, decode, R_ES); 2402} 2403 2404static void gen_LFENCE(DisasContext *s, X86DecodedInsn *decode) 2405{ 2406 tcg_gen_mb(TCG_MO_LD_LD | TCG_BAR_SC); 2407} 2408 2409static void gen_LFS(DisasContext *s, X86DecodedInsn *decode) 2410{ 2411 gen_lxx_seg(s, decode, R_FS); 2412} 2413 2414static void gen_LGS(DisasContext *s, X86DecodedInsn *decode) 2415{ 2416 gen_lxx_seg(s, decode, R_GS); 2417} 2418 2419static void gen_LODS(DisasContext *s, X86DecodedInsn *decode) 2420{ 2421 MemOp ot = decode->op[1].ot; 2422 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2423 gen_repz(s, ot, gen_lods); 2424 } else { 2425 gen_lods(s, ot); 2426 } 2427} 2428 2429static void gen_LOOP(DisasContext *s, X86DecodedInsn *decode) 2430{ 2431 TCGLabel *taken = gen_new_label(); 2432 2433 gen_update_cc_op(s); 2434 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2435 gen_op_jnz_ecx(s, taken); 2436 gen_conditional_jump_labels(s, decode->immediate, NULL, taken); 2437} 2438 2439static void gen_LOOPE(DisasContext *s, X86DecodedInsn *decode) 2440{ 2441 TCGLabel *taken = gen_new_label(); 2442 TCGLabel *not_taken = gen_new_label(); 2443 2444 gen_update_cc_op(s); 2445 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2446 gen_op_jz_ecx(s, not_taken); 2447 gen_jcc1(s, (JCC_Z << 1), taken); /* jz taken */ 2448 gen_conditional_jump_labels(s, decode->immediate, not_taken, taken); 2449} 2450 2451static void gen_LOOPNE(DisasContext *s, X86DecodedInsn *decode) 2452{ 2453 TCGLabel *taken = gen_new_label(); 2454 TCGLabel *not_taken = gen_new_label(); 2455 2456 gen_update_cc_op(s); 2457 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2458 gen_op_jz_ecx(s, not_taken); 2459 gen_jcc1(s, (JCC_Z << 1) | 1, taken); /* jnz taken */ 2460 gen_conditional_jump_labels(s, decode->immediate, not_taken, taken); 2461} 2462 2463static void gen_LSL(DisasContext *s, X86DecodedInsn *decode) 2464{ 2465 MemOp ot = decode->op[0].ot; 2466 TCGv result = tcg_temp_new(); 2467 TCGv dest; 2468 2469 gen_compute_eflags(s); 2470 gen_update_cc_op(s); 2471 gen_helper_lsl(result, tcg_env, s->T0); 2472 2473 /* Perform writeback here to skip it if ZF=0. */ 2474 decode->op[0].unit = X86_OP_SKIP; 2475 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, result, result); 2476 tcg_gen_movcond_tl(TCG_COND_TSTNE, dest, cpu_cc_src, tcg_constant_tl(CC_Z), 2477 result, dest); 2478} 2479 2480static void gen_LSS(DisasContext *s, X86DecodedInsn *decode) 2481{ 2482 gen_lxx_seg(s, decode, R_SS); 2483} 2484 2485static void gen_LZCNT(DisasContext *s, X86DecodedInsn *decode) 2486{ 2487 MemOp ot = decode->op[0].ot; 2488 2489 /* C bit (cc_src) is defined related to the input. */ 2490 decode->cc_src = tcg_temp_new(); 2491 decode->cc_dst = s->T0; 2492 decode->cc_op = CC_OP_BMILGB + ot; 2493 tcg_gen_mov_tl(decode->cc_src, s->T0); 2494 2495 /* 2496 * Reduce the target_ulong result by the number of zeros that 2497 * we expect to find at the top. 2498 */ 2499 tcg_gen_clzi_tl(s->T0, s->T0, TARGET_LONG_BITS); 2500 tcg_gen_subi_tl(s->T0, s->T0, TARGET_LONG_BITS - (8 << ot)); 2501} 2502 2503static void gen_MFENCE(DisasContext *s, X86DecodedInsn *decode) 2504{ 2505 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 2506} 2507 2508static void gen_MOV(DisasContext *s, X86DecodedInsn *decode) 2509{ 2510 /* nothing to do! */ 2511} 2512#define gen_NOP gen_MOV 2513 2514static void gen_MASKMOV(DisasContext *s, X86DecodedInsn *decode) 2515{ 2516 gen_lea_v_seg(s, cpu_regs[R_EDI], R_DS, s->override); 2517 2518 if (s->prefix & PREFIX_DATA) { 2519 gen_helper_maskmov_xmm(tcg_env, OP_PTR1, OP_PTR2, s->A0); 2520 } else { 2521 gen_helper_maskmov_mmx(tcg_env, OP_PTR1, OP_PTR2, s->A0); 2522 } 2523} 2524 2525static void gen_MOVBE(DisasContext *s, X86DecodedInsn *decode) 2526{ 2527 MemOp ot = decode->op[0].ot; 2528 2529 /* M operand type does not load/store */ 2530 if (decode->e.op0 == X86_TYPE_M) { 2531 tcg_gen_qemu_st_tl(s->T0, s->A0, s->mem_index, ot | MO_BE); 2532 } else { 2533 tcg_gen_qemu_ld_tl(s->T0, s->A0, s->mem_index, ot | MO_BE); 2534 } 2535} 2536 2537static void gen_MOVD_from(DisasContext *s, X86DecodedInsn *decode) 2538{ 2539 MemOp ot = decode->op[2].ot; 2540 2541 switch (ot) { 2542 case MO_32: 2543#ifdef TARGET_X86_64 2544 tcg_gen_ld32u_tl(s->T0, tcg_env, decode->op[2].offset); 2545 break; 2546 case MO_64: 2547#endif 2548 tcg_gen_ld_tl(s->T0, tcg_env, decode->op[2].offset); 2549 break; 2550 default: 2551 abort(); 2552 } 2553} 2554 2555static void gen_MOVD_to(DisasContext *s, X86DecodedInsn *decode) 2556{ 2557 MemOp ot = decode->op[2].ot; 2558 int vec_len = vector_len(s, decode); 2559 int lo_ofs = vector_elem_offset(&decode->op[0], ot, 0); 2560 2561 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2562 2563 switch (ot) { 2564 case MO_32: 2565#ifdef TARGET_X86_64 2566 tcg_gen_st32_tl(s->T1, tcg_env, lo_ofs); 2567 break; 2568 case MO_64: 2569#endif 2570 tcg_gen_st_tl(s->T1, tcg_env, lo_ofs); 2571 break; 2572 default: 2573 g_assert_not_reached(); 2574 } 2575} 2576 2577static void gen_MOVDQ(DisasContext *s, X86DecodedInsn *decode) 2578{ 2579 gen_store_sse(s, decode, decode->op[2].offset); 2580} 2581 2582static void gen_MOVMSK(DisasContext *s, X86DecodedInsn *decode) 2583{ 2584 typeof(gen_helper_movmskps_ymm) *ps, *pd, *fn; 2585 ps = s->vex_l ? gen_helper_movmskps_ymm : gen_helper_movmskps_xmm; 2586 pd = s->vex_l ? gen_helper_movmskpd_ymm : gen_helper_movmskpd_xmm; 2587 fn = s->prefix & PREFIX_DATA ? pd : ps; 2588 fn(s->tmp2_i32, tcg_env, OP_PTR2); 2589 tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); 2590} 2591 2592static void gen_MOVQ(DisasContext *s, X86DecodedInsn *decode) 2593{ 2594 int vec_len = vector_len(s, decode); 2595 int lo_ofs = vector_elem_offset(&decode->op[0], MO_64, 0); 2596 2597 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset); 2598 if (decode->op[0].has_ea) { 2599 tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 2600 } else { 2601 /* 2602 * tcg_gen_gvec_dup_i64(MO_64, op0.offset, 8, vec_len, s->tmp1_64) would 2603 * seem to work, but it does not on big-endian platforms; the cleared parts 2604 * are always at higher addresses, but cross-endian emulation inverts the 2605 * byte order so that the cleared parts need to be at *lower* addresses. 2606 * Because oprsz is 8, we see this here even for SSE; but more in general, 2607 * it disqualifies using oprsz < maxsz to emulate VEX128. 2608 */ 2609 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2610 tcg_gen_st_i64(s->tmp1_i64, tcg_env, lo_ofs); 2611 } 2612} 2613 2614static void gen_MOVq_dq(DisasContext *s, X86DecodedInsn *decode) 2615{ 2616 gen_helper_enter_mmx(tcg_env); 2617 /* Otherwise the same as any other movq. */ 2618 return gen_MOVQ(s, decode); 2619} 2620 2621static void gen_MOVS(DisasContext *s, X86DecodedInsn *decode) 2622{ 2623 MemOp ot = decode->op[2].ot; 2624 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2625 gen_repz(s, ot, gen_movs); 2626 } else { 2627 gen_movs(s, ot); 2628 } 2629} 2630 2631static void gen_MUL(DisasContext *s, X86DecodedInsn *decode) 2632{ 2633 MemOp ot = decode->op[1].ot; 2634 2635 switch (ot) { 2636 case MO_8: 2637 /* s->T0 already zero-extended */ 2638 tcg_gen_ext8u_tl(s->T1, s->T1); 2639 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2640 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2641 tcg_gen_andi_tl(s->T1, s->T0, 0xff00); 2642 decode->cc_dst = s->T0; 2643 decode->cc_src = s->T1; 2644 break; 2645 2646 case MO_16: 2647 /* s->T0 already zero-extended */ 2648 tcg_gen_ext16u_tl(s->T1, s->T1); 2649 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2650 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2651 tcg_gen_shri_tl(s->T1, s->T0, 16); 2652 gen_op_mov_reg_v(s, MO_16, R_EDX, s->T1); 2653 decode->cc_dst = s->T0; 2654 decode->cc_src = s->T1; 2655 break; 2656 2657 case MO_32: 2658#ifdef TARGET_X86_64 2659 /* s->T0 already zero-extended */ 2660 tcg_gen_ext32u_tl(s->T1, s->T1); 2661 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2662 tcg_gen_ext32u_tl(cpu_regs[R_EAX], s->T0); 2663 tcg_gen_shri_tl(cpu_regs[R_EDX], s->T0, 32); 2664 decode->cc_dst = cpu_regs[R_EAX]; 2665 decode->cc_src = cpu_regs[R_EDX]; 2666 break; 2667 2668 case MO_64: 2669#endif 2670 tcg_gen_mulu2_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->T0, s->T1); 2671 decode->cc_dst = cpu_regs[R_EAX]; 2672 decode->cc_src = cpu_regs[R_EDX]; 2673 break; 2674 2675 default: 2676 g_assert_not_reached(); 2677 } 2678 2679 decode->cc_op = CC_OP_MULB + ot; 2680} 2681 2682static void gen_MULX(DisasContext *s, X86DecodedInsn *decode) 2683{ 2684 MemOp ot = decode->op[0].ot; 2685 2686 /* low part of result in VEX.vvvv, high in MODRM */ 2687 switch (ot) { 2688 case MO_32: 2689#ifdef TARGET_X86_64 2690 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 2691 tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); 2692 tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32, 2693 s->tmp2_i32, s->tmp3_i32); 2694 tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], s->tmp2_i32); 2695 tcg_gen_extu_i32_tl(s->T0, s->tmp3_i32); 2696 break; 2697 2698 case MO_64: 2699#endif 2700 tcg_gen_mulu2_tl(cpu_regs[s->vex_v], s->T0, s->T0, s->T1); 2701 break; 2702 2703 default: 2704 g_assert_not_reached(); 2705 } 2706} 2707 2708static void gen_NEG(DisasContext *s, X86DecodedInsn *decode) 2709{ 2710 MemOp ot = decode->op[0].ot; 2711 TCGv oldv = tcg_temp_new(); 2712 2713 if (s->prefix & PREFIX_LOCK) { 2714 TCGv newv = tcg_temp_new(); 2715 TCGv cmpv = tcg_temp_new(); 2716 TCGLabel *label1 = gen_new_label(); 2717 2718 gen_set_label(label1); 2719 gen_op_ld_v(s, ot, oldv, s->A0); 2720 tcg_gen_neg_tl(newv, oldv); 2721 tcg_gen_atomic_cmpxchg_tl(cmpv, s->A0, oldv, newv, 2722 s->mem_index, ot | MO_LE); 2723 tcg_gen_brcond_tl(TCG_COND_NE, oldv, cmpv, label1); 2724 } else { 2725 tcg_gen_mov_tl(oldv, s->T0); 2726 } 2727 tcg_gen_neg_tl(s->T0, oldv); 2728 2729 decode->cc_dst = s->T0; 2730 decode->cc_src = oldv; 2731 tcg_gen_movi_tl(s->cc_srcT, 0); 2732 decode->cc_op = CC_OP_SUBB + ot; 2733} 2734 2735static void gen_NOT(DisasContext *s, X86DecodedInsn *decode) 2736{ 2737 MemOp ot = decode->op[0].ot; 2738 2739 if (s->prefix & PREFIX_LOCK) { 2740 tcg_gen_movi_tl(s->T0, ~0); 2741 tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T0, 2742 s->mem_index, ot | MO_LE); 2743 } else { 2744 tcg_gen_not_tl(s->T0, s->T0); 2745 } 2746} 2747 2748static void gen_OR(DisasContext *s, X86DecodedInsn *decode) 2749{ 2750 MemOp ot = decode->op[1].ot; 2751 2752 if (s->prefix & PREFIX_LOCK) { 2753 tcg_gen_atomic_or_fetch_tl(s->T0, s->A0, s->T1, 2754 s->mem_index, ot | MO_LE); 2755 } else { 2756 tcg_gen_or_tl(s->T0, s->T0, s->T1); 2757 } 2758 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 2759} 2760 2761static void gen_OUT(DisasContext *s, X86DecodedInsn *decode) 2762{ 2763 MemOp ot = decode->op[1].ot; 2764 TCGv_i32 port = tcg_temp_new_i32(); 2765 TCGv_i32 value = tcg_temp_new_i32(); 2766 2767 tcg_gen_trunc_tl_i32(port, s->T1); 2768 tcg_gen_ext16u_i32(port, port); 2769 if (!gen_check_io(s, ot, port, 0)) { 2770 return; 2771 } 2772 tcg_gen_trunc_tl_i32(value, s->T0); 2773 translator_io_start(&s->base); 2774 gen_helper_out_func(ot, port, value); 2775 gen_bpt_io(s, port, ot); 2776} 2777 2778static void gen_OUTS(DisasContext *s, X86DecodedInsn *decode) 2779{ 2780 MemOp ot = decode->op[1].ot; 2781 TCGv_i32 port = tcg_temp_new_i32(); 2782 2783 tcg_gen_trunc_tl_i32(port, s->T1); 2784 tcg_gen_ext16u_i32(port, port); 2785 if (!gen_check_io(s, ot, port, SVM_IOIO_STR_MASK)) { 2786 return; 2787 } 2788 2789 translator_io_start(&s->base); 2790 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2791 gen_repz(s, ot, gen_outs); 2792 } else { 2793 gen_outs(s, ot); 2794 } 2795} 2796 2797static void gen_PALIGNR(DisasContext *s, X86DecodedInsn *decode) 2798{ 2799 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2800 if (!(s->prefix & PREFIX_DATA)) { 2801 gen_helper_palignr_mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2802 } else if (!s->vex_l) { 2803 gen_helper_palignr_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2804 } else { 2805 gen_helper_palignr_ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2806 } 2807} 2808 2809static void gen_PANDN(DisasContext *s, X86DecodedInsn *decode) 2810{ 2811 int vec_len = vector_len(s, decode); 2812 2813 /* Careful, operand order is reversed! */ 2814 tcg_gen_gvec_andc(MO_64, 2815 decode->op[0].offset, decode->op[2].offset, 2816 decode->op[1].offset, vec_len, vec_len); 2817} 2818 2819static void gen_PAUSE(DisasContext *s, X86DecodedInsn *decode) 2820{ 2821 gen_update_cc_op(s); 2822 gen_update_eip_next(s); 2823 gen_helper_pause(tcg_env); 2824 s->base.is_jmp = DISAS_NORETURN; 2825} 2826 2827static void gen_PCMPESTRI(DisasContext *s, X86DecodedInsn *decode) 2828{ 2829 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2830 gen_helper_pcmpestri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2831 assume_cc_op(s, CC_OP_EFLAGS); 2832} 2833 2834static void gen_PCMPESTRM(DisasContext *s, X86DecodedInsn *decode) 2835{ 2836 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2837 gen_helper_pcmpestrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2838 assume_cc_op(s, CC_OP_EFLAGS); 2839 if ((s->prefix & PREFIX_VEX) && !s->vex_l) { 2840 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)), 2841 16, 16, 0); 2842 } 2843} 2844 2845static void gen_PCMPISTRI(DisasContext *s, X86DecodedInsn *decode) 2846{ 2847 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2848 gen_helper_pcmpistri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2849 assume_cc_op(s, CC_OP_EFLAGS); 2850} 2851 2852static void gen_PCMPISTRM(DisasContext *s, X86DecodedInsn *decode) 2853{ 2854 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2855 gen_helper_pcmpistrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2856 assume_cc_op(s, CC_OP_EFLAGS); 2857 if ((s->prefix & PREFIX_VEX) && !s->vex_l) { 2858 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)), 2859 16, 16, 0); 2860 } 2861} 2862 2863static void gen_PDEP(DisasContext *s, X86DecodedInsn *decode) 2864{ 2865 gen_helper_pdep(s->T0, s->T0, s->T1); 2866} 2867 2868static void gen_PEXT(DisasContext *s, X86DecodedInsn *decode) 2869{ 2870 gen_helper_pext(s->T0, s->T0, s->T1); 2871} 2872 2873static inline void gen_pextr(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 2874{ 2875 int vec_len = vector_len(s, decode); 2876 int mask = (vec_len >> ot) - 1; 2877 int val = decode->immediate & mask; 2878 2879 switch (ot) { 2880 case MO_8: 2881 tcg_gen_ld8u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2882 break; 2883 case MO_16: 2884 tcg_gen_ld16u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2885 break; 2886 case MO_32: 2887#ifdef TARGET_X86_64 2888 tcg_gen_ld32u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2889 break; 2890 case MO_64: 2891#endif 2892 tcg_gen_ld_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2893 break; 2894 default: 2895 abort(); 2896 } 2897} 2898 2899static void gen_PEXTRB(DisasContext *s, X86DecodedInsn *decode) 2900{ 2901 gen_pextr(s, decode, MO_8); 2902} 2903 2904static void gen_PEXTRW(DisasContext *s, X86DecodedInsn *decode) 2905{ 2906 gen_pextr(s, decode, MO_16); 2907} 2908 2909static void gen_PEXTR(DisasContext *s, X86DecodedInsn *decode) 2910{ 2911 MemOp ot = decode->op[0].ot; 2912 gen_pextr(s, decode, ot); 2913} 2914 2915static inline void gen_pinsr(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 2916{ 2917 int vec_len = vector_len(s, decode); 2918 int mask = (vec_len >> ot) - 1; 2919 int val = decode->immediate & mask; 2920 2921 if (decode->op[1].offset != decode->op[0].offset) { 2922 assert(vec_len == 16); 2923 gen_store_sse(s, decode, decode->op[1].offset); 2924 } 2925 2926 switch (ot) { 2927 case MO_8: 2928 tcg_gen_st8_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2929 break; 2930 case MO_16: 2931 tcg_gen_st16_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2932 break; 2933 case MO_32: 2934#ifdef TARGET_X86_64 2935 tcg_gen_st32_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2936 break; 2937 case MO_64: 2938#endif 2939 tcg_gen_st_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2940 break; 2941 default: 2942 abort(); 2943 } 2944} 2945 2946static void gen_PINSRB(DisasContext *s, X86DecodedInsn *decode) 2947{ 2948 gen_pinsr(s, decode, MO_8); 2949} 2950 2951static void gen_PINSRW(DisasContext *s, X86DecodedInsn *decode) 2952{ 2953 gen_pinsr(s, decode, MO_16); 2954} 2955 2956static void gen_PINSR(DisasContext *s, X86DecodedInsn *decode) 2957{ 2958 gen_pinsr(s, decode, decode->op[2].ot); 2959} 2960 2961static void gen_pmovmskb_i64(TCGv_i64 d, TCGv_i64 s) 2962{ 2963 TCGv_i64 t = tcg_temp_new_i64(); 2964 2965 tcg_gen_andi_i64(d, s, 0x8080808080808080ull); 2966 2967 /* 2968 * After each shift+or pair: 2969 * 0: a.......b.......c.......d.......e.......f.......g.......h....... 2970 * 7: ab......bc......cd......de......ef......fg......gh......h....... 2971 * 14: abcd....bcde....cdef....defg....efgh....fgh.....gh......h....... 2972 * 28: abcdefghbcdefgh.cdefgh..defgh...efgh....fgh.....gh......h....... 2973 * The result is left in the high bits of the word. 2974 */ 2975 tcg_gen_shli_i64(t, d, 7); 2976 tcg_gen_or_i64(d, d, t); 2977 tcg_gen_shli_i64(t, d, 14); 2978 tcg_gen_or_i64(d, d, t); 2979 tcg_gen_shli_i64(t, d, 28); 2980 tcg_gen_or_i64(d, d, t); 2981} 2982 2983static void gen_pmovmskb_vec(unsigned vece, TCGv_vec d, TCGv_vec s) 2984{ 2985 TCGv_vec t = tcg_temp_new_vec_matching(d); 2986 TCGv_vec m = tcg_constant_vec_matching(d, MO_8, 0x80); 2987 2988 /* See above */ 2989 tcg_gen_and_vec(vece, d, s, m); 2990 tcg_gen_shli_vec(vece, t, d, 7); 2991 tcg_gen_or_vec(vece, d, d, t); 2992 tcg_gen_shli_vec(vece, t, d, 14); 2993 tcg_gen_or_vec(vece, d, d, t); 2994 tcg_gen_shli_vec(vece, t, d, 28); 2995 tcg_gen_or_vec(vece, d, d, t); 2996} 2997 2998static void gen_PMOVMSKB(DisasContext *s, X86DecodedInsn *decode) 2999{ 3000 static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 }; 3001 static const GVecGen2 g = { 3002 .fni8 = gen_pmovmskb_i64, 3003 .fniv = gen_pmovmskb_vec, 3004 .opt_opc = vecop_list, 3005 .vece = MO_64, 3006 .prefer_i64 = TCG_TARGET_REG_BITS == 64 3007 }; 3008 MemOp ot = decode->op[2].ot; 3009 int vec_len = vector_len(s, decode); 3010 TCGv t = tcg_temp_new(); 3011 3012 tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode->op[2].offset, 3013 vec_len, vec_len, &g); 3014 tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); 3015 while (vec_len > 8) { 3016 vec_len -= 8; 3017 if (tcg_op_supported(INDEX_op_extract2_tl, TCG_TYPE_TL, 0)) { 3018 /* 3019 * Load the next byte of the result into the high byte of T. 3020 * TCG does a similar expansion of deposit to shl+extract2; by 3021 * loading the whole word, the shift left is avoided. 3022 */ 3023#ifdef TARGET_X86_64 3024 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8))); 3025#else 3026 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L((vec_len - 1) / 4))); 3027#endif 3028 3029 tcg_gen_extract2_tl(s->T0, t, s->T0, TARGET_LONG_BITS - 8); 3030 } else { 3031 /* 3032 * The _previous_ value is deposited into bits 8 and higher of t. Because 3033 * those bits are known to be zero after ld8u, this becomes a shift+or 3034 * if deposit is not available. 3035 */ 3036 tcg_gen_ld8u_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); 3037 tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8); 3038 } 3039 } 3040} 3041 3042static void gen_POP(DisasContext *s, X86DecodedInsn *decode) 3043{ 3044 X86DecodedOp *op = &decode->op[0]; 3045 MemOp ot = gen_pop_T0(s); 3046 3047 assert(ot >= op->ot); 3048 if (op->has_ea || op->unit == X86_OP_SEG) { 3049 /* NOTE: order is important for MMU exceptions */ 3050 gen_writeback(s, decode, 0, s->T0); 3051 } 3052 3053 /* NOTE: writing back registers after update is important for pop %sp */ 3054 gen_pop_update(s, ot); 3055} 3056 3057static void gen_POPA(DisasContext *s, X86DecodedInsn *decode) 3058{ 3059 gen_popa(s); 3060} 3061 3062static void gen_POPCNT(DisasContext *s, X86DecodedInsn *decode) 3063{ 3064 decode->cc_dst = tcg_temp_new(); 3065 decode->cc_op = CC_OP_POPCNT; 3066 3067 tcg_gen_mov_tl(decode->cc_dst, s->T0); 3068 tcg_gen_ctpop_tl(s->T0, s->T0); 3069} 3070 3071static void gen_POPF(DisasContext *s, X86DecodedInsn *decode) 3072{ 3073 MemOp ot; 3074 int mask = TF_MASK | AC_MASK | ID_MASK | NT_MASK; 3075 3076 if (CPL(s) == 0) { 3077 mask |= IF_MASK | IOPL_MASK; 3078 } else if (CPL(s) <= IOPL(s)) { 3079 mask |= IF_MASK; 3080 } 3081 if (s->dflag == MO_16) { 3082 mask &= 0xffff; 3083 } 3084 3085 ot = gen_pop_T0(s); 3086 gen_helper_write_eflags(tcg_env, s->T0, tcg_constant_i32(mask)); 3087 gen_pop_update(s, ot); 3088 set_cc_op(s, CC_OP_EFLAGS); 3089 /* abort translation because TF/AC flag may change */ 3090 s->base.is_jmp = DISAS_EOB_NEXT; 3091} 3092 3093static void gen_PSHUFW(DisasContext *s, X86DecodedInsn *decode) 3094{ 3095 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 3096 gen_helper_pshufw_mmx(OP_PTR0, OP_PTR1, imm); 3097} 3098 3099static void gen_PSRLW_i(DisasContext *s, X86DecodedInsn *decode) 3100{ 3101 int vec_len = vector_len(s, decode); 3102 3103 if (decode->immediate >= 16) { 3104 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3105 } else { 3106 tcg_gen_gvec_shri(MO_16, 3107 decode->op[0].offset, decode->op[1].offset, 3108 decode->immediate, vec_len, vec_len); 3109 } 3110} 3111 3112static void gen_PSLLW_i(DisasContext *s, X86DecodedInsn *decode) 3113{ 3114 int vec_len = vector_len(s, decode); 3115 3116 if (decode->immediate >= 16) { 3117 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3118 } else { 3119 tcg_gen_gvec_shli(MO_16, 3120 decode->op[0].offset, decode->op[1].offset, 3121 decode->immediate, vec_len, vec_len); 3122 } 3123} 3124 3125static void gen_PSRAW_i(DisasContext *s, X86DecodedInsn *decode) 3126{ 3127 int vec_len = vector_len(s, decode); 3128 3129 if (decode->immediate >= 16) { 3130 decode->immediate = 15; 3131 } 3132 tcg_gen_gvec_sari(MO_16, 3133 decode->op[0].offset, decode->op[1].offset, 3134 decode->immediate, vec_len, vec_len); 3135} 3136 3137static void gen_PSRLD_i(DisasContext *s, X86DecodedInsn *decode) 3138{ 3139 int vec_len = vector_len(s, decode); 3140 3141 if (decode->immediate >= 32) { 3142 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3143 } else { 3144 tcg_gen_gvec_shri(MO_32, 3145 decode->op[0].offset, decode->op[1].offset, 3146 decode->immediate, vec_len, vec_len); 3147 } 3148} 3149 3150static void gen_PSLLD_i(DisasContext *s, X86DecodedInsn *decode) 3151{ 3152 int vec_len = vector_len(s, decode); 3153 3154 if (decode->immediate >= 32) { 3155 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3156 } else { 3157 tcg_gen_gvec_shli(MO_32, 3158 decode->op[0].offset, decode->op[1].offset, 3159 decode->immediate, vec_len, vec_len); 3160 } 3161} 3162 3163static void gen_PSRAD_i(DisasContext *s, X86DecodedInsn *decode) 3164{ 3165 int vec_len = vector_len(s, decode); 3166 3167 if (decode->immediate >= 32) { 3168 decode->immediate = 31; 3169 } 3170 tcg_gen_gvec_sari(MO_32, 3171 decode->op[0].offset, decode->op[1].offset, 3172 decode->immediate, vec_len, vec_len); 3173} 3174 3175static void gen_PSRLQ_i(DisasContext *s, X86DecodedInsn *decode) 3176{ 3177 int vec_len = vector_len(s, decode); 3178 3179 if (decode->immediate >= 64) { 3180 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3181 } else { 3182 tcg_gen_gvec_shri(MO_64, 3183 decode->op[0].offset, decode->op[1].offset, 3184 decode->immediate, vec_len, vec_len); 3185 } 3186} 3187 3188static void gen_PSLLQ_i(DisasContext *s, X86DecodedInsn *decode) 3189{ 3190 int vec_len = vector_len(s, decode); 3191 3192 if (decode->immediate >= 64) { 3193 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3194 } else { 3195 tcg_gen_gvec_shli(MO_64, 3196 decode->op[0].offset, decode->op[1].offset, 3197 decode->immediate, vec_len, vec_len); 3198 } 3199} 3200 3201static TCGv_ptr make_imm8u_xmm_vec(uint8_t imm, int vec_len) 3202{ 3203 MemOp ot = vec_len == 16 ? MO_128 : MO_256; 3204 TCGv_i32 imm_v = tcg_constant8u_i32(imm); 3205 TCGv_ptr ptr = tcg_temp_new_ptr(); 3206 3207 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), 3208 vec_len, vec_len, 0); 3209 3210 tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_t0)); 3211 tcg_gen_st_i32(imm_v, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0))); 3212 return ptr; 3213} 3214 3215static void gen_PSRLDQ_i(DisasContext *s, X86DecodedInsn *decode) 3216{ 3217 int vec_len = vector_len(s, decode); 3218 TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len); 3219 3220 if (s->vex_l) { 3221 gen_helper_psrldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 3222 } else { 3223 gen_helper_psrldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 3224 } 3225} 3226 3227static void gen_PSLLDQ_i(DisasContext *s, X86DecodedInsn *decode) 3228{ 3229 int vec_len = vector_len(s, decode); 3230 TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len); 3231 3232 if (s->vex_l) { 3233 gen_helper_pslldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 3234 } else { 3235 gen_helper_pslldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 3236 } 3237} 3238 3239static void gen_PUSH(DisasContext *s, X86DecodedInsn *decode) 3240{ 3241 gen_push_v(s, s->T0); 3242} 3243 3244static void gen_PUSHA(DisasContext *s, X86DecodedInsn *decode) 3245{ 3246 gen_pusha(s); 3247} 3248 3249static void gen_PUSHF(DisasContext *s, X86DecodedInsn *decode) 3250{ 3251 gen_update_cc_op(s); 3252 gen_helper_read_eflags(s->T0, tcg_env); 3253 gen_push_v(s, s->T0); 3254} 3255 3256static MemOp gen_shift_count(DisasContext *s, X86DecodedInsn *decode, 3257 bool *can_be_zero, TCGv *count, int unit) 3258{ 3259 MemOp ot = decode->op[0].ot; 3260 int mask = (ot <= MO_32 ? 0x1f : 0x3f); 3261 3262 *can_be_zero = false; 3263 switch (unit) { 3264 case X86_OP_INT: 3265 *count = tcg_temp_new(); 3266 tcg_gen_andi_tl(*count, cpu_regs[R_ECX], mask); 3267 *can_be_zero = true; 3268 break; 3269 3270 case X86_OP_IMM: 3271 if ((decode->immediate & mask) == 0) { 3272 *count = NULL; 3273 break; 3274 } 3275 *count = tcg_temp_new(); 3276 tcg_gen_movi_tl(*count, decode->immediate & mask); 3277 break; 3278 3279 case X86_OP_SKIP: 3280 *count = tcg_temp_new(); 3281 tcg_gen_movi_tl(*count, 1); 3282 break; 3283 3284 default: 3285 g_assert_not_reached(); 3286 } 3287 3288 return ot; 3289} 3290 3291/* 3292 * Compute existing flags in decode->cc_src, for gen_* functions that wants 3293 * to set the cc_op set to CC_OP_ADCOX. In particular, this allows rotate 3294 * operations to compute the carry in decode->cc_dst and the overflow in 3295 * decode->cc_src2. 3296 * 3297 * If need_flags is true, decode->cc_dst and decode->cc_src2 are preloaded 3298 * with the value of CF and OF before the instruction, so that it is possible 3299 * to keep the flags unmodified. 3300 * 3301 * Return true if carry could be made available cheaply as a 1-bit value in 3302 * decode->cc_dst (trying a bit harder if want_carry is true). If false is 3303 * returned, decode->cc_dst is uninitialized and the carry is only available 3304 * as bit 0 of decode->cc_src. 3305 */ 3306static bool gen_eflags_adcox(DisasContext *s, X86DecodedInsn *decode, bool want_carry, bool need_flags) 3307{ 3308 bool got_cf = false; 3309 bool got_of = false; 3310 3311 decode->cc_dst = tcg_temp_new(); 3312 decode->cc_src = tcg_temp_new(); 3313 decode->cc_src2 = tcg_temp_new(); 3314 decode->cc_op = CC_OP_ADCOX; 3315 3316 /* A lot more cc_ops could be "optimized" to avoid the extracts at 3317 * the end (INC/DEC, BMILG, MUL), but they are all really unlikely 3318 * to be followed by rotations within the same basic block. 3319 */ 3320 switch (s->cc_op) { 3321 case CC_OP_ADCOX: 3322 /* No need to compute the full EFLAGS, CF/OF are already isolated. */ 3323 tcg_gen_mov_tl(decode->cc_src, cpu_cc_src); 3324 if (need_flags) { 3325 tcg_gen_mov_tl(decode->cc_src2, cpu_cc_src2); 3326 got_of = true; 3327 } 3328 if (want_carry || need_flags) { 3329 tcg_gen_mov_tl(decode->cc_dst, cpu_cc_dst); 3330 got_cf = true; 3331 } 3332 break; 3333 3334 case CC_OP_LOGICB ... CC_OP_LOGICQ: 3335 /* CF and OF are zero, do it just because it's easy. */ 3336 gen_mov_eflags(s, decode->cc_src); 3337 if (need_flags) { 3338 tcg_gen_movi_tl(decode->cc_src2, 0); 3339 got_of = true; 3340 } 3341 if (want_carry || need_flags) { 3342 tcg_gen_movi_tl(decode->cc_dst, 0); 3343 got_cf = true; 3344 } 3345 break; 3346 3347 case CC_OP_SARB ... CC_OP_SARQ: 3348 /* 3349 * SHR/RCR/SHR/RCR/... is a relatively common occurrence of RCR. 3350 * By computing CF without using eflags, the calls to cc_compute_all 3351 * can be eliminated as dead code (except for the last RCR). 3352 */ 3353 if (want_carry || need_flags) { 3354 tcg_gen_andi_tl(decode->cc_dst, cpu_cc_src, 1); 3355 got_cf = true; 3356 } 3357 gen_mov_eflags(s, decode->cc_src); 3358 break; 3359 3360 case CC_OP_SHLB ... CC_OP_SHLQ: 3361 /* 3362 * Likewise for SHL/RCL/SHL/RCL/... but, if CF is not in the sign 3363 * bit, we might as well fish CF out of EFLAGS and save a shift. 3364 */ 3365 if (want_carry && (!need_flags || s->cc_op == CC_OP_SHLB + MO_TL)) { 3366 MemOp size = cc_op_size(s->cc_op); 3367 tcg_gen_shri_tl(decode->cc_dst, cpu_cc_src, (8 << size) - 1); 3368 got_cf = true; 3369 } 3370 gen_mov_eflags(s, decode->cc_src); 3371 break; 3372 3373 default: 3374 gen_mov_eflags(s, decode->cc_src); 3375 break; 3376 } 3377 3378 if (need_flags) { 3379 /* If the flags could be left unmodified, always load them. */ 3380 if (!got_of) { 3381 tcg_gen_extract_tl(decode->cc_src2, decode->cc_src, ctz32(CC_O), 1); 3382 got_of = true; 3383 } 3384 if (!got_cf) { 3385 tcg_gen_extract_tl(decode->cc_dst, decode->cc_src, ctz32(CC_C), 1); 3386 got_cf = true; 3387 } 3388 } 3389 return got_cf; 3390} 3391 3392static void gen_rot_overflow(X86DecodedInsn *decode, TCGv result, TCGv old, 3393 bool can_be_zero, TCGv count) 3394{ 3395 MemOp ot = decode->op[0].ot; 3396 TCGv temp = can_be_zero ? tcg_temp_new() : decode->cc_src2; 3397 3398 tcg_gen_xor_tl(temp, old, result); 3399 tcg_gen_extract_tl(temp, temp, (8 << ot) - 1, 1); 3400 if (can_be_zero) { 3401 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src2, count, tcg_constant_tl(0), 3402 decode->cc_src2, temp); 3403 } 3404} 3405 3406/* 3407 * RCx operations are invariant modulo 8*operand_size+1. For 8 and 16-bit operands, 3408 * this is less than 0x1f (the mask applied by gen_shift_count) so reduce further. 3409 */ 3410static void gen_rotc_mod(MemOp ot, TCGv count) 3411{ 3412 TCGv temp; 3413 3414 switch (ot) { 3415 case MO_8: 3416 temp = tcg_temp_new(); 3417 tcg_gen_subi_tl(temp, count, 18); 3418 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3419 tcg_gen_subi_tl(temp, count, 9); 3420 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3421 break; 3422 3423 case MO_16: 3424 temp = tcg_temp_new(); 3425 tcg_gen_subi_tl(temp, count, 17); 3426 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3427 break; 3428 3429 default: 3430 break; 3431 } 3432} 3433 3434/* 3435 * The idea here is that the bit to the right of the new bit 0 is the 3436 * new carry, and the bit to the right of the old bit 0 is the old carry. 3437 * Just like a regular rotation, the result of the rotation is composed 3438 * from a right shifted part and a left shifted part of s->T0. The new carry 3439 * is extracted from the right-shifted portion, and the old carry is 3440 * inserted at the end of the left-shifted portion. 3441 * 3442 * Because of the separate shifts involving the carry, gen_RCL and gen_RCR 3443 * mostly operate on count-1. This also comes in handy when computing 3444 * length - count, because (length-1) - (count-1) can be computed with 3445 * a XOR, and that is commutative unlike subtraction. 3446 */ 3447static void gen_RCL(DisasContext *s, X86DecodedInsn *decode) 3448{ 3449 bool have_1bit_cin, can_be_zero; 3450 TCGv count; 3451 TCGLabel *zero_label = NULL; 3452 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3453 TCGv low, high, low_count; 3454 3455 if (!count) { 3456 return; 3457 } 3458 3459 low = tcg_temp_new(); 3460 high = tcg_temp_new(); 3461 low_count = tcg_temp_new(); 3462 3463 gen_rotc_mod(ot, count); 3464 have_1bit_cin = gen_eflags_adcox(s, decode, true, can_be_zero); 3465 if (can_be_zero) { 3466 zero_label = gen_new_label(); 3467 tcg_gen_brcondi_tl(TCG_COND_EQ, count, 0, zero_label); 3468 } 3469 3470 /* Compute high part, including incoming carry. */ 3471 if (!have_1bit_cin || tcg_op_deposit_valid(TCG_TYPE_TL, 1, TARGET_LONG_BITS - 1)) { 3472 /* high = (T0 << 1) | cin */ 3473 TCGv cin = have_1bit_cin ? decode->cc_dst : decode->cc_src; 3474 tcg_gen_deposit_tl(high, cin, s->T0, 1, TARGET_LONG_BITS - 1); 3475 } else { 3476 /* Same as above but without deposit; cin in cc_dst. */ 3477 tcg_gen_add_tl(high, s->T0, decode->cc_dst); 3478 tcg_gen_add_tl(high, high, s->T0); 3479 } 3480 tcg_gen_subi_tl(count, count, 1); 3481 tcg_gen_shl_tl(high, high, count); 3482 3483 /* Compute low part and outgoing carry, incoming s->T0 is zero extended */ 3484 tcg_gen_xori_tl(low_count, count, (8 << ot) - 1); /* LENGTH - 1 - (count - 1) */ 3485 tcg_gen_shr_tl(low, s->T0, low_count); 3486 tcg_gen_andi_tl(decode->cc_dst, low, 1); 3487 tcg_gen_shri_tl(low, low, 1); 3488 3489 /* Compute result and outgoing overflow */ 3490 tcg_gen_mov_tl(decode->cc_src2, s->T0); 3491 tcg_gen_or_tl(s->T0, low, high); 3492 gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); 3493 3494 if (zero_label) { 3495 gen_set_label(zero_label); 3496 } 3497} 3498 3499static void gen_RCR(DisasContext *s, X86DecodedInsn *decode) 3500{ 3501 bool have_1bit_cin, can_be_zero; 3502 TCGv count; 3503 TCGLabel *zero_label = NULL; 3504 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3505 TCGv low, high, high_count; 3506 3507 if (!count) { 3508 return; 3509 } 3510 3511 low = tcg_temp_new(); 3512 high = tcg_temp_new(); 3513 high_count = tcg_temp_new(); 3514 3515 gen_rotc_mod(ot, count); 3516 have_1bit_cin = gen_eflags_adcox(s, decode, true, can_be_zero); 3517 if (can_be_zero) { 3518 zero_label = gen_new_label(); 3519 tcg_gen_brcondi_tl(TCG_COND_EQ, count, 0, zero_label); 3520 } 3521 3522 /* Save incoming carry into high, it will be shifted later. */ 3523 if (!have_1bit_cin || tcg_op_deposit_valid(TCG_TYPE_TL, 1, TARGET_LONG_BITS - 1)) { 3524 TCGv cin = have_1bit_cin ? decode->cc_dst : decode->cc_src; 3525 tcg_gen_deposit_tl(high, cin, s->T0, 1, TARGET_LONG_BITS - 1); 3526 } else { 3527 /* Same as above but without deposit; cin in cc_dst. */ 3528 tcg_gen_add_tl(high, s->T0, decode->cc_dst); 3529 tcg_gen_add_tl(high, high, s->T0); 3530 } 3531 3532 /* Compute low part and outgoing carry, incoming s->T0 is zero extended */ 3533 tcg_gen_subi_tl(count, count, 1); 3534 tcg_gen_shr_tl(low, s->T0, count); 3535 tcg_gen_andi_tl(decode->cc_dst, low, 1); 3536 tcg_gen_shri_tl(low, low, 1); 3537 3538 /* Move high part to the right position */ 3539 tcg_gen_xori_tl(high_count, count, (8 << ot) - 1); /* LENGTH - 1 - (count - 1) */ 3540 tcg_gen_shl_tl(high, high, high_count); 3541 3542 /* Compute result and outgoing overflow */ 3543 tcg_gen_mov_tl(decode->cc_src2, s->T0); 3544 tcg_gen_or_tl(s->T0, low, high); 3545 gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); 3546 3547 if (zero_label) { 3548 gen_set_label(zero_label); 3549 } 3550} 3551 3552#ifdef CONFIG_USER_ONLY 3553static void gen_unreachable(DisasContext *s, X86DecodedInsn *decode) 3554{ 3555 g_assert_not_reached(); 3556} 3557#endif 3558 3559#ifndef CONFIG_USER_ONLY 3560static void gen_RDMSR(DisasContext *s, X86DecodedInsn *decode) 3561{ 3562 gen_update_cc_op(s); 3563 gen_update_eip_cur(s); 3564 gen_helper_rdmsr(tcg_env); 3565} 3566#else 3567#define gen_RDMSR gen_unreachable 3568#endif 3569 3570static void gen_RDPMC(DisasContext *s, X86DecodedInsn *decode) 3571{ 3572 gen_update_cc_op(s); 3573 gen_update_eip_cur(s); 3574 translator_io_start(&s->base); 3575 gen_helper_rdpmc(tcg_env); 3576 s->base.is_jmp = DISAS_NORETURN; 3577} 3578 3579static void gen_RDTSC(DisasContext *s, X86DecodedInsn *decode) 3580{ 3581 gen_update_cc_op(s); 3582 gen_update_eip_cur(s); 3583 translator_io_start(&s->base); 3584 gen_helper_rdtsc(tcg_env); 3585} 3586 3587static void gen_RDxxBASE(DisasContext *s, X86DecodedInsn *decode) 3588{ 3589 TCGv base = cpu_seg_base[s->modrm & 8 ? R_GS : R_FS]; 3590 3591 /* Preserve hflags bits by testing CR4 at runtime. */ 3592 gen_helper_cr4_testbit(tcg_env, tcg_constant_i32(CR4_FSGSBASE_MASK)); 3593 tcg_gen_mov_tl(s->T0, base); 3594} 3595 3596static void gen_RET(DisasContext *s, X86DecodedInsn *decode) 3597{ 3598 int16_t adjust = decode->e.op1 == X86_TYPE_I ? decode->immediate : 0; 3599 3600 MemOp ot = gen_pop_T0(s); 3601 gen_stack_update(s, adjust + (1 << ot)); 3602 gen_op_jmp_v(s, s->T0); 3603 gen_bnd_jmp(s); 3604 s->base.is_jmp = DISAS_JUMP; 3605} 3606 3607static void gen_RETF(DisasContext *s, X86DecodedInsn *decode) 3608{ 3609 int16_t adjust = decode->e.op1 == X86_TYPE_I ? decode->immediate : 0; 3610 3611 if (!PE(s) || VM86(s)) { 3612 gen_lea_ss_ofs(s, s->A0, cpu_regs[R_ESP], 0); 3613 /* pop offset */ 3614 gen_op_ld_v(s, s->dflag, s->T0, s->A0); 3615 /* NOTE: keeping EIP updated is not a problem in case of 3616 exception */ 3617 gen_op_jmp_v(s, s->T0); 3618 /* pop selector */ 3619 gen_add_A0_im(s, 1 << s->dflag); 3620 gen_op_ld_v(s, s->dflag, s->T0, s->A0); 3621 gen_op_movl_seg_real(s, R_CS, s->T0); 3622 /* add stack offset */ 3623 gen_stack_update(s, adjust + (2 << s->dflag)); 3624 } else { 3625 gen_update_cc_op(s); 3626 gen_update_eip_cur(s); 3627 gen_helper_lret_protected(tcg_env, tcg_constant_i32(s->dflag - 1), 3628 tcg_constant_i32(adjust)); 3629 } 3630 s->base.is_jmp = DISAS_EOB_ONLY; 3631} 3632 3633/* 3634 * Return non-NULL if a 32-bit rotate works, after possibly replicating the input. 3635 * The input has already been zero-extended upon operand decode. 3636 */ 3637static TCGv_i32 gen_rot_replicate(MemOp ot, TCGv in) 3638{ 3639 TCGv_i32 temp; 3640 switch (ot) { 3641 case MO_8: 3642 temp = tcg_temp_new_i32(); 3643 tcg_gen_trunc_tl_i32(temp, in); 3644 tcg_gen_muli_i32(temp, temp, 0x01010101); 3645 return temp; 3646 3647 case MO_16: 3648 temp = tcg_temp_new_i32(); 3649 tcg_gen_trunc_tl_i32(temp, in); 3650 tcg_gen_deposit_i32(temp, temp, temp, 16, 16); 3651 return temp; 3652 3653#ifdef TARGET_X86_64 3654 case MO_32: 3655 temp = tcg_temp_new_i32(); 3656 tcg_gen_trunc_tl_i32(temp, in); 3657 return temp; 3658#endif 3659 3660 default: 3661 return NULL; 3662 } 3663} 3664 3665static void gen_rot_carry(X86DecodedInsn *decode, TCGv result, 3666 bool can_be_zero, TCGv count, int bit) 3667{ 3668 if (!can_be_zero) { 3669 tcg_gen_extract_tl(decode->cc_dst, result, bit, 1); 3670 } else { 3671 TCGv temp = tcg_temp_new(); 3672 tcg_gen_extract_tl(temp, result, bit, 1); 3673 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_dst, count, tcg_constant_tl(0), 3674 decode->cc_dst, temp); 3675 } 3676} 3677 3678static void gen_ROL(DisasContext *s, X86DecodedInsn *decode) 3679{ 3680 bool can_be_zero; 3681 TCGv count; 3682 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3683 TCGv_i32 temp32, count32; 3684 TCGv old = tcg_temp_new(); 3685 3686 if (!count) { 3687 return; 3688 } 3689 3690 gen_eflags_adcox(s, decode, false, can_be_zero); 3691 tcg_gen_mov_tl(old, s->T0); 3692 temp32 = gen_rot_replicate(ot, s->T0); 3693 if (temp32) { 3694 count32 = tcg_temp_new_i32(); 3695 tcg_gen_trunc_tl_i32(count32, count); 3696 tcg_gen_rotl_i32(temp32, temp32, count32); 3697 /* Zero extend to facilitate later optimization. */ 3698 tcg_gen_extu_i32_tl(s->T0, temp32); 3699 } else { 3700 tcg_gen_rotl_tl(s->T0, s->T0, count); 3701 } 3702 gen_rot_carry(decode, s->T0, can_be_zero, count, 0); 3703 gen_rot_overflow(decode, s->T0, old, can_be_zero, count); 3704} 3705 3706static void gen_ROR(DisasContext *s, X86DecodedInsn *decode) 3707{ 3708 bool can_be_zero; 3709 TCGv count; 3710 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3711 TCGv_i32 temp32, count32; 3712 TCGv old = tcg_temp_new(); 3713 3714 if (!count) { 3715 return; 3716 } 3717 3718 gen_eflags_adcox(s, decode, false, can_be_zero); 3719 tcg_gen_mov_tl(old, s->T0); 3720 temp32 = gen_rot_replicate(ot, s->T0); 3721 if (temp32) { 3722 count32 = tcg_temp_new_i32(); 3723 tcg_gen_trunc_tl_i32(count32, count); 3724 tcg_gen_rotr_i32(temp32, temp32, count32); 3725 /* Zero extend to facilitate later optimization. */ 3726 tcg_gen_extu_i32_tl(s->T0, temp32); 3727 gen_rot_carry(decode, s->T0, can_be_zero, count, 31); 3728 } else { 3729 tcg_gen_rotr_tl(s->T0, s->T0, count); 3730 gen_rot_carry(decode, s->T0, can_be_zero, count, TARGET_LONG_BITS - 1); 3731 } 3732 gen_rot_overflow(decode, s->T0, old, can_be_zero, count); 3733} 3734 3735static void gen_RORX(DisasContext *s, X86DecodedInsn *decode) 3736{ 3737 MemOp ot = decode->op[0].ot; 3738 int mask = ot == MO_64 ? 63 : 31; 3739 int b = decode->immediate & mask; 3740 3741 switch (ot) { 3742 case MO_32: 3743#ifdef TARGET_X86_64 3744 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 3745 tcg_gen_rotri_i32(s->tmp2_i32, s->tmp2_i32, b); 3746 tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); 3747 break; 3748 3749 case MO_64: 3750#endif 3751 tcg_gen_rotri_tl(s->T0, s->T0, b); 3752 break; 3753 3754 default: 3755 g_assert_not_reached(); 3756 } 3757} 3758 3759#ifndef CONFIG_USER_ONLY 3760static void gen_RSM(DisasContext *s, X86DecodedInsn *decode) 3761{ 3762 gen_helper_rsm(tcg_env); 3763 assume_cc_op(s, CC_OP_EFLAGS); 3764 s->base.is_jmp = DISAS_EOB_ONLY; 3765} 3766#else 3767#define gen_RSM gen_UD 3768#endif 3769 3770static void gen_SAHF(DisasContext *s, X86DecodedInsn *decode) 3771{ 3772 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) { 3773 return gen_illegal_opcode(s); 3774 } 3775 tcg_gen_shri_tl(s->T0, cpu_regs[R_EAX], 8); 3776 gen_compute_eflags(s); 3777 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); 3778 tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C); 3779 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, s->T0); 3780} 3781 3782static void gen_SALC(DisasContext *s, X86DecodedInsn *decode) 3783{ 3784 gen_compute_eflags_c(s, s->T0); 3785 tcg_gen_neg_tl(s->T0, s->T0); 3786} 3787 3788static void gen_shift_dynamic_flags(DisasContext *s, X86DecodedInsn *decode, TCGv count, CCOp cc_op) 3789{ 3790 TCGv_i32 count32 = tcg_temp_new_i32(); 3791 TCGv_i32 old_cc_op; 3792 3793 decode->cc_op = CC_OP_DYNAMIC; 3794 decode->cc_op_dynamic = tcg_temp_new_i32(); 3795 3796 assert(decode->cc_dst == s->T0); 3797 if (cc_op_live(s->cc_op) & USES_CC_DST) { 3798 decode->cc_dst = tcg_temp_new(); 3799 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_dst, count, tcg_constant_tl(0), 3800 cpu_cc_dst, s->T0); 3801 } 3802 3803 if (cc_op_live(s->cc_op) & USES_CC_SRC) { 3804 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src, count, tcg_constant_tl(0), 3805 cpu_cc_src, decode->cc_src); 3806 } 3807 3808 tcg_gen_trunc_tl_i32(count32, count); 3809 if (s->cc_op == CC_OP_DYNAMIC) { 3810 old_cc_op = cpu_cc_op; 3811 } else { 3812 old_cc_op = tcg_constant_i32(s->cc_op); 3813 } 3814 tcg_gen_movcond_i32(TCG_COND_EQ, decode->cc_op_dynamic, count32, tcg_constant_i32(0), 3815 old_cc_op, tcg_constant_i32(cc_op)); 3816} 3817 3818static void gen_SAR(DisasContext *s, X86DecodedInsn *decode) 3819{ 3820 bool can_be_zero; 3821 TCGv count; 3822 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3823 3824 if (!count) { 3825 return; 3826 } 3827 3828 decode->cc_dst = s->T0; 3829 decode->cc_src = tcg_temp_new(); 3830 tcg_gen_subi_tl(decode->cc_src, count, 1); 3831 tcg_gen_sar_tl(decode->cc_src, s->T0, decode->cc_src); 3832 tcg_gen_sar_tl(s->T0, s->T0, count); 3833 if (can_be_zero) { 3834 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 3835 } else { 3836 decode->cc_op = CC_OP_SARB + ot; 3837 } 3838} 3839 3840static void gen_SARX(DisasContext *s, X86DecodedInsn *decode) 3841{ 3842 MemOp ot = decode->op[0].ot; 3843 int mask; 3844 3845 mask = ot == MO_64 ? 63 : 31; 3846 tcg_gen_andi_tl(s->T1, s->T1, mask); 3847 tcg_gen_sar_tl(s->T0, s->T0, s->T1); 3848} 3849 3850static void gen_SBB(DisasContext *s, X86DecodedInsn *decode) 3851{ 3852 MemOp ot = decode->op[0].ot; 3853 TCGv c_in = tcg_temp_new(); 3854 3855 gen_compute_eflags_c(s, c_in); 3856 if (s->prefix & PREFIX_LOCK) { 3857 tcg_gen_add_tl(s->T0, s->T1, c_in); 3858 tcg_gen_neg_tl(s->T0, s->T0); 3859 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T0, 3860 s->mem_index, ot | MO_LE); 3861 } else { 3862 /* 3863 * TODO: SBB reg, reg could use gen_prepare_eflags_c followed by 3864 * negsetcond, and CC_OP_SUBB as the cc_op. 3865 */ 3866 tcg_gen_sub_tl(s->T0, s->T0, s->T1); 3867 tcg_gen_sub_tl(s->T0, s->T0, c_in); 3868 } 3869 prepare_update3_cc(decode, s, CC_OP_SBBB + ot, c_in); 3870} 3871 3872static void gen_SCAS(DisasContext *s, X86DecodedInsn *decode) 3873{ 3874 MemOp ot = decode->op[2].ot; 3875 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 3876 gen_repz_nz(s, ot, gen_scas); 3877 } else { 3878 gen_scas(s, ot); 3879 } 3880} 3881 3882static void gen_SETcc(DisasContext *s, X86DecodedInsn *decode) 3883{ 3884 gen_setcc1(s, decode->b & 0xf, s->T0); 3885} 3886 3887static void gen_SFENCE(DisasContext *s, X86DecodedInsn *decode) 3888{ 3889 tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC); 3890} 3891 3892static void gen_SHA1NEXTE(DisasContext *s, X86DecodedInsn *decode) 3893{ 3894 gen_helper_sha1nexte(OP_PTR0, OP_PTR1, OP_PTR2); 3895} 3896 3897static void gen_SHA1MSG1(DisasContext *s, X86DecodedInsn *decode) 3898{ 3899 gen_helper_sha1msg1(OP_PTR0, OP_PTR1, OP_PTR2); 3900} 3901 3902static void gen_SHA1MSG2(DisasContext *s, X86DecodedInsn *decode) 3903{ 3904 gen_helper_sha1msg2(OP_PTR0, OP_PTR1, OP_PTR2); 3905} 3906 3907static void gen_SHA1RNDS4(DisasContext *s, X86DecodedInsn *decode) 3908{ 3909 switch(decode->immediate & 3) { 3910 case 0: 3911 gen_helper_sha1rnds4_f0(OP_PTR0, OP_PTR0, OP_PTR1); 3912 break; 3913 case 1: 3914 gen_helper_sha1rnds4_f1(OP_PTR0, OP_PTR0, OP_PTR1); 3915 break; 3916 case 2: 3917 gen_helper_sha1rnds4_f2(OP_PTR0, OP_PTR0, OP_PTR1); 3918 break; 3919 case 3: 3920 gen_helper_sha1rnds4_f3(OP_PTR0, OP_PTR0, OP_PTR1); 3921 break; 3922 } 3923} 3924 3925static void gen_SHA256MSG1(DisasContext *s, X86DecodedInsn *decode) 3926{ 3927 gen_helper_sha256msg1(OP_PTR0, OP_PTR1, OP_PTR2); 3928} 3929 3930static void gen_SHA256MSG2(DisasContext *s, X86DecodedInsn *decode) 3931{ 3932 gen_helper_sha256msg2(OP_PTR0, OP_PTR1, OP_PTR2); 3933} 3934 3935static void gen_SHA256RNDS2(DisasContext *s, X86DecodedInsn *decode) 3936{ 3937 TCGv_i32 wk0 = tcg_temp_new_i32(); 3938 TCGv_i32 wk1 = tcg_temp_new_i32(); 3939 3940 tcg_gen_ld_i32(wk0, tcg_env, ZMM_OFFSET(0) + offsetof(ZMMReg, ZMM_L(0))); 3941 tcg_gen_ld_i32(wk1, tcg_env, ZMM_OFFSET(0) + offsetof(ZMMReg, ZMM_L(1))); 3942 3943 gen_helper_sha256rnds2(OP_PTR0, OP_PTR1, OP_PTR2, wk0, wk1); 3944} 3945 3946static void gen_SHL(DisasContext *s, X86DecodedInsn *decode) 3947{ 3948 bool can_be_zero; 3949 TCGv count; 3950 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3951 3952 if (!count) { 3953 return; 3954 } 3955 3956 decode->cc_dst = s->T0; 3957 decode->cc_src = tcg_temp_new(); 3958 tcg_gen_subi_tl(decode->cc_src, count, 1); 3959 tcg_gen_shl_tl(decode->cc_src, s->T0, decode->cc_src); 3960 tcg_gen_shl_tl(s->T0, s->T0, count); 3961 if (can_be_zero) { 3962 gen_shift_dynamic_flags(s, decode, count, CC_OP_SHLB + ot); 3963 } else { 3964 decode->cc_op = CC_OP_SHLB + ot; 3965 } 3966} 3967 3968static void gen_SHLD(DisasContext *s, X86DecodedInsn *decode) 3969{ 3970 bool can_be_zero; 3971 TCGv count; 3972 int unit = decode->e.op3 == X86_TYPE_I ? X86_OP_IMM : X86_OP_INT; 3973 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, unit); 3974 3975 if (!count) { 3976 return; 3977 } 3978 3979 decode->cc_dst = s->T0; 3980 decode->cc_src = s->tmp0; 3981 gen_shiftd_rm_T1(s, ot, false, count); 3982 if (can_be_zero) { 3983 gen_shift_dynamic_flags(s, decode, count, CC_OP_SHLB + ot); 3984 } else { 3985 decode->cc_op = CC_OP_SHLB + ot; 3986 } 3987} 3988 3989static void gen_SHLX(DisasContext *s, X86DecodedInsn *decode) 3990{ 3991 MemOp ot = decode->op[0].ot; 3992 int mask; 3993 3994 mask = ot == MO_64 ? 63 : 31; 3995 tcg_gen_andi_tl(s->T1, s->T1, mask); 3996 tcg_gen_shl_tl(s->T0, s->T0, s->T1); 3997} 3998 3999static void gen_SHR(DisasContext *s, X86DecodedInsn *decode) 4000{ 4001 bool can_be_zero; 4002 TCGv count; 4003 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 4004 4005 if (!count) { 4006 return; 4007 } 4008 4009 decode->cc_dst = s->T0; 4010 decode->cc_src = tcg_temp_new(); 4011 tcg_gen_subi_tl(decode->cc_src, count, 1); 4012 tcg_gen_shr_tl(decode->cc_src, s->T0, decode->cc_src); 4013 tcg_gen_shr_tl(s->T0, s->T0, count); 4014 if (can_be_zero) { 4015 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 4016 } else { 4017 decode->cc_op = CC_OP_SARB + ot; 4018 } 4019} 4020 4021static void gen_SHRD(DisasContext *s, X86DecodedInsn *decode) 4022{ 4023 bool can_be_zero; 4024 TCGv count; 4025 int unit = decode->e.op3 == X86_TYPE_I ? X86_OP_IMM : X86_OP_INT; 4026 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, unit); 4027 4028 if (!count) { 4029 return; 4030 } 4031 4032 decode->cc_dst = s->T0; 4033 decode->cc_src = s->tmp0; 4034 gen_shiftd_rm_T1(s, ot, true, count); 4035 if (can_be_zero) { 4036 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 4037 } else { 4038 decode->cc_op = CC_OP_SARB + ot; 4039 } 4040} 4041 4042static void gen_SHRX(DisasContext *s, X86DecodedInsn *decode) 4043{ 4044 MemOp ot = decode->op[0].ot; 4045 int mask; 4046 4047 mask = ot == MO_64 ? 63 : 31; 4048 tcg_gen_andi_tl(s->T1, s->T1, mask); 4049 tcg_gen_shr_tl(s->T0, s->T0, s->T1); 4050} 4051 4052static void gen_STC(DisasContext *s, X86DecodedInsn *decode) 4053{ 4054 gen_compute_eflags(s); 4055 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); 4056} 4057 4058static void gen_STD(DisasContext *s, X86DecodedInsn *decode) 4059{ 4060 tcg_gen_st_i32(tcg_constant_i32(-1), tcg_env, offsetof(CPUX86State, df)); 4061} 4062 4063static void gen_STI(DisasContext *s, X86DecodedInsn *decode) 4064{ 4065 gen_set_eflags(s, IF_MASK); 4066 s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ; 4067} 4068 4069static void gen_VAESKEYGEN(DisasContext *s, X86DecodedInsn *decode) 4070{ 4071 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4072 assert(!s->vex_l); 4073 gen_helper_aeskeygenassist_xmm(tcg_env, OP_PTR0, OP_PTR1, imm); 4074} 4075 4076static void gen_STMXCSR(DisasContext *s, X86DecodedInsn *decode) 4077{ 4078 gen_helper_update_mxcsr(tcg_env); 4079 tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr)); 4080} 4081 4082static void gen_STOS(DisasContext *s, X86DecodedInsn *decode) 4083{ 4084 MemOp ot = decode->op[1].ot; 4085 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 4086 gen_repz(s, ot, gen_stos); 4087 } else { 4088 gen_stos(s, ot); 4089 } 4090} 4091 4092static void gen_SUB(DisasContext *s, X86DecodedInsn *decode) 4093{ 4094 MemOp ot = decode->op[1].ot; 4095 4096 if (s->prefix & PREFIX_LOCK) { 4097 tcg_gen_neg_tl(s->T0, s->T1); 4098 tcg_gen_atomic_fetch_add_tl(s->cc_srcT, s->A0, s->T0, 4099 s->mem_index, ot | MO_LE); 4100 tcg_gen_sub_tl(s->T0, s->cc_srcT, s->T1); 4101 } else { 4102 tcg_gen_mov_tl(s->cc_srcT, s->T0); 4103 tcg_gen_sub_tl(s->T0, s->T0, s->T1); 4104 } 4105 prepare_update2_cc(decode, s, CC_OP_SUBB + ot); 4106} 4107 4108static void gen_SYSCALL(DisasContext *s, X86DecodedInsn *decode) 4109{ 4110 gen_update_cc_op(s); 4111 gen_update_eip_cur(s); 4112 gen_helper_syscall(tcg_env, cur_insn_len_i32(s)); 4113 if (LMA(s)) { 4114 assume_cc_op(s, CC_OP_EFLAGS); 4115 } 4116 4117 /* 4118 * TF handling for the syscall insn is different. The TF bit is checked 4119 * after the syscall insn completes. This allows #DB to not be 4120 * generated after one has entered CPL0 if TF is set in FMASK. 4121 */ 4122 s->base.is_jmp = DISAS_EOB_RECHECK_TF; 4123} 4124 4125static void gen_SYSENTER(DisasContext *s, X86DecodedInsn *decode) 4126{ 4127 gen_helper_sysenter(tcg_env); 4128 s->base.is_jmp = DISAS_EOB_ONLY; 4129} 4130 4131static void gen_SYSEXIT(DisasContext *s, X86DecodedInsn *decode) 4132{ 4133 gen_helper_sysexit(tcg_env, tcg_constant_i32(s->dflag - 1)); 4134 s->base.is_jmp = DISAS_EOB_ONLY; 4135} 4136 4137static void gen_SYSRET(DisasContext *s, X86DecodedInsn *decode) 4138{ 4139 gen_helper_sysret(tcg_env, tcg_constant_i32(s->dflag - 1)); 4140 if (LMA(s)) { 4141 assume_cc_op(s, CC_OP_EFLAGS); 4142 } 4143 4144 /* 4145 * TF handling for the sysret insn is different. The TF bit is checked 4146 * after the sysret insn completes. This allows #DB to be 4147 * generated "as if" the syscall insn in userspace has just 4148 * completed. 4149 */ 4150 s->base.is_jmp = DISAS_EOB_RECHECK_TF; 4151} 4152 4153static void gen_TZCNT(DisasContext *s, X86DecodedInsn *decode) 4154{ 4155 MemOp ot = decode->op[0].ot; 4156 4157 /* C bit (cc_src) is defined related to the input. */ 4158 decode->cc_src = tcg_temp_new(); 4159 decode->cc_dst = s->T0; 4160 decode->cc_op = CC_OP_BMILGB + ot; 4161 tcg_gen_mov_tl(decode->cc_src, s->T0); 4162 4163 /* A zero input returns the operand size. */ 4164 tcg_gen_ctzi_tl(s->T0, s->T0, 8 << ot); 4165} 4166 4167static void gen_UD(DisasContext *s, X86DecodedInsn *decode) 4168{ 4169 gen_illegal_opcode(s); 4170} 4171 4172static void gen_VAESIMC(DisasContext *s, X86DecodedInsn *decode) 4173{ 4174 assert(!s->vex_l); 4175 gen_helper_aesimc_xmm(tcg_env, OP_PTR0, OP_PTR2); 4176} 4177 4178/* 4179 * 00 = v*ps Vps, Hps, Wpd 4180 * 66 = v*pd Vpd, Hpd, Wps 4181 * f3 = v*ss Vss, Hss, Wps 4182 * f2 = v*sd Vsd, Hsd, Wps 4183 */ 4184#define SSE_CMP(x) { \ 4185 gen_helper_ ## x ## ps ## _xmm, gen_helper_ ## x ## pd ## _xmm, \ 4186 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, \ 4187 gen_helper_ ## x ## ps ## _ymm, gen_helper_ ## x ## pd ## _ymm} 4188static const SSEFunc_0_eppp gen_helper_cmp_funcs[32][6] = { 4189 SSE_CMP(cmpeq), 4190 SSE_CMP(cmplt), 4191 SSE_CMP(cmple), 4192 SSE_CMP(cmpunord), 4193 SSE_CMP(cmpneq), 4194 SSE_CMP(cmpnlt), 4195 SSE_CMP(cmpnle), 4196 SSE_CMP(cmpord), 4197 4198 SSE_CMP(cmpequ), 4199 SSE_CMP(cmpnge), 4200 SSE_CMP(cmpngt), 4201 SSE_CMP(cmpfalse), 4202 SSE_CMP(cmpnequ), 4203 SSE_CMP(cmpge), 4204 SSE_CMP(cmpgt), 4205 SSE_CMP(cmptrue), 4206 4207 SSE_CMP(cmpeqs), 4208 SSE_CMP(cmpltq), 4209 SSE_CMP(cmpleq), 4210 SSE_CMP(cmpunords), 4211 SSE_CMP(cmpneqq), 4212 SSE_CMP(cmpnltq), 4213 SSE_CMP(cmpnleq), 4214 SSE_CMP(cmpords), 4215 4216 SSE_CMP(cmpequs), 4217 SSE_CMP(cmpngeq), 4218 SSE_CMP(cmpngtq), 4219 SSE_CMP(cmpfalses), 4220 SSE_CMP(cmpnequs), 4221 SSE_CMP(cmpgeq), 4222 SSE_CMP(cmpgtq), 4223 SSE_CMP(cmptrues), 4224}; 4225#undef SSE_CMP 4226 4227static void gen_VCMP(DisasContext *s, X86DecodedInsn *decode) 4228{ 4229 int index = decode->immediate & (s->prefix & PREFIX_VEX ? 31 : 7); 4230 int b = 4231 s->prefix & PREFIX_REPZ ? 2 /* ss */ : 4232 s->prefix & PREFIX_REPNZ ? 3 /* sd */ : 4233 !!(s->prefix & PREFIX_DATA) /* pd */ + (s->vex_l << 2); 4234 4235 gen_helper_cmp_funcs[index][b](tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 4236} 4237 4238static void gen_VCOMI(DisasContext *s, X86DecodedInsn *decode) 4239{ 4240 SSEFunc_0_epp fn; 4241 fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss; 4242 fn(tcg_env, OP_PTR1, OP_PTR2); 4243 assume_cc_op(s, CC_OP_EFLAGS); 4244} 4245 4246static void gen_VCVTPD2PS(DisasContext *s, X86DecodedInsn *decode) 4247{ 4248 if (s->vex_l) { 4249 gen_helper_cvtpd2ps_ymm(tcg_env, OP_PTR0, OP_PTR2); 4250 } else { 4251 gen_helper_cvtpd2ps_xmm(tcg_env, OP_PTR0, OP_PTR2); 4252 } 4253} 4254 4255static void gen_VCVTPS2PD(DisasContext *s, X86DecodedInsn *decode) 4256{ 4257 if (s->vex_l) { 4258 gen_helper_cvtps2pd_ymm(tcg_env, OP_PTR0, OP_PTR2); 4259 } else { 4260 gen_helper_cvtps2pd_xmm(tcg_env, OP_PTR0, OP_PTR2); 4261 } 4262} 4263 4264static void gen_VCVTPS2PH(DisasContext *s, X86DecodedInsn *decode) 4265{ 4266 gen_unary_imm_fp_sse(s, decode, 4267 gen_helper_cvtps2ph_xmm, 4268 gen_helper_cvtps2ph_ymm); 4269 /* 4270 * VCVTPS2PH is the only instruction that performs an operation on a 4271 * register source and then *stores* into memory. 4272 */ 4273 if (decode->op[0].has_ea) { 4274 gen_store_sse(s, decode, decode->op[0].offset); 4275 } 4276} 4277 4278static void gen_VCVTSD2SS(DisasContext *s, X86DecodedInsn *decode) 4279{ 4280 gen_helper_cvtsd2ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 4281} 4282 4283static void gen_VCVTSS2SD(DisasContext *s, X86DecodedInsn *decode) 4284{ 4285 gen_helper_cvtss2sd(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 4286} 4287 4288static void gen_VCVTSI2Sx(DisasContext *s, X86DecodedInsn *decode) 4289{ 4290 int vec_len = vector_len(s, decode); 4291 TCGv_i32 in; 4292 4293 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4294 4295#ifdef TARGET_X86_64 4296 MemOp ot = decode->op[2].ot; 4297 if (ot == MO_64) { 4298 if (s->prefix & PREFIX_REPNZ) { 4299 gen_helper_cvtsq2sd(tcg_env, OP_PTR0, s->T1); 4300 } else { 4301 gen_helper_cvtsq2ss(tcg_env, OP_PTR0, s->T1); 4302 } 4303 return; 4304 } 4305 in = s->tmp2_i32; 4306 tcg_gen_trunc_tl_i32(in, s->T1); 4307#else 4308 in = s->T1; 4309#endif 4310 4311 if (s->prefix & PREFIX_REPNZ) { 4312 gen_helper_cvtsi2sd(tcg_env, OP_PTR0, in); 4313 } else { 4314 gen_helper_cvtsi2ss(tcg_env, OP_PTR0, in); 4315 } 4316} 4317 4318static inline void gen_VCVTtSx2SI(DisasContext *s, X86DecodedInsn *decode, 4319 SSEFunc_i_ep ss2si, SSEFunc_l_ep ss2sq, 4320 SSEFunc_i_ep sd2si, SSEFunc_l_ep sd2sq) 4321{ 4322 TCGv_i32 out; 4323 4324#ifdef TARGET_X86_64 4325 MemOp ot = decode->op[0].ot; 4326 if (ot == MO_64) { 4327 if (s->prefix & PREFIX_REPNZ) { 4328 sd2sq(s->T0, tcg_env, OP_PTR2); 4329 } else { 4330 ss2sq(s->T0, tcg_env, OP_PTR2); 4331 } 4332 return; 4333 } 4334 4335 out = s->tmp2_i32; 4336#else 4337 out = s->T0; 4338#endif 4339 if (s->prefix & PREFIX_REPNZ) { 4340 sd2si(out, tcg_env, OP_PTR2); 4341 } else { 4342 ss2si(out, tcg_env, OP_PTR2); 4343 } 4344#ifdef TARGET_X86_64 4345 tcg_gen_extu_i32_tl(s->T0, out); 4346#endif 4347} 4348 4349#ifndef TARGET_X86_64 4350#define gen_helper_cvtss2sq NULL 4351#define gen_helper_cvtsd2sq NULL 4352#define gen_helper_cvttss2sq NULL 4353#define gen_helper_cvttsd2sq NULL 4354#endif 4355 4356static void gen_VCVTSx2SI(DisasContext *s, X86DecodedInsn *decode) 4357{ 4358 gen_VCVTtSx2SI(s, decode, 4359 gen_helper_cvtss2si, gen_helper_cvtss2sq, 4360 gen_helper_cvtsd2si, gen_helper_cvtsd2sq); 4361} 4362 4363static void gen_VCVTTSx2SI(DisasContext *s, X86DecodedInsn *decode) 4364{ 4365 gen_VCVTtSx2SI(s, decode, 4366 gen_helper_cvttss2si, gen_helper_cvttss2sq, 4367 gen_helper_cvttsd2si, gen_helper_cvttsd2sq); 4368} 4369 4370static void gen_VEXTRACTx128(DisasContext *s, X86DecodedInsn *decode) 4371{ 4372 int mask = decode->immediate & 1; 4373 int src_ofs = vector_elem_offset(&decode->op[1], MO_128, mask); 4374 if (decode->op[0].has_ea) { 4375 /* VEX-only instruction, no alignment requirements. */ 4376 gen_sto_env_A0(s, src_ofs, false); 4377 } else { 4378 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, 16, 16); 4379 } 4380} 4381 4382static void gen_VEXTRACTPS(DisasContext *s, X86DecodedInsn *decode) 4383{ 4384 gen_pextr(s, decode, MO_32); 4385} 4386 4387static void gen_vinsertps(DisasContext *s, X86DecodedInsn *decode) 4388{ 4389 int val = decode->immediate; 4390 int dest_word = (val >> 4) & 3; 4391 int new_mask = (val & 15) | (1 << dest_word); 4392 int vec_len = 16; 4393 4394 assert(!s->vex_l); 4395 4396 if (new_mask == 15) { 4397 /* All zeroes except possibly for the inserted element */ 4398 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 4399 } else if (decode->op[1].offset != decode->op[0].offset) { 4400 gen_store_sse(s, decode, decode->op[1].offset); 4401 } 4402 4403 if (new_mask != (val & 15)) { 4404 tcg_gen_st_i32(s->tmp2_i32, tcg_env, 4405 vector_elem_offset(&decode->op[0], MO_32, dest_word)); 4406 } 4407 4408 if (new_mask != 15) { 4409 TCGv_i32 zero = tcg_constant_i32(0); /* float32_zero */ 4410 int i; 4411 for (i = 0; i < 4; i++) { 4412 if ((val >> i) & 1) { 4413 tcg_gen_st_i32(zero, tcg_env, 4414 vector_elem_offset(&decode->op[0], MO_32, i)); 4415 } 4416 } 4417 } 4418} 4419 4420static void gen_VINSERTPS_r(DisasContext *s, X86DecodedInsn *decode) 4421{ 4422 int val = decode->immediate; 4423 tcg_gen_ld_i32(s->tmp2_i32, tcg_env, 4424 vector_elem_offset(&decode->op[2], MO_32, (val >> 6) & 3)); 4425 gen_vinsertps(s, decode); 4426} 4427 4428static void gen_VINSERTPS_m(DisasContext *s, X86DecodedInsn *decode) 4429{ 4430 tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4431 gen_vinsertps(s, decode); 4432} 4433 4434static void gen_VINSERTx128(DisasContext *s, X86DecodedInsn *decode) 4435{ 4436 int mask = decode->immediate & 1; 4437 tcg_gen_gvec_mov(MO_64, 4438 decode->op[0].offset + offsetof(YMMReg, YMM_X(mask)), 4439 decode->op[2].offset + offsetof(YMMReg, YMM_X(0)), 16, 16); 4440 tcg_gen_gvec_mov(MO_64, 4441 decode->op[0].offset + offsetof(YMMReg, YMM_X(!mask)), 4442 decode->op[1].offset + offsetof(YMMReg, YMM_X(!mask)), 16, 16); 4443} 4444 4445static inline void gen_maskmov(DisasContext *s, X86DecodedInsn *decode, 4446 SSEFunc_0_eppt xmm, SSEFunc_0_eppt ymm) 4447{ 4448 if (!s->vex_l) { 4449 xmm(tcg_env, OP_PTR2, OP_PTR1, s->A0); 4450 } else { 4451 ymm(tcg_env, OP_PTR2, OP_PTR1, s->A0); 4452 } 4453} 4454 4455static void gen_VMASKMOVPD_st(DisasContext *s, X86DecodedInsn *decode) 4456{ 4457 gen_maskmov(s, decode, gen_helper_vpmaskmovq_st_xmm, gen_helper_vpmaskmovq_st_ymm); 4458} 4459 4460static void gen_VMASKMOVPS_st(DisasContext *s, X86DecodedInsn *decode) 4461{ 4462 gen_maskmov(s, decode, gen_helper_vpmaskmovd_st_xmm, gen_helper_vpmaskmovd_st_ymm); 4463} 4464 4465static void gen_VMOVHPx_ld(DisasContext *s, X86DecodedInsn *decode) 4466{ 4467 gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4468 if (decode->op[0].offset != decode->op[1].offset) { 4469 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4470 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4471 } 4472} 4473 4474static void gen_VMOVHPx_st(DisasContext *s, X86DecodedInsn *decode) 4475{ 4476 gen_stq_env_A0(s, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4477} 4478 4479static void gen_VMOVHPx(DisasContext *s, X86DecodedInsn *decode) 4480{ 4481 if (decode->op[0].offset != decode->op[2].offset) { 4482 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4483 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4484 } 4485 if (decode->op[0].offset != decode->op[1].offset) { 4486 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4487 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4488 } 4489} 4490 4491static void gen_VMOVHLPS(DisasContext *s, X86DecodedInsn *decode) 4492{ 4493 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4494 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4495 if (decode->op[0].offset != decode->op[1].offset) { 4496 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1))); 4497 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4498 } 4499} 4500 4501static void gen_VMOVLHPS(DisasContext *s, X86DecodedInsn *decode) 4502{ 4503 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset); 4504 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4505 if (decode->op[0].offset != decode->op[1].offset) { 4506 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4507 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4508 } 4509} 4510 4511/* 4512 * Note that MOVLPx supports 256-bit operation unlike MOVHLPx, MOVLHPx, MOXHPx. 4513 * Use a gvec move to move everything above the bottom 64 bits. 4514 */ 4515 4516static void gen_VMOVLPx(DisasContext *s, X86DecodedInsn *decode) 4517{ 4518 int vec_len = vector_len(s, decode); 4519 4520 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0))); 4521 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4522 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4523} 4524 4525static void gen_VMOVLPx_ld(DisasContext *s, X86DecodedInsn *decode) 4526{ 4527 int vec_len = vector_len(s, decode); 4528 4529 tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4530 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4531 tcg_gen_st_i64(s->tmp1_i64, OP_PTR0, offsetof(ZMMReg, ZMM_Q(0))); 4532} 4533 4534static void gen_VMOVLPx_st(DisasContext *s, X86DecodedInsn *decode) 4535{ 4536 tcg_gen_ld_i64(s->tmp1_i64, OP_PTR2, offsetof(ZMMReg, ZMM_Q(0))); 4537 tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4538} 4539 4540static void gen_VMOVSD_ld(DisasContext *s, X86DecodedInsn *decode) 4541{ 4542 TCGv_i64 zero = tcg_constant_i64(0); 4543 4544 tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4545 tcg_gen_st_i64(zero, OP_PTR0, offsetof(ZMMReg, ZMM_Q(1))); 4546 tcg_gen_st_i64(s->tmp1_i64, OP_PTR0, offsetof(ZMMReg, ZMM_Q(0))); 4547} 4548 4549static void gen_VMOVSS(DisasContext *s, X86DecodedInsn *decode) 4550{ 4551 int vec_len = vector_len(s, decode); 4552 4553 tcg_gen_ld_i32(s->tmp2_i32, OP_PTR2, offsetof(ZMMReg, ZMM_L(0))); 4554 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4555 tcg_gen_st_i32(s->tmp2_i32, OP_PTR0, offsetof(ZMMReg, ZMM_L(0))); 4556} 4557 4558static void gen_VMOVSS_ld(DisasContext *s, X86DecodedInsn *decode) 4559{ 4560 int vec_len = vector_len(s, decode); 4561 4562 tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4563 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 4564 tcg_gen_st_i32(s->tmp2_i32, OP_PTR0, offsetof(ZMMReg, ZMM_L(0))); 4565} 4566 4567static void gen_VMOVSS_st(DisasContext *s, X86DecodedInsn *decode) 4568{ 4569 tcg_gen_ld_i32(s->tmp2_i32, OP_PTR2, offsetof(ZMMReg, ZMM_L(0))); 4570 tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4571} 4572 4573static void gen_VPMASKMOV_st(DisasContext *s, X86DecodedInsn *decode) 4574{ 4575 if (s->vex_w) { 4576 gen_VMASKMOVPD_st(s, decode); 4577 } else { 4578 gen_VMASKMOVPS_st(s, decode); 4579 } 4580} 4581 4582static void gen_VPERMD(DisasContext *s, X86DecodedInsn *decode) 4583{ 4584 assert(s->vex_l); 4585 gen_helper_vpermd_ymm(OP_PTR0, OP_PTR1, OP_PTR2); 4586} 4587 4588static void gen_VPERM2x128(DisasContext *s, X86DecodedInsn *decode) 4589{ 4590 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4591 assert(s->vex_l); 4592 gen_helper_vpermdq_ymm(OP_PTR0, OP_PTR1, OP_PTR2, imm); 4593} 4594 4595static void gen_VPHMINPOSUW(DisasContext *s, X86DecodedInsn *decode) 4596{ 4597 assert(!s->vex_l); 4598 gen_helper_phminposuw_xmm(tcg_env, OP_PTR0, OP_PTR2); 4599} 4600 4601static void gen_VROUNDSD(DisasContext *s, X86DecodedInsn *decode) 4602{ 4603 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4604 assert(!s->vex_l); 4605 gen_helper_roundsd_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 4606} 4607 4608static void gen_VROUNDSS(DisasContext *s, X86DecodedInsn *decode) 4609{ 4610 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4611 assert(!s->vex_l); 4612 gen_helper_roundss_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 4613} 4614 4615static void gen_VSHUF(DisasContext *s, X86DecodedInsn *decode) 4616{ 4617 TCGv_i32 imm = tcg_constant_i32(decode->immediate); 4618 SSEFunc_0_pppi ps, pd, fn; 4619 ps = s->vex_l ? gen_helper_shufps_ymm : gen_helper_shufps_xmm; 4620 pd = s->vex_l ? gen_helper_shufpd_ymm : gen_helper_shufpd_xmm; 4621 fn = s->prefix & PREFIX_DATA ? pd : ps; 4622 fn(OP_PTR0, OP_PTR1, OP_PTR2, imm); 4623} 4624 4625static void gen_VUCOMI(DisasContext *s, X86DecodedInsn *decode) 4626{ 4627 SSEFunc_0_epp fn; 4628 fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss; 4629 fn(tcg_env, OP_PTR1, OP_PTR2); 4630 assume_cc_op(s, CC_OP_EFLAGS); 4631} 4632 4633static void gen_VZEROALL(DisasContext *s, X86DecodedInsn *decode) 4634{ 4635 TCGv_ptr ptr = tcg_temp_new_ptr(); 4636 4637 tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_regs)); 4638 gen_helper_memset(ptr, ptr, tcg_constant_i32(0), 4639 tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg))); 4640} 4641 4642static void gen_VZEROUPPER(DisasContext *s, X86DecodedInsn *decode) 4643{ 4644 int i; 4645 4646 for (i = 0; i < CPU_NB_REGS; i++) { 4647 int offset = offsetof(CPUX86State, xmm_regs[i].ZMM_X(1)); 4648 tcg_gen_gvec_dup_imm(MO_64, offset, 16, 16, 0); 4649 } 4650} 4651 4652static void gen_WAIT(DisasContext *s, X86DecodedInsn *decode) 4653{ 4654 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == (HF_MP_MASK | HF_TS_MASK)) { 4655 gen_NM_exception(s); 4656 } else { 4657 /* needs to be treated as I/O because of ferr_irq */ 4658 translator_io_start(&s->base); 4659 gen_helper_fwait(tcg_env); 4660 } 4661} 4662 4663#ifndef CONFIG_USER_ONLY 4664static void gen_WRMSR(DisasContext *s, X86DecodedInsn *decode) 4665{ 4666 gen_update_cc_op(s); 4667 gen_update_eip_cur(s); 4668 gen_helper_wrmsr(tcg_env); 4669 s->base.is_jmp = DISAS_EOB_NEXT; 4670} 4671#else 4672#define gen_WRMSR gen_unreachable 4673#endif 4674 4675static void gen_WRxxBASE(DisasContext *s, X86DecodedInsn *decode) 4676{ 4677 TCGv base = cpu_seg_base[s->modrm & 8 ? R_GS : R_FS]; 4678 4679 /* Preserve hflags bits by testing CR4 at runtime. */ 4680 gen_helper_cr4_testbit(tcg_env, tcg_constant_i32(CR4_FSGSBASE_MASK)); 4681 tcg_gen_mov_tl(base, s->T0); 4682} 4683 4684static void gen_XADD(DisasContext *s, X86DecodedInsn *decode) 4685{ 4686 MemOp ot = decode->op[1].ot; 4687 4688 decode->cc_dst = tcg_temp_new(); 4689 decode->cc_src = s->T1; 4690 decode->cc_op = CC_OP_ADDB + ot; 4691 4692 if (s->prefix & PREFIX_LOCK) { 4693 tcg_gen_atomic_fetch_add_tl(s->T0, s->A0, s->T1, s->mem_index, ot | MO_LE); 4694 tcg_gen_add_tl(decode->cc_dst, s->T0, s->T1); 4695 } else { 4696 tcg_gen_add_tl(decode->cc_dst, s->T0, s->T1); 4697 /* 4698 * NOTE: writing memory first is important for MMU exceptions, 4699 * but "new result" wins for XADD AX, AX. 4700 */ 4701 gen_writeback(s, decode, 0, decode->cc_dst); 4702 } 4703 if (decode->op[0].has_ea || decode->op[2].n != decode->op[0].n) { 4704 gen_writeback(s, decode, 2, s->T0); 4705 } 4706} 4707 4708static void gen_XCHG(DisasContext *s, X86DecodedInsn *decode) 4709{ 4710 if (s->prefix & PREFIX_LOCK) { 4711 tcg_gen_atomic_xchg_tl(s->T0, s->A0, s->T1, 4712 s->mem_index, decode->op[0].ot | MO_LE); 4713 /* now store old value into register operand */ 4714 gen_op_mov_reg_v(s, decode->op[2].ot, decode->op[2].n, s->T0); 4715 } else { 4716 /* move destination value into source operand, source preserved in T1 */ 4717 gen_op_mov_reg_v(s, decode->op[2].ot, decode->op[2].n, s->T0); 4718 tcg_gen_mov_tl(s->T0, s->T1); 4719 } 4720} 4721 4722static void gen_XLAT(DisasContext *s, X86DecodedInsn *decode) 4723{ 4724 /* AL is already zero-extended into s->T0. */ 4725 tcg_gen_add_tl(s->A0, cpu_regs[R_EBX], s->T0); 4726 gen_lea_v_seg(s, s->A0, R_DS, s->override); 4727 gen_op_ld_v(s, MO_8, s->T0, s->A0); 4728} 4729 4730static void gen_XOR(DisasContext *s, X86DecodedInsn *decode) 4731{ 4732 /* special case XOR reg, reg */ 4733 if (decode->op[1].unit == X86_OP_INT && 4734 decode->op[2].unit == X86_OP_INT && 4735 decode->op[1].n == decode->op[2].n) { 4736 tcg_gen_movi_tl(s->T0, 0); 4737 decode->cc_op = CC_OP_EFLAGS; 4738 decode->cc_src = tcg_constant_tl(CC_Z | CC_P); 4739 } else { 4740 MemOp ot = decode->op[1].ot; 4741 4742 if (s->prefix & PREFIX_LOCK) { 4743 tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T1, 4744 s->mem_index, ot | MO_LE); 4745 } else { 4746 tcg_gen_xor_tl(s->T0, s->T0, s->T1); 4747 } 4748 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 4749 } 4750} 4751 4752static void gen_XRSTOR(DisasContext *s, X86DecodedInsn *decode) 4753{ 4754 TCGv_i64 features = tcg_temp_new_i64(); 4755 4756 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4757 gen_helper_xrstor(tcg_env, s->A0, features); 4758 if (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_MPX) { 4759 /* 4760 * XRSTOR is how MPX is enabled, which changes how 4761 * we translate. Thus we need to end the TB. 4762 */ 4763 s->base.is_jmp = DISAS_EOB_NEXT; 4764 } 4765} 4766 4767static void gen_XSAVE(DisasContext *s, X86DecodedInsn *decode) 4768{ 4769 TCGv_i64 features = tcg_temp_new_i64(); 4770 4771 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4772 gen_helper_xsave(tcg_env, s->A0, features); 4773} 4774 4775static void gen_XSAVEOPT(DisasContext *s, X86DecodedInsn *decode) 4776{ 4777 TCGv_i64 features = tcg_temp_new_i64(); 4778 4779 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4780 gen_helper_xsave(tcg_env, s->A0, features); 4781} 4782