1 /* 2 * Decode table flags, mostly based on Intel SDM. 3 * 4 * Copyright (c) 2022 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 typedef enum X86OpType { 23 X86_TYPE_None, 24 25 X86_TYPE_A, /* Implicit */ 26 X86_TYPE_B, /* VEX.vvvv selects a GPR */ 27 X86_TYPE_C, /* REG in the modrm byte selects a control register */ 28 X86_TYPE_D, /* REG in the modrm byte selects a debug register */ 29 X86_TYPE_E, /* ALU modrm operand */ 30 X86_TYPE_F, /* EFLAGS/RFLAGS */ 31 X86_TYPE_G, /* REG in the modrm byte selects a GPR */ 32 X86_TYPE_H, /* For AVX, VEX.vvvv selects an XMM/YMM register */ 33 X86_TYPE_I, /* Immediate */ 34 X86_TYPE_J, /* Relative offset for a jump */ 35 X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */ 36 X86_TYPE_M, /* modrm byte selects a memory operand */ 37 X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */ 38 X86_TYPE_O, /* Absolute address encoded in the instruction */ 39 X86_TYPE_P, /* reg in the modrm byte selects an MMX register */ 40 X86_TYPE_Q, /* MMX modrm operand */ 41 X86_TYPE_R, /* R/M in the modrm byte selects a register */ 42 X86_TYPE_S, /* reg selects a segment register */ 43 X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */ 44 X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */ 45 X86_TYPE_W, /* XMM/YMM modrm operand */ 46 X86_TYPE_X, /* string source */ 47 X86_TYPE_Y, /* string destination */ 48 49 /* Custom */ 50 X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */ 51 X86_TYPE_2op, /* 2-operand RMW instruction */ 52 X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */ 53 X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */ 54 X86_TYPE_1, 55 X86_TYPE_2, 56 X86_TYPE_3, 57 X86_TYPE_4, 58 X86_TYPE_5, 59 X86_TYPE_6, 60 X86_TYPE_7, 61 X86_TYPE_ES, /* Hard-coded segment registers */ 62 X86_TYPE_CS, 63 X86_TYPE_SS, 64 X86_TYPE_DS, 65 X86_TYPE_FS, 66 X86_TYPE_GS, 67 } X86OpType; 68 69 typedef enum X86OpSize { 70 X86_SIZE_None, 71 72 X86_SIZE_a, /* BOUND operand */ 73 X86_SIZE_b, /* byte */ 74 X86_SIZE_d, /* 32-bit */ 75 X86_SIZE_dq, /* SSE/AVX 128-bit */ 76 X86_SIZE_p, /* Far pointer */ 77 X86_SIZE_pd, /* SSE/AVX packed double precision */ 78 X86_SIZE_pi, /* MMX */ 79 X86_SIZE_ps, /* SSE/AVX packed single precision */ 80 X86_SIZE_q, /* 64-bit */ 81 X86_SIZE_qq, /* AVX 256-bit */ 82 X86_SIZE_s, /* Descriptor */ 83 X86_SIZE_sd, /* SSE/AVX scalar double precision */ 84 X86_SIZE_ss, /* SSE/AVX scalar single precision */ 85 X86_SIZE_si, /* 32-bit GPR */ 86 X86_SIZE_v, /* 16/32/64-bit, based on operand size */ 87 X86_SIZE_w, /* 16-bit */ 88 X86_SIZE_x, /* 128/256-bit, based on operand size */ 89 X86_SIZE_y, /* 32/64-bit, based on operand size */ 90 X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */ 91 92 /* Custom */ 93 X86_SIZE_d64, 94 X86_SIZE_f64, 95 X86_SIZE_xh, /* SSE/AVX packed half register */ 96 } X86OpSize; 97 98 typedef enum X86CPUIDFeature { 99 X86_FEAT_None, 100 X86_FEAT_3DNOW, 101 X86_FEAT_ADX, 102 X86_FEAT_AES, 103 X86_FEAT_AVX, 104 X86_FEAT_AVX2, 105 X86_FEAT_BMI1, 106 X86_FEAT_BMI2, 107 X86_FEAT_CMPCCXADD, 108 X86_FEAT_F16C, 109 X86_FEAT_FMA, 110 X86_FEAT_MOVBE, 111 X86_FEAT_PCLMULQDQ, 112 X86_FEAT_SHA_NI, 113 X86_FEAT_SSE, 114 X86_FEAT_SSE2, 115 X86_FEAT_SSE3, 116 X86_FEAT_SSSE3, 117 X86_FEAT_SSE41, 118 X86_FEAT_SSE42, 119 X86_FEAT_SSE4A, 120 } X86CPUIDFeature; 121 122 /* Execution flags */ 123 124 typedef enum X86OpUnit { 125 X86_OP_SKIP, /* not valid or managed by emission function */ 126 X86_OP_SEG, /* segment selector */ 127 X86_OP_CR, /* control register */ 128 X86_OP_DR, /* debug register */ 129 X86_OP_INT, /* loaded into/stored from s->T0/T1 */ 130 X86_OP_IMM, /* immediate */ 131 X86_OP_SSE, /* address in either s->ptrX or s->A0 depending on has_ea */ 132 X86_OP_MMX, /* address in either s->ptrX or s->A0 depending on has_ea */ 133 } X86OpUnit; 134 135 typedef enum X86InsnCheck { 136 /* Illegal or exclusive to 64-bit mode */ 137 X86_CHECK_i64 = 1, 138 X86_CHECK_o64 = 2, 139 140 /* Fault outside protected mode */ 141 X86_CHECK_prot = 4, 142 143 /* Privileged instruction checks */ 144 X86_CHECK_cpl0 = 8, 145 X86_CHECK_vm86_iopl = 16, 146 X86_CHECK_cpl_iopl = 32, 147 X86_CHECK_iopl = X86_CHECK_cpl_iopl | X86_CHECK_vm86_iopl, 148 149 /* Fault if VEX.L=1 */ 150 X86_CHECK_VEX128 = 64, 151 152 /* Fault if VEX.W=1 */ 153 X86_CHECK_W0 = 128, 154 155 /* Fault if VEX.W=0 */ 156 X86_CHECK_W1 = 256, 157 } X86InsnCheck; 158 159 typedef enum X86InsnSpecial { 160 X86_SPECIAL_None, 161 162 /* Accepts LOCK prefix; LOCKed operations do not load or writeback operand 0 */ 163 X86_SPECIAL_HasLock, 164 165 /* Always locked if it has a memory operand (XCHG) */ 166 X86_SPECIAL_Locked, 167 168 /* 169 * Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits 170 * (and writeback zero-extends it to 64 bits if applicable). PREFIX_DATA 171 * does not trigger 16-bit writeback and, as a side effect, high-byte 172 * registers are never used. 173 */ 174 X86_SPECIAL_Op0_Rd, 175 176 /* 177 * Ry/Mb in the manual (PINSRB). However, the high bits are never used by 178 * the instruction in either the register or memory cases; the *real* effect 179 * of this modifier is that high-byte registers are never used, even without 180 * a REX prefix. Therefore, PINSRW does not need it despite having Ry/Mw. 181 */ 182 X86_SPECIAL_Op2_Ry, 183 184 /* 185 * Register operand 2 is extended to full width, while a memory operand 186 * is doubled in size if VEX.L=1. 187 */ 188 X86_SPECIAL_AVXExtMov, 189 190 /* 191 * MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands 192 * become P/P/Q/N, and size "x" becomes "q". 193 */ 194 X86_SPECIAL_MMX, 195 196 /* When loaded into s->T0, register operand 1 is zero/sign extended. */ 197 X86_SPECIAL_SExtT0, 198 X86_SPECIAL_ZExtT0, 199 } X86InsnSpecial; 200 201 /* 202 * Special cases for instructions that operate on XMM/YMM registers. Intel 203 * retconned all of them to have VEX exception classes other than 0 and 13, so 204 * all these only matter for instructions that have a VEX exception class. 205 * Based on tables in the "AVX and SSE Instruction Exception Specification" 206 * section of the manual. 207 */ 208 typedef enum X86VEXSpecial { 209 /* Legacy SSE instructions that allow unaligned operands */ 210 X86_VEX_SSEUnaligned, 211 212 /* 213 * Used for instructions that distinguish the XMM operand type with an 214 * instruction prefix; legacy SSE encodings will allow unaligned operands 215 * for scalar operands only (identified by a REP prefix). In this case, 216 * the decoding table uses "x" for the vector operands instead of specifying 217 * pd/ps/sd/ss individually. 218 */ 219 X86_VEX_REPScalar, 220 221 /* 222 * VEX instructions that only support 256-bit operands with AVX2 (Table 2-17 223 * column 3). Columns 2 and 4 (instructions limited to 256- and 127-bit 224 * operands respectively) are implicit in the presence of dq and qq 225 * operands, and thus handled by decode_op_size. 226 */ 227 X86_VEX_AVX2_256, 228 } X86VEXSpecial; 229 230 231 typedef struct X86OpEntry X86OpEntry; 232 typedef struct X86DecodedInsn X86DecodedInsn; 233 234 /* Decode function for multibyte opcodes. */ 235 typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b); 236 237 /* Code generation function. */ 238 typedef void (*X86GenFunc)(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode); 239 240 struct X86OpEntry { 241 /* Based on the is_decode flags. */ 242 union { 243 X86GenFunc gen; 244 X86DecodeFunc decode; 245 }; 246 /* op0 is always written, op1 and op2 are always read. */ 247 X86OpType op0:8; 248 X86OpSize s0:8; 249 X86OpType op1:8; 250 X86OpSize s1:8; 251 X86OpType op2:8; 252 X86OpSize s2:8; 253 /* Must be I and b respectively if present. */ 254 X86OpType op3:8; 255 X86OpSize s3:8; 256 257 X86InsnSpecial special:8; 258 X86CPUIDFeature cpuid:8; 259 unsigned vex_class:8; 260 X86VEXSpecial vex_special:8; 261 unsigned valid_prefix:16; 262 unsigned check:16; 263 unsigned intercept:8; 264 bool is_decode:1; 265 }; 266 267 typedef struct X86DecodedOp { 268 int8_t n; 269 MemOp ot; /* For b/c/d/p/s/q/v/w/y/z */ 270 X86OpUnit unit; 271 bool has_ea; 272 int offset; /* For MMX and SSE */ 273 274 /* 275 * This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR, 276 * do not access directly! 277 */ 278 TCGv_ptr v_ptr; 279 } X86DecodedOp; 280 281 struct X86DecodedInsn { 282 X86OpEntry e; 283 X86DecodedOp op[3]; 284 target_ulong immediate; 285 AddressParts mem; 286 287 TCGv cc_dst, cc_src, cc_src2; 288 TCGv_i32 cc_op_dynamic; 289 int8_t cc_op; 290 291 uint8_t b; 292 }; 293 294