1/* 2 * New-style decoder for i386 instructions 3 * 4 * Copyright (c) 2022 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22/* 23 * The decoder is mostly based on tables copied from the Intel SDM. As 24 * a result, most operand load and writeback is done entirely in common 25 * table-driven code using the same operand type (X86_TYPE_*) and 26 * size (X86_SIZE_*) codes used in the manual. There are a few differences 27 * though. 28 * 29 * Operand sizes 30 * ------------- 31 * 32 * The manual lists d64 ("cannot encode 32-bit size in 64-bit mode") and f64 33 * ("cannot encode 16-bit or 32-bit size in 64-bit mode") as modifiers of the 34 * "v" or "z" sizes. The decoder simply makes them separate operand sizes. 35 * 36 * The manual lists immediate far destinations as Ap (technically an implicit 37 * argument). The decoder splits them into two immediates, using "Ip" for 38 * the offset part (that comes first in the instruction stream) and "Iw" for 39 * the segment/selector part. The size of the offset is given by s->dflag 40 * and the instructions are illegal in 64-bit mode, so the choice of "Ip" 41 * is somewhat arbitrary; "Iv" or "Iz" would work just as well. 42 * 43 * Operand types 44 * ------------- 45 * 46 * For memory-only operands, if the emitter functions wants to rely on 47 * generic load and writeback, the decoder needs to know the type of the 48 * operand. Therefore, M is often replaced by the more specific EM and WM 49 * (respectively selecting an ALU operand, like the operand type E, or a 50 * vector operand like the operand type W). 51 * 52 * Immediates are almost always signed or masked away in helpers. Two 53 * common exceptions are IN/OUT and absolute jumps. For these, there is 54 * an additional custom operand type "I_unsigned". Alternatively, the 55 * mask could be applied (and the original sign-extended value would be 56 * optimized away by TCG) in the emitter function. 57 * 58 * Finally, a "nop" operand type is used for multi-byte NOPs. It accepts 59 * any value of mod including 11b (unlike M) but it does not try to 60 * interpret the operand (like M). 61 * 62 * Vector operands 63 * --------------- 64 * 65 * The main difference is that the V, U and W types are extended to 66 * cover MMX as well; if an instruction is like 67 * 68 * por Pq, Qq 69 * 66 por Vx, Hx, Wx 70 * 71 * only the second row is included and the instruction is marked as a 72 * valid MMX instruction. The MMX flag directs the decoder to rewrite 73 * the V/U/H/W types to P/N/P/Q if there is no prefix, as well as changing 74 * "x" to "q" if there is no prefix. 75 * 76 * In addition, the ss/ps/sd/pd types are sometimes mushed together as "x" 77 * if the difference is expressed via prefixes. Individual instructions 78 * are separated by prefix in the generator functions. 79 * 80 * There is a custom size "xh" used to address half of a SSE/AVX operand. 81 * This points to a 64-bit operand for SSE operations, 128-bit operand 82 * for 256-bit AVX operands, etc. It is used for conversion operations 83 * such as VCVTPH2PS or VCVTSS2SD. 84 * 85 * There are a couple cases in which instructions (e.g. MOVD) write the 86 * whole XMM or MM register but are established incorrectly in the manual 87 * as "d" or "q". These have to be fixed for the decoder to work correctly. 88 * 89 * VEX exception classes 90 * --------------------- 91 * 92 * Speaking about imprecisions in the manual, the decoder treats all 93 * exception-class 4 instructions as having an optional VEX prefix, and 94 * all exception-class 6 instructions as having a mandatory VEX prefix. 95 * This is true except for a dozen instructions; these are in exception 96 * class 4 but do not ignore the VEX.W bit (which does not even exist 97 * without a VEX prefix). These instructions are mostly listed in Intel's 98 * table 2-16, but with a few exceptions. 99 * 100 * The AMD manual has more precise subclasses for exceptions, and unlike Intel 101 * they list the VEX.W requirements in the exception classes as well (except 102 * when they don't). AMD describes class 6 as "AVX Mixed Memory Argument" 103 * without defining what a mixed memory argument is, but still use 4 as the 104 * primary exception class... except when they don't. 105 * 106 * The summary is: 107 * Intel AMD VEX.W note 108 * ------------------------------------------------------------------- 109 * vpblendd 4 4J 0 110 * vpblendvb 4 4E-X 0 (*) 111 * vpbroadcastq 6 6D 0 (+) 112 * vpermd/vpermps 4 4H 0 (§) 113 * vpermq/vpermpd 4 4H-1 1 (§) 114 * vpermilpd/vpermilps 4 6E 0 (^) 115 * vpmaskmovd 6 4K significant (^) 116 * vpsllv 4 4K significant 117 * vpsrav 4 4J 0 118 * vpsrlv 4 4K significant 119 * vtestps/vtestpd 4 4G 0 120 * 121 * (*) AMD lists VPBLENDVB as related to SSE4.1 PBLENDVB, which may 122 * explain why it is considered exception class 4. However, 123 * Intel says that VEX-only instructions should be in class 6... 124 * 125 * (+) Not found in Intel's table 2-16 126 * 127 * (§) 4H and 4H-1 do not mention VEX.W requirements, which are 128 * however present in the description of the instruction 129 * 130 * (^) these are the two cases in which Intel and AMD disagree on the 131 * primary exception class 132 * 133 * Instructions still in translate.c 134 * --------------------------------- 135 * Generation of TCG opcodes for almost all instructions is in emit.c.inc; 136 * this file interprets the prefixes and opcode bytes down to individual 137 * instruction mnemonics. There is only a handful of opcodes still using 138 * a switch statement to decode modrm bits 3-5 and prefixes after decoding 139 * is complete; these are relics of the older x86 decoder and their code 140 * generation is performed in translate.c. 141 * 142 * These unconverted opcodes also perform their own effective address 143 * generation using the gen_lea_modrm() function. 144 * 145 * There is nothing particularly complicated about them; simply, they don't 146 * need any nasty hacks in the decoder, and they shouldn't get in the way 147 * of the implementation of new x86 instructions, so they are left alone 148 * for the time being. 149 * 150 * x87: 151 * 0xD8 - 0xDF 152 * 153 * privileged/system: 154 * 0x0F 0x00 group 6 (SLDT, STR, LLDT, LTR, VERR, VERW) 155 * 0x0F 0x01 group 7 (SGDT, SIDT, LGDT, LIDT, SMSW, LMSW, INVLPG, 156 * MONITOR, MWAIT, CLAC, STAC, XGETBV, XSETBV, 157 * SWAPGS, RDTSCP) 158 * 0x0F 0xC7 (reg operand) group 9 (RDRAND, RDSEED, RDPID) 159 * 160 * MPX: 161 * 0x0F 0x1A BNDLDX, BNDMOV, BNDCL, BNDCU 162 * 0x0F 0x1B BNDSTX, BNDMOV, BNDMK, BNDCN 163 */ 164 165#define X86_OP_NONE { 0 }, 166 167#define X86_OP_GROUP3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \ 168 .decode = glue(decode_, op), \ 169 .op0 = glue(X86_TYPE_, op0_), \ 170 .s0 = glue(X86_SIZE_, s0_), \ 171 .op1 = glue(X86_TYPE_, op1_), \ 172 .s1 = glue(X86_SIZE_, s1_), \ 173 .op2 = glue(X86_TYPE_, op2_), \ 174 .s2 = glue(X86_SIZE_, s2_), \ 175 .is_decode = true, \ 176 ## __VA_ARGS__ \ 177} 178 179#define X86_OP_GROUP1(op, op0, s0, ...) \ 180 X86_OP_GROUP3(op, op0, s0, 2op, s0, None, None, ## __VA_ARGS__) 181#define X86_OP_GROUP2(op, op0, s0, op1, s1, ...) \ 182 X86_OP_GROUP3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__) 183#define X86_OP_GROUPw(op, op0, s0, ...) \ 184 X86_OP_GROUP3(op, op0, s0, None, None, None, None, ## __VA_ARGS__) 185#define X86_OP_GROUPwr(op, op0, s0, op1, s1, ...) \ 186 X86_OP_GROUP3(op, op0, s0, op1, s1, None, None, ## __VA_ARGS__) 187#define X86_OP_GROUP0(op, ...) \ 188 X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__) 189 190#define X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \ 191 .gen = glue(gen_, op), \ 192 .op0 = glue(X86_TYPE_, op0_), \ 193 .s0 = glue(X86_SIZE_, s0_), \ 194 .op1 = glue(X86_TYPE_, op1_), \ 195 .s1 = glue(X86_SIZE_, s1_), \ 196 .op2 = glue(X86_TYPE_, op2_), \ 197 .s2 = glue(X86_SIZE_, s2_), \ 198 ## __VA_ARGS__ \ 199} 200 201#define X86_OP_ENTRY4(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) \ 202 X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, \ 203 .op3 = X86_TYPE_I, .s3 = X86_SIZE_b, \ 204 ## __VA_ARGS__) 205 206/* 207 * Short forms that are mostly useful for ALU opcodes and other 208 * one-byte opcodes. For vector instructions it is usually 209 * clearer to write all three operands explicitly, because the 210 * corresponding gen_* function will use OP_PTRn rather than s->T0 211 * and s->T1. 212 */ 213#define X86_OP_ENTRYrr(op, op0, s0, op1, s1, ...) \ 214 X86_OP_ENTRY3(op, None, None, op0, s0, op1, s1, ## __VA_ARGS__) 215#define X86_OP_ENTRYwr(op, op0, s0, op1, s1, ...) \ 216 X86_OP_ENTRY3(op, op0, s0, op1, s1, None, None, ## __VA_ARGS__) 217#define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \ 218 X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__) 219#define X86_OP_ENTRYw(op, op0, s0, ...) \ 220 X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__) 221#define X86_OP_ENTRYr(op, op0, s0, ...) \ 222 X86_OP_ENTRY3(op, None, None, op0, s0, None, None, ## __VA_ARGS__) 223#define X86_OP_ENTRY1(op, op0, s0, ...) \ 224 X86_OP_ENTRY3(op, op0, s0, 2op, s0, None, None, ## __VA_ARGS__) 225#define X86_OP_ENTRY0(op, ...) \ 226 X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__) 227 228#define cpuid(feat) .cpuid = X86_FEAT_##feat, 229#define nolea .special = X86_SPECIAL_NoLoadEA, 230#define xchg .special = X86_SPECIAL_Locked, 231#define lock .special = X86_SPECIAL_HasLock, 232#define mmx .special = X86_SPECIAL_MMX, 233#define op0_Rd .special = X86_SPECIAL_Op0_Rd, 234#define op2_Ry .special = X86_SPECIAL_Op2_Ry, 235#define avx_movx .special = X86_SPECIAL_AVXExtMov, 236#define sextT0 .special = X86_SPECIAL_SExtT0, 237#define zextT0 .special = X86_SPECIAL_ZExtT0, 238#define op0_Mw .special = X86_SPECIAL_Op0_Mw, 239#define btEvGv .special = X86_SPECIAL_BitTest, 240 241#define vex1 .vex_class = 1, 242#define vex1_rep3 .vex_class = 1, .vex_special = X86_VEX_REPScalar, 243#define vex2 .vex_class = 2, 244#define vex2_rep3 .vex_class = 2, .vex_special = X86_VEX_REPScalar, 245#define vex3 .vex_class = 3, 246#define vex4 .vex_class = 4, 247#define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned, 248#define vex4_rep5 .vex_class = 4, .vex_special = X86_VEX_REPScalar, 249#define vex5 .vex_class = 5, 250#define vex6 .vex_class = 6, 251#define vex7 .vex_class = 7, 252#define vex8 .vex_class = 8, 253#define vex11 .vex_class = 11, 254#define vex12 .vex_class = 12, 255#define vex13 .vex_class = 13, 256 257#define chk(a) .check = X86_CHECK_##a, 258#define chk2(a, b) .check = X86_CHECK_##a | X86_CHECK_##b, 259#define chk3(a, b, c) .check = X86_CHECK_##a | X86_CHECK_##b | X86_CHECK_##c, 260#define svm(a) .intercept = SVM_EXIT_##a, .has_intercept = true, 261 262#define avx2_256 .vex_special = X86_VEX_AVX2_256, 263 264#define P_00 1 265#define P_66 (1 << PREFIX_DATA) 266#define P_F3 (1 << PREFIX_REPZ) 267#define P_F2 (1 << PREFIX_REPNZ) 268 269#define p_00 .valid_prefix = P_00, 270#define p_66 .valid_prefix = P_66, 271#define p_f3 .valid_prefix = P_F3, 272#define p_f2 .valid_prefix = P_F2, 273#define p_00_66 .valid_prefix = P_00 | P_66, 274#define p_00_f3 .valid_prefix = P_00 | P_F3, 275#define p_66_f2 .valid_prefix = P_66 | P_F2, 276#define p_00_66_f3 .valid_prefix = P_00 | P_66 | P_F3, 277#define p_66_f3_f2 .valid_prefix = P_66 | P_F3 | P_F2, 278#define p_00_66_f3_f2 .valid_prefix = P_00 | P_66 | P_F3 | P_F2, 279 280#define UNKNOWN_OPCODE ((X86OpEntry) {}) 281 282static uint8_t get_modrm(DisasContext *s, CPUX86State *env) 283{ 284 if (!s->has_modrm) { 285 s->modrm = x86_ldub_code(env, s); 286 s->has_modrm = true; 287 } 288 return s->modrm; 289} 290 291static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4]) 292{ 293 if (s->prefix & PREFIX_REPNZ) { 294 return &entries[3]; 295 } else if (s->prefix & PREFIX_REPZ) { 296 return &entries[2]; 297 } else if (s->prefix & PREFIX_DATA) { 298 return &entries[1]; 299 } else { 300 return &entries[0]; 301 } 302} 303 304static void decode_group8(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 305{ 306 static const X86GenFunc group8_gen[8] = { 307 NULL, NULL, NULL, NULL, 308 gen_BT, gen_BTS, gen_BTR, gen_BTC, 309 }; 310 int op = (get_modrm(s, env) >> 3) & 7; 311 entry->gen = group8_gen[op]; 312 if (op == 4) { 313 /* prevent writeback and LOCK for BT */ 314 entry->op1 = entry->op0; 315 entry->op0 = X86_TYPE_None; 316 entry->s0 = X86_SIZE_None; 317 } else { 318 entry->special = X86_SPECIAL_HasLock; 319 } 320} 321 322static void decode_group9(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 323{ 324 static const X86OpEntry group9_reg = 325 X86_OP_ENTRY0(multi0F); /* unconverted */ 326 static const X86OpEntry cmpxchg8b = 327 X86_OP_ENTRY1(CMPXCHG8B, M,q, lock p_00 cpuid(CX8)); 328 static const X86OpEntry cmpxchg16b = 329 X86_OP_ENTRY1(CMPXCHG16B, M,dq, lock p_00 cpuid(CX16)); 330 331 int modrm = get_modrm(s, env); 332 int op = (modrm >> 3) & 7; 333 334 if ((modrm >> 6) == 3) { 335 *entry = group9_reg; 336 } else if (op == 1) { 337 *entry = REX_W(s) ? cmpxchg16b : cmpxchg8b; 338 } 339} 340 341static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 342{ 343 static const X86OpEntry group15_reg[8] = { 344 [0] = X86_OP_ENTRYw(RDxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3), 345 [1] = X86_OP_ENTRYw(RDxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3), 346 [2] = X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3 zextT0), 347 [3] = X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3 zextT0), 348 [5] = X86_OP_ENTRY0(LFENCE, cpuid(SSE) p_00), 349 [6] = X86_OP_ENTRY0(MFENCE, cpuid(SSE2) p_00), 350 [7] = X86_OP_ENTRY0(SFENCE, cpuid(SSE) p_00), 351 }; 352 353 static const X86OpEntry group15_mem[8] = { 354 [0] = X86_OP_ENTRYw(FXSAVE, M,y, cpuid(FXSR) p_00), 355 [1] = X86_OP_ENTRYr(FXRSTOR, M,y, cpuid(FXSR) p_00), 356 [2] = X86_OP_ENTRYr(LDMXCSR, E,d, vex5 chk(VEX128) p_00), 357 [3] = X86_OP_ENTRYw(STMXCSR, E,d, vex5 chk(VEX128) p_00), 358 [4] = X86_OP_ENTRYw(XSAVE, M,y, cpuid(XSAVE) p_00), 359 [5] = X86_OP_ENTRYr(XRSTOR, M,y, cpuid(XSAVE) p_00), 360 [6] = X86_OP_ENTRYw(XSAVEOPT, M,b, cpuid(XSAVEOPT) p_00), 361 [7] = X86_OP_ENTRYw(NOP, M,b, cpuid(CLFLUSH) p_00), 362 }; 363 364 static const X86OpEntry group15_mem_66[8] = { 365 [6] = X86_OP_ENTRYw(NOP, M,b, cpuid(CLWB)), 366 [7] = X86_OP_ENTRYw(NOP, M,b, cpuid(CLFLUSHOPT)), 367 }; 368 369 uint8_t modrm = get_modrm(s, env); 370 int op = (modrm >> 3) & 7; 371 372 if ((modrm >> 6) == 3) { 373 *entry = group15_reg[op]; 374 } else if (s->prefix & PREFIX_DATA) { 375 *entry = group15_mem_66[op]; 376 } else { 377 *entry = group15_mem[op]; 378 } 379} 380 381static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 382{ 383 static const X86GenFunc group17_gen[8] = { 384 NULL, gen_BLSR, gen_BLSMSK, gen_BLSI, 385 }; 386 int op = (get_modrm(s, env) >> 3) & 7; 387 entry->gen = group17_gen[op]; 388} 389 390static void decode_group12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 391{ 392 static const X86OpEntry opcodes_group12[8] = { 393 {}, 394 {}, 395 X86_OP_ENTRY3(PSRLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 396 {}, 397 X86_OP_ENTRY3(PSRAW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 398 {}, 399 X86_OP_ENTRY3(PSLLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 400 {}, 401 }; 402 403 int op = (get_modrm(s, env) >> 3) & 7; 404 *entry = opcodes_group12[op]; 405} 406 407static void decode_group13(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 408{ 409 static const X86OpEntry opcodes_group13[8] = { 410 {}, 411 {}, 412 X86_OP_ENTRY3(PSRLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 413 {}, 414 X86_OP_ENTRY3(PSRAD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 415 {}, 416 X86_OP_ENTRY3(PSLLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 417 {}, 418 }; 419 420 int op = (get_modrm(s, env) >> 3) & 7; 421 *entry = opcodes_group13[op]; 422} 423 424static void decode_group14(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 425{ 426 static const X86OpEntry opcodes_group14[8] = { 427 /* grp14 */ 428 {}, 429 {}, 430 X86_OP_ENTRY3(PSRLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 431 X86_OP_ENTRY3(PSRLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66), 432 {}, 433 {}, 434 X86_OP_ENTRY3(PSLLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 435 X86_OP_ENTRY3(PSLLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66), 436 }; 437 438 int op = (get_modrm(s, env) >> 3) & 7; 439 *entry = opcodes_group14[op]; 440} 441 442static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 443{ 444 static const X86OpEntry opcodes_0F6F[4] = { 445 X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex5 mmx), /* movq */ 446 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */ 447 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */ 448 {}, 449 }; 450 *entry = *decode_by_prefix(s, opcodes_0F6F); 451} 452 453static void decode_0F70(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 454{ 455 static const X86OpEntry pshufw[4] = { 456 X86_OP_ENTRY3(PSHUFW, P,q, Q,q, I,b, vex4 mmx), 457 X86_OP_ENTRY3(PSHUFD, V,x, W,x, I,b, vex4 avx2_256), 458 X86_OP_ENTRY3(PSHUFHW, V,x, W,x, I,b, vex4 avx2_256), 459 X86_OP_ENTRY3(PSHUFLW, V,x, W,x, I,b, vex4 avx2_256), 460 }; 461 462 *entry = *decode_by_prefix(s, pshufw); 463} 464 465static void decode_0F77(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 466{ 467 if (!(s->prefix & PREFIX_VEX)) { 468 entry->gen = gen_EMMS; 469 } else if (!s->vex_l) { 470 entry->gen = gen_VZEROUPPER; 471 entry->vex_class = 8; 472 } else { 473 entry->gen = gen_VZEROALL; 474 entry->vex_class = 8; 475 } 476} 477 478static void decode_0F78(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 479{ 480 static const X86OpEntry opcodes_0F78[4] = { 481 {}, 482 X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), /* AMD extension */ 483 {}, 484 X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)), /* AMD extension */ 485 }; 486 *entry = *decode_by_prefix(s, opcodes_0F78); 487} 488 489static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 490{ 491 if (s->prefix & PREFIX_REPNZ) { 492 entry->gen = gen_INSERTQ_r; /* AMD extension */ 493 } else if (s->prefix & PREFIX_DATA) { 494 entry->gen = gen_EXTRQ_r; /* AMD extension */ 495 } else { 496 entry->gen = NULL; 497 }; 498} 499 500static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 501{ 502 static const X86OpEntry opcodes_0F7E[4] = { 503 X86_OP_ENTRY3(MOVD_from, E,y, None,None, P,y, vex5 mmx), 504 X86_OP_ENTRY3(MOVD_from, E,y, None,None, V,y, vex5), 505 X86_OP_ENTRY3(MOVQ, V,x, None,None, W,q, vex5), /* wrong dest Vy on SDM! */ 506 {}, 507 }; 508 *entry = *decode_by_prefix(s, opcodes_0F7E); 509} 510 511static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 512{ 513 static const X86OpEntry opcodes_0F7F[4] = { 514 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex5 mmx), /* movq */ 515 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */ 516 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* movdqu */ 517 {}, 518 }; 519 *entry = *decode_by_prefix(s, opcodes_0F7F); 520} 521 522static void decode_0FB8(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 523{ 524 static const X86OpEntry popcnt = 525 X86_OP_ENTRYwr(POPCNT, G,v, E,v, cpuid(POPCNT) zextT0); 526 527 if (s->prefix & PREFIX_REPZ) { 528 *entry = popcnt; 529 } else { 530 memset(entry, 0, sizeof(*entry)); 531 } 532} 533 534static void decode_0FBC(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 535{ 536 /* For BSF, pass 2op as the third operand so that we can use zextT0 */ 537 static const X86OpEntry opcodes_0FBC[4] = { 538 X86_OP_ENTRY3(BSF, G,v, E,v, 2op,v, zextT0), 539 X86_OP_ENTRY3(BSF, G,v, E,v, 2op,v, zextT0), /* 0x66 */ 540 X86_OP_ENTRYwr(TZCNT, G,v, E,v, zextT0), /* 0xf3 */ 541 X86_OP_ENTRY3(BSF, G,v, E,v, 2op,v, zextT0), /* 0xf2 */ 542 }; 543 if (!(s->cpuid_ext3_features & CPUID_EXT3_ABM)) { 544 *entry = opcodes_0FBC[0]; 545 } else { 546 *entry = *decode_by_prefix(s, opcodes_0FBC); 547 } 548} 549 550static void decode_0FBD(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 551{ 552 /* For BSR, pass 2op as the third operand so that we can use zextT0 */ 553 static const X86OpEntry opcodes_0FBD[4] = { 554 X86_OP_ENTRY3(BSR, G,v, E,v, 2op,v, zextT0), 555 X86_OP_ENTRY3(BSR, G,v, E,v, 2op,v, zextT0), /* 0x66 */ 556 X86_OP_ENTRYwr(LZCNT, G,v, E,v, zextT0), /* 0xf3 */ 557 X86_OP_ENTRY3(BSR, G,v, E,v, 2op,v, zextT0), /* 0xf2 */ 558 }; 559 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) { 560 *entry = opcodes_0FBD[0]; 561 } else { 562 *entry = *decode_by_prefix(s, opcodes_0FBD); 563 } 564} 565 566static void decode_0FD6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 567{ 568 static const X86OpEntry movq[4] = { 569 {}, 570 X86_OP_ENTRY3(MOVQ, W,x, None, None, V,q, vex5), 571 X86_OP_ENTRY3(MOVq_dq, V,dq, None, None, N,q), 572 X86_OP_ENTRY3(MOVq_dq, P,q, None, None, U,q), 573 }; 574 575 *entry = *decode_by_prefix(s, movq); 576} 577 578static const X86OpEntry opcodes_0F38_00toEF[240] = { 579 [0x00] = X86_OP_ENTRY3(PSHUFB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 580 [0x01] = X86_OP_ENTRY3(PHADDW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 581 [0x02] = X86_OP_ENTRY3(PHADDD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 582 [0x03] = X86_OP_ENTRY3(PHADDSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 583 [0x04] = X86_OP_ENTRY3(PMADDUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 584 [0x05] = X86_OP_ENTRY3(PHSUBW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 585 [0x06] = X86_OP_ENTRY3(PHSUBD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 586 [0x07] = X86_OP_ENTRY3(PHSUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 587 588 [0x10] = X86_OP_ENTRY2(PBLENDVB, V,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 589 [0x13] = X86_OP_ENTRY2(VCVTPH2PS, V,x, W,xh, vex11 chk(W0) cpuid(F16C) p_66), 590 [0x14] = X86_OP_ENTRY2(BLENDVPS, V,x, W,x, vex4 cpuid(SSE41) p_66), 591 [0x15] = X86_OP_ENTRY2(BLENDVPD, V,x, W,x, vex4 cpuid(SSE41) p_66), 592 /* Listed incorrectly as type 4 */ 593 [0x16] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), /* vpermps */ 594 [0x17] = X86_OP_ENTRY3(VPTEST, None,None, V,x, W,x, vex4 cpuid(SSE41) p_66), 595 596 /* 597 * Source operand listed as Mq/Ux and similar in the manual; incorrectly listed 598 * as 128-bit only in 2-17. 599 */ 600 [0x20] = X86_OP_ENTRY3(VPMOVSXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 601 [0x21] = X86_OP_ENTRY3(VPMOVSXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 602 [0x22] = X86_OP_ENTRY3(VPMOVSXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 603 [0x23] = X86_OP_ENTRY3(VPMOVSXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 604 [0x24] = X86_OP_ENTRY3(VPMOVSXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 605 [0x25] = X86_OP_ENTRY3(VPMOVSXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 606 607 /* Same as PMOVSX. */ 608 [0x30] = X86_OP_ENTRY3(VPMOVZXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 609 [0x31] = X86_OP_ENTRY3(VPMOVZXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 610 [0x32] = X86_OP_ENTRY3(VPMOVZXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 611 [0x33] = X86_OP_ENTRY3(VPMOVZXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 612 [0x34] = X86_OP_ENTRY3(VPMOVZXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 613 [0x35] = X86_OP_ENTRY3(VPMOVZXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 614 [0x36] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), 615 [0x37] = X86_OP_ENTRY3(PCMPGTQ, V,x, H,x, W,x, vex4 cpuid(SSE42) avx2_256 p_66), 616 617 [0x40] = X86_OP_ENTRY3(PMULLD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 618 [0x41] = X86_OP_ENTRY3(VPHMINPOSUW, V,dq, None,None, W,dq, vex4 cpuid(SSE41) p_66), 619 /* Listed incorrectly as type 4 */ 620 [0x45] = X86_OP_ENTRY3(VPSRLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66), 621 [0x46] = X86_OP_ENTRY3(VPSRAV, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX2) p_66), 622 [0x47] = X86_OP_ENTRY3(VPSLLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66), 623 624 [0x90] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vpgatherdd/q */ 625 [0x91] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vpgatherqd/q */ 626 [0x92] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vgatherdps/d */ 627 [0x93] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vgatherqps/d */ 628 629 /* Should be exception type 2 but they do not have legacy SSE equivalents? */ 630 [0x96] = X86_OP_ENTRY3(VFMADDSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 631 [0x97] = X86_OP_ENTRY3(VFMSUBADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 632 633 [0xa6] = X86_OP_ENTRY3(VFMADDSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 634 [0xa7] = X86_OP_ENTRY3(VFMSUBADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 635 636 [0xb6] = X86_OP_ENTRY3(VFMADDSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 637 [0xb7] = X86_OP_ENTRY3(VFMSUBADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 638 639 [0x08] = X86_OP_ENTRY3(PSIGNB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 640 [0x09] = X86_OP_ENTRY3(PSIGNW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 641 [0x0a] = X86_OP_ENTRY3(PSIGND, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 642 [0x0b] = X86_OP_ENTRY3(PMULHRSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 643 /* Listed incorrectly as type 4 */ 644 [0x0c] = X86_OP_ENTRY3(VPERMILPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_00_66), 645 [0x0d] = X86_OP_ENTRY3(VPERMILPD, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 646 [0x0e] = X86_OP_ENTRY3(VTESTPS, None,None, V,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 647 [0x0f] = X86_OP_ENTRY3(VTESTPD, None,None, V,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 648 649 [0x18] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 chk(W0) cpuid(AVX) p_66), /* vbroadcastss */ 650 [0x19] = X86_OP_ENTRY3(VPBROADCASTQ, V,qq, None,None, W,q, vex6 chk(W0) cpuid(AVX) p_66), /* vbroadcastsd */ 651 [0x1a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 chk(W0) cpuid(AVX) p_66), 652 [0x1c] = X86_OP_ENTRY3(PABSB, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 653 [0x1d] = X86_OP_ENTRY3(PABSW, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 654 [0x1e] = X86_OP_ENTRY3(PABSD, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 655 656 [0x28] = X86_OP_ENTRY3(PMULDQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 657 [0x29] = X86_OP_ENTRY3(PCMPEQQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 658 [0x2a] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex1 cpuid(SSE41) avx2_256 p_66), /* movntdqa */ 659 [0x2b] = X86_OP_ENTRY3(VPACKUSDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 660 [0x2c] = X86_OP_ENTRY3(VMASKMOVPS, V,x, H,x, WM,x, vex6 chk(W0) cpuid(AVX) p_66), 661 [0x2d] = X86_OP_ENTRY3(VMASKMOVPD, V,x, H,x, WM,x, vex6 chk(W0) cpuid(AVX) p_66), 662 /* Incorrectly listed as Mx,Hx,Vx in the manual */ 663 [0x2e] = X86_OP_ENTRY3(VMASKMOVPS_st, M,x, V,x, H,x, vex6 chk(W0) cpuid(AVX) p_66), 664 [0x2f] = X86_OP_ENTRY3(VMASKMOVPD_st, M,x, V,x, H,x, vex6 chk(W0) cpuid(AVX) p_66), 665 666 [0x38] = X86_OP_ENTRY3(PMINSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 667 [0x39] = X86_OP_ENTRY3(PMINSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 668 [0x3a] = X86_OP_ENTRY3(PMINUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 669 [0x3b] = X86_OP_ENTRY3(PMINUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 670 [0x3c] = X86_OP_ENTRY3(PMAXSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 671 [0x3d] = X86_OP_ENTRY3(PMAXSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 672 [0x3e] = X86_OP_ENTRY3(PMAXUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 673 [0x3f] = X86_OP_ENTRY3(PMAXUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 674 675 /* VPBROADCASTQ not listed as W0 in table 2-16 */ 676 [0x58] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 chk(W0) cpuid(AVX2) p_66), 677 [0x59] = X86_OP_ENTRY3(VPBROADCASTQ, V,x, None,None, W,q, vex6 chk(W0) cpuid(AVX2) p_66), 678 [0x5a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 chk(W0) cpuid(AVX2) p_66), 679 680 [0x78] = X86_OP_ENTRY3(VPBROADCASTB, V,x, None,None, W,b, vex6 chk(W0) cpuid(AVX2) p_66), 681 [0x79] = X86_OP_ENTRY3(VPBROADCASTW, V,x, None,None, W,w, vex6 chk(W0) cpuid(AVX2) p_66), 682 683 [0x8c] = X86_OP_ENTRY3(VPMASKMOV, V,x, H,x, WM,x, vex6 cpuid(AVX2) p_66), 684 [0x8e] = X86_OP_ENTRY3(VPMASKMOV_st, M,x, V,x, H,x, vex6 cpuid(AVX2) p_66), 685 686 /* Should be exception type 2 or 3 but they do not have legacy SSE equivalents? */ 687 [0x98] = X86_OP_ENTRY3(VFMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 688 [0x99] = X86_OP_ENTRY3(VFMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 689 [0x9a] = X86_OP_ENTRY3(VFMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 690 [0x9b] = X86_OP_ENTRY3(VFMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 691 [0x9c] = X86_OP_ENTRY3(VFNMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 692 [0x9d] = X86_OP_ENTRY3(VFNMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 693 [0x9e] = X86_OP_ENTRY3(VFNMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 694 [0x9f] = X86_OP_ENTRY3(VFNMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 695 696 [0xa8] = X86_OP_ENTRY3(VFMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 697 [0xa9] = X86_OP_ENTRY3(VFMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 698 [0xaa] = X86_OP_ENTRY3(VFMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 699 [0xab] = X86_OP_ENTRY3(VFMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 700 [0xac] = X86_OP_ENTRY3(VFNMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 701 [0xad] = X86_OP_ENTRY3(VFNMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 702 [0xae] = X86_OP_ENTRY3(VFNMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 703 [0xaf] = X86_OP_ENTRY3(VFNMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 704 705 [0xb8] = X86_OP_ENTRY3(VFMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 706 [0xb9] = X86_OP_ENTRY3(VFMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 707 [0xba] = X86_OP_ENTRY3(VFMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 708 [0xbb] = X86_OP_ENTRY3(VFMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 709 [0xbc] = X86_OP_ENTRY3(VFNMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 710 [0xbd] = X86_OP_ENTRY3(VFNMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 711 [0xbe] = X86_OP_ENTRY3(VFNMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 712 [0xbf] = X86_OP_ENTRY3(VFNMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 713 714 [0xc8] = X86_OP_ENTRY2(SHA1NEXTE, V,dq, W,dq, cpuid(SHA_NI)), 715 [0xc9] = X86_OP_ENTRY2(SHA1MSG1, V,dq, W,dq, cpuid(SHA_NI)), 716 [0xca] = X86_OP_ENTRY2(SHA1MSG2, V,dq, W,dq, cpuid(SHA_NI)), 717 [0xcb] = X86_OP_ENTRY2(SHA256RNDS2, V,dq, W,dq, cpuid(SHA_NI)), 718 [0xcc] = X86_OP_ENTRY2(SHA256MSG1, V,dq, W,dq, cpuid(SHA_NI)), 719 [0xcd] = X86_OP_ENTRY2(SHA256MSG2, V,dq, W,dq, cpuid(SHA_NI)), 720 721 [0xdb] = X86_OP_ENTRY3(VAESIMC, V,dq, None,None, W,dq, vex4 cpuid(AES) p_66), 722 [0xdc] = X86_OP_ENTRY3(VAESENC, V,x, H,x, W,x, vex4 cpuid(AES) p_66), 723 [0xdd] = X86_OP_ENTRY3(VAESENCLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66), 724 [0xde] = X86_OP_ENTRY3(VAESDEC, V,x, H,x, W,x, vex4 cpuid(AES) p_66), 725 [0xdf] = X86_OP_ENTRY3(VAESDECLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66), 726 727 /* 728 * REG selects srcdest2 operand, VEX.vvvv selects src3. VEX class not found 729 * in manual, assumed to be 13 from the VEX.L0 constraint. 730 */ 731 [0xe0] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 732 [0xe1] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 733 [0xe2] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 734 [0xe3] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 735 [0xe4] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 736 [0xe5] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 737 [0xe6] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 738 [0xe7] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 739 740 [0xe8] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 741 [0xe9] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 742 [0xea] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 743 [0xeb] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 744 [0xec] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 745 [0xed] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 746 [0xee] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 747 [0xef] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 748}; 749 750/* five rows for no prefix, 66, F3, F2, 66+F2 */ 751static const X86OpEntry opcodes_0F38_F0toFF[16][5] = { 752 [0] = { 753 X86_OP_ENTRYwr(MOVBE, G,y, M,y, cpuid(MOVBE)), 754 X86_OP_ENTRYwr(MOVBE, G,w, M,w, cpuid(MOVBE)), 755 {}, 756 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)), 757 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)), 758 }, 759 [1] = { 760 X86_OP_ENTRYwr(MOVBE, M,y, G,y, cpuid(MOVBE)), 761 X86_OP_ENTRYwr(MOVBE, M,w, G,w, cpuid(MOVBE)), 762 {}, 763 X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)), 764 X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)), 765 }, 766 [2] = { 767 X86_OP_ENTRY3(ANDN, G,y, B,y, E,y, vex13 cpuid(BMI1)), 768 {}, 769 {}, 770 {}, 771 {}, 772 }, 773 [3] = { 774 X86_OP_GROUP3(group17, B,y, None,None, E,y, vex13 cpuid(BMI1)), 775 {}, 776 {}, 777 {}, 778 {}, 779 }, 780 [5] = { 781 X86_OP_ENTRY3(BZHI, G,y, E,y, B,y, vex13 cpuid(BMI1)), 782 {}, 783 X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 zextT0 cpuid(BMI2)), 784 X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 zextT0 cpuid(BMI2)), 785 {}, 786 }, 787 [6] = { 788 {}, 789 X86_OP_ENTRY2(ADCX, G,y, E,y, cpuid(ADX)), 790 X86_OP_ENTRY2(ADOX, G,y, E,y, cpuid(ADX)), 791 X86_OP_ENTRY3(MULX, /* B,y, */ G,y, E,y, 2,y, vex13 cpuid(BMI2)), 792 {}, 793 }, 794 [7] = { 795 X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 zextT0 cpuid(BMI1)), 796 X86_OP_ENTRY3(SHLX, G,y, E,y, B,y, vex13 cpuid(BMI1)), 797 X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 sextT0 cpuid(BMI1)), 798 X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 zextT0 cpuid(BMI1)), 799 {}, 800 }, 801}; 802 803static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 804{ 805 *b = x86_ldub_code(env, s); 806 if (*b < 0xf0) { 807 *entry = opcodes_0F38_00toEF[*b]; 808 } else { 809 int row = 0; 810 if (s->prefix & PREFIX_REPZ) { 811 /* The REPZ (F3) prefix has priority over 66 */ 812 row = 2; 813 } else { 814 row += s->prefix & PREFIX_REPNZ ? 3 : 0; 815 row += s->prefix & PREFIX_DATA ? 1 : 0; 816 } 817 *entry = opcodes_0F38_F0toFF[*b & 15][row]; 818 } 819} 820 821static void decode_VINSERTPS(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 822{ 823 static const X86OpEntry 824 vinsertps_reg = X86_OP_ENTRY4(VINSERTPS_r, V,dq, H,dq, U,dq, vex5 cpuid(SSE41) p_66), 825 vinsertps_mem = X86_OP_ENTRY4(VINSERTPS_m, V,dq, H,dq, M,d, vex5 cpuid(SSE41) p_66); 826 827 int modrm = get_modrm(s, env); 828 *entry = (modrm >> 6) == 3 ? vinsertps_reg : vinsertps_mem; 829} 830 831static const X86OpEntry opcodes_0F3A[256] = { 832 /* 833 * These are VEX-only, but incorrectly listed in the manual as exception type 4. 834 * Also the "qq" instructions are sometimes omitted by Table 2-17, but are VEX256 835 * only. 836 */ 837 [0x00] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 chk(W1) cpuid(AVX2) p_66), 838 [0x01] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 chk(W1) cpuid(AVX2) p_66), /* VPERMPD */ 839 [0x02] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX2) p_66), /* VPBLENDD */ 840 [0x04] = X86_OP_ENTRY3(VPERMILPS_i, V,x, W,x, I,b, vex6 chk(W0) cpuid(AVX) p_66), 841 [0x05] = X86_OP_ENTRY3(VPERMILPD_i, V,x, W,x, I,b, vex6 chk(W0) cpuid(AVX) p_66), 842 [0x06] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX) p_66), 843 844 [0x14] = X86_OP_ENTRY3(PEXTRB, E,b, V,dq, I,b, vex5 cpuid(SSE41) op0_Rd p_66), 845 [0x15] = X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE41) op0_Rd p_66), 846 [0x16] = X86_OP_ENTRY3(PEXTR, E,y, V,dq, I,b, vex5 cpuid(SSE41) p_66), 847 [0x17] = X86_OP_ENTRY3(VEXTRACTPS, E,d, V,dq, I,b, vex5 cpuid(SSE41) p_66), 848 [0x1d] = X86_OP_ENTRY3(VCVTPS2PH, W,xh, V,x, I,b, vex11 chk(W0) cpuid(F16C) p_66), 849 850 [0x20] = X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE41) op2_Ry p_66), 851 [0x21] = X86_OP_GROUP0(VINSERTPS), 852 [0x22] = X86_OP_ENTRY4(PINSR, V,dq, H,dq, E,y, vex5 cpuid(SSE41) p_66), 853 854 [0x40] = X86_OP_ENTRY4(VDDPS, V,x, H,x, W,x, vex2 cpuid(SSE41) p_66), 855 [0x41] = X86_OP_ENTRY4(VDDPD, V,dq, H,dq, W,dq, vex2 cpuid(SSE41) p_66), 856 [0x42] = X86_OP_ENTRY4(VMPSADBW, V,x, H,x, W,x, vex2 cpuid(SSE41) avx2_256 p_66), 857 [0x44] = X86_OP_ENTRY4(PCLMULQDQ, V,dq, H,dq, W,dq, vex4 cpuid(PCLMULQDQ) p_66), 858 [0x46] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), 859 860 [0x60] = X86_OP_ENTRY4(PCMPESTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66), 861 [0x61] = X86_OP_ENTRY4(PCMPESTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66), 862 [0x62] = X86_OP_ENTRY4(PCMPISTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66), 863 [0x63] = X86_OP_ENTRY4(PCMPISTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66), 864 865 [0x08] = X86_OP_ENTRY3(VROUNDPS, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66), 866 [0x09] = X86_OP_ENTRY3(VROUNDPD, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66), 867 /* 868 * Not listed as four operand in the manual. Also writes and reads 128-bits 869 * from the first two operands due to the V operand picking higher entries of 870 * the H operand; the "Vss,Hss,Wss" description from the manual is incorrect. 871 * For other unary operations such as VSQRTSx this is hidden by the "REPScalar" 872 * value of vex_special, because the table lists the operand types of VSQRTPx. 873 */ 874 [0x0a] = X86_OP_ENTRY4(VROUNDSS, V,x, H,x, W,ss, vex3 cpuid(SSE41) p_66), 875 [0x0b] = X86_OP_ENTRY4(VROUNDSD, V,x, H,x, W,sd, vex3 cpuid(SSE41) p_66), 876 [0x0c] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66), 877 [0x0d] = X86_OP_ENTRY4(VBLENDPD, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66), 878 [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 879 [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 880 881 [0x18] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX) p_66), 882 [0x19] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 chk(W0) cpuid(AVX) p_66), 883 884 [0x38] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), 885 [0x39] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 chk(W0) cpuid(AVX2) p_66), 886 887 /* Listed incorrectly as type 4 */ 888 [0x4a] = X86_OP_ENTRY4(VBLENDVPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 889 [0x4b] = X86_OP_ENTRY4(VBLENDVPD, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 890 [0x4c] = X86_OP_ENTRY4(VPBLENDVB, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66 avx2_256), 891 892 [0xcc] = X86_OP_ENTRY3(SHA1RNDS4, V,dq, W,dq, I,b, cpuid(SHA_NI)), 893 894 [0xdf] = X86_OP_ENTRY3(VAESKEYGEN, V,dq, W,dq, I,b, vex4 cpuid(AES) p_66), 895 896 [0xF0] = X86_OP_ENTRY3(RORX, G,y, E,y, I,b, vex13 cpuid(BMI2) p_f2), 897}; 898 899static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 900{ 901 *b = x86_ldub_code(env, s); 902 *entry = opcodes_0F3A[*b]; 903} 904 905/* 906 * There are some mistakes in the operands in the manual, and the load/store/register 907 * cases are easiest to keep separate, so the entries for 10-17 follow simplicity and 908 * efficiency of implementation rather than copying what the manual says. 909 * 910 * In particular: 911 * 912 * 1) "VMOVSS m32, xmm1" and "VMOVSD m64, xmm1" do not support VEX.vvvv != 1111b, 913 * but this is not mentioned in the tables. 914 * 915 * 2) MOVHLPS, MOVHPS, MOVHPD, MOVLPD, MOVLPS read the high quadword of one of their 916 * operands, which must therefore be dq; MOVLPD and MOVLPS also write the high 917 * quadword of the V operand. 918 */ 919static void decode_0F10(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 920{ 921 static const X86OpEntry opcodes_0F10_reg[4] = { 922 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */ 923 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */ 924 X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex5), 925 X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex5), /* MOVSD */ 926 }; 927 928 static const X86OpEntry opcodes_0F10_mem[4] = { 929 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */ 930 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */ 931 X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex5), 932 X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex5), 933 }; 934 935 if ((get_modrm(s, env) >> 6) == 3) { 936 *entry = *decode_by_prefix(s, opcodes_0F10_reg); 937 } else { 938 *entry = *decode_by_prefix(s, opcodes_0F10_mem); 939 } 940} 941 942static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 943{ 944 static const X86OpEntry opcodes_0F11_reg[4] = { 945 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ 946 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ 947 X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5), 948 X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */ 949 }; 950 951 static const X86OpEntry opcodes_0F11_mem[4] = { 952 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ 953 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ 954 X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5), 955 X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */ 956 }; 957 958 if ((get_modrm(s, env) >> 6) == 3) { 959 *entry = *decode_by_prefix(s, opcodes_0F11_reg); 960 } else { 961 *entry = *decode_by_prefix(s, opcodes_0F11_mem); 962 } 963} 964 965static void decode_0F12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 966{ 967 static const X86OpEntry opcodes_0F12_mem[4] = { 968 /* 969 * Use dq for operand for compatibility with gen_MOVSD and 970 * to allow VEX128 only. 971 */ 972 X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPS */ 973 X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPD */ 974 X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)), 975 X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex5 cpuid(SSE3)), /* qq if VEX.256 */ 976 }; 977 static const X86OpEntry opcodes_0F12_reg[4] = { 978 X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex7), 979 X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex5), /* MOVLPD */ 980 X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)), 981 X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex5 cpuid(SSE3)), 982 }; 983 984 if ((get_modrm(s, env) >> 6) == 3) { 985 *entry = *decode_by_prefix(s, opcodes_0F12_reg); 986 } else { 987 *entry = *decode_by_prefix(s, opcodes_0F12_mem); 988 if ((s->prefix & PREFIX_REPNZ) && s->vex_l) { 989 entry->s2 = X86_SIZE_qq; 990 } 991 } 992} 993 994static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 995{ 996 static const X86OpEntry opcodes_0F16_mem[4] = { 997 /* 998 * Operand 1 technically only reads the low 64 bits, but uses dq so that 999 * it is easier to check for op0 == op1 in an endianness-neutral manner. 1000 */ 1001 X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPS */ 1002 X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPD */ 1003 X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)), 1004 {}, 1005 }; 1006 static const X86OpEntry opcodes_0F16_reg[4] = { 1007 /* Same as above, operand 1 could be Hq if it wasn't for big-endian. */ 1008 X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex7), 1009 X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex5), /* MOVHPD */ 1010 X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)), 1011 {}, 1012 }; 1013 1014 if ((get_modrm(s, env) >> 6) == 3) { 1015 *entry = *decode_by_prefix(s, opcodes_0F16_reg); 1016 } else { 1017 *entry = *decode_by_prefix(s, opcodes_0F16_mem); 1018 } 1019} 1020 1021static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1022{ 1023 static const X86OpEntry opcodes_0F2A[4] = { 1024 X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q), 1025 X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q), 1026 X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3), 1027 X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3), 1028 }; 1029 *entry = *decode_by_prefix(s, opcodes_0F2A); 1030} 1031 1032static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1033{ 1034 static const X86OpEntry opcodes_0F2B[4] = { 1035 X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPS */ 1036 X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPD */ 1037 /* AMD extensions */ 1038 X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSS */ 1039 X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSD */ 1040 }; 1041 1042 *entry = *decode_by_prefix(s, opcodes_0F2B); 1043} 1044 1045static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1046{ 1047 static const X86OpEntry opcodes_0F2C[4] = { 1048 /* Listed as ps/pd in the manual, but CVTTPS2PI only reads 64-bit. */ 1049 X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,q), 1050 X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,dq), 1051 X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,ss, vex3), 1052 X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,sd, vex3), 1053 }; 1054 *entry = *decode_by_prefix(s, opcodes_0F2C); 1055} 1056 1057static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1058{ 1059 static const X86OpEntry opcodes_0F2D[4] = { 1060 /* Listed as ps/pd in the manual, but CVTPS2PI only reads 64-bit. */ 1061 X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,q), 1062 X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,dq), 1063 X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,ss, vex3), 1064 X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,sd, vex3), 1065 }; 1066 *entry = *decode_by_prefix(s, opcodes_0F2D); 1067} 1068 1069static void decode_VxCOMISx(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1070{ 1071 /* 1072 * VUCOMISx and VCOMISx are different and use no-prefix and 0x66 for SS and SD 1073 * respectively. Scalar values usually are associated with 0xF2 and 0xF3, for 1074 * which X86_VEX_REPScalar exists, but here it has to be decoded by hand. 1075 */ 1076 entry->s1 = entry->s2 = (s->prefix & PREFIX_DATA ? X86_SIZE_sd : X86_SIZE_ss); 1077 entry->gen = (*b == 0x2E ? gen_VUCOMI : gen_VCOMI); 1078} 1079 1080static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1081{ 1082 if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) { 1083 entry->op1 = X86_TYPE_None; 1084 entry->s1 = X86_SIZE_None; 1085 } 1086 switch (*b) { 1087 case 0x51: entry->gen = gen_VSQRT; break; 1088 case 0x52: entry->gen = gen_VRSQRT; break; 1089 case 0x53: entry->gen = gen_VRCP; break; 1090 } 1091} 1092 1093static void decode_0F5A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1094{ 1095 static const X86OpEntry opcodes_0F5A[4] = { 1096 X86_OP_ENTRY2(VCVTPS2PD, V,x, W,xh, vex2), /* VCVTPS2PD */ 1097 X86_OP_ENTRY2(VCVTPD2PS, V,x, W,x, vex2), /* VCVTPD2PS */ 1098 X86_OP_ENTRY3(VCVTSS2SD, V,x, H,x, W,x, vex2_rep3), /* VCVTSS2SD */ 1099 X86_OP_ENTRY3(VCVTSD2SS, V,x, H,x, W,x, vex2_rep3), /* VCVTSD2SS */ 1100 }; 1101 *entry = *decode_by_prefix(s, opcodes_0F5A); 1102} 1103 1104static void decode_0F5B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1105{ 1106 static const X86OpEntry opcodes_0F5B[4] = { 1107 X86_OP_ENTRY2(VCVTDQ2PS, V,x, W,x, vex2), 1108 X86_OP_ENTRY2(VCVTPS2DQ, V,x, W,x, vex2), 1109 X86_OP_ENTRY2(VCVTTPS2DQ, V,x, W,x, vex2), 1110 {}, 1111 }; 1112 *entry = *decode_by_prefix(s, opcodes_0F5B); 1113} 1114 1115static void decode_0FE6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1116{ 1117 static const X86OpEntry opcodes_0FE6[4] = { 1118 {}, 1119 X86_OP_ENTRY2(VCVTTPD2DQ, V,x, W,x, vex2), 1120 X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex5), 1121 X86_OP_ENTRY2(VCVTPD2DQ, V,x, W,x, vex2), 1122 }; 1123 *entry = *decode_by_prefix(s, opcodes_0FE6); 1124} 1125 1126/* 1127 * These ignore the mod bits (assume (modrm&0xc0)==0xc0), so group the 1128 * pre-decode tweak here for all MOVs from/to CR and DR. 1129 * 1130 * AMD documentation (24594.pdf) and testing of Intel 386 and 486 1131 * processors all show that the mod bits are assumed to be 1's, 1132 * regardless of actual values. 1133 */ 1134static void decode_MOV_CR_DR(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1135{ 1136 /* 1137 */ 1138 get_modrm(s, env); 1139 s->modrm |= 0xC0; 1140 1141 entry->gen = gen_MOV; 1142} 1143 1144static const X86OpEntry opcodes_0F[256] = { 1145 [0x00] = X86_OP_ENTRY1(multi0F, nop,v, nolea), /* unconverted */ 1146 [0x01] = X86_OP_ENTRY1(multi0F, nop,v, nolea), /* unconverted */ 1147 [0x02] = X86_OP_ENTRYwr(LAR, G,v, E,w, chk(prot)), 1148 [0x03] = X86_OP_ENTRYwr(LSL, G,v, E,w, chk(prot)), 1149 [0x05] = X86_OP_ENTRY0(SYSCALL, chk(o64_intel)), 1150 [0x06] = X86_OP_ENTRY0(CLTS, chk(cpl0) svm(WRITE_CR0)), 1151 [0x07] = X86_OP_ENTRY0(SYSRET, chk3(o64_intel, prot, cpl0)), 1152 1153 [0x10] = X86_OP_GROUP0(0F10), 1154 [0x11] = X86_OP_GROUP0(0F11), 1155 [0x12] = X86_OP_GROUP0(0F12), 1156 [0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex5 p_00_66), 1157 [0x14] = X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_66), 1158 [0x15] = X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_66), 1159 [0x16] = X86_OP_GROUP0(0F16), 1160 /* Incorrectly listed as Mq,Vq in the manual */ 1161 [0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_66), 1162 1163 /* 1164 * Incorrectly listed as using "d" operand type in the manual. In reality 1165 * there's no 16-bit version (like y) and it does not use REX.W (like d64). 1166 */ 1167 [0x20] = X86_OP_GROUPwr(MOV_CR_DR, R,y_d64, C,y_d64, chk(cpl0) svm(READ_CR0)), 1168 [0x21] = X86_OP_GROUPwr(MOV_CR_DR, R,y_d64, D,y_d64, chk(cpl0) svm(READ_DR0)), 1169 [0x22] = X86_OP_GROUPwr(MOV_CR_DR, C,y_d64, R,y_d64, zextT0 chk(cpl0) svm(WRITE_CR0)), 1170 [0x23] = X86_OP_GROUPwr(MOV_CR_DR, D,y_d64, R,y_d64, zextT0 chk(cpl0) svm(WRITE_DR0)), 1171 1172 [0x30] = X86_OP_ENTRY0(WRMSR, chk(cpl0)), 1173 [0x31] = X86_OP_ENTRY0(RDTSC), 1174 [0x32] = X86_OP_ENTRY0(RDMSR, chk(cpl0)), 1175 [0x33] = X86_OP_ENTRY0(RDPMC), 1176 [0x34] = X86_OP_ENTRY0(SYSENTER, chk2(i64_amd, prot_or_vm86)), 1177 [0x35] = X86_OP_ENTRY0(SYSEXIT, chk3(i64_amd, prot, cpl0)), 1178 1179 [0x40] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1180 [0x41] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1181 [0x42] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1182 [0x43] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1183 [0x44] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1184 [0x45] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1185 [0x46] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1186 [0x47] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1187 1188 [0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66), 1189 [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), /* sqrtps */ 1190 [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rsqrtps */ 1191 [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rcpps */ 1192 [0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand */ 1193 [0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn */ 1194 [0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */ 1195 [0x57] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 p_00_66), /* vxor */ 1196 1197 [0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1198 [0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1199 [0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1200 [0x63] = X86_OP_ENTRY3(PACKSSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1201 [0x64] = X86_OP_ENTRY3(PCMPGTB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1202 [0x65] = X86_OP_ENTRY3(PCMPGTW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1203 [0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1204 [0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1205 1206 [0x70] = X86_OP_GROUP0(0F70), 1207 [0x71] = X86_OP_GROUP0(group12), 1208 [0x72] = X86_OP_GROUP0(group13), 1209 [0x73] = X86_OP_GROUP0(group14), 1210 [0x74] = X86_OP_ENTRY3(PCMPEQB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1211 [0x75] = X86_OP_ENTRY3(PCMPEQW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1212 [0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1213 [0x77] = X86_OP_GROUP0(0F77), 1214 1215 [0x80] = X86_OP_ENTRYr(Jcc, J,z_f64), 1216 [0x81] = X86_OP_ENTRYr(Jcc, J,z_f64), 1217 [0x82] = X86_OP_ENTRYr(Jcc, J,z_f64), 1218 [0x83] = X86_OP_ENTRYr(Jcc, J,z_f64), 1219 [0x84] = X86_OP_ENTRYr(Jcc, J,z_f64), 1220 [0x85] = X86_OP_ENTRYr(Jcc, J,z_f64), 1221 [0x86] = X86_OP_ENTRYr(Jcc, J,z_f64), 1222 [0x87] = X86_OP_ENTRYr(Jcc, J,z_f64), 1223 1224 [0x90] = X86_OP_ENTRYw(SETcc, E,b), 1225 [0x91] = X86_OP_ENTRYw(SETcc, E,b), 1226 [0x92] = X86_OP_ENTRYw(SETcc, E,b), 1227 [0x93] = X86_OP_ENTRYw(SETcc, E,b), 1228 [0x94] = X86_OP_ENTRYw(SETcc, E,b), 1229 [0x95] = X86_OP_ENTRYw(SETcc, E,b), 1230 [0x96] = X86_OP_ENTRYw(SETcc, E,b), 1231 [0x97] = X86_OP_ENTRYw(SETcc, E,b), 1232 1233 [0xa0] = X86_OP_ENTRYr(PUSH, FS, w), 1234 [0xa1] = X86_OP_ENTRYw(POP, FS, w), 1235 [0xa2] = X86_OP_ENTRY0(CPUID), 1236 [0xa3] = X86_OP_ENTRYrr(BT, E,v, G,v, btEvGv), 1237 [0xa4] = X86_OP_ENTRY4(SHLD, E,v, 2op,v, G,v), 1238 [0xa5] = X86_OP_ENTRY3(SHLD, E,v, 2op,v, G,v), 1239 1240 [0xb0] = X86_OP_ENTRY2(CMPXCHG,E,b, G,b, lock), 1241 [0xb1] = X86_OP_ENTRY2(CMPXCHG,E,v, G,v, lock), 1242 [0xb2] = X86_OP_ENTRY3(LSS, G,v, EM,p, None, None), 1243 [0xb3] = X86_OP_ENTRY2(BTR, E,v, G,v, btEvGv), 1244 [0xb4] = X86_OP_ENTRY3(LFS, G,v, EM,p, None, None), 1245 [0xb5] = X86_OP_ENTRY3(LGS, G,v, EM,p, None, None), 1246 [0xb6] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, zextT0), /* MOVZX */ 1247 [0xb7] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, zextT0), /* MOVZX */ 1248 1249 [0xc0] = X86_OP_ENTRY2(XADD, E,b, G,b, lock), 1250 [0xc1] = X86_OP_ENTRY2(XADD, E,v, G,v, lock), 1251 [0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1252 [0xc3] = X86_OP_ENTRY3(MOV, EM,y,G,y, None,None, cpuid(SSE2)), /* MOVNTI */ 1253 [0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66), 1254 [0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66), 1255 [0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66), 1256 [0xc7] = X86_OP_GROUP0(group9), 1257 1258 [0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2), 1259 [0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1260 [0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1261 [0xd3] = X86_OP_ENTRY3(PSRLQ_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1262 [0xd4] = X86_OP_ENTRY3(PADDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1263 [0xd5] = X86_OP_ENTRY3(PMULLW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1264 [0xd6] = X86_OP_GROUP0(0FD6), 1265 [0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256 p_00_66), 1266 1267 [0xe0] = X86_OP_ENTRY3(PAVGB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1268 [0xe1] = X86_OP_ENTRY3(PSRAW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1269 [0xe2] = X86_OP_ENTRY3(PSRAD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1270 [0xe3] = X86_OP_ENTRY3(PAVGW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1271 [0xe4] = X86_OP_ENTRY3(PMULHUW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1272 [0xe5] = X86_OP_ENTRY3(PMULHW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1273 [0xe6] = X86_OP_GROUP0(0FE6), 1274 [0xe7] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx p_00_66), /* MOVNTQ/MOVNTDQ */ 1275 1276 [0xf0] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex4_unal cpuid(SSE3) p_f2), /* LDDQU */ 1277 [0xf1] = X86_OP_ENTRY3(PSLLW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1278 [0xf2] = X86_OP_ENTRY3(PSLLD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1279 [0xf3] = X86_OP_ENTRY3(PSLLQ_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1280 [0xf4] = X86_OP_ENTRY3(PMULUDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1281 [0xf5] = X86_OP_ENTRY3(PMADDWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1282 [0xf6] = X86_OP_ENTRY3(PSADBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1283 [0xf7] = X86_OP_ENTRY3(MASKMOV, None,None, V,dq, U,dq, vex4_unal avx2_256 mmx p_00_66), 1284 1285 [0x08] = X86_OP_ENTRY0(NOP, svm(INVD)), 1286 [0x09] = X86_OP_ENTRY0(NOP, svm(WBINVD)), 1287 [0x0b] = X86_OP_ENTRY0(UD), /* UD2 */ 1288 [0x0d] = X86_OP_ENTRY1(NOP, M,v), /* 3DNow! prefetch */ 1289 [0x0e] = X86_OP_ENTRY0(EMMS, cpuid(3DNOW)), /* femms */ 1290 /* 1291 * 3DNow!'s opcode byte comes *after* modrm and displacements, making it 1292 * more like an Ib operand. Dispatch to the right helper in a single gen_* 1293 * function. 1294 */ 1295 [0x0f] = X86_OP_ENTRY3(3dnow, P,q, Q,q, I,b, cpuid(3DNOW)), 1296 1297 [0x18] = X86_OP_ENTRY1(NOP, nop,v), /* prefetch/reserved NOP */ 1298 [0x19] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ 1299 [0x1a] = X86_OP_ENTRY1(multi0F, nop,v, nolea), /* unconverted MPX */ 1300 [0x1b] = X86_OP_ENTRY1(multi0F, nop,v, nolea), /* unconverted MPX */ 1301 [0x1c] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ 1302 [0x1d] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ 1303 [0x1e] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ 1304 [0x1f] = X86_OP_ENTRY1(NOP, nop,v), /* NOP/reserved NOP */ 1305 1306 [0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */ 1307 [0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */ 1308 [0x2A] = X86_OP_GROUP0(0F2A), 1309 [0x2B] = X86_OP_GROUP0(0F2B), 1310 [0x2C] = X86_OP_GROUP0(0F2C), 1311 [0x2D] = X86_OP_GROUP0(0F2D), 1312 [0x2E] = X86_OP_GROUP3(VxCOMISx, None,None, V,x, W,x, vex3 p_00_66), /* VUCOMISS/SD */ 1313 [0x2F] = X86_OP_GROUP3(VxCOMISx, None,None, V,x, W,x, vex3 p_00_66), /* VCOMISS/SD */ 1314 1315 [0x38] = X86_OP_GROUP0(0F38), 1316 [0x3a] = X86_OP_GROUP0(0F3A), 1317 1318 [0x48] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1319 [0x49] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1320 [0x4a] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1321 [0x4b] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1322 [0x4c] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1323 [0x4d] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1324 [0x4e] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1325 [0x4f] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1326 1327 [0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1328 [0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1329 [0x5a] = X86_OP_GROUP0(0F5A), 1330 [0x5b] = X86_OP_GROUP0(0F5B), 1331 [0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1332 [0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1333 [0x5e] = X86_OP_ENTRY3(VDIV, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1334 [0x5f] = X86_OP_ENTRY3(VMAX, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1335 1336 [0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1337 [0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1338 [0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1339 [0x6b] = X86_OP_ENTRY3(PACKSSDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1340 [0x6c] = X86_OP_ENTRY3(PUNPCKLQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256), 1341 [0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256), 1342 [0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */ 1343 [0x6f] = X86_OP_GROUP0(0F6F), 1344 1345 [0x78] = X86_OP_GROUP0(0F78), 1346 [0x79] = X86_OP_GROUP2(0F79, V,x, U,x, cpuid(SSE4A)), 1347 [0x7c] = X86_OP_ENTRY3(VHADD, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2), 1348 [0x7d] = X86_OP_ENTRY3(VHSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2), 1349 [0x7e] = X86_OP_GROUP0(0F7E), 1350 [0x7f] = X86_OP_GROUP0(0F7F), 1351 1352 [0x88] = X86_OP_ENTRYr(Jcc, J,z_f64), 1353 [0x89] = X86_OP_ENTRYr(Jcc, J,z_f64), 1354 [0x8a] = X86_OP_ENTRYr(Jcc, J,z_f64), 1355 [0x8b] = X86_OP_ENTRYr(Jcc, J,z_f64), 1356 [0x8c] = X86_OP_ENTRYr(Jcc, J,z_f64), 1357 [0x8d] = X86_OP_ENTRYr(Jcc, J,z_f64), 1358 [0x8e] = X86_OP_ENTRYr(Jcc, J,z_f64), 1359 [0x8f] = X86_OP_ENTRYr(Jcc, J,z_f64), 1360 1361 [0x98] = X86_OP_ENTRYw(SETcc, E,b), 1362 [0x99] = X86_OP_ENTRYw(SETcc, E,b), 1363 [0x9a] = X86_OP_ENTRYw(SETcc, E,b), 1364 [0x9b] = X86_OP_ENTRYw(SETcc, E,b), 1365 [0x9c] = X86_OP_ENTRYw(SETcc, E,b), 1366 [0x9d] = X86_OP_ENTRYw(SETcc, E,b), 1367 [0x9e] = X86_OP_ENTRYw(SETcc, E,b), 1368 [0x9f] = X86_OP_ENTRYw(SETcc, E,b), 1369 1370 [0xa8] = X86_OP_ENTRYr(PUSH, GS, w), 1371 [0xa9] = X86_OP_ENTRYw(POP, GS, w), 1372 [0xaa] = X86_OP_ENTRY0(RSM, chk(smm) svm(RSM)), 1373 [0xab] = X86_OP_ENTRY2(BTS, E,v, G,v, btEvGv), 1374 [0xac] = X86_OP_ENTRY4(SHRD, E,v, 2op,v, G,v), 1375 [0xad] = X86_OP_ENTRY3(SHRD, E,v, 2op,v, G,v), 1376 [0xae] = X86_OP_GROUP0(group15), 1377 /* 1378 * It's slightly more efficient to put Ev operand in T0 and allow gen_IMUL3 1379 * to assume sextT0. Multiplication is commutative anyway. 1380 */ 1381 [0xaf] = X86_OP_ENTRY3(IMUL3, G,v, E,v, 2op,v, sextT0), 1382 1383 [0xb8] = X86_OP_GROUP0(0FB8), 1384 /* decoded as modrm, which is visible as a difference between page fault and #UD */ 1385 [0xb9] = X86_OP_ENTRYr(UD, nop,v), /* UD1 */ 1386 [0xba] = X86_OP_GROUP2(group8, E,v, I,b), 1387 [0xbb] = X86_OP_ENTRY2(BTC, E,v, G,v, btEvGv), 1388 [0xbc] = X86_OP_GROUP0(0FBC), 1389 [0xbd] = X86_OP_GROUP0(0FBD), 1390 [0xbe] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, sextT0), /* MOVSX */ 1391 [0xbf] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, sextT0), /* MOVSX */ 1392 1393 [0xc8] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1394 [0xc9] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1395 [0xca] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1396 [0xcb] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1397 [0xcc] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1398 [0xcd] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1399 [0xce] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1400 [0xcf] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1401 1402 /* Incorrectly missing from 2-17 */ 1403 [0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1404 [0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1405 [0xda] = X86_OP_ENTRY3(PMINUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1406 [0xdb] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1407 [0xdc] = X86_OP_ENTRY3(PADDUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1408 [0xdd] = X86_OP_ENTRY3(PADDUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1409 [0xde] = X86_OP_ENTRY3(PMAXUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1410 [0xdf] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1411 1412 [0xe8] = X86_OP_ENTRY3(PSUBSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1413 [0xe9] = X86_OP_ENTRY3(PSUBSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1414 [0xea] = X86_OP_ENTRY3(PMINSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1415 [0xeb] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1416 [0xec] = X86_OP_ENTRY3(PADDSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1417 [0xed] = X86_OP_ENTRY3(PADDSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1418 [0xee] = X86_OP_ENTRY3(PMAXSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1419 [0xef] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1420 1421 [0xf8] = X86_OP_ENTRY3(PSUBB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1422 [0xf9] = X86_OP_ENTRY3(PSUBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1423 [0xfa] = X86_OP_ENTRY3(PSUBD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1424 [0xfb] = X86_OP_ENTRY3(PSUBQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1425 [0xfc] = X86_OP_ENTRY3(PADDB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1426 [0xfd] = X86_OP_ENTRY3(PADDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1427 [0xfe] = X86_OP_ENTRY3(PADDD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1428 [0xff] = X86_OP_ENTRYr(UD, nop,v), /* UD0 */ 1429}; 1430 1431static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1432{ 1433 *entry = opcodes_0F[*b]; 1434} 1435 1436static void decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1437{ 1438 *b = x86_ldub_code(env, s); 1439 do_decode_0F(s, env, entry, b); 1440} 1441 1442static void decode_63(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1443{ 1444 static const X86OpEntry arpl = X86_OP_ENTRY2(ARPL, E,w, G,w, chk(prot)); 1445 static const X86OpEntry mov = X86_OP_ENTRY3(MOV, G,v, E,v, None, None); 1446 static const X86OpEntry movsxd = X86_OP_ENTRY3(MOV, G,v, E,d, None, None, sextT0); 1447 if (!CODE64(s)) { 1448 *entry = arpl; 1449 } else if (REX_W(s)) { 1450 *entry = movsxd; 1451 } else { 1452 *entry = mov; 1453 } 1454} 1455 1456static void decode_group1(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1457{ 1458 static const X86GenFunc group1_gen[8] = { 1459 gen_ADD, gen_OR, gen_ADC, gen_SBB, gen_AND, gen_SUB, gen_XOR, gen_SUB, 1460 }; 1461 int op = (get_modrm(s, env) >> 3) & 7; 1462 entry->gen = group1_gen[op]; 1463 1464 if (op == 7) { 1465 /* prevent writeback for CMP */ 1466 entry->op1 = entry->op0; 1467 entry->op0 = X86_TYPE_None; 1468 entry->s0 = X86_SIZE_None; 1469 } else { 1470 entry->special = X86_SPECIAL_HasLock; 1471 } 1472} 1473 1474static void decode_group1A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1475{ 1476 int op = (get_modrm(s, env) >> 3) & 7; 1477 if (op != 0) { 1478 /* could be XOP prefix too */ 1479 *entry = UNKNOWN_OPCODE; 1480 } else { 1481 entry->gen = gen_POP; 1482 /* The address must use the value of ESP after the pop. */ 1483 s->popl_esp_hack = 1 << mo_pushpop(s, s->dflag); 1484 } 1485} 1486 1487static void decode_group2(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1488{ 1489 static const X86GenFunc group2_gen[8] = { 1490 gen_ROL, gen_ROR, gen_RCL, gen_RCR, 1491 gen_SHL, gen_SHR, gen_SHL /* SAL, undocumented */, gen_SAR, 1492 }; 1493 int op = (get_modrm(s, env) >> 3) & 7; 1494 entry->gen = group2_gen[op]; 1495 if (op == 7) { 1496 entry->special = X86_SPECIAL_SExtT0; 1497 } else { 1498 entry->special = X86_SPECIAL_ZExtT0; 1499 } 1500} 1501 1502static void decode_group3(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1503{ 1504 static const X86OpEntry opcodes_grp3[16] = { 1505 /* 0xf6 */ 1506 [0x00] = X86_OP_ENTRYrr(AND, E,b, I,b), 1507 [0x02] = X86_OP_ENTRY1(NOT, E,b, lock), 1508 [0x03] = X86_OP_ENTRY1(NEG, E,b, lock), 1509 [0x04] = X86_OP_ENTRYrr(MUL, E,b, 0,b, zextT0), 1510 [0x05] = X86_OP_ENTRYrr(IMUL,E,b, 0,b, sextT0), 1511 [0x06] = X86_OP_ENTRYr(DIV, E,b), 1512 [0x07] = X86_OP_ENTRYr(IDIV, E,b), 1513 1514 /* 0xf7 */ 1515 [0x08] = X86_OP_ENTRYrr(AND, E,v, I,z), 1516 [0x0a] = X86_OP_ENTRY1(NOT, E,v, lock), 1517 [0x0b] = X86_OP_ENTRY1(NEG, E,v, lock), 1518 [0x0c] = X86_OP_ENTRYrr(MUL, E,v, 0,v, zextT0), 1519 [0x0d] = X86_OP_ENTRYrr(IMUL,E,v, 0,v, sextT0), 1520 [0x0e] = X86_OP_ENTRYr(DIV, E,v), 1521 [0x0f] = X86_OP_ENTRYr(IDIV, E,v), 1522 }; 1523 1524 int w = (*b & 1); 1525 int reg = (get_modrm(s, env) >> 3) & 7; 1526 1527 *entry = opcodes_grp3[(w << 3) | reg]; 1528} 1529 1530static void decode_group4_5(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1531{ 1532 static const X86OpEntry opcodes_grp4_5[16] = { 1533 /* 0xfe */ 1534 [0x00] = X86_OP_ENTRY1(INC, E,b, lock), 1535 [0x01] = X86_OP_ENTRY1(DEC, E,b, lock), 1536 1537 /* 0xff */ 1538 [0x08] = X86_OP_ENTRY1(INC, E,v, lock), 1539 [0x09] = X86_OP_ENTRY1(DEC, E,v, lock), 1540 [0x0a] = X86_OP_ENTRYr(CALL_m, E,f64, zextT0), 1541 [0x0b] = X86_OP_ENTRYr(CALLF_m, M,p), 1542 [0x0c] = X86_OP_ENTRYr(JMP_m, E,f64, zextT0), 1543 [0x0d] = X86_OP_ENTRYr(JMPF_m, M,p), 1544 [0x0e] = X86_OP_ENTRYr(PUSH, E,f64), 1545 }; 1546 1547 int w = (*b & 1); 1548 int reg = (get_modrm(s, env) >> 3) & 7; 1549 1550 *entry = opcodes_grp4_5[(w << 3) | reg]; 1551} 1552 1553 1554static void decode_group11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1555{ 1556 int op = (get_modrm(s, env) >> 3) & 7; 1557 if (op != 0) { 1558 *entry = UNKNOWN_OPCODE; 1559 } else { 1560 entry->gen = gen_MOV; 1561 } 1562} 1563 1564static void decode_90(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1565{ 1566 static X86OpEntry pause = X86_OP_ENTRY0(PAUSE, svm(PAUSE)); 1567 static X86OpEntry nop = X86_OP_ENTRY0(NOP); 1568 static X86OpEntry xchg_ax = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v); 1569 1570 if (REX_B(s)) { 1571 *entry = xchg_ax; 1572 } else { 1573 *entry = (s->prefix & PREFIX_REPZ) ? pause : nop; 1574 } 1575} 1576 1577static const X86OpEntry opcodes_root[256] = { 1578 [0x00] = X86_OP_ENTRY2(ADD, E,b, G,b, lock), 1579 [0x01] = X86_OP_ENTRY2(ADD, E,v, G,v, lock), 1580 [0x02] = X86_OP_ENTRY2(ADD, G,b, E,b, lock), 1581 [0x03] = X86_OP_ENTRY2(ADD, G,v, E,v, lock), 1582 [0x04] = X86_OP_ENTRY2(ADD, 0,b, I,b, lock), /* AL, Ib */ 1583 [0x05] = X86_OP_ENTRY2(ADD, 0,v, I,z, lock), /* rAX, Iz */ 1584 [0x06] = X86_OP_ENTRYr(PUSH, ES, w, chk(i64)), 1585 [0x07] = X86_OP_ENTRYw(POP, ES, w, chk(i64)), 1586 1587 [0x10] = X86_OP_ENTRY2(ADC, E,b, G,b, lock), 1588 [0x11] = X86_OP_ENTRY2(ADC, E,v, G,v, lock), 1589 [0x12] = X86_OP_ENTRY2(ADC, G,b, E,b, lock), 1590 [0x13] = X86_OP_ENTRY2(ADC, G,v, E,v, lock), 1591 [0x14] = X86_OP_ENTRY2(ADC, 0,b, I,b, lock), /* AL, Ib */ 1592 [0x15] = X86_OP_ENTRY2(ADC, 0,v, I,z, lock), /* rAX, Iz */ 1593 [0x16] = X86_OP_ENTRYr(PUSH, SS, w, chk(i64)), 1594 [0x17] = X86_OP_ENTRYw(POP, SS, w, chk(i64)), 1595 1596 [0x20] = X86_OP_ENTRY2(AND, E,b, G,b, lock), 1597 [0x21] = X86_OP_ENTRY2(AND, E,v, G,v, lock), 1598 [0x22] = X86_OP_ENTRY2(AND, G,b, E,b, lock), 1599 [0x23] = X86_OP_ENTRY2(AND, G,v, E,v, lock), 1600 [0x24] = X86_OP_ENTRY2(AND, 0,b, I,b, lock), /* AL, Ib */ 1601 [0x25] = X86_OP_ENTRY2(AND, 0,v, I,z, lock), /* rAX, Iz */ 1602 [0x26] = {}, 1603 [0x27] = X86_OP_ENTRY0(DAA, chk(i64)), 1604 1605 [0x30] = X86_OP_ENTRY2(XOR, E,b, G,b, lock), 1606 [0x31] = X86_OP_ENTRY2(XOR, E,v, G,v, lock), 1607 [0x32] = X86_OP_ENTRY2(XOR, G,b, E,b, lock), 1608 [0x33] = X86_OP_ENTRY2(XOR, G,v, E,v, lock), 1609 [0x34] = X86_OP_ENTRY2(XOR, 0,b, I,b, lock), /* AL, Ib */ 1610 [0x35] = X86_OP_ENTRY2(XOR, 0,v, I,z, lock), /* rAX, Iz */ 1611 [0x36] = {}, 1612 [0x37] = X86_OP_ENTRY0(AAA, chk(i64)), 1613 1614 [0x40] = X86_OP_ENTRY1(INC, 0,v, chk(i64)), 1615 [0x41] = X86_OP_ENTRY1(INC, 1,v, chk(i64)), 1616 [0x42] = X86_OP_ENTRY1(INC, 2,v, chk(i64)), 1617 [0x43] = X86_OP_ENTRY1(INC, 3,v, chk(i64)), 1618 [0x44] = X86_OP_ENTRY1(INC, 4,v, chk(i64)), 1619 [0x45] = X86_OP_ENTRY1(INC, 5,v, chk(i64)), 1620 [0x46] = X86_OP_ENTRY1(INC, 6,v, chk(i64)), 1621 [0x47] = X86_OP_ENTRY1(INC, 7,v, chk(i64)), 1622 1623 [0x50] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1624 [0x51] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1625 [0x52] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1626 [0x53] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1627 [0x54] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1628 [0x55] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1629 [0x56] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1630 [0x57] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1631 1632 [0x60] = X86_OP_ENTRY0(PUSHA, chk(i64)), 1633 [0x61] = X86_OP_ENTRY0(POPA, chk(i64)), 1634 [0x62] = X86_OP_ENTRYrr(BOUND, G,v, M,a, chk(i64)), 1635 [0x63] = X86_OP_GROUP0(63), 1636 [0x64] = {}, 1637 [0x65] = {}, 1638 [0x66] = {}, 1639 [0x67] = {}, 1640 1641 [0x70] = X86_OP_ENTRYr(Jcc, J,b), 1642 [0x71] = X86_OP_ENTRYr(Jcc, J,b), 1643 [0x72] = X86_OP_ENTRYr(Jcc, J,b), 1644 [0x73] = X86_OP_ENTRYr(Jcc, J,b), 1645 [0x74] = X86_OP_ENTRYr(Jcc, J,b), 1646 [0x75] = X86_OP_ENTRYr(Jcc, J,b), 1647 [0x76] = X86_OP_ENTRYr(Jcc, J,b), 1648 [0x77] = X86_OP_ENTRYr(Jcc, J,b), 1649 1650 [0x80] = X86_OP_GROUP2(group1, E,b, I,b), 1651 [0x81] = X86_OP_GROUP2(group1, E,v, I,z), 1652 [0x82] = X86_OP_GROUP2(group1, E,b, I,b, chk(i64)), 1653 [0x83] = X86_OP_GROUP2(group1, E,v, I,b), 1654 [0x84] = X86_OP_ENTRYrr(AND, E,b, G,b), 1655 [0x85] = X86_OP_ENTRYrr(AND, E,v, G,v), 1656 [0x86] = X86_OP_ENTRY2(XCHG, E,b, G,b, xchg), 1657 [0x87] = X86_OP_ENTRY2(XCHG, E,v, G,v, xchg), 1658 1659 [0x90] = X86_OP_GROUP0(90), 1660 [0x91] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1661 [0x92] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1662 [0x93] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1663 [0x94] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1664 [0x95] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1665 [0x96] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1666 [0x97] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1667 1668 [0xA0] = X86_OP_ENTRY3(MOV, 0,b, O,b, None, None), /* AL, Ob */ 1669 [0xA1] = X86_OP_ENTRY3(MOV, 0,v, O,v, None, None), /* rAX, Ov */ 1670 [0xA2] = X86_OP_ENTRY3(MOV, O,b, 0,b, None, None), /* Ob, AL */ 1671 [0xA3] = X86_OP_ENTRY3(MOV, O,v, 0,v, None, None), /* Ov, rAX */ 1672 [0xA4] = X86_OP_ENTRYrr(MOVS, Y,b, X,b), 1673 [0xA5] = X86_OP_ENTRYrr(MOVS, Y,v, X,v), 1674 [0xA6] = X86_OP_ENTRYrr(CMPS, Y,b, X,b), 1675 [0xA7] = X86_OP_ENTRYrr(CMPS, Y,v, X,v), 1676 1677 [0xB0] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1678 [0xB1] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1679 [0xB2] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1680 [0xB3] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1681 [0xB4] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1682 [0xB5] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1683 [0xB6] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1684 [0xB7] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1685 1686 [0xC0] = X86_OP_GROUP2(group2, E,b, I,b), 1687 [0xC1] = X86_OP_GROUP2(group2, E,v, I,b), 1688 [0xC2] = X86_OP_ENTRYr(RET, I,w), 1689 [0xC3] = X86_OP_ENTRY0(RET), 1690 [0xC4] = X86_OP_ENTRY3(LES, G,z, EM,p, None, None, chk(i64)), 1691 [0xC5] = X86_OP_ENTRY3(LDS, G,z, EM,p, None, None, chk(i64)), 1692 [0xC6] = X86_OP_GROUP3(group11, E,b, I,b, None, None), /* reg=000b */ 1693 [0xC7] = X86_OP_GROUP3(group11, E,v, I,z, None, None), /* reg=000b */ 1694 1695 [0xD0] = X86_OP_GROUP1(group2, E,b), 1696 [0xD1] = X86_OP_GROUP1(group2, E,v), 1697 [0xD2] = X86_OP_GROUP2(group2, E,b, 1,b), /* CL */ 1698 [0xD3] = X86_OP_GROUP2(group2, E,v, 1,b), /* CL */ 1699 [0xD4] = X86_OP_ENTRY2(AAM, 0,w, I,b), 1700 [0xD5] = X86_OP_ENTRY2(AAD, 0,w, I,b), 1701 [0xD6] = X86_OP_ENTRYw(SALC, 0,b), 1702 [0xD7] = X86_OP_ENTRY1(XLAT, 0,b, zextT0), /* AL read/written */ 1703 1704 [0xE0] = X86_OP_ENTRYr(LOOPNE, J,b), /* implicit: CX with aflag size */ 1705 [0xE1] = X86_OP_ENTRYr(LOOPE, J,b), /* implicit: CX with aflag size */ 1706 [0xE2] = X86_OP_ENTRYr(LOOP, J,b), /* implicit: CX with aflag size */ 1707 [0xE3] = X86_OP_ENTRYr(JCXZ, J,b), /* implicit: CX with aflag size */ 1708 [0xE4] = X86_OP_ENTRYwr(IN, 0,b, I_unsigned,b), /* AL */ 1709 [0xE5] = X86_OP_ENTRYwr(IN, 0,z, I_unsigned,b), /* AX/EAX */ 1710 [0xE6] = X86_OP_ENTRYrr(OUT, 0,b, I_unsigned,b), /* AL */ 1711 [0xE7] = X86_OP_ENTRYrr(OUT, 0,z, I_unsigned,b), /* AX/EAX */ 1712 1713 [0xF1] = X86_OP_ENTRY0(INT1, svm(ICEBP)), 1714 [0xF4] = X86_OP_ENTRY0(HLT, chk(cpl0) svm(HLT)), 1715 [0xF5] = X86_OP_ENTRY0(CMC), 1716 [0xF6] = X86_OP_GROUP1(group3, E,b), 1717 [0xF7] = X86_OP_GROUP1(group3, E,v), 1718 1719 [0x08] = X86_OP_ENTRY2(OR, E,b, G,b, lock), 1720 [0x09] = X86_OP_ENTRY2(OR, E,v, G,v, lock), 1721 [0x0A] = X86_OP_ENTRY2(OR, G,b, E,b, lock), 1722 [0x0B] = X86_OP_ENTRY2(OR, G,v, E,v, lock), 1723 [0x0C] = X86_OP_ENTRY2(OR, 0,b, I,b, lock), /* AL, Ib */ 1724 [0x0D] = X86_OP_ENTRY2(OR, 0,v, I,z, lock), /* rAX, Iz */ 1725 [0x0E] = X86_OP_ENTRYr(PUSH, CS, w, chk(i64)), 1726 [0x0F] = X86_OP_GROUP0(0F), 1727 1728 [0x18] = X86_OP_ENTRY2(SBB, E,b, G,b, lock), 1729 [0x19] = X86_OP_ENTRY2(SBB, E,v, G,v, lock), 1730 [0x1A] = X86_OP_ENTRY2(SBB, G,b, E,b, lock), 1731 [0x1B] = X86_OP_ENTRY2(SBB, G,v, E,v, lock), 1732 [0x1C] = X86_OP_ENTRY2(SBB, 0,b, I,b, lock), /* AL, Ib */ 1733 [0x1D] = X86_OP_ENTRY2(SBB, 0,v, I,z, lock), /* rAX, Iz */ 1734 [0x1E] = X86_OP_ENTRYr(PUSH, DS, w, chk(i64)), 1735 [0x1F] = X86_OP_ENTRYw(POP, DS, w, chk(i64)), 1736 1737 [0x28] = X86_OP_ENTRY2(SUB, E,b, G,b, lock), 1738 [0x29] = X86_OP_ENTRY2(SUB, E,v, G,v, lock), 1739 [0x2A] = X86_OP_ENTRY2(SUB, G,b, E,b, lock), 1740 [0x2B] = X86_OP_ENTRY2(SUB, G,v, E,v, lock), 1741 [0x2C] = X86_OP_ENTRY2(SUB, 0,b, I,b, lock), /* AL, Ib */ 1742 [0x2D] = X86_OP_ENTRY2(SUB, 0,v, I,z, lock), /* rAX, Iz */ 1743 [0x2E] = {}, 1744 [0x2F] = X86_OP_ENTRY0(DAS, chk(i64)), 1745 1746 [0x38] = X86_OP_ENTRYrr(SUB, E,b, G,b), 1747 [0x39] = X86_OP_ENTRYrr(SUB, E,v, G,v), 1748 [0x3A] = X86_OP_ENTRYrr(SUB, G,b, E,b), 1749 [0x3B] = X86_OP_ENTRYrr(SUB, G,v, E,v), 1750 [0x3C] = X86_OP_ENTRYrr(SUB, 0,b, I,b), /* AL, Ib */ 1751 [0x3D] = X86_OP_ENTRYrr(SUB, 0,v, I,z), /* rAX, Iz */ 1752 [0x3E] = {}, 1753 [0x3F] = X86_OP_ENTRY0(AAS, chk(i64)), 1754 1755 [0x48] = X86_OP_ENTRY1(DEC, 0,v, chk(i64)), 1756 [0x49] = X86_OP_ENTRY1(DEC, 1,v, chk(i64)), 1757 [0x4A] = X86_OP_ENTRY1(DEC, 2,v, chk(i64)), 1758 [0x4B] = X86_OP_ENTRY1(DEC, 3,v, chk(i64)), 1759 [0x4C] = X86_OP_ENTRY1(DEC, 4,v, chk(i64)), 1760 [0x4D] = X86_OP_ENTRY1(DEC, 5,v, chk(i64)), 1761 [0x4E] = X86_OP_ENTRY1(DEC, 6,v, chk(i64)), 1762 [0x4F] = X86_OP_ENTRY1(DEC, 7,v, chk(i64)), 1763 1764 [0x58] = X86_OP_ENTRYw(POP, LoBits,d64), 1765 [0x59] = X86_OP_ENTRYw(POP, LoBits,d64), 1766 [0x5A] = X86_OP_ENTRYw(POP, LoBits,d64), 1767 [0x5B] = X86_OP_ENTRYw(POP, LoBits,d64), 1768 [0x5C] = X86_OP_ENTRYw(POP, LoBits,d64), 1769 [0x5D] = X86_OP_ENTRYw(POP, LoBits,d64), 1770 [0x5E] = X86_OP_ENTRYw(POP, LoBits,d64), 1771 [0x5F] = X86_OP_ENTRYw(POP, LoBits,d64), 1772 1773 [0x68] = X86_OP_ENTRYr(PUSH, I,z), 1774 [0x69] = X86_OP_ENTRY3(IMUL3, G,v, E,v, I,z, sextT0), 1775 [0x6A] = X86_OP_ENTRYr(PUSH, I,b), 1776 [0x6B] = X86_OP_ENTRY3(IMUL3, G,v, E,v, I,b, sextT0), 1777 [0x6C] = X86_OP_ENTRYrr(INS, Y,b, 2,w), /* DX */ 1778 [0x6D] = X86_OP_ENTRYrr(INS, Y,z, 2,w), /* DX */ 1779 [0x6E] = X86_OP_ENTRYrr(OUTS, X,b, 2,w), /* DX */ 1780 [0x6F] = X86_OP_ENTRYrr(OUTS, X,z, 2,w), /* DX */ 1781 1782 [0x78] = X86_OP_ENTRYr(Jcc, J,b), 1783 [0x79] = X86_OP_ENTRYr(Jcc, J,b), 1784 [0x7A] = X86_OP_ENTRYr(Jcc, J,b), 1785 [0x7B] = X86_OP_ENTRYr(Jcc, J,b), 1786 [0x7C] = X86_OP_ENTRYr(Jcc, J,b), 1787 [0x7D] = X86_OP_ENTRYr(Jcc, J,b), 1788 [0x7E] = X86_OP_ENTRYr(Jcc, J,b), 1789 [0x7F] = X86_OP_ENTRYr(Jcc, J,b), 1790 1791 [0x88] = X86_OP_ENTRYwr(MOV, E,b, G,b), 1792 [0x89] = X86_OP_ENTRYwr(MOV, E,v, G,v), 1793 [0x8A] = X86_OP_ENTRYwr(MOV, G,b, E,b), 1794 [0x8B] = X86_OP_ENTRYwr(MOV, G,v, E,v), 1795 /* Missing in Table A-2: memory destination is always 16-bit. */ 1796 [0x8C] = X86_OP_ENTRYwr(MOV, E,v, S,w, op0_Mw), 1797 [0x8D] = X86_OP_ENTRYwr(LEA, G,v, M,v, nolea), 1798 [0x8E] = X86_OP_ENTRYwr(MOV, S,w, E,w), 1799 [0x8F] = X86_OP_GROUPw(group1A, E,d64), 1800 1801 [0x98] = X86_OP_ENTRY1(CBW, 0,v), /* rAX */ 1802 [0x99] = X86_OP_ENTRYwr(CWD, 2,v, 0,v), /* rDX, rAX */ 1803 [0x9A] = X86_OP_ENTRYrr(CALLF, I_unsigned,p, I_unsigned,w, chk(i64)), 1804 [0x9B] = X86_OP_ENTRY0(WAIT), 1805 [0x9C] = X86_OP_ENTRY0(PUSHF, chk(vm86_iopl) svm(PUSHF)), 1806 [0x9D] = X86_OP_ENTRY0(POPF, chk(vm86_iopl) svm(POPF)), 1807 [0x9E] = X86_OP_ENTRY0(SAHF), 1808 [0x9F] = X86_OP_ENTRY0(LAHF), 1809 1810 [0xA8] = X86_OP_ENTRYrr(AND, 0,b, I,b), /* AL, Ib */ 1811 [0xA9] = X86_OP_ENTRYrr(AND, 0,v, I,z), /* rAX, Iz */ 1812 [0xAA] = X86_OP_ENTRYwr(STOS, Y,b, 0,b), 1813 [0xAB] = X86_OP_ENTRYwr(STOS, Y,v, 0,v), 1814 /* Manual writeback because REP LODS (!) has to write EAX/RAX after every LODS. */ 1815 [0xAC] = X86_OP_ENTRYr(LODS, X,b), 1816 [0xAD] = X86_OP_ENTRYr(LODS, X,v), 1817 [0xAE] = X86_OP_ENTRYrr(SCAS, 0,b, Y,b), 1818 [0xAF] = X86_OP_ENTRYrr(SCAS, 0,v, Y,v), 1819 1820 [0xB8] = X86_OP_ENTRYwr(MOV, LoBits,v, I,v), 1821 [0xB9] = X86_OP_ENTRYwr(MOV, LoBits,v, I,v), 1822 [0xBA] = X86_OP_ENTRYwr(MOV, LoBits,v, I,v), 1823 [0xBB] = X86_OP_ENTRYwr(MOV, LoBits,v, I,v), 1824 [0xBC] = X86_OP_ENTRYwr(MOV, LoBits,v, I,v), 1825 [0xBD] = X86_OP_ENTRYwr(MOV, LoBits,v, I,v), 1826 [0xBE] = X86_OP_ENTRYwr(MOV, LoBits,v, I,v), 1827 [0xBF] = X86_OP_ENTRYwr(MOV, LoBits,v, I,v), 1828 1829 [0xC8] = X86_OP_ENTRYrr(ENTER, I,w, I,b), 1830 [0xC9] = X86_OP_ENTRY1(LEAVE, A,d64), 1831 [0xCA] = X86_OP_ENTRYr(RETF, I,w), 1832 [0xCB] = X86_OP_ENTRY0(RETF), 1833 [0xCC] = X86_OP_ENTRY0(INT3), 1834 [0xCD] = X86_OP_ENTRYr(INT, I,b, chk(vm86_iopl)), 1835 [0xCE] = X86_OP_ENTRY0(INTO), 1836 [0xCF] = X86_OP_ENTRY0(IRET, chk(vm86_iopl) svm(IRET)), 1837 1838 /* 1839 * x87 is nolea because it needs the address without segment base, 1840 * in order to store it in fdp. 1841 */ 1842 [0xD8] = X86_OP_ENTRY1(x87, nop,v, nolea), 1843 [0xD9] = X86_OP_ENTRY1(x87, nop,v, nolea), 1844 [0xDA] = X86_OP_ENTRY1(x87, nop,v, nolea), 1845 [0xDB] = X86_OP_ENTRY1(x87, nop,v, nolea), 1846 [0xDC] = X86_OP_ENTRY1(x87, nop,v, nolea), 1847 [0xDD] = X86_OP_ENTRY1(x87, nop,v, nolea), 1848 [0xDE] = X86_OP_ENTRY1(x87, nop,v, nolea), 1849 [0xDF] = X86_OP_ENTRY1(x87, nop,v, nolea), 1850 1851 [0xE8] = X86_OP_ENTRYr(CALL, J,z_f64), 1852 [0xE9] = X86_OP_ENTRYr(JMP, J,z_f64), 1853 [0xEA] = X86_OP_ENTRYrr(JMPF, I_unsigned,p, I_unsigned,w, chk(i64)), 1854 [0xEB] = X86_OP_ENTRYr(JMP, J,b), 1855 [0xEC] = X86_OP_ENTRYwr(IN, 0,b, 2,w), /* AL, DX */ 1856 [0xED] = X86_OP_ENTRYwr(IN, 0,z, 2,w), /* AX/EAX, DX */ 1857 [0xEE] = X86_OP_ENTRYrr(OUT, 0,b, 2,w), /* DX, AL */ 1858 [0xEF] = X86_OP_ENTRYrr(OUT, 0,z, 2,w), /* DX, AX/EAX */ 1859 1860 [0xF8] = X86_OP_ENTRY0(CLC), 1861 [0xF9] = X86_OP_ENTRY0(STC), 1862 [0xFA] = X86_OP_ENTRY0(CLI, chk(iopl)), 1863 [0xFB] = X86_OP_ENTRY0(STI, chk(iopl)), 1864 [0xFC] = X86_OP_ENTRY0(CLD), 1865 [0xFD] = X86_OP_ENTRY0(STD), 1866 [0xFE] = X86_OP_GROUP1(group4_5, E,b), 1867 [0xFF] = X86_OP_GROUP1(group4_5, E,v), 1868}; 1869 1870#undef mmx 1871#undef vex1 1872#undef vex2 1873#undef vex3 1874#undef vex4 1875#undef vex4_unal 1876#undef vex5 1877#undef vex6 1878#undef vex7 1879#undef vex8 1880#undef vex11 1881#undef vex12 1882#undef vex13 1883 1884/* 1885 * Decode the fixed part of the opcode and place the last 1886 * in b. 1887 */ 1888static void decode_root(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1889{ 1890 *entry = opcodes_root[*b]; 1891} 1892 1893 1894static int decode_modrm(DisasContext *s, CPUX86State *env, 1895 X86DecodedInsn *decode, X86DecodedOp *op) 1896{ 1897 int modrm = get_modrm(s, env); 1898 if ((modrm >> 6) == 3) { 1899 op->n = (modrm & 7); 1900 if (op->unit != X86_OP_MMX) { 1901 op->n |= REX_B(s); 1902 } 1903 } else { 1904 op->has_ea = true; 1905 op->n = -1; 1906 decode->mem = gen_lea_modrm_0(env, s, modrm, 1907 decode->e.vex_class == 12); 1908 } 1909 return modrm; 1910} 1911 1912static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp *ot) 1913{ 1914 switch (size) { 1915 case X86_SIZE_b: /* byte */ 1916 *ot = MO_8; 1917 return true; 1918 1919 case X86_SIZE_d: /* 32-bit */ 1920 case X86_SIZE_ss: /* SSE/AVX scalar single precision */ 1921 *ot = MO_32; 1922 return true; 1923 1924 case X86_SIZE_p: /* Far pointer, return offset size */ 1925 case X86_SIZE_s: /* Descriptor, return offset size */ 1926 case X86_SIZE_v: /* 16/32/64-bit, based on operand size */ 1927 *ot = s->dflag; 1928 return true; 1929 1930 case X86_SIZE_pi: /* MMX */ 1931 case X86_SIZE_q: /* 64-bit */ 1932 case X86_SIZE_sd: /* SSE/AVX scalar double precision */ 1933 *ot = MO_64; 1934 return true; 1935 1936 case X86_SIZE_w: /* 16-bit */ 1937 *ot = MO_16; 1938 return true; 1939 1940 case X86_SIZE_y: /* 32/64-bit, based on operand size */ 1941 *ot = s->dflag == MO_16 ? MO_32 : s->dflag; 1942 return true; 1943 1944 case X86_SIZE_y_d64: /* Full (not 16-bit) register access */ 1945 *ot = CODE64(s) ? MO_64 : MO_32; 1946 return true; 1947 1948 case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */ 1949 *ot = s->dflag == MO_16 ? MO_16 : MO_32; 1950 return true; 1951 1952 case X86_SIZE_z_f64: /* 32-bit for 32-bit operand size or 64-bit mode, else 16-bit */ 1953 *ot = !CODE64(s) && s->dflag == MO_16 ? MO_16 : MO_32; 1954 return true; 1955 1956 case X86_SIZE_dq: /* SSE/AVX 128-bit */ 1957 if (e->special == X86_SPECIAL_MMX && 1958 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 1959 *ot = MO_64; 1960 return true; 1961 } 1962 if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) { 1963 return false; 1964 } 1965 *ot = MO_128; 1966 return true; 1967 1968 case X86_SIZE_qq: /* AVX 256-bit */ 1969 if (!s->vex_l) { 1970 return false; 1971 } 1972 *ot = MO_256; 1973 return true; 1974 1975 case X86_SIZE_x: /* 128/256-bit, based on operand size */ 1976 if (e->special == X86_SPECIAL_MMX && 1977 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 1978 *ot = MO_64; 1979 return true; 1980 } 1981 /* fall through */ 1982 case X86_SIZE_ps: /* SSE/AVX packed single precision */ 1983 case X86_SIZE_pd: /* SSE/AVX packed double precision */ 1984 *ot = s->vex_l ? MO_256 : MO_128; 1985 return true; 1986 1987 case X86_SIZE_xh: /* SSE/AVX packed half register */ 1988 *ot = s->vex_l ? MO_128 : MO_64; 1989 return true; 1990 1991 case X86_SIZE_d64: /* Default to 64-bit in 64-bit mode */ 1992 *ot = CODE64(s) && s->dflag == MO_32 ? MO_64 : s->dflag; 1993 return true; 1994 1995 case X86_SIZE_f64: /* Ignore size override prefix in 64-bit mode */ 1996 *ot = CODE64(s) ? MO_64 : s->dflag; 1997 return true; 1998 1999 default: 2000 *ot = -1; 2001 return true; 2002 } 2003} 2004 2005static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode, 2006 X86DecodedOp *op, X86OpType type, int b) 2007{ 2008 int modrm; 2009 2010 switch (type) { 2011 case X86_TYPE_None: /* Implicit or absent */ 2012 case X86_TYPE_A: /* Implicit */ 2013 case X86_TYPE_F: /* EFLAGS/RFLAGS */ 2014 case X86_TYPE_X: /* string source */ 2015 case X86_TYPE_Y: /* string destination */ 2016 break; 2017 2018 case X86_TYPE_B: /* VEX.vvvv selects a GPR */ 2019 op->unit = X86_OP_INT; 2020 op->n = s->vex_v; 2021 break; 2022 2023 case X86_TYPE_C: /* REG in the modrm byte selects a control register */ 2024 op->unit = X86_OP_CR; 2025 op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s); 2026 if (op->n == 0 && (s->prefix & PREFIX_LOCK) && 2027 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { 2028 op->n = 8; 2029 s->prefix &= ~PREFIX_LOCK; 2030 } 2031 if (op->n != 0 && op->n != 2 && op->n != 3 && op->n != 4 && op->n != 8) { 2032 return false; 2033 } 2034 if (decode->e.intercept) { 2035 decode->e.intercept += op->n; 2036 } 2037 break; 2038 2039 case X86_TYPE_D: /* REG in the modrm byte selects a debug register */ 2040 op->unit = X86_OP_DR; 2041 op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s); 2042 if (op->n >= 8) { 2043 /* 2044 * illegal opcode. The DR4 and DR5 case is checked in the generated 2045 * code instead, to save on hflags bits. 2046 */ 2047 return false; 2048 } 2049 if (decode->e.intercept) { 2050 decode->e.intercept += op->n; 2051 } 2052 break; 2053 2054 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */ 2055 op->unit = X86_OP_INT; 2056 goto get_reg; 2057 2058 case X86_TYPE_S: /* reg selects a segment register */ 2059 op->unit = X86_OP_SEG; 2060 goto get_reg; 2061 2062 case X86_TYPE_P: 2063 op->unit = X86_OP_MMX; 2064 goto get_reg; 2065 2066 case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */ 2067 if (decode->e.special == X86_SPECIAL_MMX && 2068 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 2069 op->unit = X86_OP_MMX; 2070 } else { 2071 op->unit = X86_OP_SSE; 2072 } 2073 get_reg: 2074 op->n = ((get_modrm(s, env) >> 3) & 7); 2075 if (op->unit != X86_OP_MMX) { 2076 op->n |= REX_R(s); 2077 } 2078 break; 2079 2080 case X86_TYPE_E: /* ALU modrm operand */ 2081 op->unit = X86_OP_INT; 2082 goto get_modrm; 2083 2084 case X86_TYPE_Q: /* MMX modrm operand */ 2085 op->unit = X86_OP_MMX; 2086 goto get_modrm; 2087 2088 case X86_TYPE_W: /* XMM/YMM modrm operand */ 2089 if (decode->e.special == X86_SPECIAL_MMX && 2090 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 2091 op->unit = X86_OP_MMX; 2092 } else { 2093 op->unit = X86_OP_SSE; 2094 } 2095 goto get_modrm; 2096 2097 case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */ 2098 op->unit = X86_OP_MMX; 2099 goto get_modrm_reg; 2100 2101 case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */ 2102 if (decode->e.special == X86_SPECIAL_MMX && 2103 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 2104 op->unit = X86_OP_MMX; 2105 } else { 2106 op->unit = X86_OP_SSE; 2107 } 2108 goto get_modrm_reg; 2109 2110 case X86_TYPE_R: /* R/M in the modrm byte selects a register */ 2111 op->unit = X86_OP_INT; 2112 get_modrm_reg: 2113 modrm = get_modrm(s, env); 2114 if ((modrm >> 6) != 3) { 2115 return false; 2116 } 2117 goto get_modrm; 2118 2119 case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */ 2120 op->unit = X86_OP_SSE; 2121 goto get_modrm_mem; 2122 2123 case X86_TYPE_EM: /* modrm byte selects an ALU memory operand */ 2124 op->unit = X86_OP_INT; 2125 /* fall through */ 2126 case X86_TYPE_M: /* modrm byte selects a memory operand */ 2127 get_modrm_mem: 2128 modrm = get_modrm(s, env); 2129 if ((modrm >> 6) == 3) { 2130 return false; 2131 } 2132 /* fall through */ 2133 case X86_TYPE_nop: /* modrm operand decoded but not fetched */ 2134 get_modrm: 2135 decode_modrm(s, env, decode, op); 2136 break; 2137 2138 case X86_TYPE_O: /* Absolute address encoded in the instruction */ 2139 op->unit = X86_OP_INT; 2140 op->has_ea = true; 2141 op->n = -1; 2142 decode->mem = (AddressParts) { 2143 .def_seg = R_DS, 2144 .base = -1, 2145 .index = -1, 2146 .disp = insn_get_addr(env, s, s->aflag) 2147 }; 2148 break; 2149 2150 case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */ 2151 if ((s->prefix & PREFIX_VEX)) { 2152 op->unit = X86_OP_SSE; 2153 op->n = s->vex_v; 2154 break; 2155 } 2156 if (op == &decode->op[0]) { 2157 /* shifts place the destination in VEX.vvvv, use modrm */ 2158 return decode_op(s, env, decode, op, decode->e.op1, b); 2159 } else { 2160 return decode_op(s, env, decode, op, decode->e.op0, b); 2161 } 2162 2163 case X86_TYPE_I: /* Immediate */ 2164 case X86_TYPE_J: /* Relative offset for a jump */ 2165 op->unit = X86_OP_IMM; 2166 decode->immediate = op->imm = insn_get_signed(env, s, op->ot); 2167 break; 2168 2169 case X86_TYPE_I_unsigned: /* Immediate */ 2170 op->unit = X86_OP_IMM; 2171 decode->immediate = op->imm = insn_get(env, s, op->ot); 2172 break; 2173 2174 case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */ 2175 op->n = insn_get(env, s, op->ot) >> 4; 2176 break; 2177 2178 case X86_TYPE_2op: 2179 *op = decode->op[0]; 2180 break; 2181 2182 case X86_TYPE_LoBits: 2183 op->n = (b & 7) | REX_B(s); 2184 op->unit = X86_OP_INT; 2185 break; 2186 2187 case X86_TYPE_0 ... X86_TYPE_7: 2188 op->n = type - X86_TYPE_0; 2189 op->unit = X86_OP_INT; 2190 break; 2191 2192 case X86_TYPE_ES ... X86_TYPE_GS: 2193 op->n = type - X86_TYPE_ES; 2194 op->unit = X86_OP_SEG; 2195 break; 2196 } 2197 2198 return true; 2199} 2200 2201static bool validate_sse_prefix(DisasContext *s, X86OpEntry *e) 2202{ 2203 uint16_t sse_prefixes; 2204 2205 if (!e->valid_prefix) { 2206 return true; 2207 } 2208 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2209 /* In SSE instructions, 0xF3 and 0xF2 cancel 0x66. */ 2210 s->prefix &= ~PREFIX_DATA; 2211 } 2212 2213 /* Now, either zero or one bit is set in sse_prefixes. */ 2214 sse_prefixes = s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); 2215 return e->valid_prefix & (1 << sse_prefixes); 2216} 2217 2218static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func, 2219 X86DecodedInsn *decode) 2220{ 2221 X86OpEntry *e = &decode->e; 2222 2223 decode_func(s, env, e, &decode->b); 2224 while (e->is_decode) { 2225 e->is_decode = false; 2226 e->decode(s, env, e, &decode->b); 2227 } 2228 2229 if (!validate_sse_prefix(s, e)) { 2230 return false; 2231 } 2232 2233 /* First compute size of operands in order to initialize s->rip_offset. */ 2234 if (e->op0 != X86_TYPE_None) { 2235 if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) { 2236 return false; 2237 } 2238 if (e->op0 == X86_TYPE_I) { 2239 s->rip_offset += 1 << decode->op[0].ot; 2240 } 2241 } 2242 if (e->op1 != X86_TYPE_None) { 2243 if (!decode_op_size(s, e, e->s1, &decode->op[1].ot)) { 2244 return false; 2245 } 2246 if (e->op1 == X86_TYPE_I) { 2247 s->rip_offset += 1 << decode->op[1].ot; 2248 } 2249 } 2250 if (e->op2 != X86_TYPE_None) { 2251 if (!decode_op_size(s, e, e->s2, &decode->op[2].ot)) { 2252 return false; 2253 } 2254 if (e->op2 == X86_TYPE_I) { 2255 s->rip_offset += 1 << decode->op[2].ot; 2256 } 2257 } 2258 if (e->op3 != X86_TYPE_None) { 2259 /* 2260 * A couple instructions actually use the extra immediate byte for an Lx 2261 * register operand; those are handled in the gen_* functions as one off. 2262 */ 2263 assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b); 2264 s->rip_offset += 1; 2265 } 2266 2267 if (e->op0 != X86_TYPE_None && 2268 !decode_op(s, env, decode, &decode->op[0], e->op0, decode->b)) { 2269 return false; 2270 } 2271 2272 if (e->op1 != X86_TYPE_None && 2273 !decode_op(s, env, decode, &decode->op[1], e->op1, decode->b)) { 2274 return false; 2275 } 2276 2277 if (e->op2 != X86_TYPE_None && 2278 !decode_op(s, env, decode, &decode->op[2], e->op2, decode->b)) { 2279 return false; 2280 } 2281 2282 if (e->op3 != X86_TYPE_None) { 2283 decode->immediate = insn_get_signed(env, s, MO_8); 2284 } 2285 2286 return true; 2287} 2288 2289static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid) 2290{ 2291 switch (cpuid) { 2292 case X86_FEAT_None: 2293 return true; 2294 case X86_FEAT_CMOV: 2295 return (s->cpuid_features & CPUID_CMOV); 2296 case X86_FEAT_CLFLUSH: 2297 return (s->cpuid_features & CPUID_CLFLUSH); 2298 case X86_FEAT_CX8: 2299 return (s->cpuid_features & CPUID_CX8); 2300 case X86_FEAT_FXSR: 2301 return (s->cpuid_features & CPUID_FXSR); 2302 case X86_FEAT_CX16: 2303 return (s->cpuid_ext_features & CPUID_EXT_CX16); 2304 case X86_FEAT_F16C: 2305 return (s->cpuid_ext_features & CPUID_EXT_F16C); 2306 case X86_FEAT_FMA: 2307 return (s->cpuid_ext_features & CPUID_EXT_FMA); 2308 case X86_FEAT_MOVBE: 2309 return (s->cpuid_ext_features & CPUID_EXT_MOVBE); 2310 case X86_FEAT_PCLMULQDQ: 2311 return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ); 2312 case X86_FEAT_POPCNT: 2313 return (s->cpuid_ext_features & CPUID_EXT_POPCNT); 2314 case X86_FEAT_SSE: 2315 return (s->cpuid_features & CPUID_SSE); 2316 case X86_FEAT_SSE2: 2317 return (s->cpuid_features & CPUID_SSE2); 2318 case X86_FEAT_SSE3: 2319 return (s->cpuid_ext_features & CPUID_EXT_SSE3); 2320 case X86_FEAT_SSSE3: 2321 return (s->cpuid_ext_features & CPUID_EXT_SSSE3); 2322 case X86_FEAT_SSE41: 2323 return (s->cpuid_ext_features & CPUID_EXT_SSE41); 2324 case X86_FEAT_SSE42: 2325 return (s->cpuid_ext_features & CPUID_EXT_SSE42); 2326 case X86_FEAT_AES: 2327 if (!(s->cpuid_ext_features & CPUID_EXT_AES)) { 2328 return false; 2329 } else if (!(s->prefix & PREFIX_VEX)) { 2330 return true; 2331 } else if (!(s->cpuid_ext_features & CPUID_EXT_AVX)) { 2332 return false; 2333 } else { 2334 return !s->vex_l || (s->cpuid_7_0_ecx_features & CPUID_7_0_ECX_VAES); 2335 } 2336 2337 case X86_FEAT_AVX: 2338 return (s->cpuid_ext_features & CPUID_EXT_AVX); 2339 case X86_FEAT_XSAVE: 2340 return (s->cpuid_ext_features & CPUID_EXT_XSAVE); 2341 2342 case X86_FEAT_3DNOW: 2343 return (s->cpuid_ext2_features & CPUID_EXT2_3DNOW); 2344 case X86_FEAT_SSE4A: 2345 return (s->cpuid_ext3_features & CPUID_EXT3_SSE4A); 2346 2347 case X86_FEAT_ADX: 2348 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX); 2349 case X86_FEAT_BMI1: 2350 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1); 2351 case X86_FEAT_BMI2: 2352 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2); 2353 case X86_FEAT_AVX2: 2354 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2); 2355 case X86_FEAT_CLFLUSHOPT: 2356 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_CLFLUSHOPT); 2357 case X86_FEAT_CLWB: 2358 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_CLWB); 2359 case X86_FEAT_FSGSBASE: 2360 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_FSGSBASE); 2361 case X86_FEAT_SHA_NI: 2362 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SHA_NI); 2363 2364 case X86_FEAT_CMPCCXADD: 2365 return (s->cpuid_7_1_eax_features & CPUID_7_1_EAX_CMPCCXADD); 2366 2367 case X86_FEAT_XSAVEOPT: 2368 return (s->cpuid_xsave_features & CPUID_XSAVE_XSAVEOPT); 2369 } 2370 g_assert_not_reached(); 2371} 2372 2373static bool validate_vex(DisasContext *s, X86DecodedInsn *decode) 2374{ 2375 X86OpEntry *e = &decode->e; 2376 2377 switch (e->vex_special) { 2378 case X86_VEX_REPScalar: 2379 /* 2380 * Instructions which differ between 00/66 and F2/F3 in the 2381 * exception classification and the size of the memory operand. 2382 */ 2383 assert(e->vex_class == 1 || e->vex_class == 2 || e->vex_class == 4); 2384 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2385 e->vex_class = e->vex_class < 4 ? 3 : 5; 2386 if (s->vex_l) { 2387 goto illegal; 2388 } 2389 assert(decode->e.s2 == X86_SIZE_x); 2390 if (decode->op[2].has_ea) { 2391 decode->op[2].ot = s->prefix & PREFIX_REPZ ? MO_32 : MO_64; 2392 } 2393 } 2394 break; 2395 2396 case X86_VEX_SSEUnaligned: 2397 /* handled in sse_needs_alignment. */ 2398 break; 2399 2400 case X86_VEX_AVX2_256: 2401 if ((s->prefix & PREFIX_VEX) && s->vex_l && !has_cpuid_feature(s, X86_FEAT_AVX2)) { 2402 goto illegal; 2403 } 2404 } 2405 2406 switch (e->vex_class) { 2407 case 0: 2408 if (s->prefix & PREFIX_VEX) { 2409 goto illegal; 2410 } 2411 return true; 2412 case 1: 2413 case 2: 2414 case 3: 2415 case 4: 2416 case 5: 2417 case 7: 2418 if (s->prefix & PREFIX_VEX) { 2419 if (!(s->flags & HF_AVX_EN_MASK)) { 2420 goto illegal; 2421 } 2422 } else if (e->special != X86_SPECIAL_MMX || 2423 (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) { 2424 if (!(s->flags & HF_OSFXSR_MASK)) { 2425 goto illegal; 2426 } 2427 } 2428 break; 2429 case 12: 2430 /* Must have a VSIB byte and no address prefix. */ 2431 assert(s->has_modrm); 2432 if ((s->modrm & 7) != 4 || s->aflag == MO_16) { 2433 goto illegal; 2434 } 2435 2436 /* Check no overlap between registers. */ 2437 if (!decode->op[0].has_ea && 2438 (decode->op[0].n == decode->mem.index || decode->op[0].n == decode->op[1].n)) { 2439 goto illegal; 2440 } 2441 assert(!decode->op[1].has_ea); 2442 if (decode->op[1].n == decode->mem.index) { 2443 goto illegal; 2444 } 2445 if (!decode->op[2].has_ea && 2446 (decode->op[2].n == decode->mem.index || decode->op[2].n == decode->op[1].n)) { 2447 goto illegal; 2448 } 2449 /* fall through */ 2450 case 6: 2451 case 11: 2452 if (!(s->prefix & PREFIX_VEX)) { 2453 goto illegal; 2454 } 2455 if (!(s->flags & HF_AVX_EN_MASK)) { 2456 goto illegal; 2457 } 2458 break; 2459 case 8: 2460 /* Non-VEX case handled in decode_0F77. */ 2461 assert(s->prefix & PREFIX_VEX); 2462 if (!(s->flags & HF_AVX_EN_MASK)) { 2463 goto illegal; 2464 } 2465 break; 2466 case 13: 2467 if (!(s->prefix & PREFIX_VEX)) { 2468 goto illegal; 2469 } 2470 if (s->vex_l) { 2471 goto illegal; 2472 } 2473 /* All integer instructions use VEX.vvvv, so exit. */ 2474 return true; 2475 } 2476 2477 if (s->vex_v != 0 && 2478 e->op0 != X86_TYPE_H && e->op0 != X86_TYPE_B && 2479 e->op1 != X86_TYPE_H && e->op1 != X86_TYPE_B && 2480 e->op2 != X86_TYPE_H && e->op2 != X86_TYPE_B) { 2481 goto illegal; 2482 } 2483 2484 if (s->flags & HF_TS_MASK) { 2485 goto nm_exception; 2486 } 2487 if (s->flags & HF_EM_MASK) { 2488 goto illegal; 2489 } 2490 2491 if (e->check) { 2492 if (e->check & X86_CHECK_VEX128) { 2493 if (s->vex_l) { 2494 goto illegal; 2495 } 2496 } 2497 if (e->check & X86_CHECK_W0) { 2498 if (s->vex_w) { 2499 goto illegal; 2500 } 2501 } 2502 if (e->check & X86_CHECK_W1) { 2503 if (!s->vex_w) { 2504 goto illegal; 2505 } 2506 } 2507 } 2508 return true; 2509 2510nm_exception: 2511 gen_NM_exception(s); 2512 return false; 2513illegal: 2514 gen_illegal_opcode(s); 2515 return false; 2516} 2517 2518/* 2519 * Convert one instruction. s->base.is_jmp is set if the translation must 2520 * be stopped. 2521 */ 2522static void disas_insn(DisasContext *s, CPUState *cpu) 2523{ 2524 CPUX86State *env = cpu_env(cpu); 2525 X86DecodedInsn decode; 2526 X86DecodeFunc decode_func = decode_root; 2527 bool accept_lock = false; 2528 uint8_t cc_live, b; 2529 2530 s->pc = s->base.pc_next; 2531 s->override = -1; 2532 s->popl_esp_hack = 0; 2533#ifdef TARGET_X86_64 2534 s->rex_r = 0; 2535 s->rex_x = 0; 2536 s->rex_b = 0; 2537#endif 2538 s->rip_offset = 0; /* for relative ip address */ 2539 s->vex_l = 0; 2540 s->vex_v = 0; 2541 s->vex_w = false; 2542 s->has_modrm = false; 2543 s->prefix = 0; 2544 2545 next_byte: 2546 b = x86_ldub_code(env, s); 2547 2548 /* Collect prefixes. */ 2549 switch (b) { 2550 case 0xf3: 2551 s->prefix |= PREFIX_REPZ; 2552 s->prefix &= ~PREFIX_REPNZ; 2553 goto next_byte; 2554 case 0xf2: 2555 s->prefix |= PREFIX_REPNZ; 2556 s->prefix &= ~PREFIX_REPZ; 2557 goto next_byte; 2558 case 0xf0: 2559 s->prefix |= PREFIX_LOCK; 2560 goto next_byte; 2561 case 0x2e: 2562 s->override = R_CS; 2563 goto next_byte; 2564 case 0x36: 2565 s->override = R_SS; 2566 goto next_byte; 2567 case 0x3e: 2568 s->override = R_DS; 2569 goto next_byte; 2570 case 0x26: 2571 s->override = R_ES; 2572 goto next_byte; 2573 case 0x64: 2574 s->override = R_FS; 2575 goto next_byte; 2576 case 0x65: 2577 s->override = R_GS; 2578 goto next_byte; 2579 case 0x66: 2580 s->prefix |= PREFIX_DATA; 2581 goto next_byte; 2582 case 0x67: 2583 s->prefix |= PREFIX_ADR; 2584 goto next_byte; 2585#ifdef TARGET_X86_64 2586 case 0x40 ... 0x4f: 2587 if (CODE64(s)) { 2588 /* REX prefix */ 2589 s->prefix |= PREFIX_REX; 2590 s->vex_w = (b >> 3) & 1; 2591 s->rex_r = (b & 0x4) << 1; 2592 s->rex_x = (b & 0x2) << 2; 2593 s->rex_b = (b & 0x1) << 3; 2594 goto next_byte; 2595 } 2596 break; 2597#endif 2598 case 0xc5: /* 2-byte VEX */ 2599 case 0xc4: /* 3-byte VEX */ 2600 /* 2601 * VEX prefixes cannot be used except in 32-bit mode. 2602 * Otherwise the instruction is LES or LDS. 2603 */ 2604 if (CODE32(s) && !VM86(s)) { 2605 static const int pp_prefix[4] = { 2606 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ 2607 }; 2608 int vex3, vex2 = x86_ldub_code(env, s); 2609 2610 if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) { 2611 /* 2612 * 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b, 2613 * otherwise the instruction is LES or LDS. 2614 */ 2615 s->pc--; /* rewind the advance_pc() x86_ldub_code() did */ 2616 break; 2617 } 2618 2619 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */ 2620 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ 2621 | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) { 2622 goto illegal_op; 2623 } 2624#ifdef TARGET_X86_64 2625 s->rex_r = (~vex2 >> 4) & 8; 2626#endif 2627 if (b == 0xc5) { 2628 /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */ 2629 vex3 = vex2; 2630 decode_func = decode_0F; 2631 } else { 2632 /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */ 2633 vex3 = x86_ldub_code(env, s); 2634#ifdef TARGET_X86_64 2635 s->rex_x = (~vex2 >> 3) & 8; 2636 s->rex_b = (~vex2 >> 2) & 8; 2637#endif 2638 s->vex_w = (vex3 >> 7) & 1; 2639 switch (vex2 & 0x1f) { 2640 case 0x01: /* Implied 0f leading opcode bytes. */ 2641 decode_func = decode_0F; 2642 break; 2643 case 0x02: /* Implied 0f 38 leading opcode bytes. */ 2644 decode_func = decode_0F38; 2645 break; 2646 case 0x03: /* Implied 0f 3a leading opcode bytes. */ 2647 decode_func = decode_0F3A; 2648 break; 2649 default: /* Reserved for future use. */ 2650 goto unknown_op; 2651 } 2652 } 2653 s->vex_v = (~vex3 >> 3) & 0xf; 2654 s->vex_l = (vex3 >> 2) & 1; 2655 s->prefix |= pp_prefix[vex3 & 3] | PREFIX_VEX; 2656 } 2657 break; 2658 default: 2659 break; 2660 } 2661 2662 /* Post-process prefixes. */ 2663 if (CODE64(s)) { 2664 /* 2665 * In 64-bit mode, the default data size is 32-bit. Select 64-bit 2666 * data with rex_w, and 16-bit data with 0x66; rex_w takes precedence 2667 * over 0x66 if both are present. 2668 */ 2669 s->dflag = (REX_W(s) ? MO_64 : s->prefix & PREFIX_DATA ? MO_16 : MO_32); 2670 /* In 64-bit mode, 0x67 selects 32-bit addressing. */ 2671 s->aflag = (s->prefix & PREFIX_ADR ? MO_32 : MO_64); 2672 } else { 2673 /* In 16/32-bit mode, 0x66 selects the opposite data size. */ 2674 if (CODE32(s) ^ ((s->prefix & PREFIX_DATA) != 0)) { 2675 s->dflag = MO_32; 2676 } else { 2677 s->dflag = MO_16; 2678 } 2679 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */ 2680 if (CODE32(s) ^ ((s->prefix & PREFIX_ADR) != 0)) { 2681 s->aflag = MO_32; 2682 } else { 2683 s->aflag = MO_16; 2684 } 2685 } 2686 2687 memset(&decode, 0, sizeof(decode)); 2688 decode.cc_op = -1; 2689 decode.b = b; 2690 if (!decode_insn(s, env, decode_func, &decode)) { 2691 goto illegal_op; 2692 } 2693 if (!decode.e.gen) { 2694 goto unknown_op; 2695 } 2696 2697 if (!has_cpuid_feature(s, decode.e.cpuid)) { 2698 goto illegal_op; 2699 } 2700 2701 /* Checks that result in #UD come first. */ 2702 if (decode.e.check) { 2703 if (CODE64(s)) { 2704 if (decode.e.check & X86_CHECK_i64) { 2705 goto illegal_op; 2706 } 2707 if ((decode.e.check & X86_CHECK_i64_amd) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) { 2708 goto illegal_op; 2709 } 2710 } else { 2711 if (decode.e.check & X86_CHECK_o64) { 2712 goto illegal_op; 2713 } 2714 if ((decode.e.check & X86_CHECK_o64_intel) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) { 2715 goto illegal_op; 2716 } 2717 } 2718 if (decode.e.check & X86_CHECK_prot_or_vm86) { 2719 if (!PE(s)) { 2720 goto illegal_op; 2721 } 2722 } 2723 if (decode.e.check & X86_CHECK_no_vm86) { 2724 if (VM86(s)) { 2725 goto illegal_op; 2726 } 2727 } 2728 } 2729 2730 switch (decode.e.special) { 2731 case X86_SPECIAL_None: 2732 break; 2733 2734 case X86_SPECIAL_Locked: 2735 if (decode.op[0].has_ea) { 2736 s->prefix |= PREFIX_LOCK; 2737 } 2738 /* fallthrough */ 2739 case X86_SPECIAL_HasLock: 2740 case X86_SPECIAL_BitTest: 2741 accept_lock = decode.op[0].has_ea; 2742 break; 2743 2744 case X86_SPECIAL_Op0_Rd: 2745 assert(decode.op[0].unit == X86_OP_INT); 2746 if (!decode.op[0].has_ea) { 2747 decode.op[0].ot = MO_32; 2748 } 2749 break; 2750 2751 case X86_SPECIAL_Op2_Ry: 2752 assert(decode.op[2].unit == X86_OP_INT); 2753 if (!decode.op[2].has_ea) { 2754 decode.op[2].ot = s->dflag == MO_16 ? MO_32 : s->dflag; 2755 } 2756 break; 2757 2758 case X86_SPECIAL_AVXExtMov: 2759 if (!decode.op[2].has_ea) { 2760 decode.op[2].ot = s->vex_l ? MO_256 : MO_128; 2761 } else if (s->vex_l) { 2762 decode.op[2].ot++; 2763 } 2764 break; 2765 2766 case X86_SPECIAL_SExtT0: 2767 case X86_SPECIAL_ZExtT0: 2768 /* Handled in gen_load. */ 2769 assert(decode.op[1].unit == X86_OP_INT); 2770 break; 2771 2772 case X86_SPECIAL_Op0_Mw: 2773 assert(decode.op[0].unit == X86_OP_INT); 2774 if (decode.op[0].has_ea) { 2775 decode.op[0].ot = MO_16; 2776 } 2777 break; 2778 2779 default: 2780 break; 2781 } 2782 2783 if ((s->prefix & PREFIX_LOCK) && !accept_lock) { 2784 goto illegal_op; 2785 } 2786 2787 if (!validate_vex(s, &decode)) { 2788 return; 2789 } 2790 2791 /* 2792 * Checks that result in #GP or VMEXIT come second. Intercepts are 2793 * generally checked after non-memory exceptions (i.e. after all 2794 * exceptions if there is no memory operand). Exceptions are 2795 * vm86 checks (INTn, IRET, PUSHF/POPF), RSM and XSETBV (!). 2796 * 2797 * XSETBV will check for CPL0 in the gen_* function instead of using chk(). 2798 */ 2799 if (decode.e.check & X86_CHECK_cpl0) { 2800 if (CPL(s) != 0) { 2801 goto gp_fault; 2802 } 2803 } 2804 if (decode.e.has_intercept && unlikely(GUEST(s))) { 2805 gen_helper_svm_check_intercept(tcg_env, 2806 tcg_constant_i32(decode.e.intercept)); 2807 } 2808 if (decode.e.check) { 2809 if ((decode.e.check & X86_CHECK_smm) && !(s->flags & HF_SMM_MASK)) { 2810 goto illegal_op; 2811 } 2812 if ((decode.e.check & X86_CHECK_vm86_iopl) && VM86(s)) { 2813 if (IOPL(s) < 3) { 2814 goto gp_fault; 2815 } 2816 } else if (decode.e.check & X86_CHECK_cpl_iopl) { 2817 if (IOPL(s) < CPL(s)) { 2818 goto gp_fault; 2819 } 2820 } 2821 } 2822 2823 if (decode.e.special == X86_SPECIAL_MMX && 2824 !(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) { 2825 gen_helper_enter_mmx(tcg_env); 2826 } 2827 2828 if (decode.e.special != X86_SPECIAL_NoLoadEA && 2829 (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea)) { 2830 gen_lea_modrm(s, &decode); 2831 } 2832 if (s->prefix & PREFIX_LOCK) { 2833 assert(decode.op[0].has_ea && !decode.op[2].has_ea); 2834 gen_load(s, &decode, 2, s->T1); 2835 decode.e.gen(s, &decode); 2836 } else { 2837 if (decode.op[0].unit == X86_OP_MMX) { 2838 compute_mmx_offset(&decode.op[0]); 2839 } else if (decode.op[0].unit == X86_OP_SSE) { 2840 compute_xmm_offset(&decode.op[0]); 2841 } 2842 gen_load(s, &decode, 1, s->T0); 2843 gen_load(s, &decode, 2, s->T1); 2844 decode.e.gen(s, &decode); 2845 gen_writeback(s, &decode, 0, s->T0); 2846 } 2847 2848 /* 2849 * Write back flags after last memory access. Some older ALU instructions, as 2850 * well as SSE instructions, write flags in the gen_* function, but that can 2851 * cause incorrect tracking of CC_OP for instructions that write to both memory 2852 * and flags. 2853 */ 2854 if (decode.cc_op != -1) { 2855 if (decode.cc_dst) { 2856 tcg_gen_mov_tl(cpu_cc_dst, decode.cc_dst); 2857 } 2858 if (decode.cc_src) { 2859 tcg_gen_mov_tl(cpu_cc_src, decode.cc_src); 2860 } 2861 if (decode.cc_src2) { 2862 tcg_gen_mov_tl(cpu_cc_src2, decode.cc_src2); 2863 } 2864 if (decode.cc_op == CC_OP_DYNAMIC) { 2865 tcg_gen_mov_i32(cpu_cc_op, decode.cc_op_dynamic); 2866 } 2867 set_cc_op(s, decode.cc_op); 2868 cc_live = cc_op_live(decode.cc_op); 2869 } else { 2870 cc_live = 0; 2871 } 2872 if (decode.cc_op != CC_OP_DYNAMIC) { 2873 assert(!decode.cc_op_dynamic); 2874 assert(!!decode.cc_dst == !!(cc_live & USES_CC_DST)); 2875 assert(!!decode.cc_src == !!(cc_live & USES_CC_SRC)); 2876 assert(!!decode.cc_src2 == !!(cc_live & USES_CC_SRC2)); 2877 } 2878 2879 return; 2880 gp_fault: 2881 gen_exception_gpf(s); 2882 return; 2883 illegal_op: 2884 gen_illegal_opcode(s); 2885 return; 2886 unknown_op: 2887 gen_unknown_opcode(env, s); 2888} 2889