1/* 2 * New-style decoder for i386 instructions 3 * 4 * Copyright (c) 2022 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22/* 23 * The decoder is mostly based on tables copied from the Intel SDM. As 24 * a result, most operand load and writeback is done entirely in common 25 * table-driven code using the same operand type (X86_TYPE_*) and 26 * size (X86_SIZE_*) codes used in the manual. There are a few differences 27 * though. 28 * 29 * Operand sizes 30 * ------------- 31 * 32 * The manual lists d64 ("cannot encode 32-bit size in 64-bit mode") and f64 33 * ("cannot encode 16-bit or 32-bit size in 64-bit mode") as modifiers of the 34 * "v" or "z" sizes. The decoder simply makes them separate operand sizes. 35 * 36 * The manual lists immediate far destinations as Ap (technically an implicit 37 * argument). The decoder splits them into two immediates, using "Ip" for 38 * the offset part (that comes first in the instruction stream) and "Iw" for 39 * the segment/selector part. The size of the offset is given by s->dflag 40 * and the instructions are illegal in 64-bit mode, so the choice of "Ip" 41 * is somewhat arbitrary; "Iv" or "Iz" would work just as well. 42 * 43 * Operand types 44 * ------------- 45 * 46 * For memory-only operands, if the emitter functions wants to rely on 47 * generic load and writeback, the decoder needs to know the type of the 48 * operand. Therefore, M is often replaced by the more specific EM and WM 49 * (respectively selecting an ALU operand, like the operand type E, or a 50 * vector operand like the operand type W). 51 * 52 * Immediates are almost always signed or masked away in helpers. Two 53 * common exceptions are IN/OUT and absolute jumps. For these, there is 54 * an additional custom operand type "I_unsigned". Alternatively, the 55 * mask could be applied (and the original sign-extended value would be 56 * optimized away by TCG) in the emitter function. 57 * 58 * Finally, a "nop" operand type is used for multi-byte NOPs. It accepts 59 * any value of mod including 11b (unlike M) but it does not try to 60 * interpret the operand (like M). 61 * 62 * Vector operands 63 * --------------- 64 * 65 * The main difference is that the V, U and W types are extended to 66 * cover MMX as well; if an instruction is like 67 * 68 * por Pq, Qq 69 * 66 por Vx, Hx, Wx 70 * 71 * only the second row is included and the instruction is marked as a 72 * valid MMX instruction. The MMX flag directs the decoder to rewrite 73 * the V/U/H/W types to P/N/P/Q if there is no prefix, as well as changing 74 * "x" to "q" if there is no prefix. 75 * 76 * In addition, the ss/ps/sd/pd types are sometimes mushed together as "x" 77 * if the difference is expressed via prefixes. Individual instructions 78 * are separated by prefix in the generator functions. 79 * 80 * There is a custom size "xh" used to address half of a SSE/AVX operand. 81 * This points to a 64-bit operand for SSE operations, 128-bit operand 82 * for 256-bit AVX operands, etc. It is used for conversion operations 83 * such as VCVTPH2PS or VCVTSS2SD. 84 * 85 * There are a couple cases in which instructions (e.g. MOVD) write the 86 * whole XMM or MM register but are established incorrectly in the manual 87 * as "d" or "q". These have to be fixed for the decoder to work correctly. 88 * 89 * VEX exception classes 90 * --------------------- 91 * 92 * Speaking about imprecisions in the manual, the decoder treats all 93 * exception-class 4 instructions as having an optional VEX prefix, and 94 * all exception-class 6 instructions as having a mandatory VEX prefix. 95 * This is true except for a dozen instructions; these are in exception 96 * class 4 but do not ignore the VEX.W bit (which does not even exist 97 * without a VEX prefix). These instructions are mostly listed in Intel's 98 * table 2-16, but with a few exceptions. 99 * 100 * The AMD manual has more precise subclasses for exceptions, and unlike Intel 101 * they list the VEX.W requirements in the exception classes as well (except 102 * when they don't). AMD describes class 6 as "AVX Mixed Memory Argument" 103 * without defining what a mixed memory argument is, but still use 4 as the 104 * primary exception class... except when they don't. 105 * 106 * The summary is: 107 * Intel AMD VEX.W note 108 * ------------------------------------------------------------------- 109 * vpblendd 4 4J 0 110 * vpblendvb 4 4E-X 0 (*) 111 * vpbroadcastq 6 6D 0 (+) 112 * vpermd/vpermps 4 4H 0 (§) 113 * vpermq/vpermpd 4 4H-1 1 (§) 114 * vpermilpd/vpermilps 4 6E 0 (^) 115 * vpmaskmovd 6 4K significant (^) 116 * vpsllv 4 4K significant 117 * vpsrav 4 4J 0 118 * vpsrlv 4 4K significant 119 * vtestps/vtestpd 4 4G 0 120 * 121 * (*) AMD lists VPBLENDVB as related to SSE4.1 PBLENDVB, which may 122 * explain why it is considered exception class 4. However, 123 * Intel says that VEX-only instructions should be in class 6... 124 * 125 * (+) Not found in Intel's table 2-16 126 * 127 * (§) 4H and 4H-1 do not mention VEX.W requirements, which are 128 * however present in the description of the instruction 129 * 130 * (^) these are the two cases in which Intel and AMD disagree on the 131 * primary exception class 132 */ 133 134#define X86_OP_NONE { 0 }, 135 136#define X86_OP_GROUP3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \ 137 .decode = glue(decode_, op), \ 138 .op0 = glue(X86_TYPE_, op0_), \ 139 .s0 = glue(X86_SIZE_, s0_), \ 140 .op1 = glue(X86_TYPE_, op1_), \ 141 .s1 = glue(X86_SIZE_, s1_), \ 142 .op2 = glue(X86_TYPE_, op2_), \ 143 .s2 = glue(X86_SIZE_, s2_), \ 144 .is_decode = true, \ 145 ## __VA_ARGS__ \ 146} 147 148#define X86_OP_GROUP1(op, op0, s0, ...) \ 149 X86_OP_GROUP3(op, op0, s0, 2op, s0, None, None, ## __VA_ARGS__) 150#define X86_OP_GROUP2(op, op0, s0, op1, s1, ...) \ 151 X86_OP_GROUP3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__) 152#define X86_OP_GROUPw(op, op0, s0, ...) \ 153 X86_OP_GROUP3(op, op0, s0, None, None, None, None, ## __VA_ARGS__) 154#define X86_OP_GROUP0(op, ...) \ 155 X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__) 156 157#define X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \ 158 .gen = glue(gen_, op), \ 159 .op0 = glue(X86_TYPE_, op0_), \ 160 .s0 = glue(X86_SIZE_, s0_), \ 161 .op1 = glue(X86_TYPE_, op1_), \ 162 .s1 = glue(X86_SIZE_, s1_), \ 163 .op2 = glue(X86_TYPE_, op2_), \ 164 .s2 = glue(X86_SIZE_, s2_), \ 165 ## __VA_ARGS__ \ 166} 167 168#define X86_OP_ENTRY4(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) \ 169 X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, \ 170 .op3 = X86_TYPE_I, .s3 = X86_SIZE_b, \ 171 ## __VA_ARGS__) 172 173/* 174 * Short forms that are mostly useful for ALU opcodes and other 175 * one-byte opcodes. For vector instructions it is usually 176 * clearer to write all three operands explicitly, because the 177 * corresponding gen_* function will use OP_PTRn rather than s->T0 178 * and s->T1. 179 */ 180#define X86_OP_ENTRYrr(op, op0, s0, op1, s1, ...) \ 181 X86_OP_ENTRY3(op, None, None, op0, s0, op1, s1, ## __VA_ARGS__) 182#define X86_OP_ENTRYwr(op, op0, s0, op1, s1, ...) \ 183 X86_OP_ENTRY3(op, op0, s0, None, None, op1, s1, ## __VA_ARGS__) 184#define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \ 185 X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__) 186#define X86_OP_ENTRYw(op, op0, s0, ...) \ 187 X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__) 188#define X86_OP_ENTRYr(op, op0, s0, ...) \ 189 X86_OP_ENTRY3(op, None, None, None, None, op0, s0, ## __VA_ARGS__) 190#define X86_OP_ENTRY1(op, op0, s0, ...) \ 191 X86_OP_ENTRY3(op, op0, s0, 2op, s0, None, None, ## __VA_ARGS__) 192#define X86_OP_ENTRY0(op, ...) \ 193 X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__) 194 195#define cpuid(feat) .cpuid = X86_FEAT_##feat, 196#define noseg .special = X86_SPECIAL_NoSeg, 197#define xchg .special = X86_SPECIAL_Locked, 198#define lock .special = X86_SPECIAL_HasLock, 199#define mmx .special = X86_SPECIAL_MMX, 200#define op0_Rd .special = X86_SPECIAL_Op0_Rd, 201#define op2_Ry .special = X86_SPECIAL_Op2_Ry, 202#define avx_movx .special = X86_SPECIAL_AVXExtMov, 203#define sextT0 .special = X86_SPECIAL_SExtT0, 204#define zextT0 .special = X86_SPECIAL_ZExtT0, 205 206#define vex1 .vex_class = 1, 207#define vex1_rep3 .vex_class = 1, .vex_special = X86_VEX_REPScalar, 208#define vex2 .vex_class = 2, 209#define vex2_rep3 .vex_class = 2, .vex_special = X86_VEX_REPScalar, 210#define vex3 .vex_class = 3, 211#define vex4 .vex_class = 4, 212#define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned, 213#define vex4_rep5 .vex_class = 4, .vex_special = X86_VEX_REPScalar, 214#define vex5 .vex_class = 5, 215#define vex6 .vex_class = 6, 216#define vex7 .vex_class = 7, 217#define vex8 .vex_class = 8, 218#define vex11 .vex_class = 11, 219#define vex12 .vex_class = 12, 220#define vex13 .vex_class = 13, 221 222#define chk(a) .check = X86_CHECK_##a, 223#define svm(a) .intercept = SVM_EXIT_##a, 224 225#define avx2_256 .vex_special = X86_VEX_AVX2_256, 226 227#define P_00 1 228#define P_66 (1 << PREFIX_DATA) 229#define P_F3 (1 << PREFIX_REPZ) 230#define P_F2 (1 << PREFIX_REPNZ) 231 232#define p_00 .valid_prefix = P_00, 233#define p_66 .valid_prefix = P_66, 234#define p_f3 .valid_prefix = P_F3, 235#define p_f2 .valid_prefix = P_F2, 236#define p_00_66 .valid_prefix = P_00 | P_66, 237#define p_00_f3 .valid_prefix = P_00 | P_F3, 238#define p_66_f2 .valid_prefix = P_66 | P_F2, 239#define p_00_66_f3 .valid_prefix = P_00 | P_66 | P_F3, 240#define p_66_f3_f2 .valid_prefix = P_66 | P_F3 | P_F2, 241#define p_00_66_f3_f2 .valid_prefix = P_00 | P_66 | P_F3 | P_F2, 242 243#define UNKNOWN_OPCODE ((X86OpEntry) {}) 244 245static uint8_t get_modrm(DisasContext *s, CPUX86State *env) 246{ 247 if (!s->has_modrm) { 248 s->modrm = x86_ldub_code(env, s); 249 s->has_modrm = true; 250 } 251 return s->modrm; 252} 253 254static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4]) 255{ 256 if (s->prefix & PREFIX_REPNZ) { 257 return &entries[3]; 258 } else if (s->prefix & PREFIX_REPZ) { 259 return &entries[2]; 260 } else if (s->prefix & PREFIX_DATA) { 261 return &entries[1]; 262 } else { 263 return &entries[0]; 264 } 265} 266 267static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 268{ 269 /* only includes ldmxcsr and stmxcsr, because they have AVX variants. */ 270 static const X86OpEntry group15_reg[8] = { 271 }; 272 273 static const X86OpEntry group15_mem[8] = { 274 [2] = X86_OP_ENTRYr(LDMXCSR, E,d, vex5 chk(VEX128)), 275 [3] = X86_OP_ENTRYw(STMXCSR, E,d, vex5 chk(VEX128)), 276 }; 277 278 uint8_t modrm = get_modrm(s, env); 279 if ((modrm >> 6) == 3) { 280 *entry = group15_reg[(modrm >> 3) & 7]; 281 } else { 282 *entry = group15_mem[(modrm >> 3) & 7]; 283 } 284} 285 286static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 287{ 288 static const X86GenFunc group17_gen[8] = { 289 NULL, gen_BLSR, gen_BLSMSK, gen_BLSI, 290 }; 291 int op = (get_modrm(s, env) >> 3) & 7; 292 entry->gen = group17_gen[op]; 293} 294 295static void decode_group12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 296{ 297 static const X86OpEntry opcodes_group12[8] = { 298 {}, 299 {}, 300 X86_OP_ENTRY3(PSRLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 301 {}, 302 X86_OP_ENTRY3(PSRAW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 303 {}, 304 X86_OP_ENTRY3(PSLLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 305 {}, 306 }; 307 308 int op = (get_modrm(s, env) >> 3) & 7; 309 *entry = opcodes_group12[op]; 310} 311 312static void decode_group13(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 313{ 314 static const X86OpEntry opcodes_group13[8] = { 315 {}, 316 {}, 317 X86_OP_ENTRY3(PSRLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 318 {}, 319 X86_OP_ENTRY3(PSRAD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 320 {}, 321 X86_OP_ENTRY3(PSLLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 322 {}, 323 }; 324 325 int op = (get_modrm(s, env) >> 3) & 7; 326 *entry = opcodes_group13[op]; 327} 328 329static void decode_group14(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 330{ 331 static const X86OpEntry opcodes_group14[8] = { 332 /* grp14 */ 333 {}, 334 {}, 335 X86_OP_ENTRY3(PSRLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 336 X86_OP_ENTRY3(PSRLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66), 337 {}, 338 {}, 339 X86_OP_ENTRY3(PSLLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66), 340 X86_OP_ENTRY3(PSLLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66), 341 }; 342 343 int op = (get_modrm(s, env) >> 3) & 7; 344 *entry = opcodes_group14[op]; 345} 346 347static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 348{ 349 static const X86OpEntry opcodes_0F6F[4] = { 350 X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex5 mmx), /* movq */ 351 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */ 352 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */ 353 {}, 354 }; 355 *entry = *decode_by_prefix(s, opcodes_0F6F); 356} 357 358static void decode_0F70(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 359{ 360 static const X86OpEntry pshufw[4] = { 361 X86_OP_ENTRY3(PSHUFW, P,q, Q,q, I,b, vex4 mmx), 362 X86_OP_ENTRY3(PSHUFD, V,x, W,x, I,b, vex4 avx2_256), 363 X86_OP_ENTRY3(PSHUFHW, V,x, W,x, I,b, vex4 avx2_256), 364 X86_OP_ENTRY3(PSHUFLW, V,x, W,x, I,b, vex4 avx2_256), 365 }; 366 367 *entry = *decode_by_prefix(s, pshufw); 368} 369 370static void decode_0F77(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 371{ 372 if (!(s->prefix & PREFIX_VEX)) { 373 entry->gen = gen_EMMS; 374 } else if (!s->vex_l) { 375 entry->gen = gen_VZEROUPPER; 376 entry->vex_class = 8; 377 } else { 378 entry->gen = gen_VZEROALL; 379 entry->vex_class = 8; 380 } 381} 382 383static void decode_0F78(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 384{ 385 static const X86OpEntry opcodes_0F78[4] = { 386 {}, 387 X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), /* AMD extension */ 388 {}, 389 X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)), /* AMD extension */ 390 }; 391 *entry = *decode_by_prefix(s, opcodes_0F78); 392} 393 394static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 395{ 396 if (s->prefix & PREFIX_REPNZ) { 397 entry->gen = gen_INSERTQ_r; /* AMD extension */ 398 } else if (s->prefix & PREFIX_DATA) { 399 entry->gen = gen_EXTRQ_r; /* AMD extension */ 400 } else { 401 entry->gen = NULL; 402 }; 403} 404 405static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 406{ 407 static const X86OpEntry opcodes_0F7E[4] = { 408 X86_OP_ENTRY3(MOVD_from, E,y, None,None, P,y, vex5 mmx), 409 X86_OP_ENTRY3(MOVD_from, E,y, None,None, V,y, vex5), 410 X86_OP_ENTRY3(MOVQ, V,x, None,None, W,q, vex5), /* wrong dest Vy on SDM! */ 411 {}, 412 }; 413 *entry = *decode_by_prefix(s, opcodes_0F7E); 414} 415 416static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 417{ 418 static const X86OpEntry opcodes_0F7F[4] = { 419 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex5 mmx), /* movq */ 420 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */ 421 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* movdqu */ 422 {}, 423 }; 424 *entry = *decode_by_prefix(s, opcodes_0F7F); 425} 426 427static void decode_0FD6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 428{ 429 static const X86OpEntry movq[4] = { 430 {}, 431 X86_OP_ENTRY3(MOVQ, W,x, None, None, V,q, vex5), 432 X86_OP_ENTRY3(MOVq_dq, V,dq, None, None, N,q), 433 X86_OP_ENTRY3(MOVq_dq, P,q, None, None, U,q), 434 }; 435 436 *entry = *decode_by_prefix(s, movq); 437} 438 439static const X86OpEntry opcodes_0F38_00toEF[240] = { 440 [0x00] = X86_OP_ENTRY3(PSHUFB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 441 [0x01] = X86_OP_ENTRY3(PHADDW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 442 [0x02] = X86_OP_ENTRY3(PHADDD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 443 [0x03] = X86_OP_ENTRY3(PHADDSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 444 [0x04] = X86_OP_ENTRY3(PMADDUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 445 [0x05] = X86_OP_ENTRY3(PHSUBW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 446 [0x06] = X86_OP_ENTRY3(PHSUBD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 447 [0x07] = X86_OP_ENTRY3(PHSUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 448 449 [0x10] = X86_OP_ENTRY2(PBLENDVB, V,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 450 [0x13] = X86_OP_ENTRY2(VCVTPH2PS, V,x, W,xh, vex11 chk(W0) cpuid(F16C) p_66), 451 [0x14] = X86_OP_ENTRY2(BLENDVPS, V,x, W,x, vex4 cpuid(SSE41) p_66), 452 [0x15] = X86_OP_ENTRY2(BLENDVPD, V,x, W,x, vex4 cpuid(SSE41) p_66), 453 /* Listed incorrectly as type 4 */ 454 [0x16] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), /* vpermps */ 455 [0x17] = X86_OP_ENTRY3(VPTEST, None,None, V,x, W,x, vex4 cpuid(SSE41) p_66), 456 457 /* 458 * Source operand listed as Mq/Ux and similar in the manual; incorrectly listed 459 * as 128-bit only in 2-17. 460 */ 461 [0x20] = X86_OP_ENTRY3(VPMOVSXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 462 [0x21] = X86_OP_ENTRY3(VPMOVSXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 463 [0x22] = X86_OP_ENTRY3(VPMOVSXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 464 [0x23] = X86_OP_ENTRY3(VPMOVSXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 465 [0x24] = X86_OP_ENTRY3(VPMOVSXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 466 [0x25] = X86_OP_ENTRY3(VPMOVSXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 467 468 /* Same as PMOVSX. */ 469 [0x30] = X86_OP_ENTRY3(VPMOVZXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 470 [0x31] = X86_OP_ENTRY3(VPMOVZXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 471 [0x32] = X86_OP_ENTRY3(VPMOVZXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 472 [0x33] = X86_OP_ENTRY3(VPMOVZXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 473 [0x34] = X86_OP_ENTRY3(VPMOVZXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 474 [0x35] = X86_OP_ENTRY3(VPMOVZXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66), 475 [0x36] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), 476 [0x37] = X86_OP_ENTRY3(PCMPGTQ, V,x, H,x, W,x, vex4 cpuid(SSE42) avx2_256 p_66), 477 478 [0x40] = X86_OP_ENTRY3(PMULLD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 479 [0x41] = X86_OP_ENTRY3(VPHMINPOSUW, V,dq, None,None, W,dq, vex4 cpuid(SSE41) p_66), 480 /* Listed incorrectly as type 4 */ 481 [0x45] = X86_OP_ENTRY3(VPSRLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66), 482 [0x46] = X86_OP_ENTRY3(VPSRAV, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX2) p_66), 483 [0x47] = X86_OP_ENTRY3(VPSLLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66), 484 485 [0x90] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vpgatherdd/q */ 486 [0x91] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vpgatherqd/q */ 487 [0x92] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vgatherdps/d */ 488 [0x93] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vgatherqps/d */ 489 490 /* Should be exception type 2 but they do not have legacy SSE equivalents? */ 491 [0x96] = X86_OP_ENTRY3(VFMADDSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 492 [0x97] = X86_OP_ENTRY3(VFMSUBADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 493 494 [0xa6] = X86_OP_ENTRY3(VFMADDSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 495 [0xa7] = X86_OP_ENTRY3(VFMSUBADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 496 497 [0xb6] = X86_OP_ENTRY3(VFMADDSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 498 [0xb7] = X86_OP_ENTRY3(VFMSUBADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 499 500 [0x08] = X86_OP_ENTRY3(PSIGNB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 501 [0x09] = X86_OP_ENTRY3(PSIGNW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 502 [0x0a] = X86_OP_ENTRY3(PSIGND, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 503 [0x0b] = X86_OP_ENTRY3(PMULHRSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 504 /* Listed incorrectly as type 4 */ 505 [0x0c] = X86_OP_ENTRY3(VPERMILPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_00_66), 506 [0x0d] = X86_OP_ENTRY3(VPERMILPD, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 507 [0x0e] = X86_OP_ENTRY3(VTESTPS, None,None, V,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 508 [0x0f] = X86_OP_ENTRY3(VTESTPD, None,None, V,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 509 510 [0x18] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 chk(W0) cpuid(AVX) p_66), /* vbroadcastss */ 511 [0x19] = X86_OP_ENTRY3(VPBROADCASTQ, V,qq, None,None, W,q, vex6 chk(W0) cpuid(AVX) p_66), /* vbroadcastsd */ 512 [0x1a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 chk(W0) cpuid(AVX) p_66), 513 [0x1c] = X86_OP_ENTRY3(PABSB, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 514 [0x1d] = X86_OP_ENTRY3(PABSW, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 515 [0x1e] = X86_OP_ENTRY3(PABSD, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 516 517 [0x28] = X86_OP_ENTRY3(PMULDQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 518 [0x29] = X86_OP_ENTRY3(PCMPEQQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 519 [0x2a] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex1 cpuid(SSE41) avx2_256 p_66), /* movntdqa */ 520 [0x2b] = X86_OP_ENTRY3(VPACKUSDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 521 [0x2c] = X86_OP_ENTRY3(VMASKMOVPS, V,x, H,x, WM,x, vex6 chk(W0) cpuid(AVX) p_66), 522 [0x2d] = X86_OP_ENTRY3(VMASKMOVPD, V,x, H,x, WM,x, vex6 chk(W0) cpuid(AVX) p_66), 523 /* Incorrectly listed as Mx,Hx,Vx in the manual */ 524 [0x2e] = X86_OP_ENTRY3(VMASKMOVPS_st, M,x, V,x, H,x, vex6 chk(W0) cpuid(AVX) p_66), 525 [0x2f] = X86_OP_ENTRY3(VMASKMOVPD_st, M,x, V,x, H,x, vex6 chk(W0) cpuid(AVX) p_66), 526 527 [0x38] = X86_OP_ENTRY3(PMINSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 528 [0x39] = X86_OP_ENTRY3(PMINSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 529 [0x3a] = X86_OP_ENTRY3(PMINUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 530 [0x3b] = X86_OP_ENTRY3(PMINUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 531 [0x3c] = X86_OP_ENTRY3(PMAXSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 532 [0x3d] = X86_OP_ENTRY3(PMAXSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 533 [0x3e] = X86_OP_ENTRY3(PMAXUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 534 [0x3f] = X86_OP_ENTRY3(PMAXUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 535 536 /* VPBROADCASTQ not listed as W0 in table 2-16 */ 537 [0x58] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 chk(W0) cpuid(AVX2) p_66), 538 [0x59] = X86_OP_ENTRY3(VPBROADCASTQ, V,x, None,None, W,q, vex6 chk(W0) cpuid(AVX2) p_66), 539 [0x5a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 chk(W0) cpuid(AVX2) p_66), 540 541 [0x78] = X86_OP_ENTRY3(VPBROADCASTB, V,x, None,None, W,b, vex6 chk(W0) cpuid(AVX2) p_66), 542 [0x79] = X86_OP_ENTRY3(VPBROADCASTW, V,x, None,None, W,w, vex6 chk(W0) cpuid(AVX2) p_66), 543 544 [0x8c] = X86_OP_ENTRY3(VPMASKMOV, V,x, H,x, WM,x, vex6 cpuid(AVX2) p_66), 545 [0x8e] = X86_OP_ENTRY3(VPMASKMOV_st, M,x, V,x, H,x, vex6 cpuid(AVX2) p_66), 546 547 /* Should be exception type 2 or 3 but they do not have legacy SSE equivalents? */ 548 [0x98] = X86_OP_ENTRY3(VFMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 549 [0x99] = X86_OP_ENTRY3(VFMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 550 [0x9a] = X86_OP_ENTRY3(VFMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 551 [0x9b] = X86_OP_ENTRY3(VFMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 552 [0x9c] = X86_OP_ENTRY3(VFNMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 553 [0x9d] = X86_OP_ENTRY3(VFNMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 554 [0x9e] = X86_OP_ENTRY3(VFNMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 555 [0x9f] = X86_OP_ENTRY3(VFNMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 556 557 [0xa8] = X86_OP_ENTRY3(VFMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 558 [0xa9] = X86_OP_ENTRY3(VFMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 559 [0xaa] = X86_OP_ENTRY3(VFMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 560 [0xab] = X86_OP_ENTRY3(VFMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 561 [0xac] = X86_OP_ENTRY3(VFNMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 562 [0xad] = X86_OP_ENTRY3(VFNMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 563 [0xae] = X86_OP_ENTRY3(VFNMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 564 [0xaf] = X86_OP_ENTRY3(VFNMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 565 566 [0xb8] = X86_OP_ENTRY3(VFMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 567 [0xb9] = X86_OP_ENTRY3(VFMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 568 [0xba] = X86_OP_ENTRY3(VFMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 569 [0xbb] = X86_OP_ENTRY3(VFMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 570 [0xbc] = X86_OP_ENTRY3(VFNMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 571 [0xbd] = X86_OP_ENTRY3(VFNMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 572 [0xbe] = X86_OP_ENTRY3(VFNMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 573 [0xbf] = X86_OP_ENTRY3(VFNMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66), 574 575 [0xc8] = X86_OP_ENTRY2(SHA1NEXTE, V,dq, W,dq, cpuid(SHA_NI)), 576 [0xc9] = X86_OP_ENTRY2(SHA1MSG1, V,dq, W,dq, cpuid(SHA_NI)), 577 [0xca] = X86_OP_ENTRY2(SHA1MSG2, V,dq, W,dq, cpuid(SHA_NI)), 578 [0xcb] = X86_OP_ENTRY2(SHA256RNDS2, V,dq, W,dq, cpuid(SHA_NI)), 579 [0xcc] = X86_OP_ENTRY2(SHA256MSG1, V,dq, W,dq, cpuid(SHA_NI)), 580 [0xcd] = X86_OP_ENTRY2(SHA256MSG2, V,dq, W,dq, cpuid(SHA_NI)), 581 582 [0xdb] = X86_OP_ENTRY3(VAESIMC, V,dq, None,None, W,dq, vex4 cpuid(AES) p_66), 583 [0xdc] = X86_OP_ENTRY3(VAESENC, V,x, H,x, W,x, vex4 cpuid(AES) p_66), 584 [0xdd] = X86_OP_ENTRY3(VAESENCLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66), 585 [0xde] = X86_OP_ENTRY3(VAESDEC, V,x, H,x, W,x, vex4 cpuid(AES) p_66), 586 [0xdf] = X86_OP_ENTRY3(VAESDECLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66), 587 588 /* 589 * REG selects srcdest2 operand, VEX.vvvv selects src3. VEX class not found 590 * in manual, assumed to be 13 from the VEX.L0 constraint. 591 */ 592 [0xe0] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 593 [0xe1] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 594 [0xe2] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 595 [0xe3] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 596 [0xe4] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 597 [0xe5] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 598 [0xe6] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 599 [0xe7] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 600 601 [0xe8] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 602 [0xe9] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 603 [0xea] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 604 [0xeb] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 605 [0xec] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 606 [0xed] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 607 [0xee] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 608 [0xef] = X86_OP_ENTRY3(CMPccXADD, M,y, G,y, B,y, vex13 xchg chk(o64) cpuid(CMPCCXADD) p_66), 609}; 610 611/* five rows for no prefix, 66, F3, F2, 66+F2 */ 612static const X86OpEntry opcodes_0F38_F0toFF[16][5] = { 613 [0] = { 614 X86_OP_ENTRY3(MOVBE, G,y, M,y, None,None, cpuid(MOVBE)), 615 X86_OP_ENTRY3(MOVBE, G,w, M,w, None,None, cpuid(MOVBE)), 616 {}, 617 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)), 618 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)), 619 }, 620 [1] = { 621 X86_OP_ENTRY3(MOVBE, M,y, G,y, None,None, cpuid(MOVBE)), 622 X86_OP_ENTRY3(MOVBE, M,w, G,w, None,None, cpuid(MOVBE)), 623 {}, 624 X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)), 625 X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)), 626 }, 627 [2] = { 628 X86_OP_ENTRY3(ANDN, G,y, B,y, E,y, vex13 cpuid(BMI1)), 629 {}, 630 {}, 631 {}, 632 {}, 633 }, 634 [3] = { 635 X86_OP_GROUP3(group17, B,y, E,y, None,None, vex13 cpuid(BMI1)), 636 {}, 637 {}, 638 {}, 639 {}, 640 }, 641 [5] = { 642 X86_OP_ENTRY3(BZHI, G,y, E,y, B,y, vex13 cpuid(BMI1)), 643 {}, 644 X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 zextT0 cpuid(BMI2)), 645 X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 zextT0 cpuid(BMI2)), 646 {}, 647 }, 648 [6] = { 649 {}, 650 X86_OP_ENTRY2(ADCX, G,y, E,y, cpuid(ADX)), 651 X86_OP_ENTRY2(ADOX, G,y, E,y, cpuid(ADX)), 652 X86_OP_ENTRY3(MULX, /* B,y, */ G,y, E,y, 2,y, vex13 cpuid(BMI2)), 653 {}, 654 }, 655 [7] = { 656 X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 zextT0 cpuid(BMI1)), 657 X86_OP_ENTRY3(SHLX, G,y, E,y, B,y, vex13 cpuid(BMI1)), 658 X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 sextT0 cpuid(BMI1)), 659 X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 zextT0 cpuid(BMI1)), 660 {}, 661 }, 662}; 663 664static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 665{ 666 *b = x86_ldub_code(env, s); 667 if (*b < 0xf0) { 668 *entry = opcodes_0F38_00toEF[*b]; 669 } else { 670 int row = 0; 671 if (s->prefix & PREFIX_REPZ) { 672 /* The REPZ (F3) prefix has priority over 66 */ 673 row = 2; 674 } else { 675 row += s->prefix & PREFIX_REPNZ ? 3 : 0; 676 row += s->prefix & PREFIX_DATA ? 1 : 0; 677 } 678 *entry = opcodes_0F38_F0toFF[*b & 15][row]; 679 } 680} 681 682static void decode_VINSERTPS(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 683{ 684 static const X86OpEntry 685 vinsertps_reg = X86_OP_ENTRY4(VINSERTPS_r, V,dq, H,dq, U,dq, vex5 cpuid(SSE41) p_66), 686 vinsertps_mem = X86_OP_ENTRY4(VINSERTPS_m, V,dq, H,dq, M,d, vex5 cpuid(SSE41) p_66); 687 688 int modrm = get_modrm(s, env); 689 *entry = (modrm >> 6) == 3 ? vinsertps_reg : vinsertps_mem; 690} 691 692static const X86OpEntry opcodes_0F3A[256] = { 693 /* 694 * These are VEX-only, but incorrectly listed in the manual as exception type 4. 695 * Also the "qq" instructions are sometimes omitted by Table 2-17, but are VEX256 696 * only. 697 */ 698 [0x00] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 chk(W1) cpuid(AVX2) p_66), 699 [0x01] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 chk(W1) cpuid(AVX2) p_66), /* VPERMPD */ 700 [0x02] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX2) p_66), /* VPBLENDD */ 701 [0x04] = X86_OP_ENTRY3(VPERMILPS_i, V,x, W,x, I,b, vex6 chk(W0) cpuid(AVX) p_66), 702 [0x05] = X86_OP_ENTRY3(VPERMILPD_i, V,x, W,x, I,b, vex6 chk(W0) cpuid(AVX) p_66), 703 [0x06] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX) p_66), 704 705 [0x14] = X86_OP_ENTRY3(PEXTRB, E,b, V,dq, I,b, vex5 cpuid(SSE41) op0_Rd p_66), 706 [0x15] = X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE41) op0_Rd p_66), 707 [0x16] = X86_OP_ENTRY3(PEXTR, E,y, V,dq, I,b, vex5 cpuid(SSE41) p_66), 708 [0x17] = X86_OP_ENTRY3(VEXTRACTPS, E,d, V,dq, I,b, vex5 cpuid(SSE41) p_66), 709 [0x1d] = X86_OP_ENTRY3(VCVTPS2PH, W,xh, V,x, I,b, vex11 chk(W0) cpuid(F16C) p_66), 710 711 [0x20] = X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE41) op2_Ry p_66), 712 [0x21] = X86_OP_GROUP0(VINSERTPS), 713 [0x22] = X86_OP_ENTRY4(PINSR, V,dq, H,dq, E,y, vex5 cpuid(SSE41) p_66), 714 715 [0x40] = X86_OP_ENTRY4(VDDPS, V,x, H,x, W,x, vex2 cpuid(SSE41) p_66), 716 [0x41] = X86_OP_ENTRY4(VDDPD, V,dq, H,dq, W,dq, vex2 cpuid(SSE41) p_66), 717 [0x42] = X86_OP_ENTRY4(VMPSADBW, V,x, H,x, W,x, vex2 cpuid(SSE41) avx2_256 p_66), 718 [0x44] = X86_OP_ENTRY4(PCLMULQDQ, V,dq, H,dq, W,dq, vex4 cpuid(PCLMULQDQ) p_66), 719 [0x46] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), 720 721 [0x60] = X86_OP_ENTRY4(PCMPESTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66), 722 [0x61] = X86_OP_ENTRY4(PCMPESTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66), 723 [0x62] = X86_OP_ENTRY4(PCMPISTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66), 724 [0x63] = X86_OP_ENTRY4(PCMPISTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66), 725 726 [0x08] = X86_OP_ENTRY3(VROUNDPS, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66), 727 [0x09] = X86_OP_ENTRY3(VROUNDPD, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66), 728 /* 729 * Not listed as four operand in the manual. Also writes and reads 128-bits 730 * from the first two operands due to the V operand picking higher entries of 731 * the H operand; the "Vss,Hss,Wss" description from the manual is incorrect. 732 * For other unary operations such as VSQRTSx this is hidden by the "REPScalar" 733 * value of vex_special, because the table lists the operand types of VSQRTPx. 734 */ 735 [0x0a] = X86_OP_ENTRY4(VROUNDSS, V,x, H,x, W,ss, vex3 cpuid(SSE41) p_66), 736 [0x0b] = X86_OP_ENTRY4(VROUNDSD, V,x, H,x, W,sd, vex3 cpuid(SSE41) p_66), 737 [0x0c] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66), 738 [0x0d] = X86_OP_ENTRY4(VBLENDPD, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66), 739 [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), 740 [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), 741 742 [0x18] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX) p_66), 743 [0x19] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 chk(W0) cpuid(AVX) p_66), 744 745 [0x38] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), 746 [0x39] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 chk(W0) cpuid(AVX2) p_66), 747 748 /* Listed incorrectly as type 4 */ 749 [0x4a] = X86_OP_ENTRY4(VBLENDVPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 750 [0x4b] = X86_OP_ENTRY4(VBLENDVPD, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66), 751 [0x4c] = X86_OP_ENTRY4(VPBLENDVB, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66 avx2_256), 752 753 [0xcc] = X86_OP_ENTRY3(SHA1RNDS4, V,dq, W,dq, I,b, cpuid(SHA_NI)), 754 755 [0xdf] = X86_OP_ENTRY3(VAESKEYGEN, V,dq, W,dq, I,b, vex4 cpuid(AES) p_66), 756 757 [0xF0] = X86_OP_ENTRY3(RORX, G,y, E,y, I,b, vex13 cpuid(BMI2) p_f2), 758}; 759 760static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 761{ 762 *b = x86_ldub_code(env, s); 763 *entry = opcodes_0F3A[*b]; 764} 765 766/* 767 * There are some mistakes in the operands in the manual, and the load/store/register 768 * cases are easiest to keep separate, so the entries for 10-17 follow simplicity and 769 * efficiency of implementation rather than copying what the manual says. 770 * 771 * In particular: 772 * 773 * 1) "VMOVSS m32, xmm1" and "VMOVSD m64, xmm1" do not support VEX.vvvv != 1111b, 774 * but this is not mentioned in the tables. 775 * 776 * 2) MOVHLPS, MOVHPS, MOVHPD, MOVLPD, MOVLPS read the high quadword of one of their 777 * operands, which must therefore be dq; MOVLPD and MOVLPS also write the high 778 * quadword of the V operand. 779 */ 780static void decode_0F10(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 781{ 782 static const X86OpEntry opcodes_0F10_reg[4] = { 783 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */ 784 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */ 785 X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex5), 786 X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex5), /* MOVSD */ 787 }; 788 789 static const X86OpEntry opcodes_0F10_mem[4] = { 790 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */ 791 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */ 792 X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex5), 793 X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex5), 794 }; 795 796 if ((get_modrm(s, env) >> 6) == 3) { 797 *entry = *decode_by_prefix(s, opcodes_0F10_reg); 798 } else { 799 *entry = *decode_by_prefix(s, opcodes_0F10_mem); 800 } 801} 802 803static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 804{ 805 static const X86OpEntry opcodes_0F11_reg[4] = { 806 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ 807 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ 808 X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5), 809 X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */ 810 }; 811 812 static const X86OpEntry opcodes_0F11_mem[4] = { 813 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ 814 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ 815 X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5), 816 X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */ 817 }; 818 819 if ((get_modrm(s, env) >> 6) == 3) { 820 *entry = *decode_by_prefix(s, opcodes_0F11_reg); 821 } else { 822 *entry = *decode_by_prefix(s, opcodes_0F11_mem); 823 } 824} 825 826static void decode_0F12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 827{ 828 static const X86OpEntry opcodes_0F12_mem[4] = { 829 /* 830 * Use dq for operand for compatibility with gen_MOVSD and 831 * to allow VEX128 only. 832 */ 833 X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPS */ 834 X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPD */ 835 X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)), 836 X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex5 cpuid(SSE3)), /* qq if VEX.256 */ 837 }; 838 static const X86OpEntry opcodes_0F12_reg[4] = { 839 X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex7), 840 X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex5), /* MOVLPD */ 841 X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)), 842 X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex5 cpuid(SSE3)), 843 }; 844 845 if ((get_modrm(s, env) >> 6) == 3) { 846 *entry = *decode_by_prefix(s, opcodes_0F12_reg); 847 } else { 848 *entry = *decode_by_prefix(s, opcodes_0F12_mem); 849 if ((s->prefix & PREFIX_REPNZ) && s->vex_l) { 850 entry->s2 = X86_SIZE_qq; 851 } 852 } 853} 854 855static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 856{ 857 static const X86OpEntry opcodes_0F16_mem[4] = { 858 /* 859 * Operand 1 technically only reads the low 64 bits, but uses dq so that 860 * it is easier to check for op0 == op1 in an endianness-neutral manner. 861 */ 862 X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPS */ 863 X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPD */ 864 X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)), 865 {}, 866 }; 867 static const X86OpEntry opcodes_0F16_reg[4] = { 868 /* Same as above, operand 1 could be Hq if it wasn't for big-endian. */ 869 X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex7), 870 X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex5), /* MOVHPD */ 871 X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)), 872 {}, 873 }; 874 875 if ((get_modrm(s, env) >> 6) == 3) { 876 *entry = *decode_by_prefix(s, opcodes_0F16_reg); 877 } else { 878 *entry = *decode_by_prefix(s, opcodes_0F16_mem); 879 } 880} 881 882static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 883{ 884 static const X86OpEntry opcodes_0F2A[4] = { 885 X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q), 886 X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q), 887 X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3), 888 X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3), 889 }; 890 *entry = *decode_by_prefix(s, opcodes_0F2A); 891} 892 893static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 894{ 895 static const X86OpEntry opcodes_0F2B[4] = { 896 X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPS */ 897 X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPD */ 898 /* AMD extensions */ 899 X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSS */ 900 X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSD */ 901 }; 902 903 *entry = *decode_by_prefix(s, opcodes_0F2B); 904} 905 906static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 907{ 908 static const X86OpEntry opcodes_0F2C[4] = { 909 /* Listed as ps/pd in the manual, but CVTTPS2PI only reads 64-bit. */ 910 X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,q), 911 X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,dq), 912 X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,ss, vex3), 913 X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,sd, vex3), 914 }; 915 *entry = *decode_by_prefix(s, opcodes_0F2C); 916} 917 918static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 919{ 920 static const X86OpEntry opcodes_0F2D[4] = { 921 /* Listed as ps/pd in the manual, but CVTPS2PI only reads 64-bit. */ 922 X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,q), 923 X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,dq), 924 X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,ss, vex3), 925 X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,sd, vex3), 926 }; 927 *entry = *decode_by_prefix(s, opcodes_0F2D); 928} 929 930static void decode_VxCOMISx(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 931{ 932 /* 933 * VUCOMISx and VCOMISx are different and use no-prefix and 0x66 for SS and SD 934 * respectively. Scalar values usually are associated with 0xF2 and 0xF3, for 935 * which X86_VEX_REPScalar exists, but here it has to be decoded by hand. 936 */ 937 entry->s1 = entry->s2 = (s->prefix & PREFIX_DATA ? X86_SIZE_sd : X86_SIZE_ss); 938 entry->gen = (*b == 0x2E ? gen_VUCOMI : gen_VCOMI); 939} 940 941static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 942{ 943 if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) { 944 entry->op1 = X86_TYPE_None; 945 entry->s1 = X86_SIZE_None; 946 } 947 switch (*b) { 948 case 0x51: entry->gen = gen_VSQRT; break; 949 case 0x52: entry->gen = gen_VRSQRT; break; 950 case 0x53: entry->gen = gen_VRCP; break; 951 } 952} 953 954static void decode_0F5A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 955{ 956 static const X86OpEntry opcodes_0F5A[4] = { 957 X86_OP_ENTRY2(VCVTPS2PD, V,x, W,xh, vex2), /* VCVTPS2PD */ 958 X86_OP_ENTRY2(VCVTPD2PS, V,x, W,x, vex2), /* VCVTPD2PS */ 959 X86_OP_ENTRY3(VCVTSS2SD, V,x, H,x, W,x, vex2_rep3), /* VCVTSS2SD */ 960 X86_OP_ENTRY3(VCVTSD2SS, V,x, H,x, W,x, vex2_rep3), /* VCVTSD2SS */ 961 }; 962 *entry = *decode_by_prefix(s, opcodes_0F5A); 963} 964 965static void decode_0F5B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 966{ 967 static const X86OpEntry opcodes_0F5B[4] = { 968 X86_OP_ENTRY2(VCVTDQ2PS, V,x, W,x, vex2), 969 X86_OP_ENTRY2(VCVTPS2DQ, V,x, W,x, vex2), 970 X86_OP_ENTRY2(VCVTTPS2DQ, V,x, W,x, vex2), 971 {}, 972 }; 973 *entry = *decode_by_prefix(s, opcodes_0F5B); 974} 975 976static void decode_0FE6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 977{ 978 static const X86OpEntry opcodes_0FE6[4] = { 979 {}, 980 X86_OP_ENTRY2(VCVTTPD2DQ, V,x, W,x, vex2), 981 X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex5), 982 X86_OP_ENTRY2(VCVTPD2DQ, V,x, W,x, vex2), 983 }; 984 *entry = *decode_by_prefix(s, opcodes_0FE6); 985} 986 987static const X86OpEntry opcodes_0F[256] = { 988 [0x0E] = X86_OP_ENTRY0(EMMS, cpuid(3DNOW)), /* femms */ 989 /* 990 * 3DNow!'s opcode byte comes *after* modrm and displacements, making it 991 * more like an Ib operand. Dispatch to the right helper in a single gen_* 992 * function. 993 */ 994 [0x0F] = X86_OP_ENTRY3(3dnow, P,q, Q,q, I,b, cpuid(3DNOW)), 995 996 [0x10] = X86_OP_GROUP0(0F10), 997 [0x11] = X86_OP_GROUP0(0F11), 998 [0x12] = X86_OP_GROUP0(0F12), 999 [0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex5 p_00_66), 1000 [0x14] = X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_66), 1001 [0x15] = X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_66), 1002 [0x16] = X86_OP_GROUP0(0F16), 1003 /* Incorrectly listed as Mq,Vq in the manual */ 1004 [0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_66), 1005 1006 [0x40] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1007 [0x41] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1008 [0x42] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1009 [0x43] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1010 [0x44] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1011 [0x45] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1012 [0x46] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1013 [0x47] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1014 1015 [0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66), 1016 [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), /* sqrtps */ 1017 [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rsqrtps */ 1018 [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rcpps */ 1019 [0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand */ 1020 [0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn */ 1021 [0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */ 1022 [0x57] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 p_00_66), /* vxor */ 1023 1024 [0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1025 [0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1026 [0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1027 [0x63] = X86_OP_ENTRY3(PACKSSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1028 [0x64] = X86_OP_ENTRY3(PCMPGTB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1029 [0x65] = X86_OP_ENTRY3(PCMPGTW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1030 [0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1031 [0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1032 1033 [0x70] = X86_OP_GROUP0(0F70), 1034 [0x71] = X86_OP_GROUP0(group12), 1035 [0x72] = X86_OP_GROUP0(group13), 1036 [0x73] = X86_OP_GROUP0(group14), 1037 [0x74] = X86_OP_ENTRY3(PCMPEQB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1038 [0x75] = X86_OP_ENTRY3(PCMPEQW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1039 [0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1040 [0x77] = X86_OP_GROUP0(0F77), 1041 1042 [0x80] = X86_OP_ENTRYr(Jcc, J,z_f64), 1043 [0x81] = X86_OP_ENTRYr(Jcc, J,z_f64), 1044 [0x82] = X86_OP_ENTRYr(Jcc, J,z_f64), 1045 [0x83] = X86_OP_ENTRYr(Jcc, J,z_f64), 1046 [0x84] = X86_OP_ENTRYr(Jcc, J,z_f64), 1047 [0x85] = X86_OP_ENTRYr(Jcc, J,z_f64), 1048 [0x86] = X86_OP_ENTRYr(Jcc, J,z_f64), 1049 [0x87] = X86_OP_ENTRYr(Jcc, J,z_f64), 1050 1051 [0x90] = X86_OP_ENTRYw(SETcc, E,b), 1052 [0x91] = X86_OP_ENTRYw(SETcc, E,b), 1053 [0x92] = X86_OP_ENTRYw(SETcc, E,b), 1054 [0x93] = X86_OP_ENTRYw(SETcc, E,b), 1055 [0x94] = X86_OP_ENTRYw(SETcc, E,b), 1056 [0x95] = X86_OP_ENTRYw(SETcc, E,b), 1057 [0x96] = X86_OP_ENTRYw(SETcc, E,b), 1058 [0x97] = X86_OP_ENTRYw(SETcc, E,b), 1059 1060 [0xa0] = X86_OP_ENTRYr(PUSH, FS, w), 1061 [0xa1] = X86_OP_ENTRYw(POP, FS, w), 1062 1063 [0x0b] = X86_OP_ENTRY0(UD), /* UD2 */ 1064 [0x0d] = X86_OP_ENTRY1(NOP, M,v), /* 3DNow! prefetch */ 1065 1066 [0x18] = X86_OP_ENTRY1(NOP, nop,v), /* prefetch/reserved NOP */ 1067 [0x19] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ 1068 [0x1c] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ 1069 [0x1d] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ 1070 [0x1e] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ 1071 [0x1f] = X86_OP_ENTRY1(NOP, nop,v), /* NOP/reserved NOP */ 1072 1073 [0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */ 1074 [0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */ 1075 [0x2A] = X86_OP_GROUP0(0F2A), 1076 [0x2B] = X86_OP_GROUP0(0F2B), 1077 [0x2C] = X86_OP_GROUP0(0F2C), 1078 [0x2D] = X86_OP_GROUP0(0F2D), 1079 [0x2E] = X86_OP_GROUP3(VxCOMISx, None,None, V,x, W,x, vex3 p_00_66), /* VUCOMISS/SD */ 1080 [0x2F] = X86_OP_GROUP3(VxCOMISx, None,None, V,x, W,x, vex3 p_00_66), /* VCOMISS/SD */ 1081 1082 [0x38] = X86_OP_GROUP0(0F38), 1083 [0x3a] = X86_OP_GROUP0(0F3A), 1084 1085 [0x48] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1086 [0x49] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1087 [0x4a] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1088 [0x4b] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1089 [0x4c] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1090 [0x4d] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1091 [0x4e] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1092 [0x4f] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), 1093 1094 [0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1095 [0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1096 [0x5a] = X86_OP_GROUP0(0F5A), 1097 [0x5b] = X86_OP_GROUP0(0F5B), 1098 [0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1099 [0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1100 [0x5e] = X86_OP_ENTRY3(VDIV, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1101 [0x5f] = X86_OP_ENTRY3(VMAX, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1102 1103 [0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1104 [0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1105 [0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1106 [0x6b] = X86_OP_ENTRY3(PACKSSDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1107 [0x6c] = X86_OP_ENTRY3(PUNPCKLQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256), 1108 [0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256), 1109 [0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */ 1110 [0x6f] = X86_OP_GROUP0(0F6F), 1111 1112 [0x78] = X86_OP_GROUP0(0F78), 1113 [0x79] = X86_OP_GROUP2(0F79, V,x, U,x, cpuid(SSE4A)), 1114 [0x7c] = X86_OP_ENTRY3(VHADD, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2), 1115 [0x7d] = X86_OP_ENTRY3(VHSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2), 1116 [0x7e] = X86_OP_GROUP0(0F7E), 1117 [0x7f] = X86_OP_GROUP0(0F7F), 1118 1119 [0x88] = X86_OP_ENTRYr(Jcc, J,z_f64), 1120 [0x89] = X86_OP_ENTRYr(Jcc, J,z_f64), 1121 [0x8a] = X86_OP_ENTRYr(Jcc, J,z_f64), 1122 [0x8b] = X86_OP_ENTRYr(Jcc, J,z_f64), 1123 [0x8c] = X86_OP_ENTRYr(Jcc, J,z_f64), 1124 [0x8d] = X86_OP_ENTRYr(Jcc, J,z_f64), 1125 [0x8e] = X86_OP_ENTRYr(Jcc, J,z_f64), 1126 [0x8f] = X86_OP_ENTRYr(Jcc, J,z_f64), 1127 1128 [0x98] = X86_OP_ENTRYw(SETcc, E,b), 1129 [0x99] = X86_OP_ENTRYw(SETcc, E,b), 1130 [0x9a] = X86_OP_ENTRYw(SETcc, E,b), 1131 [0x9b] = X86_OP_ENTRYw(SETcc, E,b), 1132 [0x9c] = X86_OP_ENTRYw(SETcc, E,b), 1133 [0x9d] = X86_OP_ENTRYw(SETcc, E,b), 1134 [0x9e] = X86_OP_ENTRYw(SETcc, E,b), 1135 [0x9f] = X86_OP_ENTRYw(SETcc, E,b), 1136 1137 [0xa8] = X86_OP_ENTRYr(PUSH, GS, w), 1138 [0xa9] = X86_OP_ENTRYw(POP, GS, w), 1139 [0xae] = X86_OP_GROUP0(group15), 1140 /* 1141 * It's slightly more efficient to put Ev operand in T0 and allow gen_IMUL3 1142 * to assume sextT0. Multiplication is commutative anyway. 1143 */ 1144 [0xaf] = X86_OP_ENTRY3(IMUL3, G,v, E,v, 2op,v, sextT0), 1145 1146 [0xb2] = X86_OP_ENTRY3(LSS, G,v, EM,p, None, None), 1147 [0xb4] = X86_OP_ENTRY3(LFS, G,v, EM,p, None, None), 1148 [0xb5] = X86_OP_ENTRY3(LGS, G,v, EM,p, None, None), 1149 [0xb6] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, zextT0), /* MOVZX */ 1150 [0xb7] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, zextT0), /* MOVZX */ 1151 1152 /* decoded as modrm, which is visible as a difference between page fault and #UD */ 1153 [0xb9] = X86_OP_ENTRYr(UD, nop,v), /* UD1 */ 1154 [0xbe] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, sextT0), /* MOVSX */ 1155 [0xbf] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, sextT0), /* MOVSX */ 1156 1157 [0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), 1158 [0xc3] = X86_OP_ENTRY3(MOV, EM,y,G,y, None,None, cpuid(SSE2)), /* MOVNTI */ 1159 [0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66), 1160 [0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66), 1161 [0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66), 1162 1163 [0xc8] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1164 [0xc9] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1165 [0xca] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1166 [0xcb] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1167 [0xcc] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1168 [0xcd] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1169 [0xce] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1170 [0xcf] = X86_OP_ENTRY1(BSWAP, LoBits,y), 1171 1172 [0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2), 1173 [0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1174 [0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1175 [0xd3] = X86_OP_ENTRY3(PSRLQ_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1176 [0xd4] = X86_OP_ENTRY3(PADDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1177 [0xd5] = X86_OP_ENTRY3(PMULLW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1178 [0xd6] = X86_OP_GROUP0(0FD6), 1179 [0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256 p_00_66), 1180 1181 [0xe0] = X86_OP_ENTRY3(PAVGB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1182 [0xe1] = X86_OP_ENTRY3(PSRAW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1183 [0xe2] = X86_OP_ENTRY3(PSRAD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1184 [0xe3] = X86_OP_ENTRY3(PAVGW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1185 [0xe4] = X86_OP_ENTRY3(PMULHUW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1186 [0xe5] = X86_OP_ENTRY3(PMULHW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1187 [0xe6] = X86_OP_GROUP0(0FE6), 1188 [0xe7] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx p_00_66), /* MOVNTQ/MOVNTDQ */ 1189 1190 [0xf0] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex4_unal cpuid(SSE3) p_f2), /* LDDQU */ 1191 [0xf1] = X86_OP_ENTRY3(PSLLW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1192 [0xf2] = X86_OP_ENTRY3(PSLLD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1193 [0xf3] = X86_OP_ENTRY3(PSLLQ_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66), 1194 [0xf4] = X86_OP_ENTRY3(PMULUDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1195 [0xf5] = X86_OP_ENTRY3(PMADDWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1196 [0xf6] = X86_OP_ENTRY3(PSADBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1197 [0xf7] = X86_OP_ENTRY3(MASKMOV, None,None, V,dq, U,dq, vex4_unal avx2_256 mmx p_00_66), 1198 1199 /* Incorrectly missing from 2-17 */ 1200 [0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1201 [0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1202 [0xda] = X86_OP_ENTRY3(PMINUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1203 [0xdb] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1204 [0xdc] = X86_OP_ENTRY3(PADDUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1205 [0xdd] = X86_OP_ENTRY3(PADDUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1206 [0xde] = X86_OP_ENTRY3(PMAXUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1207 [0xdf] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1208 1209 [0xe8] = X86_OP_ENTRY3(PSUBSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1210 [0xe9] = X86_OP_ENTRY3(PSUBSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1211 [0xea] = X86_OP_ENTRY3(PMINSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1212 [0xeb] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1213 [0xec] = X86_OP_ENTRY3(PADDSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1214 [0xed] = X86_OP_ENTRY3(PADDSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1215 [0xee] = X86_OP_ENTRY3(PMAXSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1216 [0xef] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1217 1218 [0xf8] = X86_OP_ENTRY3(PSUBB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1219 [0xf9] = X86_OP_ENTRY3(PSUBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1220 [0xfa] = X86_OP_ENTRY3(PSUBD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1221 [0xfb] = X86_OP_ENTRY3(PSUBQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1222 [0xfc] = X86_OP_ENTRY3(PADDB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1223 [0xfd] = X86_OP_ENTRY3(PADDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1224 [0xfe] = X86_OP_ENTRY3(PADDD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66), 1225 [0xff] = X86_OP_ENTRYr(UD, nop,v), /* UD0 */ 1226}; 1227 1228static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1229{ 1230 *entry = opcodes_0F[*b]; 1231} 1232 1233static void decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1234{ 1235 *b = x86_ldub_code(env, s); 1236 do_decode_0F(s, env, entry, b); 1237} 1238 1239static void decode_63(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1240{ 1241 static const X86OpEntry arpl = X86_OP_ENTRY2(ARPL, E,w, G,w, chk(prot)); 1242 static const X86OpEntry mov = X86_OP_ENTRY3(MOV, G,v, E,v, None, None); 1243 static const X86OpEntry movsxd = X86_OP_ENTRY3(MOV, G,v, E,d, None, None, sextT0); 1244 if (!CODE64(s)) { 1245 *entry = arpl; 1246 } else if (REX_W(s)) { 1247 *entry = movsxd; 1248 } else { 1249 *entry = mov; 1250 } 1251} 1252 1253static void decode_group1(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1254{ 1255 static const X86GenFunc group1_gen[8] = { 1256 gen_ADD, gen_OR, gen_ADC, gen_SBB, gen_AND, gen_SUB, gen_XOR, gen_SUB, 1257 }; 1258 int op = (get_modrm(s, env) >> 3) & 7; 1259 entry->gen = group1_gen[op]; 1260 1261 if (op == 7) { 1262 /* prevent writeback for CMP */ 1263 entry->op1 = entry->op0; 1264 entry->op0 = X86_TYPE_None; 1265 entry->s0 = X86_SIZE_None; 1266 } else { 1267 entry->special = X86_SPECIAL_HasLock; 1268 } 1269} 1270 1271static void decode_group1A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1272{ 1273 int op = (get_modrm(s, env) >> 3) & 7; 1274 if (op != 0) { 1275 /* could be XOP prefix too */ 1276 *entry = UNKNOWN_OPCODE; 1277 } else { 1278 entry->gen = gen_POP; 1279 /* The address must use the value of ESP after the pop. */ 1280 s->popl_esp_hack = 1 << mo_pushpop(s, s->dflag); 1281 } 1282} 1283 1284static void decode_group2(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1285{ 1286 static const X86GenFunc group2_gen[8] = { 1287 gen_ROL, gen_ROR, gen_RCL, gen_RCR, 1288 gen_SHL, gen_SHR, gen_SHL /* SAL, undocumented */, gen_SAR, 1289 }; 1290 int op = (get_modrm(s, env) >> 3) & 7; 1291 entry->gen = group2_gen[op]; 1292 if (op == 7) { 1293 entry->special = X86_SPECIAL_SExtT0; 1294 } else { 1295 entry->special = X86_SPECIAL_ZExtT0; 1296 } 1297} 1298 1299static void decode_group3(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1300{ 1301 static const X86OpEntry opcodes_grp3[16] = { 1302 /* 0xf6 */ 1303 [0x00] = X86_OP_ENTRYrr(AND, E,b, I,b), 1304 [0x02] = X86_OP_ENTRY1(NOT, E,b, lock), 1305 [0x03] = X86_OP_ENTRY1(NEG, E,b, lock), 1306 [0x04] = X86_OP_ENTRYrr(MUL, E,b, 0,b, zextT0), 1307 [0x05] = X86_OP_ENTRYrr(IMUL,E,b, 0,b, sextT0), 1308 [0x06] = X86_OP_ENTRYr(DIV, E,b), 1309 [0x07] = X86_OP_ENTRYr(IDIV, E,b), 1310 1311 /* 0xf7 */ 1312 [0x08] = X86_OP_ENTRYrr(AND, E,v, I,z), 1313 [0x0a] = X86_OP_ENTRY1(NOT, E,v, lock), 1314 [0x0b] = X86_OP_ENTRY1(NEG, E,v, lock), 1315 [0x0c] = X86_OP_ENTRYrr(MUL, E,v, 0,v, zextT0), 1316 [0x0d] = X86_OP_ENTRYrr(IMUL,E,v, 0,v, sextT0), 1317 [0x0e] = X86_OP_ENTRYr(DIV, E,v), 1318 [0x0f] = X86_OP_ENTRYr(IDIV, E,v), 1319 }; 1320 1321 int w = (*b & 1); 1322 int reg = (get_modrm(s, env) >> 3) & 7; 1323 1324 *entry = opcodes_grp3[(w << 3) | reg]; 1325} 1326 1327static void decode_group4_5(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1328{ 1329 static const X86OpEntry opcodes_grp4_5[16] = { 1330 /* 0xfe */ 1331 [0x00] = X86_OP_ENTRY1(INC, E,b, lock), 1332 [0x01] = X86_OP_ENTRY1(DEC, E,b, lock), 1333 1334 /* 0xff */ 1335 [0x08] = X86_OP_ENTRY1(INC, E,v, lock), 1336 [0x09] = X86_OP_ENTRY1(DEC, E,v, lock), 1337 [0x0a] = X86_OP_ENTRY3(CALL_m, None, None, E,f64, None, None, zextT0), 1338 [0x0b] = X86_OP_ENTRYr(CALLF_m, M,p), 1339 [0x0c] = X86_OP_ENTRY3(JMP_m, None, None, E,f64, None, None, zextT0), 1340 [0x0d] = X86_OP_ENTRYr(JMPF_m, M,p), 1341 [0x0e] = X86_OP_ENTRYr(PUSH, E,f64), 1342 }; 1343 1344 int w = (*b & 1); 1345 int reg = (get_modrm(s, env) >> 3) & 7; 1346 1347 *entry = opcodes_grp4_5[(w << 3) | reg]; 1348} 1349 1350 1351static void decode_group11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1352{ 1353 int op = (get_modrm(s, env) >> 3) & 7; 1354 if (op != 0) { 1355 *entry = UNKNOWN_OPCODE; 1356 } else { 1357 entry->gen = gen_MOV; 1358 } 1359} 1360 1361static const X86OpEntry opcodes_root[256] = { 1362 [0x00] = X86_OP_ENTRY2(ADD, E,b, G,b, lock), 1363 [0x01] = X86_OP_ENTRY2(ADD, E,v, G,v, lock), 1364 [0x02] = X86_OP_ENTRY2(ADD, G,b, E,b, lock), 1365 [0x03] = X86_OP_ENTRY2(ADD, G,v, E,v, lock), 1366 [0x04] = X86_OP_ENTRY2(ADD, 0,b, I,b, lock), /* AL, Ib */ 1367 [0x05] = X86_OP_ENTRY2(ADD, 0,v, I,z, lock), /* rAX, Iz */ 1368 [0x06] = X86_OP_ENTRYr(PUSH, ES, w, chk(i64)), 1369 [0x07] = X86_OP_ENTRYw(POP, ES, w, chk(i64)), 1370 1371 [0x10] = X86_OP_ENTRY2(ADC, E,b, G,b, lock), 1372 [0x11] = X86_OP_ENTRY2(ADC, E,v, G,v, lock), 1373 [0x12] = X86_OP_ENTRY2(ADC, G,b, E,b, lock), 1374 [0x13] = X86_OP_ENTRY2(ADC, G,v, E,v, lock), 1375 [0x14] = X86_OP_ENTRY2(ADC, 0,b, I,b, lock), /* AL, Ib */ 1376 [0x15] = X86_OP_ENTRY2(ADC, 0,v, I,z, lock), /* rAX, Iz */ 1377 [0x16] = X86_OP_ENTRYr(PUSH, SS, w, chk(i64)), 1378 [0x17] = X86_OP_ENTRYw(POP, SS, w, chk(i64)), 1379 1380 [0x20] = X86_OP_ENTRY2(AND, E,b, G,b, lock), 1381 [0x21] = X86_OP_ENTRY2(AND, E,v, G,v, lock), 1382 [0x22] = X86_OP_ENTRY2(AND, G,b, E,b, lock), 1383 [0x23] = X86_OP_ENTRY2(AND, G,v, E,v, lock), 1384 [0x24] = X86_OP_ENTRY2(AND, 0,b, I,b, lock), /* AL, Ib */ 1385 [0x25] = X86_OP_ENTRY2(AND, 0,v, I,z, lock), /* rAX, Iz */ 1386 [0x26] = {}, 1387 [0x27] = X86_OP_ENTRY0(DAA, chk(i64)), 1388 1389 [0x30] = X86_OP_ENTRY2(XOR, E,b, G,b, lock), 1390 [0x31] = X86_OP_ENTRY2(XOR, E,v, G,v, lock), 1391 [0x32] = X86_OP_ENTRY2(XOR, G,b, E,b, lock), 1392 [0x33] = X86_OP_ENTRY2(XOR, G,v, E,v, lock), 1393 [0x34] = X86_OP_ENTRY2(XOR, 0,b, I,b, lock), /* AL, Ib */ 1394 [0x35] = X86_OP_ENTRY2(XOR, 0,v, I,z, lock), /* rAX, Iz */ 1395 [0x36] = {}, 1396 [0x37] = X86_OP_ENTRY0(AAA, chk(i64)), 1397 1398 [0x40] = X86_OP_ENTRY1(INC, 0,v, chk(i64)), 1399 [0x41] = X86_OP_ENTRY1(INC, 1,v, chk(i64)), 1400 [0x42] = X86_OP_ENTRY1(INC, 2,v, chk(i64)), 1401 [0x43] = X86_OP_ENTRY1(INC, 3,v, chk(i64)), 1402 [0x44] = X86_OP_ENTRY1(INC, 4,v, chk(i64)), 1403 [0x45] = X86_OP_ENTRY1(INC, 5,v, chk(i64)), 1404 [0x46] = X86_OP_ENTRY1(INC, 6,v, chk(i64)), 1405 [0x47] = X86_OP_ENTRY1(INC, 7,v, chk(i64)), 1406 1407 [0x50] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1408 [0x51] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1409 [0x52] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1410 [0x53] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1411 [0x54] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1412 [0x55] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1413 [0x56] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1414 [0x57] = X86_OP_ENTRYr(PUSH, LoBits,d64), 1415 1416 [0x60] = X86_OP_ENTRY0(PUSHA, chk(i64)), 1417 [0x61] = X86_OP_ENTRY0(POPA, chk(i64)), 1418 [0x62] = X86_OP_ENTRYrr(BOUND, G,v, M,a, chk(i64)), 1419 [0x63] = X86_OP_GROUP0(63), 1420 [0x64] = {}, 1421 [0x65] = {}, 1422 [0x66] = {}, 1423 [0x67] = {}, 1424 1425 [0x70] = X86_OP_ENTRYr(Jcc, J,b), 1426 [0x71] = X86_OP_ENTRYr(Jcc, J,b), 1427 [0x72] = X86_OP_ENTRYr(Jcc, J,b), 1428 [0x73] = X86_OP_ENTRYr(Jcc, J,b), 1429 [0x74] = X86_OP_ENTRYr(Jcc, J,b), 1430 [0x75] = X86_OP_ENTRYr(Jcc, J,b), 1431 [0x76] = X86_OP_ENTRYr(Jcc, J,b), 1432 [0x77] = X86_OP_ENTRYr(Jcc, J,b), 1433 1434 [0x80] = X86_OP_GROUP2(group1, E,b, I,b), 1435 [0x81] = X86_OP_GROUP2(group1, E,v, I,z), 1436 [0x82] = X86_OP_GROUP2(group1, E,b, I,b, chk(i64)), 1437 [0x83] = X86_OP_GROUP2(group1, E,v, I,b), 1438 [0x84] = X86_OP_ENTRYrr(AND, E,b, G,b), 1439 [0x85] = X86_OP_ENTRYrr(AND, E,v, G,v), 1440 [0x86] = X86_OP_ENTRY2(XCHG, E,b, G,b, xchg), 1441 [0x87] = X86_OP_ENTRY2(XCHG, E,v, G,v, xchg), 1442 1443 [0x90] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1444 [0x91] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1445 [0x92] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1446 [0x93] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1447 [0x94] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1448 [0x95] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1449 [0x96] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1450 [0x97] = X86_OP_ENTRY2(XCHG, 0,v, LoBits,v), 1451 1452 [0xA0] = X86_OP_ENTRY3(MOV, 0,b, O,b, None, None), /* AL, Ob */ 1453 [0xA1] = X86_OP_ENTRY3(MOV, 0,v, O,v, None, None), /* rAX, Ov */ 1454 [0xA2] = X86_OP_ENTRY3(MOV, O,b, 0,b, None, None), /* Ob, AL */ 1455 [0xA3] = X86_OP_ENTRY3(MOV, O,v, 0,v, None, None), /* Ov, rAX */ 1456 [0xA4] = X86_OP_ENTRYrr(MOVS, Y,b, X,b), 1457 [0xA5] = X86_OP_ENTRYrr(MOVS, Y,v, X,v), 1458 [0xA6] = X86_OP_ENTRYrr(CMPS, Y,b, X,b), 1459 [0xA7] = X86_OP_ENTRYrr(CMPS, Y,v, X,v), 1460 1461 [0xB0] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1462 [0xB1] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1463 [0xB2] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1464 [0xB3] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1465 [0xB4] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1466 [0xB5] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1467 [0xB6] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1468 [0xB7] = X86_OP_ENTRY3(MOV, LoBits,b, I,b, None, None), 1469 1470 [0xC0] = X86_OP_GROUP2(group2, E,b, I,b), 1471 [0xC1] = X86_OP_GROUP2(group2, E,v, I,b), 1472 [0xC2] = X86_OP_ENTRYr(RET, I,w), 1473 [0xC3] = X86_OP_ENTRY0(RET), 1474 [0xC4] = X86_OP_ENTRY3(LES, G,z, EM,p, None, None, chk(i64)), 1475 [0xC5] = X86_OP_ENTRY3(LDS, G,z, EM,p, None, None, chk(i64)), 1476 [0xC6] = X86_OP_GROUP3(group11, E,b, I,b, None, None), /* reg=000b */ 1477 [0xC7] = X86_OP_GROUP3(group11, E,v, I,z, None, None), /* reg=000b */ 1478 1479 [0xD0] = X86_OP_GROUP1(group2, E,b), 1480 [0xD1] = X86_OP_GROUP1(group2, E,v), 1481 [0xD2] = X86_OP_GROUP2(group2, E,b, 1,b), /* CL */ 1482 [0xD3] = X86_OP_GROUP2(group2, E,v, 1,b), /* CL */ 1483 [0xD4] = X86_OP_ENTRYr(AAM, I,b), 1484 [0xD5] = X86_OP_ENTRYr(AAD, I,b), 1485 [0xD6] = X86_OP_ENTRYw(SALC, 0,b), 1486 [0xD7] = X86_OP_ENTRY1(XLAT, 0,b, zextT0), /* AL read/written */ 1487 1488 [0xE0] = X86_OP_ENTRYr(LOOPNE, J,b), /* implicit: CX with aflag size */ 1489 [0xE1] = X86_OP_ENTRYr(LOOPE, J,b), /* implicit: CX with aflag size */ 1490 [0xE2] = X86_OP_ENTRYr(LOOP, J,b), /* implicit: CX with aflag size */ 1491 [0xE3] = X86_OP_ENTRYr(JCXZ, J,b), /* implicit: CX with aflag size */ 1492 [0xE4] = X86_OP_ENTRYwr(IN, 0,b, I_unsigned,b), /* AL */ 1493 [0xE5] = X86_OP_ENTRYwr(IN, 0,v, I_unsigned,b), /* AX/EAX */ 1494 [0xE6] = X86_OP_ENTRYrr(OUT, 0,b, I_unsigned,b), /* AL */ 1495 [0xE7] = X86_OP_ENTRYrr(OUT, 0,v, I_unsigned,b), /* AX/EAX */ 1496 1497 [0xF1] = X86_OP_ENTRY0(INT1, svm(ICEBP)), 1498 [0xF4] = X86_OP_ENTRY0(HLT, chk(cpl0)), 1499 [0xF5] = X86_OP_ENTRY0(CMC), 1500 [0xF6] = X86_OP_GROUP1(group3, E,b), 1501 [0xF7] = X86_OP_GROUP1(group3, E,v), 1502 1503 [0x08] = X86_OP_ENTRY2(OR, E,b, G,b, lock), 1504 [0x09] = X86_OP_ENTRY2(OR, E,v, G,v, lock), 1505 [0x0A] = X86_OP_ENTRY2(OR, G,b, E,b, lock), 1506 [0x0B] = X86_OP_ENTRY2(OR, G,v, E,v, lock), 1507 [0x0C] = X86_OP_ENTRY2(OR, 0,b, I,b, lock), /* AL, Ib */ 1508 [0x0D] = X86_OP_ENTRY2(OR, 0,v, I,z, lock), /* rAX, Iz */ 1509 [0x0E] = X86_OP_ENTRYr(PUSH, CS, w, chk(i64)), 1510 [0x0F] = X86_OP_GROUP0(0F), 1511 1512 [0x18] = X86_OP_ENTRY2(SBB, E,b, G,b, lock), 1513 [0x19] = X86_OP_ENTRY2(SBB, E,v, G,v, lock), 1514 [0x1A] = X86_OP_ENTRY2(SBB, G,b, E,b, lock), 1515 [0x1B] = X86_OP_ENTRY2(SBB, G,v, E,v, lock), 1516 [0x1C] = X86_OP_ENTRY2(SBB, 0,b, I,b, lock), /* AL, Ib */ 1517 [0x1D] = X86_OP_ENTRY2(SBB, 0,v, I,z, lock), /* rAX, Iz */ 1518 [0x1E] = X86_OP_ENTRYr(PUSH, DS, w, chk(i64)), 1519 [0x1F] = X86_OP_ENTRYw(POP, DS, w, chk(i64)), 1520 1521 [0x28] = X86_OP_ENTRY2(SUB, E,b, G,b, lock), 1522 [0x29] = X86_OP_ENTRY2(SUB, E,v, G,v, lock), 1523 [0x2A] = X86_OP_ENTRY2(SUB, G,b, E,b, lock), 1524 [0x2B] = X86_OP_ENTRY2(SUB, G,v, E,v, lock), 1525 [0x2C] = X86_OP_ENTRY2(SUB, 0,b, I,b, lock), /* AL, Ib */ 1526 [0x2D] = X86_OP_ENTRY2(SUB, 0,v, I,z, lock), /* rAX, Iz */ 1527 [0x2E] = {}, 1528 [0x2F] = X86_OP_ENTRY0(DAS, chk(i64)), 1529 1530 [0x38] = X86_OP_ENTRYrr(SUB, E,b, G,b), 1531 [0x39] = X86_OP_ENTRYrr(SUB, E,v, G,v), 1532 [0x3A] = X86_OP_ENTRYrr(SUB, G,b, E,b), 1533 [0x3B] = X86_OP_ENTRYrr(SUB, G,v, E,v), 1534 [0x3C] = X86_OP_ENTRYrr(SUB, 0,b, I,b), /* AL, Ib */ 1535 [0x3D] = X86_OP_ENTRYrr(SUB, 0,v, I,z), /* rAX, Iz */ 1536 [0x3E] = {}, 1537 [0x3F] = X86_OP_ENTRY0(AAS, chk(i64)), 1538 1539 [0x48] = X86_OP_ENTRY1(DEC, 0,v, chk(i64)), 1540 [0x49] = X86_OP_ENTRY1(DEC, 1,v, chk(i64)), 1541 [0x4A] = X86_OP_ENTRY1(DEC, 2,v, chk(i64)), 1542 [0x4B] = X86_OP_ENTRY1(DEC, 3,v, chk(i64)), 1543 [0x4C] = X86_OP_ENTRY1(DEC, 4,v, chk(i64)), 1544 [0x4D] = X86_OP_ENTRY1(DEC, 5,v, chk(i64)), 1545 [0x4E] = X86_OP_ENTRY1(DEC, 6,v, chk(i64)), 1546 [0x4F] = X86_OP_ENTRY1(DEC, 7,v, chk(i64)), 1547 1548 [0x58] = X86_OP_ENTRYw(POP, LoBits,d64), 1549 [0x59] = X86_OP_ENTRYw(POP, LoBits,d64), 1550 [0x5A] = X86_OP_ENTRYw(POP, LoBits,d64), 1551 [0x5B] = X86_OP_ENTRYw(POP, LoBits,d64), 1552 [0x5C] = X86_OP_ENTRYw(POP, LoBits,d64), 1553 [0x5D] = X86_OP_ENTRYw(POP, LoBits,d64), 1554 [0x5E] = X86_OP_ENTRYw(POP, LoBits,d64), 1555 [0x5F] = X86_OP_ENTRYw(POP, LoBits,d64), 1556 1557 [0x68] = X86_OP_ENTRYr(PUSH, I,z), 1558 [0x69] = X86_OP_ENTRY3(IMUL3, G,v, E,v, I,z, sextT0), 1559 [0x6A] = X86_OP_ENTRYr(PUSH, I,b), 1560 [0x6B] = X86_OP_ENTRY3(IMUL3, G,v, E,v, I,b, sextT0), 1561 [0x6C] = X86_OP_ENTRYrr(INS, Y,b, 2,w), /* DX */ 1562 [0x6D] = X86_OP_ENTRYrr(INS, Y,z, 2,w), /* DX */ 1563 [0x6E] = X86_OP_ENTRYrr(OUTS, X,b, 2,w), /* DX */ 1564 [0x6F] = X86_OP_ENTRYrr(OUTS, X,z, 2,w), /* DX */ 1565 1566 [0x78] = X86_OP_ENTRYr(Jcc, J,b), 1567 [0x79] = X86_OP_ENTRYr(Jcc, J,b), 1568 [0x7A] = X86_OP_ENTRYr(Jcc, J,b), 1569 [0x7B] = X86_OP_ENTRYr(Jcc, J,b), 1570 [0x7C] = X86_OP_ENTRYr(Jcc, J,b), 1571 [0x7D] = X86_OP_ENTRYr(Jcc, J,b), 1572 [0x7E] = X86_OP_ENTRYr(Jcc, J,b), 1573 [0x7F] = X86_OP_ENTRYr(Jcc, J,b), 1574 1575 [0x88] = X86_OP_ENTRY3(MOV, E,b, G,b, None, None), 1576 [0x89] = X86_OP_ENTRY3(MOV, E,v, G,v, None, None), 1577 [0x8A] = X86_OP_ENTRY3(MOV, G,b, E,b, None, None), 1578 [0x8B] = X86_OP_ENTRY3(MOV, G,v, E,v, None, None), 1579 [0x8C] = X86_OP_ENTRY3(MOV, E,v, S,w, None, None), 1580 [0x8D] = X86_OP_ENTRY3(LEA, G,v, M,v, None, None, noseg), 1581 [0x8E] = X86_OP_ENTRY3(MOV, S,w, E,v, None, None), 1582 [0x8F] = X86_OP_GROUPw(group1A, E,v), 1583 1584 [0x98] = X86_OP_ENTRY1(CBW, 0,v), /* rAX */ 1585 [0x99] = X86_OP_ENTRY3(CWD, 2,v, 0,v, None, None), /* rDX, rAX */ 1586 [0x9A] = X86_OP_ENTRYrr(CALLF, I_unsigned,p, I_unsigned,w, chk(i64)), 1587 [0x9B] = X86_OP_ENTRY0(WAIT), 1588 [0x9C] = X86_OP_ENTRY0(PUSHF, chk(vm86_iopl) svm(PUSHF)), 1589 [0x9D] = X86_OP_ENTRY0(POPF, chk(vm86_iopl) svm(POPF)), 1590 [0x9E] = X86_OP_ENTRY0(SAHF), 1591 [0x9F] = X86_OP_ENTRY0(LAHF), 1592 1593 [0xA8] = X86_OP_ENTRYrr(AND, 0,b, I,b), /* AL, Ib */ 1594 [0xA9] = X86_OP_ENTRYrr(AND, 0,v, I,z), /* rAX, Iz */ 1595 [0xAA] = X86_OP_ENTRY3(STOS, Y,b, 0,b, None, None), 1596 [0xAB] = X86_OP_ENTRY3(STOS, Y,v, 0,v, None, None), 1597 /* Manual writeback because REP LODS (!) has to write EAX/RAX after every LODS. */ 1598 [0xAC] = X86_OP_ENTRYr(LODS, X,b), 1599 [0xAD] = X86_OP_ENTRYr(LODS, X,v), 1600 [0xAE] = X86_OP_ENTRYrr(SCAS, 0,b, Y,b), 1601 [0xAF] = X86_OP_ENTRYrr(SCAS, 0,v, Y,v), 1602 1603 [0xB8] = X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), 1604 [0xB9] = X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), 1605 [0xBA] = X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), 1606 [0xBB] = X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), 1607 [0xBC] = X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), 1608 [0xBD] = X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), 1609 [0xBE] = X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), 1610 [0xBF] = X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), 1611 1612 [0xC8] = X86_OP_ENTRYrr(ENTER, I,w, I,b), 1613 [0xC9] = X86_OP_ENTRY1(LEAVE, A,d64), 1614 [0xCA] = X86_OP_ENTRYr(RETF, I,w), 1615 [0xCB] = X86_OP_ENTRY0(RETF), 1616 [0xCC] = X86_OP_ENTRY0(INT3), 1617 [0xCD] = X86_OP_ENTRYr(INT, I,b, chk(vm86_iopl)), 1618 [0xCE] = X86_OP_ENTRY0(INTO), 1619 [0xCF] = X86_OP_ENTRY0(IRET, chk(vm86_iopl) svm(IRET)), 1620 1621 [0xE8] = X86_OP_ENTRYr(CALL, J,z_f64), 1622 [0xE9] = X86_OP_ENTRYr(JMP, J,z_f64), 1623 [0xEA] = X86_OP_ENTRYrr(JMPF, I_unsigned,p, I_unsigned,w, chk(i64)), 1624 [0xEB] = X86_OP_ENTRYr(JMP, J,b), 1625 [0xEC] = X86_OP_ENTRYwr(IN, 0,b, 2,w), /* AL, DX */ 1626 [0xED] = X86_OP_ENTRYwr(IN, 0,v, 2,w), /* AX/EAX, DX */ 1627 [0xEE] = X86_OP_ENTRYrr(OUT, 0,b, 2,w), /* DX, AL */ 1628 [0xEF] = X86_OP_ENTRYrr(OUT, 0,v, 2,w), /* DX, AX/EAX */ 1629 1630 [0xF8] = X86_OP_ENTRY0(CLC), 1631 [0xF9] = X86_OP_ENTRY0(STC), 1632 [0xFA] = X86_OP_ENTRY0(CLI, chk(iopl)), 1633 [0xFB] = X86_OP_ENTRY0(STI, chk(iopl)), 1634 [0xFC] = X86_OP_ENTRY0(CLD), 1635 [0xFD] = X86_OP_ENTRY0(STD), 1636 [0xFE] = X86_OP_GROUP1(group4_5, E,b), 1637 [0xFF] = X86_OP_GROUP1(group4_5, E,v), 1638}; 1639 1640#undef mmx 1641#undef vex1 1642#undef vex2 1643#undef vex3 1644#undef vex4 1645#undef vex4_unal 1646#undef vex5 1647#undef vex6 1648#undef vex7 1649#undef vex8 1650#undef vex11 1651#undef vex12 1652#undef vex13 1653 1654/* 1655 * Decode the fixed part of the opcode and place the last 1656 * in b. 1657 */ 1658static void decode_root(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) 1659{ 1660 *entry = opcodes_root[*b]; 1661} 1662 1663 1664static int decode_modrm(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode, 1665 X86DecodedOp *op, X86OpType type) 1666{ 1667 int modrm = get_modrm(s, env); 1668 if ((modrm >> 6) == 3) { 1669 op->n = (modrm & 7); 1670 if (type != X86_TYPE_Q && type != X86_TYPE_N) { 1671 op->n |= REX_B(s); 1672 } 1673 } else { 1674 op->has_ea = true; 1675 op->n = -1; 1676 decode->mem = gen_lea_modrm_0(env, s, get_modrm(s, env)); 1677 } 1678 return modrm; 1679} 1680 1681static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp *ot) 1682{ 1683 switch (size) { 1684 case X86_SIZE_b: /* byte */ 1685 *ot = MO_8; 1686 return true; 1687 1688 case X86_SIZE_d: /* 32-bit */ 1689 case X86_SIZE_ss: /* SSE/AVX scalar single precision */ 1690 *ot = MO_32; 1691 return true; 1692 1693 case X86_SIZE_p: /* Far pointer, return offset size */ 1694 case X86_SIZE_s: /* Descriptor, return offset size */ 1695 case X86_SIZE_v: /* 16/32/64-bit, based on operand size */ 1696 *ot = s->dflag; 1697 return true; 1698 1699 case X86_SIZE_pi: /* MMX */ 1700 case X86_SIZE_q: /* 64-bit */ 1701 case X86_SIZE_sd: /* SSE/AVX scalar double precision */ 1702 *ot = MO_64; 1703 return true; 1704 1705 case X86_SIZE_w: /* 16-bit */ 1706 *ot = MO_16; 1707 return true; 1708 1709 case X86_SIZE_y: /* 32/64-bit, based on operand size */ 1710 *ot = s->dflag == MO_16 ? MO_32 : s->dflag; 1711 return true; 1712 1713 case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */ 1714 *ot = s->dflag == MO_16 ? MO_16 : MO_32; 1715 return true; 1716 1717 case X86_SIZE_z_f64: /* 32-bit for 32-bit operand size or 64-bit mode, else 16-bit */ 1718 *ot = !CODE64(s) && s->dflag == MO_16 ? MO_16 : MO_32; 1719 return true; 1720 1721 case X86_SIZE_dq: /* SSE/AVX 128-bit */ 1722 if (e->special == X86_SPECIAL_MMX && 1723 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 1724 *ot = MO_64; 1725 return true; 1726 } 1727 if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) { 1728 return false; 1729 } 1730 *ot = MO_128; 1731 return true; 1732 1733 case X86_SIZE_qq: /* AVX 256-bit */ 1734 if (!s->vex_l) { 1735 return false; 1736 } 1737 *ot = MO_256; 1738 return true; 1739 1740 case X86_SIZE_x: /* 128/256-bit, based on operand size */ 1741 if (e->special == X86_SPECIAL_MMX && 1742 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 1743 *ot = MO_64; 1744 return true; 1745 } 1746 /* fall through */ 1747 case X86_SIZE_ps: /* SSE/AVX packed single precision */ 1748 case X86_SIZE_pd: /* SSE/AVX packed double precision */ 1749 *ot = s->vex_l ? MO_256 : MO_128; 1750 return true; 1751 1752 case X86_SIZE_xh: /* SSE/AVX packed half register */ 1753 *ot = s->vex_l ? MO_128 : MO_64; 1754 return true; 1755 1756 case X86_SIZE_d64: /* Default to 64-bit in 64-bit mode */ 1757 *ot = CODE64(s) && s->dflag == MO_32 ? MO_64 : s->dflag; 1758 return true; 1759 1760 case X86_SIZE_f64: /* Ignore size override prefix in 64-bit mode */ 1761 *ot = CODE64(s) ? MO_64 : s->dflag; 1762 return true; 1763 1764 default: 1765 *ot = -1; 1766 return true; 1767 } 1768} 1769 1770static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode, 1771 X86DecodedOp *op, X86OpType type, int b) 1772{ 1773 int modrm; 1774 1775 switch (type) { 1776 case X86_TYPE_None: /* Implicit or absent */ 1777 case X86_TYPE_A: /* Implicit */ 1778 case X86_TYPE_F: /* EFLAGS/RFLAGS */ 1779 case X86_TYPE_X: /* string source */ 1780 case X86_TYPE_Y: /* string destination */ 1781 break; 1782 1783 case X86_TYPE_B: /* VEX.vvvv selects a GPR */ 1784 op->unit = X86_OP_INT; 1785 op->n = s->vex_v; 1786 break; 1787 1788 case X86_TYPE_C: /* REG in the modrm byte selects a control register */ 1789 op->unit = X86_OP_CR; 1790 goto get_reg; 1791 1792 case X86_TYPE_D: /* REG in the modrm byte selects a debug register */ 1793 op->unit = X86_OP_DR; 1794 goto get_reg; 1795 1796 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */ 1797 op->unit = X86_OP_INT; 1798 goto get_reg; 1799 1800 case X86_TYPE_S: /* reg selects a segment register */ 1801 op->unit = X86_OP_SEG; 1802 goto get_reg; 1803 1804 case X86_TYPE_P: 1805 op->unit = X86_OP_MMX; 1806 goto get_reg; 1807 1808 case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */ 1809 if (decode->e.special == X86_SPECIAL_MMX && 1810 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 1811 op->unit = X86_OP_MMX; 1812 } else { 1813 op->unit = X86_OP_SSE; 1814 } 1815 get_reg: 1816 op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s); 1817 break; 1818 1819 case X86_TYPE_E: /* ALU modrm operand */ 1820 op->unit = X86_OP_INT; 1821 goto get_modrm; 1822 1823 case X86_TYPE_Q: /* MMX modrm operand */ 1824 op->unit = X86_OP_MMX; 1825 goto get_modrm; 1826 1827 case X86_TYPE_W: /* XMM/YMM modrm operand */ 1828 if (decode->e.special == X86_SPECIAL_MMX && 1829 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 1830 op->unit = X86_OP_MMX; 1831 } else { 1832 op->unit = X86_OP_SSE; 1833 } 1834 goto get_modrm; 1835 1836 case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */ 1837 op->unit = X86_OP_MMX; 1838 goto get_modrm_reg; 1839 1840 case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */ 1841 if (decode->e.special == X86_SPECIAL_MMX && 1842 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 1843 op->unit = X86_OP_MMX; 1844 } else { 1845 op->unit = X86_OP_SSE; 1846 } 1847 goto get_modrm_reg; 1848 1849 case X86_TYPE_R: /* R/M in the modrm byte selects a register */ 1850 op->unit = X86_OP_INT; 1851 get_modrm_reg: 1852 modrm = get_modrm(s, env); 1853 if ((modrm >> 6) != 3) { 1854 return false; 1855 } 1856 goto get_modrm; 1857 1858 case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */ 1859 op->unit = X86_OP_SSE; 1860 goto get_modrm_mem; 1861 1862 case X86_TYPE_EM: /* modrm byte selects an ALU memory operand */ 1863 op->unit = X86_OP_INT; 1864 /* fall through */ 1865 case X86_TYPE_M: /* modrm byte selects a memory operand */ 1866 get_modrm_mem: 1867 modrm = get_modrm(s, env); 1868 if ((modrm >> 6) == 3) { 1869 return false; 1870 } 1871 /* fall through */ 1872 case X86_TYPE_nop: /* modrm operand decoded but not fetched */ 1873 get_modrm: 1874 decode_modrm(s, env, decode, op, type); 1875 break; 1876 1877 case X86_TYPE_O: /* Absolute address encoded in the instruction */ 1878 op->unit = X86_OP_INT; 1879 op->has_ea = true; 1880 op->n = -1; 1881 decode->mem = (AddressParts) { 1882 .def_seg = R_DS, 1883 .base = -1, 1884 .index = -1, 1885 .disp = insn_get_addr(env, s, s->aflag) 1886 }; 1887 break; 1888 1889 case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */ 1890 if ((s->prefix & PREFIX_VEX)) { 1891 op->unit = X86_OP_SSE; 1892 op->n = s->vex_v; 1893 break; 1894 } 1895 if (op == &decode->op[0]) { 1896 /* shifts place the destination in VEX.vvvv, use modrm */ 1897 return decode_op(s, env, decode, op, decode->e.op1, b); 1898 } else { 1899 return decode_op(s, env, decode, op, decode->e.op0, b); 1900 } 1901 1902 case X86_TYPE_I: /* Immediate */ 1903 case X86_TYPE_J: /* Relative offset for a jump */ 1904 op->unit = X86_OP_IMM; 1905 decode->immediate = op->imm = insn_get_signed(env, s, op->ot); 1906 break; 1907 1908 case X86_TYPE_I_unsigned: /* Immediate */ 1909 op->unit = X86_OP_IMM; 1910 decode->immediate = op->imm = insn_get(env, s, op->ot); 1911 break; 1912 1913 case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */ 1914 op->n = insn_get(env, s, op->ot) >> 4; 1915 break; 1916 1917 case X86_TYPE_2op: 1918 *op = decode->op[0]; 1919 break; 1920 1921 case X86_TYPE_LoBits: 1922 op->n = (b & 7) | REX_B(s); 1923 op->unit = X86_OP_INT; 1924 break; 1925 1926 case X86_TYPE_0 ... X86_TYPE_7: 1927 op->n = type - X86_TYPE_0; 1928 op->unit = X86_OP_INT; 1929 break; 1930 1931 case X86_TYPE_ES ... X86_TYPE_GS: 1932 op->n = type - X86_TYPE_ES; 1933 op->unit = X86_OP_SEG; 1934 break; 1935 } 1936 1937 return true; 1938} 1939 1940static bool validate_sse_prefix(DisasContext *s, X86OpEntry *e) 1941{ 1942 uint16_t sse_prefixes; 1943 1944 if (!e->valid_prefix) { 1945 return true; 1946 } 1947 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 1948 /* In SSE instructions, 0xF3 and 0xF2 cancel 0x66. */ 1949 s->prefix &= ~PREFIX_DATA; 1950 } 1951 1952 /* Now, either zero or one bit is set in sse_prefixes. */ 1953 sse_prefixes = s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); 1954 return e->valid_prefix & (1 << sse_prefixes); 1955} 1956 1957static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func, 1958 X86DecodedInsn *decode) 1959{ 1960 X86OpEntry *e = &decode->e; 1961 1962 decode_func(s, env, e, &decode->b); 1963 while (e->is_decode) { 1964 e->is_decode = false; 1965 e->decode(s, env, e, &decode->b); 1966 } 1967 1968 if (!validate_sse_prefix(s, e)) { 1969 return false; 1970 } 1971 1972 /* First compute size of operands in order to initialize s->rip_offset. */ 1973 if (e->op0 != X86_TYPE_None) { 1974 if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) { 1975 return false; 1976 } 1977 if (e->op0 == X86_TYPE_I) { 1978 s->rip_offset += 1 << decode->op[0].ot; 1979 } 1980 } 1981 if (e->op1 != X86_TYPE_None) { 1982 if (!decode_op_size(s, e, e->s1, &decode->op[1].ot)) { 1983 return false; 1984 } 1985 if (e->op1 == X86_TYPE_I) { 1986 s->rip_offset += 1 << decode->op[1].ot; 1987 } 1988 } 1989 if (e->op2 != X86_TYPE_None) { 1990 if (!decode_op_size(s, e, e->s2, &decode->op[2].ot)) { 1991 return false; 1992 } 1993 if (e->op2 == X86_TYPE_I) { 1994 s->rip_offset += 1 << decode->op[2].ot; 1995 } 1996 } 1997 if (e->op3 != X86_TYPE_None) { 1998 /* 1999 * A couple instructions actually use the extra immediate byte for an Lx 2000 * register operand; those are handled in the gen_* functions as one off. 2001 */ 2002 assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b); 2003 s->rip_offset += 1; 2004 } 2005 2006 if (e->op0 != X86_TYPE_None && 2007 !decode_op(s, env, decode, &decode->op[0], e->op0, decode->b)) { 2008 return false; 2009 } 2010 2011 if (e->op1 != X86_TYPE_None && 2012 !decode_op(s, env, decode, &decode->op[1], e->op1, decode->b)) { 2013 return false; 2014 } 2015 2016 if (e->op2 != X86_TYPE_None && 2017 !decode_op(s, env, decode, &decode->op[2], e->op2, decode->b)) { 2018 return false; 2019 } 2020 2021 if (e->op3 != X86_TYPE_None) { 2022 decode->immediate = insn_get_signed(env, s, MO_8); 2023 } 2024 2025 return true; 2026} 2027 2028static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid) 2029{ 2030 switch (cpuid) { 2031 case X86_FEAT_None: 2032 return true; 2033 case X86_FEAT_CMOV: 2034 return (s->cpuid_features & CPUID_CMOV); 2035 case X86_FEAT_F16C: 2036 return (s->cpuid_ext_features & CPUID_EXT_F16C); 2037 case X86_FEAT_FMA: 2038 return (s->cpuid_ext_features & CPUID_EXT_FMA); 2039 case X86_FEAT_MOVBE: 2040 return (s->cpuid_ext_features & CPUID_EXT_MOVBE); 2041 case X86_FEAT_PCLMULQDQ: 2042 return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ); 2043 case X86_FEAT_SSE: 2044 return (s->cpuid_ext_features & CPUID_SSE); 2045 case X86_FEAT_SSE2: 2046 return (s->cpuid_ext_features & CPUID_SSE2); 2047 case X86_FEAT_SSE3: 2048 return (s->cpuid_ext_features & CPUID_EXT_SSE3); 2049 case X86_FEAT_SSSE3: 2050 return (s->cpuid_ext_features & CPUID_EXT_SSSE3); 2051 case X86_FEAT_SSE41: 2052 return (s->cpuid_ext_features & CPUID_EXT_SSE41); 2053 case X86_FEAT_SSE42: 2054 return (s->cpuid_ext_features & CPUID_EXT_SSE42); 2055 case X86_FEAT_AES: 2056 if (!(s->cpuid_ext_features & CPUID_EXT_AES)) { 2057 return false; 2058 } else if (!(s->prefix & PREFIX_VEX)) { 2059 return true; 2060 } else if (!(s->cpuid_ext_features & CPUID_EXT_AVX)) { 2061 return false; 2062 } else { 2063 return !s->vex_l || (s->cpuid_7_0_ecx_features & CPUID_7_0_ECX_VAES); 2064 } 2065 2066 case X86_FEAT_AVX: 2067 return (s->cpuid_ext_features & CPUID_EXT_AVX); 2068 2069 case X86_FEAT_3DNOW: 2070 return (s->cpuid_ext2_features & CPUID_EXT2_3DNOW); 2071 case X86_FEAT_SSE4A: 2072 return (s->cpuid_ext3_features & CPUID_EXT3_SSE4A); 2073 2074 case X86_FEAT_ADX: 2075 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX); 2076 case X86_FEAT_BMI1: 2077 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1); 2078 case X86_FEAT_BMI2: 2079 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2); 2080 case X86_FEAT_AVX2: 2081 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2); 2082 case X86_FEAT_SHA_NI: 2083 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SHA_NI); 2084 2085 case X86_FEAT_CMPCCXADD: 2086 return (s->cpuid_7_1_eax_features & CPUID_7_1_EAX_CMPCCXADD); 2087 } 2088 g_assert_not_reached(); 2089} 2090 2091static bool validate_vex(DisasContext *s, X86DecodedInsn *decode) 2092{ 2093 X86OpEntry *e = &decode->e; 2094 2095 switch (e->vex_special) { 2096 case X86_VEX_REPScalar: 2097 /* 2098 * Instructions which differ between 00/66 and F2/F3 in the 2099 * exception classification and the size of the memory operand. 2100 */ 2101 assert(e->vex_class == 1 || e->vex_class == 2 || e->vex_class == 4); 2102 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { 2103 e->vex_class = e->vex_class < 4 ? 3 : 5; 2104 if (s->vex_l) { 2105 goto illegal; 2106 } 2107 assert(decode->e.s2 == X86_SIZE_x); 2108 if (decode->op[2].has_ea) { 2109 decode->op[2].ot = s->prefix & PREFIX_REPZ ? MO_32 : MO_64; 2110 } 2111 } 2112 break; 2113 2114 case X86_VEX_SSEUnaligned: 2115 /* handled in sse_needs_alignment. */ 2116 break; 2117 2118 case X86_VEX_AVX2_256: 2119 if ((s->prefix & PREFIX_VEX) && s->vex_l && !has_cpuid_feature(s, X86_FEAT_AVX2)) { 2120 goto illegal; 2121 } 2122 } 2123 2124 switch (e->vex_class) { 2125 case 0: 2126 if (s->prefix & PREFIX_VEX) { 2127 goto illegal; 2128 } 2129 return true; 2130 case 1: 2131 case 2: 2132 case 3: 2133 case 4: 2134 case 5: 2135 case 7: 2136 if (s->prefix & PREFIX_VEX) { 2137 if (!(s->flags & HF_AVX_EN_MASK)) { 2138 goto illegal; 2139 } 2140 } else if (e->special != X86_SPECIAL_MMX || 2141 (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) { 2142 if (!(s->flags & HF_OSFXSR_MASK)) { 2143 goto illegal; 2144 } 2145 } 2146 break; 2147 case 12: 2148 /* Must have a VSIB byte and no address prefix. */ 2149 assert(s->has_modrm); 2150 if ((s->modrm & 7) != 4 || s->aflag == MO_16) { 2151 goto illegal; 2152 } 2153 2154 /* Check no overlap between registers. */ 2155 if (!decode->op[0].has_ea && 2156 (decode->op[0].n == decode->mem.index || decode->op[0].n == decode->op[1].n)) { 2157 goto illegal; 2158 } 2159 assert(!decode->op[1].has_ea); 2160 if (decode->op[1].n == decode->mem.index) { 2161 goto illegal; 2162 } 2163 if (!decode->op[2].has_ea && 2164 (decode->op[2].n == decode->mem.index || decode->op[2].n == decode->op[1].n)) { 2165 goto illegal; 2166 } 2167 /* fall through */ 2168 case 6: 2169 case 11: 2170 if (!(s->prefix & PREFIX_VEX)) { 2171 goto illegal; 2172 } 2173 if (!(s->flags & HF_AVX_EN_MASK)) { 2174 goto illegal; 2175 } 2176 break; 2177 case 8: 2178 /* Non-VEX case handled in decode_0F77. */ 2179 assert(s->prefix & PREFIX_VEX); 2180 if (!(s->flags & HF_AVX_EN_MASK)) { 2181 goto illegal; 2182 } 2183 break; 2184 case 13: 2185 if (!(s->prefix & PREFIX_VEX)) { 2186 goto illegal; 2187 } 2188 if (s->vex_l) { 2189 goto illegal; 2190 } 2191 /* All integer instructions use VEX.vvvv, so exit. */ 2192 return true; 2193 } 2194 2195 if (s->vex_v != 0 && 2196 e->op0 != X86_TYPE_H && e->op0 != X86_TYPE_B && 2197 e->op1 != X86_TYPE_H && e->op1 != X86_TYPE_B && 2198 e->op2 != X86_TYPE_H && e->op2 != X86_TYPE_B) { 2199 goto illegal; 2200 } 2201 2202 if (s->flags & HF_TS_MASK) { 2203 goto nm_exception; 2204 } 2205 if (s->flags & HF_EM_MASK) { 2206 goto illegal; 2207 } 2208 2209 if (e->check) { 2210 if (e->check & X86_CHECK_VEX128) { 2211 if (s->vex_l) { 2212 goto illegal; 2213 } 2214 } 2215 if (e->check & X86_CHECK_W0) { 2216 if (s->vex_w) { 2217 goto illegal; 2218 } 2219 } 2220 if (e->check & X86_CHECK_W1) { 2221 if (!s->vex_w) { 2222 goto illegal; 2223 } 2224 } 2225 } 2226 return true; 2227 2228nm_exception: 2229 gen_NM_exception(s); 2230 return false; 2231illegal: 2232 gen_illegal_opcode(s); 2233 return false; 2234} 2235 2236/* 2237 * Convert one instruction. s->base.is_jmp is set if the translation must 2238 * be stopped. 2239 */ 2240static void disas_insn(DisasContext *s, CPUState *cpu) 2241{ 2242 CPUX86State *env = cpu_env(cpu); 2243 X86DecodedInsn decode; 2244 X86DecodeFunc decode_func = decode_root; 2245 uint8_t cc_live, b; 2246 2247 s->pc = s->base.pc_next; 2248 s->override = -1; 2249 s->popl_esp_hack = 0; 2250#ifdef TARGET_X86_64 2251 s->rex_r = 0; 2252 s->rex_x = 0; 2253 s->rex_b = 0; 2254#endif 2255 s->rip_offset = 0; /* for relative ip address */ 2256 s->vex_l = 0; 2257 s->vex_v = 0; 2258 s->vex_w = false; 2259 s->has_modrm = false; 2260 s->prefix = 0; 2261 2262 next_byte: 2263 b = x86_ldub_code(env, s); 2264 2265 /* Collect prefixes. */ 2266 switch (b) { 2267 case 0xf3: 2268 s->prefix |= PREFIX_REPZ; 2269 s->prefix &= ~PREFIX_REPNZ; 2270 goto next_byte; 2271 case 0xf2: 2272 s->prefix |= PREFIX_REPNZ; 2273 s->prefix &= ~PREFIX_REPZ; 2274 goto next_byte; 2275 case 0xf0: 2276 s->prefix |= PREFIX_LOCK; 2277 goto next_byte; 2278 case 0x2e: 2279 s->override = R_CS; 2280 goto next_byte; 2281 case 0x36: 2282 s->override = R_SS; 2283 goto next_byte; 2284 case 0x3e: 2285 s->override = R_DS; 2286 goto next_byte; 2287 case 0x26: 2288 s->override = R_ES; 2289 goto next_byte; 2290 case 0x64: 2291 s->override = R_FS; 2292 goto next_byte; 2293 case 0x65: 2294 s->override = R_GS; 2295 goto next_byte; 2296 case 0x66: 2297 s->prefix |= PREFIX_DATA; 2298 goto next_byte; 2299 case 0x67: 2300 s->prefix |= PREFIX_ADR; 2301 goto next_byte; 2302#ifdef TARGET_X86_64 2303 case 0x40 ... 0x4f: 2304 if (CODE64(s)) { 2305 /* REX prefix */ 2306 s->prefix |= PREFIX_REX; 2307 s->vex_w = (b >> 3) & 1; 2308 s->rex_r = (b & 0x4) << 1; 2309 s->rex_x = (b & 0x2) << 2; 2310 s->rex_b = (b & 0x1) << 3; 2311 goto next_byte; 2312 } 2313 break; 2314#endif 2315 case 0xc5: /* 2-byte VEX */ 2316 case 0xc4: /* 3-byte VEX */ 2317 /* 2318 * VEX prefixes cannot be used except in 32-bit mode. 2319 * Otherwise the instruction is LES or LDS. 2320 */ 2321 if (CODE32(s) && !VM86(s)) { 2322 static const int pp_prefix[4] = { 2323 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ 2324 }; 2325 int vex3, vex2 = x86_ldub_code(env, s); 2326 2327 if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) { 2328 /* 2329 * 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b, 2330 * otherwise the instruction is LES or LDS. 2331 */ 2332 s->pc--; /* rewind the advance_pc() x86_ldub_code() did */ 2333 break; 2334 } 2335 2336 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */ 2337 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ 2338 | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) { 2339 goto illegal_op; 2340 } 2341#ifdef TARGET_X86_64 2342 s->rex_r = (~vex2 >> 4) & 8; 2343#endif 2344 if (b == 0xc5) { 2345 /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */ 2346 vex3 = vex2; 2347 decode_func = decode_0F; 2348 } else { 2349 /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */ 2350 vex3 = x86_ldub_code(env, s); 2351#ifdef TARGET_X86_64 2352 s->rex_x = (~vex2 >> 3) & 8; 2353 s->rex_b = (~vex2 >> 2) & 8; 2354#endif 2355 s->vex_w = (vex3 >> 7) & 1; 2356 switch (vex2 & 0x1f) { 2357 case 0x01: /* Implied 0f leading opcode bytes. */ 2358 decode_func = decode_0F; 2359 break; 2360 case 0x02: /* Implied 0f 38 leading opcode bytes. */ 2361 decode_func = decode_0F38; 2362 break; 2363 case 0x03: /* Implied 0f 3a leading opcode bytes. */ 2364 decode_func = decode_0F3A; 2365 break; 2366 default: /* Reserved for future use. */ 2367 goto unknown_op; 2368 } 2369 } 2370 s->vex_v = (~vex3 >> 3) & 0xf; 2371 s->vex_l = (vex3 >> 2) & 1; 2372 s->prefix |= pp_prefix[vex3 & 3] | PREFIX_VEX; 2373 } 2374 break; 2375 default: 2376 break; 2377 } 2378 2379 /* Post-process prefixes. */ 2380 if (CODE64(s)) { 2381 /* 2382 * In 64-bit mode, the default data size is 32-bit. Select 64-bit 2383 * data with rex_w, and 16-bit data with 0x66; rex_w takes precedence 2384 * over 0x66 if both are present. 2385 */ 2386 s->dflag = (REX_W(s) ? MO_64 : s->prefix & PREFIX_DATA ? MO_16 : MO_32); 2387 /* In 64-bit mode, 0x67 selects 32-bit addressing. */ 2388 s->aflag = (s->prefix & PREFIX_ADR ? MO_32 : MO_64); 2389 } else { 2390 /* In 16/32-bit mode, 0x66 selects the opposite data size. */ 2391 if (CODE32(s) ^ ((s->prefix & PREFIX_DATA) != 0)) { 2392 s->dflag = MO_32; 2393 } else { 2394 s->dflag = MO_16; 2395 } 2396 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */ 2397 if (CODE32(s) ^ ((s->prefix & PREFIX_ADR) != 0)) { 2398 s->aflag = MO_32; 2399 } else { 2400 s->aflag = MO_16; 2401 } 2402 } 2403 2404 /* Go back to old decoder for unconverted opcodes. */ 2405 if (!(s->prefix & PREFIX_VEX)) { 2406 if ((b & ~7) == 0xd8) { 2407 if (!disas_insn_x87(s, cpu, b)) { 2408 goto unknown_op; 2409 } 2410 return; 2411 } 2412 2413 if (b == 0x0f) { 2414 b = x86_ldub_code(env, s); 2415 switch (b) { 2416 case 0x00 ... 0x03: /* mostly privileged instructions */ 2417 case 0x05 ... 0x09: 2418 case 0x1a ... 0x1b: /* MPX */ 2419 case 0x20 ... 0x23: /* mov from/to CR and DR */ 2420 case 0x30 ... 0x35: /* more privileged instructions */ 2421 case 0xa2 ... 0xa5: /* CPUID, BT, SHLD */ 2422 case 0xaa ... 0xae: /* RSM, SHRD, grp15 */ 2423 case 0xb0 ... 0xb1: /* cmpxchg */ 2424 case 0xb3: /* btr */ 2425 case 0xb8: /* integer ops */ 2426 case 0xba ... 0xbd: /* integer ops */ 2427 case 0xc0 ... 0xc1: /* xadd */ 2428 case 0xc7: /* grp9 */ 2429 disas_insn_old(s, cpu, b + 0x100); 2430 return; 2431 default: 2432 decode_func = do_decode_0F; 2433 break; 2434 } 2435 } 2436 } 2437 2438 memset(&decode, 0, sizeof(decode)); 2439 decode.cc_op = -1; 2440 decode.b = b; 2441 if (!decode_insn(s, env, decode_func, &decode)) { 2442 goto illegal_op; 2443 } 2444 if (!decode.e.gen) { 2445 goto unknown_op; 2446 } 2447 2448 if (!has_cpuid_feature(s, decode.e.cpuid)) { 2449 goto illegal_op; 2450 } 2451 2452 /* Checks that result in #UD come first. */ 2453 if (decode.e.check) { 2454 if (decode.e.check & X86_CHECK_i64) { 2455 if (CODE64(s)) { 2456 goto illegal_op; 2457 } 2458 } 2459 if (decode.e.check & X86_CHECK_o64) { 2460 if (!CODE64(s)) { 2461 goto illegal_op; 2462 } 2463 } 2464 if (decode.e.check & X86_CHECK_prot) { 2465 if (!PE(s) || VM86(s)) { 2466 goto illegal_op; 2467 } 2468 } 2469 } 2470 2471 switch (decode.e.special) { 2472 case X86_SPECIAL_None: 2473 break; 2474 2475 case X86_SPECIAL_Locked: 2476 if (decode.op[0].has_ea) { 2477 s->prefix |= PREFIX_LOCK; 2478 } 2479 decode.e.special = X86_SPECIAL_HasLock; 2480 /* fallthrough */ 2481 case X86_SPECIAL_HasLock: 2482 break; 2483 2484 case X86_SPECIAL_Op0_Rd: 2485 assert(decode.op[0].unit == X86_OP_INT); 2486 if (!decode.op[0].has_ea) { 2487 decode.op[0].ot = MO_32; 2488 } 2489 break; 2490 2491 case X86_SPECIAL_Op2_Ry: 2492 assert(decode.op[2].unit == X86_OP_INT); 2493 if (!decode.op[2].has_ea) { 2494 decode.op[2].ot = s->dflag == MO_16 ? MO_32 : s->dflag; 2495 } 2496 break; 2497 2498 case X86_SPECIAL_AVXExtMov: 2499 if (!decode.op[2].has_ea) { 2500 decode.op[2].ot = s->vex_l ? MO_256 : MO_128; 2501 } else if (s->vex_l) { 2502 decode.op[2].ot++; 2503 } 2504 break; 2505 2506 case X86_SPECIAL_SExtT0: 2507 case X86_SPECIAL_ZExtT0: 2508 /* Handled in gen_load. */ 2509 assert(decode.op[1].unit == X86_OP_INT); 2510 break; 2511 2512 case X86_SPECIAL_NoSeg: 2513 decode.mem.def_seg = -1; 2514 s->override = -1; 2515 break; 2516 2517 default: 2518 break; 2519 } 2520 2521 if (s->prefix & PREFIX_LOCK) { 2522 if (decode.e.special != X86_SPECIAL_HasLock || !decode.op[0].has_ea) { 2523 goto illegal_op; 2524 } 2525 } 2526 2527 if (!validate_vex(s, &decode)) { 2528 return; 2529 } 2530 2531 /* 2532 * Checks that result in #GP or VMEXIT come second. Intercepts are 2533 * generally checked after non-memory exceptions (i.e. before all 2534 * exceptions if there is no memory operand). Exceptions are 2535 * vm86 checks (INTn, IRET, PUSHF/POPF), RSM and XSETBV (!). 2536 * 2537 * RSM and XSETBV will be handled in the gen_* functions 2538 * instead of using chk(). 2539 */ 2540 if (decode.e.check & X86_CHECK_cpl0) { 2541 if (CPL(s) != 0) { 2542 goto gp_fault; 2543 } 2544 } 2545 if (decode.e.intercept && unlikely(GUEST(s))) { 2546 gen_helper_svm_check_intercept(tcg_env, 2547 tcg_constant_i32(decode.e.intercept)); 2548 } 2549 if (decode.e.check) { 2550 if ((decode.e.check & X86_CHECK_vm86_iopl) && VM86(s)) { 2551 if (IOPL(s) < 3) { 2552 goto gp_fault; 2553 } 2554 } else if (decode.e.check & X86_CHECK_cpl_iopl) { 2555 if (IOPL(s) < CPL(s)) { 2556 goto gp_fault; 2557 } 2558 } 2559 } 2560 2561 if (decode.e.special == X86_SPECIAL_MMX && 2562 !(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) { 2563 gen_helper_enter_mmx(tcg_env); 2564 } 2565 2566 if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) { 2567 gen_load_ea(s, &decode.mem, decode.e.vex_class == 12); 2568 } 2569 if (s->prefix & PREFIX_LOCK) { 2570 gen_load(s, &decode, 2, s->T1); 2571 decode.e.gen(s, env, &decode); 2572 } else { 2573 if (decode.op[0].unit == X86_OP_MMX) { 2574 compute_mmx_offset(&decode.op[0]); 2575 } else if (decode.op[0].unit == X86_OP_SSE) { 2576 compute_xmm_offset(&decode.op[0]); 2577 } 2578 gen_load(s, &decode, 1, s->T0); 2579 gen_load(s, &decode, 2, s->T1); 2580 decode.e.gen(s, env, &decode); 2581 gen_writeback(s, &decode, 0, s->T0); 2582 } 2583 2584 /* 2585 * Write back flags after last memory access. Some newer ALU instructions, as 2586 * well as SSE instructions, write flags in the gen_* function, but that can 2587 * cause incorrect tracking of CC_OP for instructions that write to both memory 2588 * and flags. 2589 */ 2590 if (decode.cc_op != -1) { 2591 if (decode.cc_dst) { 2592 tcg_gen_mov_tl(cpu_cc_dst, decode.cc_dst); 2593 } 2594 if (decode.cc_src) { 2595 tcg_gen_mov_tl(cpu_cc_src, decode.cc_src); 2596 } 2597 if (decode.cc_src2) { 2598 tcg_gen_mov_tl(cpu_cc_src2, decode.cc_src2); 2599 } 2600 if (decode.cc_op == CC_OP_DYNAMIC) { 2601 tcg_gen_mov_i32(cpu_cc_op, decode.cc_op_dynamic); 2602 } 2603 set_cc_op(s, decode.cc_op); 2604 cc_live = cc_op_live[decode.cc_op]; 2605 } else { 2606 cc_live = 0; 2607 } 2608 if (decode.cc_op != CC_OP_DYNAMIC) { 2609 assert(!decode.cc_op_dynamic); 2610 assert(!!decode.cc_dst == !!(cc_live & USES_CC_DST)); 2611 assert(!!decode.cc_src == !!(cc_live & USES_CC_SRC)); 2612 assert(!!decode.cc_src2 == !!(cc_live & USES_CC_SRC2)); 2613 } 2614 2615 return; 2616 gp_fault: 2617 gen_exception_gpf(s); 2618 return; 2619 illegal_op: 2620 gen_illegal_opcode(s); 2621 return; 2622 unknown_op: 2623 gen_unknown_opcode(env, s); 2624} 2625