1 #include "qemu/osdep.h" 2 #include "cpu.h" 3 #include "exec/exec-all.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "hw/i386/pc.h" 7 #include "hw/isa/isa.h" 8 #include "migration/cpu.h" 9 #include "hyperv.h" 10 11 #include "sysemu/kvm.h" 12 #include "sysemu/tcg.h" 13 14 #include "qemu/error-report.h" 15 16 static const VMStateDescription vmstate_segment = { 17 .name = "segment", 18 .version_id = 1, 19 .minimum_version_id = 1, 20 .fields = (VMStateField[]) { 21 VMSTATE_UINT32(selector, SegmentCache), 22 VMSTATE_UINTTL(base, SegmentCache), 23 VMSTATE_UINT32(limit, SegmentCache), 24 VMSTATE_UINT32(flags, SegmentCache), 25 VMSTATE_END_OF_LIST() 26 } 27 }; 28 29 #define VMSTATE_SEGMENT(_field, _state) { \ 30 .name = (stringify(_field)), \ 31 .size = sizeof(SegmentCache), \ 32 .vmsd = &vmstate_segment, \ 33 .flags = VMS_STRUCT, \ 34 .offset = offsetof(_state, _field) \ 35 + type_check(SegmentCache,typeof_field(_state, _field)) \ 36 } 37 38 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \ 39 VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache) 40 41 static const VMStateDescription vmstate_xmm_reg = { 42 .name = "xmm_reg", 43 .version_id = 1, 44 .minimum_version_id = 1, 45 .fields = (VMStateField[]) { 46 VMSTATE_UINT64(ZMM_Q(0), ZMMReg), 47 VMSTATE_UINT64(ZMM_Q(1), ZMMReg), 48 VMSTATE_END_OF_LIST() 49 } 50 }; 51 52 #define VMSTATE_XMM_REGS(_field, _state, _start) \ 53 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ 54 vmstate_xmm_reg, ZMMReg) 55 56 /* YMMH format is the same as XMM, but for bits 128-255 */ 57 static const VMStateDescription vmstate_ymmh_reg = { 58 .name = "ymmh_reg", 59 .version_id = 1, 60 .minimum_version_id = 1, 61 .fields = (VMStateField[]) { 62 VMSTATE_UINT64(ZMM_Q(2), ZMMReg), 63 VMSTATE_UINT64(ZMM_Q(3), ZMMReg), 64 VMSTATE_END_OF_LIST() 65 } 66 }; 67 68 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v) \ 69 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v, \ 70 vmstate_ymmh_reg, ZMMReg) 71 72 static const VMStateDescription vmstate_zmmh_reg = { 73 .name = "zmmh_reg", 74 .version_id = 1, 75 .minimum_version_id = 1, 76 .fields = (VMStateField[]) { 77 VMSTATE_UINT64(ZMM_Q(4), ZMMReg), 78 VMSTATE_UINT64(ZMM_Q(5), ZMMReg), 79 VMSTATE_UINT64(ZMM_Q(6), ZMMReg), 80 VMSTATE_UINT64(ZMM_Q(7), ZMMReg), 81 VMSTATE_END_OF_LIST() 82 } 83 }; 84 85 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \ 86 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ 87 vmstate_zmmh_reg, ZMMReg) 88 89 #ifdef TARGET_X86_64 90 static const VMStateDescription vmstate_hi16_zmm_reg = { 91 .name = "hi16_zmm_reg", 92 .version_id = 1, 93 .minimum_version_id = 1, 94 .fields = (VMStateField[]) { 95 VMSTATE_UINT64(ZMM_Q(0), ZMMReg), 96 VMSTATE_UINT64(ZMM_Q(1), ZMMReg), 97 VMSTATE_UINT64(ZMM_Q(2), ZMMReg), 98 VMSTATE_UINT64(ZMM_Q(3), ZMMReg), 99 VMSTATE_UINT64(ZMM_Q(4), ZMMReg), 100 VMSTATE_UINT64(ZMM_Q(5), ZMMReg), 101 VMSTATE_UINT64(ZMM_Q(6), ZMMReg), 102 VMSTATE_UINT64(ZMM_Q(7), ZMMReg), 103 VMSTATE_END_OF_LIST() 104 } 105 }; 106 107 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \ 108 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ 109 vmstate_hi16_zmm_reg, ZMMReg) 110 #endif 111 112 static const VMStateDescription vmstate_bnd_regs = { 113 .name = "bnd_regs", 114 .version_id = 1, 115 .minimum_version_id = 1, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT64(lb, BNDReg), 118 VMSTATE_UINT64(ub, BNDReg), 119 VMSTATE_END_OF_LIST() 120 } 121 }; 122 123 #define VMSTATE_BND_REGS(_field, _state, _n) \ 124 VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg) 125 126 static const VMStateDescription vmstate_mtrr_var = { 127 .name = "mtrr_var", 128 .version_id = 1, 129 .minimum_version_id = 1, 130 .fields = (VMStateField[]) { 131 VMSTATE_UINT64(base, MTRRVar), 132 VMSTATE_UINT64(mask, MTRRVar), 133 VMSTATE_END_OF_LIST() 134 } 135 }; 136 137 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \ 138 VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar) 139 140 typedef struct x86_FPReg_tmp { 141 FPReg *parent; 142 uint64_t tmp_mant; 143 uint16_t tmp_exp; 144 } x86_FPReg_tmp; 145 146 static void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f) 147 { 148 CPU_LDoubleU temp; 149 150 temp.d = f; 151 *pmant = temp.l.lower; 152 *pexp = temp.l.upper; 153 } 154 155 static floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper) 156 { 157 CPU_LDoubleU temp; 158 159 temp.l.upper = upper; 160 temp.l.lower = mant; 161 return temp.d; 162 } 163 164 static int fpreg_pre_save(void *opaque) 165 { 166 x86_FPReg_tmp *tmp = opaque; 167 168 /* we save the real CPU data (in case of MMX usage only 'mant' 169 contains the MMX register */ 170 cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d); 171 172 return 0; 173 } 174 175 static int fpreg_post_load(void *opaque, int version) 176 { 177 x86_FPReg_tmp *tmp = opaque; 178 179 tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp); 180 return 0; 181 } 182 183 static const VMStateDescription vmstate_fpreg_tmp = { 184 .name = "fpreg_tmp", 185 .post_load = fpreg_post_load, 186 .pre_save = fpreg_pre_save, 187 .fields = (VMStateField[]) { 188 VMSTATE_UINT64(tmp_mant, x86_FPReg_tmp), 189 VMSTATE_UINT16(tmp_exp, x86_FPReg_tmp), 190 VMSTATE_END_OF_LIST() 191 } 192 }; 193 194 static const VMStateDescription vmstate_fpreg = { 195 .name = "fpreg", 196 .fields = (VMStateField[]) { 197 VMSTATE_WITH_TMP(FPReg, x86_FPReg_tmp, vmstate_fpreg_tmp), 198 VMSTATE_END_OF_LIST() 199 } 200 }; 201 202 static int cpu_pre_save(void *opaque) 203 { 204 X86CPU *cpu = opaque; 205 CPUX86State *env = &cpu->env; 206 int i; 207 208 /* FPU */ 209 env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; 210 env->fptag_vmstate = 0; 211 for(i = 0; i < 8; i++) { 212 env->fptag_vmstate |= ((!env->fptags[i]) << i); 213 } 214 215 env->fpregs_format_vmstate = 0; 216 217 /* 218 * Real mode guest segments register DPL should be zero. 219 * Older KVM version were setting it wrongly. 220 * Fixing it will allow live migration to host with unrestricted guest 221 * support (otherwise the migration will fail with invalid guest state 222 * error). 223 */ 224 if (!(env->cr[0] & CR0_PE_MASK) && 225 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { 226 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); 227 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); 228 env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); 229 env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); 230 env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); 231 env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); 232 } 233 234 #ifdef CONFIG_KVM 235 /* Verify we have nested virtualization state from kernel if required */ 236 if (cpu_has_nested_virt(env) && !env->nested_state) { 237 error_report("Guest enabled nested virtualization but kernel " 238 "does not support saving of nested state"); 239 return -EINVAL; 240 } 241 #endif 242 243 return 0; 244 } 245 246 static int cpu_post_load(void *opaque, int version_id) 247 { 248 X86CPU *cpu = opaque; 249 CPUState *cs = CPU(cpu); 250 CPUX86State *env = &cpu->env; 251 int i; 252 253 if (env->tsc_khz && env->user_tsc_khz && 254 env->tsc_khz != env->user_tsc_khz) { 255 error_report("Mismatch between user-specified TSC frequency and " 256 "migrated TSC frequency"); 257 return -EINVAL; 258 } 259 260 if (env->fpregs_format_vmstate) { 261 error_report("Unsupported old non-softfloat CPU state"); 262 return -EINVAL; 263 } 264 /* 265 * Real mode guest segments register DPL should be zero. 266 * Older KVM version were setting it wrongly. 267 * Fixing it will allow live migration from such host that don't have 268 * restricted guest support to a host with unrestricted guest support 269 * (otherwise the migration will fail with invalid guest state 270 * error). 271 */ 272 if (!(env->cr[0] & CR0_PE_MASK) && 273 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { 274 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); 275 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); 276 env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); 277 env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); 278 env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); 279 env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); 280 } 281 282 /* Older versions of QEMU incorrectly used CS.DPL as the CPL when 283 * running under KVM. This is wrong for conforming code segments. 284 * Luckily, in our implementation the CPL field of hflags is redundant 285 * and we can get the right value from the SS descriptor privilege level. 286 */ 287 env->hflags &= ~HF_CPL_MASK; 288 env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 289 290 #ifdef CONFIG_KVM 291 if ((env->hflags & HF_GUEST_MASK) && 292 (!env->nested_state || 293 !(env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE))) { 294 error_report("vCPU set in guest-mode inconsistent with " 295 "migrated kernel nested state"); 296 return -EINVAL; 297 } 298 #endif 299 300 env->fpstt = (env->fpus_vmstate >> 11) & 7; 301 env->fpus = env->fpus_vmstate & ~0x3800; 302 env->fptag_vmstate ^= 0xff; 303 for(i = 0; i < 8; i++) { 304 env->fptags[i] = (env->fptag_vmstate >> i) & 1; 305 } 306 if (tcg_enabled()) { 307 target_ulong dr7; 308 update_fp_status(env); 309 update_mxcsr_status(env); 310 311 cpu_breakpoint_remove_all(cs, BP_CPU); 312 cpu_watchpoint_remove_all(cs, BP_CPU); 313 314 /* Indicate all breakpoints disabled, as they are, then 315 let the helper re-enable them. */ 316 dr7 = env->dr[7]; 317 env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK); 318 cpu_x86_update_dr7(env, dr7); 319 } 320 tlb_flush(cs); 321 return 0; 322 } 323 324 static bool async_pf_msr_needed(void *opaque) 325 { 326 X86CPU *cpu = opaque; 327 328 return cpu->env.async_pf_en_msr != 0; 329 } 330 331 static bool pv_eoi_msr_needed(void *opaque) 332 { 333 X86CPU *cpu = opaque; 334 335 return cpu->env.pv_eoi_en_msr != 0; 336 } 337 338 static bool steal_time_msr_needed(void *opaque) 339 { 340 X86CPU *cpu = opaque; 341 342 return cpu->env.steal_time_msr != 0; 343 } 344 345 static const VMStateDescription vmstate_steal_time_msr = { 346 .name = "cpu/steal_time_msr", 347 .version_id = 1, 348 .minimum_version_id = 1, 349 .needed = steal_time_msr_needed, 350 .fields = (VMStateField[]) { 351 VMSTATE_UINT64(env.steal_time_msr, X86CPU), 352 VMSTATE_END_OF_LIST() 353 } 354 }; 355 356 static const VMStateDescription vmstate_async_pf_msr = { 357 .name = "cpu/async_pf_msr", 358 .version_id = 1, 359 .minimum_version_id = 1, 360 .needed = async_pf_msr_needed, 361 .fields = (VMStateField[]) { 362 VMSTATE_UINT64(env.async_pf_en_msr, X86CPU), 363 VMSTATE_END_OF_LIST() 364 } 365 }; 366 367 static const VMStateDescription vmstate_pv_eoi_msr = { 368 .name = "cpu/async_pv_eoi_msr", 369 .version_id = 1, 370 .minimum_version_id = 1, 371 .needed = pv_eoi_msr_needed, 372 .fields = (VMStateField[]) { 373 VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU), 374 VMSTATE_END_OF_LIST() 375 } 376 }; 377 378 static bool fpop_ip_dp_needed(void *opaque) 379 { 380 X86CPU *cpu = opaque; 381 CPUX86State *env = &cpu->env; 382 383 return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; 384 } 385 386 static const VMStateDescription vmstate_fpop_ip_dp = { 387 .name = "cpu/fpop_ip_dp", 388 .version_id = 1, 389 .minimum_version_id = 1, 390 .needed = fpop_ip_dp_needed, 391 .fields = (VMStateField[]) { 392 VMSTATE_UINT16(env.fpop, X86CPU), 393 VMSTATE_UINT64(env.fpip, X86CPU), 394 VMSTATE_UINT64(env.fpdp, X86CPU), 395 VMSTATE_END_OF_LIST() 396 } 397 }; 398 399 static bool tsc_adjust_needed(void *opaque) 400 { 401 X86CPU *cpu = opaque; 402 CPUX86State *env = &cpu->env; 403 404 return env->tsc_adjust != 0; 405 } 406 407 static const VMStateDescription vmstate_msr_tsc_adjust = { 408 .name = "cpu/msr_tsc_adjust", 409 .version_id = 1, 410 .minimum_version_id = 1, 411 .needed = tsc_adjust_needed, 412 .fields = (VMStateField[]) { 413 VMSTATE_UINT64(env.tsc_adjust, X86CPU), 414 VMSTATE_END_OF_LIST() 415 } 416 }; 417 418 static bool msr_smi_count_needed(void *opaque) 419 { 420 X86CPU *cpu = opaque; 421 CPUX86State *env = &cpu->env; 422 423 return cpu->migrate_smi_count && env->msr_smi_count != 0; 424 } 425 426 static const VMStateDescription vmstate_msr_smi_count = { 427 .name = "cpu/msr_smi_count", 428 .version_id = 1, 429 .minimum_version_id = 1, 430 .needed = msr_smi_count_needed, 431 .fields = (VMStateField[]) { 432 VMSTATE_UINT64(env.msr_smi_count, X86CPU), 433 VMSTATE_END_OF_LIST() 434 } 435 }; 436 437 static bool tscdeadline_needed(void *opaque) 438 { 439 X86CPU *cpu = opaque; 440 CPUX86State *env = &cpu->env; 441 442 return env->tsc_deadline != 0; 443 } 444 445 static const VMStateDescription vmstate_msr_tscdeadline = { 446 .name = "cpu/msr_tscdeadline", 447 .version_id = 1, 448 .minimum_version_id = 1, 449 .needed = tscdeadline_needed, 450 .fields = (VMStateField[]) { 451 VMSTATE_UINT64(env.tsc_deadline, X86CPU), 452 VMSTATE_END_OF_LIST() 453 } 454 }; 455 456 static bool misc_enable_needed(void *opaque) 457 { 458 X86CPU *cpu = opaque; 459 CPUX86State *env = &cpu->env; 460 461 return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT; 462 } 463 464 static bool feature_control_needed(void *opaque) 465 { 466 X86CPU *cpu = opaque; 467 CPUX86State *env = &cpu->env; 468 469 return env->msr_ia32_feature_control != 0; 470 } 471 472 static const VMStateDescription vmstate_msr_ia32_misc_enable = { 473 .name = "cpu/msr_ia32_misc_enable", 474 .version_id = 1, 475 .minimum_version_id = 1, 476 .needed = misc_enable_needed, 477 .fields = (VMStateField[]) { 478 VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU), 479 VMSTATE_END_OF_LIST() 480 } 481 }; 482 483 static const VMStateDescription vmstate_msr_ia32_feature_control = { 484 .name = "cpu/msr_ia32_feature_control", 485 .version_id = 1, 486 .minimum_version_id = 1, 487 .needed = feature_control_needed, 488 .fields = (VMStateField[]) { 489 VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU), 490 VMSTATE_END_OF_LIST() 491 } 492 }; 493 494 static bool pmu_enable_needed(void *opaque) 495 { 496 X86CPU *cpu = opaque; 497 CPUX86State *env = &cpu->env; 498 int i; 499 500 if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl || 501 env->msr_global_status || env->msr_global_ovf_ctrl) { 502 return true; 503 } 504 for (i = 0; i < MAX_FIXED_COUNTERS; i++) { 505 if (env->msr_fixed_counters[i]) { 506 return true; 507 } 508 } 509 for (i = 0; i < MAX_GP_COUNTERS; i++) { 510 if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) { 511 return true; 512 } 513 } 514 515 return false; 516 } 517 518 static const VMStateDescription vmstate_msr_architectural_pmu = { 519 .name = "cpu/msr_architectural_pmu", 520 .version_id = 1, 521 .minimum_version_id = 1, 522 .needed = pmu_enable_needed, 523 .fields = (VMStateField[]) { 524 VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), 525 VMSTATE_UINT64(env.msr_global_ctrl, X86CPU), 526 VMSTATE_UINT64(env.msr_global_status, X86CPU), 527 VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU), 528 VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS), 529 VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), 530 VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), 531 VMSTATE_END_OF_LIST() 532 } 533 }; 534 535 static bool mpx_needed(void *opaque) 536 { 537 X86CPU *cpu = opaque; 538 CPUX86State *env = &cpu->env; 539 unsigned int i; 540 541 for (i = 0; i < 4; i++) { 542 if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) { 543 return true; 544 } 545 } 546 547 if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) { 548 return true; 549 } 550 551 return !!env->msr_bndcfgs; 552 } 553 554 static const VMStateDescription vmstate_mpx = { 555 .name = "cpu/mpx", 556 .version_id = 1, 557 .minimum_version_id = 1, 558 .needed = mpx_needed, 559 .fields = (VMStateField[]) { 560 VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4), 561 VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU), 562 VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU), 563 VMSTATE_UINT64(env.msr_bndcfgs, X86CPU), 564 VMSTATE_END_OF_LIST() 565 } 566 }; 567 568 static bool hyperv_hypercall_enable_needed(void *opaque) 569 { 570 X86CPU *cpu = opaque; 571 CPUX86State *env = &cpu->env; 572 573 return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0; 574 } 575 576 static const VMStateDescription vmstate_msr_hypercall_hypercall = { 577 .name = "cpu/msr_hyperv_hypercall", 578 .version_id = 1, 579 .minimum_version_id = 1, 580 .needed = hyperv_hypercall_enable_needed, 581 .fields = (VMStateField[]) { 582 VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU), 583 VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU), 584 VMSTATE_END_OF_LIST() 585 } 586 }; 587 588 static bool hyperv_vapic_enable_needed(void *opaque) 589 { 590 X86CPU *cpu = opaque; 591 CPUX86State *env = &cpu->env; 592 593 return env->msr_hv_vapic != 0; 594 } 595 596 static const VMStateDescription vmstate_msr_hyperv_vapic = { 597 .name = "cpu/msr_hyperv_vapic", 598 .version_id = 1, 599 .minimum_version_id = 1, 600 .needed = hyperv_vapic_enable_needed, 601 .fields = (VMStateField[]) { 602 VMSTATE_UINT64(env.msr_hv_vapic, X86CPU), 603 VMSTATE_END_OF_LIST() 604 } 605 }; 606 607 static bool hyperv_time_enable_needed(void *opaque) 608 { 609 X86CPU *cpu = opaque; 610 CPUX86State *env = &cpu->env; 611 612 return env->msr_hv_tsc != 0; 613 } 614 615 static const VMStateDescription vmstate_msr_hyperv_time = { 616 .name = "cpu/msr_hyperv_time", 617 .version_id = 1, 618 .minimum_version_id = 1, 619 .needed = hyperv_time_enable_needed, 620 .fields = (VMStateField[]) { 621 VMSTATE_UINT64(env.msr_hv_tsc, X86CPU), 622 VMSTATE_END_OF_LIST() 623 } 624 }; 625 626 static bool hyperv_crash_enable_needed(void *opaque) 627 { 628 X86CPU *cpu = opaque; 629 CPUX86State *env = &cpu->env; 630 int i; 631 632 for (i = 0; i < HV_CRASH_PARAMS; i++) { 633 if (env->msr_hv_crash_params[i]) { 634 return true; 635 } 636 } 637 return false; 638 } 639 640 static const VMStateDescription vmstate_msr_hyperv_crash = { 641 .name = "cpu/msr_hyperv_crash", 642 .version_id = 1, 643 .minimum_version_id = 1, 644 .needed = hyperv_crash_enable_needed, 645 .fields = (VMStateField[]) { 646 VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params, X86CPU, HV_CRASH_PARAMS), 647 VMSTATE_END_OF_LIST() 648 } 649 }; 650 651 static bool hyperv_runtime_enable_needed(void *opaque) 652 { 653 X86CPU *cpu = opaque; 654 CPUX86State *env = &cpu->env; 655 656 if (!hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) { 657 return false; 658 } 659 660 return env->msr_hv_runtime != 0; 661 } 662 663 static const VMStateDescription vmstate_msr_hyperv_runtime = { 664 .name = "cpu/msr_hyperv_runtime", 665 .version_id = 1, 666 .minimum_version_id = 1, 667 .needed = hyperv_runtime_enable_needed, 668 .fields = (VMStateField[]) { 669 VMSTATE_UINT64(env.msr_hv_runtime, X86CPU), 670 VMSTATE_END_OF_LIST() 671 } 672 }; 673 674 static bool hyperv_synic_enable_needed(void *opaque) 675 { 676 X86CPU *cpu = opaque; 677 CPUX86State *env = &cpu->env; 678 int i; 679 680 if (env->msr_hv_synic_control != 0 || 681 env->msr_hv_synic_evt_page != 0 || 682 env->msr_hv_synic_msg_page != 0) { 683 return true; 684 } 685 686 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { 687 if (env->msr_hv_synic_sint[i] != 0) { 688 return true; 689 } 690 } 691 692 return false; 693 } 694 695 static int hyperv_synic_post_load(void *opaque, int version_id) 696 { 697 X86CPU *cpu = opaque; 698 hyperv_x86_synic_update(cpu); 699 return 0; 700 } 701 702 static const VMStateDescription vmstate_msr_hyperv_synic = { 703 .name = "cpu/msr_hyperv_synic", 704 .version_id = 1, 705 .minimum_version_id = 1, 706 .needed = hyperv_synic_enable_needed, 707 .post_load = hyperv_synic_post_load, 708 .fields = (VMStateField[]) { 709 VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU), 710 VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU), 711 VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU), 712 VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU, HV_SINT_COUNT), 713 VMSTATE_END_OF_LIST() 714 } 715 }; 716 717 static bool hyperv_stimer_enable_needed(void *opaque) 718 { 719 X86CPU *cpu = opaque; 720 CPUX86State *env = &cpu->env; 721 int i; 722 723 for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) { 724 if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) { 725 return true; 726 } 727 } 728 return false; 729 } 730 731 static const VMStateDescription vmstate_msr_hyperv_stimer = { 732 .name = "cpu/msr_hyperv_stimer", 733 .version_id = 1, 734 .minimum_version_id = 1, 735 .needed = hyperv_stimer_enable_needed, 736 .fields = (VMStateField[]) { 737 VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config, X86CPU, 738 HV_STIMER_COUNT), 739 VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count, X86CPU, HV_STIMER_COUNT), 740 VMSTATE_END_OF_LIST() 741 } 742 }; 743 744 static bool hyperv_reenlightenment_enable_needed(void *opaque) 745 { 746 X86CPU *cpu = opaque; 747 CPUX86State *env = &cpu->env; 748 749 return env->msr_hv_reenlightenment_control != 0 || 750 env->msr_hv_tsc_emulation_control != 0 || 751 env->msr_hv_tsc_emulation_status != 0; 752 } 753 754 static const VMStateDescription vmstate_msr_hyperv_reenlightenment = { 755 .name = "cpu/msr_hyperv_reenlightenment", 756 .version_id = 1, 757 .minimum_version_id = 1, 758 .needed = hyperv_reenlightenment_enable_needed, 759 .fields = (VMStateField[]) { 760 VMSTATE_UINT64(env.msr_hv_reenlightenment_control, X86CPU), 761 VMSTATE_UINT64(env.msr_hv_tsc_emulation_control, X86CPU), 762 VMSTATE_UINT64(env.msr_hv_tsc_emulation_status, X86CPU), 763 VMSTATE_END_OF_LIST() 764 } 765 }; 766 767 static bool avx512_needed(void *opaque) 768 { 769 X86CPU *cpu = opaque; 770 CPUX86State *env = &cpu->env; 771 unsigned int i; 772 773 for (i = 0; i < NB_OPMASK_REGS; i++) { 774 if (env->opmask_regs[i]) { 775 return true; 776 } 777 } 778 779 for (i = 0; i < CPU_NB_REGS; i++) { 780 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field)) 781 if (ENV_XMM(i, 4) || ENV_XMM(i, 6) || 782 ENV_XMM(i, 5) || ENV_XMM(i, 7)) { 783 return true; 784 } 785 #ifdef TARGET_X86_64 786 if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) || 787 ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) || 788 ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) || 789 ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) { 790 return true; 791 } 792 #endif 793 } 794 795 return false; 796 } 797 798 static const VMStateDescription vmstate_avx512 = { 799 .name = "cpu/avx512", 800 .version_id = 1, 801 .minimum_version_id = 1, 802 .needed = avx512_needed, 803 .fields = (VMStateField[]) { 804 VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS), 805 VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0), 806 #ifdef TARGET_X86_64 807 VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16), 808 #endif 809 VMSTATE_END_OF_LIST() 810 } 811 }; 812 813 static bool xss_needed(void *opaque) 814 { 815 X86CPU *cpu = opaque; 816 CPUX86State *env = &cpu->env; 817 818 return env->xss != 0; 819 } 820 821 static const VMStateDescription vmstate_xss = { 822 .name = "cpu/xss", 823 .version_id = 1, 824 .minimum_version_id = 1, 825 .needed = xss_needed, 826 .fields = (VMStateField[]) { 827 VMSTATE_UINT64(env.xss, X86CPU), 828 VMSTATE_END_OF_LIST() 829 } 830 }; 831 832 #ifdef TARGET_X86_64 833 static bool pkru_needed(void *opaque) 834 { 835 X86CPU *cpu = opaque; 836 CPUX86State *env = &cpu->env; 837 838 return env->pkru != 0; 839 } 840 841 static const VMStateDescription vmstate_pkru = { 842 .name = "cpu/pkru", 843 .version_id = 1, 844 .minimum_version_id = 1, 845 .needed = pkru_needed, 846 .fields = (VMStateField[]){ 847 VMSTATE_UINT32(env.pkru, X86CPU), 848 VMSTATE_END_OF_LIST() 849 } 850 }; 851 #endif 852 853 static bool tsc_khz_needed(void *opaque) 854 { 855 X86CPU *cpu = opaque; 856 CPUX86State *env = &cpu->env; 857 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 858 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc); 859 return env->tsc_khz && pcmc->save_tsc_khz; 860 } 861 862 static const VMStateDescription vmstate_tsc_khz = { 863 .name = "cpu/tsc_khz", 864 .version_id = 1, 865 .minimum_version_id = 1, 866 .needed = tsc_khz_needed, 867 .fields = (VMStateField[]) { 868 VMSTATE_INT64(env.tsc_khz, X86CPU), 869 VMSTATE_END_OF_LIST() 870 } 871 }; 872 873 #ifdef CONFIG_KVM 874 875 static bool vmx_vmcs12_needed(void *opaque) 876 { 877 struct kvm_nested_state *nested_state = opaque; 878 return (nested_state->size > 879 offsetof(struct kvm_nested_state, data.vmx[0].vmcs12)); 880 } 881 882 static const VMStateDescription vmstate_vmx_vmcs12 = { 883 .name = "cpu/kvm_nested_state/vmx/vmcs12", 884 .version_id = 1, 885 .minimum_version_id = 1, 886 .needed = vmx_vmcs12_needed, 887 .fields = (VMStateField[]) { 888 VMSTATE_UINT8_ARRAY(data.vmx[0].vmcs12, 889 struct kvm_nested_state, 890 KVM_STATE_NESTED_VMX_VMCS_SIZE), 891 VMSTATE_END_OF_LIST() 892 } 893 }; 894 895 static bool vmx_shadow_vmcs12_needed(void *opaque) 896 { 897 struct kvm_nested_state *nested_state = opaque; 898 return (nested_state->size > 899 offsetof(struct kvm_nested_state, data.vmx[0].shadow_vmcs12)); 900 } 901 902 static const VMStateDescription vmstate_vmx_shadow_vmcs12 = { 903 .name = "cpu/kvm_nested_state/vmx/shadow_vmcs12", 904 .version_id = 1, 905 .minimum_version_id = 1, 906 .needed = vmx_shadow_vmcs12_needed, 907 .fields = (VMStateField[]) { 908 VMSTATE_UINT8_ARRAY(data.vmx[0].shadow_vmcs12, 909 struct kvm_nested_state, 910 KVM_STATE_NESTED_VMX_VMCS_SIZE), 911 VMSTATE_END_OF_LIST() 912 } 913 }; 914 915 static bool vmx_nested_state_needed(void *opaque) 916 { 917 struct kvm_nested_state *nested_state = opaque; 918 919 return ((nested_state->format == KVM_STATE_NESTED_FORMAT_VMX) && 920 ((nested_state->hdr.vmx.vmxon_pa != -1ull) || 921 (nested_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))); 922 } 923 924 static const VMStateDescription vmstate_vmx_nested_state = { 925 .name = "cpu/kvm_nested_state/vmx", 926 .version_id = 1, 927 .minimum_version_id = 1, 928 .needed = vmx_nested_state_needed, 929 .fields = (VMStateField[]) { 930 VMSTATE_U64(hdr.vmx.vmxon_pa, struct kvm_nested_state), 931 VMSTATE_U64(hdr.vmx.vmcs12_pa, struct kvm_nested_state), 932 VMSTATE_U16(hdr.vmx.smm.flags, struct kvm_nested_state), 933 VMSTATE_END_OF_LIST() 934 }, 935 .subsections = (const VMStateDescription*[]) { 936 &vmstate_vmx_vmcs12, 937 &vmstate_vmx_shadow_vmcs12, 938 NULL, 939 } 940 }; 941 942 static bool svm_nested_state_needed(void *opaque) 943 { 944 struct kvm_nested_state *nested_state = opaque; 945 946 return (nested_state->format == KVM_STATE_NESTED_FORMAT_SVM); 947 } 948 949 static const VMStateDescription vmstate_svm_nested_state = { 950 .name = "cpu/kvm_nested_state/svm", 951 .version_id = 1, 952 .minimum_version_id = 1, 953 .needed = svm_nested_state_needed, 954 .fields = (VMStateField[]) { 955 VMSTATE_END_OF_LIST() 956 } 957 }; 958 959 static bool nested_state_needed(void *opaque) 960 { 961 X86CPU *cpu = opaque; 962 CPUX86State *env = &cpu->env; 963 964 return (env->nested_state && 965 (vmx_nested_state_needed(env->nested_state) || 966 svm_nested_state_needed(env->nested_state))); 967 } 968 969 static int nested_state_post_load(void *opaque, int version_id) 970 { 971 X86CPU *cpu = opaque; 972 CPUX86State *env = &cpu->env; 973 struct kvm_nested_state *nested_state = env->nested_state; 974 int min_nested_state_len = offsetof(struct kvm_nested_state, data); 975 int max_nested_state_len = kvm_max_nested_state_length(); 976 977 /* 978 * If our kernel don't support setting nested state 979 * and we have received nested state from migration stream, 980 * we need to fail migration 981 */ 982 if (max_nested_state_len <= 0) { 983 error_report("Received nested state when kernel cannot restore it"); 984 return -EINVAL; 985 } 986 987 /* 988 * Verify that the size of received nested_state struct 989 * at least cover required header and is not larger 990 * than the max size that our kernel support 991 */ 992 if (nested_state->size < min_nested_state_len) { 993 error_report("Received nested state size less than min: " 994 "len=%d, min=%d", 995 nested_state->size, min_nested_state_len); 996 return -EINVAL; 997 } 998 if (nested_state->size > max_nested_state_len) { 999 error_report("Recieved unsupported nested state size: " 1000 "nested_state->size=%d, max=%d", 1001 nested_state->size, max_nested_state_len); 1002 return -EINVAL; 1003 } 1004 1005 /* Verify format is valid */ 1006 if ((nested_state->format != KVM_STATE_NESTED_FORMAT_VMX) && 1007 (nested_state->format != KVM_STATE_NESTED_FORMAT_SVM)) { 1008 error_report("Received invalid nested state format: %d", 1009 nested_state->format); 1010 return -EINVAL; 1011 } 1012 1013 return 0; 1014 } 1015 1016 static const VMStateDescription vmstate_kvm_nested_state = { 1017 .name = "cpu/kvm_nested_state", 1018 .version_id = 1, 1019 .minimum_version_id = 1, 1020 .fields = (VMStateField[]) { 1021 VMSTATE_U16(flags, struct kvm_nested_state), 1022 VMSTATE_U16(format, struct kvm_nested_state), 1023 VMSTATE_U32(size, struct kvm_nested_state), 1024 VMSTATE_END_OF_LIST() 1025 }, 1026 .subsections = (const VMStateDescription*[]) { 1027 &vmstate_vmx_nested_state, 1028 &vmstate_svm_nested_state, 1029 NULL 1030 } 1031 }; 1032 1033 static const VMStateDescription vmstate_nested_state = { 1034 .name = "cpu/nested_state", 1035 .version_id = 1, 1036 .minimum_version_id = 1, 1037 .needed = nested_state_needed, 1038 .post_load = nested_state_post_load, 1039 .fields = (VMStateField[]) { 1040 VMSTATE_STRUCT_POINTER(env.nested_state, X86CPU, 1041 vmstate_kvm_nested_state, 1042 struct kvm_nested_state), 1043 VMSTATE_END_OF_LIST() 1044 } 1045 }; 1046 1047 #endif 1048 1049 static bool mcg_ext_ctl_needed(void *opaque) 1050 { 1051 X86CPU *cpu = opaque; 1052 CPUX86State *env = &cpu->env; 1053 return cpu->enable_lmce && env->mcg_ext_ctl; 1054 } 1055 1056 static const VMStateDescription vmstate_mcg_ext_ctl = { 1057 .name = "cpu/mcg_ext_ctl", 1058 .version_id = 1, 1059 .minimum_version_id = 1, 1060 .needed = mcg_ext_ctl_needed, 1061 .fields = (VMStateField[]) { 1062 VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU), 1063 VMSTATE_END_OF_LIST() 1064 } 1065 }; 1066 1067 static bool spec_ctrl_needed(void *opaque) 1068 { 1069 X86CPU *cpu = opaque; 1070 CPUX86State *env = &cpu->env; 1071 1072 return env->spec_ctrl != 0; 1073 } 1074 1075 static const VMStateDescription vmstate_spec_ctrl = { 1076 .name = "cpu/spec_ctrl", 1077 .version_id = 1, 1078 .minimum_version_id = 1, 1079 .needed = spec_ctrl_needed, 1080 .fields = (VMStateField[]){ 1081 VMSTATE_UINT64(env.spec_ctrl, X86CPU), 1082 VMSTATE_END_OF_LIST() 1083 } 1084 }; 1085 1086 static bool intel_pt_enable_needed(void *opaque) 1087 { 1088 X86CPU *cpu = opaque; 1089 CPUX86State *env = &cpu->env; 1090 int i; 1091 1092 if (env->msr_rtit_ctrl || env->msr_rtit_status || 1093 env->msr_rtit_output_base || env->msr_rtit_output_mask || 1094 env->msr_rtit_cr3_match) { 1095 return true; 1096 } 1097 1098 for (i = 0; i < MAX_RTIT_ADDRS; i++) { 1099 if (env->msr_rtit_addrs[i]) { 1100 return true; 1101 } 1102 } 1103 1104 return false; 1105 } 1106 1107 static const VMStateDescription vmstate_msr_intel_pt = { 1108 .name = "cpu/intel_pt", 1109 .version_id = 1, 1110 .minimum_version_id = 1, 1111 .needed = intel_pt_enable_needed, 1112 .fields = (VMStateField[]) { 1113 VMSTATE_UINT64(env.msr_rtit_ctrl, X86CPU), 1114 VMSTATE_UINT64(env.msr_rtit_status, X86CPU), 1115 VMSTATE_UINT64(env.msr_rtit_output_base, X86CPU), 1116 VMSTATE_UINT64(env.msr_rtit_output_mask, X86CPU), 1117 VMSTATE_UINT64(env.msr_rtit_cr3_match, X86CPU), 1118 VMSTATE_UINT64_ARRAY(env.msr_rtit_addrs, X86CPU, MAX_RTIT_ADDRS), 1119 VMSTATE_END_OF_LIST() 1120 } 1121 }; 1122 1123 static bool virt_ssbd_needed(void *opaque) 1124 { 1125 X86CPU *cpu = opaque; 1126 CPUX86State *env = &cpu->env; 1127 1128 return env->virt_ssbd != 0; 1129 } 1130 1131 static const VMStateDescription vmstate_msr_virt_ssbd = { 1132 .name = "cpu/virt_ssbd", 1133 .version_id = 1, 1134 .minimum_version_id = 1, 1135 .needed = virt_ssbd_needed, 1136 .fields = (VMStateField[]){ 1137 VMSTATE_UINT64(env.virt_ssbd, X86CPU), 1138 VMSTATE_END_OF_LIST() 1139 } 1140 }; 1141 1142 static bool svm_npt_needed(void *opaque) 1143 { 1144 X86CPU *cpu = opaque; 1145 CPUX86State *env = &cpu->env; 1146 1147 return !!(env->hflags2 & HF2_NPT_MASK); 1148 } 1149 1150 static const VMStateDescription vmstate_svm_npt = { 1151 .name = "cpu/svn_npt", 1152 .version_id = 1, 1153 .minimum_version_id = 1, 1154 .needed = svm_npt_needed, 1155 .fields = (VMStateField[]){ 1156 VMSTATE_UINT64(env.nested_cr3, X86CPU), 1157 VMSTATE_UINT32(env.nested_pg_mode, X86CPU), 1158 VMSTATE_END_OF_LIST() 1159 } 1160 }; 1161 1162 #ifndef TARGET_X86_64 1163 static bool intel_efer32_needed(void *opaque) 1164 { 1165 X86CPU *cpu = opaque; 1166 CPUX86State *env = &cpu->env; 1167 1168 return env->efer != 0; 1169 } 1170 1171 static const VMStateDescription vmstate_efer32 = { 1172 .name = "cpu/efer32", 1173 .version_id = 1, 1174 .minimum_version_id = 1, 1175 .needed = intel_efer32_needed, 1176 .fields = (VMStateField[]) { 1177 VMSTATE_UINT64(env.efer, X86CPU), 1178 VMSTATE_END_OF_LIST() 1179 } 1180 }; 1181 #endif 1182 1183 VMStateDescription vmstate_x86_cpu = { 1184 .name = "cpu", 1185 .version_id = 12, 1186 .minimum_version_id = 11, 1187 .pre_save = cpu_pre_save, 1188 .post_load = cpu_post_load, 1189 .fields = (VMStateField[]) { 1190 VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS), 1191 VMSTATE_UINTTL(env.eip, X86CPU), 1192 VMSTATE_UINTTL(env.eflags, X86CPU), 1193 VMSTATE_UINT32(env.hflags, X86CPU), 1194 /* FPU */ 1195 VMSTATE_UINT16(env.fpuc, X86CPU), 1196 VMSTATE_UINT16(env.fpus_vmstate, X86CPU), 1197 VMSTATE_UINT16(env.fptag_vmstate, X86CPU), 1198 VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU), 1199 1200 VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg), 1201 1202 VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6), 1203 VMSTATE_SEGMENT(env.ldt, X86CPU), 1204 VMSTATE_SEGMENT(env.tr, X86CPU), 1205 VMSTATE_SEGMENT(env.gdt, X86CPU), 1206 VMSTATE_SEGMENT(env.idt, X86CPU), 1207 1208 VMSTATE_UINT32(env.sysenter_cs, X86CPU), 1209 VMSTATE_UINTTL(env.sysenter_esp, X86CPU), 1210 VMSTATE_UINTTL(env.sysenter_eip, X86CPU), 1211 1212 VMSTATE_UINTTL(env.cr[0], X86CPU), 1213 VMSTATE_UINTTL(env.cr[2], X86CPU), 1214 VMSTATE_UINTTL(env.cr[3], X86CPU), 1215 VMSTATE_UINTTL(env.cr[4], X86CPU), 1216 VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8), 1217 /* MMU */ 1218 VMSTATE_INT32(env.a20_mask, X86CPU), 1219 /* XMM */ 1220 VMSTATE_UINT32(env.mxcsr, X86CPU), 1221 VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0), 1222 1223 #ifdef TARGET_X86_64 1224 VMSTATE_UINT64(env.efer, X86CPU), 1225 VMSTATE_UINT64(env.star, X86CPU), 1226 VMSTATE_UINT64(env.lstar, X86CPU), 1227 VMSTATE_UINT64(env.cstar, X86CPU), 1228 VMSTATE_UINT64(env.fmask, X86CPU), 1229 VMSTATE_UINT64(env.kernelgsbase, X86CPU), 1230 #endif 1231 VMSTATE_UINT32(env.smbase, X86CPU), 1232 1233 VMSTATE_UINT64(env.pat, X86CPU), 1234 VMSTATE_UINT32(env.hflags2, X86CPU), 1235 1236 VMSTATE_UINT64(env.vm_hsave, X86CPU), 1237 VMSTATE_UINT64(env.vm_vmcb, X86CPU), 1238 VMSTATE_UINT64(env.tsc_offset, X86CPU), 1239 VMSTATE_UINT64(env.intercept, X86CPU), 1240 VMSTATE_UINT16(env.intercept_cr_read, X86CPU), 1241 VMSTATE_UINT16(env.intercept_cr_write, X86CPU), 1242 VMSTATE_UINT16(env.intercept_dr_read, X86CPU), 1243 VMSTATE_UINT16(env.intercept_dr_write, X86CPU), 1244 VMSTATE_UINT32(env.intercept_exceptions, X86CPU), 1245 VMSTATE_UINT8(env.v_tpr, X86CPU), 1246 /* MTRRs */ 1247 VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11), 1248 VMSTATE_UINT64(env.mtrr_deftype, X86CPU), 1249 VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8), 1250 /* KVM-related states */ 1251 VMSTATE_INT32(env.interrupt_injected, X86CPU), 1252 VMSTATE_UINT32(env.mp_state, X86CPU), 1253 VMSTATE_UINT64(env.tsc, X86CPU), 1254 VMSTATE_INT32(env.exception_injected, X86CPU), 1255 VMSTATE_UINT8(env.soft_interrupt, X86CPU), 1256 VMSTATE_UINT8(env.nmi_injected, X86CPU), 1257 VMSTATE_UINT8(env.nmi_pending, X86CPU), 1258 VMSTATE_UINT8(env.has_error_code, X86CPU), 1259 VMSTATE_UINT32(env.sipi_vector, X86CPU), 1260 /* MCE */ 1261 VMSTATE_UINT64(env.mcg_cap, X86CPU), 1262 VMSTATE_UINT64(env.mcg_status, X86CPU), 1263 VMSTATE_UINT64(env.mcg_ctl, X86CPU), 1264 VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4), 1265 /* rdtscp */ 1266 VMSTATE_UINT64(env.tsc_aux, X86CPU), 1267 /* KVM pvclock msr */ 1268 VMSTATE_UINT64(env.system_time_msr, X86CPU), 1269 VMSTATE_UINT64(env.wall_clock_msr, X86CPU), 1270 /* XSAVE related fields */ 1271 VMSTATE_UINT64_V(env.xcr0, X86CPU, 12), 1272 VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12), 1273 VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12), 1274 VMSTATE_END_OF_LIST() 1275 /* The above list is not sorted /wrt version numbers, watch out! */ 1276 }, 1277 .subsections = (const VMStateDescription*[]) { 1278 &vmstate_async_pf_msr, 1279 &vmstate_pv_eoi_msr, 1280 &vmstate_steal_time_msr, 1281 &vmstate_fpop_ip_dp, 1282 &vmstate_msr_tsc_adjust, 1283 &vmstate_msr_tscdeadline, 1284 &vmstate_msr_ia32_misc_enable, 1285 &vmstate_msr_ia32_feature_control, 1286 &vmstate_msr_architectural_pmu, 1287 &vmstate_mpx, 1288 &vmstate_msr_hypercall_hypercall, 1289 &vmstate_msr_hyperv_vapic, 1290 &vmstate_msr_hyperv_time, 1291 &vmstate_msr_hyperv_crash, 1292 &vmstate_msr_hyperv_runtime, 1293 &vmstate_msr_hyperv_synic, 1294 &vmstate_msr_hyperv_stimer, 1295 &vmstate_msr_hyperv_reenlightenment, 1296 &vmstate_avx512, 1297 &vmstate_xss, 1298 &vmstate_tsc_khz, 1299 &vmstate_msr_smi_count, 1300 #ifdef TARGET_X86_64 1301 &vmstate_pkru, 1302 #endif 1303 &vmstate_spec_ctrl, 1304 &vmstate_mcg_ext_ctl, 1305 &vmstate_msr_intel_pt, 1306 &vmstate_msr_virt_ssbd, 1307 &vmstate_svm_npt, 1308 #ifndef TARGET_X86_64 1309 &vmstate_efer32, 1310 #endif 1311 #ifdef CONFIG_KVM 1312 &vmstate_nested_state, 1313 #endif 1314 NULL 1315 } 1316 }; 1317