1 #include "qemu/osdep.h" 2 #include "cpu.h" 3 #include "exec/exec-all.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "hw/i386/pc.h" 7 #include "hw/isa/isa.h" 8 #include "migration/cpu.h" 9 #include "hyperv.h" 10 11 #include "sysemu/kvm.h" 12 #include "sysemu/tcg.h" 13 14 #include "qemu/error-report.h" 15 16 static const VMStateDescription vmstate_segment = { 17 .name = "segment", 18 .version_id = 1, 19 .minimum_version_id = 1, 20 .fields = (VMStateField[]) { 21 VMSTATE_UINT32(selector, SegmentCache), 22 VMSTATE_UINTTL(base, SegmentCache), 23 VMSTATE_UINT32(limit, SegmentCache), 24 VMSTATE_UINT32(flags, SegmentCache), 25 VMSTATE_END_OF_LIST() 26 } 27 }; 28 29 #define VMSTATE_SEGMENT(_field, _state) { \ 30 .name = (stringify(_field)), \ 31 .size = sizeof(SegmentCache), \ 32 .vmsd = &vmstate_segment, \ 33 .flags = VMS_STRUCT, \ 34 .offset = offsetof(_state, _field) \ 35 + type_check(SegmentCache,typeof_field(_state, _field)) \ 36 } 37 38 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \ 39 VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache) 40 41 static const VMStateDescription vmstate_xmm_reg = { 42 .name = "xmm_reg", 43 .version_id = 1, 44 .minimum_version_id = 1, 45 .fields = (VMStateField[]) { 46 VMSTATE_UINT64(ZMM_Q(0), ZMMReg), 47 VMSTATE_UINT64(ZMM_Q(1), ZMMReg), 48 VMSTATE_END_OF_LIST() 49 } 50 }; 51 52 #define VMSTATE_XMM_REGS(_field, _state, _start) \ 53 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ 54 vmstate_xmm_reg, ZMMReg) 55 56 /* YMMH format is the same as XMM, but for bits 128-255 */ 57 static const VMStateDescription vmstate_ymmh_reg = { 58 .name = "ymmh_reg", 59 .version_id = 1, 60 .minimum_version_id = 1, 61 .fields = (VMStateField[]) { 62 VMSTATE_UINT64(ZMM_Q(2), ZMMReg), 63 VMSTATE_UINT64(ZMM_Q(3), ZMMReg), 64 VMSTATE_END_OF_LIST() 65 } 66 }; 67 68 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v) \ 69 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v, \ 70 vmstate_ymmh_reg, ZMMReg) 71 72 static const VMStateDescription vmstate_zmmh_reg = { 73 .name = "zmmh_reg", 74 .version_id = 1, 75 .minimum_version_id = 1, 76 .fields = (VMStateField[]) { 77 VMSTATE_UINT64(ZMM_Q(4), ZMMReg), 78 VMSTATE_UINT64(ZMM_Q(5), ZMMReg), 79 VMSTATE_UINT64(ZMM_Q(6), ZMMReg), 80 VMSTATE_UINT64(ZMM_Q(7), ZMMReg), 81 VMSTATE_END_OF_LIST() 82 } 83 }; 84 85 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \ 86 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ 87 vmstate_zmmh_reg, ZMMReg) 88 89 #ifdef TARGET_X86_64 90 static const VMStateDescription vmstate_hi16_zmm_reg = { 91 .name = "hi16_zmm_reg", 92 .version_id = 1, 93 .minimum_version_id = 1, 94 .fields = (VMStateField[]) { 95 VMSTATE_UINT64(ZMM_Q(0), ZMMReg), 96 VMSTATE_UINT64(ZMM_Q(1), ZMMReg), 97 VMSTATE_UINT64(ZMM_Q(2), ZMMReg), 98 VMSTATE_UINT64(ZMM_Q(3), ZMMReg), 99 VMSTATE_UINT64(ZMM_Q(4), ZMMReg), 100 VMSTATE_UINT64(ZMM_Q(5), ZMMReg), 101 VMSTATE_UINT64(ZMM_Q(6), ZMMReg), 102 VMSTATE_UINT64(ZMM_Q(7), ZMMReg), 103 VMSTATE_END_OF_LIST() 104 } 105 }; 106 107 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \ 108 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ 109 vmstate_hi16_zmm_reg, ZMMReg) 110 #endif 111 112 static const VMStateDescription vmstate_bnd_regs = { 113 .name = "bnd_regs", 114 .version_id = 1, 115 .minimum_version_id = 1, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT64(lb, BNDReg), 118 VMSTATE_UINT64(ub, BNDReg), 119 VMSTATE_END_OF_LIST() 120 } 121 }; 122 123 #define VMSTATE_BND_REGS(_field, _state, _n) \ 124 VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg) 125 126 static const VMStateDescription vmstate_mtrr_var = { 127 .name = "mtrr_var", 128 .version_id = 1, 129 .minimum_version_id = 1, 130 .fields = (VMStateField[]) { 131 VMSTATE_UINT64(base, MTRRVar), 132 VMSTATE_UINT64(mask, MTRRVar), 133 VMSTATE_END_OF_LIST() 134 } 135 }; 136 137 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \ 138 VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar) 139 140 typedef struct x86_FPReg_tmp { 141 FPReg *parent; 142 uint64_t tmp_mant; 143 uint16_t tmp_exp; 144 } x86_FPReg_tmp; 145 146 static void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f) 147 { 148 CPU_LDoubleU temp; 149 150 temp.d = f; 151 *pmant = temp.l.lower; 152 *pexp = temp.l.upper; 153 } 154 155 static floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper) 156 { 157 CPU_LDoubleU temp; 158 159 temp.l.upper = upper; 160 temp.l.lower = mant; 161 return temp.d; 162 } 163 164 static int fpreg_pre_save(void *opaque) 165 { 166 x86_FPReg_tmp *tmp = opaque; 167 168 /* we save the real CPU data (in case of MMX usage only 'mant' 169 contains the MMX register */ 170 cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d); 171 172 return 0; 173 } 174 175 static int fpreg_post_load(void *opaque, int version) 176 { 177 x86_FPReg_tmp *tmp = opaque; 178 179 tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp); 180 return 0; 181 } 182 183 static const VMStateDescription vmstate_fpreg_tmp = { 184 .name = "fpreg_tmp", 185 .post_load = fpreg_post_load, 186 .pre_save = fpreg_pre_save, 187 .fields = (VMStateField[]) { 188 VMSTATE_UINT64(tmp_mant, x86_FPReg_tmp), 189 VMSTATE_UINT16(tmp_exp, x86_FPReg_tmp), 190 VMSTATE_END_OF_LIST() 191 } 192 }; 193 194 static const VMStateDescription vmstate_fpreg = { 195 .name = "fpreg", 196 .fields = (VMStateField[]) { 197 VMSTATE_WITH_TMP(FPReg, x86_FPReg_tmp, vmstate_fpreg_tmp), 198 VMSTATE_END_OF_LIST() 199 } 200 }; 201 202 static int cpu_pre_save(void *opaque) 203 { 204 X86CPU *cpu = opaque; 205 CPUX86State *env = &cpu->env; 206 int i; 207 208 /* FPU */ 209 env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; 210 env->fptag_vmstate = 0; 211 for(i = 0; i < 8; i++) { 212 env->fptag_vmstate |= ((!env->fptags[i]) << i); 213 } 214 215 env->fpregs_format_vmstate = 0; 216 217 /* 218 * Real mode guest segments register DPL should be zero. 219 * Older KVM version were setting it wrongly. 220 * Fixing it will allow live migration to host with unrestricted guest 221 * support (otherwise the migration will fail with invalid guest state 222 * error). 223 */ 224 if (!(env->cr[0] & CR0_PE_MASK) && 225 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { 226 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); 227 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); 228 env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); 229 env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); 230 env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); 231 env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); 232 } 233 234 #ifdef CONFIG_KVM 235 /* Verify we have nested virtualization state from kernel if required */ 236 if (kvm_enabled() && cpu_has_vmx(env) && !env->nested_state) { 237 error_report("Guest enabled nested virtualization but kernel " 238 "does not support saving of nested state"); 239 return -EINVAL; 240 } 241 #endif 242 243 /* 244 * When vCPU is running L2 and exception is still pending, 245 * it can potentially be intercepted by L1 hypervisor. 246 * In contrast to an injected exception which cannot be 247 * intercepted anymore. 248 * 249 * Furthermore, when a L2 exception is intercepted by L1 250 * hypervisor, it's exception payload (CR2/DR6 on #PF/#DB) 251 * should not be set yet in the respective vCPU register. 252 * Thus, in case an exception is pending, it is 253 * important to save the exception payload seperately. 254 * 255 * Therefore, if an exception is not in a pending state 256 * or vCPU is not in guest-mode, it is not important to 257 * distinguish between a pending and injected exception 258 * and we don't need to store seperately the exception payload. 259 * 260 * In order to preserve better backwards-compatabile migration, 261 * convert a pending exception to an injected exception in 262 * case it is not important to distingiush between them 263 * as described above. 264 */ 265 if (env->exception_pending && !(env->hflags & HF_GUEST_MASK)) { 266 env->exception_pending = 0; 267 env->exception_injected = 1; 268 269 if (env->exception_has_payload) { 270 if (env->exception_nr == EXCP01_DB) { 271 env->dr[6] = env->exception_payload; 272 } else if (env->exception_nr == EXCP0E_PAGE) { 273 env->cr[2] = env->exception_payload; 274 } 275 } 276 } 277 278 return 0; 279 } 280 281 static int cpu_post_load(void *opaque, int version_id) 282 { 283 X86CPU *cpu = opaque; 284 CPUState *cs = CPU(cpu); 285 CPUX86State *env = &cpu->env; 286 int i; 287 288 if (env->tsc_khz && env->user_tsc_khz && 289 env->tsc_khz != env->user_tsc_khz) { 290 error_report("Mismatch between user-specified TSC frequency and " 291 "migrated TSC frequency"); 292 return -EINVAL; 293 } 294 295 if (env->fpregs_format_vmstate) { 296 error_report("Unsupported old non-softfloat CPU state"); 297 return -EINVAL; 298 } 299 /* 300 * Real mode guest segments register DPL should be zero. 301 * Older KVM version were setting it wrongly. 302 * Fixing it will allow live migration from such host that don't have 303 * restricted guest support to a host with unrestricted guest support 304 * (otherwise the migration will fail with invalid guest state 305 * error). 306 */ 307 if (!(env->cr[0] & CR0_PE_MASK) && 308 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { 309 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); 310 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); 311 env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); 312 env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); 313 env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); 314 env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); 315 } 316 317 /* Older versions of QEMU incorrectly used CS.DPL as the CPL when 318 * running under KVM. This is wrong for conforming code segments. 319 * Luckily, in our implementation the CPL field of hflags is redundant 320 * and we can get the right value from the SS descriptor privilege level. 321 */ 322 env->hflags &= ~HF_CPL_MASK; 323 env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 324 325 #ifdef CONFIG_KVM 326 if ((env->hflags & HF_GUEST_MASK) && 327 (!env->nested_state || 328 !(env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE))) { 329 error_report("vCPU set in guest-mode inconsistent with " 330 "migrated kernel nested state"); 331 return -EINVAL; 332 } 333 #endif 334 335 /* 336 * There are cases that we can get valid exception_nr with both 337 * exception_pending and exception_injected being cleared. 338 * This can happen in one of the following scenarios: 339 * 1) Source is older QEMU without KVM_CAP_EXCEPTION_PAYLOAD support. 340 * 2) Source is running on kernel without KVM_CAP_EXCEPTION_PAYLOAD support. 341 * 3) "cpu/exception_info" subsection not sent because there is no exception 342 * pending or guest wasn't running L2 (See comment in cpu_pre_save()). 343 * 344 * In those cases, we can just deduce that a valid exception_nr means 345 * we can treat the exception as already injected. 346 */ 347 if ((env->exception_nr != -1) && 348 !env->exception_pending && !env->exception_injected) { 349 env->exception_injected = 1; 350 } 351 352 env->fpstt = (env->fpus_vmstate >> 11) & 7; 353 env->fpus = env->fpus_vmstate & ~0x3800; 354 env->fptag_vmstate ^= 0xff; 355 for(i = 0; i < 8; i++) { 356 env->fptags[i] = (env->fptag_vmstate >> i) & 1; 357 } 358 if (tcg_enabled()) { 359 target_ulong dr7; 360 update_fp_status(env); 361 update_mxcsr_status(env); 362 363 cpu_breakpoint_remove_all(cs, BP_CPU); 364 cpu_watchpoint_remove_all(cs, BP_CPU); 365 366 /* Indicate all breakpoints disabled, as they are, then 367 let the helper re-enable them. */ 368 dr7 = env->dr[7]; 369 env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK); 370 cpu_x86_update_dr7(env, dr7); 371 } 372 tlb_flush(cs); 373 return 0; 374 } 375 376 static bool async_pf_msr_needed(void *opaque) 377 { 378 X86CPU *cpu = opaque; 379 380 return cpu->env.async_pf_en_msr != 0; 381 } 382 383 static bool pv_eoi_msr_needed(void *opaque) 384 { 385 X86CPU *cpu = opaque; 386 387 return cpu->env.pv_eoi_en_msr != 0; 388 } 389 390 static bool steal_time_msr_needed(void *opaque) 391 { 392 X86CPU *cpu = opaque; 393 394 return cpu->env.steal_time_msr != 0; 395 } 396 397 static bool exception_info_needed(void *opaque) 398 { 399 X86CPU *cpu = opaque; 400 CPUX86State *env = &cpu->env; 401 402 /* 403 * It is important to save exception-info only in case 404 * we need to distingiush between a pending and injected 405 * exception. Which is only required in case there is a 406 * pending exception and vCPU is running L2. 407 * For more info, refer to comment in cpu_pre_save(). 408 */ 409 return env->exception_pending && (env->hflags & HF_GUEST_MASK); 410 } 411 412 static const VMStateDescription vmstate_exception_info = { 413 .name = "cpu/exception_info", 414 .version_id = 1, 415 .minimum_version_id = 1, 416 .needed = exception_info_needed, 417 .fields = (VMStateField[]) { 418 VMSTATE_UINT8(env.exception_pending, X86CPU), 419 VMSTATE_UINT8(env.exception_injected, X86CPU), 420 VMSTATE_UINT8(env.exception_has_payload, X86CPU), 421 VMSTATE_UINT64(env.exception_payload, X86CPU), 422 VMSTATE_END_OF_LIST() 423 } 424 }; 425 426 static const VMStateDescription vmstate_steal_time_msr = { 427 .name = "cpu/steal_time_msr", 428 .version_id = 1, 429 .minimum_version_id = 1, 430 .needed = steal_time_msr_needed, 431 .fields = (VMStateField[]) { 432 VMSTATE_UINT64(env.steal_time_msr, X86CPU), 433 VMSTATE_END_OF_LIST() 434 } 435 }; 436 437 static const VMStateDescription vmstate_async_pf_msr = { 438 .name = "cpu/async_pf_msr", 439 .version_id = 1, 440 .minimum_version_id = 1, 441 .needed = async_pf_msr_needed, 442 .fields = (VMStateField[]) { 443 VMSTATE_UINT64(env.async_pf_en_msr, X86CPU), 444 VMSTATE_END_OF_LIST() 445 } 446 }; 447 448 static const VMStateDescription vmstate_pv_eoi_msr = { 449 .name = "cpu/async_pv_eoi_msr", 450 .version_id = 1, 451 .minimum_version_id = 1, 452 .needed = pv_eoi_msr_needed, 453 .fields = (VMStateField[]) { 454 VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU), 455 VMSTATE_END_OF_LIST() 456 } 457 }; 458 459 static bool fpop_ip_dp_needed(void *opaque) 460 { 461 X86CPU *cpu = opaque; 462 CPUX86State *env = &cpu->env; 463 464 return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; 465 } 466 467 static const VMStateDescription vmstate_fpop_ip_dp = { 468 .name = "cpu/fpop_ip_dp", 469 .version_id = 1, 470 .minimum_version_id = 1, 471 .needed = fpop_ip_dp_needed, 472 .fields = (VMStateField[]) { 473 VMSTATE_UINT16(env.fpop, X86CPU), 474 VMSTATE_UINT64(env.fpip, X86CPU), 475 VMSTATE_UINT64(env.fpdp, X86CPU), 476 VMSTATE_END_OF_LIST() 477 } 478 }; 479 480 static bool tsc_adjust_needed(void *opaque) 481 { 482 X86CPU *cpu = opaque; 483 CPUX86State *env = &cpu->env; 484 485 return env->tsc_adjust != 0; 486 } 487 488 static const VMStateDescription vmstate_msr_tsc_adjust = { 489 .name = "cpu/msr_tsc_adjust", 490 .version_id = 1, 491 .minimum_version_id = 1, 492 .needed = tsc_adjust_needed, 493 .fields = (VMStateField[]) { 494 VMSTATE_UINT64(env.tsc_adjust, X86CPU), 495 VMSTATE_END_OF_LIST() 496 } 497 }; 498 499 static bool msr_smi_count_needed(void *opaque) 500 { 501 X86CPU *cpu = opaque; 502 CPUX86State *env = &cpu->env; 503 504 return cpu->migrate_smi_count && env->msr_smi_count != 0; 505 } 506 507 static const VMStateDescription vmstate_msr_smi_count = { 508 .name = "cpu/msr_smi_count", 509 .version_id = 1, 510 .minimum_version_id = 1, 511 .needed = msr_smi_count_needed, 512 .fields = (VMStateField[]) { 513 VMSTATE_UINT64(env.msr_smi_count, X86CPU), 514 VMSTATE_END_OF_LIST() 515 } 516 }; 517 518 static bool tscdeadline_needed(void *opaque) 519 { 520 X86CPU *cpu = opaque; 521 CPUX86State *env = &cpu->env; 522 523 return env->tsc_deadline != 0; 524 } 525 526 static const VMStateDescription vmstate_msr_tscdeadline = { 527 .name = "cpu/msr_tscdeadline", 528 .version_id = 1, 529 .minimum_version_id = 1, 530 .needed = tscdeadline_needed, 531 .fields = (VMStateField[]) { 532 VMSTATE_UINT64(env.tsc_deadline, X86CPU), 533 VMSTATE_END_OF_LIST() 534 } 535 }; 536 537 static bool misc_enable_needed(void *opaque) 538 { 539 X86CPU *cpu = opaque; 540 CPUX86State *env = &cpu->env; 541 542 return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT; 543 } 544 545 static bool feature_control_needed(void *opaque) 546 { 547 X86CPU *cpu = opaque; 548 CPUX86State *env = &cpu->env; 549 550 return env->msr_ia32_feature_control != 0; 551 } 552 553 static const VMStateDescription vmstate_msr_ia32_misc_enable = { 554 .name = "cpu/msr_ia32_misc_enable", 555 .version_id = 1, 556 .minimum_version_id = 1, 557 .needed = misc_enable_needed, 558 .fields = (VMStateField[]) { 559 VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU), 560 VMSTATE_END_OF_LIST() 561 } 562 }; 563 564 static const VMStateDescription vmstate_msr_ia32_feature_control = { 565 .name = "cpu/msr_ia32_feature_control", 566 .version_id = 1, 567 .minimum_version_id = 1, 568 .needed = feature_control_needed, 569 .fields = (VMStateField[]) { 570 VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU), 571 VMSTATE_END_OF_LIST() 572 } 573 }; 574 575 static bool pmu_enable_needed(void *opaque) 576 { 577 X86CPU *cpu = opaque; 578 CPUX86State *env = &cpu->env; 579 int i; 580 581 if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl || 582 env->msr_global_status || env->msr_global_ovf_ctrl) { 583 return true; 584 } 585 for (i = 0; i < MAX_FIXED_COUNTERS; i++) { 586 if (env->msr_fixed_counters[i]) { 587 return true; 588 } 589 } 590 for (i = 0; i < MAX_GP_COUNTERS; i++) { 591 if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) { 592 return true; 593 } 594 } 595 596 return false; 597 } 598 599 static const VMStateDescription vmstate_msr_architectural_pmu = { 600 .name = "cpu/msr_architectural_pmu", 601 .version_id = 1, 602 .minimum_version_id = 1, 603 .needed = pmu_enable_needed, 604 .fields = (VMStateField[]) { 605 VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), 606 VMSTATE_UINT64(env.msr_global_ctrl, X86CPU), 607 VMSTATE_UINT64(env.msr_global_status, X86CPU), 608 VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU), 609 VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS), 610 VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), 611 VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), 612 VMSTATE_END_OF_LIST() 613 } 614 }; 615 616 static bool mpx_needed(void *opaque) 617 { 618 X86CPU *cpu = opaque; 619 CPUX86State *env = &cpu->env; 620 unsigned int i; 621 622 for (i = 0; i < 4; i++) { 623 if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) { 624 return true; 625 } 626 } 627 628 if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) { 629 return true; 630 } 631 632 return !!env->msr_bndcfgs; 633 } 634 635 static const VMStateDescription vmstate_mpx = { 636 .name = "cpu/mpx", 637 .version_id = 1, 638 .minimum_version_id = 1, 639 .needed = mpx_needed, 640 .fields = (VMStateField[]) { 641 VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4), 642 VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU), 643 VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU), 644 VMSTATE_UINT64(env.msr_bndcfgs, X86CPU), 645 VMSTATE_END_OF_LIST() 646 } 647 }; 648 649 static bool hyperv_hypercall_enable_needed(void *opaque) 650 { 651 X86CPU *cpu = opaque; 652 CPUX86State *env = &cpu->env; 653 654 return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0; 655 } 656 657 static const VMStateDescription vmstate_msr_hypercall_hypercall = { 658 .name = "cpu/msr_hyperv_hypercall", 659 .version_id = 1, 660 .minimum_version_id = 1, 661 .needed = hyperv_hypercall_enable_needed, 662 .fields = (VMStateField[]) { 663 VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU), 664 VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU), 665 VMSTATE_END_OF_LIST() 666 } 667 }; 668 669 static bool hyperv_vapic_enable_needed(void *opaque) 670 { 671 X86CPU *cpu = opaque; 672 CPUX86State *env = &cpu->env; 673 674 return env->msr_hv_vapic != 0; 675 } 676 677 static const VMStateDescription vmstate_msr_hyperv_vapic = { 678 .name = "cpu/msr_hyperv_vapic", 679 .version_id = 1, 680 .minimum_version_id = 1, 681 .needed = hyperv_vapic_enable_needed, 682 .fields = (VMStateField[]) { 683 VMSTATE_UINT64(env.msr_hv_vapic, X86CPU), 684 VMSTATE_END_OF_LIST() 685 } 686 }; 687 688 static bool hyperv_time_enable_needed(void *opaque) 689 { 690 X86CPU *cpu = opaque; 691 CPUX86State *env = &cpu->env; 692 693 return env->msr_hv_tsc != 0; 694 } 695 696 static const VMStateDescription vmstate_msr_hyperv_time = { 697 .name = "cpu/msr_hyperv_time", 698 .version_id = 1, 699 .minimum_version_id = 1, 700 .needed = hyperv_time_enable_needed, 701 .fields = (VMStateField[]) { 702 VMSTATE_UINT64(env.msr_hv_tsc, X86CPU), 703 VMSTATE_END_OF_LIST() 704 } 705 }; 706 707 static bool hyperv_crash_enable_needed(void *opaque) 708 { 709 X86CPU *cpu = opaque; 710 CPUX86State *env = &cpu->env; 711 int i; 712 713 for (i = 0; i < HV_CRASH_PARAMS; i++) { 714 if (env->msr_hv_crash_params[i]) { 715 return true; 716 } 717 } 718 return false; 719 } 720 721 static const VMStateDescription vmstate_msr_hyperv_crash = { 722 .name = "cpu/msr_hyperv_crash", 723 .version_id = 1, 724 .minimum_version_id = 1, 725 .needed = hyperv_crash_enable_needed, 726 .fields = (VMStateField[]) { 727 VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params, X86CPU, HV_CRASH_PARAMS), 728 VMSTATE_END_OF_LIST() 729 } 730 }; 731 732 static bool hyperv_runtime_enable_needed(void *opaque) 733 { 734 X86CPU *cpu = opaque; 735 CPUX86State *env = &cpu->env; 736 737 if (!hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) { 738 return false; 739 } 740 741 return env->msr_hv_runtime != 0; 742 } 743 744 static const VMStateDescription vmstate_msr_hyperv_runtime = { 745 .name = "cpu/msr_hyperv_runtime", 746 .version_id = 1, 747 .minimum_version_id = 1, 748 .needed = hyperv_runtime_enable_needed, 749 .fields = (VMStateField[]) { 750 VMSTATE_UINT64(env.msr_hv_runtime, X86CPU), 751 VMSTATE_END_OF_LIST() 752 } 753 }; 754 755 static bool hyperv_synic_enable_needed(void *opaque) 756 { 757 X86CPU *cpu = opaque; 758 CPUX86State *env = &cpu->env; 759 int i; 760 761 if (env->msr_hv_synic_control != 0 || 762 env->msr_hv_synic_evt_page != 0 || 763 env->msr_hv_synic_msg_page != 0) { 764 return true; 765 } 766 767 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { 768 if (env->msr_hv_synic_sint[i] != 0) { 769 return true; 770 } 771 } 772 773 return false; 774 } 775 776 static int hyperv_synic_post_load(void *opaque, int version_id) 777 { 778 X86CPU *cpu = opaque; 779 hyperv_x86_synic_update(cpu); 780 return 0; 781 } 782 783 static const VMStateDescription vmstate_msr_hyperv_synic = { 784 .name = "cpu/msr_hyperv_synic", 785 .version_id = 1, 786 .minimum_version_id = 1, 787 .needed = hyperv_synic_enable_needed, 788 .post_load = hyperv_synic_post_load, 789 .fields = (VMStateField[]) { 790 VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU), 791 VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU), 792 VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU), 793 VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU, HV_SINT_COUNT), 794 VMSTATE_END_OF_LIST() 795 } 796 }; 797 798 static bool hyperv_stimer_enable_needed(void *opaque) 799 { 800 X86CPU *cpu = opaque; 801 CPUX86State *env = &cpu->env; 802 int i; 803 804 for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) { 805 if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) { 806 return true; 807 } 808 } 809 return false; 810 } 811 812 static const VMStateDescription vmstate_msr_hyperv_stimer = { 813 .name = "cpu/msr_hyperv_stimer", 814 .version_id = 1, 815 .minimum_version_id = 1, 816 .needed = hyperv_stimer_enable_needed, 817 .fields = (VMStateField[]) { 818 VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config, X86CPU, 819 HV_STIMER_COUNT), 820 VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count, X86CPU, HV_STIMER_COUNT), 821 VMSTATE_END_OF_LIST() 822 } 823 }; 824 825 static bool hyperv_reenlightenment_enable_needed(void *opaque) 826 { 827 X86CPU *cpu = opaque; 828 CPUX86State *env = &cpu->env; 829 830 return env->msr_hv_reenlightenment_control != 0 || 831 env->msr_hv_tsc_emulation_control != 0 || 832 env->msr_hv_tsc_emulation_status != 0; 833 } 834 835 static const VMStateDescription vmstate_msr_hyperv_reenlightenment = { 836 .name = "cpu/msr_hyperv_reenlightenment", 837 .version_id = 1, 838 .minimum_version_id = 1, 839 .needed = hyperv_reenlightenment_enable_needed, 840 .fields = (VMStateField[]) { 841 VMSTATE_UINT64(env.msr_hv_reenlightenment_control, X86CPU), 842 VMSTATE_UINT64(env.msr_hv_tsc_emulation_control, X86CPU), 843 VMSTATE_UINT64(env.msr_hv_tsc_emulation_status, X86CPU), 844 VMSTATE_END_OF_LIST() 845 } 846 }; 847 848 static bool avx512_needed(void *opaque) 849 { 850 X86CPU *cpu = opaque; 851 CPUX86State *env = &cpu->env; 852 unsigned int i; 853 854 for (i = 0; i < NB_OPMASK_REGS; i++) { 855 if (env->opmask_regs[i]) { 856 return true; 857 } 858 } 859 860 for (i = 0; i < CPU_NB_REGS; i++) { 861 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field)) 862 if (ENV_XMM(i, 4) || ENV_XMM(i, 6) || 863 ENV_XMM(i, 5) || ENV_XMM(i, 7)) { 864 return true; 865 } 866 #ifdef TARGET_X86_64 867 if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) || 868 ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) || 869 ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) || 870 ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) { 871 return true; 872 } 873 #endif 874 } 875 876 return false; 877 } 878 879 static const VMStateDescription vmstate_avx512 = { 880 .name = "cpu/avx512", 881 .version_id = 1, 882 .minimum_version_id = 1, 883 .needed = avx512_needed, 884 .fields = (VMStateField[]) { 885 VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS), 886 VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0), 887 #ifdef TARGET_X86_64 888 VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16), 889 #endif 890 VMSTATE_END_OF_LIST() 891 } 892 }; 893 894 static bool xss_needed(void *opaque) 895 { 896 X86CPU *cpu = opaque; 897 CPUX86State *env = &cpu->env; 898 899 return env->xss != 0; 900 } 901 902 static const VMStateDescription vmstate_xss = { 903 .name = "cpu/xss", 904 .version_id = 1, 905 .minimum_version_id = 1, 906 .needed = xss_needed, 907 .fields = (VMStateField[]) { 908 VMSTATE_UINT64(env.xss, X86CPU), 909 VMSTATE_END_OF_LIST() 910 } 911 }; 912 913 #ifdef TARGET_X86_64 914 static bool pkru_needed(void *opaque) 915 { 916 X86CPU *cpu = opaque; 917 CPUX86State *env = &cpu->env; 918 919 return env->pkru != 0; 920 } 921 922 static const VMStateDescription vmstate_pkru = { 923 .name = "cpu/pkru", 924 .version_id = 1, 925 .minimum_version_id = 1, 926 .needed = pkru_needed, 927 .fields = (VMStateField[]){ 928 VMSTATE_UINT32(env.pkru, X86CPU), 929 VMSTATE_END_OF_LIST() 930 } 931 }; 932 #endif 933 934 static bool tsc_khz_needed(void *opaque) 935 { 936 X86CPU *cpu = opaque; 937 CPUX86State *env = &cpu->env; 938 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 939 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc); 940 return env->tsc_khz && pcmc->save_tsc_khz; 941 } 942 943 static const VMStateDescription vmstate_tsc_khz = { 944 .name = "cpu/tsc_khz", 945 .version_id = 1, 946 .minimum_version_id = 1, 947 .needed = tsc_khz_needed, 948 .fields = (VMStateField[]) { 949 VMSTATE_INT64(env.tsc_khz, X86CPU), 950 VMSTATE_END_OF_LIST() 951 } 952 }; 953 954 #ifdef CONFIG_KVM 955 956 static bool vmx_vmcs12_needed(void *opaque) 957 { 958 struct kvm_nested_state *nested_state = opaque; 959 return (nested_state->size > 960 offsetof(struct kvm_nested_state, data.vmx[0].vmcs12)); 961 } 962 963 static const VMStateDescription vmstate_vmx_vmcs12 = { 964 .name = "cpu/kvm_nested_state/vmx/vmcs12", 965 .version_id = 1, 966 .minimum_version_id = 1, 967 .needed = vmx_vmcs12_needed, 968 .fields = (VMStateField[]) { 969 VMSTATE_UINT8_ARRAY(data.vmx[0].vmcs12, 970 struct kvm_nested_state, 971 KVM_STATE_NESTED_VMX_VMCS_SIZE), 972 VMSTATE_END_OF_LIST() 973 } 974 }; 975 976 static bool vmx_shadow_vmcs12_needed(void *opaque) 977 { 978 struct kvm_nested_state *nested_state = opaque; 979 return (nested_state->size > 980 offsetof(struct kvm_nested_state, data.vmx[0].shadow_vmcs12)); 981 } 982 983 static const VMStateDescription vmstate_vmx_shadow_vmcs12 = { 984 .name = "cpu/kvm_nested_state/vmx/shadow_vmcs12", 985 .version_id = 1, 986 .minimum_version_id = 1, 987 .needed = vmx_shadow_vmcs12_needed, 988 .fields = (VMStateField[]) { 989 VMSTATE_UINT8_ARRAY(data.vmx[0].shadow_vmcs12, 990 struct kvm_nested_state, 991 KVM_STATE_NESTED_VMX_VMCS_SIZE), 992 VMSTATE_END_OF_LIST() 993 } 994 }; 995 996 static bool vmx_nested_state_needed(void *opaque) 997 { 998 struct kvm_nested_state *nested_state = opaque; 999 1000 return ((nested_state->format == KVM_STATE_NESTED_FORMAT_VMX) && 1001 ((nested_state->hdr.vmx.vmxon_pa != -1ull) || 1002 (nested_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))); 1003 } 1004 1005 static const VMStateDescription vmstate_vmx_nested_state = { 1006 .name = "cpu/kvm_nested_state/vmx", 1007 .version_id = 1, 1008 .minimum_version_id = 1, 1009 .needed = vmx_nested_state_needed, 1010 .fields = (VMStateField[]) { 1011 VMSTATE_U64(hdr.vmx.vmxon_pa, struct kvm_nested_state), 1012 VMSTATE_U64(hdr.vmx.vmcs12_pa, struct kvm_nested_state), 1013 VMSTATE_U16(hdr.vmx.smm.flags, struct kvm_nested_state), 1014 VMSTATE_END_OF_LIST() 1015 }, 1016 .subsections = (const VMStateDescription*[]) { 1017 &vmstate_vmx_vmcs12, 1018 &vmstate_vmx_shadow_vmcs12, 1019 NULL, 1020 } 1021 }; 1022 1023 static bool svm_nested_state_needed(void *opaque) 1024 { 1025 struct kvm_nested_state *nested_state = opaque; 1026 1027 return (nested_state->format == KVM_STATE_NESTED_FORMAT_SVM); 1028 } 1029 1030 static const VMStateDescription vmstate_svm_nested_state = { 1031 .name = "cpu/kvm_nested_state/svm", 1032 .version_id = 1, 1033 .minimum_version_id = 1, 1034 .needed = svm_nested_state_needed, 1035 .fields = (VMStateField[]) { 1036 VMSTATE_END_OF_LIST() 1037 } 1038 }; 1039 1040 static bool nested_state_needed(void *opaque) 1041 { 1042 X86CPU *cpu = opaque; 1043 CPUX86State *env = &cpu->env; 1044 1045 return (env->nested_state && 1046 (vmx_nested_state_needed(env->nested_state) || 1047 svm_nested_state_needed(env->nested_state))); 1048 } 1049 1050 static int nested_state_post_load(void *opaque, int version_id) 1051 { 1052 X86CPU *cpu = opaque; 1053 CPUX86State *env = &cpu->env; 1054 struct kvm_nested_state *nested_state = env->nested_state; 1055 int min_nested_state_len = offsetof(struct kvm_nested_state, data); 1056 int max_nested_state_len = kvm_max_nested_state_length(); 1057 1058 /* 1059 * If our kernel don't support setting nested state 1060 * and we have received nested state from migration stream, 1061 * we need to fail migration 1062 */ 1063 if (max_nested_state_len <= 0) { 1064 error_report("Received nested state when kernel cannot restore it"); 1065 return -EINVAL; 1066 } 1067 1068 /* 1069 * Verify that the size of received nested_state struct 1070 * at least cover required header and is not larger 1071 * than the max size that our kernel support 1072 */ 1073 if (nested_state->size < min_nested_state_len) { 1074 error_report("Received nested state size less than min: " 1075 "len=%d, min=%d", 1076 nested_state->size, min_nested_state_len); 1077 return -EINVAL; 1078 } 1079 if (nested_state->size > max_nested_state_len) { 1080 error_report("Recieved unsupported nested state size: " 1081 "nested_state->size=%d, max=%d", 1082 nested_state->size, max_nested_state_len); 1083 return -EINVAL; 1084 } 1085 1086 /* Verify format is valid */ 1087 if ((nested_state->format != KVM_STATE_NESTED_FORMAT_VMX) && 1088 (nested_state->format != KVM_STATE_NESTED_FORMAT_SVM)) { 1089 error_report("Received invalid nested state format: %d", 1090 nested_state->format); 1091 return -EINVAL; 1092 } 1093 1094 return 0; 1095 } 1096 1097 static const VMStateDescription vmstate_kvm_nested_state = { 1098 .name = "cpu/kvm_nested_state", 1099 .version_id = 1, 1100 .minimum_version_id = 1, 1101 .fields = (VMStateField[]) { 1102 VMSTATE_U16(flags, struct kvm_nested_state), 1103 VMSTATE_U16(format, struct kvm_nested_state), 1104 VMSTATE_U32(size, struct kvm_nested_state), 1105 VMSTATE_END_OF_LIST() 1106 }, 1107 .subsections = (const VMStateDescription*[]) { 1108 &vmstate_vmx_nested_state, 1109 &vmstate_svm_nested_state, 1110 NULL 1111 } 1112 }; 1113 1114 static const VMStateDescription vmstate_nested_state = { 1115 .name = "cpu/nested_state", 1116 .version_id = 1, 1117 .minimum_version_id = 1, 1118 .needed = nested_state_needed, 1119 .post_load = nested_state_post_load, 1120 .fields = (VMStateField[]) { 1121 VMSTATE_STRUCT_POINTER(env.nested_state, X86CPU, 1122 vmstate_kvm_nested_state, 1123 struct kvm_nested_state), 1124 VMSTATE_END_OF_LIST() 1125 } 1126 }; 1127 1128 #endif 1129 1130 static bool mcg_ext_ctl_needed(void *opaque) 1131 { 1132 X86CPU *cpu = opaque; 1133 CPUX86State *env = &cpu->env; 1134 return cpu->enable_lmce && env->mcg_ext_ctl; 1135 } 1136 1137 static const VMStateDescription vmstate_mcg_ext_ctl = { 1138 .name = "cpu/mcg_ext_ctl", 1139 .version_id = 1, 1140 .minimum_version_id = 1, 1141 .needed = mcg_ext_ctl_needed, 1142 .fields = (VMStateField[]) { 1143 VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU), 1144 VMSTATE_END_OF_LIST() 1145 } 1146 }; 1147 1148 static bool spec_ctrl_needed(void *opaque) 1149 { 1150 X86CPU *cpu = opaque; 1151 CPUX86State *env = &cpu->env; 1152 1153 return env->spec_ctrl != 0; 1154 } 1155 1156 static const VMStateDescription vmstate_spec_ctrl = { 1157 .name = "cpu/spec_ctrl", 1158 .version_id = 1, 1159 .minimum_version_id = 1, 1160 .needed = spec_ctrl_needed, 1161 .fields = (VMStateField[]){ 1162 VMSTATE_UINT64(env.spec_ctrl, X86CPU), 1163 VMSTATE_END_OF_LIST() 1164 } 1165 }; 1166 1167 static bool intel_pt_enable_needed(void *opaque) 1168 { 1169 X86CPU *cpu = opaque; 1170 CPUX86State *env = &cpu->env; 1171 int i; 1172 1173 if (env->msr_rtit_ctrl || env->msr_rtit_status || 1174 env->msr_rtit_output_base || env->msr_rtit_output_mask || 1175 env->msr_rtit_cr3_match) { 1176 return true; 1177 } 1178 1179 for (i = 0; i < MAX_RTIT_ADDRS; i++) { 1180 if (env->msr_rtit_addrs[i]) { 1181 return true; 1182 } 1183 } 1184 1185 return false; 1186 } 1187 1188 static const VMStateDescription vmstate_msr_intel_pt = { 1189 .name = "cpu/intel_pt", 1190 .version_id = 1, 1191 .minimum_version_id = 1, 1192 .needed = intel_pt_enable_needed, 1193 .fields = (VMStateField[]) { 1194 VMSTATE_UINT64(env.msr_rtit_ctrl, X86CPU), 1195 VMSTATE_UINT64(env.msr_rtit_status, X86CPU), 1196 VMSTATE_UINT64(env.msr_rtit_output_base, X86CPU), 1197 VMSTATE_UINT64(env.msr_rtit_output_mask, X86CPU), 1198 VMSTATE_UINT64(env.msr_rtit_cr3_match, X86CPU), 1199 VMSTATE_UINT64_ARRAY(env.msr_rtit_addrs, X86CPU, MAX_RTIT_ADDRS), 1200 VMSTATE_END_OF_LIST() 1201 } 1202 }; 1203 1204 static bool virt_ssbd_needed(void *opaque) 1205 { 1206 X86CPU *cpu = opaque; 1207 CPUX86State *env = &cpu->env; 1208 1209 return env->virt_ssbd != 0; 1210 } 1211 1212 static const VMStateDescription vmstate_msr_virt_ssbd = { 1213 .name = "cpu/virt_ssbd", 1214 .version_id = 1, 1215 .minimum_version_id = 1, 1216 .needed = virt_ssbd_needed, 1217 .fields = (VMStateField[]){ 1218 VMSTATE_UINT64(env.virt_ssbd, X86CPU), 1219 VMSTATE_END_OF_LIST() 1220 } 1221 }; 1222 1223 static bool svm_npt_needed(void *opaque) 1224 { 1225 X86CPU *cpu = opaque; 1226 CPUX86State *env = &cpu->env; 1227 1228 return !!(env->hflags2 & HF2_NPT_MASK); 1229 } 1230 1231 static const VMStateDescription vmstate_svm_npt = { 1232 .name = "cpu/svn_npt", 1233 .version_id = 1, 1234 .minimum_version_id = 1, 1235 .needed = svm_npt_needed, 1236 .fields = (VMStateField[]){ 1237 VMSTATE_UINT64(env.nested_cr3, X86CPU), 1238 VMSTATE_UINT32(env.nested_pg_mode, X86CPU), 1239 VMSTATE_END_OF_LIST() 1240 } 1241 }; 1242 1243 #ifndef TARGET_X86_64 1244 static bool intel_efer32_needed(void *opaque) 1245 { 1246 X86CPU *cpu = opaque; 1247 CPUX86State *env = &cpu->env; 1248 1249 return env->efer != 0; 1250 } 1251 1252 static const VMStateDescription vmstate_efer32 = { 1253 .name = "cpu/efer32", 1254 .version_id = 1, 1255 .minimum_version_id = 1, 1256 .needed = intel_efer32_needed, 1257 .fields = (VMStateField[]) { 1258 VMSTATE_UINT64(env.efer, X86CPU), 1259 VMSTATE_END_OF_LIST() 1260 } 1261 }; 1262 #endif 1263 1264 VMStateDescription vmstate_x86_cpu = { 1265 .name = "cpu", 1266 .version_id = 12, 1267 .minimum_version_id = 11, 1268 .pre_save = cpu_pre_save, 1269 .post_load = cpu_post_load, 1270 .fields = (VMStateField[]) { 1271 VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS), 1272 VMSTATE_UINTTL(env.eip, X86CPU), 1273 VMSTATE_UINTTL(env.eflags, X86CPU), 1274 VMSTATE_UINT32(env.hflags, X86CPU), 1275 /* FPU */ 1276 VMSTATE_UINT16(env.fpuc, X86CPU), 1277 VMSTATE_UINT16(env.fpus_vmstate, X86CPU), 1278 VMSTATE_UINT16(env.fptag_vmstate, X86CPU), 1279 VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU), 1280 1281 VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg), 1282 1283 VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6), 1284 VMSTATE_SEGMENT(env.ldt, X86CPU), 1285 VMSTATE_SEGMENT(env.tr, X86CPU), 1286 VMSTATE_SEGMENT(env.gdt, X86CPU), 1287 VMSTATE_SEGMENT(env.idt, X86CPU), 1288 1289 VMSTATE_UINT32(env.sysenter_cs, X86CPU), 1290 VMSTATE_UINTTL(env.sysenter_esp, X86CPU), 1291 VMSTATE_UINTTL(env.sysenter_eip, X86CPU), 1292 1293 VMSTATE_UINTTL(env.cr[0], X86CPU), 1294 VMSTATE_UINTTL(env.cr[2], X86CPU), 1295 VMSTATE_UINTTL(env.cr[3], X86CPU), 1296 VMSTATE_UINTTL(env.cr[4], X86CPU), 1297 VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8), 1298 /* MMU */ 1299 VMSTATE_INT32(env.a20_mask, X86CPU), 1300 /* XMM */ 1301 VMSTATE_UINT32(env.mxcsr, X86CPU), 1302 VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0), 1303 1304 #ifdef TARGET_X86_64 1305 VMSTATE_UINT64(env.efer, X86CPU), 1306 VMSTATE_UINT64(env.star, X86CPU), 1307 VMSTATE_UINT64(env.lstar, X86CPU), 1308 VMSTATE_UINT64(env.cstar, X86CPU), 1309 VMSTATE_UINT64(env.fmask, X86CPU), 1310 VMSTATE_UINT64(env.kernelgsbase, X86CPU), 1311 #endif 1312 VMSTATE_UINT32(env.smbase, X86CPU), 1313 1314 VMSTATE_UINT64(env.pat, X86CPU), 1315 VMSTATE_UINT32(env.hflags2, X86CPU), 1316 1317 VMSTATE_UINT64(env.vm_hsave, X86CPU), 1318 VMSTATE_UINT64(env.vm_vmcb, X86CPU), 1319 VMSTATE_UINT64(env.tsc_offset, X86CPU), 1320 VMSTATE_UINT64(env.intercept, X86CPU), 1321 VMSTATE_UINT16(env.intercept_cr_read, X86CPU), 1322 VMSTATE_UINT16(env.intercept_cr_write, X86CPU), 1323 VMSTATE_UINT16(env.intercept_dr_read, X86CPU), 1324 VMSTATE_UINT16(env.intercept_dr_write, X86CPU), 1325 VMSTATE_UINT32(env.intercept_exceptions, X86CPU), 1326 VMSTATE_UINT8(env.v_tpr, X86CPU), 1327 /* MTRRs */ 1328 VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11), 1329 VMSTATE_UINT64(env.mtrr_deftype, X86CPU), 1330 VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8), 1331 /* KVM-related states */ 1332 VMSTATE_INT32(env.interrupt_injected, X86CPU), 1333 VMSTATE_UINT32(env.mp_state, X86CPU), 1334 VMSTATE_UINT64(env.tsc, X86CPU), 1335 VMSTATE_INT32(env.exception_nr, X86CPU), 1336 VMSTATE_UINT8(env.soft_interrupt, X86CPU), 1337 VMSTATE_UINT8(env.nmi_injected, X86CPU), 1338 VMSTATE_UINT8(env.nmi_pending, X86CPU), 1339 VMSTATE_UINT8(env.has_error_code, X86CPU), 1340 VMSTATE_UINT32(env.sipi_vector, X86CPU), 1341 /* MCE */ 1342 VMSTATE_UINT64(env.mcg_cap, X86CPU), 1343 VMSTATE_UINT64(env.mcg_status, X86CPU), 1344 VMSTATE_UINT64(env.mcg_ctl, X86CPU), 1345 VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4), 1346 /* rdtscp */ 1347 VMSTATE_UINT64(env.tsc_aux, X86CPU), 1348 /* KVM pvclock msr */ 1349 VMSTATE_UINT64(env.system_time_msr, X86CPU), 1350 VMSTATE_UINT64(env.wall_clock_msr, X86CPU), 1351 /* XSAVE related fields */ 1352 VMSTATE_UINT64_V(env.xcr0, X86CPU, 12), 1353 VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12), 1354 VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12), 1355 VMSTATE_END_OF_LIST() 1356 /* The above list is not sorted /wrt version numbers, watch out! */ 1357 }, 1358 .subsections = (const VMStateDescription*[]) { 1359 &vmstate_exception_info, 1360 &vmstate_async_pf_msr, 1361 &vmstate_pv_eoi_msr, 1362 &vmstate_steal_time_msr, 1363 &vmstate_fpop_ip_dp, 1364 &vmstate_msr_tsc_adjust, 1365 &vmstate_msr_tscdeadline, 1366 &vmstate_msr_ia32_misc_enable, 1367 &vmstate_msr_ia32_feature_control, 1368 &vmstate_msr_architectural_pmu, 1369 &vmstate_mpx, 1370 &vmstate_msr_hypercall_hypercall, 1371 &vmstate_msr_hyperv_vapic, 1372 &vmstate_msr_hyperv_time, 1373 &vmstate_msr_hyperv_crash, 1374 &vmstate_msr_hyperv_runtime, 1375 &vmstate_msr_hyperv_synic, 1376 &vmstate_msr_hyperv_stimer, 1377 &vmstate_msr_hyperv_reenlightenment, 1378 &vmstate_avx512, 1379 &vmstate_xss, 1380 &vmstate_tsc_khz, 1381 &vmstate_msr_smi_count, 1382 #ifdef TARGET_X86_64 1383 &vmstate_pkru, 1384 #endif 1385 &vmstate_spec_ctrl, 1386 &vmstate_mcg_ext_ctl, 1387 &vmstate_msr_intel_pt, 1388 &vmstate_msr_virt_ssbd, 1389 &vmstate_svm_npt, 1390 #ifndef TARGET_X86_64 1391 &vmstate_efer32, 1392 #endif 1393 #ifdef CONFIG_KVM 1394 &vmstate_nested_state, 1395 #endif 1396 NULL 1397 } 1398 }; 1399