xref: /openbmc/qemu/target/i386/machine.c (revision 80e5db30)
1 #include "qemu/osdep.h"
2 #include "qemu-common.h"
3 #include "cpu.h"
4 #include "exec/exec-all.h"
5 #include "hw/hw.h"
6 #include "hw/boards.h"
7 #include "hw/i386/pc.h"
8 #include "hw/isa/isa.h"
9 #include "migration/cpu.h"
10 
11 #include "sysemu/kvm.h"
12 
13 #include "qemu/error-report.h"
14 
15 static const VMStateDescription vmstate_segment = {
16     .name = "segment",
17     .version_id = 1,
18     .minimum_version_id = 1,
19     .fields = (VMStateField[]) {
20         VMSTATE_UINT32(selector, SegmentCache),
21         VMSTATE_UINTTL(base, SegmentCache),
22         VMSTATE_UINT32(limit, SegmentCache),
23         VMSTATE_UINT32(flags, SegmentCache),
24         VMSTATE_END_OF_LIST()
25     }
26 };
27 
28 #define VMSTATE_SEGMENT(_field, _state) {                            \
29     .name       = (stringify(_field)),                               \
30     .size       = sizeof(SegmentCache),                              \
31     .vmsd       = &vmstate_segment,                                  \
32     .flags      = VMS_STRUCT,                                        \
33     .offset     = offsetof(_state, _field)                           \
34             + type_check(SegmentCache,typeof_field(_state, _field))  \
35 }
36 
37 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
38     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
39 
40 static const VMStateDescription vmstate_xmm_reg = {
41     .name = "xmm_reg",
42     .version_id = 1,
43     .minimum_version_id = 1,
44     .fields = (VMStateField[]) {
45         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
46         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
47         VMSTATE_END_OF_LIST()
48     }
49 };
50 
51 #define VMSTATE_XMM_REGS(_field, _state, _start)                         \
52     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
53                              vmstate_xmm_reg, ZMMReg)
54 
55 /* YMMH format is the same as XMM, but for bits 128-255 */
56 static const VMStateDescription vmstate_ymmh_reg = {
57     .name = "ymmh_reg",
58     .version_id = 1,
59     .minimum_version_id = 1,
60     .fields = (VMStateField[]) {
61         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
62         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
63         VMSTATE_END_OF_LIST()
64     }
65 };
66 
67 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v)               \
68     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v,    \
69                              vmstate_ymmh_reg, ZMMReg)
70 
71 static const VMStateDescription vmstate_zmmh_reg = {
72     .name = "zmmh_reg",
73     .version_id = 1,
74     .minimum_version_id = 1,
75     .fields = (VMStateField[]) {
76         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
77         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
78         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
79         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
80         VMSTATE_END_OF_LIST()
81     }
82 };
83 
84 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start)                   \
85     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
86                              vmstate_zmmh_reg, ZMMReg)
87 
88 #ifdef TARGET_X86_64
89 static const VMStateDescription vmstate_hi16_zmm_reg = {
90     .name = "hi16_zmm_reg",
91     .version_id = 1,
92     .minimum_version_id = 1,
93     .fields = (VMStateField[]) {
94         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
95         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
96         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
97         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
98         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
99         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
100         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
101         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
102         VMSTATE_END_OF_LIST()
103     }
104 };
105 
106 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start)               \
107     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
108                              vmstate_hi16_zmm_reg, ZMMReg)
109 #endif
110 
111 static const VMStateDescription vmstate_bnd_regs = {
112     .name = "bnd_regs",
113     .version_id = 1,
114     .minimum_version_id = 1,
115     .fields = (VMStateField[]) {
116         VMSTATE_UINT64(lb, BNDReg),
117         VMSTATE_UINT64(ub, BNDReg),
118         VMSTATE_END_OF_LIST()
119     }
120 };
121 
122 #define VMSTATE_BND_REGS(_field, _state, _n)          \
123     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
124 
125 static const VMStateDescription vmstate_mtrr_var = {
126     .name = "mtrr_var",
127     .version_id = 1,
128     .minimum_version_id = 1,
129     .fields = (VMStateField[]) {
130         VMSTATE_UINT64(base, MTRRVar),
131         VMSTATE_UINT64(mask, MTRRVar),
132         VMSTATE_END_OF_LIST()
133     }
134 };
135 
136 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
137     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
138 
139 static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
140 {
141     fprintf(stderr, "call put_fpreg() with invalid arguments\n");
142     exit(0);
143 }
144 
145 /* XXX: add that in a FPU generic layer */
146 union x86_longdouble {
147     uint64_t mant;
148     uint16_t exp;
149 };
150 
151 #define MANTD1(fp)	(fp & ((1LL << 52) - 1))
152 #define EXPBIAS1 1023
153 #define EXPD1(fp)	((fp >> 52) & 0x7FF)
154 #define SIGND1(fp)	((fp >> 32) & 0x80000000)
155 
156 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
157 {
158     int e;
159     /* mantissa */
160     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
161     /* exponent + sign */
162     e = EXPD1(temp) - EXPBIAS1 + 16383;
163     e |= SIGND1(temp) >> 16;
164     p->exp = e;
165 }
166 
167 static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
168 {
169     FPReg *fp_reg = opaque;
170     uint64_t mant;
171     uint16_t exp;
172 
173     qemu_get_be64s(f, &mant);
174     qemu_get_be16s(f, &exp);
175     fp_reg->d = cpu_set_fp80(mant, exp);
176     return 0;
177 }
178 
179 static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
180 {
181     FPReg *fp_reg = opaque;
182     uint64_t mant;
183     uint16_t exp;
184     /* we save the real CPU data (in case of MMX usage only 'mant'
185        contains the MMX register */
186     cpu_get_fp80(&mant, &exp, fp_reg->d);
187     qemu_put_be64s(f, &mant);
188     qemu_put_be16s(f, &exp);
189 }
190 
191 static const VMStateInfo vmstate_fpreg = {
192     .name = "fpreg",
193     .get  = get_fpreg,
194     .put  = put_fpreg,
195 };
196 
197 static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
198 {
199     union x86_longdouble *p = opaque;
200     uint64_t mant;
201 
202     qemu_get_be64s(f, &mant);
203     p->mant = mant;
204     p->exp = 0xffff;
205     return 0;
206 }
207 
208 static const VMStateInfo vmstate_fpreg_1_mmx = {
209     .name = "fpreg_1_mmx",
210     .get  = get_fpreg_1_mmx,
211     .put  = put_fpreg_error,
212 };
213 
214 static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
215 {
216     union x86_longdouble *p = opaque;
217     uint64_t mant;
218 
219     qemu_get_be64s(f, &mant);
220     fp64_to_fp80(p, mant);
221     return 0;
222 }
223 
224 static const VMStateInfo vmstate_fpreg_1_no_mmx = {
225     .name = "fpreg_1_no_mmx",
226     .get  = get_fpreg_1_no_mmx,
227     .put  = put_fpreg_error,
228 };
229 
230 static bool fpregs_is_0(void *opaque, int version_id)
231 {
232     X86CPU *cpu = opaque;
233     CPUX86State *env = &cpu->env;
234 
235     return (env->fpregs_format_vmstate == 0);
236 }
237 
238 static bool fpregs_is_1_mmx(void *opaque, int version_id)
239 {
240     X86CPU *cpu = opaque;
241     CPUX86State *env = &cpu->env;
242     int guess_mmx;
243 
244     guess_mmx = ((env->fptag_vmstate == 0xff) &&
245                  (env->fpus_vmstate & 0x3800) == 0);
246     return (guess_mmx && (env->fpregs_format_vmstate == 1));
247 }
248 
249 static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
250 {
251     X86CPU *cpu = opaque;
252     CPUX86State *env = &cpu->env;
253     int guess_mmx;
254 
255     guess_mmx = ((env->fptag_vmstate == 0xff) &&
256                  (env->fpus_vmstate & 0x3800) == 0);
257     return (!guess_mmx && (env->fpregs_format_vmstate == 1));
258 }
259 
260 #define VMSTATE_FP_REGS(_field, _state, _n)                               \
261     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
262     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
263     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
264 
265 static bool version_is_5(void *opaque, int version_id)
266 {
267     return version_id == 5;
268 }
269 
270 #ifdef TARGET_X86_64
271 static bool less_than_7(void *opaque, int version_id)
272 {
273     return version_id < 7;
274 }
275 
276 static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
277 {
278     uint64_t *v = pv;
279     *v = qemu_get_be32(f);
280     return 0;
281 }
282 
283 static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
284 {
285     uint64_t *v = pv;
286     qemu_put_be32(f, *v);
287 }
288 
289 static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
290     .name = "uint64_as_uint32",
291     .get  = get_uint64_as_uint32,
292     .put  = put_uint64_as_uint32,
293 };
294 
295 #define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
296     VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
297 #endif
298 
299 static void cpu_pre_save(void *opaque)
300 {
301     X86CPU *cpu = opaque;
302     CPUX86State *env = &cpu->env;
303     int i;
304 
305     /* FPU */
306     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
307     env->fptag_vmstate = 0;
308     for(i = 0; i < 8; i++) {
309         env->fptag_vmstate |= ((!env->fptags[i]) << i);
310     }
311 
312     env->fpregs_format_vmstate = 0;
313 
314     /*
315      * Real mode guest segments register DPL should be zero.
316      * Older KVM version were setting it wrongly.
317      * Fixing it will allow live migration to host with unrestricted guest
318      * support (otherwise the migration will fail with invalid guest state
319      * error).
320      */
321     if (!(env->cr[0] & CR0_PE_MASK) &&
322         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
323         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
324         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
325         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
326         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
327         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
328         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
329     }
330 
331 }
332 
333 static int cpu_post_load(void *opaque, int version_id)
334 {
335     X86CPU *cpu = opaque;
336     CPUState *cs = CPU(cpu);
337     CPUX86State *env = &cpu->env;
338     int i;
339 
340     if (env->tsc_khz && env->user_tsc_khz &&
341         env->tsc_khz != env->user_tsc_khz) {
342         error_report("Mismatch between user-specified TSC frequency and "
343                      "migrated TSC frequency");
344         return -EINVAL;
345     }
346 
347     /*
348      * Real mode guest segments register DPL should be zero.
349      * Older KVM version were setting it wrongly.
350      * Fixing it will allow live migration from such host that don't have
351      * restricted guest support to a host with unrestricted guest support
352      * (otherwise the migration will fail with invalid guest state
353      * error).
354      */
355     if (!(env->cr[0] & CR0_PE_MASK) &&
356         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
357         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
358         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
359         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
360         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
361         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
362         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
363     }
364 
365     /* Older versions of QEMU incorrectly used CS.DPL as the CPL when
366      * running under KVM.  This is wrong for conforming code segments.
367      * Luckily, in our implementation the CPL field of hflags is redundant
368      * and we can get the right value from the SS descriptor privilege level.
369      */
370     env->hflags &= ~HF_CPL_MASK;
371     env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
372 
373     env->fpstt = (env->fpus_vmstate >> 11) & 7;
374     env->fpus = env->fpus_vmstate & ~0x3800;
375     env->fptag_vmstate ^= 0xff;
376     for(i = 0; i < 8; i++) {
377         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
378     }
379     update_fp_status(env);
380 
381     cpu_breakpoint_remove_all(cs, BP_CPU);
382     cpu_watchpoint_remove_all(cs, BP_CPU);
383     {
384         /* Indicate all breakpoints disabled, as they are, then
385            let the helper re-enable them.  */
386         target_ulong dr7 = env->dr[7];
387         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
388         cpu_x86_update_dr7(env, dr7);
389     }
390     tlb_flush(cs);
391 
392     if (tcg_enabled()) {
393         cpu_smm_update(cpu);
394     }
395     return 0;
396 }
397 
398 static bool async_pf_msr_needed(void *opaque)
399 {
400     X86CPU *cpu = opaque;
401 
402     return cpu->env.async_pf_en_msr != 0;
403 }
404 
405 static bool pv_eoi_msr_needed(void *opaque)
406 {
407     X86CPU *cpu = opaque;
408 
409     return cpu->env.pv_eoi_en_msr != 0;
410 }
411 
412 static bool steal_time_msr_needed(void *opaque)
413 {
414     X86CPU *cpu = opaque;
415 
416     return cpu->env.steal_time_msr != 0;
417 }
418 
419 static const VMStateDescription vmstate_steal_time_msr = {
420     .name = "cpu/steal_time_msr",
421     .version_id = 1,
422     .minimum_version_id = 1,
423     .needed = steal_time_msr_needed,
424     .fields = (VMStateField[]) {
425         VMSTATE_UINT64(env.steal_time_msr, X86CPU),
426         VMSTATE_END_OF_LIST()
427     }
428 };
429 
430 static const VMStateDescription vmstate_async_pf_msr = {
431     .name = "cpu/async_pf_msr",
432     .version_id = 1,
433     .minimum_version_id = 1,
434     .needed = async_pf_msr_needed,
435     .fields = (VMStateField[]) {
436         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
437         VMSTATE_END_OF_LIST()
438     }
439 };
440 
441 static const VMStateDescription vmstate_pv_eoi_msr = {
442     .name = "cpu/async_pv_eoi_msr",
443     .version_id = 1,
444     .minimum_version_id = 1,
445     .needed = pv_eoi_msr_needed,
446     .fields = (VMStateField[]) {
447         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
448         VMSTATE_END_OF_LIST()
449     }
450 };
451 
452 static bool fpop_ip_dp_needed(void *opaque)
453 {
454     X86CPU *cpu = opaque;
455     CPUX86State *env = &cpu->env;
456 
457     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
458 }
459 
460 static const VMStateDescription vmstate_fpop_ip_dp = {
461     .name = "cpu/fpop_ip_dp",
462     .version_id = 1,
463     .minimum_version_id = 1,
464     .needed = fpop_ip_dp_needed,
465     .fields = (VMStateField[]) {
466         VMSTATE_UINT16(env.fpop, X86CPU),
467         VMSTATE_UINT64(env.fpip, X86CPU),
468         VMSTATE_UINT64(env.fpdp, X86CPU),
469         VMSTATE_END_OF_LIST()
470     }
471 };
472 
473 static bool tsc_adjust_needed(void *opaque)
474 {
475     X86CPU *cpu = opaque;
476     CPUX86State *env = &cpu->env;
477 
478     return env->tsc_adjust != 0;
479 }
480 
481 static const VMStateDescription vmstate_msr_tsc_adjust = {
482     .name = "cpu/msr_tsc_adjust",
483     .version_id = 1,
484     .minimum_version_id = 1,
485     .needed = tsc_adjust_needed,
486     .fields = (VMStateField[]) {
487         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
488         VMSTATE_END_OF_LIST()
489     }
490 };
491 
492 static bool tscdeadline_needed(void *opaque)
493 {
494     X86CPU *cpu = opaque;
495     CPUX86State *env = &cpu->env;
496 
497     return env->tsc_deadline != 0;
498 }
499 
500 static const VMStateDescription vmstate_msr_tscdeadline = {
501     .name = "cpu/msr_tscdeadline",
502     .version_id = 1,
503     .minimum_version_id = 1,
504     .needed = tscdeadline_needed,
505     .fields = (VMStateField[]) {
506         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
507         VMSTATE_END_OF_LIST()
508     }
509 };
510 
511 static bool misc_enable_needed(void *opaque)
512 {
513     X86CPU *cpu = opaque;
514     CPUX86State *env = &cpu->env;
515 
516     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
517 }
518 
519 static bool feature_control_needed(void *opaque)
520 {
521     X86CPU *cpu = opaque;
522     CPUX86State *env = &cpu->env;
523 
524     return env->msr_ia32_feature_control != 0;
525 }
526 
527 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
528     .name = "cpu/msr_ia32_misc_enable",
529     .version_id = 1,
530     .minimum_version_id = 1,
531     .needed = misc_enable_needed,
532     .fields = (VMStateField[]) {
533         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
534         VMSTATE_END_OF_LIST()
535     }
536 };
537 
538 static const VMStateDescription vmstate_msr_ia32_feature_control = {
539     .name = "cpu/msr_ia32_feature_control",
540     .version_id = 1,
541     .minimum_version_id = 1,
542     .needed = feature_control_needed,
543     .fields = (VMStateField[]) {
544         VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
545         VMSTATE_END_OF_LIST()
546     }
547 };
548 
549 static bool pmu_enable_needed(void *opaque)
550 {
551     X86CPU *cpu = opaque;
552     CPUX86State *env = &cpu->env;
553     int i;
554 
555     if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
556         env->msr_global_status || env->msr_global_ovf_ctrl) {
557         return true;
558     }
559     for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
560         if (env->msr_fixed_counters[i]) {
561             return true;
562         }
563     }
564     for (i = 0; i < MAX_GP_COUNTERS; i++) {
565         if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
566             return true;
567         }
568     }
569 
570     return false;
571 }
572 
573 static const VMStateDescription vmstate_msr_architectural_pmu = {
574     .name = "cpu/msr_architectural_pmu",
575     .version_id = 1,
576     .minimum_version_id = 1,
577     .needed = pmu_enable_needed,
578     .fields = (VMStateField[]) {
579         VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
580         VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
581         VMSTATE_UINT64(env.msr_global_status, X86CPU),
582         VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
583         VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
584         VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
585         VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
586         VMSTATE_END_OF_LIST()
587     }
588 };
589 
590 static bool mpx_needed(void *opaque)
591 {
592     X86CPU *cpu = opaque;
593     CPUX86State *env = &cpu->env;
594     unsigned int i;
595 
596     for (i = 0; i < 4; i++) {
597         if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
598             return true;
599         }
600     }
601 
602     if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
603         return true;
604     }
605 
606     return !!env->msr_bndcfgs;
607 }
608 
609 static const VMStateDescription vmstate_mpx = {
610     .name = "cpu/mpx",
611     .version_id = 1,
612     .minimum_version_id = 1,
613     .needed = mpx_needed,
614     .fields = (VMStateField[]) {
615         VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
616         VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
617         VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
618         VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
619         VMSTATE_END_OF_LIST()
620     }
621 };
622 
623 static bool hyperv_hypercall_enable_needed(void *opaque)
624 {
625     X86CPU *cpu = opaque;
626     CPUX86State *env = &cpu->env;
627 
628     return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
629 }
630 
631 static const VMStateDescription vmstate_msr_hypercall_hypercall = {
632     .name = "cpu/msr_hyperv_hypercall",
633     .version_id = 1,
634     .minimum_version_id = 1,
635     .needed = hyperv_hypercall_enable_needed,
636     .fields = (VMStateField[]) {
637         VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
638         VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
639         VMSTATE_END_OF_LIST()
640     }
641 };
642 
643 static bool hyperv_vapic_enable_needed(void *opaque)
644 {
645     X86CPU *cpu = opaque;
646     CPUX86State *env = &cpu->env;
647 
648     return env->msr_hv_vapic != 0;
649 }
650 
651 static const VMStateDescription vmstate_msr_hyperv_vapic = {
652     .name = "cpu/msr_hyperv_vapic",
653     .version_id = 1,
654     .minimum_version_id = 1,
655     .needed = hyperv_vapic_enable_needed,
656     .fields = (VMStateField[]) {
657         VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
658         VMSTATE_END_OF_LIST()
659     }
660 };
661 
662 static bool hyperv_time_enable_needed(void *opaque)
663 {
664     X86CPU *cpu = opaque;
665     CPUX86State *env = &cpu->env;
666 
667     return env->msr_hv_tsc != 0;
668 }
669 
670 static const VMStateDescription vmstate_msr_hyperv_time = {
671     .name = "cpu/msr_hyperv_time",
672     .version_id = 1,
673     .minimum_version_id = 1,
674     .needed = hyperv_time_enable_needed,
675     .fields = (VMStateField[]) {
676         VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
677         VMSTATE_END_OF_LIST()
678     }
679 };
680 
681 static bool hyperv_crash_enable_needed(void *opaque)
682 {
683     X86CPU *cpu = opaque;
684     CPUX86State *env = &cpu->env;
685     int i;
686 
687     for (i = 0; i < HV_X64_MSR_CRASH_PARAMS; i++) {
688         if (env->msr_hv_crash_params[i]) {
689             return true;
690         }
691     }
692     return false;
693 }
694 
695 static const VMStateDescription vmstate_msr_hyperv_crash = {
696     .name = "cpu/msr_hyperv_crash",
697     .version_id = 1,
698     .minimum_version_id = 1,
699     .needed = hyperv_crash_enable_needed,
700     .fields = (VMStateField[]) {
701         VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params,
702                              X86CPU, HV_X64_MSR_CRASH_PARAMS),
703         VMSTATE_END_OF_LIST()
704     }
705 };
706 
707 static bool hyperv_runtime_enable_needed(void *opaque)
708 {
709     X86CPU *cpu = opaque;
710     CPUX86State *env = &cpu->env;
711 
712     if (!cpu->hyperv_runtime) {
713         return false;
714     }
715 
716     return env->msr_hv_runtime != 0;
717 }
718 
719 static const VMStateDescription vmstate_msr_hyperv_runtime = {
720     .name = "cpu/msr_hyperv_runtime",
721     .version_id = 1,
722     .minimum_version_id = 1,
723     .needed = hyperv_runtime_enable_needed,
724     .fields = (VMStateField[]) {
725         VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
726         VMSTATE_END_OF_LIST()
727     }
728 };
729 
730 static bool hyperv_synic_enable_needed(void *opaque)
731 {
732     X86CPU *cpu = opaque;
733     CPUX86State *env = &cpu->env;
734     int i;
735 
736     if (env->msr_hv_synic_control != 0 ||
737         env->msr_hv_synic_evt_page != 0 ||
738         env->msr_hv_synic_msg_page != 0) {
739         return true;
740     }
741 
742     for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
743         if (env->msr_hv_synic_sint[i] != 0) {
744             return true;
745         }
746     }
747 
748     return false;
749 }
750 
751 static const VMStateDescription vmstate_msr_hyperv_synic = {
752     .name = "cpu/msr_hyperv_synic",
753     .version_id = 1,
754     .minimum_version_id = 1,
755     .needed = hyperv_synic_enable_needed,
756     .fields = (VMStateField[]) {
757         VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
758         VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
759         VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
760         VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU,
761                              HV_SYNIC_SINT_COUNT),
762         VMSTATE_END_OF_LIST()
763     }
764 };
765 
766 static bool hyperv_stimer_enable_needed(void *opaque)
767 {
768     X86CPU *cpu = opaque;
769     CPUX86State *env = &cpu->env;
770     int i;
771 
772     for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
773         if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
774             return true;
775         }
776     }
777     return false;
778 }
779 
780 static const VMStateDescription vmstate_msr_hyperv_stimer = {
781     .name = "cpu/msr_hyperv_stimer",
782     .version_id = 1,
783     .minimum_version_id = 1,
784     .needed = hyperv_stimer_enable_needed,
785     .fields = (VMStateField[]) {
786         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config,
787                              X86CPU, HV_SYNIC_STIMER_COUNT),
788         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count,
789                              X86CPU, HV_SYNIC_STIMER_COUNT),
790         VMSTATE_END_OF_LIST()
791     }
792 };
793 
794 static bool avx512_needed(void *opaque)
795 {
796     X86CPU *cpu = opaque;
797     CPUX86State *env = &cpu->env;
798     unsigned int i;
799 
800     for (i = 0; i < NB_OPMASK_REGS; i++) {
801         if (env->opmask_regs[i]) {
802             return true;
803         }
804     }
805 
806     for (i = 0; i < CPU_NB_REGS; i++) {
807 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
808         if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
809             ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
810             return true;
811         }
812 #ifdef TARGET_X86_64
813         if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
814             ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
815             ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
816             ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
817             return true;
818         }
819 #endif
820     }
821 
822     return false;
823 }
824 
825 static const VMStateDescription vmstate_avx512 = {
826     .name = "cpu/avx512",
827     .version_id = 1,
828     .minimum_version_id = 1,
829     .needed = avx512_needed,
830     .fields = (VMStateField[]) {
831         VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
832         VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
833 #ifdef TARGET_X86_64
834         VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
835 #endif
836         VMSTATE_END_OF_LIST()
837     }
838 };
839 
840 static bool xss_needed(void *opaque)
841 {
842     X86CPU *cpu = opaque;
843     CPUX86State *env = &cpu->env;
844 
845     return env->xss != 0;
846 }
847 
848 static const VMStateDescription vmstate_xss = {
849     .name = "cpu/xss",
850     .version_id = 1,
851     .minimum_version_id = 1,
852     .needed = xss_needed,
853     .fields = (VMStateField[]) {
854         VMSTATE_UINT64(env.xss, X86CPU),
855         VMSTATE_END_OF_LIST()
856     }
857 };
858 
859 #ifdef TARGET_X86_64
860 static bool pkru_needed(void *opaque)
861 {
862     X86CPU *cpu = opaque;
863     CPUX86State *env = &cpu->env;
864 
865     return env->pkru != 0;
866 }
867 
868 static const VMStateDescription vmstate_pkru = {
869     .name = "cpu/pkru",
870     .version_id = 1,
871     .minimum_version_id = 1,
872     .needed = pkru_needed,
873     .fields = (VMStateField[]){
874         VMSTATE_UINT32(env.pkru, X86CPU),
875         VMSTATE_END_OF_LIST()
876     }
877 };
878 #endif
879 
880 static bool tsc_khz_needed(void *opaque)
881 {
882     X86CPU *cpu = opaque;
883     CPUX86State *env = &cpu->env;
884     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
885     PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
886     return env->tsc_khz && pcmc->save_tsc_khz;
887 }
888 
889 static const VMStateDescription vmstate_tsc_khz = {
890     .name = "cpu/tsc_khz",
891     .version_id = 1,
892     .minimum_version_id = 1,
893     .needed = tsc_khz_needed,
894     .fields = (VMStateField[]) {
895         VMSTATE_INT64(env.tsc_khz, X86CPU),
896         VMSTATE_END_OF_LIST()
897     }
898 };
899 
900 static bool mcg_ext_ctl_needed(void *opaque)
901 {
902     X86CPU *cpu = opaque;
903     CPUX86State *env = &cpu->env;
904     return cpu->enable_lmce && env->mcg_ext_ctl;
905 }
906 
907 static const VMStateDescription vmstate_mcg_ext_ctl = {
908     .name = "cpu/mcg_ext_ctl",
909     .version_id = 1,
910     .minimum_version_id = 1,
911     .needed = mcg_ext_ctl_needed,
912     .fields = (VMStateField[]) {
913         VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU),
914         VMSTATE_END_OF_LIST()
915     }
916 };
917 
918 VMStateDescription vmstate_x86_cpu = {
919     .name = "cpu",
920     .version_id = 12,
921     .minimum_version_id = 3,
922     .pre_save = cpu_pre_save,
923     .post_load = cpu_post_load,
924     .fields = (VMStateField[]) {
925         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
926         VMSTATE_UINTTL(env.eip, X86CPU),
927         VMSTATE_UINTTL(env.eflags, X86CPU),
928         VMSTATE_UINT32(env.hflags, X86CPU),
929         /* FPU */
930         VMSTATE_UINT16(env.fpuc, X86CPU),
931         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
932         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
933         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
934         VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
935 
936         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
937         VMSTATE_SEGMENT(env.ldt, X86CPU),
938         VMSTATE_SEGMENT(env.tr, X86CPU),
939         VMSTATE_SEGMENT(env.gdt, X86CPU),
940         VMSTATE_SEGMENT(env.idt, X86CPU),
941 
942         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
943 #ifdef TARGET_X86_64
944         /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
945         VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
946         VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
947         VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
948         VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
949 #else
950         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
951         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
952 #endif
953 
954         VMSTATE_UINTTL(env.cr[0], X86CPU),
955         VMSTATE_UINTTL(env.cr[2], X86CPU),
956         VMSTATE_UINTTL(env.cr[3], X86CPU),
957         VMSTATE_UINTTL(env.cr[4], X86CPU),
958         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
959         /* MMU */
960         VMSTATE_INT32(env.a20_mask, X86CPU),
961         /* XMM */
962         VMSTATE_UINT32(env.mxcsr, X86CPU),
963         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
964 
965 #ifdef TARGET_X86_64
966         VMSTATE_UINT64(env.efer, X86CPU),
967         VMSTATE_UINT64(env.star, X86CPU),
968         VMSTATE_UINT64(env.lstar, X86CPU),
969         VMSTATE_UINT64(env.cstar, X86CPU),
970         VMSTATE_UINT64(env.fmask, X86CPU),
971         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
972 #endif
973         VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
974 
975         VMSTATE_UINT64_V(env.pat, X86CPU, 5),
976         VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
977 
978         VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5),
979         VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
980         VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
981         VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
982         VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
983         VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
984         VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
985         VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
986         VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
987         VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
988         VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
989         /* MTRRs */
990         VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
991         VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
992         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
993         /* KVM-related states */
994         VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
995         VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
996         VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
997         VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
998         VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
999         VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
1000         VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
1001         VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
1002         VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
1003         /* MCE */
1004         VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
1005         VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
1006         VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
1007         VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
1008         /* rdtscp */
1009         VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
1010         /* KVM pvclock msr */
1011         VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
1012         VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
1013         /* XSAVE related fields */
1014         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
1015         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
1016         VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
1017         VMSTATE_END_OF_LIST()
1018         /* The above list is not sorted /wrt version numbers, watch out! */
1019     },
1020     .subsections = (const VMStateDescription*[]) {
1021         &vmstate_async_pf_msr,
1022         &vmstate_pv_eoi_msr,
1023         &vmstate_steal_time_msr,
1024         &vmstate_fpop_ip_dp,
1025         &vmstate_msr_tsc_adjust,
1026         &vmstate_msr_tscdeadline,
1027         &vmstate_msr_ia32_misc_enable,
1028         &vmstate_msr_ia32_feature_control,
1029         &vmstate_msr_architectural_pmu,
1030         &vmstate_mpx,
1031         &vmstate_msr_hypercall_hypercall,
1032         &vmstate_msr_hyperv_vapic,
1033         &vmstate_msr_hyperv_time,
1034         &vmstate_msr_hyperv_crash,
1035         &vmstate_msr_hyperv_runtime,
1036         &vmstate_msr_hyperv_synic,
1037         &vmstate_msr_hyperv_stimer,
1038         &vmstate_avx512,
1039         &vmstate_xss,
1040         &vmstate_tsc_khz,
1041 #ifdef TARGET_X86_64
1042         &vmstate_pkru,
1043 #endif
1044         &vmstate_mcg_ext_ctl,
1045         NULL
1046     }
1047 };
1048