1756e12e7SXiaoyao Li /* SPDX-License-Identifier: GPL-2.0-or-later */ 2756e12e7SXiaoyao Li 3756e12e7SXiaoyao Li #ifndef QEMU_I386_TDX_H 4756e12e7SXiaoyao Li #define QEMU_I386_TDX_H 5756e12e7SXiaoyao Li 61619d0e4SXiaoyao Li #ifndef CONFIG_USER_ONLY 71619d0e4SXiaoyao Li #include CONFIG_DEVICES /* CONFIG_TDX */ 81619d0e4SXiaoyao Li #endif 91619d0e4SXiaoyao Li 10756e12e7SXiaoyao Li #include "confidential-guest.h" 11cb5d65a8SXiaoyao Li #include "hw/i386/tdvf.h" 12756e12e7SXiaoyao Li 13756e12e7SXiaoyao Li #define TYPE_TDX_GUEST "tdx-guest" 14756e12e7SXiaoyao Li #define TDX_GUEST(obj) OBJECT_CHECK(TdxGuest, (obj), TYPE_TDX_GUEST) 15756e12e7SXiaoyao Li 16756e12e7SXiaoyao Li typedef struct TdxGuestClass { 17756e12e7SXiaoyao Li X86ConfidentialGuestClass parent_class; 18756e12e7SXiaoyao Li } TdxGuestClass; 19756e12e7SXiaoyao Li 20d529a2acSXiaoyao Li /* TDX requires bus frequency 25MHz */ 21d529a2acSXiaoyao Li #define TDX_APIC_BUS_CYCLES_NS 40 22d529a2acSXiaoyao Li 23*f18672e4SXiaoyao Li enum TdxRamType { 24*f18672e4SXiaoyao Li TDX_RAM_UNACCEPTED, 25*f18672e4SXiaoyao Li TDX_RAM_ADDED, 26*f18672e4SXiaoyao Li }; 27*f18672e4SXiaoyao Li 28*f18672e4SXiaoyao Li typedef struct TdxRamEntry { 29*f18672e4SXiaoyao Li uint64_t address; 30*f18672e4SXiaoyao Li uint64_t length; 31*f18672e4SXiaoyao Li enum TdxRamType type; 32*f18672e4SXiaoyao Li } TdxRamEntry; 33*f18672e4SXiaoyao Li 34756e12e7SXiaoyao Li typedef struct TdxGuest { 35756e12e7SXiaoyao Li X86ConfidentialGuest parent_obj; 36756e12e7SXiaoyao Li 37f15898b0SXiaoyao Li QemuMutex lock; 38f15898b0SXiaoyao Li 39f15898b0SXiaoyao Li bool initialized; 40756e12e7SXiaoyao Li uint64_t attributes; /* TD attributes */ 41f15898b0SXiaoyao Li uint64_t xfam; 42d05a0858SIsaku Yamahata char *mrconfigid; /* base64 encoded sha348 digest */ 43d05a0858SIsaku Yamahata char *mrowner; /* base64 encoded sha348 digest */ 44d05a0858SIsaku Yamahata char *mrownerconfig; /* base64 encoded sha348 digest */ 450dd5fe5eSChao Peng 460dd5fe5eSChao Peng MemoryRegion *tdvf_mr; 47cb5d65a8SXiaoyao Li TdxFirmware tdvf; 48*f18672e4SXiaoyao Li 49*f18672e4SXiaoyao Li uint32_t nr_ram_entries; 50*f18672e4SXiaoyao Li TdxRamEntry *ram_entries; 51756e12e7SXiaoyao Li } TdxGuest; 52756e12e7SXiaoyao Li 531619d0e4SXiaoyao Li #ifdef CONFIG_TDX 541619d0e4SXiaoyao Li bool is_tdx_vm(void); 551619d0e4SXiaoyao Li #else 561619d0e4SXiaoyao Li #define is_tdx_vm() 0 571619d0e4SXiaoyao Li #endif /* CONFIG_TDX */ 581619d0e4SXiaoyao Li 59f15898b0SXiaoyao Li int tdx_pre_create_vcpu(CPUState *cpu, Error **errp); 600dd5fe5eSChao Peng void tdx_set_tdvf_region(MemoryRegion *tdvf_mr); 61cb5d65a8SXiaoyao Li int tdx_parse_tdvf(void *flash_ptr, int size); 62f15898b0SXiaoyao Li 63756e12e7SXiaoyao Li #endif /* QEMU_I386_TDX_H */ 64