1 /* 2 * QEMU KVM support 3 * 4 * Copyright (C) 2006-2008 Qumranet Technologies 5 * Copyright IBM, Corp. 2008 6 * 7 * Authors: 8 * Anthony Liguori <aliguori@us.ibm.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2 or later. 11 * See the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qapi/qapi-events-run-state.h" 17 #include "qapi/error.h" 18 #include <sys/ioctl.h> 19 #include <sys/utsname.h> 20 21 #include <linux/kvm.h> 22 #include "standard-headers/asm-x86/kvm_para.h" 23 24 #include "cpu.h" 25 #include "host-cpu.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/hw_accel.h" 28 #include "sysemu/kvm_int.h" 29 #include "sysemu/runstate.h" 30 #include "kvm_i386.h" 31 #include "sev_i386.h" 32 #include "hyperv.h" 33 #include "hyperv-proto.h" 34 35 #include "exec/gdbstub.h" 36 #include "qemu/host-utils.h" 37 #include "qemu/main-loop.h" 38 #include "qemu/config-file.h" 39 #include "qemu/error-report.h" 40 #include "hw/i386/x86.h" 41 #include "hw/i386/apic.h" 42 #include "hw/i386/apic_internal.h" 43 #include "hw/i386/apic-msidef.h" 44 #include "hw/i386/intel_iommu.h" 45 #include "hw/i386/x86-iommu.h" 46 #include "hw/i386/e820_memory_layout.h" 47 #include "sysemu/sev.h" 48 49 #include "hw/pci/pci.h" 50 #include "hw/pci/msi.h" 51 #include "hw/pci/msix.h" 52 #include "migration/blocker.h" 53 #include "exec/memattrs.h" 54 #include "trace.h" 55 56 //#define DEBUG_KVM 57 58 #ifdef DEBUG_KVM 59 #define DPRINTF(fmt, ...) \ 60 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 61 #else 62 #define DPRINTF(fmt, ...) \ 63 do { } while (0) 64 #endif 65 66 /* From arch/x86/kvm/lapic.h */ 67 #define KVM_APIC_BUS_CYCLE_NS 1 68 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS) 69 70 #define MSR_KVM_WALL_CLOCK 0x11 71 #define MSR_KVM_SYSTEM_TIME 0x12 72 73 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus 74 * 255 kvm_msr_entry structs */ 75 #define MSR_BUF_SIZE 4096 76 77 static void kvm_init_msrs(X86CPU *cpu); 78 79 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 80 KVM_CAP_INFO(SET_TSS_ADDR), 81 KVM_CAP_INFO(EXT_CPUID), 82 KVM_CAP_INFO(MP_STATE), 83 KVM_CAP_LAST_INFO 84 }; 85 86 static bool has_msr_star; 87 static bool has_msr_hsave_pa; 88 static bool has_msr_tsc_aux; 89 static bool has_msr_tsc_adjust; 90 static bool has_msr_tsc_deadline; 91 static bool has_msr_feature_control; 92 static bool has_msr_misc_enable; 93 static bool has_msr_smbase; 94 static bool has_msr_bndcfgs; 95 static int lm_capable_kernel; 96 static bool has_msr_hv_hypercall; 97 static bool has_msr_hv_crash; 98 static bool has_msr_hv_reset; 99 static bool has_msr_hv_vpindex; 100 static bool hv_vpindex_settable; 101 static bool has_msr_hv_runtime; 102 static bool has_msr_hv_synic; 103 static bool has_msr_hv_stimer; 104 static bool has_msr_hv_frequencies; 105 static bool has_msr_hv_reenlightenment; 106 static bool has_msr_xss; 107 static bool has_msr_umwait; 108 static bool has_msr_spec_ctrl; 109 static bool has_msr_tsx_ctrl; 110 static bool has_msr_virt_ssbd; 111 static bool has_msr_smi_count; 112 static bool has_msr_arch_capabs; 113 static bool has_msr_core_capabs; 114 static bool has_msr_vmx_vmfunc; 115 static bool has_msr_ucode_rev; 116 static bool has_msr_vmx_procbased_ctls2; 117 static bool has_msr_perf_capabs; 118 static bool has_msr_pkrs; 119 120 static uint32_t has_architectural_pmu_version; 121 static uint32_t num_architectural_pmu_gp_counters; 122 static uint32_t num_architectural_pmu_fixed_counters; 123 124 static int has_xsave; 125 static int has_xcrs; 126 static int has_pit_state2; 127 static int has_exception_payload; 128 129 static bool has_msr_mcg_ext_ctl; 130 131 static struct kvm_cpuid2 *cpuid_cache; 132 static struct kvm_cpuid2 *hv_cpuid_cache; 133 static struct kvm_msr_list *kvm_feature_msrs; 134 135 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */ 136 static RateLimit bus_lock_ratelimit_ctrl; 137 138 int kvm_has_pit_state2(void) 139 { 140 return has_pit_state2; 141 } 142 143 bool kvm_has_smm(void) 144 { 145 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM); 146 } 147 148 bool kvm_has_adjust_clock_stable(void) 149 { 150 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK); 151 152 return (ret == KVM_CLOCK_TSC_STABLE); 153 } 154 155 bool kvm_has_adjust_clock(void) 156 { 157 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK); 158 } 159 160 bool kvm_has_exception_payload(void) 161 { 162 return has_exception_payload; 163 } 164 165 static bool kvm_x2apic_api_set_flags(uint64_t flags) 166 { 167 KVMState *s = KVM_STATE(current_accel()); 168 169 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags); 170 } 171 172 #define MEMORIZE(fn, _result) \ 173 ({ \ 174 static bool _memorized; \ 175 \ 176 if (_memorized) { \ 177 return _result; \ 178 } \ 179 _memorized = true; \ 180 _result = fn; \ 181 }) 182 183 static bool has_x2apic_api; 184 185 bool kvm_has_x2apic_api(void) 186 { 187 return has_x2apic_api; 188 } 189 190 bool kvm_enable_x2apic(void) 191 { 192 return MEMORIZE( 193 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS | 194 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK), 195 has_x2apic_api); 196 } 197 198 bool kvm_hv_vpindex_settable(void) 199 { 200 return hv_vpindex_settable; 201 } 202 203 static int kvm_get_tsc(CPUState *cs) 204 { 205 X86CPU *cpu = X86_CPU(cs); 206 CPUX86State *env = &cpu->env; 207 struct { 208 struct kvm_msrs info; 209 struct kvm_msr_entry entries[1]; 210 } msr_data = {}; 211 int ret; 212 213 if (env->tsc_valid) { 214 return 0; 215 } 216 217 memset(&msr_data, 0, sizeof(msr_data)); 218 msr_data.info.nmsrs = 1; 219 msr_data.entries[0].index = MSR_IA32_TSC; 220 env->tsc_valid = !runstate_is_running(); 221 222 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); 223 if (ret < 0) { 224 return ret; 225 } 226 227 assert(ret == 1); 228 env->tsc = msr_data.entries[0].data; 229 return 0; 230 } 231 232 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg) 233 { 234 kvm_get_tsc(cpu); 235 } 236 237 void kvm_synchronize_all_tsc(void) 238 { 239 CPUState *cpu; 240 241 if (kvm_enabled()) { 242 CPU_FOREACH(cpu) { 243 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL); 244 } 245 } 246 } 247 248 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) 249 { 250 struct kvm_cpuid2 *cpuid; 251 int r, size; 252 253 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); 254 cpuid = g_malloc0(size); 255 cpuid->nent = max; 256 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); 257 if (r == 0 && cpuid->nent >= max) { 258 r = -E2BIG; 259 } 260 if (r < 0) { 261 if (r == -E2BIG) { 262 g_free(cpuid); 263 return NULL; 264 } else { 265 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", 266 strerror(-r)); 267 exit(1); 268 } 269 } 270 return cpuid; 271 } 272 273 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough 274 * for all entries. 275 */ 276 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) 277 { 278 struct kvm_cpuid2 *cpuid; 279 int max = 1; 280 281 if (cpuid_cache != NULL) { 282 return cpuid_cache; 283 } 284 while ((cpuid = try_get_cpuid(s, max)) == NULL) { 285 max *= 2; 286 } 287 cpuid_cache = cpuid; 288 return cpuid; 289 } 290 291 static bool host_tsx_broken(void) 292 { 293 int family, model, stepping;\ 294 char vendor[CPUID_VENDOR_SZ + 1]; 295 296 host_cpu_vendor_fms(vendor, &family, &model, &stepping); 297 298 /* Check if we are running on a Haswell host known to have broken TSX */ 299 return !strcmp(vendor, CPUID_VENDOR_INTEL) && 300 (family == 6) && 301 ((model == 63 && stepping < 4) || 302 model == 60 || model == 69 || model == 70); 303 } 304 305 /* Returns the value for a specific register on the cpuid entry 306 */ 307 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) 308 { 309 uint32_t ret = 0; 310 switch (reg) { 311 case R_EAX: 312 ret = entry->eax; 313 break; 314 case R_EBX: 315 ret = entry->ebx; 316 break; 317 case R_ECX: 318 ret = entry->ecx; 319 break; 320 case R_EDX: 321 ret = entry->edx; 322 break; 323 } 324 return ret; 325 } 326 327 /* Find matching entry for function/index on kvm_cpuid2 struct 328 */ 329 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, 330 uint32_t function, 331 uint32_t index) 332 { 333 int i; 334 for (i = 0; i < cpuid->nent; ++i) { 335 if (cpuid->entries[i].function == function && 336 cpuid->entries[i].index == index) { 337 return &cpuid->entries[i]; 338 } 339 } 340 /* not found: */ 341 return NULL; 342 } 343 344 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, 345 uint32_t index, int reg) 346 { 347 struct kvm_cpuid2 *cpuid; 348 uint32_t ret = 0; 349 uint32_t cpuid_1_edx; 350 351 cpuid = get_supported_cpuid(s); 352 353 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); 354 if (entry) { 355 ret = cpuid_entry_get_reg(entry, reg); 356 } 357 358 /* Fixups for the data returned by KVM, below */ 359 360 if (function == 1 && reg == R_EDX) { 361 /* KVM before 2.6.30 misreports the following features */ 362 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; 363 } else if (function == 1 && reg == R_ECX) { 364 /* We can set the hypervisor flag, even if KVM does not return it on 365 * GET_SUPPORTED_CPUID 366 */ 367 ret |= CPUID_EXT_HYPERVISOR; 368 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it 369 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, 370 * and the irqchip is in the kernel. 371 */ 372 if (kvm_irqchip_in_kernel() && 373 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { 374 ret |= CPUID_EXT_TSC_DEADLINE_TIMER; 375 } 376 377 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled 378 * without the in-kernel irqchip 379 */ 380 if (!kvm_irqchip_in_kernel()) { 381 ret &= ~CPUID_EXT_X2APIC; 382 } 383 384 if (enable_cpu_pm) { 385 int disable_exits = kvm_check_extension(s, 386 KVM_CAP_X86_DISABLE_EXITS); 387 388 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) { 389 ret |= CPUID_EXT_MONITOR; 390 } 391 } 392 } else if (function == 6 && reg == R_EAX) { 393 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ 394 } else if (function == 7 && index == 0 && reg == R_EBX) { 395 if (host_tsx_broken()) { 396 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE); 397 } 398 } else if (function == 7 && index == 0 && reg == R_EDX) { 399 /* 400 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts. 401 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is 402 * returned by KVM_GET_MSR_INDEX_LIST. 403 */ 404 if (!has_msr_arch_capabs) { 405 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES; 406 } 407 } else if (function == 0x80000001 && reg == R_ECX) { 408 /* 409 * It's safe to enable TOPOEXT even if it's not returned by 410 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows 411 * us to keep CPU models including TOPOEXT runnable on older kernels. 412 */ 413 ret |= CPUID_EXT3_TOPOEXT; 414 } else if (function == 0x80000001 && reg == R_EDX) { 415 /* On Intel, kvm returns cpuid according to the Intel spec, 416 * so add missing bits according to the AMD spec: 417 */ 418 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); 419 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; 420 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) { 421 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't 422 * be enabled without the in-kernel irqchip 423 */ 424 if (!kvm_irqchip_in_kernel()) { 425 ret &= ~(1U << KVM_FEATURE_PV_UNHALT); 426 } 427 if (kvm_irqchip_is_split()) { 428 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID; 429 } 430 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) { 431 ret |= 1U << KVM_HINTS_REALTIME; 432 } 433 434 return ret; 435 } 436 437 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) 438 { 439 struct { 440 struct kvm_msrs info; 441 struct kvm_msr_entry entries[1]; 442 } msr_data = {}; 443 uint64_t value; 444 uint32_t ret, can_be_one, must_be_one; 445 446 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */ 447 return 0; 448 } 449 450 /* Check if requested MSR is supported feature MSR */ 451 int i; 452 for (i = 0; i < kvm_feature_msrs->nmsrs; i++) 453 if (kvm_feature_msrs->indices[i] == index) { 454 break; 455 } 456 if (i == kvm_feature_msrs->nmsrs) { 457 return 0; /* if the feature MSR is not supported, simply return 0 */ 458 } 459 460 msr_data.info.nmsrs = 1; 461 msr_data.entries[0].index = index; 462 463 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data); 464 if (ret != 1) { 465 error_report("KVM get MSR (index=0x%x) feature failed, %s", 466 index, strerror(-ret)); 467 exit(1); 468 } 469 470 value = msr_data.entries[0].data; 471 switch (index) { 472 case MSR_IA32_VMX_PROCBASED_CTLS2: 473 if (!has_msr_vmx_procbased_ctls2) { 474 /* KVM forgot to add these bits for some time, do this ourselves. */ 475 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) & 476 CPUID_XSAVE_XSAVES) { 477 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32; 478 } 479 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) & 480 CPUID_EXT_RDRAND) { 481 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32; 482 } 483 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & 484 CPUID_7_0_EBX_INVPCID) { 485 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32; 486 } 487 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & 488 CPUID_7_0_EBX_RDSEED) { 489 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32; 490 } 491 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) & 492 CPUID_EXT2_RDTSCP) { 493 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32; 494 } 495 } 496 /* fall through */ 497 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 498 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 499 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 500 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 501 /* 502 * Return true for bits that can be one, but do not have to be one. 503 * The SDM tells us which bits could have a "must be one" setting, 504 * so we can do the opposite transformation in make_vmx_msr_value. 505 */ 506 must_be_one = (uint32_t)value; 507 can_be_one = (uint32_t)(value >> 32); 508 return can_be_one & ~must_be_one; 509 510 default: 511 return value; 512 } 513 } 514 515 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, 516 int *max_banks) 517 { 518 int r; 519 520 r = kvm_check_extension(s, KVM_CAP_MCE); 521 if (r > 0) { 522 *max_banks = r; 523 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); 524 } 525 return -ENOSYS; 526 } 527 528 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) 529 { 530 CPUState *cs = CPU(cpu); 531 CPUX86State *env = &cpu->env; 532 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | 533 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; 534 uint64_t mcg_status = MCG_STATUS_MCIP; 535 int flags = 0; 536 537 if (code == BUS_MCEERR_AR) { 538 status |= MCI_STATUS_AR | 0x134; 539 mcg_status |= MCG_STATUS_EIPV; 540 } else { 541 status |= 0xc0; 542 mcg_status |= MCG_STATUS_RIPV; 543 } 544 545 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0; 546 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the 547 * guest kernel back into env->mcg_ext_ctl. 548 */ 549 cpu_synchronize_state(cs); 550 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) { 551 mcg_status |= MCG_STATUS_LMCE; 552 flags = 0; 553 } 554 555 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, 556 (MCM_ADDR_PHYS << 6) | 0xc, flags); 557 } 558 559 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar) 560 { 561 MemoryFailureFlags mff = {.action_required = ar, .recursive = false}; 562 563 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action, 564 &mff); 565 } 566 567 static void hardware_memory_error(void *host_addr) 568 { 569 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true); 570 error_report("QEMU got Hardware memory error at addr %p", host_addr); 571 exit(1); 572 } 573 574 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) 575 { 576 X86CPU *cpu = X86_CPU(c); 577 CPUX86State *env = &cpu->env; 578 ram_addr_t ram_addr; 579 hwaddr paddr; 580 581 /* If we get an action required MCE, it has been injected by KVM 582 * while the VM was running. An action optional MCE instead should 583 * be coming from the main thread, which qemu_init_sigbus identifies 584 * as the "early kill" thread. 585 */ 586 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); 587 588 if ((env->mcg_cap & MCG_SER_P) && addr) { 589 ram_addr = qemu_ram_addr_from_host(addr); 590 if (ram_addr != RAM_ADDR_INVALID && 591 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { 592 kvm_hwpoison_page_add(ram_addr); 593 kvm_mce_inject(cpu, paddr, code); 594 595 /* 596 * Use different logging severity based on error type. 597 * If there is additional MCE reporting on the hypervisor, QEMU VA 598 * could be another source to identify the PA and MCE details. 599 */ 600 if (code == BUS_MCEERR_AR) { 601 error_report("Guest MCE Memory Error at QEMU addr %p and " 602 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", 603 addr, paddr, "BUS_MCEERR_AR"); 604 } else { 605 warn_report("Guest MCE Memory Error at QEMU addr %p and " 606 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", 607 addr, paddr, "BUS_MCEERR_AO"); 608 } 609 610 return; 611 } 612 613 if (code == BUS_MCEERR_AO) { 614 warn_report("Hardware memory error at addr %p of type %s " 615 "for memory used by QEMU itself instead of guest system!", 616 addr, "BUS_MCEERR_AO"); 617 } 618 } 619 620 if (code == BUS_MCEERR_AR) { 621 hardware_memory_error(addr); 622 } 623 624 /* Hope we are lucky for AO MCE, just notify a event */ 625 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false); 626 } 627 628 static void kvm_reset_exception(CPUX86State *env) 629 { 630 env->exception_nr = -1; 631 env->exception_pending = 0; 632 env->exception_injected = 0; 633 env->exception_has_payload = false; 634 env->exception_payload = 0; 635 } 636 637 static void kvm_queue_exception(CPUX86State *env, 638 int32_t exception_nr, 639 uint8_t exception_has_payload, 640 uint64_t exception_payload) 641 { 642 assert(env->exception_nr == -1); 643 assert(!env->exception_pending); 644 assert(!env->exception_injected); 645 assert(!env->exception_has_payload); 646 647 env->exception_nr = exception_nr; 648 649 if (has_exception_payload) { 650 env->exception_pending = 1; 651 652 env->exception_has_payload = exception_has_payload; 653 env->exception_payload = exception_payload; 654 } else { 655 env->exception_injected = 1; 656 657 if (exception_nr == EXCP01_DB) { 658 assert(exception_has_payload); 659 env->dr[6] = exception_payload; 660 } else if (exception_nr == EXCP0E_PAGE) { 661 assert(exception_has_payload); 662 env->cr[2] = exception_payload; 663 } else { 664 assert(!exception_has_payload); 665 } 666 } 667 } 668 669 static int kvm_inject_mce_oldstyle(X86CPU *cpu) 670 { 671 CPUX86State *env = &cpu->env; 672 673 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) { 674 unsigned int bank, bank_num = env->mcg_cap & 0xff; 675 struct kvm_x86_mce mce; 676 677 kvm_reset_exception(env); 678 679 /* 680 * There must be at least one bank in use if an MCE is pending. 681 * Find it and use its values for the event injection. 682 */ 683 for (bank = 0; bank < bank_num; bank++) { 684 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { 685 break; 686 } 687 } 688 assert(bank < bank_num); 689 690 mce.bank = bank; 691 mce.status = env->mce_banks[bank * 4 + 1]; 692 mce.mcg_status = env->mcg_status; 693 mce.addr = env->mce_banks[bank * 4 + 2]; 694 mce.misc = env->mce_banks[bank * 4 + 3]; 695 696 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce); 697 } 698 return 0; 699 } 700 701 static void cpu_update_state(void *opaque, bool running, RunState state) 702 { 703 CPUX86State *env = opaque; 704 705 if (running) { 706 env->tsc_valid = false; 707 } 708 } 709 710 unsigned long kvm_arch_vcpu_id(CPUState *cs) 711 { 712 X86CPU *cpu = X86_CPU(cs); 713 return cpu->apic_id; 714 } 715 716 #ifndef KVM_CPUID_SIGNATURE_NEXT 717 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 718 #endif 719 720 static bool hyperv_enabled(X86CPU *cpu) 721 { 722 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 && 723 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) || 724 cpu->hyperv_features || cpu->hyperv_passthrough); 725 } 726 727 /* 728 * Check whether target_freq is within conservative 729 * ntp correctable bounds (250ppm) of freq 730 */ 731 static inline bool freq_within_bounds(int freq, int target_freq) 732 { 733 int max_freq = freq + (freq * 250 / 1000000); 734 int min_freq = freq - (freq * 250 / 1000000); 735 736 if (target_freq >= min_freq && target_freq <= max_freq) { 737 return true; 738 } 739 740 return false; 741 } 742 743 static int kvm_arch_set_tsc_khz(CPUState *cs) 744 { 745 X86CPU *cpu = X86_CPU(cs); 746 CPUX86State *env = &cpu->env; 747 int r, cur_freq; 748 bool set_ioctl = false; 749 750 if (!env->tsc_khz) { 751 return 0; 752 } 753 754 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 755 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP; 756 757 /* 758 * If TSC scaling is supported, attempt to set TSC frequency. 759 */ 760 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) { 761 set_ioctl = true; 762 } 763 764 /* 765 * If desired TSC frequency is within bounds of NTP correction, 766 * attempt to set TSC frequency. 767 */ 768 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) { 769 set_ioctl = true; 770 } 771 772 r = set_ioctl ? 773 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) : 774 -ENOTSUP; 775 776 if (r < 0) { 777 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current 778 * TSC frequency doesn't match the one we want. 779 */ 780 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 781 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : 782 -ENOTSUP; 783 if (cur_freq <= 0 || cur_freq != env->tsc_khz) { 784 warn_report("TSC frequency mismatch between " 785 "VM (%" PRId64 " kHz) and host (%d kHz), " 786 "and TSC scaling unavailable", 787 env->tsc_khz, cur_freq); 788 return r; 789 } 790 } 791 792 return 0; 793 } 794 795 static bool tsc_is_stable_and_known(CPUX86State *env) 796 { 797 if (!env->tsc_khz) { 798 return false; 799 } 800 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) 801 || env->user_tsc_khz; 802 } 803 804 static struct { 805 const char *desc; 806 struct { 807 uint32_t func; 808 int reg; 809 uint32_t bits; 810 } flags[2]; 811 uint64_t dependencies; 812 } kvm_hyperv_properties[] = { 813 [HYPERV_FEAT_RELAXED] = { 814 .desc = "relaxed timing (hv-relaxed)", 815 .flags = { 816 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 817 .bits = HV_RELAXED_TIMING_RECOMMENDED} 818 } 819 }, 820 [HYPERV_FEAT_VAPIC] = { 821 .desc = "virtual APIC (hv-vapic)", 822 .flags = { 823 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 824 .bits = HV_APIC_ACCESS_AVAILABLE}, 825 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 826 .bits = HV_APIC_ACCESS_RECOMMENDED} 827 } 828 }, 829 [HYPERV_FEAT_TIME] = { 830 .desc = "clocksources (hv-time)", 831 .flags = { 832 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 833 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE} 834 } 835 }, 836 [HYPERV_FEAT_CRASH] = { 837 .desc = "crash MSRs (hv-crash)", 838 .flags = { 839 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 840 .bits = HV_GUEST_CRASH_MSR_AVAILABLE} 841 } 842 }, 843 [HYPERV_FEAT_RESET] = { 844 .desc = "reset MSR (hv-reset)", 845 .flags = { 846 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 847 .bits = HV_RESET_AVAILABLE} 848 } 849 }, 850 [HYPERV_FEAT_VPINDEX] = { 851 .desc = "VP_INDEX MSR (hv-vpindex)", 852 .flags = { 853 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 854 .bits = HV_VP_INDEX_AVAILABLE} 855 } 856 }, 857 [HYPERV_FEAT_RUNTIME] = { 858 .desc = "VP_RUNTIME MSR (hv-runtime)", 859 .flags = { 860 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 861 .bits = HV_VP_RUNTIME_AVAILABLE} 862 } 863 }, 864 [HYPERV_FEAT_SYNIC] = { 865 .desc = "synthetic interrupt controller (hv-synic)", 866 .flags = { 867 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 868 .bits = HV_SYNIC_AVAILABLE} 869 } 870 }, 871 [HYPERV_FEAT_STIMER] = { 872 .desc = "synthetic timers (hv-stimer)", 873 .flags = { 874 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 875 .bits = HV_SYNTIMERS_AVAILABLE} 876 }, 877 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME) 878 }, 879 [HYPERV_FEAT_FREQUENCIES] = { 880 .desc = "frequency MSRs (hv-frequencies)", 881 .flags = { 882 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 883 .bits = HV_ACCESS_FREQUENCY_MSRS}, 884 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 885 .bits = HV_FREQUENCY_MSRS_AVAILABLE} 886 } 887 }, 888 [HYPERV_FEAT_REENLIGHTENMENT] = { 889 .desc = "reenlightenment MSRs (hv-reenlightenment)", 890 .flags = { 891 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 892 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL} 893 } 894 }, 895 [HYPERV_FEAT_TLBFLUSH] = { 896 .desc = "paravirtualized TLB flush (hv-tlbflush)", 897 .flags = { 898 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 899 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED | 900 HV_EX_PROCESSOR_MASKS_RECOMMENDED} 901 }, 902 .dependencies = BIT(HYPERV_FEAT_VPINDEX) 903 }, 904 [HYPERV_FEAT_EVMCS] = { 905 .desc = "enlightened VMCS (hv-evmcs)", 906 .flags = { 907 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 908 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED} 909 }, 910 .dependencies = BIT(HYPERV_FEAT_VAPIC) 911 }, 912 [HYPERV_FEAT_IPI] = { 913 .desc = "paravirtualized IPI (hv-ipi)", 914 .flags = { 915 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 916 .bits = HV_CLUSTER_IPI_RECOMMENDED | 917 HV_EX_PROCESSOR_MASKS_RECOMMENDED} 918 }, 919 .dependencies = BIT(HYPERV_FEAT_VPINDEX) 920 }, 921 [HYPERV_FEAT_STIMER_DIRECT] = { 922 .desc = "direct mode synthetic timers (hv-stimer-direct)", 923 .flags = { 924 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 925 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE} 926 }, 927 .dependencies = BIT(HYPERV_FEAT_STIMER) 928 }, 929 }; 930 931 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max, 932 bool do_sys_ioctl) 933 { 934 struct kvm_cpuid2 *cpuid; 935 int r, size; 936 937 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); 938 cpuid = g_malloc0(size); 939 cpuid->nent = max; 940 941 if (do_sys_ioctl) { 942 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid); 943 } else { 944 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid); 945 } 946 if (r == 0 && cpuid->nent >= max) { 947 r = -E2BIG; 948 } 949 if (r < 0) { 950 if (r == -E2BIG) { 951 g_free(cpuid); 952 return NULL; 953 } else { 954 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n", 955 strerror(-r)); 956 exit(1); 957 } 958 } 959 return cpuid; 960 } 961 962 /* 963 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough 964 * for all entries. 965 */ 966 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs) 967 { 968 struct kvm_cpuid2 *cpuid; 969 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000080 leaves */ 970 int max = 10; 971 int i; 972 bool do_sys_ioctl; 973 974 do_sys_ioctl = 975 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0; 976 977 /* 978 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is 979 * unsupported, kvm_hyperv_expand_features() checks for that. 980 */ 981 assert(do_sys_ioctl || cs->kvm_state); 982 983 /* 984 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with 985 * -E2BIG, however, it doesn't report back the right size. Keep increasing 986 * it and re-trying until we succeed. 987 */ 988 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) { 989 max++; 990 } 991 992 /* 993 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before 994 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the 995 * information early, just check for the capability and set the bit 996 * manually. 997 */ 998 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state, 999 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { 1000 for (i = 0; i < cpuid->nent; i++) { 1001 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) { 1002 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED; 1003 } 1004 } 1005 } 1006 1007 return cpuid; 1008 } 1009 1010 /* 1011 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature 1012 * leaves from KVM_CAP_HYPERV* and present MSRs data. 1013 */ 1014 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs) 1015 { 1016 X86CPU *cpu = X86_CPU(cs); 1017 struct kvm_cpuid2 *cpuid; 1018 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm; 1019 1020 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */ 1021 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries)); 1022 cpuid->nent = 2; 1023 1024 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */ 1025 entry_feat = &cpuid->entries[0]; 1026 entry_feat->function = HV_CPUID_FEATURES; 1027 1028 entry_recomm = &cpuid->entries[1]; 1029 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO; 1030 entry_recomm->ebx = cpu->hyperv_spinlock_attempts; 1031 1032 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) { 1033 entry_feat->eax |= HV_HYPERCALL_AVAILABLE; 1034 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE; 1035 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; 1036 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED; 1037 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED; 1038 } 1039 1040 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { 1041 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE; 1042 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE; 1043 } 1044 1045 if (has_msr_hv_frequencies) { 1046 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS; 1047 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE; 1048 } 1049 1050 if (has_msr_hv_crash) { 1051 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE; 1052 } 1053 1054 if (has_msr_hv_reenlightenment) { 1055 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL; 1056 } 1057 1058 if (has_msr_hv_reset) { 1059 entry_feat->eax |= HV_RESET_AVAILABLE; 1060 } 1061 1062 if (has_msr_hv_vpindex) { 1063 entry_feat->eax |= HV_VP_INDEX_AVAILABLE; 1064 } 1065 1066 if (has_msr_hv_runtime) { 1067 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE; 1068 } 1069 1070 if (has_msr_hv_synic) { 1071 unsigned int cap = cpu->hyperv_synic_kvm_only ? 1072 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; 1073 1074 if (kvm_check_extension(cs->kvm_state, cap) > 0) { 1075 entry_feat->eax |= HV_SYNIC_AVAILABLE; 1076 } 1077 } 1078 1079 if (has_msr_hv_stimer) { 1080 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE; 1081 } 1082 1083 if (kvm_check_extension(cs->kvm_state, 1084 KVM_CAP_HYPERV_TLBFLUSH) > 0) { 1085 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED; 1086 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED; 1087 } 1088 1089 if (kvm_check_extension(cs->kvm_state, 1090 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { 1091 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED; 1092 } 1093 1094 if (kvm_check_extension(cs->kvm_state, 1095 KVM_CAP_HYPERV_SEND_IPI) > 0) { 1096 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED; 1097 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED; 1098 } 1099 1100 return cpuid; 1101 } 1102 1103 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg) 1104 { 1105 struct kvm_cpuid_entry2 *entry; 1106 struct kvm_cpuid2 *cpuid; 1107 1108 if (hv_cpuid_cache) { 1109 cpuid = hv_cpuid_cache; 1110 } else { 1111 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) { 1112 cpuid = get_supported_hv_cpuid(cs); 1113 } else { 1114 /* 1115 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded 1116 * before KVM context is created but this is only done when 1117 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies 1118 * KVM_CAP_HYPERV_CPUID. 1119 */ 1120 assert(cs->kvm_state); 1121 1122 cpuid = get_supported_hv_cpuid_legacy(cs); 1123 } 1124 hv_cpuid_cache = cpuid; 1125 } 1126 1127 if (!cpuid) { 1128 return 0; 1129 } 1130 1131 entry = cpuid_find_entry(cpuid, func, 0); 1132 if (!entry) { 1133 return 0; 1134 } 1135 1136 return cpuid_entry_get_reg(entry, reg); 1137 } 1138 1139 static bool hyperv_feature_supported(CPUState *cs, int feature) 1140 { 1141 uint32_t func, bits; 1142 int i, reg; 1143 1144 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) { 1145 1146 func = kvm_hyperv_properties[feature].flags[i].func; 1147 reg = kvm_hyperv_properties[feature].flags[i].reg; 1148 bits = kvm_hyperv_properties[feature].flags[i].bits; 1149 1150 if (!func) { 1151 continue; 1152 } 1153 1154 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) { 1155 return false; 1156 } 1157 } 1158 1159 return true; 1160 } 1161 1162 /* Checks that all feature dependencies are enabled */ 1163 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp) 1164 { 1165 uint64_t deps; 1166 int dep_feat; 1167 1168 deps = kvm_hyperv_properties[feature].dependencies; 1169 while (deps) { 1170 dep_feat = ctz64(deps); 1171 if (!(hyperv_feat_enabled(cpu, dep_feat))) { 1172 error_setg(errp, "Hyper-V %s requires Hyper-V %s", 1173 kvm_hyperv_properties[feature].desc, 1174 kvm_hyperv_properties[dep_feat].desc); 1175 return false; 1176 } 1177 deps &= ~(1ull << dep_feat); 1178 } 1179 1180 return true; 1181 } 1182 1183 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg) 1184 { 1185 X86CPU *cpu = X86_CPU(cs); 1186 uint32_t r = 0; 1187 int i, j; 1188 1189 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) { 1190 if (!hyperv_feat_enabled(cpu, i)) { 1191 continue; 1192 } 1193 1194 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) { 1195 if (kvm_hyperv_properties[i].flags[j].func != func) { 1196 continue; 1197 } 1198 if (kvm_hyperv_properties[i].flags[j].reg != reg) { 1199 continue; 1200 } 1201 1202 r |= kvm_hyperv_properties[i].flags[j].bits; 1203 } 1204 } 1205 1206 return r; 1207 } 1208 1209 /* 1210 * Expand Hyper-V CPU features. In partucular, check that all the requested 1211 * features are supported by the host and the sanity of the configuration 1212 * (that all the required dependencies are included). Also, this takes care 1213 * of 'hv_passthrough' mode and fills the environment with all supported 1214 * Hyper-V features. 1215 */ 1216 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp) 1217 { 1218 CPUState *cs = CPU(cpu); 1219 Error *local_err = NULL; 1220 int feat; 1221 1222 if (!hyperv_enabled(cpu)) 1223 return true; 1224 1225 /* 1226 * When kvm_hyperv_expand_features is called at CPU feature expansion 1227 * time per-CPU kvm_state is not available yet so we can only proceed 1228 * when KVM_CAP_SYS_HYPERV_CPUID is supported. 1229 */ 1230 if (!cs->kvm_state && 1231 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID)) 1232 return true; 1233 1234 if (cpu->hyperv_passthrough) { 1235 cpu->hyperv_vendor_id[0] = 1236 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX); 1237 cpu->hyperv_vendor_id[1] = 1238 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX); 1239 cpu->hyperv_vendor_id[2] = 1240 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX); 1241 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor, 1242 sizeof(cpu->hyperv_vendor_id) + 1); 1243 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id, 1244 sizeof(cpu->hyperv_vendor_id)); 1245 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0; 1246 1247 cpu->hyperv_interface_id[0] = 1248 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX); 1249 cpu->hyperv_interface_id[1] = 1250 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX); 1251 cpu->hyperv_interface_id[2] = 1252 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX); 1253 cpu->hyperv_interface_id[3] = 1254 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX); 1255 1256 cpu->hyperv_version_id[0] = 1257 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX); 1258 cpu->hyperv_version_id[1] = 1259 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX); 1260 cpu->hyperv_version_id[2] = 1261 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX); 1262 cpu->hyperv_version_id[3] = 1263 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX); 1264 1265 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, 1266 R_EAX); 1267 cpu->hyperv_limits[0] = 1268 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX); 1269 cpu->hyperv_limits[1] = 1270 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX); 1271 cpu->hyperv_limits[2] = 1272 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX); 1273 1274 cpu->hyperv_spinlock_attempts = 1275 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX); 1276 1277 /* 1278 * Mark feature as enabled in 'cpu->hyperv_features' as 1279 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs. 1280 */ 1281 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) { 1282 if (hyperv_feature_supported(cs, feat)) { 1283 cpu->hyperv_features |= BIT(feat); 1284 } 1285 } 1286 } else { 1287 /* Check features availability and dependencies */ 1288 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) { 1289 /* If the feature was not requested skip it. */ 1290 if (!hyperv_feat_enabled(cpu, feat)) { 1291 continue; 1292 } 1293 1294 /* Check if the feature is supported by KVM */ 1295 if (!hyperv_feature_supported(cs, feat)) { 1296 error_setg(errp, "Hyper-V %s is not supported by kernel", 1297 kvm_hyperv_properties[feat].desc); 1298 return false; 1299 } 1300 1301 /* Check dependencies */ 1302 if (!hv_feature_check_deps(cpu, feat, &local_err)) { 1303 error_propagate(errp, local_err); 1304 return false; 1305 } 1306 } 1307 } 1308 1309 /* Additional dependencies not covered by kvm_hyperv_properties[] */ 1310 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && 1311 !cpu->hyperv_synic_kvm_only && 1312 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { 1313 error_setg(errp, "Hyper-V %s requires Hyper-V %s", 1314 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc, 1315 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc); 1316 return false; 1317 } 1318 1319 return true; 1320 } 1321 1322 /* 1323 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent. 1324 */ 1325 static int hyperv_fill_cpuids(CPUState *cs, 1326 struct kvm_cpuid_entry2 *cpuid_ent) 1327 { 1328 X86CPU *cpu = X86_CPU(cs); 1329 struct kvm_cpuid_entry2 *c; 1330 uint32_t cpuid_i = 0; 1331 1332 c = &cpuid_ent[cpuid_i++]; 1333 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 1334 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? 1335 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; 1336 c->ebx = cpu->hyperv_vendor_id[0]; 1337 c->ecx = cpu->hyperv_vendor_id[1]; 1338 c->edx = cpu->hyperv_vendor_id[2]; 1339 1340 c = &cpuid_ent[cpuid_i++]; 1341 c->function = HV_CPUID_INTERFACE; 1342 c->eax = cpu->hyperv_interface_id[0]; 1343 c->ebx = cpu->hyperv_interface_id[1]; 1344 c->ecx = cpu->hyperv_interface_id[2]; 1345 c->edx = cpu->hyperv_interface_id[3]; 1346 1347 c = &cpuid_ent[cpuid_i++]; 1348 c->function = HV_CPUID_VERSION; 1349 c->eax = cpu->hyperv_version_id[0]; 1350 c->ebx = cpu->hyperv_version_id[1]; 1351 c->ecx = cpu->hyperv_version_id[2]; 1352 c->edx = cpu->hyperv_version_id[3]; 1353 1354 c = &cpuid_ent[cpuid_i++]; 1355 c->function = HV_CPUID_FEATURES; 1356 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX); 1357 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX); 1358 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX); 1359 1360 /* Unconditionally required with any Hyper-V enlightenment */ 1361 c->eax |= HV_HYPERCALL_AVAILABLE; 1362 1363 /* SynIC and Vmbus devices require messages/signals hypercalls */ 1364 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && 1365 !cpu->hyperv_synic_kvm_only) { 1366 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS; 1367 } 1368 1369 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */ 1370 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; 1371 1372 c = &cpuid_ent[cpuid_i++]; 1373 c->function = HV_CPUID_ENLIGHTMENT_INFO; 1374 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX); 1375 c->ebx = cpu->hyperv_spinlock_attempts; 1376 1377 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) { 1378 c->eax |= HV_NO_NONARCH_CORESHARING; 1379 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) { 1380 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) & 1381 HV_NO_NONARCH_CORESHARING; 1382 } 1383 1384 c = &cpuid_ent[cpuid_i++]; 1385 c->function = HV_CPUID_IMPLEMENT_LIMITS; 1386 c->eax = cpu->hv_max_vps; 1387 c->ebx = cpu->hyperv_limits[0]; 1388 c->ecx = cpu->hyperv_limits[1]; 1389 c->edx = cpu->hyperv_limits[2]; 1390 1391 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { 1392 __u32 function; 1393 1394 /* Create zeroed 0x40000006..0x40000009 leaves */ 1395 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1; 1396 function < HV_CPUID_NESTED_FEATURES; function++) { 1397 c = &cpuid_ent[cpuid_i++]; 1398 c->function = function; 1399 } 1400 1401 c = &cpuid_ent[cpuid_i++]; 1402 c->function = HV_CPUID_NESTED_FEATURES; 1403 c->eax = cpu->hyperv_nested[0]; 1404 } 1405 1406 return cpuid_i; 1407 } 1408 1409 static Error *hv_passthrough_mig_blocker; 1410 static Error *hv_no_nonarch_cs_mig_blocker; 1411 1412 /* Checks that the exposed eVMCS version range is supported by KVM */ 1413 static bool evmcs_version_supported(uint16_t evmcs_version, 1414 uint16_t supported_evmcs_version) 1415 { 1416 uint8_t min_version = evmcs_version & 0xff; 1417 uint8_t max_version = evmcs_version >> 8; 1418 uint8_t min_supported_version = supported_evmcs_version & 0xff; 1419 uint8_t max_supported_version = supported_evmcs_version >> 8; 1420 1421 return (min_version >= min_supported_version) && 1422 (max_version <= max_supported_version); 1423 } 1424 1425 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1) 1426 1427 static int hyperv_init_vcpu(X86CPU *cpu) 1428 { 1429 CPUState *cs = CPU(cpu); 1430 Error *local_err = NULL; 1431 int ret; 1432 1433 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) { 1434 error_setg(&hv_passthrough_mig_blocker, 1435 "'hv-passthrough' CPU flag prevents migration, use explicit" 1436 " set of hv-* flags instead"); 1437 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err); 1438 if (ret < 0) { 1439 error_report_err(local_err); 1440 return ret; 1441 } 1442 } 1443 1444 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO && 1445 hv_no_nonarch_cs_mig_blocker == NULL) { 1446 error_setg(&hv_no_nonarch_cs_mig_blocker, 1447 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration" 1448 " use explicit 'hv-no-nonarch-coresharing=on' instead (but" 1449 " make sure SMT is disabled and/or that vCPUs are properly" 1450 " pinned)"); 1451 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err); 1452 if (ret < 0) { 1453 error_report_err(local_err); 1454 return ret; 1455 } 1456 } 1457 1458 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) { 1459 /* 1460 * the kernel doesn't support setting vp_index; assert that its value 1461 * is in sync 1462 */ 1463 struct { 1464 struct kvm_msrs info; 1465 struct kvm_msr_entry entries[1]; 1466 } msr_data = { 1467 .info.nmsrs = 1, 1468 .entries[0].index = HV_X64_MSR_VP_INDEX, 1469 }; 1470 1471 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data); 1472 if (ret < 0) { 1473 return ret; 1474 } 1475 assert(ret == 1); 1476 1477 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) { 1478 error_report("kernel's vp_index != QEMU's vp_index"); 1479 return -ENXIO; 1480 } 1481 } 1482 1483 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 1484 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ? 1485 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; 1486 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0); 1487 if (ret < 0) { 1488 error_report("failed to turn on HyperV SynIC in KVM: %s", 1489 strerror(-ret)); 1490 return ret; 1491 } 1492 1493 if (!cpu->hyperv_synic_kvm_only) { 1494 ret = hyperv_x86_synic_add(cpu); 1495 if (ret < 0) { 1496 error_report("failed to create HyperV SynIC: %s", 1497 strerror(-ret)); 1498 return ret; 1499 } 1500 } 1501 } 1502 1503 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { 1504 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION; 1505 uint16_t supported_evmcs_version; 1506 1507 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0, 1508 (uintptr_t)&supported_evmcs_version); 1509 1510 /* 1511 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs' 1512 * option sets. Note: we hardcode the maximum supported eVMCS version 1513 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if) 1514 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have 1515 * to be added. 1516 */ 1517 if (ret < 0) { 1518 error_report("Hyper-V %s is not supported by kernel", 1519 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc); 1520 return ret; 1521 } 1522 1523 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) { 1524 error_report("eVMCS version range [%d..%d] is not supported by " 1525 "kernel (supported: [%d..%d])", evmcs_version & 0xff, 1526 evmcs_version >> 8, supported_evmcs_version & 0xff, 1527 supported_evmcs_version >> 8); 1528 return -ENOTSUP; 1529 } 1530 1531 cpu->hyperv_nested[0] = evmcs_version; 1532 } 1533 1534 return 0; 1535 } 1536 1537 static Error *invtsc_mig_blocker; 1538 1539 #define KVM_MAX_CPUID_ENTRIES 100 1540 1541 int kvm_arch_init_vcpu(CPUState *cs) 1542 { 1543 struct { 1544 struct kvm_cpuid2 cpuid; 1545 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; 1546 } cpuid_data; 1547 /* 1548 * The kernel defines these structs with padding fields so there 1549 * should be no extra padding in our cpuid_data struct. 1550 */ 1551 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) != 1552 sizeof(struct kvm_cpuid2) + 1553 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES); 1554 1555 X86CPU *cpu = X86_CPU(cs); 1556 CPUX86State *env = &cpu->env; 1557 uint32_t limit, i, j, cpuid_i; 1558 uint32_t unused; 1559 struct kvm_cpuid_entry2 *c; 1560 uint32_t signature[3]; 1561 int kvm_base = KVM_CPUID_SIGNATURE; 1562 int max_nested_state_len; 1563 int r; 1564 Error *local_err = NULL; 1565 1566 memset(&cpuid_data, 0, sizeof(cpuid_data)); 1567 1568 cpuid_i = 0; 1569 1570 r = kvm_arch_set_tsc_khz(cs); 1571 if (r < 0) { 1572 return r; 1573 } 1574 1575 /* vcpu's TSC frequency is either specified by user, or following 1576 * the value used by KVM if the former is not present. In the 1577 * latter case, we query it from KVM and record in env->tsc_khz, 1578 * so that vcpu's TSC frequency can be migrated later via this field. 1579 */ 1580 if (!env->tsc_khz) { 1581 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 1582 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : 1583 -ENOTSUP; 1584 if (r > 0) { 1585 env->tsc_khz = r; 1586 } 1587 } 1588 1589 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY; 1590 1591 /* 1592 * kvm_hyperv_expand_features() is called here for the second time in case 1593 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle 1594 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to 1595 * check which Hyper-V enlightenments are supported and which are not, we 1596 * can still proceed and check/expand Hyper-V enlightenments here so legacy 1597 * behavior is preserved. 1598 */ 1599 if (!kvm_hyperv_expand_features(cpu, &local_err)) { 1600 error_report_err(local_err); 1601 return -ENOSYS; 1602 } 1603 1604 if (hyperv_enabled(cpu)) { 1605 r = hyperv_init_vcpu(cpu); 1606 if (r) { 1607 return r; 1608 } 1609 1610 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries); 1611 kvm_base = KVM_CPUID_SIGNATURE_NEXT; 1612 has_msr_hv_hypercall = true; 1613 } 1614 1615 if (cpu->expose_kvm) { 1616 memcpy(signature, "KVMKVMKVM\0\0\0", 12); 1617 c = &cpuid_data.entries[cpuid_i++]; 1618 c->function = KVM_CPUID_SIGNATURE | kvm_base; 1619 c->eax = KVM_CPUID_FEATURES | kvm_base; 1620 c->ebx = signature[0]; 1621 c->ecx = signature[1]; 1622 c->edx = signature[2]; 1623 1624 c = &cpuid_data.entries[cpuid_i++]; 1625 c->function = KVM_CPUID_FEATURES | kvm_base; 1626 c->eax = env->features[FEAT_KVM]; 1627 c->edx = env->features[FEAT_KVM_HINTS]; 1628 } 1629 1630 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); 1631 1632 for (i = 0; i <= limit; i++) { 1633 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1634 fprintf(stderr, "unsupported level value: 0x%x\n", limit); 1635 abort(); 1636 } 1637 c = &cpuid_data.entries[cpuid_i++]; 1638 1639 switch (i) { 1640 case 2: { 1641 /* Keep reading function 2 till all the input is received */ 1642 int times; 1643 1644 c->function = i; 1645 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | 1646 KVM_CPUID_FLAG_STATE_READ_NEXT; 1647 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1648 times = c->eax & 0xff; 1649 1650 for (j = 1; j < times; ++j) { 1651 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1652 fprintf(stderr, "cpuid_data is full, no space for " 1653 "cpuid(eax:2):eax & 0xf = 0x%x\n", times); 1654 abort(); 1655 } 1656 c = &cpuid_data.entries[cpuid_i++]; 1657 c->function = i; 1658 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; 1659 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1660 } 1661 break; 1662 } 1663 case 0x1f: 1664 if (env->nr_dies < 2) { 1665 break; 1666 } 1667 /* fallthrough */ 1668 case 4: 1669 case 0xb: 1670 case 0xd: 1671 for (j = 0; ; j++) { 1672 if (i == 0xd && j == 64) { 1673 break; 1674 } 1675 1676 if (i == 0x1f && j == 64) { 1677 break; 1678 } 1679 1680 c->function = i; 1681 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1682 c->index = j; 1683 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1684 1685 if (i == 4 && c->eax == 0) { 1686 break; 1687 } 1688 if (i == 0xb && !(c->ecx & 0xff00)) { 1689 break; 1690 } 1691 if (i == 0x1f && !(c->ecx & 0xff00)) { 1692 break; 1693 } 1694 if (i == 0xd && c->eax == 0) { 1695 continue; 1696 } 1697 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1698 fprintf(stderr, "cpuid_data is full, no space for " 1699 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); 1700 abort(); 1701 } 1702 c = &cpuid_data.entries[cpuid_i++]; 1703 } 1704 break; 1705 case 0x7: 1706 case 0x12: 1707 for (j = 0; ; j++) { 1708 c->function = i; 1709 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1710 c->index = j; 1711 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1712 1713 if (j > 1 && (c->eax & 0xf) != 1) { 1714 break; 1715 } 1716 1717 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1718 fprintf(stderr, "cpuid_data is full, no space for " 1719 "cpuid(eax:0x12,ecx:0x%x)\n", j); 1720 abort(); 1721 } 1722 c = &cpuid_data.entries[cpuid_i++]; 1723 } 1724 break; 1725 case 0x14: { 1726 uint32_t times; 1727 1728 c->function = i; 1729 c->index = 0; 1730 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1731 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1732 times = c->eax; 1733 1734 for (j = 1; j <= times; ++j) { 1735 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1736 fprintf(stderr, "cpuid_data is full, no space for " 1737 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); 1738 abort(); 1739 } 1740 c = &cpuid_data.entries[cpuid_i++]; 1741 c->function = i; 1742 c->index = j; 1743 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1744 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1745 } 1746 break; 1747 } 1748 default: 1749 c->function = i; 1750 c->flags = 0; 1751 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1752 if (!c->eax && !c->ebx && !c->ecx && !c->edx) { 1753 /* 1754 * KVM already returns all zeroes if a CPUID entry is missing, 1755 * so we can omit it and avoid hitting KVM's 80-entry limit. 1756 */ 1757 cpuid_i--; 1758 } 1759 break; 1760 } 1761 } 1762 1763 if (limit >= 0x0a) { 1764 uint32_t eax, edx; 1765 1766 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); 1767 1768 has_architectural_pmu_version = eax & 0xff; 1769 if (has_architectural_pmu_version > 0) { 1770 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8; 1771 1772 /* Shouldn't be more than 32, since that's the number of bits 1773 * available in EBX to tell us _which_ counters are available. 1774 * Play it safe. 1775 */ 1776 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { 1777 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS; 1778 } 1779 1780 if (has_architectural_pmu_version > 1) { 1781 num_architectural_pmu_fixed_counters = edx & 0x1f; 1782 1783 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) { 1784 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS; 1785 } 1786 } 1787 } 1788 } 1789 1790 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); 1791 1792 for (i = 0x80000000; i <= limit; i++) { 1793 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1794 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); 1795 abort(); 1796 } 1797 c = &cpuid_data.entries[cpuid_i++]; 1798 1799 switch (i) { 1800 case 0x8000001d: 1801 /* Query for all AMD cache information leaves */ 1802 for (j = 0; ; j++) { 1803 c->function = i; 1804 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1805 c->index = j; 1806 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1807 1808 if (c->eax == 0) { 1809 break; 1810 } 1811 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1812 fprintf(stderr, "cpuid_data is full, no space for " 1813 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); 1814 abort(); 1815 } 1816 c = &cpuid_data.entries[cpuid_i++]; 1817 } 1818 break; 1819 default: 1820 c->function = i; 1821 c->flags = 0; 1822 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1823 if (!c->eax && !c->ebx && !c->ecx && !c->edx) { 1824 /* 1825 * KVM already returns all zeroes if a CPUID entry is missing, 1826 * so we can omit it and avoid hitting KVM's 80-entry limit. 1827 */ 1828 cpuid_i--; 1829 } 1830 break; 1831 } 1832 } 1833 1834 /* Call Centaur's CPUID instructions they are supported. */ 1835 if (env->cpuid_xlevel2 > 0) { 1836 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); 1837 1838 for (i = 0xC0000000; i <= limit; i++) { 1839 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1840 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit); 1841 abort(); 1842 } 1843 c = &cpuid_data.entries[cpuid_i++]; 1844 1845 c->function = i; 1846 c->flags = 0; 1847 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1848 } 1849 } 1850 1851 cpuid_data.cpuid.nent = cpuid_i; 1852 1853 if (((env->cpuid_version >> 8)&0xF) >= 6 1854 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 1855 (CPUID_MCE | CPUID_MCA) 1856 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { 1857 uint64_t mcg_cap, unsupported_caps; 1858 int banks; 1859 int ret; 1860 1861 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); 1862 if (ret < 0) { 1863 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); 1864 return ret; 1865 } 1866 1867 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) { 1868 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)", 1869 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks); 1870 return -ENOTSUP; 1871 } 1872 1873 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK); 1874 if (unsupported_caps) { 1875 if (unsupported_caps & MCG_LMCE_P) { 1876 error_report("kvm: LMCE not supported"); 1877 return -ENOTSUP; 1878 } 1879 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64, 1880 unsupported_caps); 1881 } 1882 1883 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK; 1884 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap); 1885 if (ret < 0) { 1886 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); 1887 return ret; 1888 } 1889 } 1890 1891 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env); 1892 1893 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); 1894 if (c) { 1895 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) || 1896 !!(c->ecx & CPUID_EXT_SMX); 1897 } 1898 1899 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0); 1900 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) { 1901 has_msr_feature_control = true; 1902 } 1903 1904 if (env->mcg_cap & MCG_LMCE_P) { 1905 has_msr_mcg_ext_ctl = has_msr_feature_control = true; 1906 } 1907 1908 if (!env->user_tsc_khz) { 1909 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && 1910 invtsc_mig_blocker == NULL) { 1911 error_setg(&invtsc_mig_blocker, 1912 "State blocked by non-migratable CPU device" 1913 " (invtsc flag)"); 1914 r = migrate_add_blocker(invtsc_mig_blocker, &local_err); 1915 if (r < 0) { 1916 error_report_err(local_err); 1917 return r; 1918 } 1919 } 1920 } 1921 1922 if (cpu->vmware_cpuid_freq 1923 /* Guests depend on 0x40000000 to detect this feature, so only expose 1924 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */ 1925 && cpu->expose_kvm 1926 && kvm_base == KVM_CPUID_SIGNATURE 1927 /* TSC clock must be stable and known for this feature. */ 1928 && tsc_is_stable_and_known(env)) { 1929 1930 c = &cpuid_data.entries[cpuid_i++]; 1931 c->function = KVM_CPUID_SIGNATURE | 0x10; 1932 c->eax = env->tsc_khz; 1933 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ 1934 c->ecx = c->edx = 0; 1935 1936 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0); 1937 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10); 1938 } 1939 1940 cpuid_data.cpuid.nent = cpuid_i; 1941 1942 cpuid_data.cpuid.padding = 0; 1943 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); 1944 if (r) { 1945 goto fail; 1946 } 1947 1948 if (has_xsave) { 1949 env->xsave_buf_len = sizeof(struct kvm_xsave); 1950 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len); 1951 memset(env->xsave_buf, 0, env->xsave_buf_len); 1952 1953 /* 1954 * The allocated storage must be large enough for all of the 1955 * possible XSAVE state components. 1956 */ 1957 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) 1958 <= env->xsave_buf_len); 1959 } 1960 1961 max_nested_state_len = kvm_max_nested_state_length(); 1962 if (max_nested_state_len > 0) { 1963 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data)); 1964 1965 if (cpu_has_vmx(env) || cpu_has_svm(env)) { 1966 struct kvm_vmx_nested_state_hdr *vmx_hdr; 1967 1968 env->nested_state = g_malloc0(max_nested_state_len); 1969 env->nested_state->size = max_nested_state_len; 1970 1971 if (cpu_has_vmx(env)) { 1972 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX; 1973 vmx_hdr = &env->nested_state->hdr.vmx; 1974 vmx_hdr->vmxon_pa = -1ull; 1975 vmx_hdr->vmcs12_pa = -1ull; 1976 } else { 1977 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM; 1978 } 1979 } 1980 } 1981 1982 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE); 1983 1984 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) { 1985 has_msr_tsc_aux = false; 1986 } 1987 1988 kvm_init_msrs(cpu); 1989 1990 return 0; 1991 1992 fail: 1993 migrate_del_blocker(invtsc_mig_blocker); 1994 1995 return r; 1996 } 1997 1998 int kvm_arch_destroy_vcpu(CPUState *cs) 1999 { 2000 X86CPU *cpu = X86_CPU(cs); 2001 CPUX86State *env = &cpu->env; 2002 2003 if (cpu->kvm_msr_buf) { 2004 g_free(cpu->kvm_msr_buf); 2005 cpu->kvm_msr_buf = NULL; 2006 } 2007 2008 if (env->nested_state) { 2009 g_free(env->nested_state); 2010 env->nested_state = NULL; 2011 } 2012 2013 qemu_del_vm_change_state_handler(cpu->vmsentry); 2014 2015 return 0; 2016 } 2017 2018 void kvm_arch_reset_vcpu(X86CPU *cpu) 2019 { 2020 CPUX86State *env = &cpu->env; 2021 2022 env->xcr0 = 1; 2023 if (kvm_irqchip_in_kernel()) { 2024 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : 2025 KVM_MP_STATE_UNINITIALIZED; 2026 } else { 2027 env->mp_state = KVM_MP_STATE_RUNNABLE; 2028 } 2029 2030 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 2031 int i; 2032 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { 2033 env->msr_hv_synic_sint[i] = HV_SINT_MASKED; 2034 } 2035 2036 hyperv_x86_synic_reset(cpu); 2037 } 2038 /* enabled by default */ 2039 env->poll_control_msr = 1; 2040 2041 sev_es_set_reset_vector(CPU(cpu)); 2042 } 2043 2044 void kvm_arch_do_init_vcpu(X86CPU *cpu) 2045 { 2046 CPUX86State *env = &cpu->env; 2047 2048 /* APs get directly into wait-for-SIPI state. */ 2049 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) { 2050 env->mp_state = KVM_MP_STATE_INIT_RECEIVED; 2051 } 2052 } 2053 2054 static int kvm_get_supported_feature_msrs(KVMState *s) 2055 { 2056 int ret = 0; 2057 2058 if (kvm_feature_msrs != NULL) { 2059 return 0; 2060 } 2061 2062 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) { 2063 return 0; 2064 } 2065 2066 struct kvm_msr_list msr_list; 2067 2068 msr_list.nmsrs = 0; 2069 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list); 2070 if (ret < 0 && ret != -E2BIG) { 2071 error_report("Fetch KVM feature MSR list failed: %s", 2072 strerror(-ret)); 2073 return ret; 2074 } 2075 2076 assert(msr_list.nmsrs > 0); 2077 kvm_feature_msrs = (struct kvm_msr_list *) \ 2078 g_malloc0(sizeof(msr_list) + 2079 msr_list.nmsrs * sizeof(msr_list.indices[0])); 2080 2081 kvm_feature_msrs->nmsrs = msr_list.nmsrs; 2082 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs); 2083 2084 if (ret < 0) { 2085 error_report("Fetch KVM feature MSR list failed: %s", 2086 strerror(-ret)); 2087 g_free(kvm_feature_msrs); 2088 kvm_feature_msrs = NULL; 2089 return ret; 2090 } 2091 2092 return 0; 2093 } 2094 2095 static int kvm_get_supported_msrs(KVMState *s) 2096 { 2097 int ret = 0; 2098 struct kvm_msr_list msr_list, *kvm_msr_list; 2099 2100 /* 2101 * Obtain MSR list from KVM. These are the MSRs that we must 2102 * save/restore. 2103 */ 2104 msr_list.nmsrs = 0; 2105 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); 2106 if (ret < 0 && ret != -E2BIG) { 2107 return ret; 2108 } 2109 /* 2110 * Old kernel modules had a bug and could write beyond the provided 2111 * memory. Allocate at least a safe amount of 1K. 2112 */ 2113 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + 2114 msr_list.nmsrs * 2115 sizeof(msr_list.indices[0]))); 2116 2117 kvm_msr_list->nmsrs = msr_list.nmsrs; 2118 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); 2119 if (ret >= 0) { 2120 int i; 2121 2122 for (i = 0; i < kvm_msr_list->nmsrs; i++) { 2123 switch (kvm_msr_list->indices[i]) { 2124 case MSR_STAR: 2125 has_msr_star = true; 2126 break; 2127 case MSR_VM_HSAVE_PA: 2128 has_msr_hsave_pa = true; 2129 break; 2130 case MSR_TSC_AUX: 2131 has_msr_tsc_aux = true; 2132 break; 2133 case MSR_TSC_ADJUST: 2134 has_msr_tsc_adjust = true; 2135 break; 2136 case MSR_IA32_TSCDEADLINE: 2137 has_msr_tsc_deadline = true; 2138 break; 2139 case MSR_IA32_SMBASE: 2140 has_msr_smbase = true; 2141 break; 2142 case MSR_SMI_COUNT: 2143 has_msr_smi_count = true; 2144 break; 2145 case MSR_IA32_MISC_ENABLE: 2146 has_msr_misc_enable = true; 2147 break; 2148 case MSR_IA32_BNDCFGS: 2149 has_msr_bndcfgs = true; 2150 break; 2151 case MSR_IA32_XSS: 2152 has_msr_xss = true; 2153 break; 2154 case MSR_IA32_UMWAIT_CONTROL: 2155 has_msr_umwait = true; 2156 break; 2157 case HV_X64_MSR_CRASH_CTL: 2158 has_msr_hv_crash = true; 2159 break; 2160 case HV_X64_MSR_RESET: 2161 has_msr_hv_reset = true; 2162 break; 2163 case HV_X64_MSR_VP_INDEX: 2164 has_msr_hv_vpindex = true; 2165 break; 2166 case HV_X64_MSR_VP_RUNTIME: 2167 has_msr_hv_runtime = true; 2168 break; 2169 case HV_X64_MSR_SCONTROL: 2170 has_msr_hv_synic = true; 2171 break; 2172 case HV_X64_MSR_STIMER0_CONFIG: 2173 has_msr_hv_stimer = true; 2174 break; 2175 case HV_X64_MSR_TSC_FREQUENCY: 2176 has_msr_hv_frequencies = true; 2177 break; 2178 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2179 has_msr_hv_reenlightenment = true; 2180 break; 2181 case MSR_IA32_SPEC_CTRL: 2182 has_msr_spec_ctrl = true; 2183 break; 2184 case MSR_IA32_TSX_CTRL: 2185 has_msr_tsx_ctrl = true; 2186 break; 2187 case MSR_VIRT_SSBD: 2188 has_msr_virt_ssbd = true; 2189 break; 2190 case MSR_IA32_ARCH_CAPABILITIES: 2191 has_msr_arch_capabs = true; 2192 break; 2193 case MSR_IA32_CORE_CAPABILITY: 2194 has_msr_core_capabs = true; 2195 break; 2196 case MSR_IA32_PERF_CAPABILITIES: 2197 has_msr_perf_capabs = true; 2198 break; 2199 case MSR_IA32_VMX_VMFUNC: 2200 has_msr_vmx_vmfunc = true; 2201 break; 2202 case MSR_IA32_UCODE_REV: 2203 has_msr_ucode_rev = true; 2204 break; 2205 case MSR_IA32_VMX_PROCBASED_CTLS2: 2206 has_msr_vmx_procbased_ctls2 = true; 2207 break; 2208 case MSR_IA32_PKRS: 2209 has_msr_pkrs = true; 2210 break; 2211 } 2212 } 2213 } 2214 2215 g_free(kvm_msr_list); 2216 2217 return ret; 2218 } 2219 2220 static Notifier smram_machine_done; 2221 static KVMMemoryListener smram_listener; 2222 static AddressSpace smram_address_space; 2223 static MemoryRegion smram_as_root; 2224 static MemoryRegion smram_as_mem; 2225 2226 static void register_smram_listener(Notifier *n, void *unused) 2227 { 2228 MemoryRegion *smram = 2229 (MemoryRegion *) object_resolve_path("/machine/smram", NULL); 2230 2231 /* Outer container... */ 2232 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull); 2233 memory_region_set_enabled(&smram_as_root, true); 2234 2235 /* ... with two regions inside: normal system memory with low 2236 * priority, and... 2237 */ 2238 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram", 2239 get_system_memory(), 0, ~0ull); 2240 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0); 2241 memory_region_set_enabled(&smram_as_mem, true); 2242 2243 if (smram) { 2244 /* ... SMRAM with higher priority */ 2245 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10); 2246 memory_region_set_enabled(smram, true); 2247 } 2248 2249 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM"); 2250 kvm_memory_listener_register(kvm_state, &smram_listener, 2251 &smram_address_space, 1, "kvm-smram"); 2252 } 2253 2254 int kvm_arch_init(MachineState *ms, KVMState *s) 2255 { 2256 uint64_t identity_base = 0xfffbc000; 2257 uint64_t shadow_mem; 2258 int ret; 2259 struct utsname utsname; 2260 Error *local_err = NULL; 2261 2262 /* 2263 * Initialize SEV context, if required 2264 * 2265 * If no memory encryption is requested (ms->cgs == NULL) this is 2266 * a no-op. 2267 * 2268 * It's also a no-op if a non-SEV confidential guest support 2269 * mechanism is selected. SEV is the only mechanism available to 2270 * select on x86 at present, so this doesn't arise, but if new 2271 * mechanisms are supported in future (e.g. TDX), they'll need 2272 * their own initialization either here or elsewhere. 2273 */ 2274 ret = sev_kvm_init(ms->cgs, &local_err); 2275 if (ret < 0) { 2276 error_report_err(local_err); 2277 return ret; 2278 } 2279 2280 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { 2281 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM"); 2282 return -ENOTSUP; 2283 } 2284 2285 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE); 2286 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS); 2287 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2); 2288 2289 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX); 2290 2291 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD); 2292 if (has_exception_payload) { 2293 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true); 2294 if (ret < 0) { 2295 error_report("kvm: Failed to enable exception payload cap: %s", 2296 strerror(-ret)); 2297 return ret; 2298 } 2299 } 2300 2301 ret = kvm_get_supported_msrs(s); 2302 if (ret < 0) { 2303 return ret; 2304 } 2305 2306 kvm_get_supported_feature_msrs(s); 2307 2308 uname(&utsname); 2309 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; 2310 2311 /* 2312 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. 2313 * In order to use vm86 mode, an EPT identity map and a TSS are needed. 2314 * Since these must be part of guest physical memory, we need to allocate 2315 * them, both by setting their start addresses in the kernel and by 2316 * creating a corresponding e820 entry. We need 4 pages before the BIOS. 2317 * 2318 * Older KVM versions may not support setting the identity map base. In 2319 * that case we need to stick with the default, i.e. a 256K maximum BIOS 2320 * size. 2321 */ 2322 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { 2323 /* Allows up to 16M BIOSes. */ 2324 identity_base = 0xfeffc000; 2325 2326 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); 2327 if (ret < 0) { 2328 return ret; 2329 } 2330 } 2331 2332 /* Set TSS base one page after EPT identity map. */ 2333 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); 2334 if (ret < 0) { 2335 return ret; 2336 } 2337 2338 /* Tell fw_cfg to notify the BIOS to reserve the range. */ 2339 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); 2340 if (ret < 0) { 2341 fprintf(stderr, "e820_add_entry() table is full\n"); 2342 return ret; 2343 } 2344 2345 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort); 2346 if (shadow_mem != -1) { 2347 shadow_mem /= 4096; 2348 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); 2349 if (ret < 0) { 2350 return ret; 2351 } 2352 } 2353 2354 if (kvm_check_extension(s, KVM_CAP_X86_SMM) && 2355 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) && 2356 x86_machine_is_smm_enabled(X86_MACHINE(ms))) { 2357 smram_machine_done.notify = register_smram_listener; 2358 qemu_add_machine_init_done_notifier(&smram_machine_done); 2359 } 2360 2361 if (enable_cpu_pm) { 2362 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS); 2363 int ret; 2364 2365 /* Work around for kernel header with a typo. TODO: fix header and drop. */ 2366 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT) 2367 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL 2368 #endif 2369 if (disable_exits) { 2370 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT | 2371 KVM_X86_DISABLE_EXITS_HLT | 2372 KVM_X86_DISABLE_EXITS_PAUSE | 2373 KVM_X86_DISABLE_EXITS_CSTATE); 2374 } 2375 2376 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0, 2377 disable_exits); 2378 if (ret < 0) { 2379 error_report("kvm: guest stopping CPU not supported: %s", 2380 strerror(-ret)); 2381 } 2382 } 2383 2384 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) { 2385 X86MachineState *x86ms = X86_MACHINE(ms); 2386 2387 if (x86ms->bus_lock_ratelimit > 0) { 2388 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT); 2389 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) { 2390 error_report("kvm: bus lock detection unsupported"); 2391 return -ENOTSUP; 2392 } 2393 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0, 2394 KVM_BUS_LOCK_DETECTION_EXIT); 2395 if (ret < 0) { 2396 error_report("kvm: Failed to enable bus lock detection cap: %s", 2397 strerror(-ret)); 2398 return ret; 2399 } 2400 ratelimit_init(&bus_lock_ratelimit_ctrl); 2401 ratelimit_set_speed(&bus_lock_ratelimit_ctrl, 2402 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME); 2403 } 2404 } 2405 2406 return 0; 2407 } 2408 2409 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) 2410 { 2411 lhs->selector = rhs->selector; 2412 lhs->base = rhs->base; 2413 lhs->limit = rhs->limit; 2414 lhs->type = 3; 2415 lhs->present = 1; 2416 lhs->dpl = 3; 2417 lhs->db = 0; 2418 lhs->s = 1; 2419 lhs->l = 0; 2420 lhs->g = 0; 2421 lhs->avl = 0; 2422 lhs->unusable = 0; 2423 } 2424 2425 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) 2426 { 2427 unsigned flags = rhs->flags; 2428 lhs->selector = rhs->selector; 2429 lhs->base = rhs->base; 2430 lhs->limit = rhs->limit; 2431 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; 2432 lhs->present = (flags & DESC_P_MASK) != 0; 2433 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; 2434 lhs->db = (flags >> DESC_B_SHIFT) & 1; 2435 lhs->s = (flags & DESC_S_MASK) != 0; 2436 lhs->l = (flags >> DESC_L_SHIFT) & 1; 2437 lhs->g = (flags & DESC_G_MASK) != 0; 2438 lhs->avl = (flags & DESC_AVL_MASK) != 0; 2439 lhs->unusable = !lhs->present; 2440 lhs->padding = 0; 2441 } 2442 2443 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) 2444 { 2445 lhs->selector = rhs->selector; 2446 lhs->base = rhs->base; 2447 lhs->limit = rhs->limit; 2448 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | 2449 ((rhs->present && !rhs->unusable) * DESC_P_MASK) | 2450 (rhs->dpl << DESC_DPL_SHIFT) | 2451 (rhs->db << DESC_B_SHIFT) | 2452 (rhs->s * DESC_S_MASK) | 2453 (rhs->l << DESC_L_SHIFT) | 2454 (rhs->g * DESC_G_MASK) | 2455 (rhs->avl * DESC_AVL_MASK); 2456 } 2457 2458 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) 2459 { 2460 if (set) { 2461 *kvm_reg = *qemu_reg; 2462 } else { 2463 *qemu_reg = *kvm_reg; 2464 } 2465 } 2466 2467 static int kvm_getput_regs(X86CPU *cpu, int set) 2468 { 2469 CPUX86State *env = &cpu->env; 2470 struct kvm_regs regs; 2471 int ret = 0; 2472 2473 if (!set) { 2474 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); 2475 if (ret < 0) { 2476 return ret; 2477 } 2478 } 2479 2480 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); 2481 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); 2482 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); 2483 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); 2484 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); 2485 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); 2486 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); 2487 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); 2488 #ifdef TARGET_X86_64 2489 kvm_getput_reg(®s.r8, &env->regs[8], set); 2490 kvm_getput_reg(®s.r9, &env->regs[9], set); 2491 kvm_getput_reg(®s.r10, &env->regs[10], set); 2492 kvm_getput_reg(®s.r11, &env->regs[11], set); 2493 kvm_getput_reg(®s.r12, &env->regs[12], set); 2494 kvm_getput_reg(®s.r13, &env->regs[13], set); 2495 kvm_getput_reg(®s.r14, &env->regs[14], set); 2496 kvm_getput_reg(®s.r15, &env->regs[15], set); 2497 #endif 2498 2499 kvm_getput_reg(®s.rflags, &env->eflags, set); 2500 kvm_getput_reg(®s.rip, &env->eip, set); 2501 2502 if (set) { 2503 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); 2504 } 2505 2506 return ret; 2507 } 2508 2509 static int kvm_put_fpu(X86CPU *cpu) 2510 { 2511 CPUX86State *env = &cpu->env; 2512 struct kvm_fpu fpu; 2513 int i; 2514 2515 memset(&fpu, 0, sizeof fpu); 2516 fpu.fsw = env->fpus & ~(7 << 11); 2517 fpu.fsw |= (env->fpstt & 7) << 11; 2518 fpu.fcw = env->fpuc; 2519 fpu.last_opcode = env->fpop; 2520 fpu.last_ip = env->fpip; 2521 fpu.last_dp = env->fpdp; 2522 for (i = 0; i < 8; ++i) { 2523 fpu.ftwx |= (!env->fptags[i]) << i; 2524 } 2525 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); 2526 for (i = 0; i < CPU_NB_REGS; i++) { 2527 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0)); 2528 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1)); 2529 } 2530 fpu.mxcsr = env->mxcsr; 2531 2532 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); 2533 } 2534 2535 static int kvm_put_xsave(X86CPU *cpu) 2536 { 2537 CPUX86State *env = &cpu->env; 2538 void *xsave = env->xsave_buf; 2539 2540 if (!has_xsave) { 2541 return kvm_put_fpu(cpu); 2542 } 2543 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len); 2544 2545 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); 2546 } 2547 2548 static int kvm_put_xcrs(X86CPU *cpu) 2549 { 2550 CPUX86State *env = &cpu->env; 2551 struct kvm_xcrs xcrs = {}; 2552 2553 if (!has_xcrs) { 2554 return 0; 2555 } 2556 2557 xcrs.nr_xcrs = 1; 2558 xcrs.flags = 0; 2559 xcrs.xcrs[0].xcr = 0; 2560 xcrs.xcrs[0].value = env->xcr0; 2561 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); 2562 } 2563 2564 static int kvm_put_sregs(X86CPU *cpu) 2565 { 2566 CPUX86State *env = &cpu->env; 2567 struct kvm_sregs sregs; 2568 2569 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); 2570 if (env->interrupt_injected >= 0) { 2571 sregs.interrupt_bitmap[env->interrupt_injected / 64] |= 2572 (uint64_t)1 << (env->interrupt_injected % 64); 2573 } 2574 2575 if ((env->eflags & VM_MASK)) { 2576 set_v8086_seg(&sregs.cs, &env->segs[R_CS]); 2577 set_v8086_seg(&sregs.ds, &env->segs[R_DS]); 2578 set_v8086_seg(&sregs.es, &env->segs[R_ES]); 2579 set_v8086_seg(&sregs.fs, &env->segs[R_FS]); 2580 set_v8086_seg(&sregs.gs, &env->segs[R_GS]); 2581 set_v8086_seg(&sregs.ss, &env->segs[R_SS]); 2582 } else { 2583 set_seg(&sregs.cs, &env->segs[R_CS]); 2584 set_seg(&sregs.ds, &env->segs[R_DS]); 2585 set_seg(&sregs.es, &env->segs[R_ES]); 2586 set_seg(&sregs.fs, &env->segs[R_FS]); 2587 set_seg(&sregs.gs, &env->segs[R_GS]); 2588 set_seg(&sregs.ss, &env->segs[R_SS]); 2589 } 2590 2591 set_seg(&sregs.tr, &env->tr); 2592 set_seg(&sregs.ldt, &env->ldt); 2593 2594 sregs.idt.limit = env->idt.limit; 2595 sregs.idt.base = env->idt.base; 2596 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); 2597 sregs.gdt.limit = env->gdt.limit; 2598 sregs.gdt.base = env->gdt.base; 2599 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); 2600 2601 sregs.cr0 = env->cr[0]; 2602 sregs.cr2 = env->cr[2]; 2603 sregs.cr3 = env->cr[3]; 2604 sregs.cr4 = env->cr[4]; 2605 2606 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); 2607 sregs.apic_base = cpu_get_apic_base(cpu->apic_state); 2608 2609 sregs.efer = env->efer; 2610 2611 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 2612 } 2613 2614 static void kvm_msr_buf_reset(X86CPU *cpu) 2615 { 2616 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE); 2617 } 2618 2619 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value) 2620 { 2621 struct kvm_msrs *msrs = cpu->kvm_msr_buf; 2622 void *limit = ((void *)msrs) + MSR_BUF_SIZE; 2623 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs]; 2624 2625 assert((void *)(entry + 1) <= limit); 2626 2627 entry->index = index; 2628 entry->reserved = 0; 2629 entry->data = value; 2630 msrs->nmsrs++; 2631 } 2632 2633 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value) 2634 { 2635 kvm_msr_buf_reset(cpu); 2636 kvm_msr_entry_add(cpu, index, value); 2637 2638 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); 2639 } 2640 2641 void kvm_put_apicbase(X86CPU *cpu, uint64_t value) 2642 { 2643 int ret; 2644 2645 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value); 2646 assert(ret == 1); 2647 } 2648 2649 static int kvm_put_tscdeadline_msr(X86CPU *cpu) 2650 { 2651 CPUX86State *env = &cpu->env; 2652 int ret; 2653 2654 if (!has_msr_tsc_deadline) { 2655 return 0; 2656 } 2657 2658 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline); 2659 if (ret < 0) { 2660 return ret; 2661 } 2662 2663 assert(ret == 1); 2664 return 0; 2665 } 2666 2667 /* 2668 * Provide a separate write service for the feature control MSR in order to 2669 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done 2670 * before writing any other state because forcibly leaving nested mode 2671 * invalidates the VCPU state. 2672 */ 2673 static int kvm_put_msr_feature_control(X86CPU *cpu) 2674 { 2675 int ret; 2676 2677 if (!has_msr_feature_control) { 2678 return 0; 2679 } 2680 2681 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL, 2682 cpu->env.msr_ia32_feature_control); 2683 if (ret < 0) { 2684 return ret; 2685 } 2686 2687 assert(ret == 1); 2688 return 0; 2689 } 2690 2691 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features) 2692 { 2693 uint32_t default1, can_be_one, can_be_zero; 2694 uint32_t must_be_one; 2695 2696 switch (index) { 2697 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 2698 default1 = 0x00000016; 2699 break; 2700 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 2701 default1 = 0x0401e172; 2702 break; 2703 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 2704 default1 = 0x000011ff; 2705 break; 2706 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 2707 default1 = 0x00036dff; 2708 break; 2709 case MSR_IA32_VMX_PROCBASED_CTLS2: 2710 default1 = 0; 2711 break; 2712 default: 2713 abort(); 2714 } 2715 2716 /* If a feature bit is set, the control can be either set or clear. 2717 * Otherwise the value is limited to either 0 or 1 by default1. 2718 */ 2719 can_be_one = features | default1; 2720 can_be_zero = features | ~default1; 2721 must_be_one = ~can_be_zero; 2722 2723 /* 2724 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one). 2725 * Bit 32:63 -> 1 if the control bit can be one. 2726 */ 2727 return must_be_one | (((uint64_t)can_be_one) << 32); 2728 } 2729 2730 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) 2731 { 2732 uint64_t kvm_vmx_basic = 2733 kvm_arch_get_supported_msr_feature(kvm_state, 2734 MSR_IA32_VMX_BASIC); 2735 2736 if (!kvm_vmx_basic) { 2737 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0), 2738 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail. 2739 */ 2740 return; 2741 } 2742 2743 uint64_t kvm_vmx_misc = 2744 kvm_arch_get_supported_msr_feature(kvm_state, 2745 MSR_IA32_VMX_MISC); 2746 uint64_t kvm_vmx_ept_vpid = 2747 kvm_arch_get_supported_msr_feature(kvm_state, 2748 MSR_IA32_VMX_EPT_VPID_CAP); 2749 2750 /* 2751 * If the guest is 64-bit, a value of 1 is allowed for the host address 2752 * space size vmexit control. 2753 */ 2754 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM 2755 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0; 2756 2757 /* 2758 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should 2759 * not change them for backwards compatibility. 2760 */ 2761 uint64_t fixed_vmx_basic = kvm_vmx_basic & 2762 (MSR_VMX_BASIC_VMCS_REVISION_MASK | 2763 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK | 2764 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK); 2765 2766 /* 2767 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can 2768 * change in the future but are always zero for now, clear them to be 2769 * future proof. Bits 32-63 in theory could change, though KVM does 2770 * not support dual-monitor treatment and probably never will; mask 2771 * them out as well. 2772 */ 2773 uint64_t fixed_vmx_misc = kvm_vmx_misc & 2774 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK | 2775 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK); 2776 2777 /* 2778 * EPT memory types should not change either, so we do not bother 2779 * adding features for them. 2780 */ 2781 uint64_t fixed_vmx_ept_mask = 2782 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ? 2783 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0); 2784 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask; 2785 2786 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 2787 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 2788 f[FEAT_VMX_PROCBASED_CTLS])); 2789 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS, 2790 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS, 2791 f[FEAT_VMX_PINBASED_CTLS])); 2792 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS, 2793 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS, 2794 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit); 2795 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS, 2796 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS, 2797 f[FEAT_VMX_ENTRY_CTLS])); 2798 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2, 2799 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2, 2800 f[FEAT_VMX_SECONDARY_CTLS])); 2801 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP, 2802 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid); 2803 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC, 2804 f[FEAT_VMX_BASIC] | fixed_vmx_basic); 2805 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC, 2806 f[FEAT_VMX_MISC] | fixed_vmx_misc); 2807 if (has_msr_vmx_vmfunc) { 2808 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]); 2809 } 2810 2811 /* 2812 * Just to be safe, write these with constant values. The CRn_FIXED1 2813 * MSRs are generated by KVM based on the vCPU's CPUID. 2814 */ 2815 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0, 2816 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK); 2817 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0, 2818 CR4_VMXE_MASK); 2819 2820 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) { 2821 /* TSC multiplier (0x2032). */ 2822 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32); 2823 } else { 2824 /* Preemption timer (0x482E). */ 2825 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E); 2826 } 2827 } 2828 2829 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f) 2830 { 2831 uint64_t kvm_perf_cap = 2832 kvm_arch_get_supported_msr_feature(kvm_state, 2833 MSR_IA32_PERF_CAPABILITIES); 2834 2835 if (kvm_perf_cap) { 2836 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, 2837 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]); 2838 } 2839 } 2840 2841 static int kvm_buf_set_msrs(X86CPU *cpu) 2842 { 2843 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); 2844 if (ret < 0) { 2845 return ret; 2846 } 2847 2848 if (ret < cpu->kvm_msr_buf->nmsrs) { 2849 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; 2850 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64, 2851 (uint32_t)e->index, (uint64_t)e->data); 2852 } 2853 2854 assert(ret == cpu->kvm_msr_buf->nmsrs); 2855 return 0; 2856 } 2857 2858 static void kvm_init_msrs(X86CPU *cpu) 2859 { 2860 CPUX86State *env = &cpu->env; 2861 2862 kvm_msr_buf_reset(cpu); 2863 if (has_msr_arch_capabs) { 2864 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, 2865 env->features[FEAT_ARCH_CAPABILITIES]); 2866 } 2867 2868 if (has_msr_core_capabs) { 2869 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, 2870 env->features[FEAT_CORE_CAPABILITY]); 2871 } 2872 2873 if (has_msr_perf_capabs && cpu->enable_pmu) { 2874 kvm_msr_entry_add_perf(cpu, env->features); 2875 } 2876 2877 if (has_msr_ucode_rev) { 2878 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); 2879 } 2880 2881 /* 2882 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but 2883 * all kernels with MSR features should have them. 2884 */ 2885 if (kvm_feature_msrs && cpu_has_vmx(env)) { 2886 kvm_msr_entry_add_vmx(cpu, env->features); 2887 } 2888 2889 assert(kvm_buf_set_msrs(cpu) == 0); 2890 } 2891 2892 static int kvm_put_msrs(X86CPU *cpu, int level) 2893 { 2894 CPUX86State *env = &cpu->env; 2895 int i; 2896 2897 kvm_msr_buf_reset(cpu); 2898 2899 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs); 2900 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); 2901 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); 2902 kvm_msr_entry_add(cpu, MSR_PAT, env->pat); 2903 if (has_msr_star) { 2904 kvm_msr_entry_add(cpu, MSR_STAR, env->star); 2905 } 2906 if (has_msr_hsave_pa) { 2907 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave); 2908 } 2909 if (has_msr_tsc_aux) { 2910 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux); 2911 } 2912 if (has_msr_tsc_adjust) { 2913 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust); 2914 } 2915 if (has_msr_misc_enable) { 2916 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 2917 env->msr_ia32_misc_enable); 2918 } 2919 if (has_msr_smbase) { 2920 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase); 2921 } 2922 if (has_msr_smi_count) { 2923 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count); 2924 } 2925 if (has_msr_pkrs) { 2926 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs); 2927 } 2928 if (has_msr_bndcfgs) { 2929 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs); 2930 } 2931 if (has_msr_xss) { 2932 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); 2933 } 2934 if (has_msr_umwait) { 2935 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait); 2936 } 2937 if (has_msr_spec_ctrl) { 2938 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); 2939 } 2940 if (has_msr_tsx_ctrl) { 2941 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl); 2942 } 2943 if (has_msr_virt_ssbd) { 2944 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); 2945 } 2946 2947 #ifdef TARGET_X86_64 2948 if (lm_capable_kernel) { 2949 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); 2950 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase); 2951 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask); 2952 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); 2953 } 2954 #endif 2955 2956 /* 2957 * The following MSRs have side effects on the guest or are too heavy 2958 * for normal writeback. Limit them to reset or full state updates. 2959 */ 2960 if (level >= KVM_PUT_RESET_STATE) { 2961 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc); 2962 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr); 2963 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr); 2964 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { 2965 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr); 2966 } 2967 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) { 2968 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr); 2969 } 2970 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) { 2971 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr); 2972 } 2973 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { 2974 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr); 2975 } 2976 2977 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { 2978 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr); 2979 } 2980 2981 if (has_architectural_pmu_version > 0) { 2982 if (has_architectural_pmu_version > 1) { 2983 /* Stop the counter. */ 2984 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); 2985 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); 2986 } 2987 2988 /* Set the counter values. */ 2989 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { 2990 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 2991 env->msr_fixed_counters[i]); 2992 } 2993 for (i = 0; i < num_architectural_pmu_gp_counters; i++) { 2994 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 2995 env->msr_gp_counters[i]); 2996 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 2997 env->msr_gp_evtsel[i]); 2998 } 2999 if (has_architectural_pmu_version > 1) { 3000 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 3001 env->msr_global_status); 3002 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 3003 env->msr_global_ovf_ctrl); 3004 3005 /* Now start the PMU. */ 3006 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 3007 env->msr_fixed_ctr_ctrl); 3008 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 3009 env->msr_global_ctrl); 3010 } 3011 } 3012 /* 3013 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add, 3014 * only sync them to KVM on the first cpu 3015 */ 3016 if (current_cpu == first_cpu) { 3017 if (has_msr_hv_hypercall) { 3018 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 3019 env->msr_hv_guest_os_id); 3020 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 3021 env->msr_hv_hypercall); 3022 } 3023 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { 3024 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 3025 env->msr_hv_tsc); 3026 } 3027 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { 3028 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 3029 env->msr_hv_reenlightenment_control); 3030 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 3031 env->msr_hv_tsc_emulation_control); 3032 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 3033 env->msr_hv_tsc_emulation_status); 3034 } 3035 } 3036 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { 3037 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 3038 env->msr_hv_vapic); 3039 } 3040 if (has_msr_hv_crash) { 3041 int j; 3042 3043 for (j = 0; j < HV_CRASH_PARAMS; j++) 3044 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 3045 env->msr_hv_crash_params[j]); 3046 3047 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY); 3048 } 3049 if (has_msr_hv_runtime) { 3050 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime); 3051 } 3052 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) 3053 && hv_vpindex_settable) { 3054 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX, 3055 hyperv_vp_index(CPU(cpu))); 3056 } 3057 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 3058 int j; 3059 3060 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION); 3061 3062 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 3063 env->msr_hv_synic_control); 3064 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 3065 env->msr_hv_synic_evt_page); 3066 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 3067 env->msr_hv_synic_msg_page); 3068 3069 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) { 3070 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j, 3071 env->msr_hv_synic_sint[j]); 3072 } 3073 } 3074 if (has_msr_hv_stimer) { 3075 int j; 3076 3077 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) { 3078 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2, 3079 env->msr_hv_stimer_config[j]); 3080 } 3081 3082 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) { 3083 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2, 3084 env->msr_hv_stimer_count[j]); 3085 } 3086 } 3087 if (env->features[FEAT_1_EDX] & CPUID_MTRR) { 3088 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits); 3089 3090 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype); 3091 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]); 3092 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]); 3093 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]); 3094 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]); 3095 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]); 3096 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]); 3097 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]); 3098 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]); 3099 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]); 3100 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]); 3101 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]); 3102 for (i = 0; i < MSR_MTRRcap_VCNT; i++) { 3103 /* The CPU GPs if we write to a bit above the physical limit of 3104 * the host CPU (and KVM emulates that) 3105 */ 3106 uint64_t mask = env->mtrr_var[i].mask; 3107 mask &= phys_mask; 3108 3109 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 3110 env->mtrr_var[i].base); 3111 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask); 3112 } 3113 } 3114 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { 3115 int addr_num = kvm_arch_get_supported_cpuid(kvm_state, 3116 0x14, 1, R_EAX) & 0x7; 3117 3118 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 3119 env->msr_rtit_ctrl); 3120 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 3121 env->msr_rtit_status); 3122 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 3123 env->msr_rtit_output_base); 3124 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 3125 env->msr_rtit_output_mask); 3126 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 3127 env->msr_rtit_cr3_match); 3128 for (i = 0; i < addr_num; i++) { 3129 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 3130 env->msr_rtit_addrs[i]); 3131 } 3132 } 3133 3134 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) { 3135 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 3136 env->msr_ia32_sgxlepubkeyhash[0]); 3137 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 3138 env->msr_ia32_sgxlepubkeyhash[1]); 3139 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 3140 env->msr_ia32_sgxlepubkeyhash[2]); 3141 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 3142 env->msr_ia32_sgxlepubkeyhash[3]); 3143 } 3144 3145 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see 3146 * kvm_put_msr_feature_control. */ 3147 } 3148 3149 if (env->mcg_cap) { 3150 int i; 3151 3152 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status); 3153 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl); 3154 if (has_msr_mcg_ext_ctl) { 3155 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl); 3156 } 3157 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { 3158 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]); 3159 } 3160 } 3161 3162 return kvm_buf_set_msrs(cpu); 3163 } 3164 3165 3166 static int kvm_get_fpu(X86CPU *cpu) 3167 { 3168 CPUX86State *env = &cpu->env; 3169 struct kvm_fpu fpu; 3170 int i, ret; 3171 3172 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu); 3173 if (ret < 0) { 3174 return ret; 3175 } 3176 3177 env->fpstt = (fpu.fsw >> 11) & 7; 3178 env->fpus = fpu.fsw; 3179 env->fpuc = fpu.fcw; 3180 env->fpop = fpu.last_opcode; 3181 env->fpip = fpu.last_ip; 3182 env->fpdp = fpu.last_dp; 3183 for (i = 0; i < 8; ++i) { 3184 env->fptags[i] = !((fpu.ftwx >> i) & 1); 3185 } 3186 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); 3187 for (i = 0; i < CPU_NB_REGS; i++) { 3188 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]); 3189 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]); 3190 } 3191 env->mxcsr = fpu.mxcsr; 3192 3193 return 0; 3194 } 3195 3196 static int kvm_get_xsave(X86CPU *cpu) 3197 { 3198 CPUX86State *env = &cpu->env; 3199 void *xsave = env->xsave_buf; 3200 int ret; 3201 3202 if (!has_xsave) { 3203 return kvm_get_fpu(cpu); 3204 } 3205 3206 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); 3207 if (ret < 0) { 3208 return ret; 3209 } 3210 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len); 3211 3212 return 0; 3213 } 3214 3215 static int kvm_get_xcrs(X86CPU *cpu) 3216 { 3217 CPUX86State *env = &cpu->env; 3218 int i, ret; 3219 struct kvm_xcrs xcrs; 3220 3221 if (!has_xcrs) { 3222 return 0; 3223 } 3224 3225 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); 3226 if (ret < 0) { 3227 return ret; 3228 } 3229 3230 for (i = 0; i < xcrs.nr_xcrs; i++) { 3231 /* Only support xcr0 now */ 3232 if (xcrs.xcrs[i].xcr == 0) { 3233 env->xcr0 = xcrs.xcrs[i].value; 3234 break; 3235 } 3236 } 3237 return 0; 3238 } 3239 3240 static int kvm_get_sregs(X86CPU *cpu) 3241 { 3242 CPUX86State *env = &cpu->env; 3243 struct kvm_sregs sregs; 3244 int bit, i, ret; 3245 3246 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 3247 if (ret < 0) { 3248 return ret; 3249 } 3250 3251 /* There can only be one pending IRQ set in the bitmap at a time, so try 3252 to find it and save its number instead (-1 for none). */ 3253 env->interrupt_injected = -1; 3254 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { 3255 if (sregs.interrupt_bitmap[i]) { 3256 bit = ctz64(sregs.interrupt_bitmap[i]); 3257 env->interrupt_injected = i * 64 + bit; 3258 break; 3259 } 3260 } 3261 3262 get_seg(&env->segs[R_CS], &sregs.cs); 3263 get_seg(&env->segs[R_DS], &sregs.ds); 3264 get_seg(&env->segs[R_ES], &sregs.es); 3265 get_seg(&env->segs[R_FS], &sregs.fs); 3266 get_seg(&env->segs[R_GS], &sregs.gs); 3267 get_seg(&env->segs[R_SS], &sregs.ss); 3268 3269 get_seg(&env->tr, &sregs.tr); 3270 get_seg(&env->ldt, &sregs.ldt); 3271 3272 env->idt.limit = sregs.idt.limit; 3273 env->idt.base = sregs.idt.base; 3274 env->gdt.limit = sregs.gdt.limit; 3275 env->gdt.base = sregs.gdt.base; 3276 3277 env->cr[0] = sregs.cr0; 3278 env->cr[2] = sregs.cr2; 3279 env->cr[3] = sregs.cr3; 3280 env->cr[4] = sregs.cr4; 3281 3282 env->efer = sregs.efer; 3283 3284 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ 3285 x86_update_hflags(env); 3286 3287 return 0; 3288 } 3289 3290 static int kvm_get_msrs(X86CPU *cpu) 3291 { 3292 CPUX86State *env = &cpu->env; 3293 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries; 3294 int ret, i; 3295 uint64_t mtrr_top_bits; 3296 3297 kvm_msr_buf_reset(cpu); 3298 3299 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0); 3300 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0); 3301 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0); 3302 kvm_msr_entry_add(cpu, MSR_PAT, 0); 3303 if (has_msr_star) { 3304 kvm_msr_entry_add(cpu, MSR_STAR, 0); 3305 } 3306 if (has_msr_hsave_pa) { 3307 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0); 3308 } 3309 if (has_msr_tsc_aux) { 3310 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0); 3311 } 3312 if (has_msr_tsc_adjust) { 3313 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0); 3314 } 3315 if (has_msr_tsc_deadline) { 3316 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0); 3317 } 3318 if (has_msr_misc_enable) { 3319 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0); 3320 } 3321 if (has_msr_smbase) { 3322 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0); 3323 } 3324 if (has_msr_smi_count) { 3325 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0); 3326 } 3327 if (has_msr_feature_control) { 3328 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0); 3329 } 3330 if (has_msr_pkrs) { 3331 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0); 3332 } 3333 if (has_msr_bndcfgs) { 3334 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0); 3335 } 3336 if (has_msr_xss) { 3337 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); 3338 } 3339 if (has_msr_umwait) { 3340 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0); 3341 } 3342 if (has_msr_spec_ctrl) { 3343 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); 3344 } 3345 if (has_msr_tsx_ctrl) { 3346 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0); 3347 } 3348 if (has_msr_virt_ssbd) { 3349 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); 3350 } 3351 if (!env->tsc_valid) { 3352 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); 3353 env->tsc_valid = !runstate_is_running(); 3354 } 3355 3356 #ifdef TARGET_X86_64 3357 if (lm_capable_kernel) { 3358 kvm_msr_entry_add(cpu, MSR_CSTAR, 0); 3359 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0); 3360 kvm_msr_entry_add(cpu, MSR_FMASK, 0); 3361 kvm_msr_entry_add(cpu, MSR_LSTAR, 0); 3362 } 3363 #endif 3364 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0); 3365 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0); 3366 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { 3367 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0); 3368 } 3369 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) { 3370 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0); 3371 } 3372 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) { 3373 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0); 3374 } 3375 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { 3376 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0); 3377 } 3378 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { 3379 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); 3380 } 3381 if (has_architectural_pmu_version > 0) { 3382 if (has_architectural_pmu_version > 1) { 3383 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); 3384 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); 3385 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); 3386 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); 3387 } 3388 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { 3389 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); 3390 } 3391 for (i = 0; i < num_architectural_pmu_gp_counters; i++) { 3392 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); 3393 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); 3394 } 3395 } 3396 3397 if (env->mcg_cap) { 3398 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0); 3399 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0); 3400 if (has_msr_mcg_ext_ctl) { 3401 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0); 3402 } 3403 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { 3404 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0); 3405 } 3406 } 3407 3408 if (has_msr_hv_hypercall) { 3409 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0); 3410 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0); 3411 } 3412 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { 3413 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0); 3414 } 3415 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { 3416 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0); 3417 } 3418 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { 3419 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0); 3420 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0); 3421 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0); 3422 } 3423 if (has_msr_hv_crash) { 3424 int j; 3425 3426 for (j = 0; j < HV_CRASH_PARAMS; j++) { 3427 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0); 3428 } 3429 } 3430 if (has_msr_hv_runtime) { 3431 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0); 3432 } 3433 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 3434 uint32_t msr; 3435 3436 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0); 3437 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0); 3438 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0); 3439 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) { 3440 kvm_msr_entry_add(cpu, msr, 0); 3441 } 3442 } 3443 if (has_msr_hv_stimer) { 3444 uint32_t msr; 3445 3446 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT; 3447 msr++) { 3448 kvm_msr_entry_add(cpu, msr, 0); 3449 } 3450 } 3451 if (env->features[FEAT_1_EDX] & CPUID_MTRR) { 3452 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0); 3453 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0); 3454 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0); 3455 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0); 3456 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0); 3457 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0); 3458 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0); 3459 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0); 3460 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0); 3461 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0); 3462 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0); 3463 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0); 3464 for (i = 0; i < MSR_MTRRcap_VCNT; i++) { 3465 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0); 3466 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0); 3467 } 3468 } 3469 3470 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { 3471 int addr_num = 3472 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7; 3473 3474 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0); 3475 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0); 3476 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0); 3477 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0); 3478 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0); 3479 for (i = 0; i < addr_num; i++) { 3480 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0); 3481 } 3482 } 3483 3484 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) { 3485 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0); 3486 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0); 3487 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0); 3488 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0); 3489 } 3490 3491 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); 3492 if (ret < 0) { 3493 return ret; 3494 } 3495 3496 if (ret < cpu->kvm_msr_buf->nmsrs) { 3497 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; 3498 error_report("error: failed to get MSR 0x%" PRIx32, 3499 (uint32_t)e->index); 3500 } 3501 3502 assert(ret == cpu->kvm_msr_buf->nmsrs); 3503 /* 3504 * MTRR masks: Each mask consists of 5 parts 3505 * a 10..0: must be zero 3506 * b 11 : valid bit 3507 * c n-1.12: actual mask bits 3508 * d 51..n: reserved must be zero 3509 * e 63.52: reserved must be zero 3510 * 3511 * 'n' is the number of physical bits supported by the CPU and is 3512 * apparently always <= 52. We know our 'n' but don't know what 3513 * the destinations 'n' is; it might be smaller, in which case 3514 * it masks (c) on loading. It might be larger, in which case 3515 * we fill 'd' so that d..c is consistent irrespetive of the 'n' 3516 * we're migrating to. 3517 */ 3518 3519 if (cpu->fill_mtrr_mask) { 3520 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); 3521 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); 3522 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); 3523 } else { 3524 mtrr_top_bits = 0; 3525 } 3526 3527 for (i = 0; i < ret; i++) { 3528 uint32_t index = msrs[i].index; 3529 switch (index) { 3530 case MSR_IA32_SYSENTER_CS: 3531 env->sysenter_cs = msrs[i].data; 3532 break; 3533 case MSR_IA32_SYSENTER_ESP: 3534 env->sysenter_esp = msrs[i].data; 3535 break; 3536 case MSR_IA32_SYSENTER_EIP: 3537 env->sysenter_eip = msrs[i].data; 3538 break; 3539 case MSR_PAT: 3540 env->pat = msrs[i].data; 3541 break; 3542 case MSR_STAR: 3543 env->star = msrs[i].data; 3544 break; 3545 #ifdef TARGET_X86_64 3546 case MSR_CSTAR: 3547 env->cstar = msrs[i].data; 3548 break; 3549 case MSR_KERNELGSBASE: 3550 env->kernelgsbase = msrs[i].data; 3551 break; 3552 case MSR_FMASK: 3553 env->fmask = msrs[i].data; 3554 break; 3555 case MSR_LSTAR: 3556 env->lstar = msrs[i].data; 3557 break; 3558 #endif 3559 case MSR_IA32_TSC: 3560 env->tsc = msrs[i].data; 3561 break; 3562 case MSR_TSC_AUX: 3563 env->tsc_aux = msrs[i].data; 3564 break; 3565 case MSR_TSC_ADJUST: 3566 env->tsc_adjust = msrs[i].data; 3567 break; 3568 case MSR_IA32_TSCDEADLINE: 3569 env->tsc_deadline = msrs[i].data; 3570 break; 3571 case MSR_VM_HSAVE_PA: 3572 env->vm_hsave = msrs[i].data; 3573 break; 3574 case MSR_KVM_SYSTEM_TIME: 3575 env->system_time_msr = msrs[i].data; 3576 break; 3577 case MSR_KVM_WALL_CLOCK: 3578 env->wall_clock_msr = msrs[i].data; 3579 break; 3580 case MSR_MCG_STATUS: 3581 env->mcg_status = msrs[i].data; 3582 break; 3583 case MSR_MCG_CTL: 3584 env->mcg_ctl = msrs[i].data; 3585 break; 3586 case MSR_MCG_EXT_CTL: 3587 env->mcg_ext_ctl = msrs[i].data; 3588 break; 3589 case MSR_IA32_MISC_ENABLE: 3590 env->msr_ia32_misc_enable = msrs[i].data; 3591 break; 3592 case MSR_IA32_SMBASE: 3593 env->smbase = msrs[i].data; 3594 break; 3595 case MSR_SMI_COUNT: 3596 env->msr_smi_count = msrs[i].data; 3597 break; 3598 case MSR_IA32_FEATURE_CONTROL: 3599 env->msr_ia32_feature_control = msrs[i].data; 3600 break; 3601 case MSR_IA32_BNDCFGS: 3602 env->msr_bndcfgs = msrs[i].data; 3603 break; 3604 case MSR_IA32_XSS: 3605 env->xss = msrs[i].data; 3606 break; 3607 case MSR_IA32_UMWAIT_CONTROL: 3608 env->umwait = msrs[i].data; 3609 break; 3610 case MSR_IA32_PKRS: 3611 env->pkrs = msrs[i].data; 3612 break; 3613 default: 3614 if (msrs[i].index >= MSR_MC0_CTL && 3615 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { 3616 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; 3617 } 3618 break; 3619 case MSR_KVM_ASYNC_PF_EN: 3620 env->async_pf_en_msr = msrs[i].data; 3621 break; 3622 case MSR_KVM_ASYNC_PF_INT: 3623 env->async_pf_int_msr = msrs[i].data; 3624 break; 3625 case MSR_KVM_PV_EOI_EN: 3626 env->pv_eoi_en_msr = msrs[i].data; 3627 break; 3628 case MSR_KVM_STEAL_TIME: 3629 env->steal_time_msr = msrs[i].data; 3630 break; 3631 case MSR_KVM_POLL_CONTROL: { 3632 env->poll_control_msr = msrs[i].data; 3633 break; 3634 } 3635 case MSR_CORE_PERF_FIXED_CTR_CTRL: 3636 env->msr_fixed_ctr_ctrl = msrs[i].data; 3637 break; 3638 case MSR_CORE_PERF_GLOBAL_CTRL: 3639 env->msr_global_ctrl = msrs[i].data; 3640 break; 3641 case MSR_CORE_PERF_GLOBAL_STATUS: 3642 env->msr_global_status = msrs[i].data; 3643 break; 3644 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 3645 env->msr_global_ovf_ctrl = msrs[i].data; 3646 break; 3647 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1: 3648 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data; 3649 break; 3650 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: 3651 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; 3652 break; 3653 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: 3654 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; 3655 break; 3656 case HV_X64_MSR_HYPERCALL: 3657 env->msr_hv_hypercall = msrs[i].data; 3658 break; 3659 case HV_X64_MSR_GUEST_OS_ID: 3660 env->msr_hv_guest_os_id = msrs[i].data; 3661 break; 3662 case HV_X64_MSR_APIC_ASSIST_PAGE: 3663 env->msr_hv_vapic = msrs[i].data; 3664 break; 3665 case HV_X64_MSR_REFERENCE_TSC: 3666 env->msr_hv_tsc = msrs[i].data; 3667 break; 3668 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3669 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data; 3670 break; 3671 case HV_X64_MSR_VP_RUNTIME: 3672 env->msr_hv_runtime = msrs[i].data; 3673 break; 3674 case HV_X64_MSR_SCONTROL: 3675 env->msr_hv_synic_control = msrs[i].data; 3676 break; 3677 case HV_X64_MSR_SIEFP: 3678 env->msr_hv_synic_evt_page = msrs[i].data; 3679 break; 3680 case HV_X64_MSR_SIMP: 3681 env->msr_hv_synic_msg_page = msrs[i].data; 3682 break; 3683 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: 3684 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data; 3685 break; 3686 case HV_X64_MSR_STIMER0_CONFIG: 3687 case HV_X64_MSR_STIMER1_CONFIG: 3688 case HV_X64_MSR_STIMER2_CONFIG: 3689 case HV_X64_MSR_STIMER3_CONFIG: 3690 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] = 3691 msrs[i].data; 3692 break; 3693 case HV_X64_MSR_STIMER0_COUNT: 3694 case HV_X64_MSR_STIMER1_COUNT: 3695 case HV_X64_MSR_STIMER2_COUNT: 3696 case HV_X64_MSR_STIMER3_COUNT: 3697 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] = 3698 msrs[i].data; 3699 break; 3700 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3701 env->msr_hv_reenlightenment_control = msrs[i].data; 3702 break; 3703 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3704 env->msr_hv_tsc_emulation_control = msrs[i].data; 3705 break; 3706 case HV_X64_MSR_TSC_EMULATION_STATUS: 3707 env->msr_hv_tsc_emulation_status = msrs[i].data; 3708 break; 3709 case MSR_MTRRdefType: 3710 env->mtrr_deftype = msrs[i].data; 3711 break; 3712 case MSR_MTRRfix64K_00000: 3713 env->mtrr_fixed[0] = msrs[i].data; 3714 break; 3715 case MSR_MTRRfix16K_80000: 3716 env->mtrr_fixed[1] = msrs[i].data; 3717 break; 3718 case MSR_MTRRfix16K_A0000: 3719 env->mtrr_fixed[2] = msrs[i].data; 3720 break; 3721 case MSR_MTRRfix4K_C0000: 3722 env->mtrr_fixed[3] = msrs[i].data; 3723 break; 3724 case MSR_MTRRfix4K_C8000: 3725 env->mtrr_fixed[4] = msrs[i].data; 3726 break; 3727 case MSR_MTRRfix4K_D0000: 3728 env->mtrr_fixed[5] = msrs[i].data; 3729 break; 3730 case MSR_MTRRfix4K_D8000: 3731 env->mtrr_fixed[6] = msrs[i].data; 3732 break; 3733 case MSR_MTRRfix4K_E0000: 3734 env->mtrr_fixed[7] = msrs[i].data; 3735 break; 3736 case MSR_MTRRfix4K_E8000: 3737 env->mtrr_fixed[8] = msrs[i].data; 3738 break; 3739 case MSR_MTRRfix4K_F0000: 3740 env->mtrr_fixed[9] = msrs[i].data; 3741 break; 3742 case MSR_MTRRfix4K_F8000: 3743 env->mtrr_fixed[10] = msrs[i].data; 3744 break; 3745 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): 3746 if (index & 1) { 3747 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | 3748 mtrr_top_bits; 3749 } else { 3750 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; 3751 } 3752 break; 3753 case MSR_IA32_SPEC_CTRL: 3754 env->spec_ctrl = msrs[i].data; 3755 break; 3756 case MSR_IA32_TSX_CTRL: 3757 env->tsx_ctrl = msrs[i].data; 3758 break; 3759 case MSR_VIRT_SSBD: 3760 env->virt_ssbd = msrs[i].data; 3761 break; 3762 case MSR_IA32_RTIT_CTL: 3763 env->msr_rtit_ctrl = msrs[i].data; 3764 break; 3765 case MSR_IA32_RTIT_STATUS: 3766 env->msr_rtit_status = msrs[i].data; 3767 break; 3768 case MSR_IA32_RTIT_OUTPUT_BASE: 3769 env->msr_rtit_output_base = msrs[i].data; 3770 break; 3771 case MSR_IA32_RTIT_OUTPUT_MASK: 3772 env->msr_rtit_output_mask = msrs[i].data; 3773 break; 3774 case MSR_IA32_RTIT_CR3_MATCH: 3775 env->msr_rtit_cr3_match = msrs[i].data; 3776 break; 3777 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 3778 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data; 3779 break; 3780 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3: 3781 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] = 3782 msrs[i].data; 3783 break; 3784 } 3785 } 3786 3787 return 0; 3788 } 3789 3790 static int kvm_put_mp_state(X86CPU *cpu) 3791 { 3792 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; 3793 3794 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 3795 } 3796 3797 static int kvm_get_mp_state(X86CPU *cpu) 3798 { 3799 CPUState *cs = CPU(cpu); 3800 CPUX86State *env = &cpu->env; 3801 struct kvm_mp_state mp_state; 3802 int ret; 3803 3804 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); 3805 if (ret < 0) { 3806 return ret; 3807 } 3808 env->mp_state = mp_state.mp_state; 3809 if (kvm_irqchip_in_kernel()) { 3810 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); 3811 } 3812 return 0; 3813 } 3814 3815 static int kvm_get_apic(X86CPU *cpu) 3816 { 3817 DeviceState *apic = cpu->apic_state; 3818 struct kvm_lapic_state kapic; 3819 int ret; 3820 3821 if (apic && kvm_irqchip_in_kernel()) { 3822 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); 3823 if (ret < 0) { 3824 return ret; 3825 } 3826 3827 kvm_get_apic_state(apic, &kapic); 3828 } 3829 return 0; 3830 } 3831 3832 static int kvm_put_vcpu_events(X86CPU *cpu, int level) 3833 { 3834 CPUState *cs = CPU(cpu); 3835 CPUX86State *env = &cpu->env; 3836 struct kvm_vcpu_events events = {}; 3837 3838 if (!kvm_has_vcpu_events()) { 3839 return 0; 3840 } 3841 3842 events.flags = 0; 3843 3844 if (has_exception_payload) { 3845 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 3846 events.exception.pending = env->exception_pending; 3847 events.exception_has_payload = env->exception_has_payload; 3848 events.exception_payload = env->exception_payload; 3849 } 3850 events.exception.nr = env->exception_nr; 3851 events.exception.injected = env->exception_injected; 3852 events.exception.has_error_code = env->has_error_code; 3853 events.exception.error_code = env->error_code; 3854 3855 events.interrupt.injected = (env->interrupt_injected >= 0); 3856 events.interrupt.nr = env->interrupt_injected; 3857 events.interrupt.soft = env->soft_interrupt; 3858 3859 events.nmi.injected = env->nmi_injected; 3860 events.nmi.pending = env->nmi_pending; 3861 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); 3862 3863 events.sipi_vector = env->sipi_vector; 3864 3865 if (has_msr_smbase) { 3866 events.smi.smm = !!(env->hflags & HF_SMM_MASK); 3867 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK); 3868 if (kvm_irqchip_in_kernel()) { 3869 /* As soon as these are moved to the kernel, remove them 3870 * from cs->interrupt_request. 3871 */ 3872 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI; 3873 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT; 3874 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI); 3875 } else { 3876 /* Keep these in cs->interrupt_request. */ 3877 events.smi.pending = 0; 3878 events.smi.latched_init = 0; 3879 } 3880 /* Stop SMI delivery on old machine types to avoid a reboot 3881 * on an inward migration of an old VM. 3882 */ 3883 if (!cpu->kvm_no_smi_migration) { 3884 events.flags |= KVM_VCPUEVENT_VALID_SMM; 3885 } 3886 } 3887 3888 if (level >= KVM_PUT_RESET_STATE) { 3889 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING; 3890 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 3891 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR; 3892 } 3893 } 3894 3895 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); 3896 } 3897 3898 static int kvm_get_vcpu_events(X86CPU *cpu) 3899 { 3900 CPUX86State *env = &cpu->env; 3901 struct kvm_vcpu_events events; 3902 int ret; 3903 3904 if (!kvm_has_vcpu_events()) { 3905 return 0; 3906 } 3907 3908 memset(&events, 0, sizeof(events)); 3909 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); 3910 if (ret < 0) { 3911 return ret; 3912 } 3913 3914 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 3915 env->exception_pending = events.exception.pending; 3916 env->exception_has_payload = events.exception_has_payload; 3917 env->exception_payload = events.exception_payload; 3918 } else { 3919 env->exception_pending = 0; 3920 env->exception_has_payload = false; 3921 } 3922 env->exception_injected = events.exception.injected; 3923 env->exception_nr = 3924 (env->exception_pending || env->exception_injected) ? 3925 events.exception.nr : -1; 3926 env->has_error_code = events.exception.has_error_code; 3927 env->error_code = events.exception.error_code; 3928 3929 env->interrupt_injected = 3930 events.interrupt.injected ? events.interrupt.nr : -1; 3931 env->soft_interrupt = events.interrupt.soft; 3932 3933 env->nmi_injected = events.nmi.injected; 3934 env->nmi_pending = events.nmi.pending; 3935 if (events.nmi.masked) { 3936 env->hflags2 |= HF2_NMI_MASK; 3937 } else { 3938 env->hflags2 &= ~HF2_NMI_MASK; 3939 } 3940 3941 if (events.flags & KVM_VCPUEVENT_VALID_SMM) { 3942 if (events.smi.smm) { 3943 env->hflags |= HF_SMM_MASK; 3944 } else { 3945 env->hflags &= ~HF_SMM_MASK; 3946 } 3947 if (events.smi.pending) { 3948 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 3949 } else { 3950 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 3951 } 3952 if (events.smi.smm_inside_nmi) { 3953 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; 3954 } else { 3955 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK; 3956 } 3957 if (events.smi.latched_init) { 3958 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); 3959 } else { 3960 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); 3961 } 3962 } 3963 3964 env->sipi_vector = events.sipi_vector; 3965 3966 return 0; 3967 } 3968 3969 static int kvm_guest_debug_workarounds(X86CPU *cpu) 3970 { 3971 CPUState *cs = CPU(cpu); 3972 CPUX86State *env = &cpu->env; 3973 int ret = 0; 3974 unsigned long reinject_trap = 0; 3975 3976 if (!kvm_has_vcpu_events()) { 3977 if (env->exception_nr == EXCP01_DB) { 3978 reinject_trap = KVM_GUESTDBG_INJECT_DB; 3979 } else if (env->exception_injected == EXCP03_INT3) { 3980 reinject_trap = KVM_GUESTDBG_INJECT_BP; 3981 } 3982 kvm_reset_exception(env); 3983 } 3984 3985 /* 3986 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF 3987 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this 3988 * by updating the debug state once again if single-stepping is on. 3989 * Another reason to call kvm_update_guest_debug here is a pending debug 3990 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to 3991 * reinject them via SET_GUEST_DEBUG. 3992 */ 3993 if (reinject_trap || 3994 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) { 3995 ret = kvm_update_guest_debug(cs, reinject_trap); 3996 } 3997 return ret; 3998 } 3999 4000 static int kvm_put_debugregs(X86CPU *cpu) 4001 { 4002 CPUX86State *env = &cpu->env; 4003 struct kvm_debugregs dbgregs; 4004 int i; 4005 4006 if (!kvm_has_debugregs()) { 4007 return 0; 4008 } 4009 4010 memset(&dbgregs, 0, sizeof(dbgregs)); 4011 for (i = 0; i < 4; i++) { 4012 dbgregs.db[i] = env->dr[i]; 4013 } 4014 dbgregs.dr6 = env->dr[6]; 4015 dbgregs.dr7 = env->dr[7]; 4016 dbgregs.flags = 0; 4017 4018 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); 4019 } 4020 4021 static int kvm_get_debugregs(X86CPU *cpu) 4022 { 4023 CPUX86State *env = &cpu->env; 4024 struct kvm_debugregs dbgregs; 4025 int i, ret; 4026 4027 if (!kvm_has_debugregs()) { 4028 return 0; 4029 } 4030 4031 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); 4032 if (ret < 0) { 4033 return ret; 4034 } 4035 for (i = 0; i < 4; i++) { 4036 env->dr[i] = dbgregs.db[i]; 4037 } 4038 env->dr[4] = env->dr[6] = dbgregs.dr6; 4039 env->dr[5] = env->dr[7] = dbgregs.dr7; 4040 4041 return 0; 4042 } 4043 4044 static int kvm_put_nested_state(X86CPU *cpu) 4045 { 4046 CPUX86State *env = &cpu->env; 4047 int max_nested_state_len = kvm_max_nested_state_length(); 4048 4049 if (!env->nested_state) { 4050 return 0; 4051 } 4052 4053 /* 4054 * Copy flags that are affected by reset from env->hflags and env->hflags2. 4055 */ 4056 if (env->hflags & HF_GUEST_MASK) { 4057 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE; 4058 } else { 4059 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE; 4060 } 4061 4062 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */ 4063 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) { 4064 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET; 4065 } else { 4066 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET; 4067 } 4068 4069 assert(env->nested_state->size <= max_nested_state_len); 4070 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state); 4071 } 4072 4073 static int kvm_get_nested_state(X86CPU *cpu) 4074 { 4075 CPUX86State *env = &cpu->env; 4076 int max_nested_state_len = kvm_max_nested_state_length(); 4077 int ret; 4078 4079 if (!env->nested_state) { 4080 return 0; 4081 } 4082 4083 /* 4084 * It is possible that migration restored a smaller size into 4085 * nested_state->hdr.size than what our kernel support. 4086 * We preserve migration origin nested_state->hdr.size for 4087 * call to KVM_SET_NESTED_STATE but wish that our next call 4088 * to KVM_GET_NESTED_STATE will use max size our kernel support. 4089 */ 4090 env->nested_state->size = max_nested_state_len; 4091 4092 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state); 4093 if (ret < 0) { 4094 return ret; 4095 } 4096 4097 /* 4098 * Copy flags that are affected by reset to env->hflags and env->hflags2. 4099 */ 4100 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) { 4101 env->hflags |= HF_GUEST_MASK; 4102 } else { 4103 env->hflags &= ~HF_GUEST_MASK; 4104 } 4105 4106 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */ 4107 if (cpu_has_svm(env)) { 4108 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) { 4109 env->hflags2 |= HF2_GIF_MASK; 4110 } else { 4111 env->hflags2 &= ~HF2_GIF_MASK; 4112 } 4113 } 4114 4115 return ret; 4116 } 4117 4118 int kvm_arch_put_registers(CPUState *cpu, int level) 4119 { 4120 X86CPU *x86_cpu = X86_CPU(cpu); 4121 int ret; 4122 4123 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); 4124 4125 /* must be before kvm_put_nested_state so that EFER.SVME is set */ 4126 ret = kvm_put_sregs(x86_cpu); 4127 if (ret < 0) { 4128 return ret; 4129 } 4130 4131 if (level >= KVM_PUT_RESET_STATE) { 4132 ret = kvm_put_nested_state(x86_cpu); 4133 if (ret < 0) { 4134 return ret; 4135 } 4136 4137 ret = kvm_put_msr_feature_control(x86_cpu); 4138 if (ret < 0) { 4139 return ret; 4140 } 4141 } 4142 4143 if (level == KVM_PUT_FULL_STATE) { 4144 /* We don't check for kvm_arch_set_tsc_khz() errors here, 4145 * because TSC frequency mismatch shouldn't abort migration, 4146 * unless the user explicitly asked for a more strict TSC 4147 * setting (e.g. using an explicit "tsc-freq" option). 4148 */ 4149 kvm_arch_set_tsc_khz(cpu); 4150 } 4151 4152 ret = kvm_getput_regs(x86_cpu, 1); 4153 if (ret < 0) { 4154 return ret; 4155 } 4156 ret = kvm_put_xsave(x86_cpu); 4157 if (ret < 0) { 4158 return ret; 4159 } 4160 ret = kvm_put_xcrs(x86_cpu); 4161 if (ret < 0) { 4162 return ret; 4163 } 4164 /* must be before kvm_put_msrs */ 4165 ret = kvm_inject_mce_oldstyle(x86_cpu); 4166 if (ret < 0) { 4167 return ret; 4168 } 4169 ret = kvm_put_msrs(x86_cpu, level); 4170 if (ret < 0) { 4171 return ret; 4172 } 4173 ret = kvm_put_vcpu_events(x86_cpu, level); 4174 if (ret < 0) { 4175 return ret; 4176 } 4177 if (level >= KVM_PUT_RESET_STATE) { 4178 ret = kvm_put_mp_state(x86_cpu); 4179 if (ret < 0) { 4180 return ret; 4181 } 4182 } 4183 4184 ret = kvm_put_tscdeadline_msr(x86_cpu); 4185 if (ret < 0) { 4186 return ret; 4187 } 4188 ret = kvm_put_debugregs(x86_cpu); 4189 if (ret < 0) { 4190 return ret; 4191 } 4192 /* must be last */ 4193 ret = kvm_guest_debug_workarounds(x86_cpu); 4194 if (ret < 0) { 4195 return ret; 4196 } 4197 return 0; 4198 } 4199 4200 int kvm_arch_get_registers(CPUState *cs) 4201 { 4202 X86CPU *cpu = X86_CPU(cs); 4203 int ret; 4204 4205 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); 4206 4207 ret = kvm_get_vcpu_events(cpu); 4208 if (ret < 0) { 4209 goto out; 4210 } 4211 /* 4212 * KVM_GET_MPSTATE can modify CS and RIP, call it before 4213 * KVM_GET_REGS and KVM_GET_SREGS. 4214 */ 4215 ret = kvm_get_mp_state(cpu); 4216 if (ret < 0) { 4217 goto out; 4218 } 4219 ret = kvm_getput_regs(cpu, 0); 4220 if (ret < 0) { 4221 goto out; 4222 } 4223 ret = kvm_get_xsave(cpu); 4224 if (ret < 0) { 4225 goto out; 4226 } 4227 ret = kvm_get_xcrs(cpu); 4228 if (ret < 0) { 4229 goto out; 4230 } 4231 ret = kvm_get_sregs(cpu); 4232 if (ret < 0) { 4233 goto out; 4234 } 4235 ret = kvm_get_msrs(cpu); 4236 if (ret < 0) { 4237 goto out; 4238 } 4239 ret = kvm_get_apic(cpu); 4240 if (ret < 0) { 4241 goto out; 4242 } 4243 ret = kvm_get_debugregs(cpu); 4244 if (ret < 0) { 4245 goto out; 4246 } 4247 ret = kvm_get_nested_state(cpu); 4248 if (ret < 0) { 4249 goto out; 4250 } 4251 ret = 0; 4252 out: 4253 cpu_sync_bndcs_hflags(&cpu->env); 4254 return ret; 4255 } 4256 4257 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) 4258 { 4259 X86CPU *x86_cpu = X86_CPU(cpu); 4260 CPUX86State *env = &x86_cpu->env; 4261 int ret; 4262 4263 /* Inject NMI */ 4264 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { 4265 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { 4266 qemu_mutex_lock_iothread(); 4267 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; 4268 qemu_mutex_unlock_iothread(); 4269 DPRINTF("injected NMI\n"); 4270 ret = kvm_vcpu_ioctl(cpu, KVM_NMI); 4271 if (ret < 0) { 4272 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", 4273 strerror(-ret)); 4274 } 4275 } 4276 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { 4277 qemu_mutex_lock_iothread(); 4278 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; 4279 qemu_mutex_unlock_iothread(); 4280 DPRINTF("injected SMI\n"); 4281 ret = kvm_vcpu_ioctl(cpu, KVM_SMI); 4282 if (ret < 0) { 4283 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n", 4284 strerror(-ret)); 4285 } 4286 } 4287 } 4288 4289 if (!kvm_pic_in_kernel()) { 4290 qemu_mutex_lock_iothread(); 4291 } 4292 4293 /* Force the VCPU out of its inner loop to process any INIT requests 4294 * or (for userspace APIC, but it is cheap to combine the checks here) 4295 * pending TPR access reports. 4296 */ 4297 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { 4298 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && 4299 !(env->hflags & HF_SMM_MASK)) { 4300 cpu->exit_request = 1; 4301 } 4302 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { 4303 cpu->exit_request = 1; 4304 } 4305 } 4306 4307 if (!kvm_pic_in_kernel()) { 4308 /* Try to inject an interrupt if the guest can accept it */ 4309 if (run->ready_for_interrupt_injection && 4310 (cpu->interrupt_request & CPU_INTERRUPT_HARD) && 4311 (env->eflags & IF_MASK)) { 4312 int irq; 4313 4314 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; 4315 irq = cpu_get_pic_interrupt(env); 4316 if (irq >= 0) { 4317 struct kvm_interrupt intr; 4318 4319 intr.irq = irq; 4320 DPRINTF("injected interrupt %d\n", irq); 4321 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); 4322 if (ret < 0) { 4323 fprintf(stderr, 4324 "KVM: injection failed, interrupt lost (%s)\n", 4325 strerror(-ret)); 4326 } 4327 } 4328 } 4329 4330 /* If we have an interrupt but the guest is not ready to receive an 4331 * interrupt, request an interrupt window exit. This will 4332 * cause a return to userspace as soon as the guest is ready to 4333 * receive interrupts. */ 4334 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { 4335 run->request_interrupt_window = 1; 4336 } else { 4337 run->request_interrupt_window = 0; 4338 } 4339 4340 DPRINTF("setting tpr\n"); 4341 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state); 4342 4343 qemu_mutex_unlock_iothread(); 4344 } 4345 } 4346 4347 static void kvm_rate_limit_on_bus_lock(void) 4348 { 4349 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1); 4350 4351 if (delay_ns) { 4352 g_usleep(delay_ns / SCALE_US); 4353 } 4354 } 4355 4356 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) 4357 { 4358 X86CPU *x86_cpu = X86_CPU(cpu); 4359 CPUX86State *env = &x86_cpu->env; 4360 4361 if (run->flags & KVM_RUN_X86_SMM) { 4362 env->hflags |= HF_SMM_MASK; 4363 } else { 4364 env->hflags &= ~HF_SMM_MASK; 4365 } 4366 if (run->if_flag) { 4367 env->eflags |= IF_MASK; 4368 } else { 4369 env->eflags &= ~IF_MASK; 4370 } 4371 if (run->flags & KVM_RUN_X86_BUS_LOCK) { 4372 kvm_rate_limit_on_bus_lock(); 4373 } 4374 4375 /* We need to protect the apic state against concurrent accesses from 4376 * different threads in case the userspace irqchip is used. */ 4377 if (!kvm_irqchip_in_kernel()) { 4378 qemu_mutex_lock_iothread(); 4379 } 4380 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); 4381 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); 4382 if (!kvm_irqchip_in_kernel()) { 4383 qemu_mutex_unlock_iothread(); 4384 } 4385 return cpu_get_mem_attrs(env); 4386 } 4387 4388 int kvm_arch_process_async_events(CPUState *cs) 4389 { 4390 X86CPU *cpu = X86_CPU(cs); 4391 CPUX86State *env = &cpu->env; 4392 4393 if (cs->interrupt_request & CPU_INTERRUPT_MCE) { 4394 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ 4395 assert(env->mcg_cap); 4396 4397 cs->interrupt_request &= ~CPU_INTERRUPT_MCE; 4398 4399 kvm_cpu_synchronize_state(cs); 4400 4401 if (env->exception_nr == EXCP08_DBLE) { 4402 /* this means triple fault */ 4403 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 4404 cs->exit_request = 1; 4405 return 0; 4406 } 4407 kvm_queue_exception(env, EXCP12_MCHK, 0, 0); 4408 env->has_error_code = 0; 4409 4410 cs->halted = 0; 4411 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { 4412 env->mp_state = KVM_MP_STATE_RUNNABLE; 4413 } 4414 } 4415 4416 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) && 4417 !(env->hflags & HF_SMM_MASK)) { 4418 kvm_cpu_synchronize_state(cs); 4419 do_cpu_init(cpu); 4420 } 4421 4422 if (kvm_irqchip_in_kernel()) { 4423 return 0; 4424 } 4425 4426 if (cs->interrupt_request & CPU_INTERRUPT_POLL) { 4427 cs->interrupt_request &= ~CPU_INTERRUPT_POLL; 4428 apic_poll_irq(cpu->apic_state); 4429 } 4430 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && 4431 (env->eflags & IF_MASK)) || 4432 (cs->interrupt_request & CPU_INTERRUPT_NMI)) { 4433 cs->halted = 0; 4434 } 4435 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { 4436 kvm_cpu_synchronize_state(cs); 4437 do_cpu_sipi(cpu); 4438 } 4439 if (cs->interrupt_request & CPU_INTERRUPT_TPR) { 4440 cs->interrupt_request &= ~CPU_INTERRUPT_TPR; 4441 kvm_cpu_synchronize_state(cs); 4442 apic_handle_tpr_access_report(cpu->apic_state, env->eip, 4443 env->tpr_access_type); 4444 } 4445 4446 return cs->halted; 4447 } 4448 4449 static int kvm_handle_halt(X86CPU *cpu) 4450 { 4451 CPUState *cs = CPU(cpu); 4452 CPUX86State *env = &cpu->env; 4453 4454 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && 4455 (env->eflags & IF_MASK)) && 4456 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { 4457 cs->halted = 1; 4458 return EXCP_HLT; 4459 } 4460 4461 return 0; 4462 } 4463 4464 static int kvm_handle_tpr_access(X86CPU *cpu) 4465 { 4466 CPUState *cs = CPU(cpu); 4467 struct kvm_run *run = cs->kvm_run; 4468 4469 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, 4470 run->tpr_access.is_write ? TPR_ACCESS_WRITE 4471 : TPR_ACCESS_READ); 4472 return 1; 4473 } 4474 4475 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 4476 { 4477 static const uint8_t int3 = 0xcc; 4478 4479 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || 4480 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { 4481 return -EINVAL; 4482 } 4483 return 0; 4484 } 4485 4486 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 4487 { 4488 uint8_t int3; 4489 4490 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) { 4491 return -EINVAL; 4492 } 4493 if (int3 != 0xcc) { 4494 return 0; 4495 } 4496 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { 4497 return -EINVAL; 4498 } 4499 return 0; 4500 } 4501 4502 static struct { 4503 target_ulong addr; 4504 int len; 4505 int type; 4506 } hw_breakpoint[4]; 4507 4508 static int nb_hw_breakpoint; 4509 4510 static int find_hw_breakpoint(target_ulong addr, int len, int type) 4511 { 4512 int n; 4513 4514 for (n = 0; n < nb_hw_breakpoint; n++) { 4515 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && 4516 (hw_breakpoint[n].len == len || len == -1)) { 4517 return n; 4518 } 4519 } 4520 return -1; 4521 } 4522 4523 int kvm_arch_insert_hw_breakpoint(target_ulong addr, 4524 target_ulong len, int type) 4525 { 4526 switch (type) { 4527 case GDB_BREAKPOINT_HW: 4528 len = 1; 4529 break; 4530 case GDB_WATCHPOINT_WRITE: 4531 case GDB_WATCHPOINT_ACCESS: 4532 switch (len) { 4533 case 1: 4534 break; 4535 case 2: 4536 case 4: 4537 case 8: 4538 if (addr & (len - 1)) { 4539 return -EINVAL; 4540 } 4541 break; 4542 default: 4543 return -EINVAL; 4544 } 4545 break; 4546 default: 4547 return -ENOSYS; 4548 } 4549 4550 if (nb_hw_breakpoint == 4) { 4551 return -ENOBUFS; 4552 } 4553 if (find_hw_breakpoint(addr, len, type) >= 0) { 4554 return -EEXIST; 4555 } 4556 hw_breakpoint[nb_hw_breakpoint].addr = addr; 4557 hw_breakpoint[nb_hw_breakpoint].len = len; 4558 hw_breakpoint[nb_hw_breakpoint].type = type; 4559 nb_hw_breakpoint++; 4560 4561 return 0; 4562 } 4563 4564 int kvm_arch_remove_hw_breakpoint(target_ulong addr, 4565 target_ulong len, int type) 4566 { 4567 int n; 4568 4569 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); 4570 if (n < 0) { 4571 return -ENOENT; 4572 } 4573 nb_hw_breakpoint--; 4574 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; 4575 4576 return 0; 4577 } 4578 4579 void kvm_arch_remove_all_hw_breakpoints(void) 4580 { 4581 nb_hw_breakpoint = 0; 4582 } 4583 4584 static CPUWatchpoint hw_watchpoint; 4585 4586 static int kvm_handle_debug(X86CPU *cpu, 4587 struct kvm_debug_exit_arch *arch_info) 4588 { 4589 CPUState *cs = CPU(cpu); 4590 CPUX86State *env = &cpu->env; 4591 int ret = 0; 4592 int n; 4593 4594 if (arch_info->exception == EXCP01_DB) { 4595 if (arch_info->dr6 & DR6_BS) { 4596 if (cs->singlestep_enabled) { 4597 ret = EXCP_DEBUG; 4598 } 4599 } else { 4600 for (n = 0; n < 4; n++) { 4601 if (arch_info->dr6 & (1 << n)) { 4602 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { 4603 case 0x0: 4604 ret = EXCP_DEBUG; 4605 break; 4606 case 0x1: 4607 ret = EXCP_DEBUG; 4608 cs->watchpoint_hit = &hw_watchpoint; 4609 hw_watchpoint.vaddr = hw_breakpoint[n].addr; 4610 hw_watchpoint.flags = BP_MEM_WRITE; 4611 break; 4612 case 0x3: 4613 ret = EXCP_DEBUG; 4614 cs->watchpoint_hit = &hw_watchpoint; 4615 hw_watchpoint.vaddr = hw_breakpoint[n].addr; 4616 hw_watchpoint.flags = BP_MEM_ACCESS; 4617 break; 4618 } 4619 } 4620 } 4621 } 4622 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { 4623 ret = EXCP_DEBUG; 4624 } 4625 if (ret == 0) { 4626 cpu_synchronize_state(cs); 4627 assert(env->exception_nr == -1); 4628 4629 /* pass to guest */ 4630 kvm_queue_exception(env, arch_info->exception, 4631 arch_info->exception == EXCP01_DB, 4632 arch_info->dr6); 4633 env->has_error_code = 0; 4634 } 4635 4636 return ret; 4637 } 4638 4639 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) 4640 { 4641 const uint8_t type_code[] = { 4642 [GDB_BREAKPOINT_HW] = 0x0, 4643 [GDB_WATCHPOINT_WRITE] = 0x1, 4644 [GDB_WATCHPOINT_ACCESS] = 0x3 4645 }; 4646 const uint8_t len_code[] = { 4647 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 4648 }; 4649 int n; 4650 4651 if (kvm_sw_breakpoints_active(cpu)) { 4652 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 4653 } 4654 if (nb_hw_breakpoint > 0) { 4655 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 4656 dbg->arch.debugreg[7] = 0x0600; 4657 for (n = 0; n < nb_hw_breakpoint; n++) { 4658 dbg->arch.debugreg[n] = hw_breakpoint[n].addr; 4659 dbg->arch.debugreg[7] |= (2 << (n * 2)) | 4660 (type_code[hw_breakpoint[n].type] << (16 + n*4)) | 4661 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); 4662 } 4663 } 4664 } 4665 4666 static bool has_sgx_provisioning; 4667 4668 static bool __kvm_enable_sgx_provisioning(KVMState *s) 4669 { 4670 int fd, ret; 4671 4672 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) { 4673 return false; 4674 } 4675 4676 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY); 4677 if (fd < 0) { 4678 return false; 4679 } 4680 4681 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd); 4682 if (ret) { 4683 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret)); 4684 exit(1); 4685 } 4686 close(fd); 4687 return true; 4688 } 4689 4690 bool kvm_enable_sgx_provisioning(KVMState *s) 4691 { 4692 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning); 4693 } 4694 4695 static bool host_supports_vmx(void) 4696 { 4697 uint32_t ecx, unused; 4698 4699 host_cpuid(1, 0, &unused, &unused, &ecx, &unused); 4700 return ecx & CPUID_EXT_VMX; 4701 } 4702 4703 #define VMX_INVALID_GUEST_STATE 0x80000021 4704 4705 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 4706 { 4707 X86CPU *cpu = X86_CPU(cs); 4708 uint64_t code; 4709 int ret; 4710 4711 switch (run->exit_reason) { 4712 case KVM_EXIT_HLT: 4713 DPRINTF("handle_hlt\n"); 4714 qemu_mutex_lock_iothread(); 4715 ret = kvm_handle_halt(cpu); 4716 qemu_mutex_unlock_iothread(); 4717 break; 4718 case KVM_EXIT_SET_TPR: 4719 ret = 0; 4720 break; 4721 case KVM_EXIT_TPR_ACCESS: 4722 qemu_mutex_lock_iothread(); 4723 ret = kvm_handle_tpr_access(cpu); 4724 qemu_mutex_unlock_iothread(); 4725 break; 4726 case KVM_EXIT_FAIL_ENTRY: 4727 code = run->fail_entry.hardware_entry_failure_reason; 4728 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", 4729 code); 4730 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { 4731 fprintf(stderr, 4732 "\nIf you're running a guest on an Intel machine without " 4733 "unrestricted mode\n" 4734 "support, the failure can be most likely due to the guest " 4735 "entering an invalid\n" 4736 "state for Intel VT. For example, the guest maybe running " 4737 "in big real mode\n" 4738 "which is not supported on less recent Intel processors." 4739 "\n\n"); 4740 } 4741 ret = -1; 4742 break; 4743 case KVM_EXIT_EXCEPTION: 4744 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", 4745 run->ex.exception, run->ex.error_code); 4746 ret = -1; 4747 break; 4748 case KVM_EXIT_DEBUG: 4749 DPRINTF("kvm_exit_debug\n"); 4750 qemu_mutex_lock_iothread(); 4751 ret = kvm_handle_debug(cpu, &run->debug.arch); 4752 qemu_mutex_unlock_iothread(); 4753 break; 4754 case KVM_EXIT_HYPERV: 4755 ret = kvm_hv_handle_exit(cpu, &run->hyperv); 4756 break; 4757 case KVM_EXIT_IOAPIC_EOI: 4758 ioapic_eoi_broadcast(run->eoi.vector); 4759 ret = 0; 4760 break; 4761 case KVM_EXIT_X86_BUS_LOCK: 4762 /* already handled in kvm_arch_post_run */ 4763 ret = 0; 4764 break; 4765 default: 4766 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 4767 ret = -1; 4768 break; 4769 } 4770 4771 return ret; 4772 } 4773 4774 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 4775 { 4776 X86CPU *cpu = X86_CPU(cs); 4777 CPUX86State *env = &cpu->env; 4778 4779 kvm_cpu_synchronize_state(cs); 4780 return !(env->cr[0] & CR0_PE_MASK) || 4781 ((env->segs[R_CS].selector & 3) != 3); 4782 } 4783 4784 void kvm_arch_init_irq_routing(KVMState *s) 4785 { 4786 /* We know at this point that we're using the in-kernel 4787 * irqchip, so we can use irqfds, and on x86 we know 4788 * we can use msi via irqfd and GSI routing. 4789 */ 4790 kvm_msi_via_irqfd_allowed = true; 4791 kvm_gsi_routing_allowed = true; 4792 4793 if (kvm_irqchip_is_split()) { 4794 int i; 4795 4796 /* If the ioapic is in QEMU and the lapics are in KVM, reserve 4797 MSI routes for signaling interrupts to the local apics. */ 4798 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 4799 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) { 4800 error_report("Could not enable split IRQ mode."); 4801 exit(1); 4802 } 4803 } 4804 } 4805 } 4806 4807 int kvm_arch_irqchip_create(KVMState *s) 4808 { 4809 int ret; 4810 if (kvm_kernel_irqchip_split()) { 4811 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24); 4812 if (ret) { 4813 error_report("Could not enable split irqchip mode: %s", 4814 strerror(-ret)); 4815 exit(1); 4816 } else { 4817 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n"); 4818 kvm_split_irqchip = true; 4819 return 1; 4820 } 4821 } else { 4822 return 0; 4823 } 4824 } 4825 4826 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address) 4827 { 4828 CPUX86State *env; 4829 uint64_t ext_id; 4830 4831 if (!first_cpu) { 4832 return address; 4833 } 4834 env = &X86_CPU(first_cpu)->env; 4835 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) { 4836 return address; 4837 } 4838 4839 /* 4840 * If the remappable format bit is set, or the upper bits are 4841 * already set in address_hi, or the low extended bits aren't 4842 * there anyway, do nothing. 4843 */ 4844 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT); 4845 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) { 4846 return address; 4847 } 4848 4849 address &= ~ext_id; 4850 address |= ext_id << 35; 4851 return address; 4852 } 4853 4854 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 4855 uint64_t address, uint32_t data, PCIDevice *dev) 4856 { 4857 X86IOMMUState *iommu = x86_iommu_get_default(); 4858 4859 if (iommu) { 4860 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu); 4861 4862 if (class->int_remap) { 4863 int ret; 4864 MSIMessage src, dst; 4865 4866 src.address = route->u.msi.address_hi; 4867 src.address <<= VTD_MSI_ADDR_HI_SHIFT; 4868 src.address |= route->u.msi.address_lo; 4869 src.data = route->u.msi.data; 4870 4871 ret = class->int_remap(iommu, &src, &dst, dev ? \ 4872 pci_requester_id(dev) : \ 4873 X86_IOMMU_SID_INVALID); 4874 if (ret) { 4875 trace_kvm_x86_fixup_msi_error(route->gsi); 4876 return 1; 4877 } 4878 4879 /* 4880 * Handled untranslated compatibilty format interrupt with 4881 * extended destination ID in the low bits 11-5. */ 4882 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address); 4883 4884 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT; 4885 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK; 4886 route->u.msi.data = dst.data; 4887 return 0; 4888 } 4889 } 4890 4891 address = kvm_swizzle_msi_ext_dest_id(address); 4892 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT; 4893 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK; 4894 return 0; 4895 } 4896 4897 typedef struct MSIRouteEntry MSIRouteEntry; 4898 4899 struct MSIRouteEntry { 4900 PCIDevice *dev; /* Device pointer */ 4901 int vector; /* MSI/MSIX vector index */ 4902 int virq; /* Virtual IRQ index */ 4903 QLIST_ENTRY(MSIRouteEntry) list; 4904 }; 4905 4906 /* List of used GSI routes */ 4907 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \ 4908 QLIST_HEAD_INITIALIZER(msi_route_list); 4909 4910 static void kvm_update_msi_routes_all(void *private, bool global, 4911 uint32_t index, uint32_t mask) 4912 { 4913 int cnt = 0, vector; 4914 MSIRouteEntry *entry; 4915 MSIMessage msg; 4916 PCIDevice *dev; 4917 4918 /* TODO: explicit route update */ 4919 QLIST_FOREACH(entry, &msi_route_list, list) { 4920 cnt++; 4921 vector = entry->vector; 4922 dev = entry->dev; 4923 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) { 4924 msg = msix_get_message(dev, vector); 4925 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) { 4926 msg = msi_get_message(dev, vector); 4927 } else { 4928 /* 4929 * Either MSI/MSIX is disabled for the device, or the 4930 * specific message was masked out. Skip this one. 4931 */ 4932 continue; 4933 } 4934 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev); 4935 } 4936 kvm_irqchip_commit_routes(kvm_state); 4937 trace_kvm_x86_update_msi_routes(cnt); 4938 } 4939 4940 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 4941 int vector, PCIDevice *dev) 4942 { 4943 static bool notify_list_inited = false; 4944 MSIRouteEntry *entry; 4945 4946 if (!dev) { 4947 /* These are (possibly) IOAPIC routes only used for split 4948 * kernel irqchip mode, while what we are housekeeping are 4949 * PCI devices only. */ 4950 return 0; 4951 } 4952 4953 entry = g_new0(MSIRouteEntry, 1); 4954 entry->dev = dev; 4955 entry->vector = vector; 4956 entry->virq = route->gsi; 4957 QLIST_INSERT_HEAD(&msi_route_list, entry, list); 4958 4959 trace_kvm_x86_add_msi_route(route->gsi); 4960 4961 if (!notify_list_inited) { 4962 /* For the first time we do add route, add ourselves into 4963 * IOMMU's IEC notify list if needed. */ 4964 X86IOMMUState *iommu = x86_iommu_get_default(); 4965 if (iommu) { 4966 x86_iommu_iec_register_notifier(iommu, 4967 kvm_update_msi_routes_all, 4968 NULL); 4969 } 4970 notify_list_inited = true; 4971 } 4972 return 0; 4973 } 4974 4975 int kvm_arch_release_virq_post(int virq) 4976 { 4977 MSIRouteEntry *entry, *next; 4978 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) { 4979 if (entry->virq == virq) { 4980 trace_kvm_x86_remove_msi_route(virq); 4981 QLIST_REMOVE(entry, list); 4982 g_free(entry); 4983 break; 4984 } 4985 } 4986 return 0; 4987 } 4988 4989 int kvm_arch_msi_data_to_gsi(uint32_t data) 4990 { 4991 abort(); 4992 } 4993 4994 bool kvm_has_waitpkg(void) 4995 { 4996 return has_msr_umwait; 4997 } 4998 4999 bool kvm_arch_cpu_check_are_resettable(void) 5000 { 5001 return !sev_es_enabled(); 5002 } 5003