1 /* 2 * QEMU KVM support 3 * 4 * Copyright (C) 2006-2008 Qumranet Technologies 5 * Copyright IBM, Corp. 2008 6 * 7 * Authors: 8 * Anthony Liguori <aliguori@us.ibm.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2 or later. 11 * See the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qapi/qapi-events-run-state.h" 17 #include "qapi/error.h" 18 #include "qapi/visitor.h" 19 #include <sys/ioctl.h> 20 #include <sys/utsname.h> 21 #include <sys/syscall.h> 22 23 #include <linux/kvm.h> 24 #include "standard-headers/asm-x86/kvm_para.h" 25 #include "hw/xen/interface/arch-x86/cpuid.h" 26 27 #include "cpu.h" 28 #include "host-cpu.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/hw_accel.h" 31 #include "sysemu/kvm_int.h" 32 #include "sysemu/runstate.h" 33 #include "kvm_i386.h" 34 #include "../confidential-guest.h" 35 #include "sev.h" 36 #include "xen-emu.h" 37 #include "hyperv.h" 38 #include "hyperv-proto.h" 39 40 #include "exec/gdbstub.h" 41 #include "qemu/host-utils.h" 42 #include "qemu/main-loop.h" 43 #include "qemu/ratelimit.h" 44 #include "qemu/config-file.h" 45 #include "qemu/error-report.h" 46 #include "qemu/memalign.h" 47 #include "hw/i386/x86.h" 48 #include "hw/i386/kvm/xen_evtchn.h" 49 #include "hw/i386/pc.h" 50 #include "hw/i386/apic.h" 51 #include "hw/i386/apic_internal.h" 52 #include "hw/i386/apic-msidef.h" 53 #include "hw/i386/intel_iommu.h" 54 #include "hw/i386/topology.h" 55 #include "hw/i386/x86-iommu.h" 56 #include "hw/i386/e820_memory_layout.h" 57 58 #include "hw/xen/xen.h" 59 60 #include "hw/pci/pci.h" 61 #include "hw/pci/msi.h" 62 #include "hw/pci/msix.h" 63 #include "migration/blocker.h" 64 #include "exec/memattrs.h" 65 #include "trace.h" 66 67 #include CONFIG_DEVICES 68 69 //#define DEBUG_KVM 70 71 #ifdef DEBUG_KVM 72 #define DPRINTF(fmt, ...) \ 73 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 74 #else 75 #define DPRINTF(fmt, ...) \ 76 do { } while (0) 77 #endif 78 79 /* From arch/x86/kvm/lapic.h */ 80 #define KVM_APIC_BUS_CYCLE_NS 1 81 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS) 82 83 #define MSR_KVM_WALL_CLOCK 0x11 84 #define MSR_KVM_SYSTEM_TIME 0x12 85 86 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus 87 * 255 kvm_msr_entry structs */ 88 #define MSR_BUF_SIZE 4096 89 90 static void kvm_init_msrs(X86CPU *cpu); 91 92 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 93 KVM_CAP_INFO(SET_TSS_ADDR), 94 KVM_CAP_INFO(EXT_CPUID), 95 KVM_CAP_INFO(MP_STATE), 96 KVM_CAP_INFO(SIGNAL_MSI), 97 KVM_CAP_INFO(IRQ_ROUTING), 98 KVM_CAP_INFO(DEBUGREGS), 99 KVM_CAP_INFO(XSAVE), 100 KVM_CAP_INFO(VCPU_EVENTS), 101 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP), 102 KVM_CAP_INFO(MCE), 103 KVM_CAP_INFO(ADJUST_CLOCK), 104 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR), 105 KVM_CAP_LAST_INFO 106 }; 107 108 static bool has_msr_star; 109 static bool has_msr_hsave_pa; 110 static bool has_msr_tsc_aux; 111 static bool has_msr_tsc_adjust; 112 static bool has_msr_tsc_deadline; 113 static bool has_msr_feature_control; 114 static bool has_msr_misc_enable; 115 static bool has_msr_smbase; 116 static bool has_msr_bndcfgs; 117 static int lm_capable_kernel; 118 static bool has_msr_hv_hypercall; 119 static bool has_msr_hv_crash; 120 static bool has_msr_hv_reset; 121 static bool has_msr_hv_vpindex; 122 static bool hv_vpindex_settable; 123 static bool has_msr_hv_runtime; 124 static bool has_msr_hv_synic; 125 static bool has_msr_hv_stimer; 126 static bool has_msr_hv_frequencies; 127 static bool has_msr_hv_reenlightenment; 128 static bool has_msr_hv_syndbg_options; 129 static bool has_msr_xss; 130 static bool has_msr_umwait; 131 static bool has_msr_spec_ctrl; 132 static bool has_tsc_scale_msr; 133 static bool has_msr_tsx_ctrl; 134 static bool has_msr_virt_ssbd; 135 static bool has_msr_smi_count; 136 static bool has_msr_arch_capabs; 137 static bool has_msr_core_capabs; 138 static bool has_msr_vmx_vmfunc; 139 static bool has_msr_ucode_rev; 140 static bool has_msr_vmx_procbased_ctls2; 141 static bool has_msr_perf_capabs; 142 static bool has_msr_pkrs; 143 144 static uint32_t has_architectural_pmu_version; 145 static uint32_t num_architectural_pmu_gp_counters; 146 static uint32_t num_architectural_pmu_fixed_counters; 147 148 static int has_xsave2; 149 static int has_xcrs; 150 static int has_sregs2; 151 static int has_exception_payload; 152 static int has_triple_fault_event; 153 154 static bool has_msr_mcg_ext_ctl; 155 156 static struct kvm_cpuid2 *cpuid_cache; 157 static struct kvm_cpuid2 *hv_cpuid_cache; 158 static struct kvm_msr_list *kvm_feature_msrs; 159 160 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES]; 161 162 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */ 163 static RateLimit bus_lock_ratelimit_ctrl; 164 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value); 165 166 static const char *vm_type_name[] = { 167 [KVM_X86_DEFAULT_VM] = "default", 168 [KVM_X86_SEV_VM] = "SEV", 169 [KVM_X86_SEV_ES_VM] = "SEV-ES", 170 }; 171 172 bool kvm_is_vm_type_supported(int type) 173 { 174 uint32_t machine_types; 175 176 /* 177 * old KVM doesn't support KVM_CAP_VM_TYPES but KVM_X86_DEFAULT_VM 178 * is always supported 179 */ 180 if (type == KVM_X86_DEFAULT_VM) { 181 return true; 182 } 183 184 machine_types = kvm_check_extension(KVM_STATE(current_machine->accelerator), 185 KVM_CAP_VM_TYPES); 186 return !!(machine_types & BIT(type)); 187 } 188 189 int kvm_get_vm_type(MachineState *ms) 190 { 191 int kvm_type = KVM_X86_DEFAULT_VM; 192 193 if (ms->cgs) { 194 if (!object_dynamic_cast(OBJECT(ms->cgs), TYPE_X86_CONFIDENTIAL_GUEST)) { 195 error_report("configuration type %s not supported for x86 guests", 196 object_get_typename(OBJECT(ms->cgs))); 197 exit(1); 198 } 199 kvm_type = x86_confidential_guest_kvm_type( 200 X86_CONFIDENTIAL_GUEST(ms->cgs)); 201 } 202 203 if (!kvm_is_vm_type_supported(kvm_type)) { 204 error_report("vm-type %s not supported by KVM", vm_type_name[kvm_type]); 205 exit(1); 206 } 207 208 return kvm_type; 209 } 210 211 bool kvm_has_smm(void) 212 { 213 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM); 214 } 215 216 bool kvm_has_adjust_clock_stable(void) 217 { 218 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK); 219 220 return (ret & KVM_CLOCK_TSC_STABLE); 221 } 222 223 bool kvm_has_exception_payload(void) 224 { 225 return has_exception_payload; 226 } 227 228 static bool kvm_x2apic_api_set_flags(uint64_t flags) 229 { 230 KVMState *s = KVM_STATE(current_accel()); 231 232 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags); 233 } 234 235 #define MEMORIZE(fn, _result) \ 236 ({ \ 237 static bool _memorized; \ 238 \ 239 if (_memorized) { \ 240 return _result; \ 241 } \ 242 _memorized = true; \ 243 _result = fn; \ 244 }) 245 246 static bool has_x2apic_api; 247 248 bool kvm_has_x2apic_api(void) 249 { 250 return has_x2apic_api; 251 } 252 253 bool kvm_enable_x2apic(void) 254 { 255 return MEMORIZE( 256 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS | 257 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK), 258 has_x2apic_api); 259 } 260 261 bool kvm_hv_vpindex_settable(void) 262 { 263 return hv_vpindex_settable; 264 } 265 266 static int kvm_get_tsc(CPUState *cs) 267 { 268 X86CPU *cpu = X86_CPU(cs); 269 CPUX86State *env = &cpu->env; 270 uint64_t value; 271 int ret; 272 273 if (env->tsc_valid) { 274 return 0; 275 } 276 277 env->tsc_valid = !runstate_is_running(); 278 279 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value); 280 if (ret < 0) { 281 return ret; 282 } 283 284 env->tsc = value; 285 return 0; 286 } 287 288 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg) 289 { 290 kvm_get_tsc(cpu); 291 } 292 293 void kvm_synchronize_all_tsc(void) 294 { 295 CPUState *cpu; 296 297 if (kvm_enabled()) { 298 CPU_FOREACH(cpu) { 299 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL); 300 } 301 } 302 } 303 304 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) 305 { 306 struct kvm_cpuid2 *cpuid; 307 int r, size; 308 309 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); 310 cpuid = g_malloc0(size); 311 cpuid->nent = max; 312 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); 313 if (r == 0 && cpuid->nent >= max) { 314 r = -E2BIG; 315 } 316 if (r < 0) { 317 if (r == -E2BIG) { 318 g_free(cpuid); 319 return NULL; 320 } else { 321 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", 322 strerror(-r)); 323 exit(1); 324 } 325 } 326 return cpuid; 327 } 328 329 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough 330 * for all entries. 331 */ 332 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) 333 { 334 struct kvm_cpuid2 *cpuid; 335 int max = 1; 336 337 if (cpuid_cache != NULL) { 338 return cpuid_cache; 339 } 340 while ((cpuid = try_get_cpuid(s, max)) == NULL) { 341 max *= 2; 342 } 343 cpuid_cache = cpuid; 344 return cpuid; 345 } 346 347 static bool host_tsx_broken(void) 348 { 349 int family, model, stepping;\ 350 char vendor[CPUID_VENDOR_SZ + 1]; 351 352 host_cpu_vendor_fms(vendor, &family, &model, &stepping); 353 354 /* Check if we are running on a Haswell host known to have broken TSX */ 355 return !strcmp(vendor, CPUID_VENDOR_INTEL) && 356 (family == 6) && 357 ((model == 63 && stepping < 4) || 358 model == 60 || model == 69 || model == 70); 359 } 360 361 /* Returns the value for a specific register on the cpuid entry 362 */ 363 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) 364 { 365 uint32_t ret = 0; 366 switch (reg) { 367 case R_EAX: 368 ret = entry->eax; 369 break; 370 case R_EBX: 371 ret = entry->ebx; 372 break; 373 case R_ECX: 374 ret = entry->ecx; 375 break; 376 case R_EDX: 377 ret = entry->edx; 378 break; 379 } 380 return ret; 381 } 382 383 /* Find matching entry for function/index on kvm_cpuid2 struct 384 */ 385 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, 386 uint32_t function, 387 uint32_t index) 388 { 389 int i; 390 for (i = 0; i < cpuid->nent; ++i) { 391 if (cpuid->entries[i].function == function && 392 cpuid->entries[i].index == index) { 393 return &cpuid->entries[i]; 394 } 395 } 396 /* not found: */ 397 return NULL; 398 } 399 400 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, 401 uint32_t index, int reg) 402 { 403 struct kvm_cpuid2 *cpuid; 404 uint32_t ret = 0; 405 uint32_t cpuid_1_edx, unused; 406 uint64_t bitmask; 407 408 cpuid = get_supported_cpuid(s); 409 410 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); 411 if (entry) { 412 ret = cpuid_entry_get_reg(entry, reg); 413 } 414 415 /* Fixups for the data returned by KVM, below */ 416 417 if (function == 1 && reg == R_EDX) { 418 /* KVM before 2.6.30 misreports the following features */ 419 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; 420 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */ 421 ret |= CPUID_HT; 422 } else if (function == 1 && reg == R_ECX) { 423 /* We can set the hypervisor flag, even if KVM does not return it on 424 * GET_SUPPORTED_CPUID 425 */ 426 ret |= CPUID_EXT_HYPERVISOR; 427 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it 428 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, 429 * and the irqchip is in the kernel. 430 */ 431 if (kvm_irqchip_in_kernel() && 432 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { 433 ret |= CPUID_EXT_TSC_DEADLINE_TIMER; 434 } 435 436 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled 437 * without the in-kernel irqchip 438 */ 439 if (!kvm_irqchip_in_kernel()) { 440 ret &= ~CPUID_EXT_X2APIC; 441 } 442 443 if (enable_cpu_pm) { 444 int disable_exits = kvm_check_extension(s, 445 KVM_CAP_X86_DISABLE_EXITS); 446 447 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) { 448 ret |= CPUID_EXT_MONITOR; 449 } 450 } 451 } else if (function == 6 && reg == R_EAX) { 452 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ 453 } else if (function == 7 && index == 0 && reg == R_EBX) { 454 /* Not new instructions, just an optimization. */ 455 uint32_t ebx; 456 host_cpuid(7, 0, &unused, &ebx, &unused, &unused); 457 ret |= ebx & CPUID_7_0_EBX_ERMS; 458 459 if (host_tsx_broken()) { 460 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE); 461 } 462 } else if (function == 7 && index == 0 && reg == R_EDX) { 463 /* Not new instructions, just an optimization. */ 464 uint32_t edx; 465 host_cpuid(7, 0, &unused, &unused, &unused, &edx); 466 ret |= edx & CPUID_7_0_EDX_FSRM; 467 468 /* 469 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts. 470 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is 471 * returned by KVM_GET_MSR_INDEX_LIST. 472 */ 473 if (!has_msr_arch_capabs) { 474 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES; 475 } 476 } else if (function == 7 && index == 1 && reg == R_EAX) { 477 /* Not new instructions, just an optimization. */ 478 uint32_t eax; 479 host_cpuid(7, 1, &eax, &unused, &unused, &unused); 480 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC); 481 } else if (function == 7 && index == 2 && reg == R_EDX) { 482 uint32_t edx; 483 host_cpuid(7, 2, &unused, &unused, &unused, &edx); 484 ret |= edx & CPUID_7_2_EDX_MCDT_NO; 485 } else if (function == 0xd && index == 0 && 486 (reg == R_EAX || reg == R_EDX)) { 487 /* 488 * The value returned by KVM_GET_SUPPORTED_CPUID does not include 489 * features that still have to be enabled with the arch_prctl 490 * system call. QEMU needs the full value, which is retrieved 491 * with KVM_GET_DEVICE_ATTR. 492 */ 493 struct kvm_device_attr attr = { 494 .group = 0, 495 .attr = KVM_X86_XCOMP_GUEST_SUPP, 496 .addr = (unsigned long) &bitmask 497 }; 498 499 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES); 500 if (!sys_attr) { 501 return ret; 502 } 503 504 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr); 505 if (rc < 0) { 506 if (rc != -ENXIO) { 507 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) " 508 "error: %d", rc); 509 } 510 return ret; 511 } 512 ret = (reg == R_EAX) ? bitmask : bitmask >> 32; 513 } else if (function == 0x80000001 && reg == R_ECX) { 514 /* 515 * It's safe to enable TOPOEXT even if it's not returned by 516 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows 517 * us to keep CPU models including TOPOEXT runnable on older kernels. 518 */ 519 ret |= CPUID_EXT3_TOPOEXT; 520 } else if (function == 0x80000001 && reg == R_EDX) { 521 /* On Intel, kvm returns cpuid according to the Intel spec, 522 * so add missing bits according to the AMD spec: 523 */ 524 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); 525 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; 526 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) { 527 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't 528 * be enabled without the in-kernel irqchip 529 */ 530 if (!kvm_irqchip_in_kernel()) { 531 ret &= ~(1U << KVM_FEATURE_PV_UNHALT); 532 } 533 if (kvm_irqchip_is_split()) { 534 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID; 535 } 536 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) { 537 ret |= 1U << KVM_HINTS_REALTIME; 538 } 539 540 return ret; 541 } 542 543 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) 544 { 545 struct { 546 struct kvm_msrs info; 547 struct kvm_msr_entry entries[1]; 548 } msr_data = {}; 549 uint64_t value; 550 uint32_t ret, can_be_one, must_be_one; 551 552 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */ 553 return 0; 554 } 555 556 /* Check if requested MSR is supported feature MSR */ 557 int i; 558 for (i = 0; i < kvm_feature_msrs->nmsrs; i++) 559 if (kvm_feature_msrs->indices[i] == index) { 560 break; 561 } 562 if (i == kvm_feature_msrs->nmsrs) { 563 return 0; /* if the feature MSR is not supported, simply return 0 */ 564 } 565 566 msr_data.info.nmsrs = 1; 567 msr_data.entries[0].index = index; 568 569 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data); 570 if (ret != 1) { 571 error_report("KVM get MSR (index=0x%x) feature failed, %s", 572 index, strerror(-ret)); 573 exit(1); 574 } 575 576 value = msr_data.entries[0].data; 577 switch (index) { 578 case MSR_IA32_VMX_PROCBASED_CTLS2: 579 if (!has_msr_vmx_procbased_ctls2) { 580 /* KVM forgot to add these bits for some time, do this ourselves. */ 581 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) & 582 CPUID_XSAVE_XSAVES) { 583 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32; 584 } 585 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) & 586 CPUID_EXT_RDRAND) { 587 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32; 588 } 589 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & 590 CPUID_7_0_EBX_INVPCID) { 591 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32; 592 } 593 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & 594 CPUID_7_0_EBX_RDSEED) { 595 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32; 596 } 597 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) & 598 CPUID_EXT2_RDTSCP) { 599 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32; 600 } 601 } 602 /* fall through */ 603 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 604 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 605 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 606 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 607 /* 608 * Return true for bits that can be one, but do not have to be one. 609 * The SDM tells us which bits could have a "must be one" setting, 610 * so we can do the opposite transformation in make_vmx_msr_value. 611 */ 612 must_be_one = (uint32_t)value; 613 can_be_one = (uint32_t)(value >> 32); 614 return can_be_one & ~must_be_one; 615 616 default: 617 return value; 618 } 619 } 620 621 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, 622 int *max_banks) 623 { 624 *max_banks = kvm_check_extension(s, KVM_CAP_MCE); 625 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); 626 } 627 628 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) 629 { 630 CPUState *cs = CPU(cpu); 631 CPUX86State *env = &cpu->env; 632 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | 633 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; 634 uint64_t mcg_status = MCG_STATUS_MCIP; 635 int flags = 0; 636 637 if (code == BUS_MCEERR_AR) { 638 status |= MCI_STATUS_AR | 0x134; 639 mcg_status |= MCG_STATUS_RIPV | MCG_STATUS_EIPV; 640 } else { 641 status |= 0xc0; 642 mcg_status |= MCG_STATUS_RIPV; 643 } 644 645 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0; 646 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the 647 * guest kernel back into env->mcg_ext_ctl. 648 */ 649 cpu_synchronize_state(cs); 650 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) { 651 mcg_status |= MCG_STATUS_LMCE; 652 flags = 0; 653 } 654 655 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, 656 (MCM_ADDR_PHYS << 6) | 0xc, flags); 657 } 658 659 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar) 660 { 661 MemoryFailureFlags mff = {.action_required = ar, .recursive = false}; 662 663 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action, 664 &mff); 665 } 666 667 static void hardware_memory_error(void *host_addr) 668 { 669 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true); 670 error_report("QEMU got Hardware memory error at addr %p", host_addr); 671 exit(1); 672 } 673 674 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) 675 { 676 X86CPU *cpu = X86_CPU(c); 677 CPUX86State *env = &cpu->env; 678 ram_addr_t ram_addr; 679 hwaddr paddr; 680 681 /* If we get an action required MCE, it has been injected by KVM 682 * while the VM was running. An action optional MCE instead should 683 * be coming from the main thread, which qemu_init_sigbus identifies 684 * as the "early kill" thread. 685 */ 686 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); 687 688 if ((env->mcg_cap & MCG_SER_P) && addr) { 689 ram_addr = qemu_ram_addr_from_host(addr); 690 if (ram_addr != RAM_ADDR_INVALID && 691 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { 692 kvm_hwpoison_page_add(ram_addr); 693 kvm_mce_inject(cpu, paddr, code); 694 695 /* 696 * Use different logging severity based on error type. 697 * If there is additional MCE reporting on the hypervisor, QEMU VA 698 * could be another source to identify the PA and MCE details. 699 */ 700 if (code == BUS_MCEERR_AR) { 701 error_report("Guest MCE Memory Error at QEMU addr %p and " 702 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", 703 addr, paddr, "BUS_MCEERR_AR"); 704 } else { 705 warn_report("Guest MCE Memory Error at QEMU addr %p and " 706 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", 707 addr, paddr, "BUS_MCEERR_AO"); 708 } 709 710 return; 711 } 712 713 if (code == BUS_MCEERR_AO) { 714 warn_report("Hardware memory error at addr %p of type %s " 715 "for memory used by QEMU itself instead of guest system!", 716 addr, "BUS_MCEERR_AO"); 717 } 718 } 719 720 if (code == BUS_MCEERR_AR) { 721 hardware_memory_error(addr); 722 } 723 724 /* Hope we are lucky for AO MCE, just notify a event */ 725 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false); 726 } 727 728 static void kvm_queue_exception(CPUX86State *env, 729 int32_t exception_nr, 730 uint8_t exception_has_payload, 731 uint64_t exception_payload) 732 { 733 assert(env->exception_nr == -1); 734 assert(!env->exception_pending); 735 assert(!env->exception_injected); 736 assert(!env->exception_has_payload); 737 738 env->exception_nr = exception_nr; 739 740 if (has_exception_payload) { 741 env->exception_pending = 1; 742 743 env->exception_has_payload = exception_has_payload; 744 env->exception_payload = exception_payload; 745 } else { 746 env->exception_injected = 1; 747 748 if (exception_nr == EXCP01_DB) { 749 assert(exception_has_payload); 750 env->dr[6] = exception_payload; 751 } else if (exception_nr == EXCP0E_PAGE) { 752 assert(exception_has_payload); 753 env->cr[2] = exception_payload; 754 } else { 755 assert(!exception_has_payload); 756 } 757 } 758 } 759 760 static void cpu_update_state(void *opaque, bool running, RunState state) 761 { 762 CPUX86State *env = opaque; 763 764 if (running) { 765 env->tsc_valid = false; 766 } 767 } 768 769 unsigned long kvm_arch_vcpu_id(CPUState *cs) 770 { 771 X86CPU *cpu = X86_CPU(cs); 772 return cpu->apic_id; 773 } 774 775 #ifndef KVM_CPUID_SIGNATURE_NEXT 776 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 777 #endif 778 779 static bool hyperv_enabled(X86CPU *cpu) 780 { 781 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 && 782 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) || 783 cpu->hyperv_features || cpu->hyperv_passthrough); 784 } 785 786 /* 787 * Check whether target_freq is within conservative 788 * ntp correctable bounds (250ppm) of freq 789 */ 790 static inline bool freq_within_bounds(int freq, int target_freq) 791 { 792 int max_freq = freq + (freq * 250 / 1000000); 793 int min_freq = freq - (freq * 250 / 1000000); 794 795 if (target_freq >= min_freq && target_freq <= max_freq) { 796 return true; 797 } 798 799 return false; 800 } 801 802 static int kvm_arch_set_tsc_khz(CPUState *cs) 803 { 804 X86CPU *cpu = X86_CPU(cs); 805 CPUX86State *env = &cpu->env; 806 int r, cur_freq; 807 bool set_ioctl = false; 808 809 if (!env->tsc_khz) { 810 return 0; 811 } 812 813 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 814 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP; 815 816 /* 817 * If TSC scaling is supported, attempt to set TSC frequency. 818 */ 819 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) { 820 set_ioctl = true; 821 } 822 823 /* 824 * If desired TSC frequency is within bounds of NTP correction, 825 * attempt to set TSC frequency. 826 */ 827 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) { 828 set_ioctl = true; 829 } 830 831 r = set_ioctl ? 832 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) : 833 -ENOTSUP; 834 835 if (r < 0) { 836 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current 837 * TSC frequency doesn't match the one we want. 838 */ 839 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 840 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : 841 -ENOTSUP; 842 if (cur_freq <= 0 || cur_freq != env->tsc_khz) { 843 warn_report("TSC frequency mismatch between " 844 "VM (%" PRId64 " kHz) and host (%d kHz), " 845 "and TSC scaling unavailable", 846 env->tsc_khz, cur_freq); 847 return r; 848 } 849 } 850 851 return 0; 852 } 853 854 static bool tsc_is_stable_and_known(CPUX86State *env) 855 { 856 if (!env->tsc_khz) { 857 return false; 858 } 859 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) 860 || env->user_tsc_khz; 861 } 862 863 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1) 864 865 static struct { 866 const char *desc; 867 struct { 868 uint32_t func; 869 int reg; 870 uint32_t bits; 871 } flags[2]; 872 uint64_t dependencies; 873 } kvm_hyperv_properties[] = { 874 [HYPERV_FEAT_RELAXED] = { 875 .desc = "relaxed timing (hv-relaxed)", 876 .flags = { 877 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 878 .bits = HV_RELAXED_TIMING_RECOMMENDED} 879 } 880 }, 881 [HYPERV_FEAT_VAPIC] = { 882 .desc = "virtual APIC (hv-vapic)", 883 .flags = { 884 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 885 .bits = HV_APIC_ACCESS_AVAILABLE} 886 } 887 }, 888 [HYPERV_FEAT_TIME] = { 889 .desc = "clocksources (hv-time)", 890 .flags = { 891 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 892 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE} 893 } 894 }, 895 [HYPERV_FEAT_CRASH] = { 896 .desc = "crash MSRs (hv-crash)", 897 .flags = { 898 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 899 .bits = HV_GUEST_CRASH_MSR_AVAILABLE} 900 } 901 }, 902 [HYPERV_FEAT_RESET] = { 903 .desc = "reset MSR (hv-reset)", 904 .flags = { 905 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 906 .bits = HV_RESET_AVAILABLE} 907 } 908 }, 909 [HYPERV_FEAT_VPINDEX] = { 910 .desc = "VP_INDEX MSR (hv-vpindex)", 911 .flags = { 912 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 913 .bits = HV_VP_INDEX_AVAILABLE} 914 } 915 }, 916 [HYPERV_FEAT_RUNTIME] = { 917 .desc = "VP_RUNTIME MSR (hv-runtime)", 918 .flags = { 919 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 920 .bits = HV_VP_RUNTIME_AVAILABLE} 921 } 922 }, 923 [HYPERV_FEAT_SYNIC] = { 924 .desc = "synthetic interrupt controller (hv-synic)", 925 .flags = { 926 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 927 .bits = HV_SYNIC_AVAILABLE} 928 } 929 }, 930 [HYPERV_FEAT_STIMER] = { 931 .desc = "synthetic timers (hv-stimer)", 932 .flags = { 933 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 934 .bits = HV_SYNTIMERS_AVAILABLE} 935 }, 936 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME) 937 }, 938 [HYPERV_FEAT_FREQUENCIES] = { 939 .desc = "frequency MSRs (hv-frequencies)", 940 .flags = { 941 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 942 .bits = HV_ACCESS_FREQUENCY_MSRS}, 943 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 944 .bits = HV_FREQUENCY_MSRS_AVAILABLE} 945 } 946 }, 947 [HYPERV_FEAT_REENLIGHTENMENT] = { 948 .desc = "reenlightenment MSRs (hv-reenlightenment)", 949 .flags = { 950 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 951 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL} 952 } 953 }, 954 [HYPERV_FEAT_TLBFLUSH] = { 955 .desc = "paravirtualized TLB flush (hv-tlbflush)", 956 .flags = { 957 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 958 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED | 959 HV_EX_PROCESSOR_MASKS_RECOMMENDED} 960 }, 961 .dependencies = BIT(HYPERV_FEAT_VPINDEX) 962 }, 963 [HYPERV_FEAT_EVMCS] = { 964 .desc = "enlightened VMCS (hv-evmcs)", 965 .flags = { 966 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 967 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED} 968 }, 969 .dependencies = BIT(HYPERV_FEAT_VAPIC) 970 }, 971 [HYPERV_FEAT_IPI] = { 972 .desc = "paravirtualized IPI (hv-ipi)", 973 .flags = { 974 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 975 .bits = HV_CLUSTER_IPI_RECOMMENDED | 976 HV_EX_PROCESSOR_MASKS_RECOMMENDED} 977 }, 978 .dependencies = BIT(HYPERV_FEAT_VPINDEX) 979 }, 980 [HYPERV_FEAT_STIMER_DIRECT] = { 981 .desc = "direct mode synthetic timers (hv-stimer-direct)", 982 .flags = { 983 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 984 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE} 985 }, 986 .dependencies = BIT(HYPERV_FEAT_STIMER) 987 }, 988 [HYPERV_FEAT_AVIC] = { 989 .desc = "AVIC/APICv support (hv-avic/hv-apicv)", 990 .flags = { 991 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 992 .bits = HV_DEPRECATING_AEOI_RECOMMENDED} 993 } 994 }, 995 #ifdef CONFIG_SYNDBG 996 [HYPERV_FEAT_SYNDBG] = { 997 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)", 998 .flags = { 999 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 1000 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE} 1001 }, 1002 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED) 1003 }, 1004 #endif 1005 [HYPERV_FEAT_MSR_BITMAP] = { 1006 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)", 1007 .flags = { 1008 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX, 1009 .bits = HV_NESTED_MSR_BITMAP} 1010 } 1011 }, 1012 [HYPERV_FEAT_XMM_INPUT] = { 1013 .desc = "XMM fast hypercall input (hv-xmm-input)", 1014 .flags = { 1015 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 1016 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE} 1017 } 1018 }, 1019 [HYPERV_FEAT_TLBFLUSH_EXT] = { 1020 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)", 1021 .flags = { 1022 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 1023 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE} 1024 }, 1025 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH) 1026 }, 1027 [HYPERV_FEAT_TLBFLUSH_DIRECT] = { 1028 .desc = "direct TLB flush (hv-tlbflush-direct)", 1029 .flags = { 1030 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX, 1031 .bits = HV_NESTED_DIRECT_FLUSH} 1032 }, 1033 .dependencies = BIT(HYPERV_FEAT_VAPIC) 1034 }, 1035 }; 1036 1037 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max, 1038 bool do_sys_ioctl) 1039 { 1040 struct kvm_cpuid2 *cpuid; 1041 int r, size; 1042 1043 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); 1044 cpuid = g_malloc0(size); 1045 cpuid->nent = max; 1046 1047 if (do_sys_ioctl) { 1048 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid); 1049 } else { 1050 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid); 1051 } 1052 if (r == 0 && cpuid->nent >= max) { 1053 r = -E2BIG; 1054 } 1055 if (r < 0) { 1056 if (r == -E2BIG) { 1057 g_free(cpuid); 1058 return NULL; 1059 } else { 1060 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n", 1061 strerror(-r)); 1062 exit(1); 1063 } 1064 } 1065 return cpuid; 1066 } 1067 1068 /* 1069 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough 1070 * for all entries. 1071 */ 1072 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs) 1073 { 1074 struct kvm_cpuid2 *cpuid; 1075 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */ 1076 int max = 11; 1077 int i; 1078 bool do_sys_ioctl; 1079 1080 do_sys_ioctl = 1081 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0; 1082 1083 /* 1084 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is 1085 * unsupported, kvm_hyperv_expand_features() checks for that. 1086 */ 1087 assert(do_sys_ioctl || cs->kvm_state); 1088 1089 /* 1090 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with 1091 * -E2BIG, however, it doesn't report back the right size. Keep increasing 1092 * it and re-trying until we succeed. 1093 */ 1094 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) { 1095 max++; 1096 } 1097 1098 /* 1099 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before 1100 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the 1101 * information early, just check for the capability and set the bit 1102 * manually. 1103 */ 1104 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state, 1105 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { 1106 for (i = 0; i < cpuid->nent; i++) { 1107 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) { 1108 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED; 1109 } 1110 } 1111 } 1112 1113 return cpuid; 1114 } 1115 1116 /* 1117 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature 1118 * leaves from KVM_CAP_HYPERV* and present MSRs data. 1119 */ 1120 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs) 1121 { 1122 X86CPU *cpu = X86_CPU(cs); 1123 struct kvm_cpuid2 *cpuid; 1124 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm; 1125 1126 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */ 1127 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries)); 1128 cpuid->nent = 2; 1129 1130 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */ 1131 entry_feat = &cpuid->entries[0]; 1132 entry_feat->function = HV_CPUID_FEATURES; 1133 1134 entry_recomm = &cpuid->entries[1]; 1135 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO; 1136 entry_recomm->ebx = cpu->hyperv_spinlock_attempts; 1137 1138 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) { 1139 entry_feat->eax |= HV_HYPERCALL_AVAILABLE; 1140 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE; 1141 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; 1142 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED; 1143 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED; 1144 } 1145 1146 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { 1147 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE; 1148 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE; 1149 } 1150 1151 if (has_msr_hv_frequencies) { 1152 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS; 1153 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE; 1154 } 1155 1156 if (has_msr_hv_crash) { 1157 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE; 1158 } 1159 1160 if (has_msr_hv_reenlightenment) { 1161 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL; 1162 } 1163 1164 if (has_msr_hv_reset) { 1165 entry_feat->eax |= HV_RESET_AVAILABLE; 1166 } 1167 1168 if (has_msr_hv_vpindex) { 1169 entry_feat->eax |= HV_VP_INDEX_AVAILABLE; 1170 } 1171 1172 if (has_msr_hv_runtime) { 1173 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE; 1174 } 1175 1176 if (has_msr_hv_synic) { 1177 unsigned int cap = cpu->hyperv_synic_kvm_only ? 1178 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; 1179 1180 if (kvm_check_extension(cs->kvm_state, cap) > 0) { 1181 entry_feat->eax |= HV_SYNIC_AVAILABLE; 1182 } 1183 } 1184 1185 if (has_msr_hv_stimer) { 1186 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE; 1187 } 1188 1189 if (has_msr_hv_syndbg_options) { 1190 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE; 1191 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE; 1192 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED; 1193 } 1194 1195 if (kvm_check_extension(cs->kvm_state, 1196 KVM_CAP_HYPERV_TLBFLUSH) > 0) { 1197 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED; 1198 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED; 1199 } 1200 1201 if (kvm_check_extension(cs->kvm_state, 1202 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { 1203 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED; 1204 } 1205 1206 if (kvm_check_extension(cs->kvm_state, 1207 KVM_CAP_HYPERV_SEND_IPI) > 0) { 1208 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED; 1209 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED; 1210 } 1211 1212 return cpuid; 1213 } 1214 1215 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg) 1216 { 1217 struct kvm_cpuid_entry2 *entry; 1218 struct kvm_cpuid2 *cpuid; 1219 1220 if (hv_cpuid_cache) { 1221 cpuid = hv_cpuid_cache; 1222 } else { 1223 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) { 1224 cpuid = get_supported_hv_cpuid(cs); 1225 } else { 1226 /* 1227 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded 1228 * before KVM context is created but this is only done when 1229 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies 1230 * KVM_CAP_HYPERV_CPUID. 1231 */ 1232 assert(cs->kvm_state); 1233 1234 cpuid = get_supported_hv_cpuid_legacy(cs); 1235 } 1236 hv_cpuid_cache = cpuid; 1237 } 1238 1239 if (!cpuid) { 1240 return 0; 1241 } 1242 1243 entry = cpuid_find_entry(cpuid, func, 0); 1244 if (!entry) { 1245 return 0; 1246 } 1247 1248 return cpuid_entry_get_reg(entry, reg); 1249 } 1250 1251 static bool hyperv_feature_supported(CPUState *cs, int feature) 1252 { 1253 uint32_t func, bits; 1254 int i, reg; 1255 1256 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) { 1257 1258 func = kvm_hyperv_properties[feature].flags[i].func; 1259 reg = kvm_hyperv_properties[feature].flags[i].reg; 1260 bits = kvm_hyperv_properties[feature].flags[i].bits; 1261 1262 if (!func) { 1263 continue; 1264 } 1265 1266 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) { 1267 return false; 1268 } 1269 } 1270 1271 return true; 1272 } 1273 1274 /* Checks that all feature dependencies are enabled */ 1275 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp) 1276 { 1277 uint64_t deps; 1278 int dep_feat; 1279 1280 deps = kvm_hyperv_properties[feature].dependencies; 1281 while (deps) { 1282 dep_feat = ctz64(deps); 1283 if (!(hyperv_feat_enabled(cpu, dep_feat))) { 1284 error_setg(errp, "Hyper-V %s requires Hyper-V %s", 1285 kvm_hyperv_properties[feature].desc, 1286 kvm_hyperv_properties[dep_feat].desc); 1287 return false; 1288 } 1289 deps &= ~(1ull << dep_feat); 1290 } 1291 1292 return true; 1293 } 1294 1295 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg) 1296 { 1297 X86CPU *cpu = X86_CPU(cs); 1298 uint32_t r = 0; 1299 int i, j; 1300 1301 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) { 1302 if (!hyperv_feat_enabled(cpu, i)) { 1303 continue; 1304 } 1305 1306 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) { 1307 if (kvm_hyperv_properties[i].flags[j].func != func) { 1308 continue; 1309 } 1310 if (kvm_hyperv_properties[i].flags[j].reg != reg) { 1311 continue; 1312 } 1313 1314 r |= kvm_hyperv_properties[i].flags[j].bits; 1315 } 1316 } 1317 1318 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */ 1319 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) { 1320 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { 1321 r |= DEFAULT_EVMCS_VERSION; 1322 } 1323 } 1324 1325 return r; 1326 } 1327 1328 /* 1329 * Expand Hyper-V CPU features. In partucular, check that all the requested 1330 * features are supported by the host and the sanity of the configuration 1331 * (that all the required dependencies are included). Also, this takes care 1332 * of 'hv_passthrough' mode and fills the environment with all supported 1333 * Hyper-V features. 1334 */ 1335 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp) 1336 { 1337 CPUState *cs = CPU(cpu); 1338 Error *local_err = NULL; 1339 int feat; 1340 1341 if (!hyperv_enabled(cpu)) 1342 return true; 1343 1344 /* 1345 * When kvm_hyperv_expand_features is called at CPU feature expansion 1346 * time per-CPU kvm_state is not available yet so we can only proceed 1347 * when KVM_CAP_SYS_HYPERV_CPUID is supported. 1348 */ 1349 if (!cs->kvm_state && 1350 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID)) 1351 return true; 1352 1353 if (cpu->hyperv_passthrough) { 1354 cpu->hyperv_vendor_id[0] = 1355 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX); 1356 cpu->hyperv_vendor_id[1] = 1357 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX); 1358 cpu->hyperv_vendor_id[2] = 1359 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX); 1360 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor, 1361 sizeof(cpu->hyperv_vendor_id) + 1); 1362 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id, 1363 sizeof(cpu->hyperv_vendor_id)); 1364 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0; 1365 1366 cpu->hyperv_interface_id[0] = 1367 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX); 1368 cpu->hyperv_interface_id[1] = 1369 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX); 1370 cpu->hyperv_interface_id[2] = 1371 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX); 1372 cpu->hyperv_interface_id[3] = 1373 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX); 1374 1375 cpu->hyperv_ver_id_build = 1376 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX); 1377 cpu->hyperv_ver_id_major = 1378 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16; 1379 cpu->hyperv_ver_id_minor = 1380 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff; 1381 cpu->hyperv_ver_id_sp = 1382 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX); 1383 cpu->hyperv_ver_id_sb = 1384 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24; 1385 cpu->hyperv_ver_id_sn = 1386 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff; 1387 1388 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, 1389 R_EAX); 1390 cpu->hyperv_limits[0] = 1391 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX); 1392 cpu->hyperv_limits[1] = 1393 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX); 1394 cpu->hyperv_limits[2] = 1395 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX); 1396 1397 cpu->hyperv_spinlock_attempts = 1398 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX); 1399 1400 /* 1401 * Mark feature as enabled in 'cpu->hyperv_features' as 1402 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs. 1403 */ 1404 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) { 1405 if (hyperv_feature_supported(cs, feat)) { 1406 cpu->hyperv_features |= BIT(feat); 1407 } 1408 } 1409 } else { 1410 /* Check features availability and dependencies */ 1411 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) { 1412 /* If the feature was not requested skip it. */ 1413 if (!hyperv_feat_enabled(cpu, feat)) { 1414 continue; 1415 } 1416 1417 /* Check if the feature is supported by KVM */ 1418 if (!hyperv_feature_supported(cs, feat)) { 1419 error_setg(errp, "Hyper-V %s is not supported by kernel", 1420 kvm_hyperv_properties[feat].desc); 1421 return false; 1422 } 1423 1424 /* Check dependencies */ 1425 if (!hv_feature_check_deps(cpu, feat, &local_err)) { 1426 error_propagate(errp, local_err); 1427 return false; 1428 } 1429 } 1430 } 1431 1432 /* Additional dependencies not covered by kvm_hyperv_properties[] */ 1433 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && 1434 !cpu->hyperv_synic_kvm_only && 1435 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { 1436 error_setg(errp, "Hyper-V %s requires Hyper-V %s", 1437 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc, 1438 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc); 1439 return false; 1440 } 1441 1442 return true; 1443 } 1444 1445 /* 1446 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent. 1447 */ 1448 static int hyperv_fill_cpuids(CPUState *cs, 1449 struct kvm_cpuid_entry2 *cpuid_ent) 1450 { 1451 X86CPU *cpu = X86_CPU(cs); 1452 struct kvm_cpuid_entry2 *c; 1453 uint32_t signature[3]; 1454 uint32_t cpuid_i = 0, max_cpuid_leaf = 0; 1455 uint32_t nested_eax = 1456 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX); 1457 1458 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES : 1459 HV_CPUID_IMPLEMENT_LIMITS; 1460 1461 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) { 1462 max_cpuid_leaf = 1463 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES); 1464 } 1465 1466 c = &cpuid_ent[cpuid_i++]; 1467 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 1468 c->eax = max_cpuid_leaf; 1469 c->ebx = cpu->hyperv_vendor_id[0]; 1470 c->ecx = cpu->hyperv_vendor_id[1]; 1471 c->edx = cpu->hyperv_vendor_id[2]; 1472 1473 c = &cpuid_ent[cpuid_i++]; 1474 c->function = HV_CPUID_INTERFACE; 1475 c->eax = cpu->hyperv_interface_id[0]; 1476 c->ebx = cpu->hyperv_interface_id[1]; 1477 c->ecx = cpu->hyperv_interface_id[2]; 1478 c->edx = cpu->hyperv_interface_id[3]; 1479 1480 c = &cpuid_ent[cpuid_i++]; 1481 c->function = HV_CPUID_VERSION; 1482 c->eax = cpu->hyperv_ver_id_build; 1483 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 | 1484 cpu->hyperv_ver_id_minor; 1485 c->ecx = cpu->hyperv_ver_id_sp; 1486 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 | 1487 (cpu->hyperv_ver_id_sn & 0xffffff); 1488 1489 c = &cpuid_ent[cpuid_i++]; 1490 c->function = HV_CPUID_FEATURES; 1491 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX); 1492 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX); 1493 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX); 1494 1495 /* Unconditionally required with any Hyper-V enlightenment */ 1496 c->eax |= HV_HYPERCALL_AVAILABLE; 1497 1498 /* SynIC and Vmbus devices require messages/signals hypercalls */ 1499 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && 1500 !cpu->hyperv_synic_kvm_only) { 1501 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS; 1502 } 1503 1504 1505 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */ 1506 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; 1507 1508 c = &cpuid_ent[cpuid_i++]; 1509 c->function = HV_CPUID_ENLIGHTMENT_INFO; 1510 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX); 1511 c->ebx = cpu->hyperv_spinlock_attempts; 1512 1513 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) && 1514 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) { 1515 c->eax |= HV_APIC_ACCESS_RECOMMENDED; 1516 } 1517 1518 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) { 1519 c->eax |= HV_NO_NONARCH_CORESHARING; 1520 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) { 1521 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) & 1522 HV_NO_NONARCH_CORESHARING; 1523 } 1524 1525 c = &cpuid_ent[cpuid_i++]; 1526 c->function = HV_CPUID_IMPLEMENT_LIMITS; 1527 c->eax = cpu->hv_max_vps; 1528 c->ebx = cpu->hyperv_limits[0]; 1529 c->ecx = cpu->hyperv_limits[1]; 1530 c->edx = cpu->hyperv_limits[2]; 1531 1532 if (nested_eax) { 1533 uint32_t function; 1534 1535 /* Create zeroed 0x40000006..0x40000009 leaves */ 1536 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1; 1537 function < HV_CPUID_NESTED_FEATURES; function++) { 1538 c = &cpuid_ent[cpuid_i++]; 1539 c->function = function; 1540 } 1541 1542 c = &cpuid_ent[cpuid_i++]; 1543 c->function = HV_CPUID_NESTED_FEATURES; 1544 c->eax = nested_eax; 1545 } 1546 1547 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) { 1548 c = &cpuid_ent[cpuid_i++]; 1549 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS; 1550 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? 1551 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; 1552 memcpy(signature, "Microsoft VS", 12); 1553 c->eax = 0; 1554 c->ebx = signature[0]; 1555 c->ecx = signature[1]; 1556 c->edx = signature[2]; 1557 1558 c = &cpuid_ent[cpuid_i++]; 1559 c->function = HV_CPUID_SYNDBG_INTERFACE; 1560 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12); 1561 c->eax = signature[0]; 1562 c->ebx = 0; 1563 c->ecx = 0; 1564 c->edx = 0; 1565 1566 c = &cpuid_ent[cpuid_i++]; 1567 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES; 1568 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING; 1569 c->ebx = 0; 1570 c->ecx = 0; 1571 c->edx = 0; 1572 } 1573 1574 return cpuid_i; 1575 } 1576 1577 static Error *hv_passthrough_mig_blocker; 1578 static Error *hv_no_nonarch_cs_mig_blocker; 1579 1580 /* Checks that the exposed eVMCS version range is supported by KVM */ 1581 static bool evmcs_version_supported(uint16_t evmcs_version, 1582 uint16_t supported_evmcs_version) 1583 { 1584 uint8_t min_version = evmcs_version & 0xff; 1585 uint8_t max_version = evmcs_version >> 8; 1586 uint8_t min_supported_version = supported_evmcs_version & 0xff; 1587 uint8_t max_supported_version = supported_evmcs_version >> 8; 1588 1589 return (min_version >= min_supported_version) && 1590 (max_version <= max_supported_version); 1591 } 1592 1593 static int hyperv_init_vcpu(X86CPU *cpu) 1594 { 1595 CPUState *cs = CPU(cpu); 1596 Error *local_err = NULL; 1597 int ret; 1598 1599 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) { 1600 error_setg(&hv_passthrough_mig_blocker, 1601 "'hv-passthrough' CPU flag prevents migration, use explicit" 1602 " set of hv-* flags instead"); 1603 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err); 1604 if (ret < 0) { 1605 error_report_err(local_err); 1606 return ret; 1607 } 1608 } 1609 1610 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO && 1611 hv_no_nonarch_cs_mig_blocker == NULL) { 1612 error_setg(&hv_no_nonarch_cs_mig_blocker, 1613 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration" 1614 " use explicit 'hv-no-nonarch-coresharing=on' instead (but" 1615 " make sure SMT is disabled and/or that vCPUs are properly" 1616 " pinned)"); 1617 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err); 1618 if (ret < 0) { 1619 error_report_err(local_err); 1620 return ret; 1621 } 1622 } 1623 1624 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) { 1625 /* 1626 * the kernel doesn't support setting vp_index; assert that its value 1627 * is in sync 1628 */ 1629 uint64_t value; 1630 1631 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value); 1632 if (ret < 0) { 1633 return ret; 1634 } 1635 1636 if (value != hyperv_vp_index(CPU(cpu))) { 1637 error_report("kernel's vp_index != QEMU's vp_index"); 1638 return -ENXIO; 1639 } 1640 } 1641 1642 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 1643 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ? 1644 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; 1645 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0); 1646 if (ret < 0) { 1647 error_report("failed to turn on HyperV SynIC in KVM: %s", 1648 strerror(-ret)); 1649 return ret; 1650 } 1651 1652 if (!cpu->hyperv_synic_kvm_only) { 1653 ret = hyperv_x86_synic_add(cpu); 1654 if (ret < 0) { 1655 error_report("failed to create HyperV SynIC: %s", 1656 strerror(-ret)); 1657 return ret; 1658 } 1659 } 1660 } 1661 1662 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { 1663 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION; 1664 uint16_t supported_evmcs_version; 1665 1666 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0, 1667 (uintptr_t)&supported_evmcs_version); 1668 1669 /* 1670 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs' 1671 * option sets. Note: we hardcode the maximum supported eVMCS version 1672 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if) 1673 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have 1674 * to be added. 1675 */ 1676 if (ret < 0) { 1677 error_report("Hyper-V %s is not supported by kernel", 1678 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc); 1679 return ret; 1680 } 1681 1682 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) { 1683 error_report("eVMCS version range [%d..%d] is not supported by " 1684 "kernel (supported: [%d..%d])", evmcs_version & 0xff, 1685 evmcs_version >> 8, supported_evmcs_version & 0xff, 1686 supported_evmcs_version >> 8); 1687 return -ENOTSUP; 1688 } 1689 } 1690 1691 if (cpu->hyperv_enforce_cpuid) { 1692 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1); 1693 if (ret < 0) { 1694 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s", 1695 strerror(-ret)); 1696 return ret; 1697 } 1698 } 1699 1700 /* Skip SynIC and VP_INDEX since they are hard deps already */ 1701 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) && 1702 hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) && 1703 hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) { 1704 hyperv_x86_set_vmbus_recommended_features_enabled(); 1705 } 1706 1707 return 0; 1708 } 1709 1710 static Error *invtsc_mig_blocker; 1711 1712 #define KVM_MAX_CPUID_ENTRIES 100 1713 1714 static void kvm_init_xsave(CPUX86State *env) 1715 { 1716 if (has_xsave2) { 1717 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096); 1718 } else { 1719 env->xsave_buf_len = sizeof(struct kvm_xsave); 1720 } 1721 1722 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len); 1723 memset(env->xsave_buf, 0, env->xsave_buf_len); 1724 /* 1725 * The allocated storage must be large enough for all of the 1726 * possible XSAVE state components. 1727 */ 1728 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <= 1729 env->xsave_buf_len); 1730 } 1731 1732 static void kvm_init_nested_state(CPUX86State *env) 1733 { 1734 struct kvm_vmx_nested_state_hdr *vmx_hdr; 1735 uint32_t size; 1736 1737 if (!env->nested_state) { 1738 return; 1739 } 1740 1741 size = env->nested_state->size; 1742 1743 memset(env->nested_state, 0, size); 1744 env->nested_state->size = size; 1745 1746 if (cpu_has_vmx(env)) { 1747 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX; 1748 vmx_hdr = &env->nested_state->hdr.vmx; 1749 vmx_hdr->vmxon_pa = -1ull; 1750 vmx_hdr->vmcs12_pa = -1ull; 1751 } else if (cpu_has_svm(env)) { 1752 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM; 1753 } 1754 } 1755 1756 static uint32_t kvm_x86_build_cpuid(CPUX86State *env, 1757 struct kvm_cpuid_entry2 *entries, 1758 uint32_t cpuid_i) 1759 { 1760 uint32_t limit, i, j; 1761 uint32_t unused; 1762 struct kvm_cpuid_entry2 *c; 1763 1764 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); 1765 1766 for (i = 0; i <= limit; i++) { 1767 j = 0; 1768 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1769 goto full; 1770 } 1771 c = &entries[cpuid_i++]; 1772 switch (i) { 1773 case 2: { 1774 /* Keep reading function 2 till all the input is received */ 1775 int times; 1776 1777 c->function = i; 1778 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | 1779 KVM_CPUID_FLAG_STATE_READ_NEXT; 1780 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1781 times = c->eax & 0xff; 1782 1783 for (j = 1; j < times; ++j) { 1784 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1785 goto full; 1786 } 1787 c = &entries[cpuid_i++]; 1788 c->function = i; 1789 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; 1790 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1791 } 1792 break; 1793 } 1794 case 0x1f: 1795 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 1796 cpuid_i--; 1797 break; 1798 } 1799 /* fallthrough */ 1800 case 4: 1801 case 0xb: 1802 case 0xd: 1803 for (j = 0; ; j++) { 1804 if (i == 0xd && j == 64) { 1805 break; 1806 } 1807 1808 c->function = i; 1809 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1810 c->index = j; 1811 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1812 1813 if (i == 4 && c->eax == 0) { 1814 break; 1815 } 1816 if (i == 0xb && !(c->ecx & 0xff00)) { 1817 break; 1818 } 1819 if (i == 0x1f && !(c->ecx & 0xff00)) { 1820 break; 1821 } 1822 if (i == 0xd && c->eax == 0) { 1823 continue; 1824 } 1825 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1826 goto full; 1827 } 1828 c = &entries[cpuid_i++]; 1829 } 1830 break; 1831 case 0x12: 1832 for (j = 0; ; j++) { 1833 c->function = i; 1834 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1835 c->index = j; 1836 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1837 1838 if (j > 1 && (c->eax & 0xf) != 1) { 1839 break; 1840 } 1841 1842 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1843 goto full; 1844 } 1845 c = &entries[cpuid_i++]; 1846 } 1847 break; 1848 case 0x7: 1849 case 0x14: 1850 case 0x1d: 1851 case 0x1e: { 1852 uint32_t times; 1853 1854 c->function = i; 1855 c->index = 0; 1856 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1857 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1858 times = c->eax; 1859 1860 for (j = 1; j <= times; ++j) { 1861 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1862 goto full; 1863 } 1864 c = &entries[cpuid_i++]; 1865 c->function = i; 1866 c->index = j; 1867 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1868 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1869 } 1870 break; 1871 } 1872 default: 1873 c->function = i; 1874 c->flags = 0; 1875 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1876 if (!c->eax && !c->ebx && !c->ecx && !c->edx) { 1877 /* 1878 * KVM already returns all zeroes if a CPUID entry is missing, 1879 * so we can omit it and avoid hitting KVM's 80-entry limit. 1880 */ 1881 cpuid_i--; 1882 } 1883 break; 1884 } 1885 } 1886 1887 if (limit >= 0x0a) { 1888 uint32_t eax, edx; 1889 1890 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); 1891 1892 has_architectural_pmu_version = eax & 0xff; 1893 if (has_architectural_pmu_version > 0) { 1894 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8; 1895 1896 /* Shouldn't be more than 32, since that's the number of bits 1897 * available in EBX to tell us _which_ counters are available. 1898 * Play it safe. 1899 */ 1900 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { 1901 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS; 1902 } 1903 1904 if (has_architectural_pmu_version > 1) { 1905 num_architectural_pmu_fixed_counters = edx & 0x1f; 1906 1907 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) { 1908 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS; 1909 } 1910 } 1911 } 1912 } 1913 1914 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); 1915 1916 for (i = 0x80000000; i <= limit; i++) { 1917 j = 0; 1918 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1919 goto full; 1920 } 1921 c = &entries[cpuid_i++]; 1922 1923 switch (i) { 1924 case 0x8000001d: 1925 /* Query for all AMD cache information leaves */ 1926 for (j = 0; ; j++) { 1927 c->function = i; 1928 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1929 c->index = j; 1930 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1931 1932 if (c->eax == 0) { 1933 break; 1934 } 1935 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1936 goto full; 1937 } 1938 c = &entries[cpuid_i++]; 1939 } 1940 break; 1941 default: 1942 c->function = i; 1943 c->flags = 0; 1944 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1945 if (!c->eax && !c->ebx && !c->ecx && !c->edx) { 1946 /* 1947 * KVM already returns all zeroes if a CPUID entry is missing, 1948 * so we can omit it and avoid hitting KVM's 80-entry limit. 1949 */ 1950 cpuid_i--; 1951 } 1952 break; 1953 } 1954 } 1955 1956 /* Call Centaur's CPUID instructions they are supported. */ 1957 if (env->cpuid_xlevel2 > 0) { 1958 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); 1959 1960 for (i = 0xC0000000; i <= limit; i++) { 1961 j = 0; 1962 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1963 goto full; 1964 } 1965 c = &entries[cpuid_i++]; 1966 1967 c->function = i; 1968 c->flags = 0; 1969 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1970 } 1971 } 1972 1973 return cpuid_i; 1974 1975 full: 1976 fprintf(stderr, "cpuid_data is full, no space for " 1977 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); 1978 abort(); 1979 } 1980 1981 int kvm_arch_init_vcpu(CPUState *cs) 1982 { 1983 struct { 1984 struct kvm_cpuid2 cpuid; 1985 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; 1986 } cpuid_data; 1987 /* 1988 * The kernel defines these structs with padding fields so there 1989 * should be no extra padding in our cpuid_data struct. 1990 */ 1991 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) != 1992 sizeof(struct kvm_cpuid2) + 1993 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES); 1994 1995 X86CPU *cpu = X86_CPU(cs); 1996 CPUX86State *env = &cpu->env; 1997 uint32_t cpuid_i; 1998 struct kvm_cpuid_entry2 *c; 1999 uint32_t signature[3]; 2000 int kvm_base = KVM_CPUID_SIGNATURE; 2001 int max_nested_state_len; 2002 int r; 2003 Error *local_err = NULL; 2004 2005 memset(&cpuid_data, 0, sizeof(cpuid_data)); 2006 2007 cpuid_i = 0; 2008 2009 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2); 2010 2011 r = kvm_arch_set_tsc_khz(cs); 2012 if (r < 0) { 2013 return r; 2014 } 2015 2016 /* vcpu's TSC frequency is either specified by user, or following 2017 * the value used by KVM if the former is not present. In the 2018 * latter case, we query it from KVM and record in env->tsc_khz, 2019 * so that vcpu's TSC frequency can be migrated later via this field. 2020 */ 2021 if (!env->tsc_khz) { 2022 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 2023 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : 2024 -ENOTSUP; 2025 if (r > 0) { 2026 env->tsc_khz = r; 2027 } 2028 } 2029 2030 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY; 2031 2032 /* 2033 * kvm_hyperv_expand_features() is called here for the second time in case 2034 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle 2035 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to 2036 * check which Hyper-V enlightenments are supported and which are not, we 2037 * can still proceed and check/expand Hyper-V enlightenments here so legacy 2038 * behavior is preserved. 2039 */ 2040 if (!kvm_hyperv_expand_features(cpu, &local_err)) { 2041 error_report_err(local_err); 2042 return -ENOSYS; 2043 } 2044 2045 if (hyperv_enabled(cpu)) { 2046 r = hyperv_init_vcpu(cpu); 2047 if (r) { 2048 return r; 2049 } 2050 2051 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries); 2052 kvm_base = KVM_CPUID_SIGNATURE_NEXT; 2053 has_msr_hv_hypercall = true; 2054 } 2055 2056 if (cs->kvm_state->xen_version) { 2057 #ifdef CONFIG_XEN_EMU 2058 struct kvm_cpuid_entry2 *xen_max_leaf; 2059 2060 memcpy(signature, "XenVMMXenVMM", 12); 2061 2062 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++]; 2063 c->function = kvm_base + XEN_CPUID_SIGNATURE; 2064 c->eax = kvm_base + XEN_CPUID_TIME; 2065 c->ebx = signature[0]; 2066 c->ecx = signature[1]; 2067 c->edx = signature[2]; 2068 2069 c = &cpuid_data.entries[cpuid_i++]; 2070 c->function = kvm_base + XEN_CPUID_VENDOR; 2071 c->eax = cs->kvm_state->xen_version; 2072 c->ebx = 0; 2073 c->ecx = 0; 2074 c->edx = 0; 2075 2076 c = &cpuid_data.entries[cpuid_i++]; 2077 c->function = kvm_base + XEN_CPUID_HVM_MSR; 2078 /* Number of hypercall-transfer pages */ 2079 c->eax = 1; 2080 /* Hypercall MSR base address */ 2081 if (hyperv_enabled(cpu)) { 2082 c->ebx = XEN_HYPERCALL_MSR_HYPERV; 2083 kvm_xen_init(cs->kvm_state, c->ebx); 2084 } else { 2085 c->ebx = XEN_HYPERCALL_MSR; 2086 } 2087 c->ecx = 0; 2088 c->edx = 0; 2089 2090 c = &cpuid_data.entries[cpuid_i++]; 2091 c->function = kvm_base + XEN_CPUID_TIME; 2092 c->eax = ((!!tsc_is_stable_and_known(env) << 1) | 2093 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2)); 2094 /* default=0 (emulate if necessary) */ 2095 c->ebx = 0; 2096 /* guest tsc frequency */ 2097 c->ecx = env->user_tsc_khz; 2098 /* guest tsc incarnation (migration count) */ 2099 c->edx = 0; 2100 2101 c = &cpuid_data.entries[cpuid_i++]; 2102 c->function = kvm_base + XEN_CPUID_HVM; 2103 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM; 2104 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) { 2105 c->function = kvm_base + XEN_CPUID_HVM; 2106 2107 if (cpu->xen_vapic) { 2108 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT; 2109 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT; 2110 } 2111 2112 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS; 2113 2114 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) { 2115 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT; 2116 c->ebx = cs->cpu_index; 2117 } 2118 2119 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 17)) { 2120 c->eax |= XEN_HVM_CPUID_UPCALL_VECTOR; 2121 } 2122 } 2123 2124 r = kvm_xen_init_vcpu(cs); 2125 if (r) { 2126 return r; 2127 } 2128 2129 kvm_base += 0x100; 2130 #else /* CONFIG_XEN_EMU */ 2131 /* This should never happen as kvm_arch_init() would have died first. */ 2132 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n"); 2133 abort(); 2134 #endif 2135 } else if (cpu->expose_kvm) { 2136 memcpy(signature, "KVMKVMKVM\0\0\0", 12); 2137 c = &cpuid_data.entries[cpuid_i++]; 2138 c->function = KVM_CPUID_SIGNATURE | kvm_base; 2139 c->eax = KVM_CPUID_FEATURES | kvm_base; 2140 c->ebx = signature[0]; 2141 c->ecx = signature[1]; 2142 c->edx = signature[2]; 2143 2144 c = &cpuid_data.entries[cpuid_i++]; 2145 c->function = KVM_CPUID_FEATURES | kvm_base; 2146 c->eax = env->features[FEAT_KVM]; 2147 c->edx = env->features[FEAT_KVM_HINTS]; 2148 } 2149 2150 if (cpu->kvm_pv_enforce_cpuid) { 2151 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1); 2152 if (r < 0) { 2153 fprintf(stderr, 2154 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s", 2155 strerror(-r)); 2156 abort(); 2157 } 2158 } 2159 2160 cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i); 2161 cpuid_data.cpuid.nent = cpuid_i; 2162 2163 if (((env->cpuid_version >> 8)&0xF) >= 6 2164 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 2165 (CPUID_MCE | CPUID_MCA)) { 2166 uint64_t mcg_cap, unsupported_caps; 2167 int banks; 2168 int ret; 2169 2170 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); 2171 if (ret < 0) { 2172 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); 2173 return ret; 2174 } 2175 2176 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) { 2177 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)", 2178 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks); 2179 return -ENOTSUP; 2180 } 2181 2182 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK); 2183 if (unsupported_caps) { 2184 if (unsupported_caps & MCG_LMCE_P) { 2185 error_report("kvm: LMCE not supported"); 2186 return -ENOTSUP; 2187 } 2188 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64, 2189 unsupported_caps); 2190 } 2191 2192 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK; 2193 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap); 2194 if (ret < 0) { 2195 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); 2196 return ret; 2197 } 2198 } 2199 2200 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env); 2201 2202 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); 2203 if (c) { 2204 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) || 2205 !!(c->ecx & CPUID_EXT_SMX); 2206 } 2207 2208 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0); 2209 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) { 2210 has_msr_feature_control = true; 2211 } 2212 2213 if (env->mcg_cap & MCG_LMCE_P) { 2214 has_msr_mcg_ext_ctl = has_msr_feature_control = true; 2215 } 2216 2217 if (!env->user_tsc_khz) { 2218 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && 2219 invtsc_mig_blocker == NULL) { 2220 error_setg(&invtsc_mig_blocker, 2221 "State blocked by non-migratable CPU device" 2222 " (invtsc flag)"); 2223 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err); 2224 if (r < 0) { 2225 error_report_err(local_err); 2226 return r; 2227 } 2228 } 2229 } 2230 2231 if (cpu->vmware_cpuid_freq 2232 /* Guests depend on 0x40000000 to detect this feature, so only expose 2233 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */ 2234 && cpu->expose_kvm 2235 && kvm_base == KVM_CPUID_SIGNATURE 2236 /* TSC clock must be stable and known for this feature. */ 2237 && tsc_is_stable_and_known(env)) { 2238 2239 c = &cpuid_data.entries[cpuid_i++]; 2240 c->function = KVM_CPUID_SIGNATURE | 0x10; 2241 c->eax = env->tsc_khz; 2242 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ 2243 c->ecx = c->edx = 0; 2244 2245 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0); 2246 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10); 2247 } 2248 2249 cpuid_data.cpuid.nent = cpuid_i; 2250 2251 cpuid_data.cpuid.padding = 0; 2252 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); 2253 if (r) { 2254 goto fail; 2255 } 2256 kvm_init_xsave(env); 2257 2258 max_nested_state_len = kvm_max_nested_state_length(); 2259 if (max_nested_state_len > 0) { 2260 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data)); 2261 2262 if (cpu_has_vmx(env) || cpu_has_svm(env)) { 2263 env->nested_state = g_malloc0(max_nested_state_len); 2264 env->nested_state->size = max_nested_state_len; 2265 2266 kvm_init_nested_state(env); 2267 } 2268 } 2269 2270 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE); 2271 2272 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) { 2273 has_msr_tsc_aux = false; 2274 } 2275 2276 kvm_init_msrs(cpu); 2277 2278 return 0; 2279 2280 fail: 2281 migrate_del_blocker(&invtsc_mig_blocker); 2282 2283 return r; 2284 } 2285 2286 int kvm_arch_destroy_vcpu(CPUState *cs) 2287 { 2288 X86CPU *cpu = X86_CPU(cs); 2289 CPUX86State *env = &cpu->env; 2290 2291 g_free(env->xsave_buf); 2292 2293 g_free(cpu->kvm_msr_buf); 2294 cpu->kvm_msr_buf = NULL; 2295 2296 g_free(env->nested_state); 2297 env->nested_state = NULL; 2298 2299 qemu_del_vm_change_state_handler(cpu->vmsentry); 2300 2301 return 0; 2302 } 2303 2304 void kvm_arch_reset_vcpu(X86CPU *cpu) 2305 { 2306 CPUX86State *env = &cpu->env; 2307 2308 env->xcr0 = 1; 2309 if (kvm_irqchip_in_kernel()) { 2310 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : 2311 KVM_MP_STATE_UNINITIALIZED; 2312 } else { 2313 env->mp_state = KVM_MP_STATE_RUNNABLE; 2314 } 2315 2316 /* enabled by default */ 2317 env->poll_control_msr = 1; 2318 2319 kvm_init_nested_state(env); 2320 2321 sev_es_set_reset_vector(CPU(cpu)); 2322 } 2323 2324 void kvm_arch_after_reset_vcpu(X86CPU *cpu) 2325 { 2326 CPUX86State *env = &cpu->env; 2327 int i; 2328 2329 /* 2330 * Reset SynIC after all other devices have been reset to let them remove 2331 * their SINT routes first. 2332 */ 2333 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 2334 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { 2335 env->msr_hv_synic_sint[i] = HV_SINT_MASKED; 2336 } 2337 2338 hyperv_x86_synic_reset(cpu); 2339 } 2340 } 2341 2342 void kvm_arch_do_init_vcpu(X86CPU *cpu) 2343 { 2344 CPUX86State *env = &cpu->env; 2345 2346 /* APs get directly into wait-for-SIPI state. */ 2347 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) { 2348 env->mp_state = KVM_MP_STATE_INIT_RECEIVED; 2349 } 2350 } 2351 2352 static int kvm_get_supported_feature_msrs(KVMState *s) 2353 { 2354 int ret = 0; 2355 2356 if (kvm_feature_msrs != NULL) { 2357 return 0; 2358 } 2359 2360 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) { 2361 return 0; 2362 } 2363 2364 struct kvm_msr_list msr_list; 2365 2366 msr_list.nmsrs = 0; 2367 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list); 2368 if (ret < 0 && ret != -E2BIG) { 2369 error_report("Fetch KVM feature MSR list failed: %s", 2370 strerror(-ret)); 2371 return ret; 2372 } 2373 2374 assert(msr_list.nmsrs > 0); 2375 kvm_feature_msrs = g_malloc0(sizeof(msr_list) + 2376 msr_list.nmsrs * sizeof(msr_list.indices[0])); 2377 2378 kvm_feature_msrs->nmsrs = msr_list.nmsrs; 2379 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs); 2380 2381 if (ret < 0) { 2382 error_report("Fetch KVM feature MSR list failed: %s", 2383 strerror(-ret)); 2384 g_free(kvm_feature_msrs); 2385 kvm_feature_msrs = NULL; 2386 return ret; 2387 } 2388 2389 return 0; 2390 } 2391 2392 static int kvm_get_supported_msrs(KVMState *s) 2393 { 2394 int ret = 0; 2395 struct kvm_msr_list msr_list, *kvm_msr_list; 2396 2397 /* 2398 * Obtain MSR list from KVM. These are the MSRs that we must 2399 * save/restore. 2400 */ 2401 msr_list.nmsrs = 0; 2402 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); 2403 if (ret < 0 && ret != -E2BIG) { 2404 return ret; 2405 } 2406 /* 2407 * Old kernel modules had a bug and could write beyond the provided 2408 * memory. Allocate at least a safe amount of 1K. 2409 */ 2410 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + 2411 msr_list.nmsrs * 2412 sizeof(msr_list.indices[0]))); 2413 2414 kvm_msr_list->nmsrs = msr_list.nmsrs; 2415 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); 2416 if (ret >= 0) { 2417 int i; 2418 2419 for (i = 0; i < kvm_msr_list->nmsrs; i++) { 2420 switch (kvm_msr_list->indices[i]) { 2421 case MSR_STAR: 2422 has_msr_star = true; 2423 break; 2424 case MSR_VM_HSAVE_PA: 2425 has_msr_hsave_pa = true; 2426 break; 2427 case MSR_TSC_AUX: 2428 has_msr_tsc_aux = true; 2429 break; 2430 case MSR_TSC_ADJUST: 2431 has_msr_tsc_adjust = true; 2432 break; 2433 case MSR_IA32_TSCDEADLINE: 2434 has_msr_tsc_deadline = true; 2435 break; 2436 case MSR_IA32_SMBASE: 2437 has_msr_smbase = true; 2438 break; 2439 case MSR_SMI_COUNT: 2440 has_msr_smi_count = true; 2441 break; 2442 case MSR_IA32_MISC_ENABLE: 2443 has_msr_misc_enable = true; 2444 break; 2445 case MSR_IA32_BNDCFGS: 2446 has_msr_bndcfgs = true; 2447 break; 2448 case MSR_IA32_XSS: 2449 has_msr_xss = true; 2450 break; 2451 case MSR_IA32_UMWAIT_CONTROL: 2452 has_msr_umwait = true; 2453 break; 2454 case HV_X64_MSR_CRASH_CTL: 2455 has_msr_hv_crash = true; 2456 break; 2457 case HV_X64_MSR_RESET: 2458 has_msr_hv_reset = true; 2459 break; 2460 case HV_X64_MSR_VP_INDEX: 2461 has_msr_hv_vpindex = true; 2462 break; 2463 case HV_X64_MSR_VP_RUNTIME: 2464 has_msr_hv_runtime = true; 2465 break; 2466 case HV_X64_MSR_SCONTROL: 2467 has_msr_hv_synic = true; 2468 break; 2469 case HV_X64_MSR_STIMER0_CONFIG: 2470 has_msr_hv_stimer = true; 2471 break; 2472 case HV_X64_MSR_TSC_FREQUENCY: 2473 has_msr_hv_frequencies = true; 2474 break; 2475 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2476 has_msr_hv_reenlightenment = true; 2477 break; 2478 case HV_X64_MSR_SYNDBG_OPTIONS: 2479 has_msr_hv_syndbg_options = true; 2480 break; 2481 case MSR_IA32_SPEC_CTRL: 2482 has_msr_spec_ctrl = true; 2483 break; 2484 case MSR_AMD64_TSC_RATIO: 2485 has_tsc_scale_msr = true; 2486 break; 2487 case MSR_IA32_TSX_CTRL: 2488 has_msr_tsx_ctrl = true; 2489 break; 2490 case MSR_VIRT_SSBD: 2491 has_msr_virt_ssbd = true; 2492 break; 2493 case MSR_IA32_ARCH_CAPABILITIES: 2494 has_msr_arch_capabs = true; 2495 break; 2496 case MSR_IA32_CORE_CAPABILITY: 2497 has_msr_core_capabs = true; 2498 break; 2499 case MSR_IA32_PERF_CAPABILITIES: 2500 has_msr_perf_capabs = true; 2501 break; 2502 case MSR_IA32_VMX_VMFUNC: 2503 has_msr_vmx_vmfunc = true; 2504 break; 2505 case MSR_IA32_UCODE_REV: 2506 has_msr_ucode_rev = true; 2507 break; 2508 case MSR_IA32_VMX_PROCBASED_CTLS2: 2509 has_msr_vmx_procbased_ctls2 = true; 2510 break; 2511 case MSR_IA32_PKRS: 2512 has_msr_pkrs = true; 2513 break; 2514 } 2515 } 2516 } 2517 2518 g_free(kvm_msr_list); 2519 2520 return ret; 2521 } 2522 2523 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu, uint32_t msr, 2524 uint64_t *val) 2525 { 2526 CPUState *cs = CPU(cpu); 2527 2528 *val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ 2529 *val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ 2530 2531 return true; 2532 } 2533 2534 static Notifier smram_machine_done; 2535 static KVMMemoryListener smram_listener; 2536 static AddressSpace smram_address_space; 2537 static MemoryRegion smram_as_root; 2538 static MemoryRegion smram_as_mem; 2539 2540 static void register_smram_listener(Notifier *n, void *unused) 2541 { 2542 MemoryRegion *smram = 2543 (MemoryRegion *) object_resolve_path("/machine/smram", NULL); 2544 2545 /* Outer container... */ 2546 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull); 2547 memory_region_set_enabled(&smram_as_root, true); 2548 2549 /* ... with two regions inside: normal system memory with low 2550 * priority, and... 2551 */ 2552 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram", 2553 get_system_memory(), 0, ~0ull); 2554 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0); 2555 memory_region_set_enabled(&smram_as_mem, true); 2556 2557 if (smram) { 2558 /* ... SMRAM with higher priority */ 2559 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10); 2560 memory_region_set_enabled(smram, true); 2561 } 2562 2563 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM"); 2564 kvm_memory_listener_register(kvm_state, &smram_listener, 2565 &smram_address_space, 1, "kvm-smram"); 2566 } 2567 2568 int kvm_arch_get_default_type(MachineState *ms) 2569 { 2570 return 0; 2571 } 2572 2573 int kvm_arch_init(MachineState *ms, KVMState *s) 2574 { 2575 uint64_t identity_base = 0xfffbc000; 2576 uint64_t shadow_mem; 2577 int ret; 2578 struct utsname utsname; 2579 Error *local_err = NULL; 2580 2581 /* 2582 * Initialize SEV context, if required 2583 * 2584 * If no memory encryption is requested (ms->cgs == NULL) this is 2585 * a no-op. 2586 * 2587 * It's also a no-op if a non-SEV confidential guest support 2588 * mechanism is selected. SEV is the only mechanism available to 2589 * select on x86 at present, so this doesn't arise, but if new 2590 * mechanisms are supported in future (e.g. TDX), they'll need 2591 * their own initialization either here or elsewhere. 2592 */ 2593 if (ms->cgs) { 2594 ret = confidential_guest_kvm_init(ms->cgs, &local_err); 2595 if (ret < 0) { 2596 error_report_err(local_err); 2597 return ret; 2598 } 2599 } 2600 2601 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS); 2602 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0; 2603 2604 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX); 2605 2606 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD); 2607 if (has_exception_payload) { 2608 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true); 2609 if (ret < 0) { 2610 error_report("kvm: Failed to enable exception payload cap: %s", 2611 strerror(-ret)); 2612 return ret; 2613 } 2614 } 2615 2616 has_triple_fault_event = kvm_check_extension(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT); 2617 if (has_triple_fault_event) { 2618 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true); 2619 if (ret < 0) { 2620 error_report("kvm: Failed to enable triple fault event cap: %s", 2621 strerror(-ret)); 2622 return ret; 2623 } 2624 } 2625 2626 if (s->xen_version) { 2627 #ifdef CONFIG_XEN_EMU 2628 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) { 2629 error_report("kvm: Xen support only available in PC machine"); 2630 return -ENOTSUP; 2631 } 2632 /* hyperv_enabled() doesn't work yet. */ 2633 uint32_t msr = XEN_HYPERCALL_MSR; 2634 ret = kvm_xen_init(s, msr); 2635 if (ret < 0) { 2636 return ret; 2637 } 2638 #else 2639 error_report("kvm: Xen support not enabled in qemu"); 2640 return -ENOTSUP; 2641 #endif 2642 } 2643 2644 ret = kvm_get_supported_msrs(s); 2645 if (ret < 0) { 2646 return ret; 2647 } 2648 2649 kvm_get_supported_feature_msrs(s); 2650 2651 uname(&utsname); 2652 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; 2653 2654 /* 2655 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. 2656 * In order to use vm86 mode, an EPT identity map and a TSS are needed. 2657 * Since these must be part of guest physical memory, we need to allocate 2658 * them, both by setting their start addresses in the kernel and by 2659 * creating a corresponding e820 entry. We need 4 pages before the BIOS, 2660 * so this value allows up to 16M BIOSes. 2661 */ 2662 identity_base = 0xfeffc000; 2663 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); 2664 if (ret < 0) { 2665 return ret; 2666 } 2667 2668 /* Set TSS base one page after EPT identity map. */ 2669 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); 2670 if (ret < 0) { 2671 return ret; 2672 } 2673 2674 /* Tell fw_cfg to notify the BIOS to reserve the range. */ 2675 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); 2676 if (ret < 0) { 2677 fprintf(stderr, "e820_add_entry() table is full\n"); 2678 return ret; 2679 } 2680 2681 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort); 2682 if (shadow_mem != -1) { 2683 shadow_mem /= 4096; 2684 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); 2685 if (ret < 0) { 2686 return ret; 2687 } 2688 } 2689 2690 if (kvm_check_extension(s, KVM_CAP_X86_SMM) && 2691 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) && 2692 x86_machine_is_smm_enabled(X86_MACHINE(ms))) { 2693 smram_machine_done.notify = register_smram_listener; 2694 qemu_add_machine_init_done_notifier(&smram_machine_done); 2695 } 2696 2697 if (enable_cpu_pm) { 2698 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS); 2699 /* Work around for kernel header with a typo. TODO: fix header and drop. */ 2700 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT) 2701 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL 2702 #endif 2703 if (disable_exits) { 2704 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT | 2705 KVM_X86_DISABLE_EXITS_HLT | 2706 KVM_X86_DISABLE_EXITS_PAUSE | 2707 KVM_X86_DISABLE_EXITS_CSTATE); 2708 } 2709 2710 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0, 2711 disable_exits); 2712 if (ret < 0) { 2713 error_report("kvm: guest stopping CPU not supported: %s", 2714 strerror(-ret)); 2715 } 2716 } 2717 2718 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) { 2719 X86MachineState *x86ms = X86_MACHINE(ms); 2720 2721 if (x86ms->bus_lock_ratelimit > 0) { 2722 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT); 2723 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) { 2724 error_report("kvm: bus lock detection unsupported"); 2725 return -ENOTSUP; 2726 } 2727 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0, 2728 KVM_BUS_LOCK_DETECTION_EXIT); 2729 if (ret < 0) { 2730 error_report("kvm: Failed to enable bus lock detection cap: %s", 2731 strerror(-ret)); 2732 return ret; 2733 } 2734 ratelimit_init(&bus_lock_ratelimit_ctrl); 2735 ratelimit_set_speed(&bus_lock_ratelimit_ctrl, 2736 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME); 2737 } 2738 } 2739 2740 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE && 2741 kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) { 2742 uint64_t notify_window_flags = 2743 ((uint64_t)s->notify_window << 32) | 2744 KVM_X86_NOTIFY_VMEXIT_ENABLED | 2745 KVM_X86_NOTIFY_VMEXIT_USER; 2746 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0, 2747 notify_window_flags); 2748 if (ret < 0) { 2749 error_report("kvm: Failed to enable notify vmexit cap: %s", 2750 strerror(-ret)); 2751 return ret; 2752 } 2753 } 2754 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) { 2755 bool r; 2756 2757 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0, 2758 KVM_MSR_EXIT_REASON_FILTER); 2759 if (ret) { 2760 error_report("Could not enable user space MSRs: %s", 2761 strerror(-ret)); 2762 exit(1); 2763 } 2764 2765 r = kvm_filter_msr(s, MSR_CORE_THREAD_COUNT, 2766 kvm_rdmsr_core_thread_count, NULL); 2767 if (!r) { 2768 error_report("Could not install MSR_CORE_THREAD_COUNT handler: %s", 2769 strerror(-ret)); 2770 exit(1); 2771 } 2772 } 2773 2774 return 0; 2775 } 2776 2777 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) 2778 { 2779 lhs->selector = rhs->selector; 2780 lhs->base = rhs->base; 2781 lhs->limit = rhs->limit; 2782 lhs->type = 3; 2783 lhs->present = 1; 2784 lhs->dpl = 3; 2785 lhs->db = 0; 2786 lhs->s = 1; 2787 lhs->l = 0; 2788 lhs->g = 0; 2789 lhs->avl = 0; 2790 lhs->unusable = 0; 2791 } 2792 2793 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) 2794 { 2795 unsigned flags = rhs->flags; 2796 lhs->selector = rhs->selector; 2797 lhs->base = rhs->base; 2798 lhs->limit = rhs->limit; 2799 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; 2800 lhs->present = (flags & DESC_P_MASK) != 0; 2801 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; 2802 lhs->db = (flags >> DESC_B_SHIFT) & 1; 2803 lhs->s = (flags & DESC_S_MASK) != 0; 2804 lhs->l = (flags >> DESC_L_SHIFT) & 1; 2805 lhs->g = (flags & DESC_G_MASK) != 0; 2806 lhs->avl = (flags & DESC_AVL_MASK) != 0; 2807 lhs->unusable = !lhs->present; 2808 lhs->padding = 0; 2809 } 2810 2811 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) 2812 { 2813 lhs->selector = rhs->selector; 2814 lhs->base = rhs->base; 2815 lhs->limit = rhs->limit; 2816 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | 2817 ((rhs->present && !rhs->unusable) * DESC_P_MASK) | 2818 (rhs->dpl << DESC_DPL_SHIFT) | 2819 (rhs->db << DESC_B_SHIFT) | 2820 (rhs->s * DESC_S_MASK) | 2821 (rhs->l << DESC_L_SHIFT) | 2822 (rhs->g * DESC_G_MASK) | 2823 (rhs->avl * DESC_AVL_MASK); 2824 } 2825 2826 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) 2827 { 2828 if (set) { 2829 *kvm_reg = *qemu_reg; 2830 } else { 2831 *qemu_reg = *kvm_reg; 2832 } 2833 } 2834 2835 static int kvm_getput_regs(X86CPU *cpu, int set) 2836 { 2837 CPUX86State *env = &cpu->env; 2838 struct kvm_regs regs; 2839 int ret = 0; 2840 2841 if (!set) { 2842 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); 2843 if (ret < 0) { 2844 return ret; 2845 } 2846 } 2847 2848 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); 2849 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); 2850 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); 2851 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); 2852 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); 2853 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); 2854 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); 2855 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); 2856 #ifdef TARGET_X86_64 2857 kvm_getput_reg(®s.r8, &env->regs[8], set); 2858 kvm_getput_reg(®s.r9, &env->regs[9], set); 2859 kvm_getput_reg(®s.r10, &env->regs[10], set); 2860 kvm_getput_reg(®s.r11, &env->regs[11], set); 2861 kvm_getput_reg(®s.r12, &env->regs[12], set); 2862 kvm_getput_reg(®s.r13, &env->regs[13], set); 2863 kvm_getput_reg(®s.r14, &env->regs[14], set); 2864 kvm_getput_reg(®s.r15, &env->regs[15], set); 2865 #endif 2866 2867 kvm_getput_reg(®s.rflags, &env->eflags, set); 2868 kvm_getput_reg(®s.rip, &env->eip, set); 2869 2870 if (set) { 2871 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); 2872 } 2873 2874 return ret; 2875 } 2876 2877 static int kvm_put_xsave(X86CPU *cpu) 2878 { 2879 CPUX86State *env = &cpu->env; 2880 void *xsave = env->xsave_buf; 2881 2882 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len); 2883 2884 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); 2885 } 2886 2887 static int kvm_put_xcrs(X86CPU *cpu) 2888 { 2889 CPUX86State *env = &cpu->env; 2890 struct kvm_xcrs xcrs = {}; 2891 2892 if (!has_xcrs) { 2893 return 0; 2894 } 2895 2896 xcrs.nr_xcrs = 1; 2897 xcrs.flags = 0; 2898 xcrs.xcrs[0].xcr = 0; 2899 xcrs.xcrs[0].value = env->xcr0; 2900 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); 2901 } 2902 2903 static int kvm_put_sregs(X86CPU *cpu) 2904 { 2905 CPUX86State *env = &cpu->env; 2906 struct kvm_sregs sregs; 2907 2908 /* 2909 * The interrupt_bitmap is ignored because KVM_SET_SREGS is 2910 * always followed by KVM_SET_VCPU_EVENTS. 2911 */ 2912 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); 2913 2914 if ((env->eflags & VM_MASK)) { 2915 set_v8086_seg(&sregs.cs, &env->segs[R_CS]); 2916 set_v8086_seg(&sregs.ds, &env->segs[R_DS]); 2917 set_v8086_seg(&sregs.es, &env->segs[R_ES]); 2918 set_v8086_seg(&sregs.fs, &env->segs[R_FS]); 2919 set_v8086_seg(&sregs.gs, &env->segs[R_GS]); 2920 set_v8086_seg(&sregs.ss, &env->segs[R_SS]); 2921 } else { 2922 set_seg(&sregs.cs, &env->segs[R_CS]); 2923 set_seg(&sregs.ds, &env->segs[R_DS]); 2924 set_seg(&sregs.es, &env->segs[R_ES]); 2925 set_seg(&sregs.fs, &env->segs[R_FS]); 2926 set_seg(&sregs.gs, &env->segs[R_GS]); 2927 set_seg(&sregs.ss, &env->segs[R_SS]); 2928 } 2929 2930 set_seg(&sregs.tr, &env->tr); 2931 set_seg(&sregs.ldt, &env->ldt); 2932 2933 sregs.idt.limit = env->idt.limit; 2934 sregs.idt.base = env->idt.base; 2935 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); 2936 sregs.gdt.limit = env->gdt.limit; 2937 sregs.gdt.base = env->gdt.base; 2938 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); 2939 2940 sregs.cr0 = env->cr[0]; 2941 sregs.cr2 = env->cr[2]; 2942 sregs.cr3 = env->cr[3]; 2943 sregs.cr4 = env->cr[4]; 2944 2945 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); 2946 sregs.apic_base = cpu_get_apic_base(cpu->apic_state); 2947 2948 sregs.efer = env->efer; 2949 2950 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 2951 } 2952 2953 static int kvm_put_sregs2(X86CPU *cpu) 2954 { 2955 CPUX86State *env = &cpu->env; 2956 struct kvm_sregs2 sregs; 2957 int i; 2958 2959 sregs.flags = 0; 2960 2961 if ((env->eflags & VM_MASK)) { 2962 set_v8086_seg(&sregs.cs, &env->segs[R_CS]); 2963 set_v8086_seg(&sregs.ds, &env->segs[R_DS]); 2964 set_v8086_seg(&sregs.es, &env->segs[R_ES]); 2965 set_v8086_seg(&sregs.fs, &env->segs[R_FS]); 2966 set_v8086_seg(&sregs.gs, &env->segs[R_GS]); 2967 set_v8086_seg(&sregs.ss, &env->segs[R_SS]); 2968 } else { 2969 set_seg(&sregs.cs, &env->segs[R_CS]); 2970 set_seg(&sregs.ds, &env->segs[R_DS]); 2971 set_seg(&sregs.es, &env->segs[R_ES]); 2972 set_seg(&sregs.fs, &env->segs[R_FS]); 2973 set_seg(&sregs.gs, &env->segs[R_GS]); 2974 set_seg(&sregs.ss, &env->segs[R_SS]); 2975 } 2976 2977 set_seg(&sregs.tr, &env->tr); 2978 set_seg(&sregs.ldt, &env->ldt); 2979 2980 sregs.idt.limit = env->idt.limit; 2981 sregs.idt.base = env->idt.base; 2982 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); 2983 sregs.gdt.limit = env->gdt.limit; 2984 sregs.gdt.base = env->gdt.base; 2985 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); 2986 2987 sregs.cr0 = env->cr[0]; 2988 sregs.cr2 = env->cr[2]; 2989 sregs.cr3 = env->cr[3]; 2990 sregs.cr4 = env->cr[4]; 2991 2992 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); 2993 sregs.apic_base = cpu_get_apic_base(cpu->apic_state); 2994 2995 sregs.efer = env->efer; 2996 2997 if (env->pdptrs_valid) { 2998 for (i = 0; i < 4; i++) { 2999 sregs.pdptrs[i] = env->pdptrs[i]; 3000 } 3001 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 3002 } 3003 3004 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs); 3005 } 3006 3007 3008 static void kvm_msr_buf_reset(X86CPU *cpu) 3009 { 3010 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE); 3011 } 3012 3013 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value) 3014 { 3015 struct kvm_msrs *msrs = cpu->kvm_msr_buf; 3016 void *limit = ((void *)msrs) + MSR_BUF_SIZE; 3017 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs]; 3018 3019 assert((void *)(entry + 1) <= limit); 3020 3021 entry->index = index; 3022 entry->reserved = 0; 3023 entry->data = value; 3024 msrs->nmsrs++; 3025 } 3026 3027 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value) 3028 { 3029 kvm_msr_buf_reset(cpu); 3030 kvm_msr_entry_add(cpu, index, value); 3031 3032 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); 3033 } 3034 3035 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value) 3036 { 3037 int ret; 3038 struct { 3039 struct kvm_msrs info; 3040 struct kvm_msr_entry entries[1]; 3041 } msr_data = { 3042 .info.nmsrs = 1, 3043 .entries[0].index = index, 3044 }; 3045 3046 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); 3047 if (ret < 0) { 3048 return ret; 3049 } 3050 assert(ret == 1); 3051 *value = msr_data.entries[0].data; 3052 return ret; 3053 } 3054 void kvm_put_apicbase(X86CPU *cpu, uint64_t value) 3055 { 3056 int ret; 3057 3058 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value); 3059 assert(ret == 1); 3060 } 3061 3062 static int kvm_put_tscdeadline_msr(X86CPU *cpu) 3063 { 3064 CPUX86State *env = &cpu->env; 3065 int ret; 3066 3067 if (!has_msr_tsc_deadline) { 3068 return 0; 3069 } 3070 3071 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline); 3072 if (ret < 0) { 3073 return ret; 3074 } 3075 3076 assert(ret == 1); 3077 return 0; 3078 } 3079 3080 /* 3081 * Provide a separate write service for the feature control MSR in order to 3082 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done 3083 * before writing any other state because forcibly leaving nested mode 3084 * invalidates the VCPU state. 3085 */ 3086 static int kvm_put_msr_feature_control(X86CPU *cpu) 3087 { 3088 int ret; 3089 3090 if (!has_msr_feature_control) { 3091 return 0; 3092 } 3093 3094 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL, 3095 cpu->env.msr_ia32_feature_control); 3096 if (ret < 0) { 3097 return ret; 3098 } 3099 3100 assert(ret == 1); 3101 return 0; 3102 } 3103 3104 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features) 3105 { 3106 uint32_t default1, can_be_one, can_be_zero; 3107 uint32_t must_be_one; 3108 3109 switch (index) { 3110 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 3111 default1 = 0x00000016; 3112 break; 3113 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 3114 default1 = 0x0401e172; 3115 break; 3116 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 3117 default1 = 0x000011ff; 3118 break; 3119 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 3120 default1 = 0x00036dff; 3121 break; 3122 case MSR_IA32_VMX_PROCBASED_CTLS2: 3123 default1 = 0; 3124 break; 3125 default: 3126 abort(); 3127 } 3128 3129 /* If a feature bit is set, the control can be either set or clear. 3130 * Otherwise the value is limited to either 0 or 1 by default1. 3131 */ 3132 can_be_one = features | default1; 3133 can_be_zero = features | ~default1; 3134 must_be_one = ~can_be_zero; 3135 3136 /* 3137 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one). 3138 * Bit 32:63 -> 1 if the control bit can be one. 3139 */ 3140 return must_be_one | (((uint64_t)can_be_one) << 32); 3141 } 3142 3143 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) 3144 { 3145 uint64_t kvm_vmx_basic = 3146 kvm_arch_get_supported_msr_feature(kvm_state, 3147 MSR_IA32_VMX_BASIC); 3148 3149 if (!kvm_vmx_basic) { 3150 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0), 3151 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail. 3152 */ 3153 return; 3154 } 3155 3156 uint64_t kvm_vmx_misc = 3157 kvm_arch_get_supported_msr_feature(kvm_state, 3158 MSR_IA32_VMX_MISC); 3159 uint64_t kvm_vmx_ept_vpid = 3160 kvm_arch_get_supported_msr_feature(kvm_state, 3161 MSR_IA32_VMX_EPT_VPID_CAP); 3162 3163 /* 3164 * If the guest is 64-bit, a value of 1 is allowed for the host address 3165 * space size vmexit control. 3166 */ 3167 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM 3168 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0; 3169 3170 /* 3171 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should 3172 * not change them for backwards compatibility. 3173 */ 3174 uint64_t fixed_vmx_basic = kvm_vmx_basic & 3175 (MSR_VMX_BASIC_VMCS_REVISION_MASK | 3176 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK | 3177 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK); 3178 3179 /* 3180 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can 3181 * change in the future but are always zero for now, clear them to be 3182 * future proof. Bits 32-63 in theory could change, though KVM does 3183 * not support dual-monitor treatment and probably never will; mask 3184 * them out as well. 3185 */ 3186 uint64_t fixed_vmx_misc = kvm_vmx_misc & 3187 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK | 3188 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK); 3189 3190 /* 3191 * EPT memory types should not change either, so we do not bother 3192 * adding features for them. 3193 */ 3194 uint64_t fixed_vmx_ept_mask = 3195 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ? 3196 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0); 3197 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask; 3198 3199 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 3200 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 3201 f[FEAT_VMX_PROCBASED_CTLS])); 3202 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS, 3203 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS, 3204 f[FEAT_VMX_PINBASED_CTLS])); 3205 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS, 3206 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS, 3207 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit); 3208 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS, 3209 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS, 3210 f[FEAT_VMX_ENTRY_CTLS])); 3211 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2, 3212 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2, 3213 f[FEAT_VMX_SECONDARY_CTLS])); 3214 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP, 3215 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid); 3216 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC, 3217 f[FEAT_VMX_BASIC] | fixed_vmx_basic); 3218 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC, 3219 f[FEAT_VMX_MISC] | fixed_vmx_misc); 3220 if (has_msr_vmx_vmfunc) { 3221 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]); 3222 } 3223 3224 /* 3225 * Just to be safe, write these with constant values. The CRn_FIXED1 3226 * MSRs are generated by KVM based on the vCPU's CPUID. 3227 */ 3228 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0, 3229 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK); 3230 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0, 3231 CR4_VMXE_MASK); 3232 3233 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) { 3234 /* TSC multiplier (0x2032). */ 3235 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32); 3236 } else { 3237 /* Preemption timer (0x482E). */ 3238 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E); 3239 } 3240 } 3241 3242 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f) 3243 { 3244 uint64_t kvm_perf_cap = 3245 kvm_arch_get_supported_msr_feature(kvm_state, 3246 MSR_IA32_PERF_CAPABILITIES); 3247 3248 if (kvm_perf_cap) { 3249 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, 3250 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]); 3251 } 3252 } 3253 3254 static int kvm_buf_set_msrs(X86CPU *cpu) 3255 { 3256 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); 3257 if (ret < 0) { 3258 return ret; 3259 } 3260 3261 if (ret < cpu->kvm_msr_buf->nmsrs) { 3262 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; 3263 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64, 3264 (uint32_t)e->index, (uint64_t)e->data); 3265 } 3266 3267 assert(ret == cpu->kvm_msr_buf->nmsrs); 3268 return 0; 3269 } 3270 3271 static void kvm_init_msrs(X86CPU *cpu) 3272 { 3273 CPUX86State *env = &cpu->env; 3274 3275 kvm_msr_buf_reset(cpu); 3276 if (has_msr_arch_capabs) { 3277 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, 3278 env->features[FEAT_ARCH_CAPABILITIES]); 3279 } 3280 3281 if (has_msr_core_capabs) { 3282 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, 3283 env->features[FEAT_CORE_CAPABILITY]); 3284 } 3285 3286 if (has_msr_perf_capabs && cpu->enable_pmu) { 3287 kvm_msr_entry_add_perf(cpu, env->features); 3288 } 3289 3290 if (has_msr_ucode_rev) { 3291 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); 3292 } 3293 3294 /* 3295 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but 3296 * all kernels with MSR features should have them. 3297 */ 3298 if (kvm_feature_msrs && cpu_has_vmx(env)) { 3299 kvm_msr_entry_add_vmx(cpu, env->features); 3300 } 3301 3302 assert(kvm_buf_set_msrs(cpu) == 0); 3303 } 3304 3305 static int kvm_put_msrs(X86CPU *cpu, int level) 3306 { 3307 CPUX86State *env = &cpu->env; 3308 int i; 3309 3310 kvm_msr_buf_reset(cpu); 3311 3312 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs); 3313 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); 3314 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); 3315 kvm_msr_entry_add(cpu, MSR_PAT, env->pat); 3316 if (has_msr_star) { 3317 kvm_msr_entry_add(cpu, MSR_STAR, env->star); 3318 } 3319 if (has_msr_hsave_pa) { 3320 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave); 3321 } 3322 if (has_msr_tsc_aux) { 3323 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux); 3324 } 3325 if (has_msr_tsc_adjust) { 3326 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust); 3327 } 3328 if (has_msr_misc_enable) { 3329 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 3330 env->msr_ia32_misc_enable); 3331 } 3332 if (has_msr_smbase) { 3333 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase); 3334 } 3335 if (has_msr_smi_count) { 3336 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count); 3337 } 3338 if (has_msr_pkrs) { 3339 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs); 3340 } 3341 if (has_msr_bndcfgs) { 3342 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs); 3343 } 3344 if (has_msr_xss) { 3345 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); 3346 } 3347 if (has_msr_umwait) { 3348 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait); 3349 } 3350 if (has_msr_spec_ctrl) { 3351 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); 3352 } 3353 if (has_tsc_scale_msr) { 3354 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr); 3355 } 3356 3357 if (has_msr_tsx_ctrl) { 3358 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl); 3359 } 3360 if (has_msr_virt_ssbd) { 3361 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); 3362 } 3363 3364 #ifdef TARGET_X86_64 3365 if (lm_capable_kernel) { 3366 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); 3367 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase); 3368 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask); 3369 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); 3370 } 3371 #endif 3372 3373 /* 3374 * The following MSRs have side effects on the guest or are too heavy 3375 * for normal writeback. Limit them to reset or full state updates. 3376 */ 3377 if (level >= KVM_PUT_RESET_STATE) { 3378 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc); 3379 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr); 3380 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr); 3381 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { 3382 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr); 3383 } 3384 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) { 3385 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr); 3386 } 3387 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) { 3388 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr); 3389 } 3390 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { 3391 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr); 3392 } 3393 3394 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { 3395 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr); 3396 } 3397 3398 if (has_architectural_pmu_version > 0) { 3399 if (has_architectural_pmu_version > 1) { 3400 /* Stop the counter. */ 3401 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); 3402 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); 3403 } 3404 3405 /* Set the counter values. */ 3406 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { 3407 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 3408 env->msr_fixed_counters[i]); 3409 } 3410 for (i = 0; i < num_architectural_pmu_gp_counters; i++) { 3411 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 3412 env->msr_gp_counters[i]); 3413 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 3414 env->msr_gp_evtsel[i]); 3415 } 3416 if (has_architectural_pmu_version > 1) { 3417 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 3418 env->msr_global_status); 3419 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 3420 env->msr_global_ovf_ctrl); 3421 3422 /* Now start the PMU. */ 3423 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 3424 env->msr_fixed_ctr_ctrl); 3425 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 3426 env->msr_global_ctrl); 3427 } 3428 } 3429 /* 3430 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add, 3431 * only sync them to KVM on the first cpu 3432 */ 3433 if (current_cpu == first_cpu) { 3434 if (has_msr_hv_hypercall) { 3435 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 3436 env->msr_hv_guest_os_id); 3437 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 3438 env->msr_hv_hypercall); 3439 } 3440 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { 3441 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 3442 env->msr_hv_tsc); 3443 } 3444 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { 3445 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 3446 env->msr_hv_reenlightenment_control); 3447 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 3448 env->msr_hv_tsc_emulation_control); 3449 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 3450 env->msr_hv_tsc_emulation_status); 3451 } 3452 #ifdef CONFIG_SYNDBG 3453 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) && 3454 has_msr_hv_syndbg_options) { 3455 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 3456 hyperv_syndbg_query_options()); 3457 } 3458 #endif 3459 } 3460 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { 3461 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 3462 env->msr_hv_vapic); 3463 } 3464 if (has_msr_hv_crash) { 3465 int j; 3466 3467 for (j = 0; j < HV_CRASH_PARAMS; j++) 3468 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 3469 env->msr_hv_crash_params[j]); 3470 3471 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY); 3472 } 3473 if (has_msr_hv_runtime) { 3474 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime); 3475 } 3476 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) 3477 && hv_vpindex_settable) { 3478 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX, 3479 hyperv_vp_index(CPU(cpu))); 3480 } 3481 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 3482 int j; 3483 3484 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION); 3485 3486 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 3487 env->msr_hv_synic_control); 3488 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 3489 env->msr_hv_synic_evt_page); 3490 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 3491 env->msr_hv_synic_msg_page); 3492 3493 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) { 3494 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j, 3495 env->msr_hv_synic_sint[j]); 3496 } 3497 } 3498 if (has_msr_hv_stimer) { 3499 int j; 3500 3501 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) { 3502 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2, 3503 env->msr_hv_stimer_config[j]); 3504 } 3505 3506 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) { 3507 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2, 3508 env->msr_hv_stimer_count[j]); 3509 } 3510 } 3511 if (env->features[FEAT_1_EDX] & CPUID_MTRR) { 3512 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits); 3513 3514 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype); 3515 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]); 3516 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]); 3517 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]); 3518 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]); 3519 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]); 3520 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]); 3521 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]); 3522 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]); 3523 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]); 3524 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]); 3525 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]); 3526 for (i = 0; i < MSR_MTRRcap_VCNT; i++) { 3527 /* The CPU GPs if we write to a bit above the physical limit of 3528 * the host CPU (and KVM emulates that) 3529 */ 3530 uint64_t mask = env->mtrr_var[i].mask; 3531 mask &= phys_mask; 3532 3533 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 3534 env->mtrr_var[i].base); 3535 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask); 3536 } 3537 } 3538 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { 3539 int addr_num = kvm_arch_get_supported_cpuid(kvm_state, 3540 0x14, 1, R_EAX) & 0x7; 3541 3542 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 3543 env->msr_rtit_ctrl); 3544 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 3545 env->msr_rtit_status); 3546 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 3547 env->msr_rtit_output_base); 3548 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 3549 env->msr_rtit_output_mask); 3550 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 3551 env->msr_rtit_cr3_match); 3552 for (i = 0; i < addr_num; i++) { 3553 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 3554 env->msr_rtit_addrs[i]); 3555 } 3556 } 3557 3558 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) { 3559 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 3560 env->msr_ia32_sgxlepubkeyhash[0]); 3561 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 3562 env->msr_ia32_sgxlepubkeyhash[1]); 3563 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 3564 env->msr_ia32_sgxlepubkeyhash[2]); 3565 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 3566 env->msr_ia32_sgxlepubkeyhash[3]); 3567 } 3568 3569 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { 3570 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 3571 env->msr_xfd); 3572 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 3573 env->msr_xfd_err); 3574 } 3575 3576 if (kvm_enabled() && cpu->enable_pmu && 3577 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 3578 uint64_t depth; 3579 int ret; 3580 3581 /* 3582 * Only migrate Arch LBR states when the host Arch LBR depth 3583 * equals that of source guest's, this is to avoid mismatch 3584 * of guest/host config for the msr hence avoid unexpected 3585 * misbehavior. 3586 */ 3587 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth); 3588 3589 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) { 3590 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl); 3591 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth); 3592 3593 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) { 3594 if (!env->lbr_records[i].from) { 3595 continue; 3596 } 3597 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 3598 env->lbr_records[i].from); 3599 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 3600 env->lbr_records[i].to); 3601 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 3602 env->lbr_records[i].info); 3603 } 3604 } 3605 } 3606 3607 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see 3608 * kvm_put_msr_feature_control. */ 3609 } 3610 3611 if (env->mcg_cap) { 3612 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status); 3613 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl); 3614 if (has_msr_mcg_ext_ctl) { 3615 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl); 3616 } 3617 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { 3618 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]); 3619 } 3620 } 3621 3622 return kvm_buf_set_msrs(cpu); 3623 } 3624 3625 3626 static int kvm_get_xsave(X86CPU *cpu) 3627 { 3628 CPUX86State *env = &cpu->env; 3629 void *xsave = env->xsave_buf; 3630 int type, ret; 3631 3632 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE; 3633 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave); 3634 if (ret < 0) { 3635 return ret; 3636 } 3637 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len); 3638 3639 return 0; 3640 } 3641 3642 static int kvm_get_xcrs(X86CPU *cpu) 3643 { 3644 CPUX86State *env = &cpu->env; 3645 int i, ret; 3646 struct kvm_xcrs xcrs; 3647 3648 if (!has_xcrs) { 3649 return 0; 3650 } 3651 3652 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); 3653 if (ret < 0) { 3654 return ret; 3655 } 3656 3657 for (i = 0; i < xcrs.nr_xcrs; i++) { 3658 /* Only support xcr0 now */ 3659 if (xcrs.xcrs[i].xcr == 0) { 3660 env->xcr0 = xcrs.xcrs[i].value; 3661 break; 3662 } 3663 } 3664 return 0; 3665 } 3666 3667 static int kvm_get_sregs(X86CPU *cpu) 3668 { 3669 CPUX86State *env = &cpu->env; 3670 struct kvm_sregs sregs; 3671 int ret; 3672 3673 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 3674 if (ret < 0) { 3675 return ret; 3676 } 3677 3678 /* 3679 * The interrupt_bitmap is ignored because KVM_GET_SREGS is 3680 * always preceded by KVM_GET_VCPU_EVENTS. 3681 */ 3682 3683 get_seg(&env->segs[R_CS], &sregs.cs); 3684 get_seg(&env->segs[R_DS], &sregs.ds); 3685 get_seg(&env->segs[R_ES], &sregs.es); 3686 get_seg(&env->segs[R_FS], &sregs.fs); 3687 get_seg(&env->segs[R_GS], &sregs.gs); 3688 get_seg(&env->segs[R_SS], &sregs.ss); 3689 3690 get_seg(&env->tr, &sregs.tr); 3691 get_seg(&env->ldt, &sregs.ldt); 3692 3693 env->idt.limit = sregs.idt.limit; 3694 env->idt.base = sregs.idt.base; 3695 env->gdt.limit = sregs.gdt.limit; 3696 env->gdt.base = sregs.gdt.base; 3697 3698 env->cr[0] = sregs.cr0; 3699 env->cr[2] = sregs.cr2; 3700 env->cr[3] = sregs.cr3; 3701 env->cr[4] = sregs.cr4; 3702 3703 env->efer = sregs.efer; 3704 if (sev_es_enabled() && env->efer & MSR_EFER_LME && 3705 env->cr[0] & CR0_PG_MASK) { 3706 env->efer |= MSR_EFER_LMA; 3707 } 3708 3709 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ 3710 x86_update_hflags(env); 3711 3712 return 0; 3713 } 3714 3715 static int kvm_get_sregs2(X86CPU *cpu) 3716 { 3717 CPUX86State *env = &cpu->env; 3718 struct kvm_sregs2 sregs; 3719 int i, ret; 3720 3721 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs); 3722 if (ret < 0) { 3723 return ret; 3724 } 3725 3726 get_seg(&env->segs[R_CS], &sregs.cs); 3727 get_seg(&env->segs[R_DS], &sregs.ds); 3728 get_seg(&env->segs[R_ES], &sregs.es); 3729 get_seg(&env->segs[R_FS], &sregs.fs); 3730 get_seg(&env->segs[R_GS], &sregs.gs); 3731 get_seg(&env->segs[R_SS], &sregs.ss); 3732 3733 get_seg(&env->tr, &sregs.tr); 3734 get_seg(&env->ldt, &sregs.ldt); 3735 3736 env->idt.limit = sregs.idt.limit; 3737 env->idt.base = sregs.idt.base; 3738 env->gdt.limit = sregs.gdt.limit; 3739 env->gdt.base = sregs.gdt.base; 3740 3741 env->cr[0] = sregs.cr0; 3742 env->cr[2] = sregs.cr2; 3743 env->cr[3] = sregs.cr3; 3744 env->cr[4] = sregs.cr4; 3745 3746 env->efer = sregs.efer; 3747 if (sev_es_enabled() && env->efer & MSR_EFER_LME && 3748 env->cr[0] & CR0_PG_MASK) { 3749 env->efer |= MSR_EFER_LMA; 3750 } 3751 3752 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 3753 3754 if (env->pdptrs_valid) { 3755 for (i = 0; i < 4; i++) { 3756 env->pdptrs[i] = sregs.pdptrs[i]; 3757 } 3758 } 3759 3760 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ 3761 x86_update_hflags(env); 3762 3763 return 0; 3764 } 3765 3766 static int kvm_get_msrs(X86CPU *cpu) 3767 { 3768 CPUX86State *env = &cpu->env; 3769 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries; 3770 int ret, i; 3771 uint64_t mtrr_top_bits; 3772 3773 kvm_msr_buf_reset(cpu); 3774 3775 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0); 3776 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0); 3777 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0); 3778 kvm_msr_entry_add(cpu, MSR_PAT, 0); 3779 if (has_msr_star) { 3780 kvm_msr_entry_add(cpu, MSR_STAR, 0); 3781 } 3782 if (has_msr_hsave_pa) { 3783 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0); 3784 } 3785 if (has_msr_tsc_aux) { 3786 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0); 3787 } 3788 if (has_msr_tsc_adjust) { 3789 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0); 3790 } 3791 if (has_msr_tsc_deadline) { 3792 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0); 3793 } 3794 if (has_msr_misc_enable) { 3795 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0); 3796 } 3797 if (has_msr_smbase) { 3798 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0); 3799 } 3800 if (has_msr_smi_count) { 3801 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0); 3802 } 3803 if (has_msr_feature_control) { 3804 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0); 3805 } 3806 if (has_msr_pkrs) { 3807 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0); 3808 } 3809 if (has_msr_bndcfgs) { 3810 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0); 3811 } 3812 if (has_msr_xss) { 3813 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); 3814 } 3815 if (has_msr_umwait) { 3816 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0); 3817 } 3818 if (has_msr_spec_ctrl) { 3819 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); 3820 } 3821 if (has_tsc_scale_msr) { 3822 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0); 3823 } 3824 3825 if (has_msr_tsx_ctrl) { 3826 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0); 3827 } 3828 if (has_msr_virt_ssbd) { 3829 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); 3830 } 3831 if (!env->tsc_valid) { 3832 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); 3833 env->tsc_valid = !runstate_is_running(); 3834 } 3835 3836 #ifdef TARGET_X86_64 3837 if (lm_capable_kernel) { 3838 kvm_msr_entry_add(cpu, MSR_CSTAR, 0); 3839 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0); 3840 kvm_msr_entry_add(cpu, MSR_FMASK, 0); 3841 kvm_msr_entry_add(cpu, MSR_LSTAR, 0); 3842 } 3843 #endif 3844 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0); 3845 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0); 3846 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { 3847 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0); 3848 } 3849 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) { 3850 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0); 3851 } 3852 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) { 3853 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0); 3854 } 3855 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { 3856 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0); 3857 } 3858 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { 3859 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); 3860 } 3861 if (has_architectural_pmu_version > 0) { 3862 if (has_architectural_pmu_version > 1) { 3863 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); 3864 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); 3865 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); 3866 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); 3867 } 3868 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { 3869 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); 3870 } 3871 for (i = 0; i < num_architectural_pmu_gp_counters; i++) { 3872 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); 3873 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); 3874 } 3875 } 3876 3877 if (env->mcg_cap) { 3878 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0); 3879 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0); 3880 if (has_msr_mcg_ext_ctl) { 3881 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0); 3882 } 3883 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { 3884 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0); 3885 } 3886 } 3887 3888 if (has_msr_hv_hypercall) { 3889 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0); 3890 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0); 3891 } 3892 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { 3893 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0); 3894 } 3895 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { 3896 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0); 3897 } 3898 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { 3899 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0); 3900 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0); 3901 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0); 3902 } 3903 if (has_msr_hv_syndbg_options) { 3904 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0); 3905 } 3906 if (has_msr_hv_crash) { 3907 int j; 3908 3909 for (j = 0; j < HV_CRASH_PARAMS; j++) { 3910 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0); 3911 } 3912 } 3913 if (has_msr_hv_runtime) { 3914 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0); 3915 } 3916 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 3917 uint32_t msr; 3918 3919 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0); 3920 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0); 3921 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0); 3922 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) { 3923 kvm_msr_entry_add(cpu, msr, 0); 3924 } 3925 } 3926 if (has_msr_hv_stimer) { 3927 uint32_t msr; 3928 3929 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT; 3930 msr++) { 3931 kvm_msr_entry_add(cpu, msr, 0); 3932 } 3933 } 3934 if (env->features[FEAT_1_EDX] & CPUID_MTRR) { 3935 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0); 3936 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0); 3937 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0); 3938 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0); 3939 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0); 3940 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0); 3941 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0); 3942 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0); 3943 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0); 3944 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0); 3945 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0); 3946 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0); 3947 for (i = 0; i < MSR_MTRRcap_VCNT; i++) { 3948 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0); 3949 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0); 3950 } 3951 } 3952 3953 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { 3954 int addr_num = 3955 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7; 3956 3957 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0); 3958 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0); 3959 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0); 3960 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0); 3961 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0); 3962 for (i = 0; i < addr_num; i++) { 3963 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0); 3964 } 3965 } 3966 3967 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) { 3968 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0); 3969 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0); 3970 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0); 3971 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0); 3972 } 3973 3974 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { 3975 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0); 3976 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0); 3977 } 3978 3979 if (kvm_enabled() && cpu->enable_pmu && 3980 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 3981 uint64_t depth; 3982 3983 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth); 3984 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) { 3985 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0); 3986 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0); 3987 3988 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) { 3989 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0); 3990 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0); 3991 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0); 3992 } 3993 } 3994 } 3995 3996 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); 3997 if (ret < 0) { 3998 return ret; 3999 } 4000 4001 if (ret < cpu->kvm_msr_buf->nmsrs) { 4002 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; 4003 error_report("error: failed to get MSR 0x%" PRIx32, 4004 (uint32_t)e->index); 4005 } 4006 4007 assert(ret == cpu->kvm_msr_buf->nmsrs); 4008 /* 4009 * MTRR masks: Each mask consists of 5 parts 4010 * a 10..0: must be zero 4011 * b 11 : valid bit 4012 * c n-1.12: actual mask bits 4013 * d 51..n: reserved must be zero 4014 * e 63.52: reserved must be zero 4015 * 4016 * 'n' is the number of physical bits supported by the CPU and is 4017 * apparently always <= 52. We know our 'n' but don't know what 4018 * the destinations 'n' is; it might be smaller, in which case 4019 * it masks (c) on loading. It might be larger, in which case 4020 * we fill 'd' so that d..c is consistent irrespetive of the 'n' 4021 * we're migrating to. 4022 */ 4023 4024 if (cpu->fill_mtrr_mask) { 4025 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); 4026 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); 4027 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); 4028 } else { 4029 mtrr_top_bits = 0; 4030 } 4031 4032 for (i = 0; i < ret; i++) { 4033 uint32_t index = msrs[i].index; 4034 switch (index) { 4035 case MSR_IA32_SYSENTER_CS: 4036 env->sysenter_cs = msrs[i].data; 4037 break; 4038 case MSR_IA32_SYSENTER_ESP: 4039 env->sysenter_esp = msrs[i].data; 4040 break; 4041 case MSR_IA32_SYSENTER_EIP: 4042 env->sysenter_eip = msrs[i].data; 4043 break; 4044 case MSR_PAT: 4045 env->pat = msrs[i].data; 4046 break; 4047 case MSR_STAR: 4048 env->star = msrs[i].data; 4049 break; 4050 #ifdef TARGET_X86_64 4051 case MSR_CSTAR: 4052 env->cstar = msrs[i].data; 4053 break; 4054 case MSR_KERNELGSBASE: 4055 env->kernelgsbase = msrs[i].data; 4056 break; 4057 case MSR_FMASK: 4058 env->fmask = msrs[i].data; 4059 break; 4060 case MSR_LSTAR: 4061 env->lstar = msrs[i].data; 4062 break; 4063 #endif 4064 case MSR_IA32_TSC: 4065 env->tsc = msrs[i].data; 4066 break; 4067 case MSR_TSC_AUX: 4068 env->tsc_aux = msrs[i].data; 4069 break; 4070 case MSR_TSC_ADJUST: 4071 env->tsc_adjust = msrs[i].data; 4072 break; 4073 case MSR_IA32_TSCDEADLINE: 4074 env->tsc_deadline = msrs[i].data; 4075 break; 4076 case MSR_VM_HSAVE_PA: 4077 env->vm_hsave = msrs[i].data; 4078 break; 4079 case MSR_KVM_SYSTEM_TIME: 4080 env->system_time_msr = msrs[i].data; 4081 break; 4082 case MSR_KVM_WALL_CLOCK: 4083 env->wall_clock_msr = msrs[i].data; 4084 break; 4085 case MSR_MCG_STATUS: 4086 env->mcg_status = msrs[i].data; 4087 break; 4088 case MSR_MCG_CTL: 4089 env->mcg_ctl = msrs[i].data; 4090 break; 4091 case MSR_MCG_EXT_CTL: 4092 env->mcg_ext_ctl = msrs[i].data; 4093 break; 4094 case MSR_IA32_MISC_ENABLE: 4095 env->msr_ia32_misc_enable = msrs[i].data; 4096 break; 4097 case MSR_IA32_SMBASE: 4098 env->smbase = msrs[i].data; 4099 break; 4100 case MSR_SMI_COUNT: 4101 env->msr_smi_count = msrs[i].data; 4102 break; 4103 case MSR_IA32_FEATURE_CONTROL: 4104 env->msr_ia32_feature_control = msrs[i].data; 4105 break; 4106 case MSR_IA32_BNDCFGS: 4107 env->msr_bndcfgs = msrs[i].data; 4108 break; 4109 case MSR_IA32_XSS: 4110 env->xss = msrs[i].data; 4111 break; 4112 case MSR_IA32_UMWAIT_CONTROL: 4113 env->umwait = msrs[i].data; 4114 break; 4115 case MSR_IA32_PKRS: 4116 env->pkrs = msrs[i].data; 4117 break; 4118 default: 4119 if (msrs[i].index >= MSR_MC0_CTL && 4120 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { 4121 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; 4122 } 4123 break; 4124 case MSR_KVM_ASYNC_PF_EN: 4125 env->async_pf_en_msr = msrs[i].data; 4126 break; 4127 case MSR_KVM_ASYNC_PF_INT: 4128 env->async_pf_int_msr = msrs[i].data; 4129 break; 4130 case MSR_KVM_PV_EOI_EN: 4131 env->pv_eoi_en_msr = msrs[i].data; 4132 break; 4133 case MSR_KVM_STEAL_TIME: 4134 env->steal_time_msr = msrs[i].data; 4135 break; 4136 case MSR_KVM_POLL_CONTROL: { 4137 env->poll_control_msr = msrs[i].data; 4138 break; 4139 } 4140 case MSR_CORE_PERF_FIXED_CTR_CTRL: 4141 env->msr_fixed_ctr_ctrl = msrs[i].data; 4142 break; 4143 case MSR_CORE_PERF_GLOBAL_CTRL: 4144 env->msr_global_ctrl = msrs[i].data; 4145 break; 4146 case MSR_CORE_PERF_GLOBAL_STATUS: 4147 env->msr_global_status = msrs[i].data; 4148 break; 4149 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 4150 env->msr_global_ovf_ctrl = msrs[i].data; 4151 break; 4152 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1: 4153 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data; 4154 break; 4155 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: 4156 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; 4157 break; 4158 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: 4159 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; 4160 break; 4161 case HV_X64_MSR_HYPERCALL: 4162 env->msr_hv_hypercall = msrs[i].data; 4163 break; 4164 case HV_X64_MSR_GUEST_OS_ID: 4165 env->msr_hv_guest_os_id = msrs[i].data; 4166 break; 4167 case HV_X64_MSR_APIC_ASSIST_PAGE: 4168 env->msr_hv_vapic = msrs[i].data; 4169 break; 4170 case HV_X64_MSR_REFERENCE_TSC: 4171 env->msr_hv_tsc = msrs[i].data; 4172 break; 4173 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4174 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data; 4175 break; 4176 case HV_X64_MSR_VP_RUNTIME: 4177 env->msr_hv_runtime = msrs[i].data; 4178 break; 4179 case HV_X64_MSR_SCONTROL: 4180 env->msr_hv_synic_control = msrs[i].data; 4181 break; 4182 case HV_X64_MSR_SIEFP: 4183 env->msr_hv_synic_evt_page = msrs[i].data; 4184 break; 4185 case HV_X64_MSR_SIMP: 4186 env->msr_hv_synic_msg_page = msrs[i].data; 4187 break; 4188 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: 4189 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data; 4190 break; 4191 case HV_X64_MSR_STIMER0_CONFIG: 4192 case HV_X64_MSR_STIMER1_CONFIG: 4193 case HV_X64_MSR_STIMER2_CONFIG: 4194 case HV_X64_MSR_STIMER3_CONFIG: 4195 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] = 4196 msrs[i].data; 4197 break; 4198 case HV_X64_MSR_STIMER0_COUNT: 4199 case HV_X64_MSR_STIMER1_COUNT: 4200 case HV_X64_MSR_STIMER2_COUNT: 4201 case HV_X64_MSR_STIMER3_COUNT: 4202 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] = 4203 msrs[i].data; 4204 break; 4205 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4206 env->msr_hv_reenlightenment_control = msrs[i].data; 4207 break; 4208 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4209 env->msr_hv_tsc_emulation_control = msrs[i].data; 4210 break; 4211 case HV_X64_MSR_TSC_EMULATION_STATUS: 4212 env->msr_hv_tsc_emulation_status = msrs[i].data; 4213 break; 4214 case HV_X64_MSR_SYNDBG_OPTIONS: 4215 env->msr_hv_syndbg_options = msrs[i].data; 4216 break; 4217 case MSR_MTRRdefType: 4218 env->mtrr_deftype = msrs[i].data; 4219 break; 4220 case MSR_MTRRfix64K_00000: 4221 env->mtrr_fixed[0] = msrs[i].data; 4222 break; 4223 case MSR_MTRRfix16K_80000: 4224 env->mtrr_fixed[1] = msrs[i].data; 4225 break; 4226 case MSR_MTRRfix16K_A0000: 4227 env->mtrr_fixed[2] = msrs[i].data; 4228 break; 4229 case MSR_MTRRfix4K_C0000: 4230 env->mtrr_fixed[3] = msrs[i].data; 4231 break; 4232 case MSR_MTRRfix4K_C8000: 4233 env->mtrr_fixed[4] = msrs[i].data; 4234 break; 4235 case MSR_MTRRfix4K_D0000: 4236 env->mtrr_fixed[5] = msrs[i].data; 4237 break; 4238 case MSR_MTRRfix4K_D8000: 4239 env->mtrr_fixed[6] = msrs[i].data; 4240 break; 4241 case MSR_MTRRfix4K_E0000: 4242 env->mtrr_fixed[7] = msrs[i].data; 4243 break; 4244 case MSR_MTRRfix4K_E8000: 4245 env->mtrr_fixed[8] = msrs[i].data; 4246 break; 4247 case MSR_MTRRfix4K_F0000: 4248 env->mtrr_fixed[9] = msrs[i].data; 4249 break; 4250 case MSR_MTRRfix4K_F8000: 4251 env->mtrr_fixed[10] = msrs[i].data; 4252 break; 4253 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): 4254 if (index & 1) { 4255 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | 4256 mtrr_top_bits; 4257 } else { 4258 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; 4259 } 4260 break; 4261 case MSR_IA32_SPEC_CTRL: 4262 env->spec_ctrl = msrs[i].data; 4263 break; 4264 case MSR_AMD64_TSC_RATIO: 4265 env->amd_tsc_scale_msr = msrs[i].data; 4266 break; 4267 case MSR_IA32_TSX_CTRL: 4268 env->tsx_ctrl = msrs[i].data; 4269 break; 4270 case MSR_VIRT_SSBD: 4271 env->virt_ssbd = msrs[i].data; 4272 break; 4273 case MSR_IA32_RTIT_CTL: 4274 env->msr_rtit_ctrl = msrs[i].data; 4275 break; 4276 case MSR_IA32_RTIT_STATUS: 4277 env->msr_rtit_status = msrs[i].data; 4278 break; 4279 case MSR_IA32_RTIT_OUTPUT_BASE: 4280 env->msr_rtit_output_base = msrs[i].data; 4281 break; 4282 case MSR_IA32_RTIT_OUTPUT_MASK: 4283 env->msr_rtit_output_mask = msrs[i].data; 4284 break; 4285 case MSR_IA32_RTIT_CR3_MATCH: 4286 env->msr_rtit_cr3_match = msrs[i].data; 4287 break; 4288 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 4289 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data; 4290 break; 4291 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3: 4292 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] = 4293 msrs[i].data; 4294 break; 4295 case MSR_IA32_XFD: 4296 env->msr_xfd = msrs[i].data; 4297 break; 4298 case MSR_IA32_XFD_ERR: 4299 env->msr_xfd_err = msrs[i].data; 4300 break; 4301 case MSR_ARCH_LBR_CTL: 4302 env->msr_lbr_ctl = msrs[i].data; 4303 break; 4304 case MSR_ARCH_LBR_DEPTH: 4305 env->msr_lbr_depth = msrs[i].data; 4306 break; 4307 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31: 4308 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data; 4309 break; 4310 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31: 4311 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data; 4312 break; 4313 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: 4314 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data; 4315 break; 4316 } 4317 } 4318 4319 return 0; 4320 } 4321 4322 static int kvm_put_mp_state(X86CPU *cpu) 4323 { 4324 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; 4325 4326 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 4327 } 4328 4329 static int kvm_get_mp_state(X86CPU *cpu) 4330 { 4331 CPUState *cs = CPU(cpu); 4332 CPUX86State *env = &cpu->env; 4333 struct kvm_mp_state mp_state; 4334 int ret; 4335 4336 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); 4337 if (ret < 0) { 4338 return ret; 4339 } 4340 env->mp_state = mp_state.mp_state; 4341 if (kvm_irqchip_in_kernel()) { 4342 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); 4343 } 4344 return 0; 4345 } 4346 4347 static int kvm_get_apic(X86CPU *cpu) 4348 { 4349 DeviceState *apic = cpu->apic_state; 4350 struct kvm_lapic_state kapic; 4351 int ret; 4352 4353 if (apic && kvm_irqchip_in_kernel()) { 4354 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); 4355 if (ret < 0) { 4356 return ret; 4357 } 4358 4359 kvm_get_apic_state(apic, &kapic); 4360 } 4361 return 0; 4362 } 4363 4364 static int kvm_put_vcpu_events(X86CPU *cpu, int level) 4365 { 4366 CPUState *cs = CPU(cpu); 4367 CPUX86State *env = &cpu->env; 4368 struct kvm_vcpu_events events = {}; 4369 4370 events.flags = 0; 4371 4372 if (has_exception_payload) { 4373 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4374 events.exception.pending = env->exception_pending; 4375 events.exception_has_payload = env->exception_has_payload; 4376 events.exception_payload = env->exception_payload; 4377 } 4378 events.exception.nr = env->exception_nr; 4379 events.exception.injected = env->exception_injected; 4380 events.exception.has_error_code = env->has_error_code; 4381 events.exception.error_code = env->error_code; 4382 4383 events.interrupt.injected = (env->interrupt_injected >= 0); 4384 events.interrupt.nr = env->interrupt_injected; 4385 events.interrupt.soft = env->soft_interrupt; 4386 4387 events.nmi.injected = env->nmi_injected; 4388 events.nmi.pending = env->nmi_pending; 4389 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); 4390 4391 events.sipi_vector = env->sipi_vector; 4392 4393 if (has_msr_smbase) { 4394 events.smi.smm = !!(env->hflags & HF_SMM_MASK); 4395 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK); 4396 if (kvm_irqchip_in_kernel()) { 4397 /* As soon as these are moved to the kernel, remove them 4398 * from cs->interrupt_request. 4399 */ 4400 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI; 4401 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT; 4402 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI); 4403 } else { 4404 /* Keep these in cs->interrupt_request. */ 4405 events.smi.pending = 0; 4406 events.smi.latched_init = 0; 4407 } 4408 /* Stop SMI delivery on old machine types to avoid a reboot 4409 * on an inward migration of an old VM. 4410 */ 4411 if (!cpu->kvm_no_smi_migration) { 4412 events.flags |= KVM_VCPUEVENT_VALID_SMM; 4413 } 4414 } 4415 4416 if (level >= KVM_PUT_RESET_STATE) { 4417 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING; 4418 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 4419 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR; 4420 } 4421 } 4422 4423 if (has_triple_fault_event) { 4424 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; 4425 events.triple_fault.pending = env->triple_fault_pending; 4426 } 4427 4428 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); 4429 } 4430 4431 static int kvm_get_vcpu_events(X86CPU *cpu) 4432 { 4433 CPUX86State *env = &cpu->env; 4434 struct kvm_vcpu_events events; 4435 int ret; 4436 4437 memset(&events, 0, sizeof(events)); 4438 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); 4439 if (ret < 0) { 4440 return ret; 4441 } 4442 4443 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4444 env->exception_pending = events.exception.pending; 4445 env->exception_has_payload = events.exception_has_payload; 4446 env->exception_payload = events.exception_payload; 4447 } else { 4448 env->exception_pending = 0; 4449 env->exception_has_payload = false; 4450 } 4451 env->exception_injected = events.exception.injected; 4452 env->exception_nr = 4453 (env->exception_pending || env->exception_injected) ? 4454 events.exception.nr : -1; 4455 env->has_error_code = events.exception.has_error_code; 4456 env->error_code = events.exception.error_code; 4457 4458 env->interrupt_injected = 4459 events.interrupt.injected ? events.interrupt.nr : -1; 4460 env->soft_interrupt = events.interrupt.soft; 4461 4462 env->nmi_injected = events.nmi.injected; 4463 env->nmi_pending = events.nmi.pending; 4464 if (events.nmi.masked) { 4465 env->hflags2 |= HF2_NMI_MASK; 4466 } else { 4467 env->hflags2 &= ~HF2_NMI_MASK; 4468 } 4469 4470 if (events.flags & KVM_VCPUEVENT_VALID_SMM) { 4471 if (events.smi.smm) { 4472 env->hflags |= HF_SMM_MASK; 4473 } else { 4474 env->hflags &= ~HF_SMM_MASK; 4475 } 4476 if (events.smi.pending) { 4477 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 4478 } else { 4479 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 4480 } 4481 if (events.smi.smm_inside_nmi) { 4482 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; 4483 } else { 4484 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK; 4485 } 4486 if (events.smi.latched_init) { 4487 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); 4488 } else { 4489 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); 4490 } 4491 } 4492 4493 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { 4494 env->triple_fault_pending = events.triple_fault.pending; 4495 } 4496 4497 env->sipi_vector = events.sipi_vector; 4498 4499 return 0; 4500 } 4501 4502 static int kvm_put_debugregs(X86CPU *cpu) 4503 { 4504 CPUX86State *env = &cpu->env; 4505 struct kvm_debugregs dbgregs; 4506 int i; 4507 4508 memset(&dbgregs, 0, sizeof(dbgregs)); 4509 for (i = 0; i < 4; i++) { 4510 dbgregs.db[i] = env->dr[i]; 4511 } 4512 dbgregs.dr6 = env->dr[6]; 4513 dbgregs.dr7 = env->dr[7]; 4514 dbgregs.flags = 0; 4515 4516 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); 4517 } 4518 4519 static int kvm_get_debugregs(X86CPU *cpu) 4520 { 4521 CPUX86State *env = &cpu->env; 4522 struct kvm_debugregs dbgregs; 4523 int i, ret; 4524 4525 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); 4526 if (ret < 0) { 4527 return ret; 4528 } 4529 for (i = 0; i < 4; i++) { 4530 env->dr[i] = dbgregs.db[i]; 4531 } 4532 env->dr[4] = env->dr[6] = dbgregs.dr6; 4533 env->dr[5] = env->dr[7] = dbgregs.dr7; 4534 4535 return 0; 4536 } 4537 4538 static int kvm_put_nested_state(X86CPU *cpu) 4539 { 4540 CPUX86State *env = &cpu->env; 4541 int max_nested_state_len = kvm_max_nested_state_length(); 4542 4543 if (!env->nested_state) { 4544 return 0; 4545 } 4546 4547 /* 4548 * Copy flags that are affected by reset from env->hflags and env->hflags2. 4549 */ 4550 if (env->hflags & HF_GUEST_MASK) { 4551 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE; 4552 } else { 4553 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE; 4554 } 4555 4556 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */ 4557 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) { 4558 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET; 4559 } else { 4560 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET; 4561 } 4562 4563 assert(env->nested_state->size <= max_nested_state_len); 4564 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state); 4565 } 4566 4567 static int kvm_get_nested_state(X86CPU *cpu) 4568 { 4569 CPUX86State *env = &cpu->env; 4570 int max_nested_state_len = kvm_max_nested_state_length(); 4571 int ret; 4572 4573 if (!env->nested_state) { 4574 return 0; 4575 } 4576 4577 /* 4578 * It is possible that migration restored a smaller size into 4579 * nested_state->hdr.size than what our kernel support. 4580 * We preserve migration origin nested_state->hdr.size for 4581 * call to KVM_SET_NESTED_STATE but wish that our next call 4582 * to KVM_GET_NESTED_STATE will use max size our kernel support. 4583 */ 4584 env->nested_state->size = max_nested_state_len; 4585 4586 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state); 4587 if (ret < 0) { 4588 return ret; 4589 } 4590 4591 /* 4592 * Copy flags that are affected by reset to env->hflags and env->hflags2. 4593 */ 4594 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) { 4595 env->hflags |= HF_GUEST_MASK; 4596 } else { 4597 env->hflags &= ~HF_GUEST_MASK; 4598 } 4599 4600 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */ 4601 if (cpu_has_svm(env)) { 4602 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) { 4603 env->hflags2 |= HF2_GIF_MASK; 4604 } else { 4605 env->hflags2 &= ~HF2_GIF_MASK; 4606 } 4607 } 4608 4609 return ret; 4610 } 4611 4612 int kvm_arch_put_registers(CPUState *cpu, int level) 4613 { 4614 X86CPU *x86_cpu = X86_CPU(cpu); 4615 int ret; 4616 4617 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); 4618 4619 /* 4620 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX 4621 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also 4622 * precede kvm_put_nested_state() when 'real' nested state is set. 4623 */ 4624 if (level >= KVM_PUT_RESET_STATE) { 4625 ret = kvm_put_msr_feature_control(x86_cpu); 4626 if (ret < 0) { 4627 return ret; 4628 } 4629 } 4630 4631 /* must be before kvm_put_nested_state so that EFER.SVME is set */ 4632 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu); 4633 if (ret < 0) { 4634 return ret; 4635 } 4636 4637 if (level >= KVM_PUT_RESET_STATE) { 4638 ret = kvm_put_nested_state(x86_cpu); 4639 if (ret < 0) { 4640 return ret; 4641 } 4642 } 4643 4644 if (level == KVM_PUT_FULL_STATE) { 4645 /* We don't check for kvm_arch_set_tsc_khz() errors here, 4646 * because TSC frequency mismatch shouldn't abort migration, 4647 * unless the user explicitly asked for a more strict TSC 4648 * setting (e.g. using an explicit "tsc-freq" option). 4649 */ 4650 kvm_arch_set_tsc_khz(cpu); 4651 } 4652 4653 #ifdef CONFIG_XEN_EMU 4654 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) { 4655 ret = kvm_put_xen_state(cpu); 4656 if (ret < 0) { 4657 return ret; 4658 } 4659 } 4660 #endif 4661 4662 ret = kvm_getput_regs(x86_cpu, 1); 4663 if (ret < 0) { 4664 return ret; 4665 } 4666 ret = kvm_put_xsave(x86_cpu); 4667 if (ret < 0) { 4668 return ret; 4669 } 4670 ret = kvm_put_xcrs(x86_cpu); 4671 if (ret < 0) { 4672 return ret; 4673 } 4674 ret = kvm_put_msrs(x86_cpu, level); 4675 if (ret < 0) { 4676 return ret; 4677 } 4678 ret = kvm_put_vcpu_events(x86_cpu, level); 4679 if (ret < 0) { 4680 return ret; 4681 } 4682 if (level >= KVM_PUT_RESET_STATE) { 4683 ret = kvm_put_mp_state(x86_cpu); 4684 if (ret < 0) { 4685 return ret; 4686 } 4687 } 4688 4689 ret = kvm_put_tscdeadline_msr(x86_cpu); 4690 if (ret < 0) { 4691 return ret; 4692 } 4693 ret = kvm_put_debugregs(x86_cpu); 4694 if (ret < 0) { 4695 return ret; 4696 } 4697 return 0; 4698 } 4699 4700 int kvm_arch_get_registers(CPUState *cs) 4701 { 4702 X86CPU *cpu = X86_CPU(cs); 4703 int ret; 4704 4705 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); 4706 4707 ret = kvm_get_vcpu_events(cpu); 4708 if (ret < 0) { 4709 goto out; 4710 } 4711 /* 4712 * KVM_GET_MPSTATE can modify CS and RIP, call it before 4713 * KVM_GET_REGS and KVM_GET_SREGS. 4714 */ 4715 ret = kvm_get_mp_state(cpu); 4716 if (ret < 0) { 4717 goto out; 4718 } 4719 ret = kvm_getput_regs(cpu, 0); 4720 if (ret < 0) { 4721 goto out; 4722 } 4723 ret = kvm_get_xsave(cpu); 4724 if (ret < 0) { 4725 goto out; 4726 } 4727 ret = kvm_get_xcrs(cpu); 4728 if (ret < 0) { 4729 goto out; 4730 } 4731 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu); 4732 if (ret < 0) { 4733 goto out; 4734 } 4735 ret = kvm_get_msrs(cpu); 4736 if (ret < 0) { 4737 goto out; 4738 } 4739 ret = kvm_get_apic(cpu); 4740 if (ret < 0) { 4741 goto out; 4742 } 4743 ret = kvm_get_debugregs(cpu); 4744 if (ret < 0) { 4745 goto out; 4746 } 4747 ret = kvm_get_nested_state(cpu); 4748 if (ret < 0) { 4749 goto out; 4750 } 4751 #ifdef CONFIG_XEN_EMU 4752 if (xen_mode == XEN_EMULATE) { 4753 ret = kvm_get_xen_state(cs); 4754 if (ret < 0) { 4755 goto out; 4756 } 4757 } 4758 #endif 4759 ret = 0; 4760 out: 4761 cpu_sync_bndcs_hflags(&cpu->env); 4762 return ret; 4763 } 4764 4765 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) 4766 { 4767 X86CPU *x86_cpu = X86_CPU(cpu); 4768 CPUX86State *env = &x86_cpu->env; 4769 int ret; 4770 4771 /* Inject NMI */ 4772 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { 4773 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { 4774 bql_lock(); 4775 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; 4776 bql_unlock(); 4777 DPRINTF("injected NMI\n"); 4778 ret = kvm_vcpu_ioctl(cpu, KVM_NMI); 4779 if (ret < 0) { 4780 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", 4781 strerror(-ret)); 4782 } 4783 } 4784 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { 4785 bql_lock(); 4786 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; 4787 bql_unlock(); 4788 DPRINTF("injected SMI\n"); 4789 ret = kvm_vcpu_ioctl(cpu, KVM_SMI); 4790 if (ret < 0) { 4791 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n", 4792 strerror(-ret)); 4793 } 4794 } 4795 } 4796 4797 if (!kvm_pic_in_kernel()) { 4798 bql_lock(); 4799 } 4800 4801 /* Force the VCPU out of its inner loop to process any INIT requests 4802 * or (for userspace APIC, but it is cheap to combine the checks here) 4803 * pending TPR access reports. 4804 */ 4805 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { 4806 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && 4807 !(env->hflags & HF_SMM_MASK)) { 4808 cpu->exit_request = 1; 4809 } 4810 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { 4811 cpu->exit_request = 1; 4812 } 4813 } 4814 4815 if (!kvm_pic_in_kernel()) { 4816 /* Try to inject an interrupt if the guest can accept it */ 4817 if (run->ready_for_interrupt_injection && 4818 (cpu->interrupt_request & CPU_INTERRUPT_HARD) && 4819 (env->eflags & IF_MASK)) { 4820 int irq; 4821 4822 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; 4823 irq = cpu_get_pic_interrupt(env); 4824 if (irq >= 0) { 4825 struct kvm_interrupt intr; 4826 4827 intr.irq = irq; 4828 DPRINTF("injected interrupt %d\n", irq); 4829 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); 4830 if (ret < 0) { 4831 fprintf(stderr, 4832 "KVM: injection failed, interrupt lost (%s)\n", 4833 strerror(-ret)); 4834 } 4835 } 4836 } 4837 4838 /* If we have an interrupt but the guest is not ready to receive an 4839 * interrupt, request an interrupt window exit. This will 4840 * cause a return to userspace as soon as the guest is ready to 4841 * receive interrupts. */ 4842 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { 4843 run->request_interrupt_window = 1; 4844 } else { 4845 run->request_interrupt_window = 0; 4846 } 4847 4848 DPRINTF("setting tpr\n"); 4849 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state); 4850 4851 bql_unlock(); 4852 } 4853 } 4854 4855 static void kvm_rate_limit_on_bus_lock(void) 4856 { 4857 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1); 4858 4859 if (delay_ns) { 4860 g_usleep(delay_ns / SCALE_US); 4861 } 4862 } 4863 4864 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) 4865 { 4866 X86CPU *x86_cpu = X86_CPU(cpu); 4867 CPUX86State *env = &x86_cpu->env; 4868 4869 if (run->flags & KVM_RUN_X86_SMM) { 4870 env->hflags |= HF_SMM_MASK; 4871 } else { 4872 env->hflags &= ~HF_SMM_MASK; 4873 } 4874 if (run->if_flag) { 4875 env->eflags |= IF_MASK; 4876 } else { 4877 env->eflags &= ~IF_MASK; 4878 } 4879 if (run->flags & KVM_RUN_X86_BUS_LOCK) { 4880 kvm_rate_limit_on_bus_lock(); 4881 } 4882 4883 #ifdef CONFIG_XEN_EMU 4884 /* 4885 * If the callback is asserted as a GSI (or PCI INTx) then check if 4886 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert 4887 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC 4888 * EOI and only resample then, exactly how the VFIO eventfd pairs 4889 * are designed to work for level triggered interrupts. 4890 */ 4891 if (x86_cpu->env.xen_callback_asserted) { 4892 kvm_xen_maybe_deassert_callback(cpu); 4893 } 4894 #endif 4895 4896 /* We need to protect the apic state against concurrent accesses from 4897 * different threads in case the userspace irqchip is used. */ 4898 if (!kvm_irqchip_in_kernel()) { 4899 bql_lock(); 4900 } 4901 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); 4902 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); 4903 if (!kvm_irqchip_in_kernel()) { 4904 bql_unlock(); 4905 } 4906 return cpu_get_mem_attrs(env); 4907 } 4908 4909 int kvm_arch_process_async_events(CPUState *cs) 4910 { 4911 X86CPU *cpu = X86_CPU(cs); 4912 CPUX86State *env = &cpu->env; 4913 4914 if (cs->interrupt_request & CPU_INTERRUPT_MCE) { 4915 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ 4916 assert(env->mcg_cap); 4917 4918 cs->interrupt_request &= ~CPU_INTERRUPT_MCE; 4919 4920 kvm_cpu_synchronize_state(cs); 4921 4922 if (env->exception_nr == EXCP08_DBLE) { 4923 /* this means triple fault */ 4924 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 4925 cs->exit_request = 1; 4926 return 0; 4927 } 4928 kvm_queue_exception(env, EXCP12_MCHK, 0, 0); 4929 env->has_error_code = 0; 4930 4931 cs->halted = 0; 4932 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { 4933 env->mp_state = KVM_MP_STATE_RUNNABLE; 4934 } 4935 } 4936 4937 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) && 4938 !(env->hflags & HF_SMM_MASK)) { 4939 kvm_cpu_synchronize_state(cs); 4940 do_cpu_init(cpu); 4941 } 4942 4943 if (kvm_irqchip_in_kernel()) { 4944 return 0; 4945 } 4946 4947 if (cs->interrupt_request & CPU_INTERRUPT_POLL) { 4948 cs->interrupt_request &= ~CPU_INTERRUPT_POLL; 4949 apic_poll_irq(cpu->apic_state); 4950 } 4951 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && 4952 (env->eflags & IF_MASK)) || 4953 (cs->interrupt_request & CPU_INTERRUPT_NMI)) { 4954 cs->halted = 0; 4955 } 4956 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { 4957 kvm_cpu_synchronize_state(cs); 4958 do_cpu_sipi(cpu); 4959 } 4960 if (cs->interrupt_request & CPU_INTERRUPT_TPR) { 4961 cs->interrupt_request &= ~CPU_INTERRUPT_TPR; 4962 kvm_cpu_synchronize_state(cs); 4963 apic_handle_tpr_access_report(cpu->apic_state, env->eip, 4964 env->tpr_access_type); 4965 } 4966 4967 return cs->halted; 4968 } 4969 4970 static int kvm_handle_halt(X86CPU *cpu) 4971 { 4972 CPUState *cs = CPU(cpu); 4973 CPUX86State *env = &cpu->env; 4974 4975 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && 4976 (env->eflags & IF_MASK)) && 4977 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { 4978 cs->halted = 1; 4979 return EXCP_HLT; 4980 } 4981 4982 return 0; 4983 } 4984 4985 static int kvm_handle_tpr_access(X86CPU *cpu) 4986 { 4987 CPUState *cs = CPU(cpu); 4988 struct kvm_run *run = cs->kvm_run; 4989 4990 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, 4991 run->tpr_access.is_write ? TPR_ACCESS_WRITE 4992 : TPR_ACCESS_READ); 4993 return 1; 4994 } 4995 4996 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 4997 { 4998 static const uint8_t int3 = 0xcc; 4999 5000 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || 5001 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { 5002 return -EINVAL; 5003 } 5004 return 0; 5005 } 5006 5007 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 5008 { 5009 uint8_t int3; 5010 5011 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) { 5012 return -EINVAL; 5013 } 5014 if (int3 != 0xcc) { 5015 return 0; 5016 } 5017 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { 5018 return -EINVAL; 5019 } 5020 return 0; 5021 } 5022 5023 static struct { 5024 target_ulong addr; 5025 int len; 5026 int type; 5027 } hw_breakpoint[4]; 5028 5029 static int nb_hw_breakpoint; 5030 5031 static int find_hw_breakpoint(target_ulong addr, int len, int type) 5032 { 5033 int n; 5034 5035 for (n = 0; n < nb_hw_breakpoint; n++) { 5036 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && 5037 (hw_breakpoint[n].len == len || len == -1)) { 5038 return n; 5039 } 5040 } 5041 return -1; 5042 } 5043 5044 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 5045 { 5046 switch (type) { 5047 case GDB_BREAKPOINT_HW: 5048 len = 1; 5049 break; 5050 case GDB_WATCHPOINT_WRITE: 5051 case GDB_WATCHPOINT_ACCESS: 5052 switch (len) { 5053 case 1: 5054 break; 5055 case 2: 5056 case 4: 5057 case 8: 5058 if (addr & (len - 1)) { 5059 return -EINVAL; 5060 } 5061 break; 5062 default: 5063 return -EINVAL; 5064 } 5065 break; 5066 default: 5067 return -ENOSYS; 5068 } 5069 5070 if (nb_hw_breakpoint == 4) { 5071 return -ENOBUFS; 5072 } 5073 if (find_hw_breakpoint(addr, len, type) >= 0) { 5074 return -EEXIST; 5075 } 5076 hw_breakpoint[nb_hw_breakpoint].addr = addr; 5077 hw_breakpoint[nb_hw_breakpoint].len = len; 5078 hw_breakpoint[nb_hw_breakpoint].type = type; 5079 nb_hw_breakpoint++; 5080 5081 return 0; 5082 } 5083 5084 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 5085 { 5086 int n; 5087 5088 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); 5089 if (n < 0) { 5090 return -ENOENT; 5091 } 5092 nb_hw_breakpoint--; 5093 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; 5094 5095 return 0; 5096 } 5097 5098 void kvm_arch_remove_all_hw_breakpoints(void) 5099 { 5100 nb_hw_breakpoint = 0; 5101 } 5102 5103 static CPUWatchpoint hw_watchpoint; 5104 5105 static int kvm_handle_debug(X86CPU *cpu, 5106 struct kvm_debug_exit_arch *arch_info) 5107 { 5108 CPUState *cs = CPU(cpu); 5109 CPUX86State *env = &cpu->env; 5110 int ret = 0; 5111 int n; 5112 5113 if (arch_info->exception == EXCP01_DB) { 5114 if (arch_info->dr6 & DR6_BS) { 5115 if (cs->singlestep_enabled) { 5116 ret = EXCP_DEBUG; 5117 } 5118 } else { 5119 for (n = 0; n < 4; n++) { 5120 if (arch_info->dr6 & (1 << n)) { 5121 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { 5122 case 0x0: 5123 ret = EXCP_DEBUG; 5124 break; 5125 case 0x1: 5126 ret = EXCP_DEBUG; 5127 cs->watchpoint_hit = &hw_watchpoint; 5128 hw_watchpoint.vaddr = hw_breakpoint[n].addr; 5129 hw_watchpoint.flags = BP_MEM_WRITE; 5130 break; 5131 case 0x3: 5132 ret = EXCP_DEBUG; 5133 cs->watchpoint_hit = &hw_watchpoint; 5134 hw_watchpoint.vaddr = hw_breakpoint[n].addr; 5135 hw_watchpoint.flags = BP_MEM_ACCESS; 5136 break; 5137 } 5138 } 5139 } 5140 } 5141 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { 5142 ret = EXCP_DEBUG; 5143 } 5144 if (ret == 0) { 5145 cpu_synchronize_state(cs); 5146 assert(env->exception_nr == -1); 5147 5148 /* pass to guest */ 5149 kvm_queue_exception(env, arch_info->exception, 5150 arch_info->exception == EXCP01_DB, 5151 arch_info->dr6); 5152 env->has_error_code = 0; 5153 } 5154 5155 return ret; 5156 } 5157 5158 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) 5159 { 5160 const uint8_t type_code[] = { 5161 [GDB_BREAKPOINT_HW] = 0x0, 5162 [GDB_WATCHPOINT_WRITE] = 0x1, 5163 [GDB_WATCHPOINT_ACCESS] = 0x3 5164 }; 5165 const uint8_t len_code[] = { 5166 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 5167 }; 5168 int n; 5169 5170 if (kvm_sw_breakpoints_active(cpu)) { 5171 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 5172 } 5173 if (nb_hw_breakpoint > 0) { 5174 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 5175 dbg->arch.debugreg[7] = 0x0600; 5176 for (n = 0; n < nb_hw_breakpoint; n++) { 5177 dbg->arch.debugreg[n] = hw_breakpoint[n].addr; 5178 dbg->arch.debugreg[7] |= (2 << (n * 2)) | 5179 (type_code[hw_breakpoint[n].type] << (16 + n*4)) | 5180 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); 5181 } 5182 } 5183 } 5184 5185 static bool kvm_install_msr_filters(KVMState *s) 5186 { 5187 uint64_t zero = 0; 5188 struct kvm_msr_filter filter = { 5189 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW, 5190 }; 5191 int r, i, j = 0; 5192 5193 for (i = 0; i < KVM_MSR_FILTER_MAX_RANGES; i++) { 5194 KVMMSRHandlers *handler = &msr_handlers[i]; 5195 if (handler->msr) { 5196 struct kvm_msr_filter_range *range = &filter.ranges[j++]; 5197 5198 *range = (struct kvm_msr_filter_range) { 5199 .flags = 0, 5200 .nmsrs = 1, 5201 .base = handler->msr, 5202 .bitmap = (__u8 *)&zero, 5203 }; 5204 5205 if (handler->rdmsr) { 5206 range->flags |= KVM_MSR_FILTER_READ; 5207 } 5208 5209 if (handler->wrmsr) { 5210 range->flags |= KVM_MSR_FILTER_WRITE; 5211 } 5212 } 5213 } 5214 5215 r = kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter); 5216 if (r) { 5217 return false; 5218 } 5219 5220 return true; 5221 } 5222 5223 bool kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr, 5224 QEMUWRMSRHandler *wrmsr) 5225 { 5226 int i; 5227 5228 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) { 5229 if (!msr_handlers[i].msr) { 5230 msr_handlers[i] = (KVMMSRHandlers) { 5231 .msr = msr, 5232 .rdmsr = rdmsr, 5233 .wrmsr = wrmsr, 5234 }; 5235 5236 if (!kvm_install_msr_filters(s)) { 5237 msr_handlers[i] = (KVMMSRHandlers) { }; 5238 return false; 5239 } 5240 5241 return true; 5242 } 5243 } 5244 5245 return false; 5246 } 5247 5248 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run) 5249 { 5250 int i; 5251 bool r; 5252 5253 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) { 5254 KVMMSRHandlers *handler = &msr_handlers[i]; 5255 if (run->msr.index == handler->msr) { 5256 if (handler->rdmsr) { 5257 r = handler->rdmsr(cpu, handler->msr, 5258 (uint64_t *)&run->msr.data); 5259 run->msr.error = r ? 0 : 1; 5260 return 0; 5261 } 5262 } 5263 } 5264 5265 assert(false); 5266 } 5267 5268 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run) 5269 { 5270 int i; 5271 bool r; 5272 5273 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) { 5274 KVMMSRHandlers *handler = &msr_handlers[i]; 5275 if (run->msr.index == handler->msr) { 5276 if (handler->wrmsr) { 5277 r = handler->wrmsr(cpu, handler->msr, run->msr.data); 5278 run->msr.error = r ? 0 : 1; 5279 return 0; 5280 } 5281 } 5282 } 5283 5284 assert(false); 5285 } 5286 5287 static bool has_sgx_provisioning; 5288 5289 static bool __kvm_enable_sgx_provisioning(KVMState *s) 5290 { 5291 int fd, ret; 5292 5293 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) { 5294 return false; 5295 } 5296 5297 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY); 5298 if (fd < 0) { 5299 return false; 5300 } 5301 5302 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd); 5303 if (ret) { 5304 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret)); 5305 exit(1); 5306 } 5307 close(fd); 5308 return true; 5309 } 5310 5311 bool kvm_enable_sgx_provisioning(KVMState *s) 5312 { 5313 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning); 5314 } 5315 5316 static bool host_supports_vmx(void) 5317 { 5318 uint32_t ecx, unused; 5319 5320 host_cpuid(1, 0, &unused, &unused, &ecx, &unused); 5321 return ecx & CPUID_EXT_VMX; 5322 } 5323 5324 #define VMX_INVALID_GUEST_STATE 0x80000021 5325 5326 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 5327 { 5328 X86CPU *cpu = X86_CPU(cs); 5329 uint64_t code; 5330 int ret; 5331 bool ctx_invalid; 5332 KVMState *state; 5333 5334 switch (run->exit_reason) { 5335 case KVM_EXIT_HLT: 5336 DPRINTF("handle_hlt\n"); 5337 bql_lock(); 5338 ret = kvm_handle_halt(cpu); 5339 bql_unlock(); 5340 break; 5341 case KVM_EXIT_SET_TPR: 5342 ret = 0; 5343 break; 5344 case KVM_EXIT_TPR_ACCESS: 5345 bql_lock(); 5346 ret = kvm_handle_tpr_access(cpu); 5347 bql_unlock(); 5348 break; 5349 case KVM_EXIT_FAIL_ENTRY: 5350 code = run->fail_entry.hardware_entry_failure_reason; 5351 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", 5352 code); 5353 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { 5354 fprintf(stderr, 5355 "\nIf you're running a guest on an Intel machine without " 5356 "unrestricted mode\n" 5357 "support, the failure can be most likely due to the guest " 5358 "entering an invalid\n" 5359 "state for Intel VT. For example, the guest maybe running " 5360 "in big real mode\n" 5361 "which is not supported on less recent Intel processors." 5362 "\n\n"); 5363 } 5364 ret = -1; 5365 break; 5366 case KVM_EXIT_EXCEPTION: 5367 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", 5368 run->ex.exception, run->ex.error_code); 5369 ret = -1; 5370 break; 5371 case KVM_EXIT_DEBUG: 5372 DPRINTF("kvm_exit_debug\n"); 5373 bql_lock(); 5374 ret = kvm_handle_debug(cpu, &run->debug.arch); 5375 bql_unlock(); 5376 break; 5377 case KVM_EXIT_HYPERV: 5378 ret = kvm_hv_handle_exit(cpu, &run->hyperv); 5379 break; 5380 case KVM_EXIT_IOAPIC_EOI: 5381 ioapic_eoi_broadcast(run->eoi.vector); 5382 ret = 0; 5383 break; 5384 case KVM_EXIT_X86_BUS_LOCK: 5385 /* already handled in kvm_arch_post_run */ 5386 ret = 0; 5387 break; 5388 case KVM_EXIT_NOTIFY: 5389 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID); 5390 state = KVM_STATE(current_accel()); 5391 if (ctx_invalid || 5392 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) { 5393 warn_report("KVM internal error: Encountered a notify exit " 5394 "with invalid context in guest."); 5395 ret = -1; 5396 } else { 5397 warn_report_once("KVM: Encountered a notify exit with valid " 5398 "context in guest. " 5399 "The guest could be misbehaving."); 5400 ret = 0; 5401 } 5402 break; 5403 case KVM_EXIT_X86_RDMSR: 5404 /* We only enable MSR filtering, any other exit is bogus */ 5405 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER); 5406 ret = kvm_handle_rdmsr(cpu, run); 5407 break; 5408 case KVM_EXIT_X86_WRMSR: 5409 /* We only enable MSR filtering, any other exit is bogus */ 5410 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER); 5411 ret = kvm_handle_wrmsr(cpu, run); 5412 break; 5413 #ifdef CONFIG_XEN_EMU 5414 case KVM_EXIT_XEN: 5415 ret = kvm_xen_handle_exit(cpu, &run->xen); 5416 break; 5417 #endif 5418 default: 5419 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 5420 ret = -1; 5421 break; 5422 } 5423 5424 return ret; 5425 } 5426 5427 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 5428 { 5429 X86CPU *cpu = X86_CPU(cs); 5430 CPUX86State *env = &cpu->env; 5431 5432 kvm_cpu_synchronize_state(cs); 5433 return !(env->cr[0] & CR0_PE_MASK) || 5434 ((env->segs[R_CS].selector & 3) != 3); 5435 } 5436 5437 void kvm_arch_init_irq_routing(KVMState *s) 5438 { 5439 /* We know at this point that we're using the in-kernel 5440 * irqchip, so we can use irqfds, and on x86 we know 5441 * we can use msi via irqfd and GSI routing. 5442 */ 5443 kvm_msi_via_irqfd_allowed = true; 5444 kvm_gsi_routing_allowed = true; 5445 5446 if (kvm_irqchip_is_split()) { 5447 KVMRouteChange c = kvm_irqchip_begin_route_changes(s); 5448 int i; 5449 5450 /* If the ioapic is in QEMU and the lapics are in KVM, reserve 5451 MSI routes for signaling interrupts to the local apics. */ 5452 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 5453 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) { 5454 error_report("Could not enable split IRQ mode."); 5455 exit(1); 5456 } 5457 } 5458 kvm_irqchip_commit_route_changes(&c); 5459 } 5460 } 5461 5462 int kvm_arch_irqchip_create(KVMState *s) 5463 { 5464 int ret; 5465 if (kvm_kernel_irqchip_split()) { 5466 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24); 5467 if (ret) { 5468 error_report("Could not enable split irqchip mode: %s", 5469 strerror(-ret)); 5470 exit(1); 5471 } else { 5472 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n"); 5473 kvm_split_irqchip = true; 5474 return 1; 5475 } 5476 } else { 5477 return 0; 5478 } 5479 } 5480 5481 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address) 5482 { 5483 CPUX86State *env; 5484 uint64_t ext_id; 5485 5486 if (!first_cpu) { 5487 return address; 5488 } 5489 env = &X86_CPU(first_cpu)->env; 5490 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) { 5491 return address; 5492 } 5493 5494 /* 5495 * If the remappable format bit is set, or the upper bits are 5496 * already set in address_hi, or the low extended bits aren't 5497 * there anyway, do nothing. 5498 */ 5499 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT); 5500 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) { 5501 return address; 5502 } 5503 5504 address &= ~ext_id; 5505 address |= ext_id << 35; 5506 return address; 5507 } 5508 5509 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 5510 uint64_t address, uint32_t data, PCIDevice *dev) 5511 { 5512 X86IOMMUState *iommu = x86_iommu_get_default(); 5513 5514 if (iommu) { 5515 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu); 5516 5517 if (class->int_remap) { 5518 int ret; 5519 MSIMessage src, dst; 5520 5521 src.address = route->u.msi.address_hi; 5522 src.address <<= VTD_MSI_ADDR_HI_SHIFT; 5523 src.address |= route->u.msi.address_lo; 5524 src.data = route->u.msi.data; 5525 5526 ret = class->int_remap(iommu, &src, &dst, dev ? \ 5527 pci_requester_id(dev) : \ 5528 X86_IOMMU_SID_INVALID); 5529 if (ret) { 5530 trace_kvm_x86_fixup_msi_error(route->gsi); 5531 return 1; 5532 } 5533 5534 /* 5535 * Handled untranslated compatibility format interrupt with 5536 * extended destination ID in the low bits 11-5. */ 5537 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address); 5538 5539 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT; 5540 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK; 5541 route->u.msi.data = dst.data; 5542 return 0; 5543 } 5544 } 5545 5546 #ifdef CONFIG_XEN_EMU 5547 if (xen_mode == XEN_EMULATE) { 5548 int handled = xen_evtchn_translate_pirq_msi(route, address, data); 5549 5550 /* 5551 * If it was a PIRQ and successfully routed (handled == 0) or it was 5552 * an error (handled < 0), return. If it wasn't a PIRQ, keep going. 5553 */ 5554 if (handled <= 0) { 5555 return handled; 5556 } 5557 } 5558 #endif 5559 5560 address = kvm_swizzle_msi_ext_dest_id(address); 5561 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT; 5562 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK; 5563 return 0; 5564 } 5565 5566 typedef struct MSIRouteEntry MSIRouteEntry; 5567 5568 struct MSIRouteEntry { 5569 PCIDevice *dev; /* Device pointer */ 5570 int vector; /* MSI/MSIX vector index */ 5571 int virq; /* Virtual IRQ index */ 5572 QLIST_ENTRY(MSIRouteEntry) list; 5573 }; 5574 5575 /* List of used GSI routes */ 5576 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \ 5577 QLIST_HEAD_INITIALIZER(msi_route_list); 5578 5579 void kvm_update_msi_routes_all(void *private, bool global, 5580 uint32_t index, uint32_t mask) 5581 { 5582 int cnt = 0, vector; 5583 MSIRouteEntry *entry; 5584 MSIMessage msg; 5585 PCIDevice *dev; 5586 5587 /* TODO: explicit route update */ 5588 QLIST_FOREACH(entry, &msi_route_list, list) { 5589 cnt++; 5590 vector = entry->vector; 5591 dev = entry->dev; 5592 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) { 5593 msg = msix_get_message(dev, vector); 5594 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) { 5595 msg = msi_get_message(dev, vector); 5596 } else { 5597 /* 5598 * Either MSI/MSIX is disabled for the device, or the 5599 * specific message was masked out. Skip this one. 5600 */ 5601 continue; 5602 } 5603 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev); 5604 } 5605 kvm_irqchip_commit_routes(kvm_state); 5606 trace_kvm_x86_update_msi_routes(cnt); 5607 } 5608 5609 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 5610 int vector, PCIDevice *dev) 5611 { 5612 static bool notify_list_inited = false; 5613 MSIRouteEntry *entry; 5614 5615 if (!dev) { 5616 /* These are (possibly) IOAPIC routes only used for split 5617 * kernel irqchip mode, while what we are housekeeping are 5618 * PCI devices only. */ 5619 return 0; 5620 } 5621 5622 entry = g_new0(MSIRouteEntry, 1); 5623 entry->dev = dev; 5624 entry->vector = vector; 5625 entry->virq = route->gsi; 5626 QLIST_INSERT_HEAD(&msi_route_list, entry, list); 5627 5628 trace_kvm_x86_add_msi_route(route->gsi); 5629 5630 if (!notify_list_inited) { 5631 /* For the first time we do add route, add ourselves into 5632 * IOMMU's IEC notify list if needed. */ 5633 X86IOMMUState *iommu = x86_iommu_get_default(); 5634 if (iommu) { 5635 x86_iommu_iec_register_notifier(iommu, 5636 kvm_update_msi_routes_all, 5637 NULL); 5638 } 5639 notify_list_inited = true; 5640 } 5641 return 0; 5642 } 5643 5644 int kvm_arch_release_virq_post(int virq) 5645 { 5646 MSIRouteEntry *entry, *next; 5647 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) { 5648 if (entry->virq == virq) { 5649 trace_kvm_x86_remove_msi_route(virq); 5650 QLIST_REMOVE(entry, list); 5651 g_free(entry); 5652 break; 5653 } 5654 } 5655 return 0; 5656 } 5657 5658 int kvm_arch_msi_data_to_gsi(uint32_t data) 5659 { 5660 abort(); 5661 } 5662 5663 bool kvm_has_waitpkg(void) 5664 { 5665 return has_msr_umwait; 5666 } 5667 5668 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 5669 5670 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask) 5671 { 5672 KVMState *s = kvm_state; 5673 uint64_t supported; 5674 5675 mask &= XSTATE_DYNAMIC_MASK; 5676 if (!mask) { 5677 return; 5678 } 5679 /* 5680 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0]. 5681 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned 5682 * about them already because they are not supported features. 5683 */ 5684 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX); 5685 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32; 5686 mask &= supported; 5687 5688 while (mask) { 5689 int bit = ctz64(mask); 5690 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit); 5691 if (rc) { 5692 /* 5693 * Older kernel version (<5.17) do not support 5694 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return 5695 * any dynamic feature from kvm_arch_get_supported_cpuid. 5696 */ 5697 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure " 5698 "for feature bit %d", bit); 5699 } 5700 mask &= ~BIT_ULL(bit); 5701 } 5702 } 5703 5704 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp) 5705 { 5706 KVMState *s = KVM_STATE(obj); 5707 return s->notify_vmexit; 5708 } 5709 5710 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp) 5711 { 5712 KVMState *s = KVM_STATE(obj); 5713 5714 if (s->fd != -1) { 5715 error_setg(errp, "Cannot set properties after the accelerator has been initialized"); 5716 return; 5717 } 5718 5719 s->notify_vmexit = value; 5720 } 5721 5722 static void kvm_arch_get_notify_window(Object *obj, Visitor *v, 5723 const char *name, void *opaque, 5724 Error **errp) 5725 { 5726 KVMState *s = KVM_STATE(obj); 5727 uint32_t value = s->notify_window; 5728 5729 visit_type_uint32(v, name, &value, errp); 5730 } 5731 5732 static void kvm_arch_set_notify_window(Object *obj, Visitor *v, 5733 const char *name, void *opaque, 5734 Error **errp) 5735 { 5736 KVMState *s = KVM_STATE(obj); 5737 uint32_t value; 5738 5739 if (s->fd != -1) { 5740 error_setg(errp, "Cannot set properties after the accelerator has been initialized"); 5741 return; 5742 } 5743 5744 if (!visit_type_uint32(v, name, &value, errp)) { 5745 return; 5746 } 5747 5748 s->notify_window = value; 5749 } 5750 5751 static void kvm_arch_get_xen_version(Object *obj, Visitor *v, 5752 const char *name, void *opaque, 5753 Error **errp) 5754 { 5755 KVMState *s = KVM_STATE(obj); 5756 uint32_t value = s->xen_version; 5757 5758 visit_type_uint32(v, name, &value, errp); 5759 } 5760 5761 static void kvm_arch_set_xen_version(Object *obj, Visitor *v, 5762 const char *name, void *opaque, 5763 Error **errp) 5764 { 5765 KVMState *s = KVM_STATE(obj); 5766 Error *error = NULL; 5767 uint32_t value; 5768 5769 visit_type_uint32(v, name, &value, &error); 5770 if (error) { 5771 error_propagate(errp, error); 5772 return; 5773 } 5774 5775 s->xen_version = value; 5776 if (value && xen_mode == XEN_DISABLED) { 5777 xen_mode = XEN_EMULATE; 5778 } 5779 } 5780 5781 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v, 5782 const char *name, void *opaque, 5783 Error **errp) 5784 { 5785 KVMState *s = KVM_STATE(obj); 5786 uint16_t value = s->xen_gnttab_max_frames; 5787 5788 visit_type_uint16(v, name, &value, errp); 5789 } 5790 5791 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v, 5792 const char *name, void *opaque, 5793 Error **errp) 5794 { 5795 KVMState *s = KVM_STATE(obj); 5796 Error *error = NULL; 5797 uint16_t value; 5798 5799 visit_type_uint16(v, name, &value, &error); 5800 if (error) { 5801 error_propagate(errp, error); 5802 return; 5803 } 5804 5805 s->xen_gnttab_max_frames = value; 5806 } 5807 5808 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v, 5809 const char *name, void *opaque, 5810 Error **errp) 5811 { 5812 KVMState *s = KVM_STATE(obj); 5813 uint16_t value = s->xen_evtchn_max_pirq; 5814 5815 visit_type_uint16(v, name, &value, errp); 5816 } 5817 5818 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v, 5819 const char *name, void *opaque, 5820 Error **errp) 5821 { 5822 KVMState *s = KVM_STATE(obj); 5823 Error *error = NULL; 5824 uint16_t value; 5825 5826 visit_type_uint16(v, name, &value, &error); 5827 if (error) { 5828 error_propagate(errp, error); 5829 return; 5830 } 5831 5832 s->xen_evtchn_max_pirq = value; 5833 } 5834 5835 void kvm_arch_accel_class_init(ObjectClass *oc) 5836 { 5837 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption", 5838 &NotifyVmexitOption_lookup, 5839 kvm_arch_get_notify_vmexit, 5840 kvm_arch_set_notify_vmexit); 5841 object_class_property_set_description(oc, "notify-vmexit", 5842 "Enable notify VM exit"); 5843 5844 object_class_property_add(oc, "notify-window", "uint32", 5845 kvm_arch_get_notify_window, 5846 kvm_arch_set_notify_window, 5847 NULL, NULL); 5848 object_class_property_set_description(oc, "notify-window", 5849 "Clock cycles without an event window " 5850 "after which a notification VM exit occurs"); 5851 5852 object_class_property_add(oc, "xen-version", "uint32", 5853 kvm_arch_get_xen_version, 5854 kvm_arch_set_xen_version, 5855 NULL, NULL); 5856 object_class_property_set_description(oc, "xen-version", 5857 "Xen version to be emulated " 5858 "(in XENVER_version form " 5859 "e.g. 0x4000a for 4.10)"); 5860 5861 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16", 5862 kvm_arch_get_xen_gnttab_max_frames, 5863 kvm_arch_set_xen_gnttab_max_frames, 5864 NULL, NULL); 5865 object_class_property_set_description(oc, "xen-gnttab-max-frames", 5866 "Maximum number of grant table frames"); 5867 5868 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16", 5869 kvm_arch_get_xen_evtchn_max_pirq, 5870 kvm_arch_set_xen_evtchn_max_pirq, 5871 NULL, NULL); 5872 object_class_property_set_description(oc, "xen-evtchn-max-pirq", 5873 "Maximum number of Xen PIRQs"); 5874 } 5875 5876 void kvm_set_max_apic_id(uint32_t max_apic_id) 5877 { 5878 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id); 5879 } 5880