1 /* 2 * Copyright (c) 2003-2008 Fabrice Bellard 3 * Copyright (C) 2016 Veertu Inc, 4 * Copyright (C) 2017 Google Inc, 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 22 #include "qemu-common.h" 23 #include "x86hvf.h" 24 #include "vmx.h" 25 #include "vmcs.h" 26 #include "cpu.h" 27 #include "x86_descr.h" 28 #include "x86_decode.h" 29 #include "sysemu/hw_accel.h" 30 31 #include "hw/i386/apic_internal.h" 32 33 #include <Hypervisor/hv.h> 34 #include <Hypervisor/hv_vmx.h> 35 36 void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, 37 SegmentCache *qseg, bool is_tr) 38 { 39 vmx_seg->sel = qseg->selector; 40 vmx_seg->base = qseg->base; 41 vmx_seg->limit = qseg->limit; 42 43 if (!qseg->selector && !x86_is_real(cpu) && !is_tr) { 44 /* the TR register is usable after processor reset despite 45 * having a null selector */ 46 vmx_seg->ar = 1 << 16; 47 return; 48 } 49 vmx_seg->ar = (qseg->flags >> DESC_TYPE_SHIFT) & 0xf; 50 vmx_seg->ar |= ((qseg->flags >> DESC_G_SHIFT) & 1) << 15; 51 vmx_seg->ar |= ((qseg->flags >> DESC_B_SHIFT) & 1) << 14; 52 vmx_seg->ar |= ((qseg->flags >> DESC_L_SHIFT) & 1) << 13; 53 vmx_seg->ar |= ((qseg->flags >> DESC_AVL_SHIFT) & 1) << 12; 54 vmx_seg->ar |= ((qseg->flags >> DESC_P_SHIFT) & 1) << 7; 55 vmx_seg->ar |= ((qseg->flags >> DESC_DPL_SHIFT) & 3) << 5; 56 vmx_seg->ar |= ((qseg->flags >> DESC_S_SHIFT) & 1) << 4; 57 } 58 59 void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg) 60 { 61 qseg->limit = vmx_seg->limit; 62 qseg->base = vmx_seg->base; 63 qseg->selector = vmx_seg->sel; 64 qseg->flags = ((vmx_seg->ar & 0xf) << DESC_TYPE_SHIFT) | 65 (((vmx_seg->ar >> 4) & 1) << DESC_S_SHIFT) | 66 (((vmx_seg->ar >> 5) & 3) << DESC_DPL_SHIFT) | 67 (((vmx_seg->ar >> 7) & 1) << DESC_P_SHIFT) | 68 (((vmx_seg->ar >> 12) & 1) << DESC_AVL_SHIFT) | 69 (((vmx_seg->ar >> 13) & 1) << DESC_L_SHIFT) | 70 (((vmx_seg->ar >> 14) & 1) << DESC_B_SHIFT) | 71 (((vmx_seg->ar >> 15) & 1) << DESC_G_SHIFT); 72 } 73 74 void hvf_put_xsave(CPUState *cpu_state) 75 { 76 void *xsave = X86_CPU(cpu_state)->env.xsave_buf; 77 uint32_t xsave_len = X86_CPU(cpu_state)->env.xsave_buf_len; 78 79 x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave, xsave_len); 80 81 if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) { 82 abort(); 83 } 84 } 85 86 void hvf_put_segments(CPUState *cpu_state) 87 { 88 CPUX86State *env = &X86_CPU(cpu_state)->env; 89 struct vmx_segment seg; 90 91 wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); 92 wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); 93 94 wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); 95 wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); 96 97 /* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ 98 wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); 99 vmx_update_tpr(cpu_state); 100 wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); 101 102 macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]); 103 macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]); 104 105 hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false); 106 vmx_write_segment_descriptor(cpu_state, &seg, R_CS); 107 108 hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false); 109 vmx_write_segment_descriptor(cpu_state, &seg, R_DS); 110 111 hvf_set_segment(cpu_state, &seg, &env->segs[R_ES], false); 112 vmx_write_segment_descriptor(cpu_state, &seg, R_ES); 113 114 hvf_set_segment(cpu_state, &seg, &env->segs[R_SS], false); 115 vmx_write_segment_descriptor(cpu_state, &seg, R_SS); 116 117 hvf_set_segment(cpu_state, &seg, &env->segs[R_FS], false); 118 vmx_write_segment_descriptor(cpu_state, &seg, R_FS); 119 120 hvf_set_segment(cpu_state, &seg, &env->segs[R_GS], false); 121 vmx_write_segment_descriptor(cpu_state, &seg, R_GS); 122 123 hvf_set_segment(cpu_state, &seg, &env->tr, true); 124 vmx_write_segment_descriptor(cpu_state, &seg, R_TR); 125 126 hvf_set_segment(cpu_state, &seg, &env->ldt, false); 127 vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR); 128 129 hv_vcpu_flush(cpu_state->hvf->fd); 130 } 131 132 void hvf_put_msrs(CPUState *cpu_state) 133 { 134 CPUX86State *env = &X86_CPU(cpu_state)->env; 135 136 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, 137 env->sysenter_cs); 138 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, 139 env->sysenter_esp); 140 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, 141 env->sysenter_eip); 142 143 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star); 144 145 #ifdef TARGET_X86_64 146 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar); 147 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase); 148 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask); 149 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar); 150 #endif 151 152 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base); 153 hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base); 154 } 155 156 157 void hvf_get_xsave(CPUState *cpu_state) 158 { 159 void *xsave = X86_CPU(cpu_state)->env.xsave_buf; 160 uint32_t xsave_len = X86_CPU(cpu_state)->env.xsave_buf_len; 161 162 if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) { 163 abort(); 164 } 165 166 x86_cpu_xrstor_all_areas(X86_CPU(cpu_state), xsave, xsave_len); 167 } 168 169 void hvf_get_segments(CPUState *cpu_state) 170 { 171 CPUX86State *env = &X86_CPU(cpu_state)->env; 172 173 struct vmx_segment seg; 174 175 env->interrupt_injected = -1; 176 177 vmx_read_segment_descriptor(cpu_state, &seg, R_CS); 178 hvf_get_segment(&env->segs[R_CS], &seg); 179 180 vmx_read_segment_descriptor(cpu_state, &seg, R_DS); 181 hvf_get_segment(&env->segs[R_DS], &seg); 182 183 vmx_read_segment_descriptor(cpu_state, &seg, R_ES); 184 hvf_get_segment(&env->segs[R_ES], &seg); 185 186 vmx_read_segment_descriptor(cpu_state, &seg, R_FS); 187 hvf_get_segment(&env->segs[R_FS], &seg); 188 189 vmx_read_segment_descriptor(cpu_state, &seg, R_GS); 190 hvf_get_segment(&env->segs[R_GS], &seg); 191 192 vmx_read_segment_descriptor(cpu_state, &seg, R_SS); 193 hvf_get_segment(&env->segs[R_SS], &seg); 194 195 vmx_read_segment_descriptor(cpu_state, &seg, R_TR); 196 hvf_get_segment(&env->tr, &seg); 197 198 vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR); 199 hvf_get_segment(&env->ldt, &seg); 200 201 env->idt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT); 202 env->idt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE); 203 env->gdt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT); 204 env->gdt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE); 205 206 env->cr[0] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0); 207 env->cr[2] = 0; 208 env->cr[3] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3); 209 env->cr[4] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4); 210 211 env->efer = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER); 212 } 213 214 void hvf_get_msrs(CPUState *cpu_state) 215 { 216 CPUX86State *env = &X86_CPU(cpu_state)->env; 217 uint64_t tmp; 218 219 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); 220 env->sysenter_cs = tmp; 221 222 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); 223 env->sysenter_esp = tmp; 224 225 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); 226 env->sysenter_eip = tmp; 227 228 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star); 229 230 #ifdef TARGET_X86_64 231 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar); 232 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase); 233 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask); 234 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar); 235 #endif 236 237 hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp); 238 239 env->tsc = rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET); 240 } 241 242 int hvf_put_registers(CPUState *cpu_state) 243 { 244 X86CPU *x86cpu = X86_CPU(cpu_state); 245 CPUX86State *env = &x86cpu->env; 246 247 wreg(cpu_state->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); 248 wreg(cpu_state->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); 249 wreg(cpu_state->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); 250 wreg(cpu_state->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); 251 wreg(cpu_state->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); 252 wreg(cpu_state->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); 253 wreg(cpu_state->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); 254 wreg(cpu_state->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); 255 wreg(cpu_state->hvf->fd, HV_X86_R8, env->regs[8]); 256 wreg(cpu_state->hvf->fd, HV_X86_R9, env->regs[9]); 257 wreg(cpu_state->hvf->fd, HV_X86_R10, env->regs[10]); 258 wreg(cpu_state->hvf->fd, HV_X86_R11, env->regs[11]); 259 wreg(cpu_state->hvf->fd, HV_X86_R12, env->regs[12]); 260 wreg(cpu_state->hvf->fd, HV_X86_R13, env->regs[13]); 261 wreg(cpu_state->hvf->fd, HV_X86_R14, env->regs[14]); 262 wreg(cpu_state->hvf->fd, HV_X86_R15, env->regs[15]); 263 wreg(cpu_state->hvf->fd, HV_X86_RFLAGS, env->eflags); 264 wreg(cpu_state->hvf->fd, HV_X86_RIP, env->eip); 265 266 wreg(cpu_state->hvf->fd, HV_X86_XCR0, env->xcr0); 267 268 hvf_put_xsave(cpu_state); 269 270 hvf_put_segments(cpu_state); 271 272 hvf_put_msrs(cpu_state); 273 274 wreg(cpu_state->hvf->fd, HV_X86_DR0, env->dr[0]); 275 wreg(cpu_state->hvf->fd, HV_X86_DR1, env->dr[1]); 276 wreg(cpu_state->hvf->fd, HV_X86_DR2, env->dr[2]); 277 wreg(cpu_state->hvf->fd, HV_X86_DR3, env->dr[3]); 278 wreg(cpu_state->hvf->fd, HV_X86_DR4, env->dr[4]); 279 wreg(cpu_state->hvf->fd, HV_X86_DR5, env->dr[5]); 280 wreg(cpu_state->hvf->fd, HV_X86_DR6, env->dr[6]); 281 wreg(cpu_state->hvf->fd, HV_X86_DR7, env->dr[7]); 282 283 return 0; 284 } 285 286 int hvf_get_registers(CPUState *cpu_state) 287 { 288 X86CPU *x86cpu = X86_CPU(cpu_state); 289 CPUX86State *env = &x86cpu->env; 290 291 env->regs[R_EAX] = rreg(cpu_state->hvf->fd, HV_X86_RAX); 292 env->regs[R_EBX] = rreg(cpu_state->hvf->fd, HV_X86_RBX); 293 env->regs[R_ECX] = rreg(cpu_state->hvf->fd, HV_X86_RCX); 294 env->regs[R_EDX] = rreg(cpu_state->hvf->fd, HV_X86_RDX); 295 env->regs[R_EBP] = rreg(cpu_state->hvf->fd, HV_X86_RBP); 296 env->regs[R_ESP] = rreg(cpu_state->hvf->fd, HV_X86_RSP); 297 env->regs[R_ESI] = rreg(cpu_state->hvf->fd, HV_X86_RSI); 298 env->regs[R_EDI] = rreg(cpu_state->hvf->fd, HV_X86_RDI); 299 env->regs[8] = rreg(cpu_state->hvf->fd, HV_X86_R8); 300 env->regs[9] = rreg(cpu_state->hvf->fd, HV_X86_R9); 301 env->regs[10] = rreg(cpu_state->hvf->fd, HV_X86_R10); 302 env->regs[11] = rreg(cpu_state->hvf->fd, HV_X86_R11); 303 env->regs[12] = rreg(cpu_state->hvf->fd, HV_X86_R12); 304 env->regs[13] = rreg(cpu_state->hvf->fd, HV_X86_R13); 305 env->regs[14] = rreg(cpu_state->hvf->fd, HV_X86_R14); 306 env->regs[15] = rreg(cpu_state->hvf->fd, HV_X86_R15); 307 308 env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); 309 env->eip = rreg(cpu_state->hvf->fd, HV_X86_RIP); 310 311 hvf_get_xsave(cpu_state); 312 env->xcr0 = rreg(cpu_state->hvf->fd, HV_X86_XCR0); 313 314 hvf_get_segments(cpu_state); 315 hvf_get_msrs(cpu_state); 316 317 env->dr[0] = rreg(cpu_state->hvf->fd, HV_X86_DR0); 318 env->dr[1] = rreg(cpu_state->hvf->fd, HV_X86_DR1); 319 env->dr[2] = rreg(cpu_state->hvf->fd, HV_X86_DR2); 320 env->dr[3] = rreg(cpu_state->hvf->fd, HV_X86_DR3); 321 env->dr[4] = rreg(cpu_state->hvf->fd, HV_X86_DR4); 322 env->dr[5] = rreg(cpu_state->hvf->fd, HV_X86_DR5); 323 env->dr[6] = rreg(cpu_state->hvf->fd, HV_X86_DR6); 324 env->dr[7] = rreg(cpu_state->hvf->fd, HV_X86_DR7); 325 326 x86_update_hflags(env); 327 return 0; 328 } 329 330 static void vmx_set_int_window_exiting(CPUState *cpu) 331 { 332 uint64_t val; 333 val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); 334 wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | 335 VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); 336 } 337 338 void vmx_clear_int_window_exiting(CPUState *cpu) 339 { 340 uint64_t val; 341 val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); 342 wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & 343 ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); 344 } 345 346 bool hvf_inject_interrupts(CPUState *cpu_state) 347 { 348 X86CPU *x86cpu = X86_CPU(cpu_state); 349 CPUX86State *env = &x86cpu->env; 350 351 uint8_t vector; 352 uint64_t intr_type; 353 bool have_event = true; 354 if (env->interrupt_injected != -1) { 355 vector = env->interrupt_injected; 356 if (env->ins_len) { 357 intr_type = VMCS_INTR_T_SWINTR; 358 } else { 359 intr_type = VMCS_INTR_T_HWINTR; 360 } 361 } else if (env->exception_nr != -1) { 362 vector = env->exception_nr; 363 if (vector == EXCP03_INT3 || vector == EXCP04_INTO) { 364 intr_type = VMCS_INTR_T_SWEXCEPTION; 365 } else { 366 intr_type = VMCS_INTR_T_HWEXCEPTION; 367 } 368 } else if (env->nmi_injected) { 369 vector = EXCP02_NMI; 370 intr_type = VMCS_INTR_T_NMI; 371 } else { 372 have_event = false; 373 } 374 375 uint64_t info = 0; 376 if (have_event) { 377 info = vector | intr_type | VMCS_INTR_VALID; 378 uint64_t reason = rvmcs(cpu_state->hvf->fd, VMCS_EXIT_REASON); 379 if (env->nmi_injected && reason != EXIT_REASON_TASK_SWITCH) { 380 vmx_clear_nmi_blocking(cpu_state); 381 } 382 383 if (!(env->hflags2 & HF2_NMI_MASK) || intr_type != VMCS_INTR_T_NMI) { 384 info &= ~(1 << 12); /* clear undefined bit */ 385 if (intr_type == VMCS_INTR_T_SWINTR || 386 intr_type == VMCS_INTR_T_SWEXCEPTION) { 387 wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); 388 } 389 390 if (env->has_error_code) { 391 wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, 392 env->error_code); 393 /* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */ 394 info |= VMCS_INTR_DEL_ERRCODE; 395 } 396 /*printf("reinject %lx err %d\n", info, err);*/ 397 wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); 398 }; 399 } 400 401 if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) { 402 if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { 403 cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI; 404 info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; 405 wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); 406 } else { 407 vmx_set_nmi_window_exiting(cpu_state); 408 } 409 } 410 411 if (!(env->hflags & HF_INHIBIT_IRQ_MASK) && 412 (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && 413 (env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) { 414 int line = cpu_get_pic_interrupt(&x86cpu->env); 415 cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD; 416 if (line >= 0) { 417 wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, line | 418 VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); 419 } 420 } 421 if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) { 422 vmx_set_int_window_exiting(cpu_state); 423 } 424 return (cpu_state->interrupt_request 425 & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)); 426 } 427 428 int hvf_process_events(CPUState *cpu_state) 429 { 430 X86CPU *cpu = X86_CPU(cpu_state); 431 CPUX86State *env = &cpu->env; 432 433 if (!cpu_state->vcpu_dirty) { 434 /* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */ 435 env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); 436 } 437 438 if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { 439 cpu_synchronize_state(cpu_state); 440 do_cpu_init(cpu); 441 } 442 443 if (cpu_state->interrupt_request & CPU_INTERRUPT_POLL) { 444 cpu_state->interrupt_request &= ~CPU_INTERRUPT_POLL; 445 apic_poll_irq(cpu->apic_state); 446 } 447 if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && 448 (env->eflags & IF_MASK)) || 449 (cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) { 450 cpu_state->halted = 0; 451 } 452 if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) { 453 cpu_synchronize_state(cpu_state); 454 do_cpu_sipi(cpu); 455 } 456 if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) { 457 cpu_state->interrupt_request &= ~CPU_INTERRUPT_TPR; 458 cpu_synchronize_state(cpu_state); 459 apic_handle_tpr_access_report(cpu->apic_state, env->eip, 460 env->tpr_access_type); 461 } 462 return cpu_state->halted; 463 } 464