1 /* 2 * Copyright (C) 2016 Veertu Inc, 3 * Copyright (C) 2017 Google Inc, 4 * Based on Veertu vddh/vmm/vmx.h 5 * 6 * Interfaces to Hypervisor.framework to read/write X86 registers and VMCS. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this program; if not, see <http://www.gnu.org/licenses/>. 20 * 21 * This file contain code under public domain from the hvdos project: 22 * https://github.com/mist64/hvdos 23 */ 24 25 #ifndef VMX_H 26 #define VMX_H 27 28 #include <stdint.h> 29 #include <Hypervisor/hv.h> 30 #include <Hypervisor/hv_vmx.h> 31 #include "vmcs.h" 32 #include "cpu.h" 33 #include "x86.h" 34 35 #include "exec/address-spaces.h" 36 37 static inline uint64_t rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg) 38 { 39 uint64_t v; 40 41 if (hv_vcpu_read_register(vcpu, reg, &v)) { 42 abort(); 43 } 44 45 return v; 46 } 47 48 /* write GPR */ 49 static inline void wreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t v) 50 { 51 if (hv_vcpu_write_register(vcpu, reg, v)) { 52 abort(); 53 } 54 } 55 56 /* read VMCS field */ 57 static inline uint64_t rvmcs(hv_vcpuid_t vcpu, uint32_t field) 58 { 59 uint64_t v; 60 61 hv_vmx_vcpu_read_vmcs(vcpu, field, &v); 62 63 return v; 64 } 65 66 /* write VMCS field */ 67 static inline void wvmcs(hv_vcpuid_t vcpu, uint32_t field, uint64_t v) 68 { 69 hv_vmx_vcpu_write_vmcs(vcpu, field, v); 70 } 71 72 /* desired control word constrained by hardware/hypervisor capabilities */ 73 static inline uint64_t cap2ctrl(uint64_t cap, uint64_t ctrl) 74 { 75 return (ctrl | (cap & 0xffffffff)) & (cap >> 32); 76 } 77 78 #define VM_ENTRY_GUEST_LMA (1LL << 9) 79 80 #define AR_TYPE_ACCESSES_MASK 1 81 #define AR_TYPE_READABLE_MASK (1 << 1) 82 #define AR_TYPE_WRITEABLE_MASK (1 << 2) 83 #define AR_TYPE_CODE_MASK (1 << 3) 84 #define AR_TYPE_MASK 0x0f 85 #define AR_TYPE_BUSY_64_TSS 11 86 #define AR_TYPE_BUSY_32_TSS 11 87 #define AR_TYPE_BUSY_16_TSS 3 88 #define AR_TYPE_LDT 2 89 90 static void enter_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer) 91 { 92 uint64_t entry_ctls; 93 94 efer |= MSR_EFER_LMA; 95 wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer); 96 entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS); 97 wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) | 98 VM_ENTRY_GUEST_LMA); 99 100 uint64_t guest_tr_ar = rvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS); 101 if ((efer & MSR_EFER_LME) && 102 (guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { 103 wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS, 104 (guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS); 105 } 106 } 107 108 static void exit_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer) 109 { 110 uint64_t entry_ctls; 111 112 entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS); 113 wvmcs(vcpu, VMCS_ENTRY_CTLS, entry_ctls & ~VM_ENTRY_GUEST_LMA); 114 115 efer &= ~MSR_EFER_LMA; 116 wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer); 117 } 118 119 static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0) 120 { 121 int i; 122 uint64_t pdpte[4] = {0, 0, 0, 0}; 123 uint64_t efer = rvmcs(vcpu, VMCS_GUEST_IA32_EFER); 124 uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0); 125 126 if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && 127 !(efer & MSR_EFER_LME)) { 128 address_space_rw(&address_space_memory, 129 rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, 130 MEMTXATTRS_UNSPECIFIED, 131 (uint8_t *)pdpte, 32, 0); 132 } 133 134 for (i = 0; i < 4; i++) { 135 wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]); 136 } 137 138 wvmcs(vcpu, VMCS_CR0_MASK, CR0_CD | CR0_NE | CR0_PG); 139 wvmcs(vcpu, VMCS_CR0_SHADOW, cr0); 140 141 cr0 &= ~CR0_CD; 142 wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE | CR0_ET); 143 144 if (efer & MSR_EFER_LME) { 145 if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG)) { 146 enter_long_mode(vcpu, cr0, efer); 147 } 148 if (/*(old_cr0 & CR0_PG) &&*/ !(cr0 & CR0_PG)) { 149 exit_long_mode(vcpu, cr0, efer); 150 } 151 } 152 153 hv_vcpu_invalidate_tlb(vcpu); 154 hv_vcpu_flush(vcpu); 155 } 156 157 static inline void macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4) 158 { 159 uint64_t guest_cr4 = cr4 | CR4_VMXE; 160 161 wvmcs(vcpu, VMCS_GUEST_CR4, guest_cr4); 162 wvmcs(vcpu, VMCS_CR4_SHADOW, cr4); 163 164 hv_vcpu_invalidate_tlb(vcpu); 165 hv_vcpu_flush(vcpu); 166 } 167 168 static inline void macvm_set_rip(CPUState *cpu, uint64_t rip) 169 { 170 uint64_t val; 171 172 /* BUG, should take considering overlap.. */ 173 wreg(cpu->hvf_fd, HV_X86_RIP, rip); 174 175 /* after moving forward in rip, we need to clean INTERRUPTABILITY */ 176 val = rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); 177 if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | 178 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { 179 wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, 180 val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | 181 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)); 182 } 183 } 184 185 static inline void vmx_clear_nmi_blocking(CPUState *cpu) 186 { 187 X86CPU *x86_cpu = X86_CPU(cpu); 188 CPUX86State *env = &x86_cpu->env; 189 190 env->hflags2 &= ~HF2_NMI_MASK; 191 uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); 192 gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; 193 wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); 194 } 195 196 static inline void vmx_set_nmi_blocking(CPUState *cpu) 197 { 198 X86CPU *x86_cpu = X86_CPU(cpu); 199 CPUX86State *env = &x86_cpu->env; 200 201 env->hflags2 |= HF2_NMI_MASK; 202 uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); 203 gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING; 204 wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); 205 } 206 207 static inline void vmx_set_nmi_window_exiting(CPUState *cpu) 208 { 209 uint64_t val; 210 val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); 211 wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | 212 VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); 213 214 } 215 216 static inline void vmx_clear_nmi_window_exiting(CPUState *cpu) 217 { 218 219 uint64_t val; 220 val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); 221 wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & 222 ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); 223 } 224 225 #endif 226