169e0a03cSPaolo Bonzini /* 269e0a03cSPaolo Bonzini * Copyright (C) 2016 Veertu Inc, 369e0a03cSPaolo Bonzini * Copyright (C) 2017 Google Inc, 469e0a03cSPaolo Bonzini * Based on Veertu vddh/vmm/vmx.h 569e0a03cSPaolo Bonzini * 669e0a03cSPaolo Bonzini * Interfaces to Hypervisor.framework to read/write X86 registers and VMCS. 769e0a03cSPaolo Bonzini * 869e0a03cSPaolo Bonzini * This program is free software; you can redistribute it and/or 969e0a03cSPaolo Bonzini * modify it under the terms of the GNU Lesser General Public 1069e0a03cSPaolo Bonzini * License as published by the Free Software Foundation; either 118af82b8eSChetan Pant * version 2.1 of the License, or (at your option) any later version. 1269e0a03cSPaolo Bonzini * 1369e0a03cSPaolo Bonzini * This program is distributed in the hope that it will be useful, 1469e0a03cSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 1569e0a03cSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1669e0a03cSPaolo Bonzini * Lesser General Public License for more details. 1769e0a03cSPaolo Bonzini * 1869e0a03cSPaolo Bonzini * You should have received a copy of the GNU Lesser General Public 1969e0a03cSPaolo Bonzini * License along with this program; if not, see <http://www.gnu.org/licenses/>. 20d781e24dSIzik Eidus * 21d781e24dSIzik Eidus * This file contain code under public domain from the hvdos project: 22d781e24dSIzik Eidus * https://github.com/mist64/hvdos 2369e0a03cSPaolo Bonzini */ 2469e0a03cSPaolo Bonzini 2569e0a03cSPaolo Bonzini #ifndef VMX_H 2669e0a03cSPaolo Bonzini #define VMX_H 2769e0a03cSPaolo Bonzini 2869e0a03cSPaolo Bonzini #include <Hypervisor/hv.h> 2969e0a03cSPaolo Bonzini #include <Hypervisor/hv_vmx.h> 3069e0a03cSPaolo Bonzini #include "vmcs.h" 3169e0a03cSPaolo Bonzini #include "cpu.h" 3269e0a03cSPaolo Bonzini #include "x86.h" 33*b533450eSAlexander Graf #include "sysemu/hvf.h" 34*b533450eSAlexander Graf #include "sysemu/hvf_int.h" 3569e0a03cSPaolo Bonzini 3669e0a03cSPaolo Bonzini #include "exec/address-spaces.h" 3769e0a03cSPaolo Bonzini 3869e0a03cSPaolo Bonzini static inline uint64_t rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg) 3969e0a03cSPaolo Bonzini { 4069e0a03cSPaolo Bonzini uint64_t v; 4169e0a03cSPaolo Bonzini 4269e0a03cSPaolo Bonzini if (hv_vcpu_read_register(vcpu, reg, &v)) { 4369e0a03cSPaolo Bonzini abort(); 4469e0a03cSPaolo Bonzini } 4569e0a03cSPaolo Bonzini 4669e0a03cSPaolo Bonzini return v; 4769e0a03cSPaolo Bonzini } 4869e0a03cSPaolo Bonzini 4969e0a03cSPaolo Bonzini /* write GPR */ 5069e0a03cSPaolo Bonzini static inline void wreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t v) 5169e0a03cSPaolo Bonzini { 5269e0a03cSPaolo Bonzini if (hv_vcpu_write_register(vcpu, reg, v)) { 5369e0a03cSPaolo Bonzini abort(); 5469e0a03cSPaolo Bonzini } 5569e0a03cSPaolo Bonzini } 5669e0a03cSPaolo Bonzini 5769e0a03cSPaolo Bonzini /* read VMCS field */ 5869e0a03cSPaolo Bonzini static inline uint64_t rvmcs(hv_vcpuid_t vcpu, uint32_t field) 5969e0a03cSPaolo Bonzini { 6069e0a03cSPaolo Bonzini uint64_t v; 6169e0a03cSPaolo Bonzini 6269e0a03cSPaolo Bonzini hv_vmx_vcpu_read_vmcs(vcpu, field, &v); 6369e0a03cSPaolo Bonzini 6469e0a03cSPaolo Bonzini return v; 6569e0a03cSPaolo Bonzini } 6669e0a03cSPaolo Bonzini 6769e0a03cSPaolo Bonzini /* write VMCS field */ 6869e0a03cSPaolo Bonzini static inline void wvmcs(hv_vcpuid_t vcpu, uint32_t field, uint64_t v) 6969e0a03cSPaolo Bonzini { 7069e0a03cSPaolo Bonzini hv_vmx_vcpu_write_vmcs(vcpu, field, v); 7169e0a03cSPaolo Bonzini } 7269e0a03cSPaolo Bonzini 7369e0a03cSPaolo Bonzini /* desired control word constrained by hardware/hypervisor capabilities */ 7469e0a03cSPaolo Bonzini static inline uint64_t cap2ctrl(uint64_t cap, uint64_t ctrl) 7569e0a03cSPaolo Bonzini { 7669e0a03cSPaolo Bonzini return (ctrl | (cap & 0xffffffff)) & (cap >> 32); 7769e0a03cSPaolo Bonzini } 7869e0a03cSPaolo Bonzini 7969e0a03cSPaolo Bonzini #define VM_ENTRY_GUEST_LMA (1LL << 9) 8069e0a03cSPaolo Bonzini 8169e0a03cSPaolo Bonzini #define AR_TYPE_ACCESSES_MASK 1 8269e0a03cSPaolo Bonzini #define AR_TYPE_READABLE_MASK (1 << 1) 8369e0a03cSPaolo Bonzini #define AR_TYPE_WRITEABLE_MASK (1 << 2) 8469e0a03cSPaolo Bonzini #define AR_TYPE_CODE_MASK (1 << 3) 8569e0a03cSPaolo Bonzini #define AR_TYPE_MASK 0x0f 8669e0a03cSPaolo Bonzini #define AR_TYPE_BUSY_64_TSS 11 8769e0a03cSPaolo Bonzini #define AR_TYPE_BUSY_32_TSS 11 8869e0a03cSPaolo Bonzini #define AR_TYPE_BUSY_16_TSS 3 8969e0a03cSPaolo Bonzini #define AR_TYPE_LDT 2 9069e0a03cSPaolo Bonzini 9169e0a03cSPaolo Bonzini static void enter_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer) 9269e0a03cSPaolo Bonzini { 9369e0a03cSPaolo Bonzini uint64_t entry_ctls; 9469e0a03cSPaolo Bonzini 956701d81dSPaolo Bonzini efer |= MSR_EFER_LMA; 9669e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer); 9769e0a03cSPaolo Bonzini entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS); 9869e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) | 9969e0a03cSPaolo Bonzini VM_ENTRY_GUEST_LMA); 10069e0a03cSPaolo Bonzini 10169e0a03cSPaolo Bonzini uint64_t guest_tr_ar = rvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS); 1026701d81dSPaolo Bonzini if ((efer & MSR_EFER_LME) && 10369e0a03cSPaolo Bonzini (guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { 10469e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS, 10569e0a03cSPaolo Bonzini (guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS); 10669e0a03cSPaolo Bonzini } 10769e0a03cSPaolo Bonzini } 10869e0a03cSPaolo Bonzini 10969e0a03cSPaolo Bonzini static void exit_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer) 11069e0a03cSPaolo Bonzini { 11169e0a03cSPaolo Bonzini uint64_t entry_ctls; 11269e0a03cSPaolo Bonzini 11369e0a03cSPaolo Bonzini entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS); 11469e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_ENTRY_CTLS, entry_ctls & ~VM_ENTRY_GUEST_LMA); 11569e0a03cSPaolo Bonzini 1166701d81dSPaolo Bonzini efer &= ~MSR_EFER_LMA; 11769e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer); 11869e0a03cSPaolo Bonzini } 11969e0a03cSPaolo Bonzini 12069e0a03cSPaolo Bonzini static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0) 12169e0a03cSPaolo Bonzini { 12269e0a03cSPaolo Bonzini int i; 12369e0a03cSPaolo Bonzini uint64_t pdpte[4] = {0, 0, 0, 0}; 12469e0a03cSPaolo Bonzini uint64_t efer = rvmcs(vcpu, VMCS_GUEST_IA32_EFER); 12569e0a03cSPaolo Bonzini uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0); 126a4e26fa8SCameron Esfahani uint64_t changed_cr0 = old_cr0 ^ cr0; 127e37aa8b0SCameron Esfahani uint64_t mask = CR0_PG | CR0_CD | CR0_NW | CR0_NE | CR0_ET; 12882695a1bSRoman Bolshakov uint64_t entry_ctls; 12969e0a03cSPaolo Bonzini 13069e0a03cSPaolo Bonzini if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && 1316701d81dSPaolo Bonzini !(efer & MSR_EFER_LME)) { 13219f70347SPeter Maydell address_space_read(&address_space_memory, 13369e0a03cSPaolo Bonzini rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, 13419f70347SPeter Maydell MEMTXATTRS_UNSPECIFIED, pdpte, 32); 135e37aa8b0SCameron Esfahani /* Only set PDPTE when appropriate. */ 13669e0a03cSPaolo Bonzini for (i = 0; i < 4; i++) { 13769e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]); 13869e0a03cSPaolo Bonzini } 139e37aa8b0SCameron Esfahani } 14069e0a03cSPaolo Bonzini 141e37aa8b0SCameron Esfahani wvmcs(vcpu, VMCS_CR0_MASK, mask); 14269e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_CR0_SHADOW, cr0); 14369e0a03cSPaolo Bonzini 1446701d81dSPaolo Bonzini if (efer & MSR_EFER_LME) { 145a4e26fa8SCameron Esfahani if (changed_cr0 & CR0_PG) { 146a4e26fa8SCameron Esfahani if (cr0 & CR0_PG) { 14769e0a03cSPaolo Bonzini enter_long_mode(vcpu, cr0, efer); 148a4e26fa8SCameron Esfahani } else { 14969e0a03cSPaolo Bonzini exit_long_mode(vcpu, cr0, efer); 15069e0a03cSPaolo Bonzini } 15169e0a03cSPaolo Bonzini } 15282695a1bSRoman Bolshakov } else { 15382695a1bSRoman Bolshakov entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS); 15482695a1bSRoman Bolshakov wvmcs(vcpu, VMCS_ENTRY_CTLS, entry_ctls & ~VM_ENTRY_GUEST_LMA); 155a4e26fa8SCameron Esfahani } 15669e0a03cSPaolo Bonzini 157e37aa8b0SCameron Esfahani /* Filter new CR0 after we are finished examining it above. */ 158e37aa8b0SCameron Esfahani cr0 = (cr0 & ~(mask & ~CR0_PG)); 159e37aa8b0SCameron Esfahani wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE | CR0_ET); 160e37aa8b0SCameron Esfahani 16169e0a03cSPaolo Bonzini hv_vcpu_invalidate_tlb(vcpu); 16269e0a03cSPaolo Bonzini hv_vcpu_flush(vcpu); 16369e0a03cSPaolo Bonzini } 16469e0a03cSPaolo Bonzini 16569e0a03cSPaolo Bonzini static inline void macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4) 16669e0a03cSPaolo Bonzini { 16769e0a03cSPaolo Bonzini uint64_t guest_cr4 = cr4 | CR4_VMXE; 16869e0a03cSPaolo Bonzini 16969e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_GUEST_CR4, guest_cr4); 17069e0a03cSPaolo Bonzini wvmcs(vcpu, VMCS_CR4_SHADOW, cr4); 171818b9f11SRoman Bolshakov wvmcs(vcpu, VMCS_CR4_MASK, CR4_VMXE); 17269e0a03cSPaolo Bonzini 17369e0a03cSPaolo Bonzini hv_vcpu_invalidate_tlb(vcpu); 17469e0a03cSPaolo Bonzini hv_vcpu_flush(vcpu); 17569e0a03cSPaolo Bonzini } 17669e0a03cSPaolo Bonzini 17769e0a03cSPaolo Bonzini static inline void macvm_set_rip(CPUState *cpu, uint64_t rip) 17869e0a03cSPaolo Bonzini { 179ddd31732SRoman Bolshakov X86CPU *x86_cpu = X86_CPU(cpu); 180ddd31732SRoman Bolshakov CPUX86State *env = &x86_cpu->env; 18169e0a03cSPaolo Bonzini uint64_t val; 18269e0a03cSPaolo Bonzini 18369e0a03cSPaolo Bonzini /* BUG, should take considering overlap.. */ 184*b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RIP, rip); 185b8d864f6SRoman Bolshakov env->eip = rip; 18669e0a03cSPaolo Bonzini 18769e0a03cSPaolo Bonzini /* after moving forward in rip, we need to clean INTERRUPTABILITY */ 188*b533450eSAlexander Graf val = rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); 18969e0a03cSPaolo Bonzini if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | 19069e0a03cSPaolo Bonzini VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { 191ddd31732SRoman Bolshakov env->hflags &= ~HF_INHIBIT_IRQ_MASK; 192*b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, 19369e0a03cSPaolo Bonzini val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | 19469e0a03cSPaolo Bonzini VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)); 19569e0a03cSPaolo Bonzini } 19669e0a03cSPaolo Bonzini } 19769e0a03cSPaolo Bonzini 19869e0a03cSPaolo Bonzini static inline void vmx_clear_nmi_blocking(CPUState *cpu) 19969e0a03cSPaolo Bonzini { 20069e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 20169e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 20269e0a03cSPaolo Bonzini 20369e0a03cSPaolo Bonzini env->hflags2 &= ~HF2_NMI_MASK; 204*b533450eSAlexander Graf uint32_t gi = (uint32_t) rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); 20569e0a03cSPaolo Bonzini gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; 206*b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); 20769e0a03cSPaolo Bonzini } 20869e0a03cSPaolo Bonzini 20969e0a03cSPaolo Bonzini static inline void vmx_set_nmi_blocking(CPUState *cpu) 21069e0a03cSPaolo Bonzini { 21169e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 21269e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 21369e0a03cSPaolo Bonzini 21469e0a03cSPaolo Bonzini env->hflags2 |= HF2_NMI_MASK; 215*b533450eSAlexander Graf uint32_t gi = (uint32_t)rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); 21669e0a03cSPaolo Bonzini gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING; 217*b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); 21869e0a03cSPaolo Bonzini } 21969e0a03cSPaolo Bonzini 22069e0a03cSPaolo Bonzini static inline void vmx_set_nmi_window_exiting(CPUState *cpu) 22169e0a03cSPaolo Bonzini { 22269e0a03cSPaolo Bonzini uint64_t val; 223*b533450eSAlexander Graf val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); 224*b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | 22569e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); 22669e0a03cSPaolo Bonzini 22769e0a03cSPaolo Bonzini } 22869e0a03cSPaolo Bonzini 22969e0a03cSPaolo Bonzini static inline void vmx_clear_nmi_window_exiting(CPUState *cpu) 23069e0a03cSPaolo Bonzini { 23169e0a03cSPaolo Bonzini 23269e0a03cSPaolo Bonzini uint64_t val; 233*b533450eSAlexander Graf val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); 234*b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & 23569e0a03cSPaolo Bonzini ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); 23669e0a03cSPaolo Bonzini } 23769e0a03cSPaolo Bonzini 23869e0a03cSPaolo Bonzini #endif 239