169e0a03cSPaolo Bonzini /* Copyright 2008 IBM Corporation 269e0a03cSPaolo Bonzini * 2008 Red Hat, Inc. 369e0a03cSPaolo Bonzini * Copyright 2011 Intel Corporation 469e0a03cSPaolo Bonzini * Copyright 2016 Veertu, Inc. 569e0a03cSPaolo Bonzini * Copyright 2017 The Android Open Source Project 669e0a03cSPaolo Bonzini * 769e0a03cSPaolo Bonzini * QEMU Hypervisor.framework support 869e0a03cSPaolo Bonzini * 969e0a03cSPaolo Bonzini * This program is free software; you can redistribute it and/or 1069e0a03cSPaolo Bonzini * modify it under the terms of version 2 of the GNU General Public 1169e0a03cSPaolo Bonzini * License as published by the Free Software Foundation. 1269e0a03cSPaolo Bonzini * 1369e0a03cSPaolo Bonzini * This program is distributed in the hope that it will be useful, 1469e0a03cSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 1569e0a03cSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16e361a772SThomas Huth * General Public License for more details. 1769e0a03cSPaolo Bonzini * 18e361a772SThomas Huth * You should have received a copy of the GNU General Public License 19e361a772SThomas Huth * along with this program; if not, see <http://www.gnu.org/licenses/>. 20d781e24dSIzik Eidus * 21d781e24dSIzik Eidus * This file contain code under public domain from the hvdos project: 22d781e24dSIzik Eidus * https://github.com/mist64/hvdos 234d98a8e5SPaolo Bonzini * 244d98a8e5SPaolo Bonzini * Parts Copyright (c) 2011 NetApp, Inc. 254d98a8e5SPaolo Bonzini * All rights reserved. 264d98a8e5SPaolo Bonzini * 274d98a8e5SPaolo Bonzini * Redistribution and use in source and binary forms, with or without 284d98a8e5SPaolo Bonzini * modification, are permitted provided that the following conditions 294d98a8e5SPaolo Bonzini * are met: 304d98a8e5SPaolo Bonzini * 1. Redistributions of source code must retain the above copyright 314d98a8e5SPaolo Bonzini * notice, this list of conditions and the following disclaimer. 324d98a8e5SPaolo Bonzini * 2. Redistributions in binary form must reproduce the above copyright 334d98a8e5SPaolo Bonzini * notice, this list of conditions and the following disclaimer in the 344d98a8e5SPaolo Bonzini * documentation and/or other materials provided with the distribution. 354d98a8e5SPaolo Bonzini * 364d98a8e5SPaolo Bonzini * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 374d98a8e5SPaolo Bonzini * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 384d98a8e5SPaolo Bonzini * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 394d98a8e5SPaolo Bonzini * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 404d98a8e5SPaolo Bonzini * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 414d98a8e5SPaolo Bonzini * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 424d98a8e5SPaolo Bonzini * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 434d98a8e5SPaolo Bonzini * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 444d98a8e5SPaolo Bonzini * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 454d98a8e5SPaolo Bonzini * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 464d98a8e5SPaolo Bonzini * SUCH DAMAGE. 4769e0a03cSPaolo Bonzini */ 4854d31236SMarkus Armbruster 4969e0a03cSPaolo Bonzini #include "qemu/osdep.h" 5069e0a03cSPaolo Bonzini #include "qemu/error-report.h" 515df022cfSPeter Maydell #include "qemu/memalign.h" 5269e0a03cSPaolo Bonzini 5369e0a03cSPaolo Bonzini #include "sysemu/hvf.h" 54d57bc3c1SAlexander Graf #include "sysemu/hvf_int.h" 5554d31236SMarkus Armbruster #include "sysemu/runstate.h" 56a1477da3SAlexander Graf #include "sysemu/cpus.h" 5769e0a03cSPaolo Bonzini #include "hvf-i386.h" 5869e0a03cSPaolo Bonzini #include "vmcs.h" 5969e0a03cSPaolo Bonzini #include "vmx.h" 6069e0a03cSPaolo Bonzini #include "x86.h" 6169e0a03cSPaolo Bonzini #include "x86_descr.h" 6269e0a03cSPaolo Bonzini #include "x86_mmu.h" 6369e0a03cSPaolo Bonzini #include "x86_decode.h" 6469e0a03cSPaolo Bonzini #include "x86_emu.h" 6569e0a03cSPaolo Bonzini #include "x86_task.h" 6669e0a03cSPaolo Bonzini #include "x86hvf.h" 6769e0a03cSPaolo Bonzini 6869e0a03cSPaolo Bonzini #include <Hypervisor/hv.h> 6969e0a03cSPaolo Bonzini #include <Hypervisor/hv_vmx.h> 703b502b0eSVladislav Yaroshchuk #include <sys/sysctl.h> 7169e0a03cSPaolo Bonzini 7269e0a03cSPaolo Bonzini #include "hw/i386/apic_internal.h" 7369e0a03cSPaolo Bonzini #include "qemu/main-loop.h" 74940e43aaSClaudio Fontana #include "qemu/accel.h" 7569e0a03cSPaolo Bonzini #include "target/i386/cpu.h" 7669e0a03cSPaolo Bonzini 7769e0a03cSPaolo Bonzini void vmx_update_tpr(CPUState *cpu) 7869e0a03cSPaolo Bonzini { 7969e0a03cSPaolo Bonzini /* TODO: need integrate APIC handling */ 8069e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 8169e0a03cSPaolo Bonzini int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; 8269e0a03cSPaolo Bonzini int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); 8369e0a03cSPaolo Bonzini 84b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_TPR, tpr); 8569e0a03cSPaolo Bonzini if (irr == -1) { 86b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); 8769e0a03cSPaolo Bonzini } else { 88b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : 8969e0a03cSPaolo Bonzini irr >> 4); 9069e0a03cSPaolo Bonzini } 9169e0a03cSPaolo Bonzini } 9269e0a03cSPaolo Bonzini 93583ae161SRoman Bolshakov static void update_apic_tpr(CPUState *cpu) 9469e0a03cSPaolo Bonzini { 9569e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 96b533450eSAlexander Graf int tpr = rreg(cpu->hvf->fd, HV_X86_TPR) >> 4; 9769e0a03cSPaolo Bonzini cpu_set_apic_tpr(x86_cpu->apic_state, tpr); 9869e0a03cSPaolo Bonzini } 9969e0a03cSPaolo Bonzini 10069e0a03cSPaolo Bonzini #define VECTORING_INFO_VECTOR_MASK 0xff 10169e0a03cSPaolo Bonzini 10269e0a03cSPaolo Bonzini void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer, 10369e0a03cSPaolo Bonzini int direction, int size, int count) 10469e0a03cSPaolo Bonzini { 10569e0a03cSPaolo Bonzini int i; 10669e0a03cSPaolo Bonzini uint8_t *ptr = buffer; 10769e0a03cSPaolo Bonzini 10869e0a03cSPaolo Bonzini for (i = 0; i < count; i++) { 10969e0a03cSPaolo Bonzini address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED, 11069e0a03cSPaolo Bonzini ptr, size, 11169e0a03cSPaolo Bonzini direction); 11269e0a03cSPaolo Bonzini ptr += size; 11369e0a03cSPaolo Bonzini } 11469e0a03cSPaolo Bonzini } 11569e0a03cSPaolo Bonzini 116ff2de166SPaolo Bonzini static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept_qual) 11769e0a03cSPaolo Bonzini { 11869e0a03cSPaolo Bonzini int read, write; 11969e0a03cSPaolo Bonzini 12069e0a03cSPaolo Bonzini /* EPT fault on an instruction fetch doesn't make sense here */ 12169e0a03cSPaolo Bonzini if (ept_qual & EPT_VIOLATION_INST_FETCH) { 12269e0a03cSPaolo Bonzini return false; 12369e0a03cSPaolo Bonzini } 12469e0a03cSPaolo Bonzini 12569e0a03cSPaolo Bonzini /* EPT fault must be a read fault or a write fault */ 12669e0a03cSPaolo Bonzini read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0; 12769e0a03cSPaolo Bonzini write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0; 12869e0a03cSPaolo Bonzini if ((read | write) == 0) { 12969e0a03cSPaolo Bonzini return false; 13069e0a03cSPaolo Bonzini } 13169e0a03cSPaolo Bonzini 13269e0a03cSPaolo Bonzini if (write && slot) { 13369e0a03cSPaolo Bonzini if (slot->flags & HVF_SLOT_LOG) { 13469e0a03cSPaolo Bonzini memory_region_set_dirty(slot->region, gpa - slot->start, 1); 13569e0a03cSPaolo Bonzini hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, 13669e0a03cSPaolo Bonzini HV_MEMORY_READ | HV_MEMORY_WRITE); 13769e0a03cSPaolo Bonzini } 13869e0a03cSPaolo Bonzini } 13969e0a03cSPaolo Bonzini 14069e0a03cSPaolo Bonzini /* 14169e0a03cSPaolo Bonzini * The EPT violation must have been caused by accessing a 14269e0a03cSPaolo Bonzini * guest-physical address that is a translation of a guest-linear 14369e0a03cSPaolo Bonzini * address. 14469e0a03cSPaolo Bonzini */ 14569e0a03cSPaolo Bonzini if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 || 14669e0a03cSPaolo Bonzini (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) { 14769e0a03cSPaolo Bonzini return false; 14869e0a03cSPaolo Bonzini } 14969e0a03cSPaolo Bonzini 150fbafbb6dSCameron Esfahani if (!slot) { 151fbafbb6dSCameron Esfahani return true; 152fbafbb6dSCameron Esfahani } 153fbafbb6dSCameron Esfahani if (!memory_region_is_ram(slot->region) && 154fbafbb6dSCameron Esfahani !(read && memory_region_is_romd(slot->region))) { 155fbafbb6dSCameron Esfahani return true; 156fbafbb6dSCameron Esfahani } 157fbafbb6dSCameron Esfahani return false; 15869e0a03cSPaolo Bonzini } 15969e0a03cSPaolo Bonzini 160cfe58455SAlexander Graf void hvf_arch_vcpu_destroy(CPUState *cpu) 16169e0a03cSPaolo Bonzini { 162fe76b09cSRoman Bolshakov X86CPU *x86_cpu = X86_CPU(cpu); 163fe76b09cSRoman Bolshakov CPUX86State *env = &x86_cpu->env; 164fe76b09cSRoman Bolshakov 165fe76b09cSRoman Bolshakov g_free(env->hvf_mmio_buf); 16669e0a03cSPaolo Bonzini } 16769e0a03cSPaolo Bonzini 1683b502b0eSVladislav Yaroshchuk static void init_tsc_freq(CPUX86State *env) 1693b502b0eSVladislav Yaroshchuk { 1703b502b0eSVladislav Yaroshchuk size_t length; 1713b502b0eSVladislav Yaroshchuk uint64_t tsc_freq; 1723b502b0eSVladislav Yaroshchuk 1733b502b0eSVladislav Yaroshchuk if (env->tsc_khz != 0) { 1743b502b0eSVladislav Yaroshchuk return; 1753b502b0eSVladislav Yaroshchuk } 1763b502b0eSVladislav Yaroshchuk 1773b502b0eSVladislav Yaroshchuk length = sizeof(uint64_t); 1783b502b0eSVladislav Yaroshchuk if (sysctlbyname("machdep.tsc.frequency", &tsc_freq, &length, NULL, 0)) { 1793b502b0eSVladislav Yaroshchuk return; 1803b502b0eSVladislav Yaroshchuk } 1813b502b0eSVladislav Yaroshchuk env->tsc_khz = tsc_freq / 1000; /* Hz to KHz */ 1823b502b0eSVladislav Yaroshchuk } 1833b502b0eSVladislav Yaroshchuk 1843b502b0eSVladislav Yaroshchuk static void init_apic_bus_freq(CPUX86State *env) 1853b502b0eSVladislav Yaroshchuk { 1863b502b0eSVladislav Yaroshchuk size_t length; 1873b502b0eSVladislav Yaroshchuk uint64_t bus_freq; 1883b502b0eSVladislav Yaroshchuk 1893b502b0eSVladislav Yaroshchuk if (env->apic_bus_freq != 0) { 1903b502b0eSVladislav Yaroshchuk return; 1913b502b0eSVladislav Yaroshchuk } 1923b502b0eSVladislav Yaroshchuk 1933b502b0eSVladislav Yaroshchuk length = sizeof(uint64_t); 1943b502b0eSVladislav Yaroshchuk if (sysctlbyname("hw.busfrequency", &bus_freq, &length, NULL, 0)) { 1953b502b0eSVladislav Yaroshchuk return; 1963b502b0eSVladislav Yaroshchuk } 1973b502b0eSVladislav Yaroshchuk env->apic_bus_freq = bus_freq; 1983b502b0eSVladislav Yaroshchuk } 1993b502b0eSVladislav Yaroshchuk 2003b502b0eSVladislav Yaroshchuk static inline bool tsc_is_known(CPUX86State *env) 2013b502b0eSVladislav Yaroshchuk { 2023b502b0eSVladislav Yaroshchuk return env->tsc_khz != 0; 2033b502b0eSVladislav Yaroshchuk } 2043b502b0eSVladislav Yaroshchuk 2053b502b0eSVladislav Yaroshchuk static inline bool apic_bus_freq_is_known(CPUX86State *env) 2063b502b0eSVladislav Yaroshchuk { 2073b502b0eSVladislav Yaroshchuk return env->apic_bus_freq != 0; 2083b502b0eSVladislav Yaroshchuk } 2093b502b0eSVladislav Yaroshchuk 210a1477da3SAlexander Graf void hvf_kick_vcpu_thread(CPUState *cpu) 211a1477da3SAlexander Graf { 212a1477da3SAlexander Graf cpus_kick_thread(cpu); 213a1477da3SAlexander Graf } 214a1477da3SAlexander Graf 215ce7f5b1cSAlexander Graf int hvf_arch_init(void) 216ce7f5b1cSAlexander Graf { 217ce7f5b1cSAlexander Graf return 0; 218ce7f5b1cSAlexander Graf } 219ce7f5b1cSAlexander Graf 220cfe58455SAlexander Graf int hvf_arch_init_vcpu(CPUState *cpu) 22169e0a03cSPaolo Bonzini { 22269e0a03cSPaolo Bonzini X86CPU *x86cpu = X86_CPU(cpu); 22369e0a03cSPaolo Bonzini CPUX86State *env = &x86cpu->env; 224d8cf2c29SCameron Esfahani uint64_t reqCap; 22569e0a03cSPaolo Bonzini 22669e0a03cSPaolo Bonzini init_emu(); 22769e0a03cSPaolo Bonzini init_decoder(); 22869e0a03cSPaolo Bonzini 22969e0a03cSPaolo Bonzini hvf_state->hvf_caps = g_new0(struct hvf_vcpu_caps, 1); 230fe76b09cSRoman Bolshakov env->hvf_mmio_buf = g_new(char, 4096); 23169e0a03cSPaolo Bonzini 2323b502b0eSVladislav Yaroshchuk if (x86cpu->vmware_cpuid_freq) { 2333b502b0eSVladislav Yaroshchuk init_tsc_freq(env); 2343b502b0eSVladislav Yaroshchuk init_apic_bus_freq(env); 2353b502b0eSVladislav Yaroshchuk 2363b502b0eSVladislav Yaroshchuk if (!tsc_is_known(env) || !apic_bus_freq_is_known(env)) { 2373b502b0eSVladislav Yaroshchuk error_report("vmware-cpuid-freq: feature couldn't be enabled"); 2383b502b0eSVladislav Yaroshchuk } 2393b502b0eSVladislav Yaroshchuk } 2403b502b0eSVladislav Yaroshchuk 24169e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, 24269e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_pinbased)) { 24369e0a03cSPaolo Bonzini abort(); 24469e0a03cSPaolo Bonzini } 24569e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, 24669e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_procbased)) { 24769e0a03cSPaolo Bonzini abort(); 24869e0a03cSPaolo Bonzini } 24969e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, 25069e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_procbased2)) { 25169e0a03cSPaolo Bonzini abort(); 25269e0a03cSPaolo Bonzini } 25369e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, 25469e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_entry)) { 25569e0a03cSPaolo Bonzini abort(); 25669e0a03cSPaolo Bonzini } 25769e0a03cSPaolo Bonzini 25869e0a03cSPaolo Bonzini /* set VMCS control fields */ 259b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS, 26069e0a03cSPaolo Bonzini cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, 26169e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_EXTINT | 26269e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_NMI | 26369e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_VNMI)); 264b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, 26569e0a03cSPaolo Bonzini cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, 26669e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_HLT | 26769e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_MWAIT | 26869e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET | 26969e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) | 27069e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL); 271d8cf2c29SCameron Esfahani 272d8cf2c29SCameron Esfahani reqCap = VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES; 273d8cf2c29SCameron Esfahani 274d8cf2c29SCameron Esfahani /* Is RDTSCP support in CPUID? If so, enable it in the VMCS. */ 275d8cf2c29SCameron Esfahani if (hvf_get_supported_cpuid(0x80000001, 0, R_EDX) & CPUID_EXT2_RDTSCP) { 276d8cf2c29SCameron Esfahani reqCap |= VMCS_PRI_PROC_BASED2_CTLS_RDTSCP; 277d8cf2c29SCameron Esfahani } 278d8cf2c29SCameron Esfahani 279b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS, 280d8cf2c29SCameron Esfahani cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap)); 28169e0a03cSPaolo Bonzini 282b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, 28369e0a03cSPaolo Bonzini 0)); 284b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ 28569e0a03cSPaolo Bonzini 286b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); 28769e0a03cSPaolo Bonzini 28869e0a03cSPaolo Bonzini x86cpu = X86_CPU(cpu); 289c0198c5fSDavid Edmondson x86cpu->env.xsave_buf_len = 4096; 290c0198c5fSDavid Edmondson x86cpu->env.xsave_buf = qemu_memalign(4096, x86cpu->env.xsave_buf_len); 29169e0a03cSPaolo Bonzini 292fea45008SDavid Edmondson /* 293fea45008SDavid Edmondson * The allocated storage must be large enough for all of the 294fea45008SDavid Edmondson * possible XSAVE state components. 295fea45008SDavid Edmondson */ 296fea45008SDavid Edmondson assert(hvf_get_supported_cpuid(0xd, 0, R_ECX) <= x86cpu->env.xsave_buf_len); 297fea45008SDavid Edmondson 298b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1); 299b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1); 300b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1); 301b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1); 302b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1); 303b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1); 304b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1); 305b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1); 306b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1); 307b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1); 308b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1); 309b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1); 31069e0a03cSPaolo Bonzini 31169e0a03cSPaolo Bonzini return 0; 31269e0a03cSPaolo Bonzini } 31369e0a03cSPaolo Bonzini 31469e0a03cSPaolo Bonzini static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info) 31569e0a03cSPaolo Bonzini { 31669e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 31769e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 31869e0a03cSPaolo Bonzini 319fd13f23bSLiran Alon env->exception_nr = -1; 320fd13f23bSLiran Alon env->exception_pending = 0; 321fd13f23bSLiran Alon env->exception_injected = 0; 32269e0a03cSPaolo Bonzini env->interrupt_injected = -1; 32369e0a03cSPaolo Bonzini env->nmi_injected = false; 32464bef038SCameron Esfahani env->ins_len = 0; 32564bef038SCameron Esfahani env->has_error_code = false; 32669e0a03cSPaolo Bonzini if (idtvec_info & VMCS_IDT_VEC_VALID) { 32769e0a03cSPaolo Bonzini switch (idtvec_info & VMCS_IDT_VEC_TYPE) { 32869e0a03cSPaolo Bonzini case VMCS_IDT_VEC_HWINTR: 32969e0a03cSPaolo Bonzini case VMCS_IDT_VEC_SWINTR: 33069e0a03cSPaolo Bonzini env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM; 33169e0a03cSPaolo Bonzini break; 33269e0a03cSPaolo Bonzini case VMCS_IDT_VEC_NMI: 33369e0a03cSPaolo Bonzini env->nmi_injected = true; 33469e0a03cSPaolo Bonzini break; 33569e0a03cSPaolo Bonzini case VMCS_IDT_VEC_HWEXCEPTION: 33669e0a03cSPaolo Bonzini case VMCS_IDT_VEC_SWEXCEPTION: 337fd13f23bSLiran Alon env->exception_nr = idtvec_info & VMCS_IDT_VEC_VECNUM; 338fd13f23bSLiran Alon env->exception_injected = 1; 33969e0a03cSPaolo Bonzini break; 34069e0a03cSPaolo Bonzini case VMCS_IDT_VEC_PRIV_SWEXCEPTION: 34169e0a03cSPaolo Bonzini default: 34269e0a03cSPaolo Bonzini abort(); 34369e0a03cSPaolo Bonzini } 34469e0a03cSPaolo Bonzini if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION || 34569e0a03cSPaolo Bonzini (idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) { 34669e0a03cSPaolo Bonzini env->ins_len = ins_len; 34769e0a03cSPaolo Bonzini } 34864bef038SCameron Esfahani if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { 34969e0a03cSPaolo Bonzini env->has_error_code = true; 350b533450eSAlexander Graf env->error_code = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERROR); 35169e0a03cSPaolo Bonzini } 35269e0a03cSPaolo Bonzini } 353b533450eSAlexander Graf if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & 35469e0a03cSPaolo Bonzini VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { 35569e0a03cSPaolo Bonzini env->hflags2 |= HF2_NMI_MASK; 35669e0a03cSPaolo Bonzini } else { 35769e0a03cSPaolo Bonzini env->hflags2 &= ~HF2_NMI_MASK; 35869e0a03cSPaolo Bonzini } 359b533450eSAlexander Graf if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & 36069e0a03cSPaolo Bonzini (VMCS_INTERRUPTIBILITY_STI_BLOCKING | 36169e0a03cSPaolo Bonzini VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { 36269e0a03cSPaolo Bonzini env->hflags |= HF_INHIBIT_IRQ_MASK; 36369e0a03cSPaolo Bonzini } else { 36469e0a03cSPaolo Bonzini env->hflags &= ~HF_INHIBIT_IRQ_MASK; 36569e0a03cSPaolo Bonzini } 36669e0a03cSPaolo Bonzini } 36769e0a03cSPaolo Bonzini 3683b502b0eSVladislav Yaroshchuk static void hvf_cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 3693b502b0eSVladislav Yaroshchuk uint32_t *eax, uint32_t *ebx, 3703b502b0eSVladislav Yaroshchuk uint32_t *ecx, uint32_t *edx) 3713b502b0eSVladislav Yaroshchuk { 3723b502b0eSVladislav Yaroshchuk /* 3733b502b0eSVladislav Yaroshchuk * A wrapper extends cpu_x86_cpuid with 0x40000000 and 0x40000010 leafs, 3743b502b0eSVladislav Yaroshchuk * leafs 0x40000001-0x4000000F are filled with zeros 3753b502b0eSVladislav Yaroshchuk * Provides vmware-cpuid-freq support to hvf 3763b502b0eSVladislav Yaroshchuk * 3773b502b0eSVladislav Yaroshchuk * Note: leaf 0x40000000 not exposes HVF, 3783b502b0eSVladislav Yaroshchuk * leaving hypervisor signature empty 3793b502b0eSVladislav Yaroshchuk */ 3803b502b0eSVladislav Yaroshchuk 3813b502b0eSVladislav Yaroshchuk if (index < 0x40000000 || index > 0x40000010 || 3823b502b0eSVladislav Yaroshchuk !tsc_is_known(env) || !apic_bus_freq_is_known(env)) { 3833b502b0eSVladislav Yaroshchuk 3843b502b0eSVladislav Yaroshchuk cpu_x86_cpuid(env, index, count, eax, ebx, ecx, edx); 3853b502b0eSVladislav Yaroshchuk return; 3863b502b0eSVladislav Yaroshchuk } 3873b502b0eSVladislav Yaroshchuk 3883b502b0eSVladislav Yaroshchuk switch (index) { 3893b502b0eSVladislav Yaroshchuk case 0x40000000: 3903b502b0eSVladislav Yaroshchuk *eax = 0x40000010; /* Max available cpuid leaf */ 3913b502b0eSVladislav Yaroshchuk *ebx = 0; /* Leave signature empty */ 3923b502b0eSVladislav Yaroshchuk *ecx = 0; 3933b502b0eSVladislav Yaroshchuk *edx = 0; 3943b502b0eSVladislav Yaroshchuk break; 3953b502b0eSVladislav Yaroshchuk case 0x40000010: 3963b502b0eSVladislav Yaroshchuk *eax = env->tsc_khz; 3973b502b0eSVladislav Yaroshchuk *ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ 3983b502b0eSVladislav Yaroshchuk *ecx = 0; 3993b502b0eSVladislav Yaroshchuk *edx = 0; 4003b502b0eSVladislav Yaroshchuk break; 4013b502b0eSVladislav Yaroshchuk default: 4023b502b0eSVladislav Yaroshchuk *eax = 0; 4033b502b0eSVladislav Yaroshchuk *ebx = 0; 4043b502b0eSVladislav Yaroshchuk *ecx = 0; 4053b502b0eSVladislav Yaroshchuk *edx = 0; 4063b502b0eSVladislav Yaroshchuk break; 4073b502b0eSVladislav Yaroshchuk } 4083b502b0eSVladislav Yaroshchuk } 4093b502b0eSVladislav Yaroshchuk 41069e0a03cSPaolo Bonzini int hvf_vcpu_exec(CPUState *cpu) 41169e0a03cSPaolo Bonzini { 41269e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 41369e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 41469e0a03cSPaolo Bonzini int ret = 0; 41569e0a03cSPaolo Bonzini uint64_t rip = 0; 41669e0a03cSPaolo Bonzini 41769e0a03cSPaolo Bonzini if (hvf_process_events(cpu)) { 41869e0a03cSPaolo Bonzini return EXCP_HLT; 41969e0a03cSPaolo Bonzini } 42069e0a03cSPaolo Bonzini 42169e0a03cSPaolo Bonzini do { 42269e0a03cSPaolo Bonzini if (cpu->vcpu_dirty) { 42369e0a03cSPaolo Bonzini hvf_put_registers(cpu); 42469e0a03cSPaolo Bonzini cpu->vcpu_dirty = false; 42569e0a03cSPaolo Bonzini } 42669e0a03cSPaolo Bonzini 42769e0a03cSPaolo Bonzini if (hvf_inject_interrupts(cpu)) { 42869e0a03cSPaolo Bonzini return EXCP_INTERRUPT; 42969e0a03cSPaolo Bonzini } 43069e0a03cSPaolo Bonzini vmx_update_tpr(cpu); 43169e0a03cSPaolo Bonzini 43269e0a03cSPaolo Bonzini qemu_mutex_unlock_iothread(); 43369e0a03cSPaolo Bonzini if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) { 43469e0a03cSPaolo Bonzini qemu_mutex_lock_iothread(); 43569e0a03cSPaolo Bonzini return EXCP_HLT; 43669e0a03cSPaolo Bonzini } 43769e0a03cSPaolo Bonzini 438b533450eSAlexander Graf hv_return_t r = hv_vcpu_run(cpu->hvf->fd); 43969e0a03cSPaolo Bonzini assert_hvf_ok(r); 44069e0a03cSPaolo Bonzini 44169e0a03cSPaolo Bonzini /* handle VMEXIT */ 442b533450eSAlexander Graf uint64_t exit_reason = rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON); 443b533450eSAlexander Graf uint64_t exit_qual = rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION); 444b533450eSAlexander Graf uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf->fd, 44569e0a03cSPaolo Bonzini VMCS_EXIT_INSTRUCTION_LENGTH); 44669e0a03cSPaolo Bonzini 447b533450eSAlexander Graf uint64_t idtvec_info = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO); 44869e0a03cSPaolo Bonzini 44969e0a03cSPaolo Bonzini hvf_store_events(cpu, ins_len, idtvec_info); 450b533450eSAlexander Graf rip = rreg(cpu->hvf->fd, HV_X86_RIP); 451b533450eSAlexander Graf env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS); 45269e0a03cSPaolo Bonzini 45369e0a03cSPaolo Bonzini qemu_mutex_lock_iothread(); 45469e0a03cSPaolo Bonzini 45569e0a03cSPaolo Bonzini update_apic_tpr(cpu); 45669e0a03cSPaolo Bonzini current_cpu = cpu; 45769e0a03cSPaolo Bonzini 45869e0a03cSPaolo Bonzini ret = 0; 45969e0a03cSPaolo Bonzini switch (exit_reason) { 46069e0a03cSPaolo Bonzini case EXIT_REASON_HLT: { 46169e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 46269e0a03cSPaolo Bonzini if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && 463967f4da2SRoman Bolshakov (env->eflags & IF_MASK)) 46469e0a03cSPaolo Bonzini && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) && 46569e0a03cSPaolo Bonzini !(idtvec_info & VMCS_IDT_VEC_VALID)) { 46669e0a03cSPaolo Bonzini cpu->halted = 1; 46769e0a03cSPaolo Bonzini ret = EXCP_HLT; 4683b9c59daSChen Zhang break; 46969e0a03cSPaolo Bonzini } 47069e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 47169e0a03cSPaolo Bonzini break; 47269e0a03cSPaolo Bonzini } 47369e0a03cSPaolo Bonzini case EXIT_REASON_MWAIT: { 47469e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 47569e0a03cSPaolo Bonzini break; 47669e0a03cSPaolo Bonzini } 477fbafbb6dSCameron Esfahani /* Need to check if MMIO or unmapped fault */ 47869e0a03cSPaolo Bonzini case EXIT_REASON_EPT_FAULT: 47969e0a03cSPaolo Bonzini { 48069e0a03cSPaolo Bonzini hvf_slot *slot; 481b533450eSAlexander Graf uint64_t gpa = rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRESS); 48269e0a03cSPaolo Bonzini 48369e0a03cSPaolo Bonzini if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) && 48469e0a03cSPaolo Bonzini ((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) { 48569e0a03cSPaolo Bonzini vmx_set_nmi_blocking(cpu); 48669e0a03cSPaolo Bonzini } 48769e0a03cSPaolo Bonzini 488fbafbb6dSCameron Esfahani slot = hvf_find_overlap_slot(gpa, 1); 48969e0a03cSPaolo Bonzini /* mmio */ 49069e0a03cSPaolo Bonzini if (ept_emulation_fault(slot, gpa, exit_qual)) { 49169e0a03cSPaolo Bonzini struct x86_decode decode; 49269e0a03cSPaolo Bonzini 49369e0a03cSPaolo Bonzini load_regs(cpu); 49469e0a03cSPaolo Bonzini decode_instruction(env, &decode); 49569e0a03cSPaolo Bonzini exec_instruction(env, &decode); 49669e0a03cSPaolo Bonzini store_regs(cpu); 49769e0a03cSPaolo Bonzini break; 49869e0a03cSPaolo Bonzini } 49969e0a03cSPaolo Bonzini break; 50069e0a03cSPaolo Bonzini } 50169e0a03cSPaolo Bonzini case EXIT_REASON_INOUT: 50269e0a03cSPaolo Bonzini { 50369e0a03cSPaolo Bonzini uint32_t in = (exit_qual & 8) != 0; 50469e0a03cSPaolo Bonzini uint32_t size = (exit_qual & 7) + 1; 50569e0a03cSPaolo Bonzini uint32_t string = (exit_qual & 16) != 0; 50669e0a03cSPaolo Bonzini uint32_t port = exit_qual >> 16; 50769e0a03cSPaolo Bonzini /*uint32_t rep = (exit_qual & 0x20) != 0;*/ 50869e0a03cSPaolo Bonzini 50969e0a03cSPaolo Bonzini if (!string && in) { 51069e0a03cSPaolo Bonzini uint64_t val = 0; 51169e0a03cSPaolo Bonzini load_regs(cpu); 51269e0a03cSPaolo Bonzini hvf_handle_io(env, port, &val, 0, size, 1); 51369e0a03cSPaolo Bonzini if (size == 1) { 51469e0a03cSPaolo Bonzini AL(env) = val; 51569e0a03cSPaolo Bonzini } else if (size == 2) { 51669e0a03cSPaolo Bonzini AX(env) = val; 51769e0a03cSPaolo Bonzini } else if (size == 4) { 51869e0a03cSPaolo Bonzini RAX(env) = (uint32_t)val; 51969e0a03cSPaolo Bonzini } else { 520da20f5cdSPaolo Bonzini RAX(env) = (uint64_t)val; 52169e0a03cSPaolo Bonzini } 5225d32173fSRoman Bolshakov env->eip += ins_len; 52369e0a03cSPaolo Bonzini store_regs(cpu); 52469e0a03cSPaolo Bonzini break; 52569e0a03cSPaolo Bonzini } else if (!string && !in) { 526b533450eSAlexander Graf RAX(env) = rreg(cpu->hvf->fd, HV_X86_RAX); 52769e0a03cSPaolo Bonzini hvf_handle_io(env, port, &RAX(env), 1, size, 1); 52869e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 52969e0a03cSPaolo Bonzini break; 53069e0a03cSPaolo Bonzini } 53169e0a03cSPaolo Bonzini struct x86_decode decode; 53269e0a03cSPaolo Bonzini 53369e0a03cSPaolo Bonzini load_regs(cpu); 53469e0a03cSPaolo Bonzini decode_instruction(env, &decode); 535e62963bfSPaolo Bonzini assert(ins_len == decode.len); 53669e0a03cSPaolo Bonzini exec_instruction(env, &decode); 53769e0a03cSPaolo Bonzini store_regs(cpu); 53869e0a03cSPaolo Bonzini 53969e0a03cSPaolo Bonzini break; 54069e0a03cSPaolo Bonzini } 54169e0a03cSPaolo Bonzini case EXIT_REASON_CPUID: { 542b533450eSAlexander Graf uint32_t rax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); 543b533450eSAlexander Graf uint32_t rbx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX); 544b533450eSAlexander Graf uint32_t rcx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); 545b533450eSAlexander Graf uint32_t rdx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); 54669e0a03cSPaolo Bonzini 547106f91d5SAlexander Graf if (rax == 1) { 548106f91d5SAlexander Graf /* CPUID1.ecx.OSXSAVE needs to know CR4 */ 549b533450eSAlexander Graf env->cr[4] = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); 550106f91d5SAlexander Graf } 5513b502b0eSVladislav Yaroshchuk hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); 55269e0a03cSPaolo Bonzini 553b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RAX, rax); 554b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RBX, rbx); 555b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RCX, rcx); 556b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RDX, rdx); 55769e0a03cSPaolo Bonzini 55869e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 55969e0a03cSPaolo Bonzini break; 56069e0a03cSPaolo Bonzini } 56169e0a03cSPaolo Bonzini case EXIT_REASON_XSETBV: { 56269e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 56369e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 564b533450eSAlexander Graf uint32_t eax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); 565b533450eSAlexander Graf uint32_t ecx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); 566b533450eSAlexander Graf uint32_t edx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); 56769e0a03cSPaolo Bonzini 56869e0a03cSPaolo Bonzini if (ecx) { 56969e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 57069e0a03cSPaolo Bonzini break; 57169e0a03cSPaolo Bonzini } 57269e0a03cSPaolo Bonzini env->xcr0 = ((uint64_t)edx << 32) | eax; 573b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1); 57469e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 57569e0a03cSPaolo Bonzini break; 57669e0a03cSPaolo Bonzini } 57769e0a03cSPaolo Bonzini case EXIT_REASON_INTR_WINDOW: 57869e0a03cSPaolo Bonzini vmx_clear_int_window_exiting(cpu); 57969e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 58069e0a03cSPaolo Bonzini break; 58169e0a03cSPaolo Bonzini case EXIT_REASON_NMI_WINDOW: 58269e0a03cSPaolo Bonzini vmx_clear_nmi_window_exiting(cpu); 58369e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 58469e0a03cSPaolo Bonzini break; 58569e0a03cSPaolo Bonzini case EXIT_REASON_EXT_INTR: 58669e0a03cSPaolo Bonzini /* force exit and allow io handling */ 58769e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 58869e0a03cSPaolo Bonzini break; 58969e0a03cSPaolo Bonzini case EXIT_REASON_RDMSR: 59069e0a03cSPaolo Bonzini case EXIT_REASON_WRMSR: 59169e0a03cSPaolo Bonzini { 59269e0a03cSPaolo Bonzini load_regs(cpu); 59369e0a03cSPaolo Bonzini if (exit_reason == EXIT_REASON_RDMSR) { 59469e0a03cSPaolo Bonzini simulate_rdmsr(cpu); 59569e0a03cSPaolo Bonzini } else { 59669e0a03cSPaolo Bonzini simulate_wrmsr(cpu); 59769e0a03cSPaolo Bonzini } 5985d32173fSRoman Bolshakov env->eip += ins_len; 59969e0a03cSPaolo Bonzini store_regs(cpu); 60069e0a03cSPaolo Bonzini break; 60169e0a03cSPaolo Bonzini } 60269e0a03cSPaolo Bonzini case EXIT_REASON_CR_ACCESS: { 60369e0a03cSPaolo Bonzini int cr; 60469e0a03cSPaolo Bonzini int reg; 60569e0a03cSPaolo Bonzini 60669e0a03cSPaolo Bonzini load_regs(cpu); 60769e0a03cSPaolo Bonzini cr = exit_qual & 15; 60869e0a03cSPaolo Bonzini reg = (exit_qual >> 8) & 15; 60969e0a03cSPaolo Bonzini 61069e0a03cSPaolo Bonzini switch (cr) { 61169e0a03cSPaolo Bonzini case 0x0: { 612b533450eSAlexander Graf macvm_set_cr0(cpu->hvf->fd, RRX(env, reg)); 61369e0a03cSPaolo Bonzini break; 61469e0a03cSPaolo Bonzini } 61569e0a03cSPaolo Bonzini case 4: { 616b533450eSAlexander Graf macvm_set_cr4(cpu->hvf->fd, RRX(env, reg)); 61769e0a03cSPaolo Bonzini break; 61869e0a03cSPaolo Bonzini } 61969e0a03cSPaolo Bonzini case 8: { 62069e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 62169e0a03cSPaolo Bonzini if (exit_qual & 0x10) { 62269e0a03cSPaolo Bonzini RRX(env, reg) = cpu_get_apic_tpr(x86_cpu->apic_state); 62369e0a03cSPaolo Bonzini } else { 62469e0a03cSPaolo Bonzini int tpr = RRX(env, reg); 62569e0a03cSPaolo Bonzini cpu_set_apic_tpr(x86_cpu->apic_state, tpr); 62669e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 62769e0a03cSPaolo Bonzini } 62869e0a03cSPaolo Bonzini break; 62969e0a03cSPaolo Bonzini } 63069e0a03cSPaolo Bonzini default: 6312d9178d9SLaurent Vivier error_report("Unrecognized CR %d", cr); 63269e0a03cSPaolo Bonzini abort(); 63369e0a03cSPaolo Bonzini } 6345d32173fSRoman Bolshakov env->eip += ins_len; 63569e0a03cSPaolo Bonzini store_regs(cpu); 63669e0a03cSPaolo Bonzini break; 63769e0a03cSPaolo Bonzini } 63869e0a03cSPaolo Bonzini case EXIT_REASON_APIC_ACCESS: { /* TODO */ 63969e0a03cSPaolo Bonzini struct x86_decode decode; 64069e0a03cSPaolo Bonzini 64169e0a03cSPaolo Bonzini load_regs(cpu); 64269e0a03cSPaolo Bonzini decode_instruction(env, &decode); 64369e0a03cSPaolo Bonzini exec_instruction(env, &decode); 64469e0a03cSPaolo Bonzini store_regs(cpu); 64569e0a03cSPaolo Bonzini break; 64669e0a03cSPaolo Bonzini } 64769e0a03cSPaolo Bonzini case EXIT_REASON_TPR: { 64869e0a03cSPaolo Bonzini ret = 1; 64969e0a03cSPaolo Bonzini break; 65069e0a03cSPaolo Bonzini } 65169e0a03cSPaolo Bonzini case EXIT_REASON_TASK_SWITCH: { 652b533450eSAlexander Graf uint64_t vinfo = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO); 65369e0a03cSPaolo Bonzini x68_segment_selector sel = {.sel = exit_qual & 0xffff}; 65469e0a03cSPaolo Bonzini vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, 65569e0a03cSPaolo Bonzini vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo 65669e0a03cSPaolo Bonzini & VMCS_INTR_T_MASK); 65769e0a03cSPaolo Bonzini break; 65869e0a03cSPaolo Bonzini } 65969e0a03cSPaolo Bonzini case EXIT_REASON_TRIPLE_FAULT: { 66069e0a03cSPaolo Bonzini qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 66169e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 66269e0a03cSPaolo Bonzini break; 66369e0a03cSPaolo Bonzini } 66469e0a03cSPaolo Bonzini case EXIT_REASON_RDPMC: 665b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RAX, 0); 666b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RDX, 0); 66769e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 66869e0a03cSPaolo Bonzini break; 66969e0a03cSPaolo Bonzini case VMX_REASON_VMCALL: 670fd13f23bSLiran Alon env->exception_nr = EXCP0D_GPF; 671fd13f23bSLiran Alon env->exception_injected = 1; 67269e0a03cSPaolo Bonzini env->has_error_code = true; 67369e0a03cSPaolo Bonzini env->error_code = 0; 67469e0a03cSPaolo Bonzini break; 67569e0a03cSPaolo Bonzini default: 6762d9178d9SLaurent Vivier error_report("%llx: unhandled exit %llx", rip, exit_reason); 67769e0a03cSPaolo Bonzini } 67869e0a03cSPaolo Bonzini } while (ret == 0); 67969e0a03cSPaolo Bonzini 68069e0a03cSPaolo Bonzini return ret; 68169e0a03cSPaolo Bonzini } 682f4152040SFrancesco Cagnin 683f4152040SFrancesco Cagnin int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 684f4152040SFrancesco Cagnin { 685f4152040SFrancesco Cagnin return -ENOSYS; 686f4152040SFrancesco Cagnin } 687f4152040SFrancesco Cagnin 688f4152040SFrancesco Cagnin int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 689f4152040SFrancesco Cagnin { 690f4152040SFrancesco Cagnin return -ENOSYS; 691f4152040SFrancesco Cagnin } 692f4152040SFrancesco Cagnin 693f4152040SFrancesco Cagnin int hvf_arch_insert_hw_breakpoint(target_ulong addr, target_ulong len, int type) 694f4152040SFrancesco Cagnin { 695f4152040SFrancesco Cagnin return -ENOSYS; 696f4152040SFrancesco Cagnin } 697f4152040SFrancesco Cagnin 698f4152040SFrancesco Cagnin int hvf_arch_remove_hw_breakpoint(target_ulong addr, target_ulong len, int type) 699f4152040SFrancesco Cagnin { 700f4152040SFrancesco Cagnin return -ENOSYS; 701f4152040SFrancesco Cagnin } 702f4152040SFrancesco Cagnin 703f4152040SFrancesco Cagnin void hvf_arch_remove_all_hw_breakpoints(void) 704f4152040SFrancesco Cagnin { 705f4152040SFrancesco Cagnin } 706*eb2edc42SFrancesco Cagnin 707*eb2edc42SFrancesco Cagnin void hvf_arch_update_guest_debug(CPUState *cpu) 708*eb2edc42SFrancesco Cagnin { 709*eb2edc42SFrancesco Cagnin } 710*eb2edc42SFrancesco Cagnin 711*eb2edc42SFrancesco Cagnin inline bool hvf_arch_supports_guest_debug(void) 712*eb2edc42SFrancesco Cagnin { 713*eb2edc42SFrancesco Cagnin return false; 714*eb2edc42SFrancesco Cagnin } 715