169e0a03cSPaolo Bonzini /* Copyright 2008 IBM Corporation 269e0a03cSPaolo Bonzini * 2008 Red Hat, Inc. 369e0a03cSPaolo Bonzini * Copyright 2011 Intel Corporation 469e0a03cSPaolo Bonzini * Copyright 2016 Veertu, Inc. 569e0a03cSPaolo Bonzini * Copyright 2017 The Android Open Source Project 669e0a03cSPaolo Bonzini * 769e0a03cSPaolo Bonzini * QEMU Hypervisor.framework support 869e0a03cSPaolo Bonzini * 969e0a03cSPaolo Bonzini * This program is free software; you can redistribute it and/or 1069e0a03cSPaolo Bonzini * modify it under the terms of version 2 of the GNU General Public 1169e0a03cSPaolo Bonzini * License as published by the Free Software Foundation. 1269e0a03cSPaolo Bonzini * 1369e0a03cSPaolo Bonzini * This program is distributed in the hope that it will be useful, 1469e0a03cSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 1569e0a03cSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16e361a772SThomas Huth * General Public License for more details. 1769e0a03cSPaolo Bonzini * 18e361a772SThomas Huth * You should have received a copy of the GNU General Public License 19e361a772SThomas Huth * along with this program; if not, see <http://www.gnu.org/licenses/>. 20d781e24dSIzik Eidus * 21d781e24dSIzik Eidus * This file contain code under public domain from the hvdos project: 22d781e24dSIzik Eidus * https://github.com/mist64/hvdos 234d98a8e5SPaolo Bonzini * 244d98a8e5SPaolo Bonzini * Parts Copyright (c) 2011 NetApp, Inc. 254d98a8e5SPaolo Bonzini * All rights reserved. 264d98a8e5SPaolo Bonzini * 274d98a8e5SPaolo Bonzini * Redistribution and use in source and binary forms, with or without 284d98a8e5SPaolo Bonzini * modification, are permitted provided that the following conditions 294d98a8e5SPaolo Bonzini * are met: 304d98a8e5SPaolo Bonzini * 1. Redistributions of source code must retain the above copyright 314d98a8e5SPaolo Bonzini * notice, this list of conditions and the following disclaimer. 324d98a8e5SPaolo Bonzini * 2. Redistributions in binary form must reproduce the above copyright 334d98a8e5SPaolo Bonzini * notice, this list of conditions and the following disclaimer in the 344d98a8e5SPaolo Bonzini * documentation and/or other materials provided with the distribution. 354d98a8e5SPaolo Bonzini * 364d98a8e5SPaolo Bonzini * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 374d98a8e5SPaolo Bonzini * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 384d98a8e5SPaolo Bonzini * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 394d98a8e5SPaolo Bonzini * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 404d98a8e5SPaolo Bonzini * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 414d98a8e5SPaolo Bonzini * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 424d98a8e5SPaolo Bonzini * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 434d98a8e5SPaolo Bonzini * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 444d98a8e5SPaolo Bonzini * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 454d98a8e5SPaolo Bonzini * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 464d98a8e5SPaolo Bonzini * SUCH DAMAGE. 4769e0a03cSPaolo Bonzini */ 4854d31236SMarkus Armbruster 4969e0a03cSPaolo Bonzini #include "qemu/osdep.h" 5069e0a03cSPaolo Bonzini #include "qemu-common.h" 5169e0a03cSPaolo Bonzini #include "qemu/error-report.h" 5269e0a03cSPaolo Bonzini 5369e0a03cSPaolo Bonzini #include "sysemu/hvf.h" 54d57bc3c1SAlexander Graf #include "sysemu/hvf_int.h" 5554d31236SMarkus Armbruster #include "sysemu/runstate.h" 5669e0a03cSPaolo Bonzini #include "hvf-i386.h" 5769e0a03cSPaolo Bonzini #include "vmcs.h" 5869e0a03cSPaolo Bonzini #include "vmx.h" 5969e0a03cSPaolo Bonzini #include "x86.h" 6069e0a03cSPaolo Bonzini #include "x86_descr.h" 6169e0a03cSPaolo Bonzini #include "x86_mmu.h" 6269e0a03cSPaolo Bonzini #include "x86_decode.h" 6369e0a03cSPaolo Bonzini #include "x86_emu.h" 6469e0a03cSPaolo Bonzini #include "x86_task.h" 6569e0a03cSPaolo Bonzini #include "x86hvf.h" 6669e0a03cSPaolo Bonzini 6769e0a03cSPaolo Bonzini #include <Hypervisor/hv.h> 6869e0a03cSPaolo Bonzini #include <Hypervisor/hv_vmx.h> 693b502b0eSVladislav Yaroshchuk #include <sys/sysctl.h> 7069e0a03cSPaolo Bonzini 7169e0a03cSPaolo Bonzini #include "hw/i386/apic_internal.h" 7269e0a03cSPaolo Bonzini #include "qemu/main-loop.h" 73940e43aaSClaudio Fontana #include "qemu/accel.h" 7469e0a03cSPaolo Bonzini #include "target/i386/cpu.h" 7569e0a03cSPaolo Bonzini 7669e0a03cSPaolo Bonzini void vmx_update_tpr(CPUState *cpu) 7769e0a03cSPaolo Bonzini { 7869e0a03cSPaolo Bonzini /* TODO: need integrate APIC handling */ 7969e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 8069e0a03cSPaolo Bonzini int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; 8169e0a03cSPaolo Bonzini int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); 8269e0a03cSPaolo Bonzini 83b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_TPR, tpr); 8469e0a03cSPaolo Bonzini if (irr == -1) { 85b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); 8669e0a03cSPaolo Bonzini } else { 87b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : 8869e0a03cSPaolo Bonzini irr >> 4); 8969e0a03cSPaolo Bonzini } 9069e0a03cSPaolo Bonzini } 9169e0a03cSPaolo Bonzini 92583ae161SRoman Bolshakov static void update_apic_tpr(CPUState *cpu) 9369e0a03cSPaolo Bonzini { 9469e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 95b533450eSAlexander Graf int tpr = rreg(cpu->hvf->fd, HV_X86_TPR) >> 4; 9669e0a03cSPaolo Bonzini cpu_set_apic_tpr(x86_cpu->apic_state, tpr); 9769e0a03cSPaolo Bonzini } 9869e0a03cSPaolo Bonzini 9969e0a03cSPaolo Bonzini #define VECTORING_INFO_VECTOR_MASK 0xff 10069e0a03cSPaolo Bonzini 10169e0a03cSPaolo Bonzini void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer, 10269e0a03cSPaolo Bonzini int direction, int size, int count) 10369e0a03cSPaolo Bonzini { 10469e0a03cSPaolo Bonzini int i; 10569e0a03cSPaolo Bonzini uint8_t *ptr = buffer; 10669e0a03cSPaolo Bonzini 10769e0a03cSPaolo Bonzini for (i = 0; i < count; i++) { 10869e0a03cSPaolo Bonzini address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED, 10969e0a03cSPaolo Bonzini ptr, size, 11069e0a03cSPaolo Bonzini direction); 11169e0a03cSPaolo Bonzini ptr += size; 11269e0a03cSPaolo Bonzini } 11369e0a03cSPaolo Bonzini } 11469e0a03cSPaolo Bonzini 115ff2de166SPaolo Bonzini static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept_qual) 11669e0a03cSPaolo Bonzini { 11769e0a03cSPaolo Bonzini int read, write; 11869e0a03cSPaolo Bonzini 11969e0a03cSPaolo Bonzini /* EPT fault on an instruction fetch doesn't make sense here */ 12069e0a03cSPaolo Bonzini if (ept_qual & EPT_VIOLATION_INST_FETCH) { 12169e0a03cSPaolo Bonzini return false; 12269e0a03cSPaolo Bonzini } 12369e0a03cSPaolo Bonzini 12469e0a03cSPaolo Bonzini /* EPT fault must be a read fault or a write fault */ 12569e0a03cSPaolo Bonzini read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0; 12669e0a03cSPaolo Bonzini write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0; 12769e0a03cSPaolo Bonzini if ((read | write) == 0) { 12869e0a03cSPaolo Bonzini return false; 12969e0a03cSPaolo Bonzini } 13069e0a03cSPaolo Bonzini 13169e0a03cSPaolo Bonzini if (write && slot) { 13269e0a03cSPaolo Bonzini if (slot->flags & HVF_SLOT_LOG) { 13369e0a03cSPaolo Bonzini memory_region_set_dirty(slot->region, gpa - slot->start, 1); 13469e0a03cSPaolo Bonzini hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, 13569e0a03cSPaolo Bonzini HV_MEMORY_READ | HV_MEMORY_WRITE); 13669e0a03cSPaolo Bonzini } 13769e0a03cSPaolo Bonzini } 13869e0a03cSPaolo Bonzini 13969e0a03cSPaolo Bonzini /* 14069e0a03cSPaolo Bonzini * The EPT violation must have been caused by accessing a 14169e0a03cSPaolo Bonzini * guest-physical address that is a translation of a guest-linear 14269e0a03cSPaolo Bonzini * address. 14369e0a03cSPaolo Bonzini */ 14469e0a03cSPaolo Bonzini if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 || 14569e0a03cSPaolo Bonzini (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) { 14669e0a03cSPaolo Bonzini return false; 14769e0a03cSPaolo Bonzini } 14869e0a03cSPaolo Bonzini 149fbafbb6dSCameron Esfahani if (!slot) { 150fbafbb6dSCameron Esfahani return true; 151fbafbb6dSCameron Esfahani } 152fbafbb6dSCameron Esfahani if (!memory_region_is_ram(slot->region) && 153fbafbb6dSCameron Esfahani !(read && memory_region_is_romd(slot->region))) { 154fbafbb6dSCameron Esfahani return true; 155fbafbb6dSCameron Esfahani } 156fbafbb6dSCameron Esfahani return false; 15769e0a03cSPaolo Bonzini } 15869e0a03cSPaolo Bonzini 159cfe58455SAlexander Graf void hvf_arch_vcpu_destroy(CPUState *cpu) 16069e0a03cSPaolo Bonzini { 161fe76b09cSRoman Bolshakov X86CPU *x86_cpu = X86_CPU(cpu); 162fe76b09cSRoman Bolshakov CPUX86State *env = &x86_cpu->env; 163fe76b09cSRoman Bolshakov 164fe76b09cSRoman Bolshakov g_free(env->hvf_mmio_buf); 16569e0a03cSPaolo Bonzini } 16669e0a03cSPaolo Bonzini 1673b502b0eSVladislav Yaroshchuk static void init_tsc_freq(CPUX86State *env) 1683b502b0eSVladislav Yaroshchuk { 1693b502b0eSVladislav Yaroshchuk size_t length; 1703b502b0eSVladislav Yaroshchuk uint64_t tsc_freq; 1713b502b0eSVladislav Yaroshchuk 1723b502b0eSVladislav Yaroshchuk if (env->tsc_khz != 0) { 1733b502b0eSVladislav Yaroshchuk return; 1743b502b0eSVladislav Yaroshchuk } 1753b502b0eSVladislav Yaroshchuk 1763b502b0eSVladislav Yaroshchuk length = sizeof(uint64_t); 1773b502b0eSVladislav Yaroshchuk if (sysctlbyname("machdep.tsc.frequency", &tsc_freq, &length, NULL, 0)) { 1783b502b0eSVladislav Yaroshchuk return; 1793b502b0eSVladislav Yaroshchuk } 1803b502b0eSVladislav Yaroshchuk env->tsc_khz = tsc_freq / 1000; /* Hz to KHz */ 1813b502b0eSVladislav Yaroshchuk } 1823b502b0eSVladislav Yaroshchuk 1833b502b0eSVladislav Yaroshchuk static void init_apic_bus_freq(CPUX86State *env) 1843b502b0eSVladislav Yaroshchuk { 1853b502b0eSVladislav Yaroshchuk size_t length; 1863b502b0eSVladislav Yaroshchuk uint64_t bus_freq; 1873b502b0eSVladislav Yaroshchuk 1883b502b0eSVladislav Yaroshchuk if (env->apic_bus_freq != 0) { 1893b502b0eSVladislav Yaroshchuk return; 1903b502b0eSVladislav Yaroshchuk } 1913b502b0eSVladislav Yaroshchuk 1923b502b0eSVladislav Yaroshchuk length = sizeof(uint64_t); 1933b502b0eSVladislav Yaroshchuk if (sysctlbyname("hw.busfrequency", &bus_freq, &length, NULL, 0)) { 1943b502b0eSVladislav Yaroshchuk return; 1953b502b0eSVladislav Yaroshchuk } 1963b502b0eSVladislav Yaroshchuk env->apic_bus_freq = bus_freq; 1973b502b0eSVladislav Yaroshchuk } 1983b502b0eSVladislav Yaroshchuk 1993b502b0eSVladislav Yaroshchuk static inline bool tsc_is_known(CPUX86State *env) 2003b502b0eSVladislav Yaroshchuk { 2013b502b0eSVladislav Yaroshchuk return env->tsc_khz != 0; 2023b502b0eSVladislav Yaroshchuk } 2033b502b0eSVladislav Yaroshchuk 2043b502b0eSVladislav Yaroshchuk static inline bool apic_bus_freq_is_known(CPUX86State *env) 2053b502b0eSVladislav Yaroshchuk { 2063b502b0eSVladislav Yaroshchuk return env->apic_bus_freq != 0; 2073b502b0eSVladislav Yaroshchuk } 2083b502b0eSVladislav Yaroshchuk 209cfe58455SAlexander Graf int hvf_arch_init_vcpu(CPUState *cpu) 21069e0a03cSPaolo Bonzini { 21169e0a03cSPaolo Bonzini X86CPU *x86cpu = X86_CPU(cpu); 21269e0a03cSPaolo Bonzini CPUX86State *env = &x86cpu->env; 21369e0a03cSPaolo Bonzini 21469e0a03cSPaolo Bonzini init_emu(); 21569e0a03cSPaolo Bonzini init_decoder(); 21669e0a03cSPaolo Bonzini 21769e0a03cSPaolo Bonzini hvf_state->hvf_caps = g_new0(struct hvf_vcpu_caps, 1); 218fe76b09cSRoman Bolshakov env->hvf_mmio_buf = g_new(char, 4096); 21969e0a03cSPaolo Bonzini 2203b502b0eSVladislav Yaroshchuk if (x86cpu->vmware_cpuid_freq) { 2213b502b0eSVladislav Yaroshchuk init_tsc_freq(env); 2223b502b0eSVladislav Yaroshchuk init_apic_bus_freq(env); 2233b502b0eSVladislav Yaroshchuk 2243b502b0eSVladislav Yaroshchuk if (!tsc_is_known(env) || !apic_bus_freq_is_known(env)) { 2253b502b0eSVladislav Yaroshchuk error_report("vmware-cpuid-freq: feature couldn't be enabled"); 2263b502b0eSVladislav Yaroshchuk } 2273b502b0eSVladislav Yaroshchuk } 2283b502b0eSVladislav Yaroshchuk 22969e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, 23069e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_pinbased)) { 23169e0a03cSPaolo Bonzini abort(); 23269e0a03cSPaolo Bonzini } 23369e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, 23469e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_procbased)) { 23569e0a03cSPaolo Bonzini abort(); 23669e0a03cSPaolo Bonzini } 23769e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, 23869e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_procbased2)) { 23969e0a03cSPaolo Bonzini abort(); 24069e0a03cSPaolo Bonzini } 24169e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, 24269e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_entry)) { 24369e0a03cSPaolo Bonzini abort(); 24469e0a03cSPaolo Bonzini } 24569e0a03cSPaolo Bonzini 24669e0a03cSPaolo Bonzini /* set VMCS control fields */ 247b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS, 24869e0a03cSPaolo Bonzini cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, 24969e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_EXTINT | 25069e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_NMI | 25169e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_VNMI)); 252b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, 25369e0a03cSPaolo Bonzini cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, 25469e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_HLT | 25569e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_MWAIT | 25669e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET | 25769e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) | 25869e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL); 259b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS, 26069e0a03cSPaolo Bonzini cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, 26169e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES)); 26269e0a03cSPaolo Bonzini 263b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, 26469e0a03cSPaolo Bonzini 0)); 265b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ 26669e0a03cSPaolo Bonzini 267b533450eSAlexander Graf wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); 26869e0a03cSPaolo Bonzini 26969e0a03cSPaolo Bonzini x86cpu = X86_CPU(cpu); 270*c0198c5fSDavid Edmondson x86cpu->env.xsave_buf_len = 4096; 271*c0198c5fSDavid Edmondson x86cpu->env.xsave_buf = qemu_memalign(4096, x86cpu->env.xsave_buf_len); 27269e0a03cSPaolo Bonzini 273b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1); 274b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1); 275b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1); 276b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1); 277b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1); 278b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1); 279b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1); 280b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1); 281b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1); 282b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1); 283b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1); 284b533450eSAlexander Graf hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1); 28569e0a03cSPaolo Bonzini 28669e0a03cSPaolo Bonzini return 0; 28769e0a03cSPaolo Bonzini } 28869e0a03cSPaolo Bonzini 28969e0a03cSPaolo Bonzini static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info) 29069e0a03cSPaolo Bonzini { 29169e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 29269e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 29369e0a03cSPaolo Bonzini 294fd13f23bSLiran Alon env->exception_nr = -1; 295fd13f23bSLiran Alon env->exception_pending = 0; 296fd13f23bSLiran Alon env->exception_injected = 0; 29769e0a03cSPaolo Bonzini env->interrupt_injected = -1; 29869e0a03cSPaolo Bonzini env->nmi_injected = false; 29964bef038SCameron Esfahani env->ins_len = 0; 30064bef038SCameron Esfahani env->has_error_code = false; 30169e0a03cSPaolo Bonzini if (idtvec_info & VMCS_IDT_VEC_VALID) { 30269e0a03cSPaolo Bonzini switch (idtvec_info & VMCS_IDT_VEC_TYPE) { 30369e0a03cSPaolo Bonzini case VMCS_IDT_VEC_HWINTR: 30469e0a03cSPaolo Bonzini case VMCS_IDT_VEC_SWINTR: 30569e0a03cSPaolo Bonzini env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM; 30669e0a03cSPaolo Bonzini break; 30769e0a03cSPaolo Bonzini case VMCS_IDT_VEC_NMI: 30869e0a03cSPaolo Bonzini env->nmi_injected = true; 30969e0a03cSPaolo Bonzini break; 31069e0a03cSPaolo Bonzini case VMCS_IDT_VEC_HWEXCEPTION: 31169e0a03cSPaolo Bonzini case VMCS_IDT_VEC_SWEXCEPTION: 312fd13f23bSLiran Alon env->exception_nr = idtvec_info & VMCS_IDT_VEC_VECNUM; 313fd13f23bSLiran Alon env->exception_injected = 1; 31469e0a03cSPaolo Bonzini break; 31569e0a03cSPaolo Bonzini case VMCS_IDT_VEC_PRIV_SWEXCEPTION: 31669e0a03cSPaolo Bonzini default: 31769e0a03cSPaolo Bonzini abort(); 31869e0a03cSPaolo Bonzini } 31969e0a03cSPaolo Bonzini if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION || 32069e0a03cSPaolo Bonzini (idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) { 32169e0a03cSPaolo Bonzini env->ins_len = ins_len; 32269e0a03cSPaolo Bonzini } 32364bef038SCameron Esfahani if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { 32469e0a03cSPaolo Bonzini env->has_error_code = true; 325b533450eSAlexander Graf env->error_code = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERROR); 32669e0a03cSPaolo Bonzini } 32769e0a03cSPaolo Bonzini } 328b533450eSAlexander Graf if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & 32969e0a03cSPaolo Bonzini VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { 33069e0a03cSPaolo Bonzini env->hflags2 |= HF2_NMI_MASK; 33169e0a03cSPaolo Bonzini } else { 33269e0a03cSPaolo Bonzini env->hflags2 &= ~HF2_NMI_MASK; 33369e0a03cSPaolo Bonzini } 334b533450eSAlexander Graf if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & 33569e0a03cSPaolo Bonzini (VMCS_INTERRUPTIBILITY_STI_BLOCKING | 33669e0a03cSPaolo Bonzini VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { 33769e0a03cSPaolo Bonzini env->hflags |= HF_INHIBIT_IRQ_MASK; 33869e0a03cSPaolo Bonzini } else { 33969e0a03cSPaolo Bonzini env->hflags &= ~HF_INHIBIT_IRQ_MASK; 34069e0a03cSPaolo Bonzini } 34169e0a03cSPaolo Bonzini } 34269e0a03cSPaolo Bonzini 3433b502b0eSVladislav Yaroshchuk static void hvf_cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 3443b502b0eSVladislav Yaroshchuk uint32_t *eax, uint32_t *ebx, 3453b502b0eSVladislav Yaroshchuk uint32_t *ecx, uint32_t *edx) 3463b502b0eSVladislav Yaroshchuk { 3473b502b0eSVladislav Yaroshchuk /* 3483b502b0eSVladislav Yaroshchuk * A wrapper extends cpu_x86_cpuid with 0x40000000 and 0x40000010 leafs, 3493b502b0eSVladislav Yaroshchuk * leafs 0x40000001-0x4000000F are filled with zeros 3503b502b0eSVladislav Yaroshchuk * Provides vmware-cpuid-freq support to hvf 3513b502b0eSVladislav Yaroshchuk * 3523b502b0eSVladislav Yaroshchuk * Note: leaf 0x40000000 not exposes HVF, 3533b502b0eSVladislav Yaroshchuk * leaving hypervisor signature empty 3543b502b0eSVladislav Yaroshchuk */ 3553b502b0eSVladislav Yaroshchuk 3563b502b0eSVladislav Yaroshchuk if (index < 0x40000000 || index > 0x40000010 || 3573b502b0eSVladislav Yaroshchuk !tsc_is_known(env) || !apic_bus_freq_is_known(env)) { 3583b502b0eSVladislav Yaroshchuk 3593b502b0eSVladislav Yaroshchuk cpu_x86_cpuid(env, index, count, eax, ebx, ecx, edx); 3603b502b0eSVladislav Yaroshchuk return; 3613b502b0eSVladislav Yaroshchuk } 3623b502b0eSVladislav Yaroshchuk 3633b502b0eSVladislav Yaroshchuk switch (index) { 3643b502b0eSVladislav Yaroshchuk case 0x40000000: 3653b502b0eSVladislav Yaroshchuk *eax = 0x40000010; /* Max available cpuid leaf */ 3663b502b0eSVladislav Yaroshchuk *ebx = 0; /* Leave signature empty */ 3673b502b0eSVladislav Yaroshchuk *ecx = 0; 3683b502b0eSVladislav Yaroshchuk *edx = 0; 3693b502b0eSVladislav Yaroshchuk break; 3703b502b0eSVladislav Yaroshchuk case 0x40000010: 3713b502b0eSVladislav Yaroshchuk *eax = env->tsc_khz; 3723b502b0eSVladislav Yaroshchuk *ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ 3733b502b0eSVladislav Yaroshchuk *ecx = 0; 3743b502b0eSVladislav Yaroshchuk *edx = 0; 3753b502b0eSVladislav Yaroshchuk break; 3763b502b0eSVladislav Yaroshchuk default: 3773b502b0eSVladislav Yaroshchuk *eax = 0; 3783b502b0eSVladislav Yaroshchuk *ebx = 0; 3793b502b0eSVladislav Yaroshchuk *ecx = 0; 3803b502b0eSVladislav Yaroshchuk *edx = 0; 3813b502b0eSVladislav Yaroshchuk break; 3823b502b0eSVladislav Yaroshchuk } 3833b502b0eSVladislav Yaroshchuk } 3843b502b0eSVladislav Yaroshchuk 38569e0a03cSPaolo Bonzini int hvf_vcpu_exec(CPUState *cpu) 38669e0a03cSPaolo Bonzini { 38769e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 38869e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 38969e0a03cSPaolo Bonzini int ret = 0; 39069e0a03cSPaolo Bonzini uint64_t rip = 0; 39169e0a03cSPaolo Bonzini 39269e0a03cSPaolo Bonzini if (hvf_process_events(cpu)) { 39369e0a03cSPaolo Bonzini return EXCP_HLT; 39469e0a03cSPaolo Bonzini } 39569e0a03cSPaolo Bonzini 39669e0a03cSPaolo Bonzini do { 39769e0a03cSPaolo Bonzini if (cpu->vcpu_dirty) { 39869e0a03cSPaolo Bonzini hvf_put_registers(cpu); 39969e0a03cSPaolo Bonzini cpu->vcpu_dirty = false; 40069e0a03cSPaolo Bonzini } 40169e0a03cSPaolo Bonzini 40269e0a03cSPaolo Bonzini if (hvf_inject_interrupts(cpu)) { 40369e0a03cSPaolo Bonzini return EXCP_INTERRUPT; 40469e0a03cSPaolo Bonzini } 40569e0a03cSPaolo Bonzini vmx_update_tpr(cpu); 40669e0a03cSPaolo Bonzini 40769e0a03cSPaolo Bonzini qemu_mutex_unlock_iothread(); 40869e0a03cSPaolo Bonzini if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) { 40969e0a03cSPaolo Bonzini qemu_mutex_lock_iothread(); 41069e0a03cSPaolo Bonzini return EXCP_HLT; 41169e0a03cSPaolo Bonzini } 41269e0a03cSPaolo Bonzini 413b533450eSAlexander Graf hv_return_t r = hv_vcpu_run(cpu->hvf->fd); 41469e0a03cSPaolo Bonzini assert_hvf_ok(r); 41569e0a03cSPaolo Bonzini 41669e0a03cSPaolo Bonzini /* handle VMEXIT */ 417b533450eSAlexander Graf uint64_t exit_reason = rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON); 418b533450eSAlexander Graf uint64_t exit_qual = rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION); 419b533450eSAlexander Graf uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf->fd, 42069e0a03cSPaolo Bonzini VMCS_EXIT_INSTRUCTION_LENGTH); 42169e0a03cSPaolo Bonzini 422b533450eSAlexander Graf uint64_t idtvec_info = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO); 42369e0a03cSPaolo Bonzini 42469e0a03cSPaolo Bonzini hvf_store_events(cpu, ins_len, idtvec_info); 425b533450eSAlexander Graf rip = rreg(cpu->hvf->fd, HV_X86_RIP); 426b533450eSAlexander Graf env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS); 42769e0a03cSPaolo Bonzini 42869e0a03cSPaolo Bonzini qemu_mutex_lock_iothread(); 42969e0a03cSPaolo Bonzini 43069e0a03cSPaolo Bonzini update_apic_tpr(cpu); 43169e0a03cSPaolo Bonzini current_cpu = cpu; 43269e0a03cSPaolo Bonzini 43369e0a03cSPaolo Bonzini ret = 0; 43469e0a03cSPaolo Bonzini switch (exit_reason) { 43569e0a03cSPaolo Bonzini case EXIT_REASON_HLT: { 43669e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 43769e0a03cSPaolo Bonzini if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && 438967f4da2SRoman Bolshakov (env->eflags & IF_MASK)) 43969e0a03cSPaolo Bonzini && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) && 44069e0a03cSPaolo Bonzini !(idtvec_info & VMCS_IDT_VEC_VALID)) { 44169e0a03cSPaolo Bonzini cpu->halted = 1; 44269e0a03cSPaolo Bonzini ret = EXCP_HLT; 4433b9c59daSChen Zhang break; 44469e0a03cSPaolo Bonzini } 44569e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 44669e0a03cSPaolo Bonzini break; 44769e0a03cSPaolo Bonzini } 44869e0a03cSPaolo Bonzini case EXIT_REASON_MWAIT: { 44969e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 45069e0a03cSPaolo Bonzini break; 45169e0a03cSPaolo Bonzini } 452fbafbb6dSCameron Esfahani /* Need to check if MMIO or unmapped fault */ 45369e0a03cSPaolo Bonzini case EXIT_REASON_EPT_FAULT: 45469e0a03cSPaolo Bonzini { 45569e0a03cSPaolo Bonzini hvf_slot *slot; 456b533450eSAlexander Graf uint64_t gpa = rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRESS); 45769e0a03cSPaolo Bonzini 45869e0a03cSPaolo Bonzini if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) && 45969e0a03cSPaolo Bonzini ((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) { 46069e0a03cSPaolo Bonzini vmx_set_nmi_blocking(cpu); 46169e0a03cSPaolo Bonzini } 46269e0a03cSPaolo Bonzini 463fbafbb6dSCameron Esfahani slot = hvf_find_overlap_slot(gpa, 1); 46469e0a03cSPaolo Bonzini /* mmio */ 46569e0a03cSPaolo Bonzini if (ept_emulation_fault(slot, gpa, exit_qual)) { 46669e0a03cSPaolo Bonzini struct x86_decode decode; 46769e0a03cSPaolo Bonzini 46869e0a03cSPaolo Bonzini load_regs(cpu); 46969e0a03cSPaolo Bonzini decode_instruction(env, &decode); 47069e0a03cSPaolo Bonzini exec_instruction(env, &decode); 47169e0a03cSPaolo Bonzini store_regs(cpu); 47269e0a03cSPaolo Bonzini break; 47369e0a03cSPaolo Bonzini } 47469e0a03cSPaolo Bonzini break; 47569e0a03cSPaolo Bonzini } 47669e0a03cSPaolo Bonzini case EXIT_REASON_INOUT: 47769e0a03cSPaolo Bonzini { 47869e0a03cSPaolo Bonzini uint32_t in = (exit_qual & 8) != 0; 47969e0a03cSPaolo Bonzini uint32_t size = (exit_qual & 7) + 1; 48069e0a03cSPaolo Bonzini uint32_t string = (exit_qual & 16) != 0; 48169e0a03cSPaolo Bonzini uint32_t port = exit_qual >> 16; 48269e0a03cSPaolo Bonzini /*uint32_t rep = (exit_qual & 0x20) != 0;*/ 48369e0a03cSPaolo Bonzini 48469e0a03cSPaolo Bonzini if (!string && in) { 48569e0a03cSPaolo Bonzini uint64_t val = 0; 48669e0a03cSPaolo Bonzini load_regs(cpu); 48769e0a03cSPaolo Bonzini hvf_handle_io(env, port, &val, 0, size, 1); 48869e0a03cSPaolo Bonzini if (size == 1) { 48969e0a03cSPaolo Bonzini AL(env) = val; 49069e0a03cSPaolo Bonzini } else if (size == 2) { 49169e0a03cSPaolo Bonzini AX(env) = val; 49269e0a03cSPaolo Bonzini } else if (size == 4) { 49369e0a03cSPaolo Bonzini RAX(env) = (uint32_t)val; 49469e0a03cSPaolo Bonzini } else { 495da20f5cdSPaolo Bonzini RAX(env) = (uint64_t)val; 49669e0a03cSPaolo Bonzini } 4975d32173fSRoman Bolshakov env->eip += ins_len; 49869e0a03cSPaolo Bonzini store_regs(cpu); 49969e0a03cSPaolo Bonzini break; 50069e0a03cSPaolo Bonzini } else if (!string && !in) { 501b533450eSAlexander Graf RAX(env) = rreg(cpu->hvf->fd, HV_X86_RAX); 50269e0a03cSPaolo Bonzini hvf_handle_io(env, port, &RAX(env), 1, size, 1); 50369e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 50469e0a03cSPaolo Bonzini break; 50569e0a03cSPaolo Bonzini } 50669e0a03cSPaolo Bonzini struct x86_decode decode; 50769e0a03cSPaolo Bonzini 50869e0a03cSPaolo Bonzini load_regs(cpu); 50969e0a03cSPaolo Bonzini decode_instruction(env, &decode); 510e62963bfSPaolo Bonzini assert(ins_len == decode.len); 51169e0a03cSPaolo Bonzini exec_instruction(env, &decode); 51269e0a03cSPaolo Bonzini store_regs(cpu); 51369e0a03cSPaolo Bonzini 51469e0a03cSPaolo Bonzini break; 51569e0a03cSPaolo Bonzini } 51669e0a03cSPaolo Bonzini case EXIT_REASON_CPUID: { 517b533450eSAlexander Graf uint32_t rax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); 518b533450eSAlexander Graf uint32_t rbx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX); 519b533450eSAlexander Graf uint32_t rcx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); 520b533450eSAlexander Graf uint32_t rdx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); 52169e0a03cSPaolo Bonzini 522106f91d5SAlexander Graf if (rax == 1) { 523106f91d5SAlexander Graf /* CPUID1.ecx.OSXSAVE needs to know CR4 */ 524b533450eSAlexander Graf env->cr[4] = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); 525106f91d5SAlexander Graf } 5263b502b0eSVladislav Yaroshchuk hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); 52769e0a03cSPaolo Bonzini 528b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RAX, rax); 529b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RBX, rbx); 530b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RCX, rcx); 531b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RDX, rdx); 53269e0a03cSPaolo Bonzini 53369e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 53469e0a03cSPaolo Bonzini break; 53569e0a03cSPaolo Bonzini } 53669e0a03cSPaolo Bonzini case EXIT_REASON_XSETBV: { 53769e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 53869e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 539b533450eSAlexander Graf uint32_t eax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); 540b533450eSAlexander Graf uint32_t ecx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); 541b533450eSAlexander Graf uint32_t edx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); 54269e0a03cSPaolo Bonzini 54369e0a03cSPaolo Bonzini if (ecx) { 54469e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 54569e0a03cSPaolo Bonzini break; 54669e0a03cSPaolo Bonzini } 54769e0a03cSPaolo Bonzini env->xcr0 = ((uint64_t)edx << 32) | eax; 548b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1); 54969e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 55069e0a03cSPaolo Bonzini break; 55169e0a03cSPaolo Bonzini } 55269e0a03cSPaolo Bonzini case EXIT_REASON_INTR_WINDOW: 55369e0a03cSPaolo Bonzini vmx_clear_int_window_exiting(cpu); 55469e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 55569e0a03cSPaolo Bonzini break; 55669e0a03cSPaolo Bonzini case EXIT_REASON_NMI_WINDOW: 55769e0a03cSPaolo Bonzini vmx_clear_nmi_window_exiting(cpu); 55869e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 55969e0a03cSPaolo Bonzini break; 56069e0a03cSPaolo Bonzini case EXIT_REASON_EXT_INTR: 56169e0a03cSPaolo Bonzini /* force exit and allow io handling */ 56269e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 56369e0a03cSPaolo Bonzini break; 56469e0a03cSPaolo Bonzini case EXIT_REASON_RDMSR: 56569e0a03cSPaolo Bonzini case EXIT_REASON_WRMSR: 56669e0a03cSPaolo Bonzini { 56769e0a03cSPaolo Bonzini load_regs(cpu); 56869e0a03cSPaolo Bonzini if (exit_reason == EXIT_REASON_RDMSR) { 56969e0a03cSPaolo Bonzini simulate_rdmsr(cpu); 57069e0a03cSPaolo Bonzini } else { 57169e0a03cSPaolo Bonzini simulate_wrmsr(cpu); 57269e0a03cSPaolo Bonzini } 5735d32173fSRoman Bolshakov env->eip += ins_len; 57469e0a03cSPaolo Bonzini store_regs(cpu); 57569e0a03cSPaolo Bonzini break; 57669e0a03cSPaolo Bonzini } 57769e0a03cSPaolo Bonzini case EXIT_REASON_CR_ACCESS: { 57869e0a03cSPaolo Bonzini int cr; 57969e0a03cSPaolo Bonzini int reg; 58069e0a03cSPaolo Bonzini 58169e0a03cSPaolo Bonzini load_regs(cpu); 58269e0a03cSPaolo Bonzini cr = exit_qual & 15; 58369e0a03cSPaolo Bonzini reg = (exit_qual >> 8) & 15; 58469e0a03cSPaolo Bonzini 58569e0a03cSPaolo Bonzini switch (cr) { 58669e0a03cSPaolo Bonzini case 0x0: { 587b533450eSAlexander Graf macvm_set_cr0(cpu->hvf->fd, RRX(env, reg)); 58869e0a03cSPaolo Bonzini break; 58969e0a03cSPaolo Bonzini } 59069e0a03cSPaolo Bonzini case 4: { 591b533450eSAlexander Graf macvm_set_cr4(cpu->hvf->fd, RRX(env, reg)); 59269e0a03cSPaolo Bonzini break; 59369e0a03cSPaolo Bonzini } 59469e0a03cSPaolo Bonzini case 8: { 59569e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 59669e0a03cSPaolo Bonzini if (exit_qual & 0x10) { 59769e0a03cSPaolo Bonzini RRX(env, reg) = cpu_get_apic_tpr(x86_cpu->apic_state); 59869e0a03cSPaolo Bonzini } else { 59969e0a03cSPaolo Bonzini int tpr = RRX(env, reg); 60069e0a03cSPaolo Bonzini cpu_set_apic_tpr(x86_cpu->apic_state, tpr); 60169e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 60269e0a03cSPaolo Bonzini } 60369e0a03cSPaolo Bonzini break; 60469e0a03cSPaolo Bonzini } 60569e0a03cSPaolo Bonzini default: 6062d9178d9SLaurent Vivier error_report("Unrecognized CR %d", cr); 60769e0a03cSPaolo Bonzini abort(); 60869e0a03cSPaolo Bonzini } 6095d32173fSRoman Bolshakov env->eip += ins_len; 61069e0a03cSPaolo Bonzini store_regs(cpu); 61169e0a03cSPaolo Bonzini break; 61269e0a03cSPaolo Bonzini } 61369e0a03cSPaolo Bonzini case EXIT_REASON_APIC_ACCESS: { /* TODO */ 61469e0a03cSPaolo Bonzini struct x86_decode decode; 61569e0a03cSPaolo Bonzini 61669e0a03cSPaolo Bonzini load_regs(cpu); 61769e0a03cSPaolo Bonzini decode_instruction(env, &decode); 61869e0a03cSPaolo Bonzini exec_instruction(env, &decode); 61969e0a03cSPaolo Bonzini store_regs(cpu); 62069e0a03cSPaolo Bonzini break; 62169e0a03cSPaolo Bonzini } 62269e0a03cSPaolo Bonzini case EXIT_REASON_TPR: { 62369e0a03cSPaolo Bonzini ret = 1; 62469e0a03cSPaolo Bonzini break; 62569e0a03cSPaolo Bonzini } 62669e0a03cSPaolo Bonzini case EXIT_REASON_TASK_SWITCH: { 627b533450eSAlexander Graf uint64_t vinfo = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO); 62869e0a03cSPaolo Bonzini x68_segment_selector sel = {.sel = exit_qual & 0xffff}; 62969e0a03cSPaolo Bonzini vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, 63069e0a03cSPaolo Bonzini vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo 63169e0a03cSPaolo Bonzini & VMCS_INTR_T_MASK); 63269e0a03cSPaolo Bonzini break; 63369e0a03cSPaolo Bonzini } 63469e0a03cSPaolo Bonzini case EXIT_REASON_TRIPLE_FAULT: { 63569e0a03cSPaolo Bonzini qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 63669e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 63769e0a03cSPaolo Bonzini break; 63869e0a03cSPaolo Bonzini } 63969e0a03cSPaolo Bonzini case EXIT_REASON_RDPMC: 640b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RAX, 0); 641b533450eSAlexander Graf wreg(cpu->hvf->fd, HV_X86_RDX, 0); 64269e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 64369e0a03cSPaolo Bonzini break; 64469e0a03cSPaolo Bonzini case VMX_REASON_VMCALL: 645fd13f23bSLiran Alon env->exception_nr = EXCP0D_GPF; 646fd13f23bSLiran Alon env->exception_injected = 1; 64769e0a03cSPaolo Bonzini env->has_error_code = true; 64869e0a03cSPaolo Bonzini env->error_code = 0; 64969e0a03cSPaolo Bonzini break; 65069e0a03cSPaolo Bonzini default: 6512d9178d9SLaurent Vivier error_report("%llx: unhandled exit %llx", rip, exit_reason); 65269e0a03cSPaolo Bonzini } 65369e0a03cSPaolo Bonzini } while (ret == 0); 65469e0a03cSPaolo Bonzini 65569e0a03cSPaolo Bonzini return ret; 65669e0a03cSPaolo Bonzini } 657