169e0a03cSPaolo Bonzini /* Copyright 2008 IBM Corporation 269e0a03cSPaolo Bonzini * 2008 Red Hat, Inc. 369e0a03cSPaolo Bonzini * Copyright 2011 Intel Corporation 469e0a03cSPaolo Bonzini * Copyright 2016 Veertu, Inc. 569e0a03cSPaolo Bonzini * Copyright 2017 The Android Open Source Project 669e0a03cSPaolo Bonzini * 769e0a03cSPaolo Bonzini * QEMU Hypervisor.framework support 869e0a03cSPaolo Bonzini * 969e0a03cSPaolo Bonzini * This program is free software; you can redistribute it and/or 1069e0a03cSPaolo Bonzini * modify it under the terms of version 2 of the GNU General Public 1169e0a03cSPaolo Bonzini * License as published by the Free Software Foundation. 1269e0a03cSPaolo Bonzini * 1369e0a03cSPaolo Bonzini * This program is distributed in the hope that it will be useful, 1469e0a03cSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 1569e0a03cSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16e361a772SThomas Huth * General Public License for more details. 1769e0a03cSPaolo Bonzini * 18e361a772SThomas Huth * You should have received a copy of the GNU General Public License 19e361a772SThomas Huth * along with this program; if not, see <http://www.gnu.org/licenses/>. 20d781e24dSIzik Eidus * 21d781e24dSIzik Eidus * This file contain code under public domain from the hvdos project: 22d781e24dSIzik Eidus * https://github.com/mist64/hvdos 234d98a8e5SPaolo Bonzini * 244d98a8e5SPaolo Bonzini * Parts Copyright (c) 2011 NetApp, Inc. 254d98a8e5SPaolo Bonzini * All rights reserved. 264d98a8e5SPaolo Bonzini * 274d98a8e5SPaolo Bonzini * Redistribution and use in source and binary forms, with or without 284d98a8e5SPaolo Bonzini * modification, are permitted provided that the following conditions 294d98a8e5SPaolo Bonzini * are met: 304d98a8e5SPaolo Bonzini * 1. Redistributions of source code must retain the above copyright 314d98a8e5SPaolo Bonzini * notice, this list of conditions and the following disclaimer. 324d98a8e5SPaolo Bonzini * 2. Redistributions in binary form must reproduce the above copyright 334d98a8e5SPaolo Bonzini * notice, this list of conditions and the following disclaimer in the 344d98a8e5SPaolo Bonzini * documentation and/or other materials provided with the distribution. 354d98a8e5SPaolo Bonzini * 364d98a8e5SPaolo Bonzini * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 374d98a8e5SPaolo Bonzini * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 384d98a8e5SPaolo Bonzini * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 394d98a8e5SPaolo Bonzini * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 404d98a8e5SPaolo Bonzini * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 414d98a8e5SPaolo Bonzini * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 424d98a8e5SPaolo Bonzini * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 434d98a8e5SPaolo Bonzini * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 444d98a8e5SPaolo Bonzini * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 454d98a8e5SPaolo Bonzini * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 464d98a8e5SPaolo Bonzini * SUCH DAMAGE. 4769e0a03cSPaolo Bonzini */ 4854d31236SMarkus Armbruster 4969e0a03cSPaolo Bonzini #include "qemu/osdep.h" 5069e0a03cSPaolo Bonzini #include "qemu/error-report.h" 515df022cfSPeter Maydell #include "qemu/memalign.h" 529c267239SPhil Dennis-Jordan #include "qapi/error.h" 539c267239SPhil Dennis-Jordan #include "migration/blocker.h" 5469e0a03cSPaolo Bonzini 5569e0a03cSPaolo Bonzini #include "sysemu/hvf.h" 56d57bc3c1SAlexander Graf #include "sysemu/hvf_int.h" 5754d31236SMarkus Armbruster #include "sysemu/runstate.h" 58a1477da3SAlexander Graf #include "sysemu/cpus.h" 5969e0a03cSPaolo Bonzini #include "hvf-i386.h" 6069e0a03cSPaolo Bonzini #include "vmcs.h" 6169e0a03cSPaolo Bonzini #include "vmx.h" 6269e0a03cSPaolo Bonzini #include "x86.h" 6369e0a03cSPaolo Bonzini #include "x86_descr.h" 6469e0a03cSPaolo Bonzini #include "x86_mmu.h" 6569e0a03cSPaolo Bonzini #include "x86_decode.h" 6669e0a03cSPaolo Bonzini #include "x86_emu.h" 6769e0a03cSPaolo Bonzini #include "x86_task.h" 6869e0a03cSPaolo Bonzini #include "x86hvf.h" 6969e0a03cSPaolo Bonzini 7069e0a03cSPaolo Bonzini #include <Hypervisor/hv.h> 7169e0a03cSPaolo Bonzini #include <Hypervisor/hv_vmx.h> 723b502b0eSVladislav Yaroshchuk #include <sys/sysctl.h> 7369e0a03cSPaolo Bonzini 7469e0a03cSPaolo Bonzini #include "hw/i386/apic_internal.h" 7569e0a03cSPaolo Bonzini #include "qemu/main-loop.h" 76940e43aaSClaudio Fontana #include "qemu/accel.h" 7769e0a03cSPaolo Bonzini #include "target/i386/cpu.h" 7869e0a03cSPaolo Bonzini 799c267239SPhil Dennis-Jordan static Error *invtsc_mig_blocker; 809c267239SPhil Dennis-Jordan 8169e0a03cSPaolo Bonzini void vmx_update_tpr(CPUState *cpu) 8269e0a03cSPaolo Bonzini { 8369e0a03cSPaolo Bonzini /* TODO: need integrate APIC handling */ 8469e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 8569e0a03cSPaolo Bonzini int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; 8669e0a03cSPaolo Bonzini int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); 8769e0a03cSPaolo Bonzini 883b295bcbSPhilippe Mathieu-Daudé wreg(cpu->accel->fd, HV_X86_TPR, tpr); 8969e0a03cSPaolo Bonzini if (irr == -1) { 903b295bcbSPhilippe Mathieu-Daudé wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); 9169e0a03cSPaolo Bonzini } else { 923b295bcbSPhilippe Mathieu-Daudé wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : 9369e0a03cSPaolo Bonzini irr >> 4); 9469e0a03cSPaolo Bonzini } 9569e0a03cSPaolo Bonzini } 9669e0a03cSPaolo Bonzini 97583ae161SRoman Bolshakov static void update_apic_tpr(CPUState *cpu) 9869e0a03cSPaolo Bonzini { 9969e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 1003b295bcbSPhilippe Mathieu-Daudé int tpr = rreg(cpu->accel->fd, HV_X86_TPR) >> 4; 10169e0a03cSPaolo Bonzini cpu_set_apic_tpr(x86_cpu->apic_state, tpr); 10269e0a03cSPaolo Bonzini } 10369e0a03cSPaolo Bonzini 10469e0a03cSPaolo Bonzini #define VECTORING_INFO_VECTOR_MASK 0xff 10569e0a03cSPaolo Bonzini 10669e0a03cSPaolo Bonzini void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer, 10769e0a03cSPaolo Bonzini int direction, int size, int count) 10869e0a03cSPaolo Bonzini { 10969e0a03cSPaolo Bonzini int i; 11069e0a03cSPaolo Bonzini uint8_t *ptr = buffer; 11169e0a03cSPaolo Bonzini 11269e0a03cSPaolo Bonzini for (i = 0; i < count; i++) { 11369e0a03cSPaolo Bonzini address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED, 11469e0a03cSPaolo Bonzini ptr, size, 11569e0a03cSPaolo Bonzini direction); 11669e0a03cSPaolo Bonzini ptr += size; 11769e0a03cSPaolo Bonzini } 11869e0a03cSPaolo Bonzini } 11969e0a03cSPaolo Bonzini 120ff2de166SPaolo Bonzini static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept_qual) 12169e0a03cSPaolo Bonzini { 12269e0a03cSPaolo Bonzini int read, write; 12369e0a03cSPaolo Bonzini 12469e0a03cSPaolo Bonzini /* EPT fault on an instruction fetch doesn't make sense here */ 12569e0a03cSPaolo Bonzini if (ept_qual & EPT_VIOLATION_INST_FETCH) { 12669e0a03cSPaolo Bonzini return false; 12769e0a03cSPaolo Bonzini } 12869e0a03cSPaolo Bonzini 12969e0a03cSPaolo Bonzini /* EPT fault must be a read fault or a write fault */ 13069e0a03cSPaolo Bonzini read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0; 13169e0a03cSPaolo Bonzini write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0; 13269e0a03cSPaolo Bonzini if ((read | write) == 0) { 13369e0a03cSPaolo Bonzini return false; 13469e0a03cSPaolo Bonzini } 13569e0a03cSPaolo Bonzini 13669e0a03cSPaolo Bonzini if (write && slot) { 13769e0a03cSPaolo Bonzini if (slot->flags & HVF_SLOT_LOG) { 138*3e2c6727SPhil Dennis-Jordan uint64_t dirty_page_start = gpa & ~(TARGET_PAGE_SIZE - 1u); 13969e0a03cSPaolo Bonzini memory_region_set_dirty(slot->region, gpa - slot->start, 1); 140*3e2c6727SPhil Dennis-Jordan hv_vm_protect(dirty_page_start, TARGET_PAGE_SIZE, 141*3e2c6727SPhil Dennis-Jordan HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC); 14269e0a03cSPaolo Bonzini } 14369e0a03cSPaolo Bonzini } 14469e0a03cSPaolo Bonzini 14569e0a03cSPaolo Bonzini /* 14669e0a03cSPaolo Bonzini * The EPT violation must have been caused by accessing a 14769e0a03cSPaolo Bonzini * guest-physical address that is a translation of a guest-linear 14869e0a03cSPaolo Bonzini * address. 14969e0a03cSPaolo Bonzini */ 15069e0a03cSPaolo Bonzini if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 || 15169e0a03cSPaolo Bonzini (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) { 15269e0a03cSPaolo Bonzini return false; 15369e0a03cSPaolo Bonzini } 15469e0a03cSPaolo Bonzini 155fbafbb6dSCameron Esfahani if (!slot) { 156fbafbb6dSCameron Esfahani return true; 157fbafbb6dSCameron Esfahani } 158fbafbb6dSCameron Esfahani if (!memory_region_is_ram(slot->region) && 159fbafbb6dSCameron Esfahani !(read && memory_region_is_romd(slot->region))) { 160fbafbb6dSCameron Esfahani return true; 161fbafbb6dSCameron Esfahani } 162fbafbb6dSCameron Esfahani return false; 16369e0a03cSPaolo Bonzini } 16469e0a03cSPaolo Bonzini 165cfe58455SAlexander Graf void hvf_arch_vcpu_destroy(CPUState *cpu) 16669e0a03cSPaolo Bonzini { 167fe76b09cSRoman Bolshakov X86CPU *x86_cpu = X86_CPU(cpu); 168fe76b09cSRoman Bolshakov CPUX86State *env = &x86_cpu->env; 169fe76b09cSRoman Bolshakov 170fe76b09cSRoman Bolshakov g_free(env->hvf_mmio_buf); 17169e0a03cSPaolo Bonzini } 17269e0a03cSPaolo Bonzini 1733b502b0eSVladislav Yaroshchuk static void init_tsc_freq(CPUX86State *env) 1743b502b0eSVladislav Yaroshchuk { 1753b502b0eSVladislav Yaroshchuk size_t length; 1763b502b0eSVladislav Yaroshchuk uint64_t tsc_freq; 1773b502b0eSVladislav Yaroshchuk 1783b502b0eSVladislav Yaroshchuk if (env->tsc_khz != 0) { 1793b502b0eSVladislav Yaroshchuk return; 1803b502b0eSVladislav Yaroshchuk } 1813b502b0eSVladislav Yaroshchuk 1823b502b0eSVladislav Yaroshchuk length = sizeof(uint64_t); 1833b502b0eSVladislav Yaroshchuk if (sysctlbyname("machdep.tsc.frequency", &tsc_freq, &length, NULL, 0)) { 1843b502b0eSVladislav Yaroshchuk return; 1853b502b0eSVladislav Yaroshchuk } 1863b502b0eSVladislav Yaroshchuk env->tsc_khz = tsc_freq / 1000; /* Hz to KHz */ 1873b502b0eSVladislav Yaroshchuk } 1883b502b0eSVladislav Yaroshchuk 1893b502b0eSVladislav Yaroshchuk static void init_apic_bus_freq(CPUX86State *env) 1903b502b0eSVladislav Yaroshchuk { 1913b502b0eSVladislav Yaroshchuk size_t length; 1923b502b0eSVladislav Yaroshchuk uint64_t bus_freq; 1933b502b0eSVladislav Yaroshchuk 1943b502b0eSVladislav Yaroshchuk if (env->apic_bus_freq != 0) { 1953b502b0eSVladislav Yaroshchuk return; 1963b502b0eSVladislav Yaroshchuk } 1973b502b0eSVladislav Yaroshchuk 1983b502b0eSVladislav Yaroshchuk length = sizeof(uint64_t); 1993b502b0eSVladislav Yaroshchuk if (sysctlbyname("hw.busfrequency", &bus_freq, &length, NULL, 0)) { 2003b502b0eSVladislav Yaroshchuk return; 2013b502b0eSVladislav Yaroshchuk } 2023b502b0eSVladislav Yaroshchuk env->apic_bus_freq = bus_freq; 2033b502b0eSVladislav Yaroshchuk } 2043b502b0eSVladislav Yaroshchuk 2053b502b0eSVladislav Yaroshchuk static inline bool tsc_is_known(CPUX86State *env) 2063b502b0eSVladislav Yaroshchuk { 2073b502b0eSVladislav Yaroshchuk return env->tsc_khz != 0; 2083b502b0eSVladislav Yaroshchuk } 2093b502b0eSVladislav Yaroshchuk 2103b502b0eSVladislav Yaroshchuk static inline bool apic_bus_freq_is_known(CPUX86State *env) 2113b502b0eSVladislav Yaroshchuk { 2123b502b0eSVladislav Yaroshchuk return env->apic_bus_freq != 0; 2133b502b0eSVladislav Yaroshchuk } 2143b502b0eSVladislav Yaroshchuk 215a1477da3SAlexander Graf void hvf_kick_vcpu_thread(CPUState *cpu) 216a1477da3SAlexander Graf { 217a1477da3SAlexander Graf cpus_kick_thread(cpu); 218a1477da3SAlexander Graf } 219a1477da3SAlexander Graf 220ce7f5b1cSAlexander Graf int hvf_arch_init(void) 221ce7f5b1cSAlexander Graf { 222ce7f5b1cSAlexander Graf return 0; 223ce7f5b1cSAlexander Graf } 224ce7f5b1cSAlexander Graf 225cfe58455SAlexander Graf int hvf_arch_init_vcpu(CPUState *cpu) 22669e0a03cSPaolo Bonzini { 22769e0a03cSPaolo Bonzini X86CPU *x86cpu = X86_CPU(cpu); 22869e0a03cSPaolo Bonzini CPUX86State *env = &x86cpu->env; 2299c267239SPhil Dennis-Jordan Error *local_err = NULL; 2309c267239SPhil Dennis-Jordan int r; 231d8cf2c29SCameron Esfahani uint64_t reqCap; 23269e0a03cSPaolo Bonzini 23369e0a03cSPaolo Bonzini init_emu(); 23469e0a03cSPaolo Bonzini init_decoder(); 23569e0a03cSPaolo Bonzini 23669e0a03cSPaolo Bonzini hvf_state->hvf_caps = g_new0(struct hvf_vcpu_caps, 1); 237fe76b09cSRoman Bolshakov env->hvf_mmio_buf = g_new(char, 4096); 23869e0a03cSPaolo Bonzini 2393b502b0eSVladislav Yaroshchuk if (x86cpu->vmware_cpuid_freq) { 2403b502b0eSVladislav Yaroshchuk init_tsc_freq(env); 2413b502b0eSVladislav Yaroshchuk init_apic_bus_freq(env); 2423b502b0eSVladislav Yaroshchuk 2433b502b0eSVladislav Yaroshchuk if (!tsc_is_known(env) || !apic_bus_freq_is_known(env)) { 2443b502b0eSVladislav Yaroshchuk error_report("vmware-cpuid-freq: feature couldn't be enabled"); 2453b502b0eSVladislav Yaroshchuk } 2463b502b0eSVladislav Yaroshchuk } 2473b502b0eSVladislav Yaroshchuk 2489c267239SPhil Dennis-Jordan if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && 2499c267239SPhil Dennis-Jordan invtsc_mig_blocker == NULL) { 2509c267239SPhil Dennis-Jordan error_setg(&invtsc_mig_blocker, 2519c267239SPhil Dennis-Jordan "State blocked by non-migratable CPU device (invtsc flag)"); 2529c267239SPhil Dennis-Jordan r = migrate_add_blocker(&invtsc_mig_blocker, &local_err); 2539c267239SPhil Dennis-Jordan if (r < 0) { 2549c267239SPhil Dennis-Jordan error_report_err(local_err); 2559c267239SPhil Dennis-Jordan return r; 2569c267239SPhil Dennis-Jordan } 2579c267239SPhil Dennis-Jordan } 2589c267239SPhil Dennis-Jordan 2599c267239SPhil Dennis-Jordan 26069e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, 26169e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_pinbased)) { 26269e0a03cSPaolo Bonzini abort(); 26369e0a03cSPaolo Bonzini } 26469e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, 26569e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_procbased)) { 26669e0a03cSPaolo Bonzini abort(); 26769e0a03cSPaolo Bonzini } 26869e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, 26969e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_procbased2)) { 27069e0a03cSPaolo Bonzini abort(); 27169e0a03cSPaolo Bonzini } 27269e0a03cSPaolo Bonzini if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, 27369e0a03cSPaolo Bonzini &hvf_state->hvf_caps->vmx_cap_entry)) { 27469e0a03cSPaolo Bonzini abort(); 27569e0a03cSPaolo Bonzini } 27669e0a03cSPaolo Bonzini 27769e0a03cSPaolo Bonzini /* set VMCS control fields */ 2783b295bcbSPhilippe Mathieu-Daudé wvmcs(cpu->accel->fd, VMCS_PIN_BASED_CTLS, 27969e0a03cSPaolo Bonzini cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, 28069e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_EXTINT | 28169e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_NMI | 28269e0a03cSPaolo Bonzini VMCS_PIN_BASED_CTLS_VNMI)); 2833b295bcbSPhilippe Mathieu-Daudé wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, 28469e0a03cSPaolo Bonzini cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, 28569e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_HLT | 28669e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_MWAIT | 28769e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET | 28869e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) | 28969e0a03cSPaolo Bonzini VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL); 290d8cf2c29SCameron Esfahani 291d8cf2c29SCameron Esfahani reqCap = VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES; 292d8cf2c29SCameron Esfahani 293d8cf2c29SCameron Esfahani /* Is RDTSCP support in CPUID? If so, enable it in the VMCS. */ 294d8cf2c29SCameron Esfahani if (hvf_get_supported_cpuid(0x80000001, 0, R_EDX) & CPUID_EXT2_RDTSCP) { 295d8cf2c29SCameron Esfahani reqCap |= VMCS_PRI_PROC_BASED2_CTLS_RDTSCP; 296d8cf2c29SCameron Esfahani } 297d8cf2c29SCameron Esfahani 2983b295bcbSPhilippe Mathieu-Daudé wvmcs(cpu->accel->fd, VMCS_SEC_PROC_BASED_CTLS, 299d8cf2c29SCameron Esfahani cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap)); 30069e0a03cSPaolo Bonzini 3013b295bcbSPhilippe Mathieu-Daudé wvmcs(cpu->accel->fd, VMCS_ENTRY_CTLS, 3023b295bcbSPhilippe Mathieu-Daudé cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, 0)); 3033b295bcbSPhilippe Mathieu-Daudé wvmcs(cpu->accel->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ 30469e0a03cSPaolo Bonzini 3053b295bcbSPhilippe Mathieu-Daudé wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); 30669e0a03cSPaolo Bonzini 30769e0a03cSPaolo Bonzini x86cpu = X86_CPU(cpu); 308c0198c5fSDavid Edmondson x86cpu->env.xsave_buf_len = 4096; 309c0198c5fSDavid Edmondson x86cpu->env.xsave_buf = qemu_memalign(4096, x86cpu->env.xsave_buf_len); 31069e0a03cSPaolo Bonzini 311fea45008SDavid Edmondson /* 312fea45008SDavid Edmondson * The allocated storage must be large enough for all of the 313fea45008SDavid Edmondson * possible XSAVE state components. 314fea45008SDavid Edmondson */ 315fea45008SDavid Edmondson assert(hvf_get_supported_cpuid(0xd, 0, R_ECX) <= x86cpu->env.xsave_buf_len); 316fea45008SDavid Edmondson 3173b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_STAR, 1); 3183b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_LSTAR, 1); 3193b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_CSTAR, 1); 3203b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FMASK, 1); 3213b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FSBASE, 1); 3223b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_GSBASE, 1); 3233b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_KERNELGSBASE, 1); 3243b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_TSC_AUX, 1); 3253b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_TSC, 1); 3263b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_CS, 1); 3273b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_EIP, 1); 3283b295bcbSPhilippe Mathieu-Daudé hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_ESP, 1); 32969e0a03cSPaolo Bonzini 33069e0a03cSPaolo Bonzini return 0; 33169e0a03cSPaolo Bonzini } 33269e0a03cSPaolo Bonzini 33369e0a03cSPaolo Bonzini static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info) 33469e0a03cSPaolo Bonzini { 33569e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 33669e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 33769e0a03cSPaolo Bonzini 338fd13f23bSLiran Alon env->exception_nr = -1; 339fd13f23bSLiran Alon env->exception_pending = 0; 340fd13f23bSLiran Alon env->exception_injected = 0; 34169e0a03cSPaolo Bonzini env->interrupt_injected = -1; 34269e0a03cSPaolo Bonzini env->nmi_injected = false; 34364bef038SCameron Esfahani env->ins_len = 0; 34464bef038SCameron Esfahani env->has_error_code = false; 34569e0a03cSPaolo Bonzini if (idtvec_info & VMCS_IDT_VEC_VALID) { 34669e0a03cSPaolo Bonzini switch (idtvec_info & VMCS_IDT_VEC_TYPE) { 34769e0a03cSPaolo Bonzini case VMCS_IDT_VEC_HWINTR: 34869e0a03cSPaolo Bonzini case VMCS_IDT_VEC_SWINTR: 34969e0a03cSPaolo Bonzini env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM; 35069e0a03cSPaolo Bonzini break; 35169e0a03cSPaolo Bonzini case VMCS_IDT_VEC_NMI: 35269e0a03cSPaolo Bonzini env->nmi_injected = true; 35369e0a03cSPaolo Bonzini break; 35469e0a03cSPaolo Bonzini case VMCS_IDT_VEC_HWEXCEPTION: 35569e0a03cSPaolo Bonzini case VMCS_IDT_VEC_SWEXCEPTION: 356fd13f23bSLiran Alon env->exception_nr = idtvec_info & VMCS_IDT_VEC_VECNUM; 357fd13f23bSLiran Alon env->exception_injected = 1; 35869e0a03cSPaolo Bonzini break; 35969e0a03cSPaolo Bonzini case VMCS_IDT_VEC_PRIV_SWEXCEPTION: 36069e0a03cSPaolo Bonzini default: 36169e0a03cSPaolo Bonzini abort(); 36269e0a03cSPaolo Bonzini } 36369e0a03cSPaolo Bonzini if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION || 36469e0a03cSPaolo Bonzini (idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) { 36569e0a03cSPaolo Bonzini env->ins_len = ins_len; 36669e0a03cSPaolo Bonzini } 36764bef038SCameron Esfahani if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { 36869e0a03cSPaolo Bonzini env->has_error_code = true; 3693b295bcbSPhilippe Mathieu-Daudé env->error_code = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_ERROR); 37069e0a03cSPaolo Bonzini } 37169e0a03cSPaolo Bonzini } 3723b295bcbSPhilippe Mathieu-Daudé if ((rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & 37369e0a03cSPaolo Bonzini VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { 37469e0a03cSPaolo Bonzini env->hflags2 |= HF2_NMI_MASK; 37569e0a03cSPaolo Bonzini } else { 37669e0a03cSPaolo Bonzini env->hflags2 &= ~HF2_NMI_MASK; 37769e0a03cSPaolo Bonzini } 3783b295bcbSPhilippe Mathieu-Daudé if (rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & 37969e0a03cSPaolo Bonzini (VMCS_INTERRUPTIBILITY_STI_BLOCKING | 38069e0a03cSPaolo Bonzini VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { 38169e0a03cSPaolo Bonzini env->hflags |= HF_INHIBIT_IRQ_MASK; 38269e0a03cSPaolo Bonzini } else { 38369e0a03cSPaolo Bonzini env->hflags &= ~HF_INHIBIT_IRQ_MASK; 38469e0a03cSPaolo Bonzini } 38569e0a03cSPaolo Bonzini } 38669e0a03cSPaolo Bonzini 3873b502b0eSVladislav Yaroshchuk static void hvf_cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 3883b502b0eSVladislav Yaroshchuk uint32_t *eax, uint32_t *ebx, 3893b502b0eSVladislav Yaroshchuk uint32_t *ecx, uint32_t *edx) 3903b502b0eSVladislav Yaroshchuk { 3913b502b0eSVladislav Yaroshchuk /* 3923b502b0eSVladislav Yaroshchuk * A wrapper extends cpu_x86_cpuid with 0x40000000 and 0x40000010 leafs, 3933b502b0eSVladislav Yaroshchuk * leafs 0x40000001-0x4000000F are filled with zeros 3943b502b0eSVladislav Yaroshchuk * Provides vmware-cpuid-freq support to hvf 3953b502b0eSVladislav Yaroshchuk * 3963b502b0eSVladislav Yaroshchuk * Note: leaf 0x40000000 not exposes HVF, 3973b502b0eSVladislav Yaroshchuk * leaving hypervisor signature empty 3983b502b0eSVladislav Yaroshchuk */ 3993b502b0eSVladislav Yaroshchuk 4003b502b0eSVladislav Yaroshchuk if (index < 0x40000000 || index > 0x40000010 || 4013b502b0eSVladislav Yaroshchuk !tsc_is_known(env) || !apic_bus_freq_is_known(env)) { 4023b502b0eSVladislav Yaroshchuk 4033b502b0eSVladislav Yaroshchuk cpu_x86_cpuid(env, index, count, eax, ebx, ecx, edx); 4043b502b0eSVladislav Yaroshchuk return; 4053b502b0eSVladislav Yaroshchuk } 4063b502b0eSVladislav Yaroshchuk 4073b502b0eSVladislav Yaroshchuk switch (index) { 4083b502b0eSVladislav Yaroshchuk case 0x40000000: 4093b502b0eSVladislav Yaroshchuk *eax = 0x40000010; /* Max available cpuid leaf */ 4103b502b0eSVladislav Yaroshchuk *ebx = 0; /* Leave signature empty */ 4113b502b0eSVladislav Yaroshchuk *ecx = 0; 4123b502b0eSVladislav Yaroshchuk *edx = 0; 4133b502b0eSVladislav Yaroshchuk break; 4143b502b0eSVladislav Yaroshchuk case 0x40000010: 4153b502b0eSVladislav Yaroshchuk *eax = env->tsc_khz; 4163b502b0eSVladislav Yaroshchuk *ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ 4173b502b0eSVladislav Yaroshchuk *ecx = 0; 4183b502b0eSVladislav Yaroshchuk *edx = 0; 4193b502b0eSVladislav Yaroshchuk break; 4203b502b0eSVladislav Yaroshchuk default: 4213b502b0eSVladislav Yaroshchuk *eax = 0; 4223b502b0eSVladislav Yaroshchuk *ebx = 0; 4233b502b0eSVladislav Yaroshchuk *ecx = 0; 4243b502b0eSVladislav Yaroshchuk *edx = 0; 4253b502b0eSVladislav Yaroshchuk break; 4263b502b0eSVladislav Yaroshchuk } 4273b502b0eSVladislav Yaroshchuk } 4283b502b0eSVladislav Yaroshchuk 42969e0a03cSPaolo Bonzini int hvf_vcpu_exec(CPUState *cpu) 43069e0a03cSPaolo Bonzini { 43169e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 43269e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 43369e0a03cSPaolo Bonzini int ret = 0; 43469e0a03cSPaolo Bonzini uint64_t rip = 0; 43569e0a03cSPaolo Bonzini 43669e0a03cSPaolo Bonzini if (hvf_process_events(cpu)) { 43769e0a03cSPaolo Bonzini return EXCP_HLT; 43869e0a03cSPaolo Bonzini } 43969e0a03cSPaolo Bonzini 44069e0a03cSPaolo Bonzini do { 441e6203636SPhilippe Mathieu-Daudé if (cpu->accel->dirty) { 44269e0a03cSPaolo Bonzini hvf_put_registers(cpu); 443e6203636SPhilippe Mathieu-Daudé cpu->accel->dirty = false; 44469e0a03cSPaolo Bonzini } 44569e0a03cSPaolo Bonzini 44669e0a03cSPaolo Bonzini if (hvf_inject_interrupts(cpu)) { 44769e0a03cSPaolo Bonzini return EXCP_INTERRUPT; 44869e0a03cSPaolo Bonzini } 44969e0a03cSPaolo Bonzini vmx_update_tpr(cpu); 45069e0a03cSPaolo Bonzini 451195801d7SStefan Hajnoczi bql_unlock(); 45269e0a03cSPaolo Bonzini if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) { 453195801d7SStefan Hajnoczi bql_lock(); 45469e0a03cSPaolo Bonzini return EXCP_HLT; 45569e0a03cSPaolo Bonzini } 45669e0a03cSPaolo Bonzini 4573b295bcbSPhilippe Mathieu-Daudé hv_return_t r = hv_vcpu_run(cpu->accel->fd); 45869e0a03cSPaolo Bonzini assert_hvf_ok(r); 45969e0a03cSPaolo Bonzini 46069e0a03cSPaolo Bonzini /* handle VMEXIT */ 4613b295bcbSPhilippe Mathieu-Daudé uint64_t exit_reason = rvmcs(cpu->accel->fd, VMCS_EXIT_REASON); 4623b295bcbSPhilippe Mathieu-Daudé uint64_t exit_qual = rvmcs(cpu->accel->fd, VMCS_EXIT_QUALIFICATION); 4633b295bcbSPhilippe Mathieu-Daudé uint32_t ins_len = (uint32_t)rvmcs(cpu->accel->fd, 46469e0a03cSPaolo Bonzini VMCS_EXIT_INSTRUCTION_LENGTH); 46569e0a03cSPaolo Bonzini 4663b295bcbSPhilippe Mathieu-Daudé uint64_t idtvec_info = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO); 46769e0a03cSPaolo Bonzini 46869e0a03cSPaolo Bonzini hvf_store_events(cpu, ins_len, idtvec_info); 4693b295bcbSPhilippe Mathieu-Daudé rip = rreg(cpu->accel->fd, HV_X86_RIP); 4703b295bcbSPhilippe Mathieu-Daudé env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS); 47169e0a03cSPaolo Bonzini 472195801d7SStefan Hajnoczi bql_lock(); 47369e0a03cSPaolo Bonzini 47469e0a03cSPaolo Bonzini update_apic_tpr(cpu); 47569e0a03cSPaolo Bonzini current_cpu = cpu; 47669e0a03cSPaolo Bonzini 47769e0a03cSPaolo Bonzini ret = 0; 47869e0a03cSPaolo Bonzini switch (exit_reason) { 47969e0a03cSPaolo Bonzini case EXIT_REASON_HLT: { 48069e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 48169e0a03cSPaolo Bonzini if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && 482967f4da2SRoman Bolshakov (env->eflags & IF_MASK)) 48369e0a03cSPaolo Bonzini && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) && 48469e0a03cSPaolo Bonzini !(idtvec_info & VMCS_IDT_VEC_VALID)) { 48569e0a03cSPaolo Bonzini cpu->halted = 1; 48669e0a03cSPaolo Bonzini ret = EXCP_HLT; 4873b9c59daSChen Zhang break; 48869e0a03cSPaolo Bonzini } 48969e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 49069e0a03cSPaolo Bonzini break; 49169e0a03cSPaolo Bonzini } 49269e0a03cSPaolo Bonzini case EXIT_REASON_MWAIT: { 49369e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 49469e0a03cSPaolo Bonzini break; 49569e0a03cSPaolo Bonzini } 496fbafbb6dSCameron Esfahani /* Need to check if MMIO or unmapped fault */ 49769e0a03cSPaolo Bonzini case EXIT_REASON_EPT_FAULT: 49869e0a03cSPaolo Bonzini { 49969e0a03cSPaolo Bonzini hvf_slot *slot; 5003b295bcbSPhilippe Mathieu-Daudé uint64_t gpa = rvmcs(cpu->accel->fd, VMCS_GUEST_PHYSICAL_ADDRESS); 50169e0a03cSPaolo Bonzini 50269e0a03cSPaolo Bonzini if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) && 50369e0a03cSPaolo Bonzini ((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) { 50469e0a03cSPaolo Bonzini vmx_set_nmi_blocking(cpu); 50569e0a03cSPaolo Bonzini } 50669e0a03cSPaolo Bonzini 507fbafbb6dSCameron Esfahani slot = hvf_find_overlap_slot(gpa, 1); 50869e0a03cSPaolo Bonzini /* mmio */ 50969e0a03cSPaolo Bonzini if (ept_emulation_fault(slot, gpa, exit_qual)) { 51069e0a03cSPaolo Bonzini struct x86_decode decode; 51169e0a03cSPaolo Bonzini 51269e0a03cSPaolo Bonzini load_regs(cpu); 51369e0a03cSPaolo Bonzini decode_instruction(env, &decode); 51469e0a03cSPaolo Bonzini exec_instruction(env, &decode); 51569e0a03cSPaolo Bonzini store_regs(cpu); 51669e0a03cSPaolo Bonzini break; 51769e0a03cSPaolo Bonzini } 51869e0a03cSPaolo Bonzini break; 51969e0a03cSPaolo Bonzini } 52069e0a03cSPaolo Bonzini case EXIT_REASON_INOUT: 52169e0a03cSPaolo Bonzini { 52269e0a03cSPaolo Bonzini uint32_t in = (exit_qual & 8) != 0; 52369e0a03cSPaolo Bonzini uint32_t size = (exit_qual & 7) + 1; 52469e0a03cSPaolo Bonzini uint32_t string = (exit_qual & 16) != 0; 52569e0a03cSPaolo Bonzini uint32_t port = exit_qual >> 16; 52669e0a03cSPaolo Bonzini /*uint32_t rep = (exit_qual & 0x20) != 0;*/ 52769e0a03cSPaolo Bonzini 52869e0a03cSPaolo Bonzini if (!string && in) { 52969e0a03cSPaolo Bonzini uint64_t val = 0; 53069e0a03cSPaolo Bonzini load_regs(cpu); 53169e0a03cSPaolo Bonzini hvf_handle_io(env, port, &val, 0, size, 1); 53269e0a03cSPaolo Bonzini if (size == 1) { 53369e0a03cSPaolo Bonzini AL(env) = val; 53469e0a03cSPaolo Bonzini } else if (size == 2) { 53569e0a03cSPaolo Bonzini AX(env) = val; 53669e0a03cSPaolo Bonzini } else if (size == 4) { 53769e0a03cSPaolo Bonzini RAX(env) = (uint32_t)val; 53869e0a03cSPaolo Bonzini } else { 539da20f5cdSPaolo Bonzini RAX(env) = (uint64_t)val; 54069e0a03cSPaolo Bonzini } 5415d32173fSRoman Bolshakov env->eip += ins_len; 54269e0a03cSPaolo Bonzini store_regs(cpu); 54369e0a03cSPaolo Bonzini break; 54469e0a03cSPaolo Bonzini } else if (!string && !in) { 5453b295bcbSPhilippe Mathieu-Daudé RAX(env) = rreg(cpu->accel->fd, HV_X86_RAX); 54669e0a03cSPaolo Bonzini hvf_handle_io(env, port, &RAX(env), 1, size, 1); 54769e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 54869e0a03cSPaolo Bonzini break; 54969e0a03cSPaolo Bonzini } 55069e0a03cSPaolo Bonzini struct x86_decode decode; 55169e0a03cSPaolo Bonzini 55269e0a03cSPaolo Bonzini load_regs(cpu); 55369e0a03cSPaolo Bonzini decode_instruction(env, &decode); 554e62963bfSPaolo Bonzini assert(ins_len == decode.len); 55569e0a03cSPaolo Bonzini exec_instruction(env, &decode); 55669e0a03cSPaolo Bonzini store_regs(cpu); 55769e0a03cSPaolo Bonzini 55869e0a03cSPaolo Bonzini break; 55969e0a03cSPaolo Bonzini } 56069e0a03cSPaolo Bonzini case EXIT_REASON_CPUID: { 5613b295bcbSPhilippe Mathieu-Daudé uint32_t rax = (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); 5623b295bcbSPhilippe Mathieu-Daudé uint32_t rbx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RBX); 5633b295bcbSPhilippe Mathieu-Daudé uint32_t rcx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); 5643b295bcbSPhilippe Mathieu-Daudé uint32_t rdx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); 56569e0a03cSPaolo Bonzini 566106f91d5SAlexander Graf if (rax == 1) { 567106f91d5SAlexander Graf /* CPUID1.ecx.OSXSAVE needs to know CR4 */ 5683b295bcbSPhilippe Mathieu-Daudé env->cr[4] = rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); 569106f91d5SAlexander Graf } 5703b502b0eSVladislav Yaroshchuk hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); 57169e0a03cSPaolo Bonzini 5723b295bcbSPhilippe Mathieu-Daudé wreg(cpu->accel->fd, HV_X86_RAX, rax); 5733b295bcbSPhilippe Mathieu-Daudé wreg(cpu->accel->fd, HV_X86_RBX, rbx); 5743b295bcbSPhilippe Mathieu-Daudé wreg(cpu->accel->fd, HV_X86_RCX, rcx); 5753b295bcbSPhilippe Mathieu-Daudé wreg(cpu->accel->fd, HV_X86_RDX, rdx); 57669e0a03cSPaolo Bonzini 57769e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 57869e0a03cSPaolo Bonzini break; 57969e0a03cSPaolo Bonzini } 58069e0a03cSPaolo Bonzini case EXIT_REASON_XSETBV: { 58169e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 58269e0a03cSPaolo Bonzini CPUX86State *env = &x86_cpu->env; 5833b295bcbSPhilippe Mathieu-Daudé uint32_t eax = (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); 5843b295bcbSPhilippe Mathieu-Daudé uint32_t ecx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); 5853b295bcbSPhilippe Mathieu-Daudé uint32_t edx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); 58669e0a03cSPaolo Bonzini 58769e0a03cSPaolo Bonzini if (ecx) { 58869e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 58969e0a03cSPaolo Bonzini break; 59069e0a03cSPaolo Bonzini } 59169e0a03cSPaolo Bonzini env->xcr0 = ((uint64_t)edx << 32) | eax; 5923b295bcbSPhilippe Mathieu-Daudé wreg(cpu->accel->fd, HV_X86_XCR0, env->xcr0 | 1); 59369e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 59469e0a03cSPaolo Bonzini break; 59569e0a03cSPaolo Bonzini } 59669e0a03cSPaolo Bonzini case EXIT_REASON_INTR_WINDOW: 59769e0a03cSPaolo Bonzini vmx_clear_int_window_exiting(cpu); 59869e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 59969e0a03cSPaolo Bonzini break; 60069e0a03cSPaolo Bonzini case EXIT_REASON_NMI_WINDOW: 60169e0a03cSPaolo Bonzini vmx_clear_nmi_window_exiting(cpu); 60269e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 60369e0a03cSPaolo Bonzini break; 60469e0a03cSPaolo Bonzini case EXIT_REASON_EXT_INTR: 60569e0a03cSPaolo Bonzini /* force exit and allow io handling */ 60669e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 60769e0a03cSPaolo Bonzini break; 60869e0a03cSPaolo Bonzini case EXIT_REASON_RDMSR: 60969e0a03cSPaolo Bonzini case EXIT_REASON_WRMSR: 61069e0a03cSPaolo Bonzini { 61169e0a03cSPaolo Bonzini load_regs(cpu); 61269e0a03cSPaolo Bonzini if (exit_reason == EXIT_REASON_RDMSR) { 613a9e445dfSPhilippe Mathieu-Daudé simulate_rdmsr(env); 61469e0a03cSPaolo Bonzini } else { 615a9e445dfSPhilippe Mathieu-Daudé simulate_wrmsr(env); 61669e0a03cSPaolo Bonzini } 6175d32173fSRoman Bolshakov env->eip += ins_len; 61869e0a03cSPaolo Bonzini store_regs(cpu); 61969e0a03cSPaolo Bonzini break; 62069e0a03cSPaolo Bonzini } 62169e0a03cSPaolo Bonzini case EXIT_REASON_CR_ACCESS: { 62269e0a03cSPaolo Bonzini int cr; 62369e0a03cSPaolo Bonzini int reg; 62469e0a03cSPaolo Bonzini 62569e0a03cSPaolo Bonzini load_regs(cpu); 62669e0a03cSPaolo Bonzini cr = exit_qual & 15; 62769e0a03cSPaolo Bonzini reg = (exit_qual >> 8) & 15; 62869e0a03cSPaolo Bonzini 62969e0a03cSPaolo Bonzini switch (cr) { 63069e0a03cSPaolo Bonzini case 0x0: { 6313b295bcbSPhilippe Mathieu-Daudé macvm_set_cr0(cpu->accel->fd, RRX(env, reg)); 63269e0a03cSPaolo Bonzini break; 63369e0a03cSPaolo Bonzini } 63469e0a03cSPaolo Bonzini case 4: { 6353b295bcbSPhilippe Mathieu-Daudé macvm_set_cr4(cpu->accel->fd, RRX(env, reg)); 63669e0a03cSPaolo Bonzini break; 63769e0a03cSPaolo Bonzini } 63869e0a03cSPaolo Bonzini case 8: { 63969e0a03cSPaolo Bonzini X86CPU *x86_cpu = X86_CPU(cpu); 64069e0a03cSPaolo Bonzini if (exit_qual & 0x10) { 64169e0a03cSPaolo Bonzini RRX(env, reg) = cpu_get_apic_tpr(x86_cpu->apic_state); 64269e0a03cSPaolo Bonzini } else { 64369e0a03cSPaolo Bonzini int tpr = RRX(env, reg); 64469e0a03cSPaolo Bonzini cpu_set_apic_tpr(x86_cpu->apic_state, tpr); 64569e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 64669e0a03cSPaolo Bonzini } 64769e0a03cSPaolo Bonzini break; 64869e0a03cSPaolo Bonzini } 64969e0a03cSPaolo Bonzini default: 6502d9178d9SLaurent Vivier error_report("Unrecognized CR %d", cr); 65169e0a03cSPaolo Bonzini abort(); 65269e0a03cSPaolo Bonzini } 6535d32173fSRoman Bolshakov env->eip += ins_len; 65469e0a03cSPaolo Bonzini store_regs(cpu); 65569e0a03cSPaolo Bonzini break; 65669e0a03cSPaolo Bonzini } 65769e0a03cSPaolo Bonzini case EXIT_REASON_APIC_ACCESS: { /* TODO */ 65869e0a03cSPaolo Bonzini struct x86_decode decode; 65969e0a03cSPaolo Bonzini 66069e0a03cSPaolo Bonzini load_regs(cpu); 66169e0a03cSPaolo Bonzini decode_instruction(env, &decode); 66269e0a03cSPaolo Bonzini exec_instruction(env, &decode); 66369e0a03cSPaolo Bonzini store_regs(cpu); 66469e0a03cSPaolo Bonzini break; 66569e0a03cSPaolo Bonzini } 66669e0a03cSPaolo Bonzini case EXIT_REASON_TPR: { 66769e0a03cSPaolo Bonzini ret = 1; 66869e0a03cSPaolo Bonzini break; 66969e0a03cSPaolo Bonzini } 67069e0a03cSPaolo Bonzini case EXIT_REASON_TASK_SWITCH: { 6713b295bcbSPhilippe Mathieu-Daudé uint64_t vinfo = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO); 67269e0a03cSPaolo Bonzini x68_segment_selector sel = {.sel = exit_qual & 0xffff}; 67369e0a03cSPaolo Bonzini vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, 67469e0a03cSPaolo Bonzini vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo 67569e0a03cSPaolo Bonzini & VMCS_INTR_T_MASK); 67669e0a03cSPaolo Bonzini break; 67769e0a03cSPaolo Bonzini } 67869e0a03cSPaolo Bonzini case EXIT_REASON_TRIPLE_FAULT: { 67969e0a03cSPaolo Bonzini qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 68069e0a03cSPaolo Bonzini ret = EXCP_INTERRUPT; 68169e0a03cSPaolo Bonzini break; 68269e0a03cSPaolo Bonzini } 68369e0a03cSPaolo Bonzini case EXIT_REASON_RDPMC: 6843b295bcbSPhilippe Mathieu-Daudé wreg(cpu->accel->fd, HV_X86_RAX, 0); 6853b295bcbSPhilippe Mathieu-Daudé wreg(cpu->accel->fd, HV_X86_RDX, 0); 68669e0a03cSPaolo Bonzini macvm_set_rip(cpu, rip + ins_len); 68769e0a03cSPaolo Bonzini break; 68869e0a03cSPaolo Bonzini case VMX_REASON_VMCALL: 689fd13f23bSLiran Alon env->exception_nr = EXCP0D_GPF; 690fd13f23bSLiran Alon env->exception_injected = 1; 69169e0a03cSPaolo Bonzini env->has_error_code = true; 69269e0a03cSPaolo Bonzini env->error_code = 0; 69369e0a03cSPaolo Bonzini break; 69469e0a03cSPaolo Bonzini default: 6952d9178d9SLaurent Vivier error_report("%llx: unhandled exit %llx", rip, exit_reason); 69669e0a03cSPaolo Bonzini } 69769e0a03cSPaolo Bonzini } while (ret == 0); 69869e0a03cSPaolo Bonzini 69969e0a03cSPaolo Bonzini return ret; 70069e0a03cSPaolo Bonzini } 701f4152040SFrancesco Cagnin 702f4152040SFrancesco Cagnin int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 703f4152040SFrancesco Cagnin { 704f4152040SFrancesco Cagnin return -ENOSYS; 705f4152040SFrancesco Cagnin } 706f4152040SFrancesco Cagnin 707f4152040SFrancesco Cagnin int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 708f4152040SFrancesco Cagnin { 709f4152040SFrancesco Cagnin return -ENOSYS; 710f4152040SFrancesco Cagnin } 711f4152040SFrancesco Cagnin 712d447a624SAnton Johansson int hvf_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 713f4152040SFrancesco Cagnin { 714f4152040SFrancesco Cagnin return -ENOSYS; 715f4152040SFrancesco Cagnin } 716f4152040SFrancesco Cagnin 717d447a624SAnton Johansson int hvf_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 718f4152040SFrancesco Cagnin { 719f4152040SFrancesco Cagnin return -ENOSYS; 720f4152040SFrancesco Cagnin } 721f4152040SFrancesco Cagnin 722f4152040SFrancesco Cagnin void hvf_arch_remove_all_hw_breakpoints(void) 723f4152040SFrancesco Cagnin { 724f4152040SFrancesco Cagnin } 725eb2edc42SFrancesco Cagnin 726eb2edc42SFrancesco Cagnin void hvf_arch_update_guest_debug(CPUState *cpu) 727eb2edc42SFrancesco Cagnin { 728eb2edc42SFrancesco Cagnin } 729eb2edc42SFrancesco Cagnin 730d6fd5d83SPhilippe Mathieu-Daudé bool hvf_arch_supports_guest_debug(void) 731eb2edc42SFrancesco Cagnin { 732eb2edc42SFrancesco Cagnin return false; 733eb2edc42SFrancesco Cagnin } 734