1 /* 2 * x86 host CPU functions, and "host" cpu type initialization 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "cpu.h" 12 #include "host-cpu.h" 13 #include "qapi/error.h" 14 #include "sysemu/sysemu.h" 15 16 /* Note: Only safe for use on x86(-64) hosts */ 17 static uint32_t host_cpu_phys_bits(void) 18 { 19 uint32_t eax; 20 uint32_t host_phys_bits; 21 22 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); 23 if (eax >= 0x80000008) { 24 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); 25 /* 26 * Note: According to AMD doc 25481 rev 2.34 they have a field 27 * at 23:16 that can specify a maximum physical address bits for 28 * the guest that can override this value; but I've not seen 29 * anything with that set. 30 */ 31 host_phys_bits = eax & 0xff; 32 } else { 33 /* 34 * It's an odd 64 bit machine that doesn't have the leaf for 35 * physical address bits; fall back to 36 that's most older 36 * Intel. 37 */ 38 host_phys_bits = 36; 39 } 40 41 return host_phys_bits; 42 } 43 44 static void host_cpu_enable_cpu_pm(X86CPU *cpu) 45 { 46 CPUX86State *env = &cpu->env; 47 48 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, 49 &cpu->mwait.ecx, &cpu->mwait.edx); 50 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; 51 } 52 53 static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu) 54 { 55 uint32_t host_phys_bits = host_cpu_phys_bits(); 56 uint32_t phys_bits = cpu->phys_bits; 57 static bool warned; 58 59 /* 60 * Print a warning if the user set it to a value that's not the 61 * host value. 62 */ 63 if (phys_bits != host_phys_bits && phys_bits != 0 && 64 !warned) { 65 warn_report("Host physical bits (%u)" 66 " does not match phys-bits property (%u)", 67 host_phys_bits, phys_bits); 68 warned = true; 69 } 70 71 if (cpu->host_phys_bits) { 72 /* The user asked for us to use the host physical bits */ 73 phys_bits = host_phys_bits; 74 if (cpu->host_phys_bits_limit && 75 phys_bits > cpu->host_phys_bits_limit) { 76 phys_bits = cpu->host_phys_bits_limit; 77 } 78 } 79 80 return phys_bits; 81 } 82 83 bool host_cpu_realizefn(CPUState *cs, Error **errp) 84 { 85 X86CPU *cpu = X86_CPU(cs); 86 CPUX86State *env = &cpu->env; 87 88 if (cpu->max_features && enable_cpu_pm) { 89 host_cpu_enable_cpu_pm(cpu); 90 } 91 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 92 uint32_t phys_bits = host_cpu_adjust_phys_bits(cpu); 93 94 if (phys_bits && 95 (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 96 phys_bits < 32)) { 97 error_setg(errp, "phys-bits should be between 32 and %u " 98 " (but is %u)", 99 TARGET_PHYS_ADDR_SPACE_BITS, phys_bits); 100 return false; 101 } 102 cpu->phys_bits = phys_bits; 103 } 104 return true; 105 } 106 107 #define CPUID_MODEL_ID_SZ 48 108 /** 109 * cpu_x86_fill_model_id: 110 * Get CPUID model ID string from host CPU. 111 * 112 * @str should have at least CPUID_MODEL_ID_SZ bytes 113 * 114 * The function does NOT add a null terminator to the string 115 * automatically. 116 */ 117 static int host_cpu_fill_model_id(char *str) 118 { 119 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; 120 int i; 121 122 for (i = 0; i < 3; i++) { 123 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); 124 memcpy(str + i * 16 + 0, &eax, 4); 125 memcpy(str + i * 16 + 4, &ebx, 4); 126 memcpy(str + i * 16 + 8, &ecx, 4); 127 memcpy(str + i * 16 + 12, &edx, 4); 128 } 129 return 0; 130 } 131 132 void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping) 133 { 134 uint32_t eax, ebx, ecx, edx; 135 136 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); 137 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 138 139 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); 140 if (family) { 141 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); 142 } 143 if (model) { 144 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); 145 } 146 if (stepping) { 147 *stepping = eax & 0x0F; 148 } 149 } 150 151 void host_cpu_instance_init(X86CPU *cpu) 152 { 153 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 154 155 if (xcc->model) { 156 uint32_t ebx = 0, ecx = 0, edx = 0; 157 char vendor[CPUID_VENDOR_SZ + 1]; 158 159 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); 160 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 161 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 162 } 163 } 164 165 void host_cpu_max_instance_init(X86CPU *cpu) 166 { 167 char vendor[CPUID_VENDOR_SZ + 1] = { 0 }; 168 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 }; 169 int family, model, stepping; 170 171 /* Use max host physical address bits if -cpu max option is applied */ 172 object_property_set_bool(OBJECT(cpu), "host-phys-bits", true, &error_abort); 173 174 host_cpu_vendor_fms(vendor, &family, &model, &stepping); 175 host_cpu_fill_model_id(model_id); 176 177 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 178 object_property_set_int(OBJECT(cpu), "family", family, &error_abort); 179 object_property_set_int(OBJECT(cpu), "model", model, &error_abort); 180 object_property_set_int(OBJECT(cpu), "stepping", stepping, 181 &error_abort); 182 object_property_set_str(OBJECT(cpu), "model-id", model_id, 183 &error_abort); 184 } 185 186 static void host_cpu_class_init(ObjectClass *oc, void *data) 187 { 188 X86CPUClass *xcc = X86_CPU_CLASS(oc); 189 190 xcc->host_cpuid_required = true; 191 xcc->ordering = 8; 192 xcc->model_description = 193 g_strdup_printf("processor with all supported host features "); 194 } 195 196 static const TypeInfo host_cpu_type_info = { 197 .name = X86_CPU_TYPE_NAME("host"), 198 .parent = X86_CPU_TYPE_NAME("max"), 199 .class_init = host_cpu_class_init, 200 }; 201 202 static void host_cpu_type_init(void) 203 { 204 type_register_static(&host_cpu_type_info); 205 } 206 207 type_init(host_cpu_type_init); 208