1 /* 2 * x86 host CPU functions, and "host" cpu type initialization 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "cpu.h" 12 #include "host-cpu.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "sysemu/sysemu.h" 16 17 /* Note: Only safe for use on x86(-64) hosts */ 18 static uint32_t host_cpu_phys_bits(void) 19 { 20 uint32_t eax; 21 uint32_t host_phys_bits; 22 23 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); 24 if (eax >= 0x80000008) { 25 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); 26 /* 27 * Note: According to AMD doc 25481 rev 2.34 they have a field 28 * at 23:16 that can specify a maximum physical address bits for 29 * the guest that can override this value; but I've not seen 30 * anything with that set. 31 */ 32 host_phys_bits = eax & 0xff; 33 } else { 34 /* 35 * It's an odd 64 bit machine that doesn't have the leaf for 36 * physical address bits; fall back to 36 that's most older 37 * Intel. 38 */ 39 host_phys_bits = 36; 40 } 41 42 return host_phys_bits; 43 } 44 45 static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu) 46 { 47 uint32_t host_phys_bits = host_cpu_phys_bits(); 48 uint32_t phys_bits = cpu->phys_bits; 49 50 /* 51 * Print a warning if the user set it to a value that's not the 52 * host value. 53 */ 54 if (phys_bits != host_phys_bits && phys_bits != 0) { 55 warn_report_once("Host physical bits (%u)" 56 " does not match phys-bits property (%u)", 57 host_phys_bits, phys_bits); 58 } 59 60 if (cpu->host_phys_bits) { 61 /* The user asked for us to use the host physical bits */ 62 phys_bits = host_phys_bits; 63 if (cpu->host_phys_bits_limit && 64 phys_bits > cpu->host_phys_bits_limit) { 65 phys_bits = cpu->host_phys_bits_limit; 66 } 67 } 68 69 return phys_bits; 70 } 71 72 bool host_cpu_realizefn(CPUState *cs, Error **errp) 73 { 74 X86CPU *cpu = X86_CPU(cs); 75 CPUX86State *env = &cpu->env; 76 77 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 78 uint32_t phys_bits = host_cpu_adjust_phys_bits(cpu); 79 80 if (phys_bits && 81 (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 82 phys_bits < 32)) { 83 error_setg(errp, "phys-bits should be between 32 and %u " 84 " (but is %u)", 85 TARGET_PHYS_ADDR_SPACE_BITS, phys_bits); 86 return false; 87 } 88 cpu->phys_bits = phys_bits; 89 } 90 return true; 91 } 92 93 #define CPUID_MODEL_ID_SZ 48 94 /** 95 * cpu_x86_fill_model_id: 96 * Get CPUID model ID string from host CPU. 97 * 98 * @str should have at least CPUID_MODEL_ID_SZ bytes 99 * 100 * The function does NOT add a null terminator to the string 101 * automatically. 102 */ 103 static int host_cpu_fill_model_id(char *str) 104 { 105 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; 106 int i; 107 108 for (i = 0; i < 3; i++) { 109 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); 110 memcpy(str + i * 16 + 0, &eax, 4); 111 memcpy(str + i * 16 + 4, &ebx, 4); 112 memcpy(str + i * 16 + 8, &ecx, 4); 113 memcpy(str + i * 16 + 12, &edx, 4); 114 } 115 return 0; 116 } 117 118 void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping) 119 { 120 uint32_t eax, ebx, ecx, edx; 121 122 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); 123 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 124 125 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); 126 if (family) { 127 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); 128 } 129 if (model) { 130 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); 131 } 132 if (stepping) { 133 *stepping = eax & 0x0F; 134 } 135 } 136 137 void host_cpu_instance_init(X86CPU *cpu) 138 { 139 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 140 141 if (xcc->model) { 142 uint32_t ebx = 0, ecx = 0, edx = 0; 143 char vendor[CPUID_VENDOR_SZ + 1]; 144 145 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); 146 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 147 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 148 } 149 } 150 151 void host_cpu_max_instance_init(X86CPU *cpu) 152 { 153 char vendor[CPUID_VENDOR_SZ + 1] = { 0 }; 154 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 }; 155 int family, model, stepping; 156 157 /* Use max host physical address bits if -cpu max option is applied */ 158 object_property_set_bool(OBJECT(cpu), "host-phys-bits", true, &error_abort); 159 160 host_cpu_vendor_fms(vendor, &family, &model, &stepping); 161 host_cpu_fill_model_id(model_id); 162 163 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 164 object_property_set_int(OBJECT(cpu), "family", family, &error_abort); 165 object_property_set_int(OBJECT(cpu), "model", model, &error_abort); 166 object_property_set_int(OBJECT(cpu), "stepping", stepping, 167 &error_abort); 168 object_property_set_str(OBJECT(cpu), "model-id", model_id, 169 &error_abort); 170 } 171 172 static void host_cpu_class_init(ObjectClass *oc, void *data) 173 { 174 X86CPUClass *xcc = X86_CPU_CLASS(oc); 175 176 xcc->host_cpuid_required = true; 177 xcc->ordering = 8; 178 xcc->model_description = 179 g_strdup_printf("processor with all supported host features "); 180 } 181 182 static const TypeInfo host_cpu_type_info = { 183 .name = X86_CPU_TYPE_NAME("host"), 184 .parent = X86_CPU_TYPE_NAME("max"), 185 .class_init = host_cpu_class_init, 186 }; 187 188 static void host_cpu_type_init(void) 189 { 190 type_register_static(&host_cpu_type_info); 191 } 192 193 type_init(host_cpu_type_init); 194