1 /* 2 * x86 host CPU functions, and "host" cpu type initialization 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "cpu.h" 12 #include "host-cpu.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "sysemu/sysemu.h" 16 17 /* Note: Only safe for use on x86(-64) hosts */ 18 static uint32_t host_cpu_phys_bits(void) 19 { 20 uint32_t eax; 21 uint32_t host_phys_bits; 22 23 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); 24 if (eax >= 0x80000008) { 25 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); 26 /* 27 * Note: According to AMD doc 25481 rev 2.34 they have a field 28 * at 23:16 that can specify a maximum physical address bits for 29 * the guest that can override this value; but I've not seen 30 * anything with that set. 31 */ 32 host_phys_bits = eax & 0xff; 33 } else { 34 /* 35 * It's an odd 64 bit machine that doesn't have the leaf for 36 * physical address bits; fall back to 36 that's most older 37 * Intel. 38 */ 39 host_phys_bits = 36; 40 } 41 42 return host_phys_bits; 43 } 44 45 static void host_cpu_enable_cpu_pm(X86CPU *cpu) 46 { 47 CPUX86State *env = &cpu->env; 48 49 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, 50 &cpu->mwait.ecx, &cpu->mwait.edx); 51 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; 52 } 53 54 static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu) 55 { 56 uint32_t host_phys_bits = host_cpu_phys_bits(); 57 uint32_t phys_bits = cpu->phys_bits; 58 59 /* 60 * Print a warning if the user set it to a value that's not the 61 * host value. 62 */ 63 if (phys_bits != host_phys_bits && phys_bits != 0) { 64 warn_report_once("Host physical bits (%u)" 65 " does not match phys-bits property (%u)", 66 host_phys_bits, phys_bits); 67 } 68 69 if (cpu->host_phys_bits) { 70 /* The user asked for us to use the host physical bits */ 71 phys_bits = host_phys_bits; 72 if (cpu->host_phys_bits_limit && 73 phys_bits > cpu->host_phys_bits_limit) { 74 phys_bits = cpu->host_phys_bits_limit; 75 } 76 } 77 78 return phys_bits; 79 } 80 81 bool host_cpu_realizefn(CPUState *cs, Error **errp) 82 { 83 X86CPU *cpu = X86_CPU(cs); 84 CPUX86State *env = &cpu->env; 85 86 if (cpu->max_features && enable_cpu_pm) { 87 host_cpu_enable_cpu_pm(cpu); 88 } 89 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 90 uint32_t phys_bits = host_cpu_adjust_phys_bits(cpu); 91 92 if (phys_bits && 93 (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 94 phys_bits < 32)) { 95 error_setg(errp, "phys-bits should be between 32 and %u " 96 " (but is %u)", 97 TARGET_PHYS_ADDR_SPACE_BITS, phys_bits); 98 return false; 99 } 100 cpu->phys_bits = phys_bits; 101 } 102 return true; 103 } 104 105 #define CPUID_MODEL_ID_SZ 48 106 /** 107 * cpu_x86_fill_model_id: 108 * Get CPUID model ID string from host CPU. 109 * 110 * @str should have at least CPUID_MODEL_ID_SZ bytes 111 * 112 * The function does NOT add a null terminator to the string 113 * automatically. 114 */ 115 static int host_cpu_fill_model_id(char *str) 116 { 117 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; 118 int i; 119 120 for (i = 0; i < 3; i++) { 121 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); 122 memcpy(str + i * 16 + 0, &eax, 4); 123 memcpy(str + i * 16 + 4, &ebx, 4); 124 memcpy(str + i * 16 + 8, &ecx, 4); 125 memcpy(str + i * 16 + 12, &edx, 4); 126 } 127 return 0; 128 } 129 130 void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping) 131 { 132 uint32_t eax, ebx, ecx, edx; 133 134 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); 135 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 136 137 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); 138 if (family) { 139 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); 140 } 141 if (model) { 142 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); 143 } 144 if (stepping) { 145 *stepping = eax & 0x0F; 146 } 147 } 148 149 void host_cpu_instance_init(X86CPU *cpu) 150 { 151 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 152 153 if (xcc->model) { 154 uint32_t ebx = 0, ecx = 0, edx = 0; 155 char vendor[CPUID_VENDOR_SZ + 1]; 156 157 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); 158 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 159 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 160 } 161 } 162 163 void host_cpu_max_instance_init(X86CPU *cpu) 164 { 165 char vendor[CPUID_VENDOR_SZ + 1] = { 0 }; 166 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 }; 167 int family, model, stepping; 168 169 /* Use max host physical address bits if -cpu max option is applied */ 170 object_property_set_bool(OBJECT(cpu), "host-phys-bits", true, &error_abort); 171 172 host_cpu_vendor_fms(vendor, &family, &model, &stepping); 173 host_cpu_fill_model_id(model_id); 174 175 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 176 object_property_set_int(OBJECT(cpu), "family", family, &error_abort); 177 object_property_set_int(OBJECT(cpu), "model", model, &error_abort); 178 object_property_set_int(OBJECT(cpu), "stepping", stepping, 179 &error_abort); 180 object_property_set_str(OBJECT(cpu), "model-id", model_id, 181 &error_abort); 182 } 183 184 static void host_cpu_class_init(ObjectClass *oc, void *data) 185 { 186 X86CPUClass *xcc = X86_CPU_CLASS(oc); 187 188 xcc->host_cpuid_required = true; 189 xcc->ordering = 8; 190 xcc->model_description = 191 g_strdup_printf("processor with all supported host features "); 192 } 193 194 static const TypeInfo host_cpu_type_info = { 195 .name = X86_CPU_TYPE_NAME("host"), 196 .parent = X86_CPU_TYPE_NAME("max"), 197 .class_init = host_cpu_class_init, 198 }; 199 200 static void host_cpu_type_init(void) 201 { 202 type_register_static(&host_cpu_type_info); 203 } 204 205 type_init(host_cpu_type_init); 206