1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "kvm/hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 #define KVM_HAVE_MCE_INJECTION 1 33 34 /* support for self modifying code even if the modified instruction is 35 close to the modifying instruction */ 36 #define TARGET_HAS_PRECISE_SMC 37 38 #ifdef TARGET_X86_64 39 #define I386_ELF_MACHINE EM_X86_64 40 #define ELF_MACHINE_UNAME "x86_64" 41 #else 42 #define I386_ELF_MACHINE EM_386 43 #define ELF_MACHINE_UNAME "i686" 44 #endif 45 46 enum { 47 R_EAX = 0, 48 R_ECX = 1, 49 R_EDX = 2, 50 R_EBX = 3, 51 R_ESP = 4, 52 R_EBP = 5, 53 R_ESI = 6, 54 R_EDI = 7, 55 R_R8 = 8, 56 R_R9 = 9, 57 R_R10 = 10, 58 R_R11 = 11, 59 R_R12 = 12, 60 R_R13 = 13, 61 R_R14 = 14, 62 R_R15 = 15, 63 64 R_AL = 0, 65 R_CL = 1, 66 R_DL = 2, 67 R_BL = 3, 68 R_AH = 4, 69 R_CH = 5, 70 R_DH = 6, 71 R_BH = 7, 72 }; 73 74 typedef enum X86Seg { 75 R_ES = 0, 76 R_CS = 1, 77 R_SS = 2, 78 R_DS = 3, 79 R_FS = 4, 80 R_GS = 5, 81 R_LDTR = 6, 82 R_TR = 7, 83 } X86Seg; 84 85 /* segment descriptor fields */ 86 #define DESC_G_SHIFT 23 87 #define DESC_G_MASK (1 << DESC_G_SHIFT) 88 #define DESC_B_SHIFT 22 89 #define DESC_B_MASK (1 << DESC_B_SHIFT) 90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91 #define DESC_L_MASK (1 << DESC_L_SHIFT) 92 #define DESC_AVL_SHIFT 20 93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94 #define DESC_P_SHIFT 15 95 #define DESC_P_MASK (1 << DESC_P_SHIFT) 96 #define DESC_DPL_SHIFT 13 97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98 #define DESC_S_SHIFT 12 99 #define DESC_S_MASK (1 << DESC_S_SHIFT) 100 #define DESC_TYPE_SHIFT 8 101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102 #define DESC_A_MASK (1 << 8) 103 104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105 #define DESC_C_MASK (1 << 10) /* code: conforming */ 106 #define DESC_R_MASK (1 << 9) /* code: readable */ 107 108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109 #define DESC_W_MASK (1 << 9) /* data: writable */ 110 111 #define DESC_TSS_BUSY_MASK (1 << 9) 112 113 /* eflags masks */ 114 #define CC_C 0x0001 115 #define CC_P 0x0004 116 #define CC_A 0x0010 117 #define CC_Z 0x0040 118 #define CC_S 0x0080 119 #define CC_O 0x0800 120 121 #define TF_SHIFT 8 122 #define IOPL_SHIFT 12 123 #define VM_SHIFT 17 124 125 #define TF_MASK 0x00000100 126 #define IF_MASK 0x00000200 127 #define DF_MASK 0x00000400 128 #define IOPL_MASK 0x00003000 129 #define NT_MASK 0x00004000 130 #define RF_MASK 0x00010000 131 #define VM_MASK 0x00020000 132 #define AC_MASK 0x00040000 133 #define VIF_MASK 0x00080000 134 #define VIP_MASK 0x00100000 135 #define ID_MASK 0x00200000 136 137 /* hidden flags - used internally by qemu to represent additional cpu 138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140 positions to ease oring with eflags. */ 141 /* current cpl */ 142 #define HF_CPL_SHIFT 0 143 /* true if hardware interrupts must be disabled for next instruction */ 144 #define HF_INHIBIT_IRQ_SHIFT 3 145 /* 16 or 32 segments */ 146 #define HF_CS32_SHIFT 4 147 #define HF_SS32_SHIFT 5 148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149 #define HF_ADDSEG_SHIFT 6 150 /* copy of CR0.PE (protected mode) */ 151 #define HF_PE_SHIFT 7 152 #define HF_TF_SHIFT 8 /* must be same as eflags */ 153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154 #define HF_EM_SHIFT 10 155 #define HF_TS_SHIFT 11 156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159 #define HF_RF_SHIFT 16 /* must be same as eflags */ 160 #define HF_VM_SHIFT 17 /* must be same as eflags */ 161 #define HF_AC_SHIFT 18 /* must be same as eflags */ 162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170 171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176 #define HF_PE_MASK (1 << HF_PE_SHIFT) 177 #define HF_TF_MASK (1 << HF_TF_SHIFT) 178 #define HF_MP_MASK (1 << HF_MP_SHIFT) 179 #define HF_EM_MASK (1 << HF_EM_SHIFT) 180 #define HF_TS_MASK (1 << HF_TS_SHIFT) 181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184 #define HF_RF_MASK (1 << HF_RF_SHIFT) 185 #define HF_VM_MASK (1 << HF_VM_SHIFT) 186 #define HF_AC_MASK (1 << HF_AC_SHIFT) 187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195 196 /* hflags2 */ 197 198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 206 #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/ 207 208 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 209 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 210 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 211 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 212 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 213 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 214 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 215 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 216 #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT) 217 218 #define CR0_PE_SHIFT 0 219 #define CR0_MP_SHIFT 1 220 221 #define CR0_PE_MASK (1U << 0) 222 #define CR0_MP_MASK (1U << 1) 223 #define CR0_EM_MASK (1U << 2) 224 #define CR0_TS_MASK (1U << 3) 225 #define CR0_ET_MASK (1U << 4) 226 #define CR0_NE_MASK (1U << 5) 227 #define CR0_WP_MASK (1U << 16) 228 #define CR0_AM_MASK (1U << 18) 229 #define CR0_NW_MASK (1U << 29) 230 #define CR0_CD_MASK (1U << 30) 231 #define CR0_PG_MASK (1U << 31) 232 233 #define CR4_VME_MASK (1U << 0) 234 #define CR4_PVI_MASK (1U << 1) 235 #define CR4_TSD_MASK (1U << 2) 236 #define CR4_DE_MASK (1U << 3) 237 #define CR4_PSE_MASK (1U << 4) 238 #define CR4_PAE_MASK (1U << 5) 239 #define CR4_MCE_MASK (1U << 6) 240 #define CR4_PGE_MASK (1U << 7) 241 #define CR4_PCE_MASK (1U << 8) 242 #define CR4_OSFXSR_SHIFT 9 243 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 244 #define CR4_OSXMMEXCPT_MASK (1U << 10) 245 #define CR4_UMIP_MASK (1U << 11) 246 #define CR4_LA57_MASK (1U << 12) 247 #define CR4_VMXE_MASK (1U << 13) 248 #define CR4_SMXE_MASK (1U << 14) 249 #define CR4_FSGSBASE_MASK (1U << 16) 250 #define CR4_PCIDE_MASK (1U << 17) 251 #define CR4_OSXSAVE_MASK (1U << 18) 252 #define CR4_SMEP_MASK (1U << 20) 253 #define CR4_SMAP_MASK (1U << 21) 254 #define CR4_PKE_MASK (1U << 22) 255 #define CR4_PKS_MASK (1U << 24) 256 257 #define CR4_RESERVED_MASK \ 258 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ 259 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ 260 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ 261 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK |CR4_UMIP_MASK \ 262 | CR4_LA57_MASK \ 263 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ 264 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) 265 266 #define DR6_BD (1 << 13) 267 #define DR6_BS (1 << 14) 268 #define DR6_BT (1 << 15) 269 #define DR6_FIXED_1 0xffff0ff0 270 271 #define DR7_GD (1 << 13) 272 #define DR7_TYPE_SHIFT 16 273 #define DR7_LEN_SHIFT 18 274 #define DR7_FIXED_1 0x00000400 275 #define DR7_GLOBAL_BP_MASK 0xaa 276 #define DR7_LOCAL_BP_MASK 0x55 277 #define DR7_MAX_BP 4 278 #define DR7_TYPE_BP_INST 0x0 279 #define DR7_TYPE_DATA_WR 0x1 280 #define DR7_TYPE_IO_RW 0x2 281 #define DR7_TYPE_DATA_RW 0x3 282 283 #define DR_RESERVED_MASK 0xffffffff00000000ULL 284 285 #define PG_PRESENT_BIT 0 286 #define PG_RW_BIT 1 287 #define PG_USER_BIT 2 288 #define PG_PWT_BIT 3 289 #define PG_PCD_BIT 4 290 #define PG_ACCESSED_BIT 5 291 #define PG_DIRTY_BIT 6 292 #define PG_PSE_BIT 7 293 #define PG_GLOBAL_BIT 8 294 #define PG_PSE_PAT_BIT 12 295 #define PG_PKRU_BIT 59 296 #define PG_NX_BIT 63 297 298 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 299 #define PG_RW_MASK (1 << PG_RW_BIT) 300 #define PG_USER_MASK (1 << PG_USER_BIT) 301 #define PG_PWT_MASK (1 << PG_PWT_BIT) 302 #define PG_PCD_MASK (1 << PG_PCD_BIT) 303 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 304 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 305 #define PG_PSE_MASK (1 << PG_PSE_BIT) 306 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 307 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 308 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 309 #define PG_HI_USER_MASK 0x7ff0000000000000LL 310 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 311 #define PG_NX_MASK (1ULL << PG_NX_BIT) 312 313 #define PG_ERROR_W_BIT 1 314 315 #define PG_ERROR_P_MASK 0x01 316 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 317 #define PG_ERROR_U_MASK 0x04 318 #define PG_ERROR_RSVD_MASK 0x08 319 #define PG_ERROR_I_D_MASK 0x10 320 #define PG_ERROR_PK_MASK 0x20 321 322 #define PG_MODE_PAE (1 << 0) 323 #define PG_MODE_LMA (1 << 1) 324 #define PG_MODE_NXE (1 << 2) 325 #define PG_MODE_PSE (1 << 3) 326 #define PG_MODE_LA57 (1 << 4) 327 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) 328 329 /* Bits of CR4 that do not affect the NPT page format. */ 330 #define PG_MODE_WP (1 << 16) 331 #define PG_MODE_PKE (1 << 17) 332 #define PG_MODE_PKS (1 << 18) 333 #define PG_MODE_SMEP (1 << 19) 334 335 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 336 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 337 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 338 339 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 340 #define MCE_BANKS_DEF 10 341 342 #define MCG_CAP_BANKS_MASK 0xff 343 344 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 345 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 346 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 347 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 348 349 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 350 351 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 352 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 353 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 354 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 355 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 356 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 357 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 358 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 359 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 360 361 /* MISC register defines */ 362 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 363 #define MCM_ADDR_LINEAR 1 /* linear address */ 364 #define MCM_ADDR_PHYS 2 /* physical address */ 365 #define MCM_ADDR_MEM 3 /* memory address */ 366 #define MCM_ADDR_GENERIC 7 /* generic */ 367 368 #define MSR_IA32_TSC 0x10 369 #define MSR_IA32_APICBASE 0x1b 370 #define MSR_IA32_APICBASE_BSP (1<<8) 371 #define MSR_IA32_APICBASE_ENABLE (1<<11) 372 #define MSR_IA32_APICBASE_EXTD (1 << 10) 373 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 374 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 375 #define MSR_TSC_ADJUST 0x0000003b 376 #define MSR_IA32_SPEC_CTRL 0x48 377 #define MSR_VIRT_SSBD 0xc001011f 378 #define MSR_IA32_PRED_CMD 0x49 379 #define MSR_IA32_UCODE_REV 0x8b 380 #define MSR_IA32_CORE_CAPABILITY 0xcf 381 382 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 383 #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 384 385 #define MSR_IA32_PERF_CAPABILITIES 0x345 386 387 #define MSR_IA32_TSX_CTRL 0x122 388 #define MSR_IA32_TSCDEADLINE 0x6e0 389 #define MSR_IA32_PKRS 0x6e1 390 391 #define FEATURE_CONTROL_LOCKED (1<<0) 392 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1) 393 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 394 #define FEATURE_CONTROL_SGX_LC (1ULL << 17) 395 #define FEATURE_CONTROL_SGX (1ULL << 18) 396 #define FEATURE_CONTROL_LMCE (1<<20) 397 398 #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c 399 #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d 400 #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e 401 #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f 402 403 #define MSR_P6_PERFCTR0 0xc1 404 405 #define MSR_IA32_SMBASE 0x9e 406 #define MSR_SMI_COUNT 0x34 407 #define MSR_CORE_THREAD_COUNT 0x35 408 #define MSR_MTRRcap 0xfe 409 #define MSR_MTRRcap_VCNT 8 410 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 411 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 412 413 #define MSR_IA32_SYSENTER_CS 0x174 414 #define MSR_IA32_SYSENTER_ESP 0x175 415 #define MSR_IA32_SYSENTER_EIP 0x176 416 417 #define MSR_MCG_CAP 0x179 418 #define MSR_MCG_STATUS 0x17a 419 #define MSR_MCG_CTL 0x17b 420 #define MSR_MCG_EXT_CTL 0x4d0 421 422 #define MSR_P6_EVNTSEL0 0x186 423 424 #define MSR_IA32_PERF_STATUS 0x198 425 426 #define MSR_IA32_MISC_ENABLE 0x1a0 427 /* Indicates good rep/movs microcode on some processors: */ 428 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 429 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 430 431 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 432 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 433 434 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 435 436 #define MSR_MTRRfix64K_00000 0x250 437 #define MSR_MTRRfix16K_80000 0x258 438 #define MSR_MTRRfix16K_A0000 0x259 439 #define MSR_MTRRfix4K_C0000 0x268 440 #define MSR_MTRRfix4K_C8000 0x269 441 #define MSR_MTRRfix4K_D0000 0x26a 442 #define MSR_MTRRfix4K_D8000 0x26b 443 #define MSR_MTRRfix4K_E0000 0x26c 444 #define MSR_MTRRfix4K_E8000 0x26d 445 #define MSR_MTRRfix4K_F0000 0x26e 446 #define MSR_MTRRfix4K_F8000 0x26f 447 448 #define MSR_PAT 0x277 449 450 #define MSR_MTRRdefType 0x2ff 451 452 #define MSR_CORE_PERF_FIXED_CTR0 0x309 453 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 454 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 455 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 456 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 457 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 458 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 459 460 #define MSR_MC0_CTL 0x400 461 #define MSR_MC0_STATUS 0x401 462 #define MSR_MC0_ADDR 0x402 463 #define MSR_MC0_MISC 0x403 464 465 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 466 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 467 #define MSR_IA32_RTIT_CTL 0x570 468 #define MSR_IA32_RTIT_STATUS 0x571 469 #define MSR_IA32_RTIT_CR3_MATCH 0x572 470 #define MSR_IA32_RTIT_ADDR0_A 0x580 471 #define MSR_IA32_RTIT_ADDR0_B 0x581 472 #define MSR_IA32_RTIT_ADDR1_A 0x582 473 #define MSR_IA32_RTIT_ADDR1_B 0x583 474 #define MSR_IA32_RTIT_ADDR2_A 0x584 475 #define MSR_IA32_RTIT_ADDR2_B 0x585 476 #define MSR_IA32_RTIT_ADDR3_A 0x586 477 #define MSR_IA32_RTIT_ADDR3_B 0x587 478 #define MAX_RTIT_ADDRS 8 479 480 #define MSR_EFER 0xc0000080 481 482 #define MSR_EFER_SCE (1 << 0) 483 #define MSR_EFER_LME (1 << 8) 484 #define MSR_EFER_LMA (1 << 10) 485 #define MSR_EFER_NXE (1 << 11) 486 #define MSR_EFER_SVME (1 << 12) 487 #define MSR_EFER_FFXSR (1 << 14) 488 489 #define MSR_EFER_RESERVED\ 490 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\ 491 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\ 492 | MSR_EFER_FFXSR)) 493 494 #define MSR_STAR 0xc0000081 495 #define MSR_LSTAR 0xc0000082 496 #define MSR_CSTAR 0xc0000083 497 #define MSR_FMASK 0xc0000084 498 #define MSR_FSBASE 0xc0000100 499 #define MSR_GSBASE 0xc0000101 500 #define MSR_KERNELGSBASE 0xc0000102 501 #define MSR_TSC_AUX 0xc0000103 502 503 #define MSR_VM_HSAVE_PA 0xc0010117 504 505 #define MSR_IA32_BNDCFGS 0x00000d90 506 #define MSR_IA32_XSS 0x00000da0 507 #define MSR_IA32_UMWAIT_CONTROL 0xe1 508 509 #define MSR_IA32_VMX_BASIC 0x00000480 510 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 511 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 512 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 513 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 514 #define MSR_IA32_VMX_MISC 0x00000485 515 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 516 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 517 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 518 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 519 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 520 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 521 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 522 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 523 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 524 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 525 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 526 #define MSR_IA32_VMX_VMFUNC 0x00000491 527 528 #define XSTATE_FP_BIT 0 529 #define XSTATE_SSE_BIT 1 530 #define XSTATE_YMM_BIT 2 531 #define XSTATE_BNDREGS_BIT 3 532 #define XSTATE_BNDCSR_BIT 4 533 #define XSTATE_OPMASK_BIT 5 534 #define XSTATE_ZMM_Hi256_BIT 6 535 #define XSTATE_Hi16_ZMM_BIT 7 536 #define XSTATE_PKRU_BIT 9 537 538 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 539 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 540 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 541 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 542 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 543 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 544 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 545 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 546 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 547 548 /* CPUID feature words */ 549 typedef enum FeatureWord { 550 FEAT_1_EDX, /* CPUID[1].EDX */ 551 FEAT_1_ECX, /* CPUID[1].ECX */ 552 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 553 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 554 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 555 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 556 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 557 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 558 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 559 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 560 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 561 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 562 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 563 FEAT_SVM, /* CPUID[8000_000A].EDX */ 564 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 565 FEAT_6_EAX, /* CPUID[6].EAX */ 566 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 567 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 568 FEAT_ARCH_CAPABILITIES, 569 FEAT_CORE_CAPABILITY, 570 FEAT_PERF_CAPABILITIES, 571 FEAT_VMX_PROCBASED_CTLS, 572 FEAT_VMX_SECONDARY_CTLS, 573 FEAT_VMX_PINBASED_CTLS, 574 FEAT_VMX_EXIT_CTLS, 575 FEAT_VMX_ENTRY_CTLS, 576 FEAT_VMX_MISC, 577 FEAT_VMX_EPT_VPID_CAPS, 578 FEAT_VMX_BASIC, 579 FEAT_VMX_VMFUNC, 580 FEAT_14_0_ECX, 581 FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */ 582 FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */ 583 FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ 584 FEATURE_WORDS, 585 } FeatureWord; 586 587 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 588 589 /* cpuid_features bits */ 590 #define CPUID_FP87 (1U << 0) 591 #define CPUID_VME (1U << 1) 592 #define CPUID_DE (1U << 2) 593 #define CPUID_PSE (1U << 3) 594 #define CPUID_TSC (1U << 4) 595 #define CPUID_MSR (1U << 5) 596 #define CPUID_PAE (1U << 6) 597 #define CPUID_MCE (1U << 7) 598 #define CPUID_CX8 (1U << 8) 599 #define CPUID_APIC (1U << 9) 600 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 601 #define CPUID_MTRR (1U << 12) 602 #define CPUID_PGE (1U << 13) 603 #define CPUID_MCA (1U << 14) 604 #define CPUID_CMOV (1U << 15) 605 #define CPUID_PAT (1U << 16) 606 #define CPUID_PSE36 (1U << 17) 607 #define CPUID_PN (1U << 18) 608 #define CPUID_CLFLUSH (1U << 19) 609 #define CPUID_DTS (1U << 21) 610 #define CPUID_ACPI (1U << 22) 611 #define CPUID_MMX (1U << 23) 612 #define CPUID_FXSR (1U << 24) 613 #define CPUID_SSE (1U << 25) 614 #define CPUID_SSE2 (1U << 26) 615 #define CPUID_SS (1U << 27) 616 #define CPUID_HT (1U << 28) 617 #define CPUID_TM (1U << 29) 618 #define CPUID_IA64 (1U << 30) 619 #define CPUID_PBE (1U << 31) 620 621 #define CPUID_EXT_SSE3 (1U << 0) 622 #define CPUID_EXT_PCLMULQDQ (1U << 1) 623 #define CPUID_EXT_DTES64 (1U << 2) 624 #define CPUID_EXT_MONITOR (1U << 3) 625 #define CPUID_EXT_DSCPL (1U << 4) 626 #define CPUID_EXT_VMX (1U << 5) 627 #define CPUID_EXT_SMX (1U << 6) 628 #define CPUID_EXT_EST (1U << 7) 629 #define CPUID_EXT_TM2 (1U << 8) 630 #define CPUID_EXT_SSSE3 (1U << 9) 631 #define CPUID_EXT_CID (1U << 10) 632 #define CPUID_EXT_FMA (1U << 12) 633 #define CPUID_EXT_CX16 (1U << 13) 634 #define CPUID_EXT_XTPR (1U << 14) 635 #define CPUID_EXT_PDCM (1U << 15) 636 #define CPUID_EXT_PCID (1U << 17) 637 #define CPUID_EXT_DCA (1U << 18) 638 #define CPUID_EXT_SSE41 (1U << 19) 639 #define CPUID_EXT_SSE42 (1U << 20) 640 #define CPUID_EXT_X2APIC (1U << 21) 641 #define CPUID_EXT_MOVBE (1U << 22) 642 #define CPUID_EXT_POPCNT (1U << 23) 643 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 644 #define CPUID_EXT_AES (1U << 25) 645 #define CPUID_EXT_XSAVE (1U << 26) 646 #define CPUID_EXT_OSXSAVE (1U << 27) 647 #define CPUID_EXT_AVX (1U << 28) 648 #define CPUID_EXT_F16C (1U << 29) 649 #define CPUID_EXT_RDRAND (1U << 30) 650 #define CPUID_EXT_HYPERVISOR (1U << 31) 651 652 #define CPUID_EXT2_FPU (1U << 0) 653 #define CPUID_EXT2_VME (1U << 1) 654 #define CPUID_EXT2_DE (1U << 2) 655 #define CPUID_EXT2_PSE (1U << 3) 656 #define CPUID_EXT2_TSC (1U << 4) 657 #define CPUID_EXT2_MSR (1U << 5) 658 #define CPUID_EXT2_PAE (1U << 6) 659 #define CPUID_EXT2_MCE (1U << 7) 660 #define CPUID_EXT2_CX8 (1U << 8) 661 #define CPUID_EXT2_APIC (1U << 9) 662 #define CPUID_EXT2_SYSCALL (1U << 11) 663 #define CPUID_EXT2_MTRR (1U << 12) 664 #define CPUID_EXT2_PGE (1U << 13) 665 #define CPUID_EXT2_MCA (1U << 14) 666 #define CPUID_EXT2_CMOV (1U << 15) 667 #define CPUID_EXT2_PAT (1U << 16) 668 #define CPUID_EXT2_PSE36 (1U << 17) 669 #define CPUID_EXT2_MP (1U << 19) 670 #define CPUID_EXT2_NX (1U << 20) 671 #define CPUID_EXT2_MMXEXT (1U << 22) 672 #define CPUID_EXT2_MMX (1U << 23) 673 #define CPUID_EXT2_FXSR (1U << 24) 674 #define CPUID_EXT2_FFXSR (1U << 25) 675 #define CPUID_EXT2_PDPE1GB (1U << 26) 676 #define CPUID_EXT2_RDTSCP (1U << 27) 677 #define CPUID_EXT2_LM (1U << 29) 678 #define CPUID_EXT2_3DNOWEXT (1U << 30) 679 #define CPUID_EXT2_3DNOW (1U << 31) 680 681 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 682 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 683 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 684 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 685 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 686 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 687 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 688 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 689 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 690 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 691 692 #define CPUID_EXT3_LAHF_LM (1U << 0) 693 #define CPUID_EXT3_CMP_LEG (1U << 1) 694 #define CPUID_EXT3_SVM (1U << 2) 695 #define CPUID_EXT3_EXTAPIC (1U << 3) 696 #define CPUID_EXT3_CR8LEG (1U << 4) 697 #define CPUID_EXT3_ABM (1U << 5) 698 #define CPUID_EXT3_SSE4A (1U << 6) 699 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 700 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 701 #define CPUID_EXT3_OSVW (1U << 9) 702 #define CPUID_EXT3_IBS (1U << 10) 703 #define CPUID_EXT3_XOP (1U << 11) 704 #define CPUID_EXT3_SKINIT (1U << 12) 705 #define CPUID_EXT3_WDT (1U << 13) 706 #define CPUID_EXT3_LWP (1U << 15) 707 #define CPUID_EXT3_FMA4 (1U << 16) 708 #define CPUID_EXT3_TCE (1U << 17) 709 #define CPUID_EXT3_NODEID (1U << 19) 710 #define CPUID_EXT3_TBM (1U << 21) 711 #define CPUID_EXT3_TOPOEXT (1U << 22) 712 #define CPUID_EXT3_PERFCORE (1U << 23) 713 #define CPUID_EXT3_PERFNB (1U << 24) 714 715 #define CPUID_SVM_NPT (1U << 0) 716 #define CPUID_SVM_LBRV (1U << 1) 717 #define CPUID_SVM_SVMLOCK (1U << 2) 718 #define CPUID_SVM_NRIPSAVE (1U << 3) 719 #define CPUID_SVM_TSCSCALE (1U << 4) 720 #define CPUID_SVM_VMCBCLEAN (1U << 5) 721 #define CPUID_SVM_FLUSHASID (1U << 6) 722 #define CPUID_SVM_DECODEASSIST (1U << 7) 723 #define CPUID_SVM_PAUSEFILTER (1U << 10) 724 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 725 #define CPUID_SVM_AVIC (1U << 13) 726 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) 727 #define CPUID_SVM_VGIF (1U << 16) 728 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) 729 730 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 731 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 732 /* Support SGX */ 733 #define CPUID_7_0_EBX_SGX (1U << 2) 734 /* 1st Group of Advanced Bit Manipulation Extensions */ 735 #define CPUID_7_0_EBX_BMI1 (1U << 3) 736 /* Hardware Lock Elision */ 737 #define CPUID_7_0_EBX_HLE (1U << 4) 738 /* Intel Advanced Vector Extensions 2 */ 739 #define CPUID_7_0_EBX_AVX2 (1U << 5) 740 /* Supervisor-mode Execution Prevention */ 741 #define CPUID_7_0_EBX_SMEP (1U << 7) 742 /* 2nd Group of Advanced Bit Manipulation Extensions */ 743 #define CPUID_7_0_EBX_BMI2 (1U << 8) 744 /* Enhanced REP MOVSB/STOSB */ 745 #define CPUID_7_0_EBX_ERMS (1U << 9) 746 /* Invalidate Process-Context Identifier */ 747 #define CPUID_7_0_EBX_INVPCID (1U << 10) 748 /* Restricted Transactional Memory */ 749 #define CPUID_7_0_EBX_RTM (1U << 11) 750 /* Memory Protection Extension */ 751 #define CPUID_7_0_EBX_MPX (1U << 14) 752 /* AVX-512 Foundation */ 753 #define CPUID_7_0_EBX_AVX512F (1U << 16) 754 /* AVX-512 Doubleword & Quadword Instruction */ 755 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 756 /* Read Random SEED */ 757 #define CPUID_7_0_EBX_RDSEED (1U << 18) 758 /* ADCX and ADOX instructions */ 759 #define CPUID_7_0_EBX_ADX (1U << 19) 760 /* Supervisor Mode Access Prevention */ 761 #define CPUID_7_0_EBX_SMAP (1U << 20) 762 /* AVX-512 Integer Fused Multiply Add */ 763 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 764 /* Persistent Commit */ 765 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 766 /* Flush a Cache Line Optimized */ 767 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 768 /* Cache Line Write Back */ 769 #define CPUID_7_0_EBX_CLWB (1U << 24) 770 /* Intel Processor Trace */ 771 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 772 /* AVX-512 Prefetch */ 773 #define CPUID_7_0_EBX_AVX512PF (1U << 26) 774 /* AVX-512 Exponential and Reciprocal */ 775 #define CPUID_7_0_EBX_AVX512ER (1U << 27) 776 /* AVX-512 Conflict Detection */ 777 #define CPUID_7_0_EBX_AVX512CD (1U << 28) 778 /* SHA1/SHA256 Instruction Extensions */ 779 #define CPUID_7_0_EBX_SHA_NI (1U << 29) 780 /* AVX-512 Byte and Word Instructions */ 781 #define CPUID_7_0_EBX_AVX512BW (1U << 30) 782 /* AVX-512 Vector Length Extensions */ 783 #define CPUID_7_0_EBX_AVX512VL (1U << 31) 784 785 /* AVX-512 Vector Byte Manipulation Instruction */ 786 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 787 /* User-Mode Instruction Prevention */ 788 #define CPUID_7_0_ECX_UMIP (1U << 2) 789 /* Protection Keys for User-mode Pages */ 790 #define CPUID_7_0_ECX_PKU (1U << 3) 791 /* OS Enable Protection Keys */ 792 #define CPUID_7_0_ECX_OSPKE (1U << 4) 793 /* UMONITOR/UMWAIT/TPAUSE Instructions */ 794 #define CPUID_7_0_ECX_WAITPKG (1U << 5) 795 /* Additional AVX-512 Vector Byte Manipulation Instruction */ 796 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 797 /* Galois Field New Instructions */ 798 #define CPUID_7_0_ECX_GFNI (1U << 8) 799 /* Vector AES Instructions */ 800 #define CPUID_7_0_ECX_VAES (1U << 9) 801 /* Carry-Less Multiplication Quadword */ 802 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 803 /* Vector Neural Network Instructions */ 804 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 805 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 806 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 807 /* POPCNT for vectors of DW/QW */ 808 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 809 /* 5-level Page Tables */ 810 #define CPUID_7_0_ECX_LA57 (1U << 16) 811 /* Read Processor ID */ 812 #define CPUID_7_0_ECX_RDPID (1U << 22) 813 /* Bus Lock Debug Exception */ 814 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) 815 /* Cache Line Demote Instruction */ 816 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 817 /* Move Doubleword as Direct Store Instruction */ 818 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 819 /* Move 64 Bytes as Direct Store Instruction */ 820 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 821 /* Support SGX Launch Control */ 822 #define CPUID_7_0_ECX_SGX_LC (1U << 30) 823 /* Protection Keys for Supervisor-mode Pages */ 824 #define CPUID_7_0_ECX_PKS (1U << 31) 825 826 /* AVX512 Neural Network Instructions */ 827 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 828 /* AVX512 Multiply Accumulation Single Precision */ 829 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 830 /* Fast Short Rep Mov */ 831 #define CPUID_7_0_EDX_FSRM (1U << 4) 832 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 833 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 834 /* SERIALIZE instruction */ 835 #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 836 /* TSX Suspend Load Address Tracking instruction */ 837 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 838 /* AVX512_FP16 instruction */ 839 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) 840 /* Speculation Control */ 841 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 842 /* Single Thread Indirect Branch Predictors */ 843 #define CPUID_7_0_EDX_STIBP (1U << 27) 844 /* Arch Capabilities */ 845 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 846 /* Core Capability */ 847 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 848 /* Speculative Store Bypass Disable */ 849 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 850 851 /* AVX VNNI Instruction */ 852 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) 853 /* AVX512 BFloat16 Instruction */ 854 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 855 856 /* Packets which contain IP payload have LIP values */ 857 #define CPUID_14_0_ECX_LIP (1U << 31) 858 859 /* CLZERO instruction */ 860 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 861 /* Always save/restore FP error pointers */ 862 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 863 /* Write back and do not invalidate cache */ 864 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 865 /* Indirect Branch Prediction Barrier */ 866 #define CPUID_8000_0008_EBX_IBPB (1U << 12) 867 /* Indirect Branch Restricted Speculation */ 868 #define CPUID_8000_0008_EBX_IBRS (1U << 14) 869 /* Single Thread Indirect Branch Predictors */ 870 #define CPUID_8000_0008_EBX_STIBP (1U << 15) 871 /* Speculative Store Bypass Disable */ 872 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) 873 874 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 875 #define CPUID_XSAVE_XSAVEC (1U << 1) 876 #define CPUID_XSAVE_XGETBV1 (1U << 2) 877 #define CPUID_XSAVE_XSAVES (1U << 3) 878 879 #define CPUID_6_EAX_ARAT (1U << 2) 880 881 /* CPUID[0x80000007].EDX flags: */ 882 #define CPUID_APM_INVTSC (1U << 8) 883 884 #define CPUID_VENDOR_SZ 12 885 886 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 887 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 888 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 889 #define CPUID_VENDOR_INTEL "GenuineIntel" 890 891 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 892 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 893 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 894 #define CPUID_VENDOR_AMD "AuthenticAMD" 895 896 #define CPUID_VENDOR_VIA "CentaurHauls" 897 898 #define CPUID_VENDOR_HYGON "HygonGenuine" 899 900 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 901 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 902 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 903 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 904 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 905 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 906 907 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 908 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 909 910 /* CPUID[0xB].ECX level types */ 911 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 912 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 913 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 914 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 915 916 /* MSR Feature Bits */ 917 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 918 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 919 #define MSR_ARCH_CAP_RSBA (1U << 2) 920 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 921 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 922 #define MSR_ARCH_CAP_MDS_NO (1U << 5) 923 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 924 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 925 #define MSR_ARCH_CAP_TAA_NO (1U << 8) 926 927 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 928 929 /* VMX MSR features */ 930 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 931 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 932 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 933 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 934 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 935 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 936 937 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 938 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 939 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 940 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 941 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 942 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 943 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 944 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 945 946 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 947 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 948 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 949 #define MSR_VMX_EPT_UC (1ULL << 8) 950 #define MSR_VMX_EPT_WB (1ULL << 14) 951 #define MSR_VMX_EPT_2MB (1ULL << 16) 952 #define MSR_VMX_EPT_1GB (1ULL << 17) 953 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 954 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 955 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 956 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 957 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 958 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 959 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 960 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 961 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 962 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 963 964 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 965 966 967 /* VMX controls */ 968 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 969 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 970 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 971 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 972 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 973 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 974 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 975 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 976 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 977 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 978 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 979 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 980 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 981 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 982 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 983 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 984 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 985 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 986 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 987 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 988 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 989 990 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 991 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 992 #define VMX_SECONDARY_EXEC_DESC 0x00000004 993 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 994 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 995 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 996 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 997 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 998 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 999 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 1000 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 1001 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 1002 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 1003 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 1004 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 1005 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 1006 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 1007 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 1008 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 1009 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000 1010 1011 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 1012 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 1013 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 1014 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 1015 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 1016 1017 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 1018 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 1019 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 1020 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 1021 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 1022 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 1023 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 1024 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 1025 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 1026 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 1027 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 1028 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 1029 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 1030 1031 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 1032 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 1033 #define VMX_VM_ENTRY_SMM 0x00000400 1034 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 1035 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 1036 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 1037 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 1038 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 1039 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 1040 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 1041 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 1042 1043 /* Supported Hyper-V Enlightenments */ 1044 #define HYPERV_FEAT_RELAXED 0 1045 #define HYPERV_FEAT_VAPIC 1 1046 #define HYPERV_FEAT_TIME 2 1047 #define HYPERV_FEAT_CRASH 3 1048 #define HYPERV_FEAT_RESET 4 1049 #define HYPERV_FEAT_VPINDEX 5 1050 #define HYPERV_FEAT_RUNTIME 6 1051 #define HYPERV_FEAT_SYNIC 7 1052 #define HYPERV_FEAT_STIMER 8 1053 #define HYPERV_FEAT_FREQUENCIES 9 1054 #define HYPERV_FEAT_REENLIGHTENMENT 10 1055 #define HYPERV_FEAT_TLBFLUSH 11 1056 #define HYPERV_FEAT_EVMCS 12 1057 #define HYPERV_FEAT_IPI 13 1058 #define HYPERV_FEAT_STIMER_DIRECT 14 1059 1060 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY 1061 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF 1062 #endif 1063 1064 #define EXCP00_DIVZ 0 1065 #define EXCP01_DB 1 1066 #define EXCP02_NMI 2 1067 #define EXCP03_INT3 3 1068 #define EXCP04_INTO 4 1069 #define EXCP05_BOUND 5 1070 #define EXCP06_ILLOP 6 1071 #define EXCP07_PREX 7 1072 #define EXCP08_DBLE 8 1073 #define EXCP09_XERR 9 1074 #define EXCP0A_TSS 10 1075 #define EXCP0B_NOSEG 11 1076 #define EXCP0C_STACK 12 1077 #define EXCP0D_GPF 13 1078 #define EXCP0E_PAGE 14 1079 #define EXCP10_COPR 16 1080 #define EXCP11_ALGN 17 1081 #define EXCP12_MCHK 18 1082 1083 #define EXCP_VMEXIT 0x100 /* only for system emulation */ 1084 #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1085 #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1086 1087 /* i386-specific interrupt pending bits. */ 1088 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1089 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1090 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1091 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1092 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1093 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1094 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1095 1096 /* Use a clearer name for this. */ 1097 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1098 1099 /* Instead of computing the condition codes after each x86 instruction, 1100 * QEMU just stores one operand (called CC_SRC), the result 1101 * (called CC_DST) and the type of operation (called CC_OP). When the 1102 * condition codes are needed, the condition codes can be calculated 1103 * using this information. Condition codes are not generated if they 1104 * are only needed for conditional branches. 1105 */ 1106 typedef enum { 1107 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1108 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1109 1110 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1111 CC_OP_MULW, 1112 CC_OP_MULL, 1113 CC_OP_MULQ, 1114 1115 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1116 CC_OP_ADDW, 1117 CC_OP_ADDL, 1118 CC_OP_ADDQ, 1119 1120 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1121 CC_OP_ADCW, 1122 CC_OP_ADCL, 1123 CC_OP_ADCQ, 1124 1125 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1126 CC_OP_SUBW, 1127 CC_OP_SUBL, 1128 CC_OP_SUBQ, 1129 1130 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1131 CC_OP_SBBW, 1132 CC_OP_SBBL, 1133 CC_OP_SBBQ, 1134 1135 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1136 CC_OP_LOGICW, 1137 CC_OP_LOGICL, 1138 CC_OP_LOGICQ, 1139 1140 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1141 CC_OP_INCW, 1142 CC_OP_INCL, 1143 CC_OP_INCQ, 1144 1145 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1146 CC_OP_DECW, 1147 CC_OP_DECL, 1148 CC_OP_DECQ, 1149 1150 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1151 CC_OP_SHLW, 1152 CC_OP_SHLL, 1153 CC_OP_SHLQ, 1154 1155 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1156 CC_OP_SARW, 1157 CC_OP_SARL, 1158 CC_OP_SARQ, 1159 1160 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1161 CC_OP_BMILGW, 1162 CC_OP_BMILGL, 1163 CC_OP_BMILGQ, 1164 1165 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1166 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1167 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1168 1169 CC_OP_CLR, /* Z set, all other flags clear. */ 1170 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1171 1172 CC_OP_NB, 1173 } CCOp; 1174 1175 typedef struct SegmentCache { 1176 uint32_t selector; 1177 target_ulong base; 1178 uint32_t limit; 1179 uint32_t flags; 1180 } SegmentCache; 1181 1182 #define MMREG_UNION(n, bits) \ 1183 union n { \ 1184 uint8_t _b_##n[(bits)/8]; \ 1185 uint16_t _w_##n[(bits)/16]; \ 1186 uint32_t _l_##n[(bits)/32]; \ 1187 uint64_t _q_##n[(bits)/64]; \ 1188 float32 _s_##n[(bits)/32]; \ 1189 float64 _d_##n[(bits)/64]; \ 1190 } 1191 1192 typedef union { 1193 uint8_t _b[16]; 1194 uint16_t _w[8]; 1195 uint32_t _l[4]; 1196 uint64_t _q[2]; 1197 } XMMReg; 1198 1199 typedef union { 1200 uint8_t _b[32]; 1201 uint16_t _w[16]; 1202 uint32_t _l[8]; 1203 uint64_t _q[4]; 1204 } YMMReg; 1205 1206 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1207 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1208 1209 typedef struct BNDReg { 1210 uint64_t lb; 1211 uint64_t ub; 1212 } BNDReg; 1213 1214 typedef struct BNDCSReg { 1215 uint64_t cfgu; 1216 uint64_t sts; 1217 } BNDCSReg; 1218 1219 #define BNDCFG_ENABLE 1ULL 1220 #define BNDCFG_BNDPRESERVE 2ULL 1221 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1222 1223 #ifdef HOST_WORDS_BIGENDIAN 1224 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1225 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1226 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1227 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1228 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1229 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1230 1231 #define MMX_B(n) _b_MMXReg[7 - (n)] 1232 #define MMX_W(n) _w_MMXReg[3 - (n)] 1233 #define MMX_L(n) _l_MMXReg[1 - (n)] 1234 #define MMX_S(n) _s_MMXReg[1 - (n)] 1235 #else 1236 #define ZMM_B(n) _b_ZMMReg[n] 1237 #define ZMM_W(n) _w_ZMMReg[n] 1238 #define ZMM_L(n) _l_ZMMReg[n] 1239 #define ZMM_S(n) _s_ZMMReg[n] 1240 #define ZMM_Q(n) _q_ZMMReg[n] 1241 #define ZMM_D(n) _d_ZMMReg[n] 1242 1243 #define MMX_B(n) _b_MMXReg[n] 1244 #define MMX_W(n) _w_MMXReg[n] 1245 #define MMX_L(n) _l_MMXReg[n] 1246 #define MMX_S(n) _s_MMXReg[n] 1247 #endif 1248 #define MMX_Q(n) _q_MMXReg[n] 1249 1250 typedef union { 1251 floatx80 d __attribute__((aligned(16))); 1252 MMXReg mmx; 1253 } FPReg; 1254 1255 typedef struct { 1256 uint64_t base; 1257 uint64_t mask; 1258 } MTRRVar; 1259 1260 #define CPU_NB_REGS64 16 1261 #define CPU_NB_REGS32 8 1262 1263 #ifdef TARGET_X86_64 1264 #define CPU_NB_REGS CPU_NB_REGS64 1265 #else 1266 #define CPU_NB_REGS CPU_NB_REGS32 1267 #endif 1268 1269 #define MAX_FIXED_COUNTERS 3 1270 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1271 1272 #define TARGET_INSN_START_EXTRA_WORDS 1 1273 1274 #define NB_OPMASK_REGS 8 1275 1276 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1277 * that APIC ID hasn't been set yet 1278 */ 1279 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1280 1281 typedef union X86LegacyXSaveArea { 1282 struct { 1283 uint16_t fcw; 1284 uint16_t fsw; 1285 uint8_t ftw; 1286 uint8_t reserved; 1287 uint16_t fpop; 1288 uint64_t fpip; 1289 uint64_t fpdp; 1290 uint32_t mxcsr; 1291 uint32_t mxcsr_mask; 1292 FPReg fpregs[8]; 1293 uint8_t xmm_regs[16][16]; 1294 }; 1295 uint8_t data[512]; 1296 } X86LegacyXSaveArea; 1297 1298 typedef struct X86XSaveHeader { 1299 uint64_t xstate_bv; 1300 uint64_t xcomp_bv; 1301 uint64_t reserve0; 1302 uint8_t reserved[40]; 1303 } X86XSaveHeader; 1304 1305 /* Ext. save area 2: AVX State */ 1306 typedef struct XSaveAVX { 1307 uint8_t ymmh[16][16]; 1308 } XSaveAVX; 1309 1310 /* Ext. save area 3: BNDREG */ 1311 typedef struct XSaveBNDREG { 1312 BNDReg bnd_regs[4]; 1313 } XSaveBNDREG; 1314 1315 /* Ext. save area 4: BNDCSR */ 1316 typedef union XSaveBNDCSR { 1317 BNDCSReg bndcsr; 1318 uint8_t data[64]; 1319 } XSaveBNDCSR; 1320 1321 /* Ext. save area 5: Opmask */ 1322 typedef struct XSaveOpmask { 1323 uint64_t opmask_regs[NB_OPMASK_REGS]; 1324 } XSaveOpmask; 1325 1326 /* Ext. save area 6: ZMM_Hi256 */ 1327 typedef struct XSaveZMM_Hi256 { 1328 uint8_t zmm_hi256[16][32]; 1329 } XSaveZMM_Hi256; 1330 1331 /* Ext. save area 7: Hi16_ZMM */ 1332 typedef struct XSaveHi16_ZMM { 1333 uint8_t hi16_zmm[16][64]; 1334 } XSaveHi16_ZMM; 1335 1336 /* Ext. save area 9: PKRU state */ 1337 typedef struct XSavePKRU { 1338 uint32_t pkru; 1339 uint32_t padding; 1340 } XSavePKRU; 1341 1342 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1343 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1344 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1345 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1346 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1347 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1348 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1349 1350 typedef struct ExtSaveArea { 1351 uint32_t feature, bits; 1352 uint32_t offset, size; 1353 } ExtSaveArea; 1354 1355 #define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) 1356 1357 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; 1358 1359 typedef enum TPRAccess { 1360 TPR_ACCESS_READ, 1361 TPR_ACCESS_WRITE, 1362 } TPRAccess; 1363 1364 /* Cache information data structures: */ 1365 1366 enum CacheType { 1367 DATA_CACHE, 1368 INSTRUCTION_CACHE, 1369 UNIFIED_CACHE 1370 }; 1371 1372 typedef struct CPUCacheInfo { 1373 enum CacheType type; 1374 uint8_t level; 1375 /* Size in bytes */ 1376 uint32_t size; 1377 /* Line size, in bytes */ 1378 uint16_t line_size; 1379 /* 1380 * Associativity. 1381 * Note: representation of fully-associative caches is not implemented 1382 */ 1383 uint8_t associativity; 1384 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1385 uint8_t partitions; 1386 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1387 uint32_t sets; 1388 /* 1389 * Lines per tag. 1390 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1391 * (Is this synonym to @partitions?) 1392 */ 1393 uint8_t lines_per_tag; 1394 1395 /* Self-initializing cache */ 1396 bool self_init; 1397 /* 1398 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1399 * non-originating threads sharing this cache. 1400 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1401 */ 1402 bool no_invd_sharing; 1403 /* 1404 * Cache is inclusive of lower cache levels. 1405 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1406 */ 1407 bool inclusive; 1408 /* 1409 * A complex function is used to index the cache, potentially using all 1410 * address bits. CPUID[4].EDX[bit 2]. 1411 */ 1412 bool complex_indexing; 1413 } CPUCacheInfo; 1414 1415 1416 typedef struct CPUCaches { 1417 CPUCacheInfo *l1d_cache; 1418 CPUCacheInfo *l1i_cache; 1419 CPUCacheInfo *l2_cache; 1420 CPUCacheInfo *l3_cache; 1421 } CPUCaches; 1422 1423 typedef struct HVFX86LazyFlags { 1424 target_ulong result; 1425 target_ulong auxbits; 1426 } HVFX86LazyFlags; 1427 1428 typedef struct CPUX86State { 1429 /* standard registers */ 1430 target_ulong regs[CPU_NB_REGS]; 1431 target_ulong eip; 1432 target_ulong eflags; /* eflags register. During CPU emulation, CC 1433 flags and DF are set to zero because they are 1434 stored elsewhere */ 1435 1436 /* emulator internal eflags handling */ 1437 target_ulong cc_dst; 1438 target_ulong cc_src; 1439 target_ulong cc_src2; 1440 uint32_t cc_op; 1441 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1442 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1443 are known at translation time. */ 1444 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1445 1446 /* segments */ 1447 SegmentCache segs[6]; /* selector values */ 1448 SegmentCache ldt; 1449 SegmentCache tr; 1450 SegmentCache gdt; /* only base and limit are used */ 1451 SegmentCache idt; /* only base and limit are used */ 1452 1453 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1454 int32_t a20_mask; 1455 1456 BNDReg bnd_regs[4]; 1457 BNDCSReg bndcs_regs; 1458 uint64_t msr_bndcfgs; 1459 uint64_t efer; 1460 1461 /* Beginning of state preserved by INIT (dummy marker). */ 1462 struct {} start_init_save; 1463 1464 /* FPU state */ 1465 unsigned int fpstt; /* top of stack index */ 1466 uint16_t fpus; 1467 uint16_t fpuc; 1468 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1469 FPReg fpregs[8]; 1470 /* KVM-only so far */ 1471 uint16_t fpop; 1472 uint16_t fpcs; 1473 uint16_t fpds; 1474 uint64_t fpip; 1475 uint64_t fpdp; 1476 1477 /* emulator internal variables */ 1478 float_status fp_status; 1479 floatx80 ft0; 1480 1481 float_status mmx_status; /* for 3DNow! float ops */ 1482 float_status sse_status; 1483 uint32_t mxcsr; 1484 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1485 ZMMReg xmm_t0; 1486 MMXReg mmx_t0; 1487 1488 XMMReg ymmh_regs[CPU_NB_REGS]; 1489 1490 uint64_t opmask_regs[NB_OPMASK_REGS]; 1491 YMMReg zmmh_regs[CPU_NB_REGS]; 1492 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1493 1494 /* sysenter registers */ 1495 uint32_t sysenter_cs; 1496 target_ulong sysenter_esp; 1497 target_ulong sysenter_eip; 1498 uint64_t star; 1499 1500 uint64_t vm_hsave; 1501 1502 #ifdef TARGET_X86_64 1503 target_ulong lstar; 1504 target_ulong cstar; 1505 target_ulong fmask; 1506 target_ulong kernelgsbase; 1507 #endif 1508 1509 uint64_t tsc; 1510 uint64_t tsc_adjust; 1511 uint64_t tsc_deadline; 1512 uint64_t tsc_aux; 1513 1514 uint64_t xcr0; 1515 1516 uint64_t mcg_status; 1517 uint64_t msr_ia32_misc_enable; 1518 uint64_t msr_ia32_feature_control; 1519 uint64_t msr_ia32_sgxlepubkeyhash[4]; 1520 1521 uint64_t msr_fixed_ctr_ctrl; 1522 uint64_t msr_global_ctrl; 1523 uint64_t msr_global_status; 1524 uint64_t msr_global_ovf_ctrl; 1525 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1526 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1527 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1528 1529 uint64_t pat; 1530 uint32_t smbase; 1531 uint64_t msr_smi_count; 1532 1533 uint32_t pkru; 1534 uint32_t pkrs; 1535 uint32_t tsx_ctrl; 1536 1537 uint64_t spec_ctrl; 1538 uint64_t virt_ssbd; 1539 1540 /* End of state preserved by INIT (dummy marker). */ 1541 struct {} end_init_save; 1542 1543 uint64_t system_time_msr; 1544 uint64_t wall_clock_msr; 1545 uint64_t steal_time_msr; 1546 uint64_t async_pf_en_msr; 1547 uint64_t async_pf_int_msr; 1548 uint64_t pv_eoi_en_msr; 1549 uint64_t poll_control_msr; 1550 1551 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1552 uint64_t msr_hv_hypercall; 1553 uint64_t msr_hv_guest_os_id; 1554 uint64_t msr_hv_tsc; 1555 1556 /* Per-VCPU HV MSRs */ 1557 uint64_t msr_hv_vapic; 1558 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1559 uint64_t msr_hv_runtime; 1560 uint64_t msr_hv_synic_control; 1561 uint64_t msr_hv_synic_evt_page; 1562 uint64_t msr_hv_synic_msg_page; 1563 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1564 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1565 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1566 uint64_t msr_hv_reenlightenment_control; 1567 uint64_t msr_hv_tsc_emulation_control; 1568 uint64_t msr_hv_tsc_emulation_status; 1569 1570 uint64_t msr_rtit_ctrl; 1571 uint64_t msr_rtit_status; 1572 uint64_t msr_rtit_output_base; 1573 uint64_t msr_rtit_output_mask; 1574 uint64_t msr_rtit_cr3_match; 1575 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1576 1577 /* exception/interrupt handling */ 1578 int error_code; 1579 int exception_is_int; 1580 target_ulong exception_next_eip; 1581 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1582 union { 1583 struct CPUBreakpoint *cpu_breakpoint[4]; 1584 struct CPUWatchpoint *cpu_watchpoint[4]; 1585 }; /* break/watchpoints for dr[0..3] */ 1586 int old_exception; /* exception in flight */ 1587 1588 uint64_t vm_vmcb; 1589 uint64_t tsc_offset; 1590 uint64_t intercept; 1591 uint16_t intercept_cr_read; 1592 uint16_t intercept_cr_write; 1593 uint16_t intercept_dr_read; 1594 uint16_t intercept_dr_write; 1595 uint32_t intercept_exceptions; 1596 uint64_t nested_cr3; 1597 uint32_t nested_pg_mode; 1598 uint8_t v_tpr; 1599 uint32_t int_ctl; 1600 1601 /* KVM states, automatically cleared on reset */ 1602 uint8_t nmi_injected; 1603 uint8_t nmi_pending; 1604 1605 uintptr_t retaddr; 1606 1607 /* Fields up to this point are cleared by a CPU reset */ 1608 struct {} end_reset_fields; 1609 1610 /* Fields after this point are preserved across CPU reset. */ 1611 1612 /* processor features (e.g. for CPUID insn) */ 1613 /* Minimum cpuid leaf 7 value */ 1614 uint32_t cpuid_level_func7; 1615 /* Actual cpuid leaf 7 value */ 1616 uint32_t cpuid_min_level_func7; 1617 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1618 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1619 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1620 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1621 /* Actual level/xlevel/xlevel2 value: */ 1622 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1623 uint32_t cpuid_vendor1; 1624 uint32_t cpuid_vendor2; 1625 uint32_t cpuid_vendor3; 1626 uint32_t cpuid_version; 1627 FeatureWordArray features; 1628 /* Features that were explicitly enabled/disabled */ 1629 FeatureWordArray user_features; 1630 uint32_t cpuid_model[12]; 1631 /* Cache information for CPUID. When legacy-cache=on, the cache data 1632 * on each CPUID leaf will be different, because we keep compatibility 1633 * with old QEMU versions. 1634 */ 1635 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1636 1637 /* MTRRs */ 1638 uint64_t mtrr_fixed[11]; 1639 uint64_t mtrr_deftype; 1640 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1641 1642 /* For KVM */ 1643 uint32_t mp_state; 1644 int32_t exception_nr; 1645 int32_t interrupt_injected; 1646 uint8_t soft_interrupt; 1647 uint8_t exception_pending; 1648 uint8_t exception_injected; 1649 uint8_t has_error_code; 1650 uint8_t exception_has_payload; 1651 uint64_t exception_payload; 1652 uint32_t ins_len; 1653 uint32_t sipi_vector; 1654 bool tsc_valid; 1655 int64_t tsc_khz; 1656 int64_t user_tsc_khz; /* for sanity check only */ 1657 uint64_t apic_bus_freq; 1658 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1659 void *xsave_buf; 1660 uint32_t xsave_buf_len; 1661 #endif 1662 #if defined(CONFIG_KVM) 1663 struct kvm_nested_state *nested_state; 1664 #endif 1665 #if defined(CONFIG_HVF) 1666 HVFX86LazyFlags hvf_lflags; 1667 void *hvf_mmio_buf; 1668 #endif 1669 1670 uint64_t mcg_cap; 1671 uint64_t mcg_ctl; 1672 uint64_t mcg_ext_ctl; 1673 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1674 uint64_t xstate_bv; 1675 1676 /* vmstate */ 1677 uint16_t fpus_vmstate; 1678 uint16_t fptag_vmstate; 1679 uint16_t fpregs_format_vmstate; 1680 1681 uint64_t xss; 1682 uint32_t umwait; 1683 1684 TPRAccess tpr_access_type; 1685 1686 unsigned nr_dies; 1687 } CPUX86State; 1688 1689 struct kvm_msrs; 1690 1691 /** 1692 * X86CPU: 1693 * @env: #CPUX86State 1694 * @migratable: If set, only migratable flags will be accepted when "enforce" 1695 * mode is used, and only migratable flags will be included in the "host" 1696 * CPU model. 1697 * 1698 * An x86 CPU. 1699 */ 1700 struct X86CPU { 1701 /*< private >*/ 1702 CPUState parent_obj; 1703 /*< public >*/ 1704 1705 CPUNegativeOffsetState neg; 1706 CPUX86State env; 1707 VMChangeStateEntry *vmsentry; 1708 1709 uint64_t ucode_rev; 1710 1711 uint32_t hyperv_spinlock_attempts; 1712 char *hyperv_vendor; 1713 bool hyperv_synic_kvm_only; 1714 uint64_t hyperv_features; 1715 bool hyperv_passthrough; 1716 OnOffAuto hyperv_no_nonarch_cs; 1717 uint32_t hyperv_vendor_id[3]; 1718 uint32_t hyperv_interface_id[4]; 1719 uint32_t hyperv_version_id[4]; 1720 uint32_t hyperv_limits[3]; 1721 uint32_t hyperv_nested[4]; 1722 1723 bool check_cpuid; 1724 bool enforce_cpuid; 1725 /* 1726 * Force features to be enabled even if the host doesn't support them. 1727 * This is dangerous and should be done only for testing CPUID 1728 * compatibility. 1729 */ 1730 bool force_features; 1731 bool expose_kvm; 1732 bool expose_tcg; 1733 bool migratable; 1734 bool migrate_smi_count; 1735 bool max_features; /* Enable all supported features automatically */ 1736 uint32_t apic_id; 1737 1738 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1739 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1740 bool vmware_cpuid_freq; 1741 1742 /* if true the CPUID code directly forward host cache leaves to the guest */ 1743 bool cache_info_passthrough; 1744 1745 /* if true the CPUID code directly forwards 1746 * host monitor/mwait leaves to the guest */ 1747 struct { 1748 uint32_t eax; 1749 uint32_t ebx; 1750 uint32_t ecx; 1751 uint32_t edx; 1752 } mwait; 1753 1754 /* Features that were filtered out because of missing host capabilities */ 1755 FeatureWordArray filtered_features; 1756 1757 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1758 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1759 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1760 * capabilities) directly to the guest. 1761 */ 1762 bool enable_pmu; 1763 1764 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1765 * disabled by default to avoid breaking migration between QEMU with 1766 * different LMCE configurations. 1767 */ 1768 bool enable_lmce; 1769 1770 /* Compatibility bits for old machine types. 1771 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1772 * socket share an virtual l3 cache. 1773 */ 1774 bool enable_l3_cache; 1775 1776 /* Compatibility bits for old machine types. 1777 * If true present the old cache topology information 1778 */ 1779 bool legacy_cache; 1780 1781 /* Compatibility bits for old machine types: */ 1782 bool enable_cpuid_0xb; 1783 1784 /* Enable auto level-increase for all CPUID leaves */ 1785 bool full_cpuid_auto_level; 1786 1787 /* Only advertise CPUID leaves defined by the vendor */ 1788 bool vendor_cpuid_only; 1789 1790 /* Enable auto level-increase for Intel Processor Trace leave */ 1791 bool intel_pt_auto_level; 1792 1793 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1794 bool fill_mtrr_mask; 1795 1796 /* if true override the phys_bits value with a value read from the host */ 1797 bool host_phys_bits; 1798 1799 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1800 uint8_t host_phys_bits_limit; 1801 1802 /* Stop SMI delivery for migration compatibility with old machines */ 1803 bool kvm_no_smi_migration; 1804 1805 /* Number of physical address bits supported */ 1806 uint32_t phys_bits; 1807 1808 /* in order to simplify APIC support, we leave this pointer to the 1809 user */ 1810 struct DeviceState *apic_state; 1811 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1812 Notifier machine_done; 1813 1814 struct kvm_msrs *kvm_msr_buf; 1815 1816 int32_t node_id; /* NUMA node this CPU belongs to */ 1817 int32_t socket_id; 1818 int32_t die_id; 1819 int32_t core_id; 1820 int32_t thread_id; 1821 1822 int32_t hv_max_vps; 1823 }; 1824 1825 1826 #ifndef CONFIG_USER_ONLY 1827 extern const VMStateDescription vmstate_x86_cpu; 1828 #endif 1829 1830 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1831 1832 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1833 int cpuid, void *opaque); 1834 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1835 int cpuid, void *opaque); 1836 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1837 void *opaque); 1838 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1839 void *opaque); 1840 1841 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1842 Error **errp); 1843 1844 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1845 1846 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1847 MemTxAttrs *attrs); 1848 1849 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1850 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1851 1852 void x86_cpu_list(void); 1853 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1854 1855 #ifndef CONFIG_USER_ONLY 1856 int cpu_get_pic_interrupt(CPUX86State *s); 1857 1858 /* MSDOS compatibility mode FPU exception support */ 1859 void x86_register_ferr_irq(qemu_irq irq); 1860 void fpu_check_raise_ferr_irq(CPUX86State *s); 1861 void cpu_set_ignne(void); 1862 void cpu_clear_ignne(void); 1863 #endif 1864 1865 /* mpx_helper.c */ 1866 void cpu_sync_bndcs_hflags(CPUX86State *env); 1867 1868 /* this function must always be used to load data in the segment 1869 cache: it synchronizes the hflags with the segment cache values */ 1870 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1871 X86Seg seg_reg, unsigned int selector, 1872 target_ulong base, 1873 unsigned int limit, 1874 unsigned int flags) 1875 { 1876 SegmentCache *sc; 1877 unsigned int new_hflags; 1878 1879 sc = &env->segs[seg_reg]; 1880 sc->selector = selector; 1881 sc->base = base; 1882 sc->limit = limit; 1883 sc->flags = flags; 1884 1885 /* update the hidden flags */ 1886 { 1887 if (seg_reg == R_CS) { 1888 #ifdef TARGET_X86_64 1889 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1890 /* long mode */ 1891 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1892 env->hflags &= ~(HF_ADDSEG_MASK); 1893 } else 1894 #endif 1895 { 1896 /* legacy / compatibility case */ 1897 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1898 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1899 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1900 new_hflags; 1901 } 1902 } 1903 if (seg_reg == R_SS) { 1904 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1905 #if HF_CPL_MASK != 3 1906 #error HF_CPL_MASK is hardcoded 1907 #endif 1908 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1909 /* Possibly switch between BNDCFGS and BNDCFGU */ 1910 cpu_sync_bndcs_hflags(env); 1911 } 1912 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1913 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1914 if (env->hflags & HF_CS64_MASK) { 1915 /* zero base assumed for DS, ES and SS in long mode */ 1916 } else if (!(env->cr[0] & CR0_PE_MASK) || 1917 (env->eflags & VM_MASK) || 1918 !(env->hflags & HF_CS32_MASK)) { 1919 /* XXX: try to avoid this test. The problem comes from the 1920 fact that is real mode or vm86 mode we only modify the 1921 'base' and 'selector' fields of the segment cache to go 1922 faster. A solution may be to force addseg to one in 1923 translate-i386.c. */ 1924 new_hflags |= HF_ADDSEG_MASK; 1925 } else { 1926 new_hflags |= ((env->segs[R_DS].base | 1927 env->segs[R_ES].base | 1928 env->segs[R_SS].base) != 0) << 1929 HF_ADDSEG_SHIFT; 1930 } 1931 env->hflags = (env->hflags & 1932 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1933 } 1934 } 1935 1936 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1937 uint8_t sipi_vector) 1938 { 1939 CPUState *cs = CPU(cpu); 1940 CPUX86State *env = &cpu->env; 1941 1942 env->eip = 0; 1943 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1944 sipi_vector << 12, 1945 env->segs[R_CS].limit, 1946 env->segs[R_CS].flags); 1947 cs->halted = 0; 1948 } 1949 1950 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1951 target_ulong *base, unsigned int *limit, 1952 unsigned int *flags); 1953 1954 /* op_helper.c */ 1955 /* used for debug or cpu save/restore */ 1956 1957 /* cpu-exec.c */ 1958 /* the following helpers are only usable in user mode simulation as 1959 they can trigger unexpected exceptions */ 1960 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); 1961 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1962 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1963 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1964 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1965 1966 /* cpu.c */ 1967 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 1968 uint32_t vendor2, uint32_t vendor3); 1969 typedef struct PropValue { 1970 const char *prop, *value; 1971 } PropValue; 1972 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); 1973 1974 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env); 1975 1976 /* cpu.c other functions (cpuid) */ 1977 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1978 uint32_t *eax, uint32_t *ebx, 1979 uint32_t *ecx, uint32_t *edx); 1980 void cpu_clear_apic_feature(CPUX86State *env); 1981 void host_cpuid(uint32_t function, uint32_t count, 1982 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1983 1984 /* helper.c */ 1985 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1986 1987 #ifndef CONFIG_USER_ONLY 1988 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1989 { 1990 return !!attrs.secure; 1991 } 1992 1993 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1994 { 1995 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1996 } 1997 1998 /* 1999 * load efer and update the corresponding hflags. XXX: do consistency 2000 * checks with cpuid bits? 2001 */ 2002 void cpu_load_efer(CPUX86State *env, uint64_t val); 2003 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 2004 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 2005 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 2006 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 2007 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 2008 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 2009 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 2010 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 2011 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 2012 #endif 2013 2014 /* will be suppressed */ 2015 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 2016 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 2017 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 2018 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 2019 2020 /* hw/pc.c */ 2021 uint64_t cpu_get_tsc(CPUX86State *env); 2022 2023 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 2024 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 2025 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 2026 2027 #ifdef TARGET_X86_64 2028 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 2029 #else 2030 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 2031 #endif 2032 2033 #define cpu_list x86_cpu_list 2034 2035 /* MMU modes definitions */ 2036 #define MMU_KSMAP_IDX 0 2037 #define MMU_USER_IDX 1 2038 #define MMU_KNOSMAP_IDX 2 2039 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 2040 { 2041 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 2042 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 2043 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2044 } 2045 2046 static inline int cpu_mmu_index_kernel(CPUX86State *env) 2047 { 2048 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 2049 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 2050 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2051 } 2052 2053 #define CC_DST (env->cc_dst) 2054 #define CC_SRC (env->cc_src) 2055 #define CC_SRC2 (env->cc_src2) 2056 #define CC_OP (env->cc_op) 2057 2058 typedef CPUX86State CPUArchState; 2059 typedef X86CPU ArchCPU; 2060 2061 #include "exec/cpu-all.h" 2062 #include "svm.h" 2063 2064 #if !defined(CONFIG_USER_ONLY) 2065 #include "hw/i386/apic.h" 2066 #endif 2067 2068 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2069 target_ulong *cs_base, uint32_t *flags) 2070 { 2071 *cs_base = env->segs[R_CS].base; 2072 *pc = *cs_base + env->eip; 2073 *flags = env->hflags | 2074 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2075 } 2076 2077 void do_cpu_init(X86CPU *cpu); 2078 void do_cpu_sipi(X86CPU *cpu); 2079 2080 #define MCE_INJECT_BROADCAST 1 2081 #define MCE_INJECT_UNCOND_AO 2 2082 2083 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2084 uint64_t status, uint64_t mcg_status, uint64_t addr, 2085 uint64_t misc, int flags); 2086 2087 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2088 2089 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2090 { 2091 uint32_t eflags = env->eflags; 2092 if (tcg_enabled()) { 2093 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 2094 } 2095 return eflags; 2096 } 2097 2098 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2099 { 2100 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2101 } 2102 2103 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2104 { 2105 if (env->hflags & HF_SMM_MASK) { 2106 return -1; 2107 } else { 2108 return env->a20_mask; 2109 } 2110 } 2111 2112 static inline bool cpu_has_vmx(CPUX86State *env) 2113 { 2114 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2115 } 2116 2117 static inline bool cpu_has_svm(CPUX86State *env) 2118 { 2119 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2120 } 2121 2122 /* 2123 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2124 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2125 * VMX operation. This is because CR4.VMXE is one of the bits set 2126 * in MSR_IA32_VMX_CR4_FIXED1. 2127 * 2128 * There is one exception to above statement when vCPU enters SMM mode. 2129 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2130 * may also reset CR4.VMXE during execution in SMM mode. 2131 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2132 * and CR4.VMXE is restored to it's original value of being set. 2133 * 2134 * Therefore, when vCPU is not in SMM mode, we can infer whether 2135 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2136 * know for certain. 2137 */ 2138 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2139 { 2140 return cpu_has_vmx(env) && 2141 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2142 } 2143 2144 /* excp_helper.c */ 2145 int get_pg_mode(CPUX86State *env); 2146 2147 /* fpu_helper.c */ 2148 void update_fp_status(CPUX86State *env); 2149 void update_mxcsr_status(CPUX86State *env); 2150 void update_mxcsr_from_sse_status(CPUX86State *env); 2151 2152 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2153 { 2154 env->mxcsr = mxcsr; 2155 if (tcg_enabled()) { 2156 update_mxcsr_status(env); 2157 } 2158 } 2159 2160 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2161 { 2162 env->fpuc = fpuc; 2163 if (tcg_enabled()) { 2164 update_fp_status(env); 2165 } 2166 } 2167 2168 /* mem_helper.c */ 2169 void helper_lock_init(void); 2170 2171 /* svm_helper.c */ 2172 #ifdef CONFIG_USER_ONLY 2173 static inline void 2174 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2175 uint64_t param, uintptr_t retaddr) 2176 { /* no-op */ } 2177 static inline bool 2178 cpu_svm_has_intercept(CPUX86State *env, uint32_t type) 2179 { return false; } 2180 #else 2181 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2182 uint64_t param, uintptr_t retaddr); 2183 bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); 2184 #endif 2185 2186 /* apic.c */ 2187 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2188 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2189 TPRAccess access); 2190 2191 /* Special values for X86CPUVersion: */ 2192 2193 /* Resolve to latest CPU version */ 2194 #define CPU_VERSION_LATEST -1 2195 2196 /* 2197 * Resolve to version defined by current machine type. 2198 * See x86_cpu_set_default_version() 2199 */ 2200 #define CPU_VERSION_AUTO -2 2201 2202 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2203 #define CPU_VERSION_LEGACY 0 2204 2205 typedef int X86CPUVersion; 2206 2207 /* 2208 * Set default CPU model version for CPU models having 2209 * version == CPU_VERSION_AUTO. 2210 */ 2211 void x86_cpu_set_default_version(X86CPUVersion version); 2212 2213 #define APIC_DEFAULT_ADDRESS 0xfee00000 2214 #define APIC_SPACE_SIZE 0x100000 2215 2216 /* cpu-dump.c */ 2217 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2218 2219 /* cpu.c */ 2220 bool cpu_is_bsp(X86CPU *cpu); 2221 2222 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen); 2223 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); 2224 void x86_update_hflags(CPUX86State* env); 2225 2226 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2227 { 2228 return !!(cpu->hyperv_features & BIT(feat)); 2229 } 2230 2231 static inline uint64_t cr4_reserved_bits(CPUX86State *env) 2232 { 2233 uint64_t reserved_bits = CR4_RESERVED_MASK; 2234 if (!env->features[FEAT_XSAVE]) { 2235 reserved_bits |= CR4_OSXSAVE_MASK; 2236 } 2237 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) { 2238 reserved_bits |= CR4_SMEP_MASK; 2239 } 2240 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { 2241 reserved_bits |= CR4_SMAP_MASK; 2242 } 2243 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) { 2244 reserved_bits |= CR4_FSGSBASE_MASK; 2245 } 2246 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { 2247 reserved_bits |= CR4_PKE_MASK; 2248 } 2249 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) { 2250 reserved_bits |= CR4_LA57_MASK; 2251 } 2252 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { 2253 reserved_bits |= CR4_UMIP_MASK; 2254 } 2255 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { 2256 reserved_bits |= CR4_PKS_MASK; 2257 } 2258 return reserved_bits; 2259 } 2260 2261 static inline bool ctl_has_irq(CPUX86State *env) 2262 { 2263 uint32_t int_prio; 2264 uint32_t tpr; 2265 2266 int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; 2267 tpr = env->int_ctl & V_TPR_MASK; 2268 2269 if (env->int_ctl & V_IGN_TPR_MASK) { 2270 return (env->int_ctl & V_IRQ_MASK); 2271 } 2272 2273 return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr); 2274 } 2275 2276 hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, 2277 int *prot); 2278 #if defined(TARGET_X86_64) && \ 2279 defined(CONFIG_USER_ONLY) && \ 2280 defined(CONFIG_LINUX) 2281 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2282 #endif 2283 2284 #endif /* I386_CPU_H */ 2285