1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 #define KVM_HAVE_MCE_INJECTION 1 33 34 /* Maximum instruction code size */ 35 #define TARGET_MAX_INSN_SIZE 16 36 37 /* support for self modifying code even if the modified instruction is 38 close to the modifying instruction */ 39 #define TARGET_HAS_PRECISE_SMC 40 41 #ifdef TARGET_X86_64 42 #define I386_ELF_MACHINE EM_X86_64 43 #define ELF_MACHINE_UNAME "x86_64" 44 #else 45 #define I386_ELF_MACHINE EM_386 46 #define ELF_MACHINE_UNAME "i686" 47 #endif 48 49 enum { 50 R_EAX = 0, 51 R_ECX = 1, 52 R_EDX = 2, 53 R_EBX = 3, 54 R_ESP = 4, 55 R_EBP = 5, 56 R_ESI = 6, 57 R_EDI = 7, 58 R_R8 = 8, 59 R_R9 = 9, 60 R_R10 = 10, 61 R_R11 = 11, 62 R_R12 = 12, 63 R_R13 = 13, 64 R_R14 = 14, 65 R_R15 = 15, 66 67 R_AL = 0, 68 R_CL = 1, 69 R_DL = 2, 70 R_BL = 3, 71 R_AH = 4, 72 R_CH = 5, 73 R_DH = 6, 74 R_BH = 7, 75 }; 76 77 typedef enum X86Seg { 78 R_ES = 0, 79 R_CS = 1, 80 R_SS = 2, 81 R_DS = 3, 82 R_FS = 4, 83 R_GS = 5, 84 R_LDTR = 6, 85 R_TR = 7, 86 } X86Seg; 87 88 /* segment descriptor fields */ 89 #define DESC_G_SHIFT 23 90 #define DESC_G_MASK (1 << DESC_G_SHIFT) 91 #define DESC_B_SHIFT 22 92 #define DESC_B_MASK (1 << DESC_B_SHIFT) 93 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 94 #define DESC_L_MASK (1 << DESC_L_SHIFT) 95 #define DESC_AVL_SHIFT 20 96 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 97 #define DESC_P_SHIFT 15 98 #define DESC_P_MASK (1 << DESC_P_SHIFT) 99 #define DESC_DPL_SHIFT 13 100 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 101 #define DESC_S_SHIFT 12 102 #define DESC_S_MASK (1 << DESC_S_SHIFT) 103 #define DESC_TYPE_SHIFT 8 104 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 105 #define DESC_A_MASK (1 << 8) 106 107 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 108 #define DESC_C_MASK (1 << 10) /* code: conforming */ 109 #define DESC_R_MASK (1 << 9) /* code: readable */ 110 111 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 112 #define DESC_W_MASK (1 << 9) /* data: writable */ 113 114 #define DESC_TSS_BUSY_MASK (1 << 9) 115 116 /* eflags masks */ 117 #define CC_C 0x0001 118 #define CC_P 0x0004 119 #define CC_A 0x0010 120 #define CC_Z 0x0040 121 #define CC_S 0x0080 122 #define CC_O 0x0800 123 124 #define TF_SHIFT 8 125 #define IOPL_SHIFT 12 126 #define VM_SHIFT 17 127 128 #define TF_MASK 0x00000100 129 #define IF_MASK 0x00000200 130 #define DF_MASK 0x00000400 131 #define IOPL_MASK 0x00003000 132 #define NT_MASK 0x00004000 133 #define RF_MASK 0x00010000 134 #define VM_MASK 0x00020000 135 #define AC_MASK 0x00040000 136 #define VIF_MASK 0x00080000 137 #define VIP_MASK 0x00100000 138 #define ID_MASK 0x00200000 139 140 /* hidden flags - used internally by qemu to represent additional cpu 141 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 142 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 143 positions to ease oring with eflags. */ 144 /* current cpl */ 145 #define HF_CPL_SHIFT 0 146 /* true if hardware interrupts must be disabled for next instruction */ 147 #define HF_INHIBIT_IRQ_SHIFT 3 148 /* 16 or 32 segments */ 149 #define HF_CS32_SHIFT 4 150 #define HF_SS32_SHIFT 5 151 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 152 #define HF_ADDSEG_SHIFT 6 153 /* copy of CR0.PE (protected mode) */ 154 #define HF_PE_SHIFT 7 155 #define HF_TF_SHIFT 8 /* must be same as eflags */ 156 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 157 #define HF_EM_SHIFT 10 158 #define HF_TS_SHIFT 11 159 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 160 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 161 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 162 #define HF_RF_SHIFT 16 /* must be same as eflags */ 163 #define HF_VM_SHIFT 17 /* must be same as eflags */ 164 #define HF_AC_SHIFT 18 /* must be same as eflags */ 165 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 166 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 167 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 168 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 169 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 170 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 171 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 172 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 173 174 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 175 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 176 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 177 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 178 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 179 #define HF_PE_MASK (1 << HF_PE_SHIFT) 180 #define HF_TF_MASK (1 << HF_TF_SHIFT) 181 #define HF_MP_MASK (1 << HF_MP_SHIFT) 182 #define HF_EM_MASK (1 << HF_EM_SHIFT) 183 #define HF_TS_MASK (1 << HF_TS_SHIFT) 184 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 185 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 186 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 187 #define HF_RF_MASK (1 << HF_RF_SHIFT) 188 #define HF_VM_MASK (1 << HF_VM_SHIFT) 189 #define HF_AC_MASK (1 << HF_AC_SHIFT) 190 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 191 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 192 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 193 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 194 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 195 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 196 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 197 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 198 199 /* hflags2 */ 200 201 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 202 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 203 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 204 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 205 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 206 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 207 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 208 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 209 210 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 211 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 212 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 213 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 214 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 215 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 216 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 217 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 218 219 #define CR0_PE_SHIFT 0 220 #define CR0_MP_SHIFT 1 221 222 #define CR0_PE_MASK (1U << 0) 223 #define CR0_MP_MASK (1U << 1) 224 #define CR0_EM_MASK (1U << 2) 225 #define CR0_TS_MASK (1U << 3) 226 #define CR0_ET_MASK (1U << 4) 227 #define CR0_NE_MASK (1U << 5) 228 #define CR0_WP_MASK (1U << 16) 229 #define CR0_AM_MASK (1U << 18) 230 #define CR0_PG_MASK (1U << 31) 231 232 #define CR4_VME_MASK (1U << 0) 233 #define CR4_PVI_MASK (1U << 1) 234 #define CR4_TSD_MASK (1U << 2) 235 #define CR4_DE_MASK (1U << 3) 236 #define CR4_PSE_MASK (1U << 4) 237 #define CR4_PAE_MASK (1U << 5) 238 #define CR4_MCE_MASK (1U << 6) 239 #define CR4_PGE_MASK (1U << 7) 240 #define CR4_PCE_MASK (1U << 8) 241 #define CR4_OSFXSR_SHIFT 9 242 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 243 #define CR4_OSXMMEXCPT_MASK (1U << 10) 244 #define CR4_LA57_MASK (1U << 12) 245 #define CR4_VMXE_MASK (1U << 13) 246 #define CR4_SMXE_MASK (1U << 14) 247 #define CR4_FSGSBASE_MASK (1U << 16) 248 #define CR4_PCIDE_MASK (1U << 17) 249 #define CR4_OSXSAVE_MASK (1U << 18) 250 #define CR4_SMEP_MASK (1U << 20) 251 #define CR4_SMAP_MASK (1U << 21) 252 #define CR4_PKE_MASK (1U << 22) 253 254 #define DR6_BD (1 << 13) 255 #define DR6_BS (1 << 14) 256 #define DR6_BT (1 << 15) 257 #define DR6_FIXED_1 0xffff0ff0 258 259 #define DR7_GD (1 << 13) 260 #define DR7_TYPE_SHIFT 16 261 #define DR7_LEN_SHIFT 18 262 #define DR7_FIXED_1 0x00000400 263 #define DR7_GLOBAL_BP_MASK 0xaa 264 #define DR7_LOCAL_BP_MASK 0x55 265 #define DR7_MAX_BP 4 266 #define DR7_TYPE_BP_INST 0x0 267 #define DR7_TYPE_DATA_WR 0x1 268 #define DR7_TYPE_IO_RW 0x2 269 #define DR7_TYPE_DATA_RW 0x3 270 271 #define PG_PRESENT_BIT 0 272 #define PG_RW_BIT 1 273 #define PG_USER_BIT 2 274 #define PG_PWT_BIT 3 275 #define PG_PCD_BIT 4 276 #define PG_ACCESSED_BIT 5 277 #define PG_DIRTY_BIT 6 278 #define PG_PSE_BIT 7 279 #define PG_GLOBAL_BIT 8 280 #define PG_PSE_PAT_BIT 12 281 #define PG_PKRU_BIT 59 282 #define PG_NX_BIT 63 283 284 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 285 #define PG_RW_MASK (1 << PG_RW_BIT) 286 #define PG_USER_MASK (1 << PG_USER_BIT) 287 #define PG_PWT_MASK (1 << PG_PWT_BIT) 288 #define PG_PCD_MASK (1 << PG_PCD_BIT) 289 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 290 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 291 #define PG_PSE_MASK (1 << PG_PSE_BIT) 292 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 293 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 294 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 295 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 296 #define PG_HI_USER_MASK 0x7ff0000000000000LL 297 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 298 #define PG_NX_MASK (1ULL << PG_NX_BIT) 299 300 #define PG_ERROR_W_BIT 1 301 302 #define PG_ERROR_P_MASK 0x01 303 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 304 #define PG_ERROR_U_MASK 0x04 305 #define PG_ERROR_RSVD_MASK 0x08 306 #define PG_ERROR_I_D_MASK 0x10 307 #define PG_ERROR_PK_MASK 0x20 308 309 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 310 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 311 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 312 313 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 314 #define MCE_BANKS_DEF 10 315 316 #define MCG_CAP_BANKS_MASK 0xff 317 318 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 319 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 320 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 321 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 322 323 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 324 325 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 326 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 327 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 328 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 329 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 330 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 331 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 332 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 333 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 334 335 /* MISC register defines */ 336 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 337 #define MCM_ADDR_LINEAR 1 /* linear address */ 338 #define MCM_ADDR_PHYS 2 /* physical address */ 339 #define MCM_ADDR_MEM 3 /* memory address */ 340 #define MCM_ADDR_GENERIC 7 /* generic */ 341 342 #define MSR_IA32_TSC 0x10 343 #define MSR_IA32_APICBASE 0x1b 344 #define MSR_IA32_APICBASE_BSP (1<<8) 345 #define MSR_IA32_APICBASE_ENABLE (1<<11) 346 #define MSR_IA32_APICBASE_EXTD (1 << 10) 347 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 348 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 349 #define MSR_TSC_ADJUST 0x0000003b 350 #define MSR_IA32_SPEC_CTRL 0x48 351 #define MSR_VIRT_SSBD 0xc001011f 352 #define MSR_IA32_PRED_CMD 0x49 353 #define MSR_IA32_UCODE_REV 0x8b 354 #define MSR_IA32_CORE_CAPABILITY 0xcf 355 356 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 357 #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 358 359 #define MSR_IA32_PERF_CAPABILITIES 0x345 360 361 #define MSR_IA32_TSX_CTRL 0x122 362 #define MSR_IA32_TSCDEADLINE 0x6e0 363 364 #define FEATURE_CONTROL_LOCKED (1<<0) 365 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 366 #define FEATURE_CONTROL_LMCE (1<<20) 367 368 #define MSR_P6_PERFCTR0 0xc1 369 370 #define MSR_IA32_SMBASE 0x9e 371 #define MSR_SMI_COUNT 0x34 372 #define MSR_MTRRcap 0xfe 373 #define MSR_MTRRcap_VCNT 8 374 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 375 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 376 377 #define MSR_IA32_SYSENTER_CS 0x174 378 #define MSR_IA32_SYSENTER_ESP 0x175 379 #define MSR_IA32_SYSENTER_EIP 0x176 380 381 #define MSR_MCG_CAP 0x179 382 #define MSR_MCG_STATUS 0x17a 383 #define MSR_MCG_CTL 0x17b 384 #define MSR_MCG_EXT_CTL 0x4d0 385 386 #define MSR_P6_EVNTSEL0 0x186 387 388 #define MSR_IA32_PERF_STATUS 0x198 389 390 #define MSR_IA32_MISC_ENABLE 0x1a0 391 /* Indicates good rep/movs microcode on some processors: */ 392 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 393 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 394 395 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 396 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 397 398 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 399 400 #define MSR_MTRRfix64K_00000 0x250 401 #define MSR_MTRRfix16K_80000 0x258 402 #define MSR_MTRRfix16K_A0000 0x259 403 #define MSR_MTRRfix4K_C0000 0x268 404 #define MSR_MTRRfix4K_C8000 0x269 405 #define MSR_MTRRfix4K_D0000 0x26a 406 #define MSR_MTRRfix4K_D8000 0x26b 407 #define MSR_MTRRfix4K_E0000 0x26c 408 #define MSR_MTRRfix4K_E8000 0x26d 409 #define MSR_MTRRfix4K_F0000 0x26e 410 #define MSR_MTRRfix4K_F8000 0x26f 411 412 #define MSR_PAT 0x277 413 414 #define MSR_MTRRdefType 0x2ff 415 416 #define MSR_CORE_PERF_FIXED_CTR0 0x309 417 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 418 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 419 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 420 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 421 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 422 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 423 424 #define MSR_MC0_CTL 0x400 425 #define MSR_MC0_STATUS 0x401 426 #define MSR_MC0_ADDR 0x402 427 #define MSR_MC0_MISC 0x403 428 429 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 430 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 431 #define MSR_IA32_RTIT_CTL 0x570 432 #define MSR_IA32_RTIT_STATUS 0x571 433 #define MSR_IA32_RTIT_CR3_MATCH 0x572 434 #define MSR_IA32_RTIT_ADDR0_A 0x580 435 #define MSR_IA32_RTIT_ADDR0_B 0x581 436 #define MSR_IA32_RTIT_ADDR1_A 0x582 437 #define MSR_IA32_RTIT_ADDR1_B 0x583 438 #define MSR_IA32_RTIT_ADDR2_A 0x584 439 #define MSR_IA32_RTIT_ADDR2_B 0x585 440 #define MSR_IA32_RTIT_ADDR3_A 0x586 441 #define MSR_IA32_RTIT_ADDR3_B 0x587 442 #define MAX_RTIT_ADDRS 8 443 444 #define MSR_EFER 0xc0000080 445 446 #define MSR_EFER_SCE (1 << 0) 447 #define MSR_EFER_LME (1 << 8) 448 #define MSR_EFER_LMA (1 << 10) 449 #define MSR_EFER_NXE (1 << 11) 450 #define MSR_EFER_SVME (1 << 12) 451 #define MSR_EFER_FFXSR (1 << 14) 452 453 #define MSR_STAR 0xc0000081 454 #define MSR_LSTAR 0xc0000082 455 #define MSR_CSTAR 0xc0000083 456 #define MSR_FMASK 0xc0000084 457 #define MSR_FSBASE 0xc0000100 458 #define MSR_GSBASE 0xc0000101 459 #define MSR_KERNELGSBASE 0xc0000102 460 #define MSR_TSC_AUX 0xc0000103 461 462 #define MSR_VM_HSAVE_PA 0xc0010117 463 464 #define MSR_IA32_BNDCFGS 0x00000d90 465 #define MSR_IA32_XSS 0x00000da0 466 #define MSR_IA32_UMWAIT_CONTROL 0xe1 467 468 #define MSR_IA32_VMX_BASIC 0x00000480 469 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 470 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 471 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 472 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 473 #define MSR_IA32_VMX_MISC 0x00000485 474 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 475 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 476 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 477 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 478 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 479 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 480 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 481 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 482 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 483 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 484 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 485 #define MSR_IA32_VMX_VMFUNC 0x00000491 486 487 #define XSTATE_FP_BIT 0 488 #define XSTATE_SSE_BIT 1 489 #define XSTATE_YMM_BIT 2 490 #define XSTATE_BNDREGS_BIT 3 491 #define XSTATE_BNDCSR_BIT 4 492 #define XSTATE_OPMASK_BIT 5 493 #define XSTATE_ZMM_Hi256_BIT 6 494 #define XSTATE_Hi16_ZMM_BIT 7 495 #define XSTATE_PKRU_BIT 9 496 497 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 498 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 499 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 500 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 501 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 502 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 503 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 504 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 505 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 506 507 /* CPUID feature words */ 508 typedef enum FeatureWord { 509 FEAT_1_EDX, /* CPUID[1].EDX */ 510 FEAT_1_ECX, /* CPUID[1].ECX */ 511 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 512 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 513 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 514 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 515 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 516 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 517 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 518 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 519 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 520 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 521 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 522 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 523 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 524 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 525 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ 526 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ 527 FEAT_SVM, /* CPUID[8000_000A].EDX */ 528 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 529 FEAT_6_EAX, /* CPUID[6].EAX */ 530 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 531 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 532 FEAT_ARCH_CAPABILITIES, 533 FEAT_CORE_CAPABILITY, 534 FEAT_PERF_CAPABILITIES, 535 FEAT_VMX_PROCBASED_CTLS, 536 FEAT_VMX_SECONDARY_CTLS, 537 FEAT_VMX_PINBASED_CTLS, 538 FEAT_VMX_EXIT_CTLS, 539 FEAT_VMX_ENTRY_CTLS, 540 FEAT_VMX_MISC, 541 FEAT_VMX_EPT_VPID_CAPS, 542 FEAT_VMX_BASIC, 543 FEAT_VMX_VMFUNC, 544 FEATURE_WORDS, 545 } FeatureWord; 546 547 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 548 549 /* cpuid_features bits */ 550 #define CPUID_FP87 (1U << 0) 551 #define CPUID_VME (1U << 1) 552 #define CPUID_DE (1U << 2) 553 #define CPUID_PSE (1U << 3) 554 #define CPUID_TSC (1U << 4) 555 #define CPUID_MSR (1U << 5) 556 #define CPUID_PAE (1U << 6) 557 #define CPUID_MCE (1U << 7) 558 #define CPUID_CX8 (1U << 8) 559 #define CPUID_APIC (1U << 9) 560 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 561 #define CPUID_MTRR (1U << 12) 562 #define CPUID_PGE (1U << 13) 563 #define CPUID_MCA (1U << 14) 564 #define CPUID_CMOV (1U << 15) 565 #define CPUID_PAT (1U << 16) 566 #define CPUID_PSE36 (1U << 17) 567 #define CPUID_PN (1U << 18) 568 #define CPUID_CLFLUSH (1U << 19) 569 #define CPUID_DTS (1U << 21) 570 #define CPUID_ACPI (1U << 22) 571 #define CPUID_MMX (1U << 23) 572 #define CPUID_FXSR (1U << 24) 573 #define CPUID_SSE (1U << 25) 574 #define CPUID_SSE2 (1U << 26) 575 #define CPUID_SS (1U << 27) 576 #define CPUID_HT (1U << 28) 577 #define CPUID_TM (1U << 29) 578 #define CPUID_IA64 (1U << 30) 579 #define CPUID_PBE (1U << 31) 580 581 #define CPUID_EXT_SSE3 (1U << 0) 582 #define CPUID_EXT_PCLMULQDQ (1U << 1) 583 #define CPUID_EXT_DTES64 (1U << 2) 584 #define CPUID_EXT_MONITOR (1U << 3) 585 #define CPUID_EXT_DSCPL (1U << 4) 586 #define CPUID_EXT_VMX (1U << 5) 587 #define CPUID_EXT_SMX (1U << 6) 588 #define CPUID_EXT_EST (1U << 7) 589 #define CPUID_EXT_TM2 (1U << 8) 590 #define CPUID_EXT_SSSE3 (1U << 9) 591 #define CPUID_EXT_CID (1U << 10) 592 #define CPUID_EXT_FMA (1U << 12) 593 #define CPUID_EXT_CX16 (1U << 13) 594 #define CPUID_EXT_XTPR (1U << 14) 595 #define CPUID_EXT_PDCM (1U << 15) 596 #define CPUID_EXT_PCID (1U << 17) 597 #define CPUID_EXT_DCA (1U << 18) 598 #define CPUID_EXT_SSE41 (1U << 19) 599 #define CPUID_EXT_SSE42 (1U << 20) 600 #define CPUID_EXT_X2APIC (1U << 21) 601 #define CPUID_EXT_MOVBE (1U << 22) 602 #define CPUID_EXT_POPCNT (1U << 23) 603 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 604 #define CPUID_EXT_AES (1U << 25) 605 #define CPUID_EXT_XSAVE (1U << 26) 606 #define CPUID_EXT_OSXSAVE (1U << 27) 607 #define CPUID_EXT_AVX (1U << 28) 608 #define CPUID_EXT_F16C (1U << 29) 609 #define CPUID_EXT_RDRAND (1U << 30) 610 #define CPUID_EXT_HYPERVISOR (1U << 31) 611 612 #define CPUID_EXT2_FPU (1U << 0) 613 #define CPUID_EXT2_VME (1U << 1) 614 #define CPUID_EXT2_DE (1U << 2) 615 #define CPUID_EXT2_PSE (1U << 3) 616 #define CPUID_EXT2_TSC (1U << 4) 617 #define CPUID_EXT2_MSR (1U << 5) 618 #define CPUID_EXT2_PAE (1U << 6) 619 #define CPUID_EXT2_MCE (1U << 7) 620 #define CPUID_EXT2_CX8 (1U << 8) 621 #define CPUID_EXT2_APIC (1U << 9) 622 #define CPUID_EXT2_SYSCALL (1U << 11) 623 #define CPUID_EXT2_MTRR (1U << 12) 624 #define CPUID_EXT2_PGE (1U << 13) 625 #define CPUID_EXT2_MCA (1U << 14) 626 #define CPUID_EXT2_CMOV (1U << 15) 627 #define CPUID_EXT2_PAT (1U << 16) 628 #define CPUID_EXT2_PSE36 (1U << 17) 629 #define CPUID_EXT2_MP (1U << 19) 630 #define CPUID_EXT2_NX (1U << 20) 631 #define CPUID_EXT2_MMXEXT (1U << 22) 632 #define CPUID_EXT2_MMX (1U << 23) 633 #define CPUID_EXT2_FXSR (1U << 24) 634 #define CPUID_EXT2_FFXSR (1U << 25) 635 #define CPUID_EXT2_PDPE1GB (1U << 26) 636 #define CPUID_EXT2_RDTSCP (1U << 27) 637 #define CPUID_EXT2_LM (1U << 29) 638 #define CPUID_EXT2_3DNOWEXT (1U << 30) 639 #define CPUID_EXT2_3DNOW (1U << 31) 640 641 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 642 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 643 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 644 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 645 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 646 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 647 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 648 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 649 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 650 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 651 652 #define CPUID_EXT3_LAHF_LM (1U << 0) 653 #define CPUID_EXT3_CMP_LEG (1U << 1) 654 #define CPUID_EXT3_SVM (1U << 2) 655 #define CPUID_EXT3_EXTAPIC (1U << 3) 656 #define CPUID_EXT3_CR8LEG (1U << 4) 657 #define CPUID_EXT3_ABM (1U << 5) 658 #define CPUID_EXT3_SSE4A (1U << 6) 659 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 660 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 661 #define CPUID_EXT3_OSVW (1U << 9) 662 #define CPUID_EXT3_IBS (1U << 10) 663 #define CPUID_EXT3_XOP (1U << 11) 664 #define CPUID_EXT3_SKINIT (1U << 12) 665 #define CPUID_EXT3_WDT (1U << 13) 666 #define CPUID_EXT3_LWP (1U << 15) 667 #define CPUID_EXT3_FMA4 (1U << 16) 668 #define CPUID_EXT3_TCE (1U << 17) 669 #define CPUID_EXT3_NODEID (1U << 19) 670 #define CPUID_EXT3_TBM (1U << 21) 671 #define CPUID_EXT3_TOPOEXT (1U << 22) 672 #define CPUID_EXT3_PERFCORE (1U << 23) 673 #define CPUID_EXT3_PERFNB (1U << 24) 674 675 #define CPUID_SVM_NPT (1U << 0) 676 #define CPUID_SVM_LBRV (1U << 1) 677 #define CPUID_SVM_SVMLOCK (1U << 2) 678 #define CPUID_SVM_NRIPSAVE (1U << 3) 679 #define CPUID_SVM_TSCSCALE (1U << 4) 680 #define CPUID_SVM_VMCBCLEAN (1U << 5) 681 #define CPUID_SVM_FLUSHASID (1U << 6) 682 #define CPUID_SVM_DECODEASSIST (1U << 7) 683 #define CPUID_SVM_PAUSEFILTER (1U << 10) 684 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 685 686 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 687 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 688 /* 1st Group of Advanced Bit Manipulation Extensions */ 689 #define CPUID_7_0_EBX_BMI1 (1U << 3) 690 /* Hardware Lock Elision */ 691 #define CPUID_7_0_EBX_HLE (1U << 4) 692 /* Intel Advanced Vector Extensions 2 */ 693 #define CPUID_7_0_EBX_AVX2 (1U << 5) 694 /* Supervisor-mode Execution Prevention */ 695 #define CPUID_7_0_EBX_SMEP (1U << 7) 696 /* 2nd Group of Advanced Bit Manipulation Extensions */ 697 #define CPUID_7_0_EBX_BMI2 (1U << 8) 698 /* Enhanced REP MOVSB/STOSB */ 699 #define CPUID_7_0_EBX_ERMS (1U << 9) 700 /* Invalidate Process-Context Identifier */ 701 #define CPUID_7_0_EBX_INVPCID (1U << 10) 702 /* Restricted Transactional Memory */ 703 #define CPUID_7_0_EBX_RTM (1U << 11) 704 /* Memory Protection Extension */ 705 #define CPUID_7_0_EBX_MPX (1U << 14) 706 /* AVX-512 Foundation */ 707 #define CPUID_7_0_EBX_AVX512F (1U << 16) 708 /* AVX-512 Doubleword & Quadword Instruction */ 709 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 710 /* Read Random SEED */ 711 #define CPUID_7_0_EBX_RDSEED (1U << 18) 712 /* ADCX and ADOX instructions */ 713 #define CPUID_7_0_EBX_ADX (1U << 19) 714 /* Supervisor Mode Access Prevention */ 715 #define CPUID_7_0_EBX_SMAP (1U << 20) 716 /* AVX-512 Integer Fused Multiply Add */ 717 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 718 /* Persistent Commit */ 719 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 720 /* Flush a Cache Line Optimized */ 721 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 722 /* Cache Line Write Back */ 723 #define CPUID_7_0_EBX_CLWB (1U << 24) 724 /* Intel Processor Trace */ 725 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 726 /* AVX-512 Prefetch */ 727 #define CPUID_7_0_EBX_AVX512PF (1U << 26) 728 /* AVX-512 Exponential and Reciprocal */ 729 #define CPUID_7_0_EBX_AVX512ER (1U << 27) 730 /* AVX-512 Conflict Detection */ 731 #define CPUID_7_0_EBX_AVX512CD (1U << 28) 732 /* SHA1/SHA256 Instruction Extensions */ 733 #define CPUID_7_0_EBX_SHA_NI (1U << 29) 734 /* AVX-512 Byte and Word Instructions */ 735 #define CPUID_7_0_EBX_AVX512BW (1U << 30) 736 /* AVX-512 Vector Length Extensions */ 737 #define CPUID_7_0_EBX_AVX512VL (1U << 31) 738 739 /* AVX-512 Vector Byte Manipulation Instruction */ 740 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 741 /* User-Mode Instruction Prevention */ 742 #define CPUID_7_0_ECX_UMIP (1U << 2) 743 /* Protection Keys for User-mode Pages */ 744 #define CPUID_7_0_ECX_PKU (1U << 3) 745 /* OS Enable Protection Keys */ 746 #define CPUID_7_0_ECX_OSPKE (1U << 4) 747 /* UMONITOR/UMWAIT/TPAUSE Instructions */ 748 #define CPUID_7_0_ECX_WAITPKG (1U << 5) 749 /* Additional AVX-512 Vector Byte Manipulation Instruction */ 750 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 751 /* Galois Field New Instructions */ 752 #define CPUID_7_0_ECX_GFNI (1U << 8) 753 /* Vector AES Instructions */ 754 #define CPUID_7_0_ECX_VAES (1U << 9) 755 /* Carry-Less Multiplication Quadword */ 756 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 757 /* Vector Neural Network Instructions */ 758 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 759 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 760 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 761 /* POPCNT for vectors of DW/QW */ 762 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 763 /* 5-level Page Tables */ 764 #define CPUID_7_0_ECX_LA57 (1U << 16) 765 /* Read Processor ID */ 766 #define CPUID_7_0_ECX_RDPID (1U << 22) 767 /* Cache Line Demote Instruction */ 768 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 769 /* Move Doubleword as Direct Store Instruction */ 770 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 771 /* Move 64 Bytes as Direct Store Instruction */ 772 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 773 774 /* AVX512 Neural Network Instructions */ 775 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 776 /* AVX512 Multiply Accumulation Single Precision */ 777 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 778 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 779 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 780 /* SERIALIZE instruction */ 781 #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 782 /* TSX Suspend Load Address Tracking instruction */ 783 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 784 /* Speculation Control */ 785 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 786 /* Single Thread Indirect Branch Predictors */ 787 #define CPUID_7_0_EDX_STIBP (1U << 27) 788 /* Arch Capabilities */ 789 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 790 /* Core Capability */ 791 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 792 /* Speculative Store Bypass Disable */ 793 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 794 795 /* AVX512 BFloat16 Instruction */ 796 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 797 798 /* CLZERO instruction */ 799 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 800 /* Always save/restore FP error pointers */ 801 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 802 /* Write back and do not invalidate cache */ 803 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 804 /* Indirect Branch Prediction Barrier */ 805 #define CPUID_8000_0008_EBX_IBPB (1U << 12) 806 /* Single Thread Indirect Branch Predictors */ 807 #define CPUID_8000_0008_EBX_STIBP (1U << 15) 808 809 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 810 #define CPUID_XSAVE_XSAVEC (1U << 1) 811 #define CPUID_XSAVE_XGETBV1 (1U << 2) 812 #define CPUID_XSAVE_XSAVES (1U << 3) 813 814 #define CPUID_6_EAX_ARAT (1U << 2) 815 816 /* CPUID[0x80000007].EDX flags: */ 817 #define CPUID_APM_INVTSC (1U << 8) 818 819 #define CPUID_VENDOR_SZ 12 820 821 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 822 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 823 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 824 #define CPUID_VENDOR_INTEL "GenuineIntel" 825 826 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 827 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 828 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 829 #define CPUID_VENDOR_AMD "AuthenticAMD" 830 831 #define CPUID_VENDOR_VIA "CentaurHauls" 832 833 #define CPUID_VENDOR_HYGON "HygonGenuine" 834 835 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 836 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 837 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 838 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 839 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 840 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 841 842 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 843 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 844 845 /* CPUID[0xB].ECX level types */ 846 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 847 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 848 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 849 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 850 851 /* MSR Feature Bits */ 852 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 853 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 854 #define MSR_ARCH_CAP_RSBA (1U << 2) 855 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 856 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 857 #define MSR_ARCH_CAP_MDS_NO (1U << 5) 858 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 859 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 860 #define MSR_ARCH_CAP_TAA_NO (1U << 8) 861 862 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 863 864 /* VMX MSR features */ 865 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 866 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 867 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 868 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 869 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 870 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 871 872 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 873 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 874 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 875 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 876 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 877 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 878 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 879 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 880 881 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 882 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 883 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 884 #define MSR_VMX_EPT_UC (1ULL << 8) 885 #define MSR_VMX_EPT_WB (1ULL << 14) 886 #define MSR_VMX_EPT_2MB (1ULL << 16) 887 #define MSR_VMX_EPT_1GB (1ULL << 17) 888 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 889 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 890 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 891 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 892 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 893 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 894 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 895 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 896 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 897 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 898 899 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 900 901 902 /* VMX controls */ 903 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 904 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 905 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 906 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 907 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 908 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 909 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 910 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 911 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 912 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 913 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 914 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 915 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 916 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 917 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 918 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 919 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 920 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 921 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 922 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 923 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 924 925 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 926 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 927 #define VMX_SECONDARY_EXEC_DESC 0x00000004 928 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 929 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 930 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 931 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 932 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 933 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 934 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 935 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 936 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 937 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 938 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 939 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 940 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 941 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 942 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 943 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 944 945 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 946 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 947 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 948 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 949 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 950 951 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 952 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 953 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 954 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 955 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 956 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 957 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 958 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 959 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 960 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 961 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 962 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 963 964 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 965 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 966 #define VMX_VM_ENTRY_SMM 0x00000400 967 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 968 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 969 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 970 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 971 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 972 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 973 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 974 975 /* Supported Hyper-V Enlightenments */ 976 #define HYPERV_FEAT_RELAXED 0 977 #define HYPERV_FEAT_VAPIC 1 978 #define HYPERV_FEAT_TIME 2 979 #define HYPERV_FEAT_CRASH 3 980 #define HYPERV_FEAT_RESET 4 981 #define HYPERV_FEAT_VPINDEX 5 982 #define HYPERV_FEAT_RUNTIME 6 983 #define HYPERV_FEAT_SYNIC 7 984 #define HYPERV_FEAT_STIMER 8 985 #define HYPERV_FEAT_FREQUENCIES 9 986 #define HYPERV_FEAT_REENLIGHTENMENT 10 987 #define HYPERV_FEAT_TLBFLUSH 11 988 #define HYPERV_FEAT_EVMCS 12 989 #define HYPERV_FEAT_IPI 13 990 #define HYPERV_FEAT_STIMER_DIRECT 14 991 992 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 993 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 994 #endif 995 996 #define EXCP00_DIVZ 0 997 #define EXCP01_DB 1 998 #define EXCP02_NMI 2 999 #define EXCP03_INT3 3 1000 #define EXCP04_INTO 4 1001 #define EXCP05_BOUND 5 1002 #define EXCP06_ILLOP 6 1003 #define EXCP07_PREX 7 1004 #define EXCP08_DBLE 8 1005 #define EXCP09_XERR 9 1006 #define EXCP0A_TSS 10 1007 #define EXCP0B_NOSEG 11 1008 #define EXCP0C_STACK 12 1009 #define EXCP0D_GPF 13 1010 #define EXCP0E_PAGE 14 1011 #define EXCP10_COPR 16 1012 #define EXCP11_ALGN 17 1013 #define EXCP12_MCHK 18 1014 1015 #define EXCP_VMEXIT 0x100 /* only for system emulation */ 1016 #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1017 #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1018 1019 /* i386-specific interrupt pending bits. */ 1020 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1021 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1022 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1023 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1024 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1025 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1026 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1027 1028 /* Use a clearer name for this. */ 1029 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1030 1031 /* Instead of computing the condition codes after each x86 instruction, 1032 * QEMU just stores one operand (called CC_SRC), the result 1033 * (called CC_DST) and the type of operation (called CC_OP). When the 1034 * condition codes are needed, the condition codes can be calculated 1035 * using this information. Condition codes are not generated if they 1036 * are only needed for conditional branches. 1037 */ 1038 typedef enum { 1039 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1040 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1041 1042 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1043 CC_OP_MULW, 1044 CC_OP_MULL, 1045 CC_OP_MULQ, 1046 1047 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1048 CC_OP_ADDW, 1049 CC_OP_ADDL, 1050 CC_OP_ADDQ, 1051 1052 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1053 CC_OP_ADCW, 1054 CC_OP_ADCL, 1055 CC_OP_ADCQ, 1056 1057 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1058 CC_OP_SUBW, 1059 CC_OP_SUBL, 1060 CC_OP_SUBQ, 1061 1062 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1063 CC_OP_SBBW, 1064 CC_OP_SBBL, 1065 CC_OP_SBBQ, 1066 1067 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1068 CC_OP_LOGICW, 1069 CC_OP_LOGICL, 1070 CC_OP_LOGICQ, 1071 1072 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1073 CC_OP_INCW, 1074 CC_OP_INCL, 1075 CC_OP_INCQ, 1076 1077 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1078 CC_OP_DECW, 1079 CC_OP_DECL, 1080 CC_OP_DECQ, 1081 1082 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1083 CC_OP_SHLW, 1084 CC_OP_SHLL, 1085 CC_OP_SHLQ, 1086 1087 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1088 CC_OP_SARW, 1089 CC_OP_SARL, 1090 CC_OP_SARQ, 1091 1092 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1093 CC_OP_BMILGW, 1094 CC_OP_BMILGL, 1095 CC_OP_BMILGQ, 1096 1097 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1098 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1099 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1100 1101 CC_OP_CLR, /* Z set, all other flags clear. */ 1102 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1103 1104 CC_OP_NB, 1105 } CCOp; 1106 1107 typedef struct SegmentCache { 1108 uint32_t selector; 1109 target_ulong base; 1110 uint32_t limit; 1111 uint32_t flags; 1112 } SegmentCache; 1113 1114 #define MMREG_UNION(n, bits) \ 1115 union n { \ 1116 uint8_t _b_##n[(bits)/8]; \ 1117 uint16_t _w_##n[(bits)/16]; \ 1118 uint32_t _l_##n[(bits)/32]; \ 1119 uint64_t _q_##n[(bits)/64]; \ 1120 float32 _s_##n[(bits)/32]; \ 1121 float64 _d_##n[(bits)/64]; \ 1122 } 1123 1124 typedef union { 1125 uint8_t _b[16]; 1126 uint16_t _w[8]; 1127 uint32_t _l[4]; 1128 uint64_t _q[2]; 1129 } XMMReg; 1130 1131 typedef union { 1132 uint8_t _b[32]; 1133 uint16_t _w[16]; 1134 uint32_t _l[8]; 1135 uint64_t _q[4]; 1136 } YMMReg; 1137 1138 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1139 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1140 1141 typedef struct BNDReg { 1142 uint64_t lb; 1143 uint64_t ub; 1144 } BNDReg; 1145 1146 typedef struct BNDCSReg { 1147 uint64_t cfgu; 1148 uint64_t sts; 1149 } BNDCSReg; 1150 1151 #define BNDCFG_ENABLE 1ULL 1152 #define BNDCFG_BNDPRESERVE 2ULL 1153 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1154 1155 #ifdef HOST_WORDS_BIGENDIAN 1156 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1157 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1158 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1159 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1160 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1161 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1162 1163 #define MMX_B(n) _b_MMXReg[7 - (n)] 1164 #define MMX_W(n) _w_MMXReg[3 - (n)] 1165 #define MMX_L(n) _l_MMXReg[1 - (n)] 1166 #define MMX_S(n) _s_MMXReg[1 - (n)] 1167 #else 1168 #define ZMM_B(n) _b_ZMMReg[n] 1169 #define ZMM_W(n) _w_ZMMReg[n] 1170 #define ZMM_L(n) _l_ZMMReg[n] 1171 #define ZMM_S(n) _s_ZMMReg[n] 1172 #define ZMM_Q(n) _q_ZMMReg[n] 1173 #define ZMM_D(n) _d_ZMMReg[n] 1174 1175 #define MMX_B(n) _b_MMXReg[n] 1176 #define MMX_W(n) _w_MMXReg[n] 1177 #define MMX_L(n) _l_MMXReg[n] 1178 #define MMX_S(n) _s_MMXReg[n] 1179 #endif 1180 #define MMX_Q(n) _q_MMXReg[n] 1181 1182 typedef union { 1183 floatx80 d __attribute__((aligned(16))); 1184 MMXReg mmx; 1185 } FPReg; 1186 1187 typedef struct { 1188 uint64_t base; 1189 uint64_t mask; 1190 } MTRRVar; 1191 1192 #define CPU_NB_REGS64 16 1193 #define CPU_NB_REGS32 8 1194 1195 #ifdef TARGET_X86_64 1196 #define CPU_NB_REGS CPU_NB_REGS64 1197 #else 1198 #define CPU_NB_REGS CPU_NB_REGS32 1199 #endif 1200 1201 #define MAX_FIXED_COUNTERS 3 1202 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1203 1204 #define TARGET_INSN_START_EXTRA_WORDS 1 1205 1206 #define NB_OPMASK_REGS 8 1207 1208 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1209 * that APIC ID hasn't been set yet 1210 */ 1211 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1212 1213 typedef union X86LegacyXSaveArea { 1214 struct { 1215 uint16_t fcw; 1216 uint16_t fsw; 1217 uint8_t ftw; 1218 uint8_t reserved; 1219 uint16_t fpop; 1220 uint64_t fpip; 1221 uint64_t fpdp; 1222 uint32_t mxcsr; 1223 uint32_t mxcsr_mask; 1224 FPReg fpregs[8]; 1225 uint8_t xmm_regs[16][16]; 1226 }; 1227 uint8_t data[512]; 1228 } X86LegacyXSaveArea; 1229 1230 typedef struct X86XSaveHeader { 1231 uint64_t xstate_bv; 1232 uint64_t xcomp_bv; 1233 uint64_t reserve0; 1234 uint8_t reserved[40]; 1235 } X86XSaveHeader; 1236 1237 /* Ext. save area 2: AVX State */ 1238 typedef struct XSaveAVX { 1239 uint8_t ymmh[16][16]; 1240 } XSaveAVX; 1241 1242 /* Ext. save area 3: BNDREG */ 1243 typedef struct XSaveBNDREG { 1244 BNDReg bnd_regs[4]; 1245 } XSaveBNDREG; 1246 1247 /* Ext. save area 4: BNDCSR */ 1248 typedef union XSaveBNDCSR { 1249 BNDCSReg bndcsr; 1250 uint8_t data[64]; 1251 } XSaveBNDCSR; 1252 1253 /* Ext. save area 5: Opmask */ 1254 typedef struct XSaveOpmask { 1255 uint64_t opmask_regs[NB_OPMASK_REGS]; 1256 } XSaveOpmask; 1257 1258 /* Ext. save area 6: ZMM_Hi256 */ 1259 typedef struct XSaveZMM_Hi256 { 1260 uint8_t zmm_hi256[16][32]; 1261 } XSaveZMM_Hi256; 1262 1263 /* Ext. save area 7: Hi16_ZMM */ 1264 typedef struct XSaveHi16_ZMM { 1265 uint8_t hi16_zmm[16][64]; 1266 } XSaveHi16_ZMM; 1267 1268 /* Ext. save area 9: PKRU state */ 1269 typedef struct XSavePKRU { 1270 uint32_t pkru; 1271 uint32_t padding; 1272 } XSavePKRU; 1273 1274 typedef struct X86XSaveArea { 1275 X86LegacyXSaveArea legacy; 1276 X86XSaveHeader header; 1277 1278 /* Extended save areas: */ 1279 1280 /* AVX State: */ 1281 XSaveAVX avx_state; 1282 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1283 /* MPX State: */ 1284 XSaveBNDREG bndreg_state; 1285 XSaveBNDCSR bndcsr_state; 1286 /* AVX-512 State: */ 1287 XSaveOpmask opmask_state; 1288 XSaveZMM_Hi256 zmm_hi256_state; 1289 XSaveHi16_ZMM hi16_zmm_state; 1290 /* PKRU State: */ 1291 XSavePKRU pkru_state; 1292 } X86XSaveArea; 1293 1294 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1295 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1296 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1297 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1298 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1299 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1300 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1301 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1302 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1303 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1304 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1305 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1306 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1307 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1308 1309 typedef enum TPRAccess { 1310 TPR_ACCESS_READ, 1311 TPR_ACCESS_WRITE, 1312 } TPRAccess; 1313 1314 /* Cache information data structures: */ 1315 1316 enum CacheType { 1317 DATA_CACHE, 1318 INSTRUCTION_CACHE, 1319 UNIFIED_CACHE 1320 }; 1321 1322 typedef struct CPUCacheInfo { 1323 enum CacheType type; 1324 uint8_t level; 1325 /* Size in bytes */ 1326 uint32_t size; 1327 /* Line size, in bytes */ 1328 uint16_t line_size; 1329 /* 1330 * Associativity. 1331 * Note: representation of fully-associative caches is not implemented 1332 */ 1333 uint8_t associativity; 1334 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1335 uint8_t partitions; 1336 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1337 uint32_t sets; 1338 /* 1339 * Lines per tag. 1340 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1341 * (Is this synonym to @partitions?) 1342 */ 1343 uint8_t lines_per_tag; 1344 1345 /* Self-initializing cache */ 1346 bool self_init; 1347 /* 1348 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1349 * non-originating threads sharing this cache. 1350 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1351 */ 1352 bool no_invd_sharing; 1353 /* 1354 * Cache is inclusive of lower cache levels. 1355 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1356 */ 1357 bool inclusive; 1358 /* 1359 * A complex function is used to index the cache, potentially using all 1360 * address bits. CPUID[4].EDX[bit 2]. 1361 */ 1362 bool complex_indexing; 1363 } CPUCacheInfo; 1364 1365 1366 typedef struct CPUCaches { 1367 CPUCacheInfo *l1d_cache; 1368 CPUCacheInfo *l1i_cache; 1369 CPUCacheInfo *l2_cache; 1370 CPUCacheInfo *l3_cache; 1371 } CPUCaches; 1372 1373 typedef struct HVFX86LazyFlags { 1374 target_ulong result; 1375 target_ulong auxbits; 1376 } HVFX86LazyFlags; 1377 1378 typedef struct CPUX86State { 1379 /* standard registers */ 1380 target_ulong regs[CPU_NB_REGS]; 1381 target_ulong eip; 1382 target_ulong eflags; /* eflags register. During CPU emulation, CC 1383 flags and DF are set to zero because they are 1384 stored elsewhere */ 1385 1386 /* emulator internal eflags handling */ 1387 target_ulong cc_dst; 1388 target_ulong cc_src; 1389 target_ulong cc_src2; 1390 uint32_t cc_op; 1391 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1392 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1393 are known at translation time. */ 1394 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1395 1396 /* segments */ 1397 SegmentCache segs[6]; /* selector values */ 1398 SegmentCache ldt; 1399 SegmentCache tr; 1400 SegmentCache gdt; /* only base and limit are used */ 1401 SegmentCache idt; /* only base and limit are used */ 1402 1403 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1404 int32_t a20_mask; 1405 1406 BNDReg bnd_regs[4]; 1407 BNDCSReg bndcs_regs; 1408 uint64_t msr_bndcfgs; 1409 uint64_t efer; 1410 1411 /* Beginning of state preserved by INIT (dummy marker). */ 1412 struct {} start_init_save; 1413 1414 /* FPU state */ 1415 unsigned int fpstt; /* top of stack index */ 1416 uint16_t fpus; 1417 uint16_t fpuc; 1418 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1419 FPReg fpregs[8]; 1420 /* KVM-only so far */ 1421 uint16_t fpop; 1422 uint64_t fpip; 1423 uint64_t fpdp; 1424 1425 /* emulator internal variables */ 1426 float_status fp_status; 1427 floatx80 ft0; 1428 1429 float_status mmx_status; /* for 3DNow! float ops */ 1430 float_status sse_status; 1431 uint32_t mxcsr; 1432 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1433 ZMMReg xmm_t0; 1434 MMXReg mmx_t0; 1435 1436 XMMReg ymmh_regs[CPU_NB_REGS]; 1437 1438 uint64_t opmask_regs[NB_OPMASK_REGS]; 1439 YMMReg zmmh_regs[CPU_NB_REGS]; 1440 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1441 1442 /* sysenter registers */ 1443 uint32_t sysenter_cs; 1444 target_ulong sysenter_esp; 1445 target_ulong sysenter_eip; 1446 uint64_t star; 1447 1448 uint64_t vm_hsave; 1449 1450 #ifdef TARGET_X86_64 1451 target_ulong lstar; 1452 target_ulong cstar; 1453 target_ulong fmask; 1454 target_ulong kernelgsbase; 1455 #endif 1456 1457 uint64_t tsc; 1458 uint64_t tsc_adjust; 1459 uint64_t tsc_deadline; 1460 uint64_t tsc_aux; 1461 1462 uint64_t xcr0; 1463 1464 uint64_t mcg_status; 1465 uint64_t msr_ia32_misc_enable; 1466 uint64_t msr_ia32_feature_control; 1467 1468 uint64_t msr_fixed_ctr_ctrl; 1469 uint64_t msr_global_ctrl; 1470 uint64_t msr_global_status; 1471 uint64_t msr_global_ovf_ctrl; 1472 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1473 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1474 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1475 1476 uint64_t pat; 1477 uint32_t smbase; 1478 uint64_t msr_smi_count; 1479 1480 uint32_t pkru; 1481 uint32_t tsx_ctrl; 1482 1483 uint64_t spec_ctrl; 1484 uint64_t virt_ssbd; 1485 1486 /* End of state preserved by INIT (dummy marker). */ 1487 struct {} end_init_save; 1488 1489 uint64_t system_time_msr; 1490 uint64_t wall_clock_msr; 1491 uint64_t steal_time_msr; 1492 uint64_t async_pf_en_msr; 1493 uint64_t pv_eoi_en_msr; 1494 uint64_t poll_control_msr; 1495 1496 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1497 uint64_t msr_hv_hypercall; 1498 uint64_t msr_hv_guest_os_id; 1499 uint64_t msr_hv_tsc; 1500 1501 /* Per-VCPU HV MSRs */ 1502 uint64_t msr_hv_vapic; 1503 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1504 uint64_t msr_hv_runtime; 1505 uint64_t msr_hv_synic_control; 1506 uint64_t msr_hv_synic_evt_page; 1507 uint64_t msr_hv_synic_msg_page; 1508 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1509 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1510 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1511 uint64_t msr_hv_reenlightenment_control; 1512 uint64_t msr_hv_tsc_emulation_control; 1513 uint64_t msr_hv_tsc_emulation_status; 1514 1515 uint64_t msr_rtit_ctrl; 1516 uint64_t msr_rtit_status; 1517 uint64_t msr_rtit_output_base; 1518 uint64_t msr_rtit_output_mask; 1519 uint64_t msr_rtit_cr3_match; 1520 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1521 1522 /* exception/interrupt handling */ 1523 int error_code; 1524 int exception_is_int; 1525 target_ulong exception_next_eip; 1526 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1527 union { 1528 struct CPUBreakpoint *cpu_breakpoint[4]; 1529 struct CPUWatchpoint *cpu_watchpoint[4]; 1530 }; /* break/watchpoints for dr[0..3] */ 1531 int old_exception; /* exception in flight */ 1532 1533 uint64_t vm_vmcb; 1534 uint64_t tsc_offset; 1535 uint64_t intercept; 1536 uint16_t intercept_cr_read; 1537 uint16_t intercept_cr_write; 1538 uint16_t intercept_dr_read; 1539 uint16_t intercept_dr_write; 1540 uint32_t intercept_exceptions; 1541 uint64_t nested_cr3; 1542 uint32_t nested_pg_mode; 1543 uint8_t v_tpr; 1544 1545 /* KVM states, automatically cleared on reset */ 1546 uint8_t nmi_injected; 1547 uint8_t nmi_pending; 1548 1549 uintptr_t retaddr; 1550 1551 /* Fields up to this point are cleared by a CPU reset */ 1552 struct {} end_reset_fields; 1553 1554 /* Fields after this point are preserved across CPU reset. */ 1555 1556 /* processor features (e.g. for CPUID insn) */ 1557 /* Minimum cpuid leaf 7 value */ 1558 uint32_t cpuid_level_func7; 1559 /* Actual cpuid leaf 7 value */ 1560 uint32_t cpuid_min_level_func7; 1561 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1562 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1563 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1564 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1565 /* Actual level/xlevel/xlevel2 value: */ 1566 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1567 uint32_t cpuid_vendor1; 1568 uint32_t cpuid_vendor2; 1569 uint32_t cpuid_vendor3; 1570 uint32_t cpuid_version; 1571 FeatureWordArray features; 1572 /* Features that were explicitly enabled/disabled */ 1573 FeatureWordArray user_features; 1574 uint32_t cpuid_model[12]; 1575 /* Cache information for CPUID. When legacy-cache=on, the cache data 1576 * on each CPUID leaf will be different, because we keep compatibility 1577 * with old QEMU versions. 1578 */ 1579 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1580 1581 /* MTRRs */ 1582 uint64_t mtrr_fixed[11]; 1583 uint64_t mtrr_deftype; 1584 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1585 1586 /* For KVM */ 1587 uint32_t mp_state; 1588 int32_t exception_nr; 1589 int32_t interrupt_injected; 1590 uint8_t soft_interrupt; 1591 uint8_t exception_pending; 1592 uint8_t exception_injected; 1593 uint8_t has_error_code; 1594 uint8_t exception_has_payload; 1595 uint64_t exception_payload; 1596 uint32_t ins_len; 1597 uint32_t sipi_vector; 1598 bool tsc_valid; 1599 int64_t tsc_khz; 1600 int64_t user_tsc_khz; /* for sanity check only */ 1601 uint64_t apic_bus_freq; 1602 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1603 void *xsave_buf; 1604 #endif 1605 #if defined(CONFIG_KVM) 1606 struct kvm_nested_state *nested_state; 1607 #endif 1608 #if defined(CONFIG_HVF) 1609 HVFX86LazyFlags hvf_lflags; 1610 void *hvf_mmio_buf; 1611 #endif 1612 1613 uint64_t mcg_cap; 1614 uint64_t mcg_ctl; 1615 uint64_t mcg_ext_ctl; 1616 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1617 uint64_t xstate_bv; 1618 1619 /* vmstate */ 1620 uint16_t fpus_vmstate; 1621 uint16_t fptag_vmstate; 1622 uint16_t fpregs_format_vmstate; 1623 1624 uint64_t xss; 1625 uint32_t umwait; 1626 1627 TPRAccess tpr_access_type; 1628 1629 unsigned nr_dies; 1630 unsigned nr_nodes; 1631 unsigned pkg_offset; 1632 } CPUX86State; 1633 1634 struct kvm_msrs; 1635 1636 /** 1637 * X86CPU: 1638 * @env: #CPUX86State 1639 * @migratable: If set, only migratable flags will be accepted when "enforce" 1640 * mode is used, and only migratable flags will be included in the "host" 1641 * CPU model. 1642 * 1643 * An x86 CPU. 1644 */ 1645 struct X86CPU { 1646 /*< private >*/ 1647 CPUState parent_obj; 1648 /*< public >*/ 1649 1650 CPUNegativeOffsetState neg; 1651 CPUX86State env; 1652 VMChangeStateEntry *vmsentry; 1653 1654 uint64_t ucode_rev; 1655 1656 uint32_t hyperv_spinlock_attempts; 1657 char *hyperv_vendor_id; 1658 bool hyperv_synic_kvm_only; 1659 uint64_t hyperv_features; 1660 bool hyperv_passthrough; 1661 OnOffAuto hyperv_no_nonarch_cs; 1662 1663 bool check_cpuid; 1664 bool enforce_cpuid; 1665 /* 1666 * Force features to be enabled even if the host doesn't support them. 1667 * This is dangerous and should be done only for testing CPUID 1668 * compatibility. 1669 */ 1670 bool force_features; 1671 bool expose_kvm; 1672 bool expose_tcg; 1673 bool migratable; 1674 bool migrate_smi_count; 1675 bool max_features; /* Enable all supported features automatically */ 1676 uint32_t apic_id; 1677 1678 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1679 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1680 bool vmware_cpuid_freq; 1681 1682 /* if true the CPUID code directly forward host cache leaves to the guest */ 1683 bool cache_info_passthrough; 1684 1685 /* if true the CPUID code directly forwards 1686 * host monitor/mwait leaves to the guest */ 1687 struct { 1688 uint32_t eax; 1689 uint32_t ebx; 1690 uint32_t ecx; 1691 uint32_t edx; 1692 } mwait; 1693 1694 /* Features that were filtered out because of missing host capabilities */ 1695 FeatureWordArray filtered_features; 1696 1697 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1698 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1699 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1700 * capabilities) directly to the guest. 1701 */ 1702 bool enable_pmu; 1703 1704 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1705 * disabled by default to avoid breaking migration between QEMU with 1706 * different LMCE configurations. 1707 */ 1708 bool enable_lmce; 1709 1710 /* Compatibility bits for old machine types. 1711 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1712 * socket share an virtual l3 cache. 1713 */ 1714 bool enable_l3_cache; 1715 1716 /* Compatibility bits for old machine types. 1717 * If true present the old cache topology information 1718 */ 1719 bool legacy_cache; 1720 1721 /* Compatibility bits for old machine types: */ 1722 bool enable_cpuid_0xb; 1723 1724 /* Enable auto level-increase for all CPUID leaves */ 1725 bool full_cpuid_auto_level; 1726 1727 /* Enable auto level-increase for Intel Processor Trace leave */ 1728 bool intel_pt_auto_level; 1729 1730 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1731 bool fill_mtrr_mask; 1732 1733 /* if true override the phys_bits value with a value read from the host */ 1734 bool host_phys_bits; 1735 1736 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1737 uint8_t host_phys_bits_limit; 1738 1739 /* Stop SMI delivery for migration compatibility with old machines */ 1740 bool kvm_no_smi_migration; 1741 1742 /* Number of physical address bits supported */ 1743 uint32_t phys_bits; 1744 1745 /* in order to simplify APIC support, we leave this pointer to the 1746 user */ 1747 struct DeviceState *apic_state; 1748 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1749 Notifier machine_done; 1750 1751 struct kvm_msrs *kvm_msr_buf; 1752 1753 int32_t node_id; /* NUMA node this CPU belongs to */ 1754 int32_t socket_id; 1755 int32_t die_id; 1756 int32_t core_id; 1757 int32_t thread_id; 1758 1759 int32_t hv_max_vps; 1760 }; 1761 1762 1763 #ifndef CONFIG_USER_ONLY 1764 extern VMStateDescription vmstate_x86_cpu; 1765 #endif 1766 1767 /** 1768 * x86_cpu_do_interrupt: 1769 * @cpu: vCPU the interrupt is to be handled by. 1770 */ 1771 void x86_cpu_do_interrupt(CPUState *cpu); 1772 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1773 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1774 1775 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1776 int cpuid, void *opaque); 1777 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1778 int cpuid, void *opaque); 1779 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1780 void *opaque); 1781 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1782 void *opaque); 1783 1784 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1785 Error **errp); 1786 1787 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1788 1789 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1790 MemTxAttrs *attrs); 1791 1792 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1793 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1794 1795 void x86_cpu_exec_enter(CPUState *cpu); 1796 void x86_cpu_exec_exit(CPUState *cpu); 1797 1798 void x86_cpu_list(void); 1799 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1800 1801 int cpu_get_pic_interrupt(CPUX86State *s); 1802 /* MSDOS compatibility mode FPU exception support */ 1803 void x86_register_ferr_irq(qemu_irq irq); 1804 void cpu_set_ignne(void); 1805 /* mpx_helper.c */ 1806 void cpu_sync_bndcs_hflags(CPUX86State *env); 1807 1808 /* this function must always be used to load data in the segment 1809 cache: it synchronizes the hflags with the segment cache values */ 1810 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1811 int seg_reg, unsigned int selector, 1812 target_ulong base, 1813 unsigned int limit, 1814 unsigned int flags) 1815 { 1816 SegmentCache *sc; 1817 unsigned int new_hflags; 1818 1819 sc = &env->segs[seg_reg]; 1820 sc->selector = selector; 1821 sc->base = base; 1822 sc->limit = limit; 1823 sc->flags = flags; 1824 1825 /* update the hidden flags */ 1826 { 1827 if (seg_reg == R_CS) { 1828 #ifdef TARGET_X86_64 1829 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1830 /* long mode */ 1831 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1832 env->hflags &= ~(HF_ADDSEG_MASK); 1833 } else 1834 #endif 1835 { 1836 /* legacy / compatibility case */ 1837 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1838 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1839 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1840 new_hflags; 1841 } 1842 } 1843 if (seg_reg == R_SS) { 1844 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1845 #if HF_CPL_MASK != 3 1846 #error HF_CPL_MASK is hardcoded 1847 #endif 1848 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1849 /* Possibly switch between BNDCFGS and BNDCFGU */ 1850 cpu_sync_bndcs_hflags(env); 1851 } 1852 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1853 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1854 if (env->hflags & HF_CS64_MASK) { 1855 /* zero base assumed for DS, ES and SS in long mode */ 1856 } else if (!(env->cr[0] & CR0_PE_MASK) || 1857 (env->eflags & VM_MASK) || 1858 !(env->hflags & HF_CS32_MASK)) { 1859 /* XXX: try to avoid this test. The problem comes from the 1860 fact that is real mode or vm86 mode we only modify the 1861 'base' and 'selector' fields of the segment cache to go 1862 faster. A solution may be to force addseg to one in 1863 translate-i386.c. */ 1864 new_hflags |= HF_ADDSEG_MASK; 1865 } else { 1866 new_hflags |= ((env->segs[R_DS].base | 1867 env->segs[R_ES].base | 1868 env->segs[R_SS].base) != 0) << 1869 HF_ADDSEG_SHIFT; 1870 } 1871 env->hflags = (env->hflags & 1872 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1873 } 1874 } 1875 1876 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1877 uint8_t sipi_vector) 1878 { 1879 CPUState *cs = CPU(cpu); 1880 CPUX86State *env = &cpu->env; 1881 1882 env->eip = 0; 1883 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1884 sipi_vector << 12, 1885 env->segs[R_CS].limit, 1886 env->segs[R_CS].flags); 1887 cs->halted = 0; 1888 } 1889 1890 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1891 target_ulong *base, unsigned int *limit, 1892 unsigned int *flags); 1893 1894 /* op_helper.c */ 1895 /* used for debug or cpu save/restore */ 1896 1897 /* cpu-exec.c */ 1898 /* the following helpers are only usable in user mode simulation as 1899 they can trigger unexpected exceptions */ 1900 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1901 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1902 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1903 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1904 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1905 1906 /* you can call this signal handler from your SIGBUS and SIGSEGV 1907 signal handlers to inform the virtual CPU of exceptions. non zero 1908 is returned if the signal was handled by the virtual CPU. */ 1909 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1910 void *puc); 1911 1912 /* cpu.c */ 1913 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1914 uint32_t *eax, uint32_t *ebx, 1915 uint32_t *ecx, uint32_t *edx); 1916 void cpu_clear_apic_feature(CPUX86State *env); 1917 void host_cpuid(uint32_t function, uint32_t count, 1918 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1919 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1920 bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type); 1921 1922 /* helper.c */ 1923 bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1924 MMUAccessType access_type, int mmu_idx, 1925 bool probe, uintptr_t retaddr); 1926 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1927 1928 #ifndef CONFIG_USER_ONLY 1929 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1930 { 1931 return !!attrs.secure; 1932 } 1933 1934 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1935 { 1936 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1937 } 1938 1939 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1940 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1941 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1942 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1943 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1944 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1945 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1946 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1947 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1948 #endif 1949 1950 void breakpoint_handler(CPUState *cs); 1951 1952 /* will be suppressed */ 1953 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1954 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1955 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1956 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1957 1958 /* hw/pc.c */ 1959 uint64_t cpu_get_tsc(CPUX86State *env); 1960 1961 /* XXX: This value should match the one returned by CPUID 1962 * and in exec.c */ 1963 # if defined(TARGET_X86_64) 1964 # define TCG_PHYS_ADDR_BITS 40 1965 # else 1966 # define TCG_PHYS_ADDR_BITS 36 1967 # endif 1968 1969 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1970 1971 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1972 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1973 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1974 1975 #ifdef TARGET_X86_64 1976 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1977 #else 1978 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1979 #endif 1980 1981 #define cpu_signal_handler cpu_x86_signal_handler 1982 #define cpu_list x86_cpu_list 1983 1984 /* MMU modes definitions */ 1985 #define MMU_KSMAP_IDX 0 1986 #define MMU_USER_IDX 1 1987 #define MMU_KNOSMAP_IDX 2 1988 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1989 { 1990 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1991 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1992 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1993 } 1994 1995 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1996 { 1997 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1998 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1999 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2000 } 2001 2002 #define CC_DST (env->cc_dst) 2003 #define CC_SRC (env->cc_src) 2004 #define CC_SRC2 (env->cc_src2) 2005 #define CC_OP (env->cc_op) 2006 2007 /* n must be a constant to be efficient */ 2008 static inline target_long lshift(target_long x, int n) 2009 { 2010 if (n >= 0) { 2011 return x << n; 2012 } else { 2013 return x >> (-n); 2014 } 2015 } 2016 2017 /* float macros */ 2018 #define FT0 (env->ft0) 2019 #define ST0 (env->fpregs[env->fpstt].d) 2020 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 2021 #define ST1 ST(1) 2022 2023 /* translate.c */ 2024 void tcg_x86_init(void); 2025 2026 typedef CPUX86State CPUArchState; 2027 typedef X86CPU ArchCPU; 2028 2029 #include "exec/cpu-all.h" 2030 #include "svm.h" 2031 2032 #if !defined(CONFIG_USER_ONLY) 2033 #include "hw/i386/apic.h" 2034 #endif 2035 2036 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2037 target_ulong *cs_base, uint32_t *flags) 2038 { 2039 *cs_base = env->segs[R_CS].base; 2040 *pc = *cs_base + env->eip; 2041 *flags = env->hflags | 2042 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2043 } 2044 2045 void do_cpu_init(X86CPU *cpu); 2046 void do_cpu_sipi(X86CPU *cpu); 2047 2048 #define MCE_INJECT_BROADCAST 1 2049 #define MCE_INJECT_UNCOND_AO 2 2050 2051 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2052 uint64_t status, uint64_t mcg_status, uint64_t addr, 2053 uint64_t misc, int flags); 2054 2055 /* excp_helper.c */ 2056 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 2057 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 2058 uintptr_t retaddr); 2059 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 2060 int error_code); 2061 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 2062 int error_code, uintptr_t retaddr); 2063 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 2064 int error_code, int next_eip_addend); 2065 2066 /* cc_helper.c */ 2067 extern const uint8_t parity_table[256]; 2068 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2069 2070 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2071 { 2072 uint32_t eflags = env->eflags; 2073 if (tcg_enabled()) { 2074 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 2075 } 2076 return eflags; 2077 } 2078 2079 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 2080 * after generating a call to a helper that uses this. 2081 */ 2082 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 2083 int update_mask) 2084 { 2085 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 2086 CC_OP = CC_OP_EFLAGS; 2087 env->df = 1 - (2 * ((eflags >> 10) & 1)); 2088 env->eflags = (env->eflags & ~update_mask) | 2089 (eflags & update_mask) | 0x2; 2090 } 2091 2092 /* load efer and update the corresponding hflags. XXX: do consistency 2093 checks with cpuid bits? */ 2094 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 2095 { 2096 env->efer = val; 2097 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 2098 if (env->efer & MSR_EFER_LMA) { 2099 env->hflags |= HF_LMA_MASK; 2100 } 2101 if (env->efer & MSR_EFER_SVME) { 2102 env->hflags |= HF_SVME_MASK; 2103 } 2104 } 2105 2106 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2107 { 2108 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2109 } 2110 2111 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2112 { 2113 if (env->hflags & HF_SMM_MASK) { 2114 return -1; 2115 } else { 2116 return env->a20_mask; 2117 } 2118 } 2119 2120 static inline bool cpu_has_vmx(CPUX86State *env) 2121 { 2122 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2123 } 2124 2125 static inline bool cpu_has_svm(CPUX86State *env) 2126 { 2127 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2128 } 2129 2130 /* 2131 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2132 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2133 * VMX operation. This is because CR4.VMXE is one of the bits set 2134 * in MSR_IA32_VMX_CR4_FIXED1. 2135 * 2136 * There is one exception to above statement when vCPU enters SMM mode. 2137 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2138 * may also reset CR4.VMXE during execution in SMM mode. 2139 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2140 * and CR4.VMXE is restored to it's original value of being set. 2141 * 2142 * Therefore, when vCPU is not in SMM mode, we can infer whether 2143 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2144 * know for certain. 2145 */ 2146 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2147 { 2148 return cpu_has_vmx(env) && 2149 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2150 } 2151 2152 /* fpu_helper.c */ 2153 void update_fp_status(CPUX86State *env); 2154 void update_mxcsr_status(CPUX86State *env); 2155 void update_mxcsr_from_sse_status(CPUX86State *env); 2156 2157 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2158 { 2159 env->mxcsr = mxcsr; 2160 if (tcg_enabled()) { 2161 update_mxcsr_status(env); 2162 } 2163 } 2164 2165 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2166 { 2167 env->fpuc = fpuc; 2168 if (tcg_enabled()) { 2169 update_fp_status(env); 2170 } 2171 } 2172 2173 /* mem_helper.c */ 2174 void helper_lock_init(void); 2175 2176 /* svm_helper.c */ 2177 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2178 uint64_t param, uintptr_t retaddr); 2179 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, 2180 uint64_t exit_info_1, uintptr_t retaddr); 2181 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 2182 2183 /* seg_helper.c */ 2184 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 2185 2186 /* smm_helper.c */ 2187 void do_smm_enter(X86CPU *cpu); 2188 2189 /* apic.c */ 2190 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2191 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2192 TPRAccess access); 2193 2194 2195 /* Change the value of a KVM-specific default 2196 * 2197 * If value is NULL, no default will be set and the original 2198 * value from the CPU model table will be kept. 2199 * 2200 * It is valid to call this function only for properties that 2201 * are already present in the kvm_default_props table. 2202 */ 2203 void x86_cpu_change_kvm_default(const char *prop, const char *value); 2204 2205 /* Special values for X86CPUVersion: */ 2206 2207 /* Resolve to latest CPU version */ 2208 #define CPU_VERSION_LATEST -1 2209 2210 /* 2211 * Resolve to version defined by current machine type. 2212 * See x86_cpu_set_default_version() 2213 */ 2214 #define CPU_VERSION_AUTO -2 2215 2216 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2217 #define CPU_VERSION_LEGACY 0 2218 2219 typedef int X86CPUVersion; 2220 2221 /* 2222 * Set default CPU model version for CPU models having 2223 * version == CPU_VERSION_AUTO. 2224 */ 2225 void x86_cpu_set_default_version(X86CPUVersion version); 2226 2227 /* Return name of 32-bit register, from a R_* constant */ 2228 const char *get_register_name_32(unsigned int reg); 2229 2230 void enable_compat_apic_id_mode(void); 2231 2232 #define APIC_DEFAULT_ADDRESS 0xfee00000 2233 #define APIC_SPACE_SIZE 0x100000 2234 2235 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2236 2237 /* cpu.c */ 2238 bool cpu_is_bsp(X86CPU *cpu); 2239 2240 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 2241 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 2242 void x86_update_hflags(CPUX86State* env); 2243 2244 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2245 { 2246 return !!(cpu->hyperv_features & BIT(feat)); 2247 } 2248 2249 #if defined(TARGET_X86_64) && \ 2250 defined(CONFIG_USER_ONLY) && \ 2251 defined(CONFIG_LINUX) 2252 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2253 #endif 2254 2255 #endif /* I386_CPU_H */ 2256