1 2 /* 3 * i386 virtual CPU header 4 * 5 * Copyright (c) 2003 Fabrice Bellard 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef I386_CPU_H 22 #define I386_CPU_H 23 24 #include "qemu-common.h" 25 #include "cpu-qom.h" 26 #include "hyperv-proto.h" 27 28 #ifdef TARGET_X86_64 29 #define TARGET_LONG_BITS 64 30 #else 31 #define TARGET_LONG_BITS 32 32 #endif 33 34 #include "exec/cpu-defs.h" 35 36 /* The x86 has a strong memory model with some store-after-load re-ordering */ 37 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 38 39 /* Maximum instruction code size */ 40 #define TARGET_MAX_INSN_SIZE 16 41 42 /* support for self modifying code even if the modified instruction is 43 close to the modifying instruction */ 44 #define TARGET_HAS_PRECISE_SMC 45 46 #ifdef TARGET_X86_64 47 #define I386_ELF_MACHINE EM_X86_64 48 #define ELF_MACHINE_UNAME "x86_64" 49 #else 50 #define I386_ELF_MACHINE EM_386 51 #define ELF_MACHINE_UNAME "i686" 52 #endif 53 54 #define CPUArchState struct CPUX86State 55 56 enum { 57 R_EAX = 0, 58 R_ECX = 1, 59 R_EDX = 2, 60 R_EBX = 3, 61 R_ESP = 4, 62 R_EBP = 5, 63 R_ESI = 6, 64 R_EDI = 7, 65 R_R8 = 8, 66 R_R9 = 9, 67 R_R10 = 10, 68 R_R11 = 11, 69 R_R12 = 12, 70 R_R13 = 13, 71 R_R14 = 14, 72 R_R15 = 15, 73 74 R_AL = 0, 75 R_CL = 1, 76 R_DL = 2, 77 R_BL = 3, 78 R_AH = 4, 79 R_CH = 5, 80 R_DH = 6, 81 R_BH = 7, 82 }; 83 84 typedef enum X86Seg { 85 R_ES = 0, 86 R_CS = 1, 87 R_SS = 2, 88 R_DS = 3, 89 R_FS = 4, 90 R_GS = 5, 91 R_LDTR = 6, 92 R_TR = 7, 93 } X86Seg; 94 95 /* segment descriptor fields */ 96 #define DESC_G_SHIFT 23 97 #define DESC_G_MASK (1 << DESC_G_SHIFT) 98 #define DESC_B_SHIFT 22 99 #define DESC_B_MASK (1 << DESC_B_SHIFT) 100 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 101 #define DESC_L_MASK (1 << DESC_L_SHIFT) 102 #define DESC_AVL_SHIFT 20 103 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 104 #define DESC_P_SHIFT 15 105 #define DESC_P_MASK (1 << DESC_P_SHIFT) 106 #define DESC_DPL_SHIFT 13 107 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 108 #define DESC_S_SHIFT 12 109 #define DESC_S_MASK (1 << DESC_S_SHIFT) 110 #define DESC_TYPE_SHIFT 8 111 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 112 #define DESC_A_MASK (1 << 8) 113 114 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 115 #define DESC_C_MASK (1 << 10) /* code: conforming */ 116 #define DESC_R_MASK (1 << 9) /* code: readable */ 117 118 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 119 #define DESC_W_MASK (1 << 9) /* data: writable */ 120 121 #define DESC_TSS_BUSY_MASK (1 << 9) 122 123 /* eflags masks */ 124 #define CC_C 0x0001 125 #define CC_P 0x0004 126 #define CC_A 0x0010 127 #define CC_Z 0x0040 128 #define CC_S 0x0080 129 #define CC_O 0x0800 130 131 #define TF_SHIFT 8 132 #define IOPL_SHIFT 12 133 #define VM_SHIFT 17 134 135 #define TF_MASK 0x00000100 136 #define IF_MASK 0x00000200 137 #define DF_MASK 0x00000400 138 #define IOPL_MASK 0x00003000 139 #define NT_MASK 0x00004000 140 #define RF_MASK 0x00010000 141 #define VM_MASK 0x00020000 142 #define AC_MASK 0x00040000 143 #define VIF_MASK 0x00080000 144 #define VIP_MASK 0x00100000 145 #define ID_MASK 0x00200000 146 147 /* hidden flags - used internally by qemu to represent additional cpu 148 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 149 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 150 positions to ease oring with eflags. */ 151 /* current cpl */ 152 #define HF_CPL_SHIFT 0 153 /* true if hardware interrupts must be disabled for next instruction */ 154 #define HF_INHIBIT_IRQ_SHIFT 3 155 /* 16 or 32 segments */ 156 #define HF_CS32_SHIFT 4 157 #define HF_SS32_SHIFT 5 158 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 159 #define HF_ADDSEG_SHIFT 6 160 /* copy of CR0.PE (protected mode) */ 161 #define HF_PE_SHIFT 7 162 #define HF_TF_SHIFT 8 /* must be same as eflags */ 163 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 164 #define HF_EM_SHIFT 10 165 #define HF_TS_SHIFT 11 166 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 167 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 168 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 169 #define HF_RF_SHIFT 16 /* must be same as eflags */ 170 #define HF_VM_SHIFT 17 /* must be same as eflags */ 171 #define HF_AC_SHIFT 18 /* must be same as eflags */ 172 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 173 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 174 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 175 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 176 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 177 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 178 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 179 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 180 181 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 182 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 183 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 184 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 185 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 186 #define HF_PE_MASK (1 << HF_PE_SHIFT) 187 #define HF_TF_MASK (1 << HF_TF_SHIFT) 188 #define HF_MP_MASK (1 << HF_MP_SHIFT) 189 #define HF_EM_MASK (1 << HF_EM_SHIFT) 190 #define HF_TS_MASK (1 << HF_TS_SHIFT) 191 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 192 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 193 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 194 #define HF_RF_MASK (1 << HF_RF_SHIFT) 195 #define HF_VM_MASK (1 << HF_VM_SHIFT) 196 #define HF_AC_MASK (1 << HF_AC_SHIFT) 197 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 198 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 199 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 200 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 201 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 202 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 203 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 204 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 205 206 /* hflags2 */ 207 208 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 209 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 210 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 211 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 212 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 213 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 214 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 215 216 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 217 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 218 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 219 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 220 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 221 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 222 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 223 224 #define CR0_PE_SHIFT 0 225 #define CR0_MP_SHIFT 1 226 227 #define CR0_PE_MASK (1U << 0) 228 #define CR0_MP_MASK (1U << 1) 229 #define CR0_EM_MASK (1U << 2) 230 #define CR0_TS_MASK (1U << 3) 231 #define CR0_ET_MASK (1U << 4) 232 #define CR0_NE_MASK (1U << 5) 233 #define CR0_WP_MASK (1U << 16) 234 #define CR0_AM_MASK (1U << 18) 235 #define CR0_PG_MASK (1U << 31) 236 237 #define CR4_VME_MASK (1U << 0) 238 #define CR4_PVI_MASK (1U << 1) 239 #define CR4_TSD_MASK (1U << 2) 240 #define CR4_DE_MASK (1U << 3) 241 #define CR4_PSE_MASK (1U << 4) 242 #define CR4_PAE_MASK (1U << 5) 243 #define CR4_MCE_MASK (1U << 6) 244 #define CR4_PGE_MASK (1U << 7) 245 #define CR4_PCE_MASK (1U << 8) 246 #define CR4_OSFXSR_SHIFT 9 247 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 248 #define CR4_OSXMMEXCPT_MASK (1U << 10) 249 #define CR4_LA57_MASK (1U << 12) 250 #define CR4_VMXE_MASK (1U << 13) 251 #define CR4_SMXE_MASK (1U << 14) 252 #define CR4_FSGSBASE_MASK (1U << 16) 253 #define CR4_PCIDE_MASK (1U << 17) 254 #define CR4_OSXSAVE_MASK (1U << 18) 255 #define CR4_SMEP_MASK (1U << 20) 256 #define CR4_SMAP_MASK (1U << 21) 257 #define CR4_PKE_MASK (1U << 22) 258 259 #define DR6_BD (1 << 13) 260 #define DR6_BS (1 << 14) 261 #define DR6_BT (1 << 15) 262 #define DR6_FIXED_1 0xffff0ff0 263 264 #define DR7_GD (1 << 13) 265 #define DR7_TYPE_SHIFT 16 266 #define DR7_LEN_SHIFT 18 267 #define DR7_FIXED_1 0x00000400 268 #define DR7_GLOBAL_BP_MASK 0xaa 269 #define DR7_LOCAL_BP_MASK 0x55 270 #define DR7_MAX_BP 4 271 #define DR7_TYPE_BP_INST 0x0 272 #define DR7_TYPE_DATA_WR 0x1 273 #define DR7_TYPE_IO_RW 0x2 274 #define DR7_TYPE_DATA_RW 0x3 275 276 #define PG_PRESENT_BIT 0 277 #define PG_RW_BIT 1 278 #define PG_USER_BIT 2 279 #define PG_PWT_BIT 3 280 #define PG_PCD_BIT 4 281 #define PG_ACCESSED_BIT 5 282 #define PG_DIRTY_BIT 6 283 #define PG_PSE_BIT 7 284 #define PG_GLOBAL_BIT 8 285 #define PG_PSE_PAT_BIT 12 286 #define PG_PKRU_BIT 59 287 #define PG_NX_BIT 63 288 289 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 290 #define PG_RW_MASK (1 << PG_RW_BIT) 291 #define PG_USER_MASK (1 << PG_USER_BIT) 292 #define PG_PWT_MASK (1 << PG_PWT_BIT) 293 #define PG_PCD_MASK (1 << PG_PCD_BIT) 294 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 295 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 296 #define PG_PSE_MASK (1 << PG_PSE_BIT) 297 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 298 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 299 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 300 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 301 #define PG_HI_USER_MASK 0x7ff0000000000000LL 302 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 303 #define PG_NX_MASK (1ULL << PG_NX_BIT) 304 305 #define PG_ERROR_W_BIT 1 306 307 #define PG_ERROR_P_MASK 0x01 308 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 309 #define PG_ERROR_U_MASK 0x04 310 #define PG_ERROR_RSVD_MASK 0x08 311 #define PG_ERROR_I_D_MASK 0x10 312 #define PG_ERROR_PK_MASK 0x20 313 314 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 315 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 316 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 317 318 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 319 #define MCE_BANKS_DEF 10 320 321 #define MCG_CAP_BANKS_MASK 0xff 322 323 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 324 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 325 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 326 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 327 328 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 329 330 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 331 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 332 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 333 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 334 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 335 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 336 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 337 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 338 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 339 340 /* MISC register defines */ 341 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 342 #define MCM_ADDR_LINEAR 1 /* linear address */ 343 #define MCM_ADDR_PHYS 2 /* physical address */ 344 #define MCM_ADDR_MEM 3 /* memory address */ 345 #define MCM_ADDR_GENERIC 7 /* generic */ 346 347 #define MSR_IA32_TSC 0x10 348 #define MSR_IA32_APICBASE 0x1b 349 #define MSR_IA32_APICBASE_BSP (1<<8) 350 #define MSR_IA32_APICBASE_ENABLE (1<<11) 351 #define MSR_IA32_APICBASE_EXTD (1 << 10) 352 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 353 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 354 #define MSR_TSC_ADJUST 0x0000003b 355 #define MSR_IA32_SPEC_CTRL 0x48 356 #define MSR_VIRT_SSBD 0xc001011f 357 #define MSR_IA32_TSCDEADLINE 0x6e0 358 359 #define FEATURE_CONTROL_LOCKED (1<<0) 360 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 361 #define FEATURE_CONTROL_LMCE (1<<20) 362 363 #define MSR_P6_PERFCTR0 0xc1 364 365 #define MSR_IA32_SMBASE 0x9e 366 #define MSR_SMI_COUNT 0x34 367 #define MSR_MTRRcap 0xfe 368 #define MSR_MTRRcap_VCNT 8 369 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 370 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 371 372 #define MSR_IA32_SYSENTER_CS 0x174 373 #define MSR_IA32_SYSENTER_ESP 0x175 374 #define MSR_IA32_SYSENTER_EIP 0x176 375 376 #define MSR_MCG_CAP 0x179 377 #define MSR_MCG_STATUS 0x17a 378 #define MSR_MCG_CTL 0x17b 379 #define MSR_MCG_EXT_CTL 0x4d0 380 381 #define MSR_P6_EVNTSEL0 0x186 382 383 #define MSR_IA32_PERF_STATUS 0x198 384 385 #define MSR_IA32_MISC_ENABLE 0x1a0 386 /* Indicates good rep/movs microcode on some processors: */ 387 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 388 389 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 390 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 391 392 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 393 394 #define MSR_MTRRfix64K_00000 0x250 395 #define MSR_MTRRfix16K_80000 0x258 396 #define MSR_MTRRfix16K_A0000 0x259 397 #define MSR_MTRRfix4K_C0000 0x268 398 #define MSR_MTRRfix4K_C8000 0x269 399 #define MSR_MTRRfix4K_D0000 0x26a 400 #define MSR_MTRRfix4K_D8000 0x26b 401 #define MSR_MTRRfix4K_E0000 0x26c 402 #define MSR_MTRRfix4K_E8000 0x26d 403 #define MSR_MTRRfix4K_F0000 0x26e 404 #define MSR_MTRRfix4K_F8000 0x26f 405 406 #define MSR_PAT 0x277 407 408 #define MSR_MTRRdefType 0x2ff 409 410 #define MSR_CORE_PERF_FIXED_CTR0 0x309 411 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 412 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 413 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 414 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 415 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 416 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 417 418 #define MSR_MC0_CTL 0x400 419 #define MSR_MC0_STATUS 0x401 420 #define MSR_MC0_ADDR 0x402 421 #define MSR_MC0_MISC 0x403 422 423 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 424 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 425 #define MSR_IA32_RTIT_CTL 0x570 426 #define MSR_IA32_RTIT_STATUS 0x571 427 #define MSR_IA32_RTIT_CR3_MATCH 0x572 428 #define MSR_IA32_RTIT_ADDR0_A 0x580 429 #define MSR_IA32_RTIT_ADDR0_B 0x581 430 #define MSR_IA32_RTIT_ADDR1_A 0x582 431 #define MSR_IA32_RTIT_ADDR1_B 0x583 432 #define MSR_IA32_RTIT_ADDR2_A 0x584 433 #define MSR_IA32_RTIT_ADDR2_B 0x585 434 #define MSR_IA32_RTIT_ADDR3_A 0x586 435 #define MSR_IA32_RTIT_ADDR3_B 0x587 436 #define MAX_RTIT_ADDRS 8 437 438 #define MSR_EFER 0xc0000080 439 440 #define MSR_EFER_SCE (1 << 0) 441 #define MSR_EFER_LME (1 << 8) 442 #define MSR_EFER_LMA (1 << 10) 443 #define MSR_EFER_NXE (1 << 11) 444 #define MSR_EFER_SVME (1 << 12) 445 #define MSR_EFER_FFXSR (1 << 14) 446 447 #define MSR_STAR 0xc0000081 448 #define MSR_LSTAR 0xc0000082 449 #define MSR_CSTAR 0xc0000083 450 #define MSR_FMASK 0xc0000084 451 #define MSR_FSBASE 0xc0000100 452 #define MSR_GSBASE 0xc0000101 453 #define MSR_KERNELGSBASE 0xc0000102 454 #define MSR_TSC_AUX 0xc0000103 455 456 #define MSR_VM_HSAVE_PA 0xc0010117 457 458 #define MSR_IA32_BNDCFGS 0x00000d90 459 #define MSR_IA32_XSS 0x00000da0 460 461 #define XSTATE_FP_BIT 0 462 #define XSTATE_SSE_BIT 1 463 #define XSTATE_YMM_BIT 2 464 #define XSTATE_BNDREGS_BIT 3 465 #define XSTATE_BNDCSR_BIT 4 466 #define XSTATE_OPMASK_BIT 5 467 #define XSTATE_ZMM_Hi256_BIT 6 468 #define XSTATE_Hi16_ZMM_BIT 7 469 #define XSTATE_PKRU_BIT 9 470 471 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 472 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 473 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 474 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 475 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 476 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 477 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 478 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 479 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 480 481 /* CPUID feature words */ 482 typedef enum FeatureWord { 483 FEAT_1_EDX, /* CPUID[1].EDX */ 484 FEAT_1_ECX, /* CPUID[1].ECX */ 485 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 486 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 487 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 488 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 489 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 490 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 491 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 492 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 493 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 494 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 495 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 496 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 497 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 498 FEAT_SVM, /* CPUID[8000_000A].EDX */ 499 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 500 FEAT_6_EAX, /* CPUID[6].EAX */ 501 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 502 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 503 FEATURE_WORDS, 504 } FeatureWord; 505 506 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 507 508 /* cpuid_features bits */ 509 #define CPUID_FP87 (1U << 0) 510 #define CPUID_VME (1U << 1) 511 #define CPUID_DE (1U << 2) 512 #define CPUID_PSE (1U << 3) 513 #define CPUID_TSC (1U << 4) 514 #define CPUID_MSR (1U << 5) 515 #define CPUID_PAE (1U << 6) 516 #define CPUID_MCE (1U << 7) 517 #define CPUID_CX8 (1U << 8) 518 #define CPUID_APIC (1U << 9) 519 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 520 #define CPUID_MTRR (1U << 12) 521 #define CPUID_PGE (1U << 13) 522 #define CPUID_MCA (1U << 14) 523 #define CPUID_CMOV (1U << 15) 524 #define CPUID_PAT (1U << 16) 525 #define CPUID_PSE36 (1U << 17) 526 #define CPUID_PN (1U << 18) 527 #define CPUID_CLFLUSH (1U << 19) 528 #define CPUID_DTS (1U << 21) 529 #define CPUID_ACPI (1U << 22) 530 #define CPUID_MMX (1U << 23) 531 #define CPUID_FXSR (1U << 24) 532 #define CPUID_SSE (1U << 25) 533 #define CPUID_SSE2 (1U << 26) 534 #define CPUID_SS (1U << 27) 535 #define CPUID_HT (1U << 28) 536 #define CPUID_TM (1U << 29) 537 #define CPUID_IA64 (1U << 30) 538 #define CPUID_PBE (1U << 31) 539 540 #define CPUID_EXT_SSE3 (1U << 0) 541 #define CPUID_EXT_PCLMULQDQ (1U << 1) 542 #define CPUID_EXT_DTES64 (1U << 2) 543 #define CPUID_EXT_MONITOR (1U << 3) 544 #define CPUID_EXT_DSCPL (1U << 4) 545 #define CPUID_EXT_VMX (1U << 5) 546 #define CPUID_EXT_SMX (1U << 6) 547 #define CPUID_EXT_EST (1U << 7) 548 #define CPUID_EXT_TM2 (1U << 8) 549 #define CPUID_EXT_SSSE3 (1U << 9) 550 #define CPUID_EXT_CID (1U << 10) 551 #define CPUID_EXT_FMA (1U << 12) 552 #define CPUID_EXT_CX16 (1U << 13) 553 #define CPUID_EXT_XTPR (1U << 14) 554 #define CPUID_EXT_PDCM (1U << 15) 555 #define CPUID_EXT_PCID (1U << 17) 556 #define CPUID_EXT_DCA (1U << 18) 557 #define CPUID_EXT_SSE41 (1U << 19) 558 #define CPUID_EXT_SSE42 (1U << 20) 559 #define CPUID_EXT_X2APIC (1U << 21) 560 #define CPUID_EXT_MOVBE (1U << 22) 561 #define CPUID_EXT_POPCNT (1U << 23) 562 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 563 #define CPUID_EXT_AES (1U << 25) 564 #define CPUID_EXT_XSAVE (1U << 26) 565 #define CPUID_EXT_OSXSAVE (1U << 27) 566 #define CPUID_EXT_AVX (1U << 28) 567 #define CPUID_EXT_F16C (1U << 29) 568 #define CPUID_EXT_RDRAND (1U << 30) 569 #define CPUID_EXT_HYPERVISOR (1U << 31) 570 571 #define CPUID_EXT2_FPU (1U << 0) 572 #define CPUID_EXT2_VME (1U << 1) 573 #define CPUID_EXT2_DE (1U << 2) 574 #define CPUID_EXT2_PSE (1U << 3) 575 #define CPUID_EXT2_TSC (1U << 4) 576 #define CPUID_EXT2_MSR (1U << 5) 577 #define CPUID_EXT2_PAE (1U << 6) 578 #define CPUID_EXT2_MCE (1U << 7) 579 #define CPUID_EXT2_CX8 (1U << 8) 580 #define CPUID_EXT2_APIC (1U << 9) 581 #define CPUID_EXT2_SYSCALL (1U << 11) 582 #define CPUID_EXT2_MTRR (1U << 12) 583 #define CPUID_EXT2_PGE (1U << 13) 584 #define CPUID_EXT2_MCA (1U << 14) 585 #define CPUID_EXT2_CMOV (1U << 15) 586 #define CPUID_EXT2_PAT (1U << 16) 587 #define CPUID_EXT2_PSE36 (1U << 17) 588 #define CPUID_EXT2_MP (1U << 19) 589 #define CPUID_EXT2_NX (1U << 20) 590 #define CPUID_EXT2_MMXEXT (1U << 22) 591 #define CPUID_EXT2_MMX (1U << 23) 592 #define CPUID_EXT2_FXSR (1U << 24) 593 #define CPUID_EXT2_FFXSR (1U << 25) 594 #define CPUID_EXT2_PDPE1GB (1U << 26) 595 #define CPUID_EXT2_RDTSCP (1U << 27) 596 #define CPUID_EXT2_LM (1U << 29) 597 #define CPUID_EXT2_3DNOWEXT (1U << 30) 598 #define CPUID_EXT2_3DNOW (1U << 31) 599 600 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 601 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 602 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 603 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 604 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 605 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 606 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 607 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 608 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 609 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 610 611 #define CPUID_EXT3_LAHF_LM (1U << 0) 612 #define CPUID_EXT3_CMP_LEG (1U << 1) 613 #define CPUID_EXT3_SVM (1U << 2) 614 #define CPUID_EXT3_EXTAPIC (1U << 3) 615 #define CPUID_EXT3_CR8LEG (1U << 4) 616 #define CPUID_EXT3_ABM (1U << 5) 617 #define CPUID_EXT3_SSE4A (1U << 6) 618 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 619 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 620 #define CPUID_EXT3_OSVW (1U << 9) 621 #define CPUID_EXT3_IBS (1U << 10) 622 #define CPUID_EXT3_XOP (1U << 11) 623 #define CPUID_EXT3_SKINIT (1U << 12) 624 #define CPUID_EXT3_WDT (1U << 13) 625 #define CPUID_EXT3_LWP (1U << 15) 626 #define CPUID_EXT3_FMA4 (1U << 16) 627 #define CPUID_EXT3_TCE (1U << 17) 628 #define CPUID_EXT3_NODEID (1U << 19) 629 #define CPUID_EXT3_TBM (1U << 21) 630 #define CPUID_EXT3_TOPOEXT (1U << 22) 631 #define CPUID_EXT3_PERFCORE (1U << 23) 632 #define CPUID_EXT3_PERFNB (1U << 24) 633 634 #define CPUID_SVM_NPT (1U << 0) 635 #define CPUID_SVM_LBRV (1U << 1) 636 #define CPUID_SVM_SVMLOCK (1U << 2) 637 #define CPUID_SVM_NRIPSAVE (1U << 3) 638 #define CPUID_SVM_TSCSCALE (1U << 4) 639 #define CPUID_SVM_VMCBCLEAN (1U << 5) 640 #define CPUID_SVM_FLUSHASID (1U << 6) 641 #define CPUID_SVM_DECODEASSIST (1U << 7) 642 #define CPUID_SVM_PAUSEFILTER (1U << 10) 643 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 644 645 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 646 #define CPUID_7_0_EBX_BMI1 (1U << 3) 647 #define CPUID_7_0_EBX_HLE (1U << 4) 648 #define CPUID_7_0_EBX_AVX2 (1U << 5) 649 #define CPUID_7_0_EBX_SMEP (1U << 7) 650 #define CPUID_7_0_EBX_BMI2 (1U << 8) 651 #define CPUID_7_0_EBX_ERMS (1U << 9) 652 #define CPUID_7_0_EBX_INVPCID (1U << 10) 653 #define CPUID_7_0_EBX_RTM (1U << 11) 654 #define CPUID_7_0_EBX_MPX (1U << 14) 655 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 656 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 657 #define CPUID_7_0_EBX_RDSEED (1U << 18) 658 #define CPUID_7_0_EBX_ADX (1U << 19) 659 #define CPUID_7_0_EBX_SMAP (1U << 20) 660 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 661 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 662 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 663 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 664 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */ 665 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 666 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 667 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 668 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 669 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 670 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 671 672 #define CPUID_7_0_ECX_AVX512BMI (1U << 1) 673 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 674 #define CPUID_7_0_ECX_UMIP (1U << 2) 675 #define CPUID_7_0_ECX_PKU (1U << 3) 676 #define CPUID_7_0_ECX_OSPKE (1U << 4) 677 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ 678 #define CPUID_7_0_ECX_GFNI (1U << 8) 679 #define CPUID_7_0_ECX_VAES (1U << 9) 680 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 681 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 682 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 683 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 684 #define CPUID_7_0_ECX_LA57 (1U << 16) 685 #define CPUID_7_0_ECX_RDPID (1U << 22) 686 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ 687 688 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 689 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 690 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ 691 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ 692 693 #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ 694 695 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 696 #define CPUID_XSAVE_XSAVEC (1U << 1) 697 #define CPUID_XSAVE_XGETBV1 (1U << 2) 698 #define CPUID_XSAVE_XSAVES (1U << 3) 699 700 #define CPUID_6_EAX_ARAT (1U << 2) 701 702 /* CPUID[0x80000007].EDX flags: */ 703 #define CPUID_APM_INVTSC (1U << 8) 704 705 #define CPUID_VENDOR_SZ 12 706 707 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 708 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 709 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 710 #define CPUID_VENDOR_INTEL "GenuineIntel" 711 712 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 713 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 714 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 715 #define CPUID_VENDOR_AMD "AuthenticAMD" 716 717 #define CPUID_VENDOR_VIA "CentaurHauls" 718 719 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 720 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 721 722 /* CPUID[0xB].ECX level types */ 723 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 724 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 725 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 726 727 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 728 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 729 #endif 730 731 #define EXCP00_DIVZ 0 732 #define EXCP01_DB 1 733 #define EXCP02_NMI 2 734 #define EXCP03_INT3 3 735 #define EXCP04_INTO 4 736 #define EXCP05_BOUND 5 737 #define EXCP06_ILLOP 6 738 #define EXCP07_PREX 7 739 #define EXCP08_DBLE 8 740 #define EXCP09_XERR 9 741 #define EXCP0A_TSS 10 742 #define EXCP0B_NOSEG 11 743 #define EXCP0C_STACK 12 744 #define EXCP0D_GPF 13 745 #define EXCP0E_PAGE 14 746 #define EXCP10_COPR 16 747 #define EXCP11_ALGN 17 748 #define EXCP12_MCHK 18 749 750 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 751 for syscall instruction */ 752 #define EXCP_VMEXIT 0x100 753 754 /* i386-specific interrupt pending bits. */ 755 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 756 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 757 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 758 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 759 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 760 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 761 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 762 763 /* Use a clearer name for this. */ 764 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 765 766 /* Instead of computing the condition codes after each x86 instruction, 767 * QEMU just stores one operand (called CC_SRC), the result 768 * (called CC_DST) and the type of operation (called CC_OP). When the 769 * condition codes are needed, the condition codes can be calculated 770 * using this information. Condition codes are not generated if they 771 * are only needed for conditional branches. 772 */ 773 typedef enum { 774 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 775 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 776 777 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 778 CC_OP_MULW, 779 CC_OP_MULL, 780 CC_OP_MULQ, 781 782 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 783 CC_OP_ADDW, 784 CC_OP_ADDL, 785 CC_OP_ADDQ, 786 787 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 788 CC_OP_ADCW, 789 CC_OP_ADCL, 790 CC_OP_ADCQ, 791 792 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 793 CC_OP_SUBW, 794 CC_OP_SUBL, 795 CC_OP_SUBQ, 796 797 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 798 CC_OP_SBBW, 799 CC_OP_SBBL, 800 CC_OP_SBBQ, 801 802 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 803 CC_OP_LOGICW, 804 CC_OP_LOGICL, 805 CC_OP_LOGICQ, 806 807 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 808 CC_OP_INCW, 809 CC_OP_INCL, 810 CC_OP_INCQ, 811 812 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 813 CC_OP_DECW, 814 CC_OP_DECL, 815 CC_OP_DECQ, 816 817 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 818 CC_OP_SHLW, 819 CC_OP_SHLL, 820 CC_OP_SHLQ, 821 822 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 823 CC_OP_SARW, 824 CC_OP_SARL, 825 CC_OP_SARQ, 826 827 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 828 CC_OP_BMILGW, 829 CC_OP_BMILGL, 830 CC_OP_BMILGQ, 831 832 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 833 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 834 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 835 836 CC_OP_CLR, /* Z set, all other flags clear. */ 837 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 838 839 CC_OP_NB, 840 } CCOp; 841 842 typedef struct SegmentCache { 843 uint32_t selector; 844 target_ulong base; 845 uint32_t limit; 846 uint32_t flags; 847 } SegmentCache; 848 849 #define MMREG_UNION(n, bits) \ 850 union n { \ 851 uint8_t _b_##n[(bits)/8]; \ 852 uint16_t _w_##n[(bits)/16]; \ 853 uint32_t _l_##n[(bits)/32]; \ 854 uint64_t _q_##n[(bits)/64]; \ 855 float32 _s_##n[(bits)/32]; \ 856 float64 _d_##n[(bits)/64]; \ 857 } 858 859 typedef union { 860 uint8_t _b[16]; 861 uint16_t _w[8]; 862 uint32_t _l[4]; 863 uint64_t _q[2]; 864 } XMMReg; 865 866 typedef union { 867 uint8_t _b[32]; 868 uint16_t _w[16]; 869 uint32_t _l[8]; 870 uint64_t _q[4]; 871 } YMMReg; 872 873 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 874 typedef MMREG_UNION(MMXReg, 64) MMXReg; 875 876 typedef struct BNDReg { 877 uint64_t lb; 878 uint64_t ub; 879 } BNDReg; 880 881 typedef struct BNDCSReg { 882 uint64_t cfgu; 883 uint64_t sts; 884 } BNDCSReg; 885 886 #define BNDCFG_ENABLE 1ULL 887 #define BNDCFG_BNDPRESERVE 2ULL 888 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 889 890 #ifdef HOST_WORDS_BIGENDIAN 891 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 892 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 893 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 894 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 895 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 896 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 897 898 #define MMX_B(n) _b_MMXReg[7 - (n)] 899 #define MMX_W(n) _w_MMXReg[3 - (n)] 900 #define MMX_L(n) _l_MMXReg[1 - (n)] 901 #define MMX_S(n) _s_MMXReg[1 - (n)] 902 #else 903 #define ZMM_B(n) _b_ZMMReg[n] 904 #define ZMM_W(n) _w_ZMMReg[n] 905 #define ZMM_L(n) _l_ZMMReg[n] 906 #define ZMM_S(n) _s_ZMMReg[n] 907 #define ZMM_Q(n) _q_ZMMReg[n] 908 #define ZMM_D(n) _d_ZMMReg[n] 909 910 #define MMX_B(n) _b_MMXReg[n] 911 #define MMX_W(n) _w_MMXReg[n] 912 #define MMX_L(n) _l_MMXReg[n] 913 #define MMX_S(n) _s_MMXReg[n] 914 #endif 915 #define MMX_Q(n) _q_MMXReg[n] 916 917 typedef union { 918 floatx80 d __attribute__((aligned(16))); 919 MMXReg mmx; 920 } FPReg; 921 922 typedef struct { 923 uint64_t base; 924 uint64_t mask; 925 } MTRRVar; 926 927 #define CPU_NB_REGS64 16 928 #define CPU_NB_REGS32 8 929 930 #ifdef TARGET_X86_64 931 #define CPU_NB_REGS CPU_NB_REGS64 932 #else 933 #define CPU_NB_REGS CPU_NB_REGS32 934 #endif 935 936 #define MAX_FIXED_COUNTERS 3 937 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 938 939 #define NB_MMU_MODES 3 940 #define TARGET_INSN_START_EXTRA_WORDS 1 941 942 #define NB_OPMASK_REGS 8 943 944 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 945 * that APIC ID hasn't been set yet 946 */ 947 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 948 949 typedef union X86LegacyXSaveArea { 950 struct { 951 uint16_t fcw; 952 uint16_t fsw; 953 uint8_t ftw; 954 uint8_t reserved; 955 uint16_t fpop; 956 uint64_t fpip; 957 uint64_t fpdp; 958 uint32_t mxcsr; 959 uint32_t mxcsr_mask; 960 FPReg fpregs[8]; 961 uint8_t xmm_regs[16][16]; 962 }; 963 uint8_t data[512]; 964 } X86LegacyXSaveArea; 965 966 typedef struct X86XSaveHeader { 967 uint64_t xstate_bv; 968 uint64_t xcomp_bv; 969 uint64_t reserve0; 970 uint8_t reserved[40]; 971 } X86XSaveHeader; 972 973 /* Ext. save area 2: AVX State */ 974 typedef struct XSaveAVX { 975 uint8_t ymmh[16][16]; 976 } XSaveAVX; 977 978 /* Ext. save area 3: BNDREG */ 979 typedef struct XSaveBNDREG { 980 BNDReg bnd_regs[4]; 981 } XSaveBNDREG; 982 983 /* Ext. save area 4: BNDCSR */ 984 typedef union XSaveBNDCSR { 985 BNDCSReg bndcsr; 986 uint8_t data[64]; 987 } XSaveBNDCSR; 988 989 /* Ext. save area 5: Opmask */ 990 typedef struct XSaveOpmask { 991 uint64_t opmask_regs[NB_OPMASK_REGS]; 992 } XSaveOpmask; 993 994 /* Ext. save area 6: ZMM_Hi256 */ 995 typedef struct XSaveZMM_Hi256 { 996 uint8_t zmm_hi256[16][32]; 997 } XSaveZMM_Hi256; 998 999 /* Ext. save area 7: Hi16_ZMM */ 1000 typedef struct XSaveHi16_ZMM { 1001 uint8_t hi16_zmm[16][64]; 1002 } XSaveHi16_ZMM; 1003 1004 /* Ext. save area 9: PKRU state */ 1005 typedef struct XSavePKRU { 1006 uint32_t pkru; 1007 uint32_t padding; 1008 } XSavePKRU; 1009 1010 typedef struct X86XSaveArea { 1011 X86LegacyXSaveArea legacy; 1012 X86XSaveHeader header; 1013 1014 /* Extended save areas: */ 1015 1016 /* AVX State: */ 1017 XSaveAVX avx_state; 1018 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1019 /* MPX State: */ 1020 XSaveBNDREG bndreg_state; 1021 XSaveBNDCSR bndcsr_state; 1022 /* AVX-512 State: */ 1023 XSaveOpmask opmask_state; 1024 XSaveZMM_Hi256 zmm_hi256_state; 1025 XSaveHi16_ZMM hi16_zmm_state; 1026 /* PKRU State: */ 1027 XSavePKRU pkru_state; 1028 } X86XSaveArea; 1029 1030 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1031 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1032 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1033 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1034 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1035 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1036 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1037 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1038 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1039 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1040 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1041 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1042 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1043 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1044 1045 typedef enum TPRAccess { 1046 TPR_ACCESS_READ, 1047 TPR_ACCESS_WRITE, 1048 } TPRAccess; 1049 1050 /* Cache information data structures: */ 1051 1052 enum CacheType { 1053 DATA_CACHE, 1054 INSTRUCTION_CACHE, 1055 UNIFIED_CACHE 1056 }; 1057 1058 typedef struct CPUCacheInfo { 1059 enum CacheType type; 1060 uint8_t level; 1061 /* Size in bytes */ 1062 uint32_t size; 1063 /* Line size, in bytes */ 1064 uint16_t line_size; 1065 /* 1066 * Associativity. 1067 * Note: representation of fully-associative caches is not implemented 1068 */ 1069 uint8_t associativity; 1070 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1071 uint8_t partitions; 1072 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1073 uint32_t sets; 1074 /* 1075 * Lines per tag. 1076 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1077 * (Is this synonym to @partitions?) 1078 */ 1079 uint8_t lines_per_tag; 1080 1081 /* Self-initializing cache */ 1082 bool self_init; 1083 /* 1084 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1085 * non-originating threads sharing this cache. 1086 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1087 */ 1088 bool no_invd_sharing; 1089 /* 1090 * Cache is inclusive of lower cache levels. 1091 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1092 */ 1093 bool inclusive; 1094 /* 1095 * A complex function is used to index the cache, potentially using all 1096 * address bits. CPUID[4].EDX[bit 2]. 1097 */ 1098 bool complex_indexing; 1099 } CPUCacheInfo; 1100 1101 1102 typedef struct CPUCaches { 1103 CPUCacheInfo *l1d_cache; 1104 CPUCacheInfo *l1i_cache; 1105 CPUCacheInfo *l2_cache; 1106 CPUCacheInfo *l3_cache; 1107 } CPUCaches; 1108 1109 typedef struct CPUX86State { 1110 /* standard registers */ 1111 target_ulong regs[CPU_NB_REGS]; 1112 target_ulong eip; 1113 target_ulong eflags; /* eflags register. During CPU emulation, CC 1114 flags and DF are set to zero because they are 1115 stored elsewhere */ 1116 1117 /* emulator internal eflags handling */ 1118 target_ulong cc_dst; 1119 target_ulong cc_src; 1120 target_ulong cc_src2; 1121 uint32_t cc_op; 1122 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1123 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1124 are known at translation time. */ 1125 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1126 1127 /* segments */ 1128 SegmentCache segs[6]; /* selector values */ 1129 SegmentCache ldt; 1130 SegmentCache tr; 1131 SegmentCache gdt; /* only base and limit are used */ 1132 SegmentCache idt; /* only base and limit are used */ 1133 1134 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1135 int32_t a20_mask; 1136 1137 BNDReg bnd_regs[4]; 1138 BNDCSReg bndcs_regs; 1139 uint64_t msr_bndcfgs; 1140 uint64_t efer; 1141 1142 /* Beginning of state preserved by INIT (dummy marker). */ 1143 struct {} start_init_save; 1144 1145 /* FPU state */ 1146 unsigned int fpstt; /* top of stack index */ 1147 uint16_t fpus; 1148 uint16_t fpuc; 1149 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1150 FPReg fpregs[8]; 1151 /* KVM-only so far */ 1152 uint16_t fpop; 1153 uint64_t fpip; 1154 uint64_t fpdp; 1155 1156 /* emulator internal variables */ 1157 float_status fp_status; 1158 floatx80 ft0; 1159 1160 float_status mmx_status; /* for 3DNow! float ops */ 1161 float_status sse_status; 1162 uint32_t mxcsr; 1163 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1164 ZMMReg xmm_t0; 1165 MMXReg mmx_t0; 1166 1167 XMMReg ymmh_regs[CPU_NB_REGS]; 1168 1169 uint64_t opmask_regs[NB_OPMASK_REGS]; 1170 YMMReg zmmh_regs[CPU_NB_REGS]; 1171 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1172 1173 /* sysenter registers */ 1174 uint32_t sysenter_cs; 1175 target_ulong sysenter_esp; 1176 target_ulong sysenter_eip; 1177 uint64_t star; 1178 1179 uint64_t vm_hsave; 1180 1181 #ifdef TARGET_X86_64 1182 target_ulong lstar; 1183 target_ulong cstar; 1184 target_ulong fmask; 1185 target_ulong kernelgsbase; 1186 #endif 1187 1188 uint64_t tsc; 1189 uint64_t tsc_adjust; 1190 uint64_t tsc_deadline; 1191 uint64_t tsc_aux; 1192 1193 uint64_t xcr0; 1194 1195 uint64_t mcg_status; 1196 uint64_t msr_ia32_misc_enable; 1197 uint64_t msr_ia32_feature_control; 1198 1199 uint64_t msr_fixed_ctr_ctrl; 1200 uint64_t msr_global_ctrl; 1201 uint64_t msr_global_status; 1202 uint64_t msr_global_ovf_ctrl; 1203 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1204 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1205 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1206 1207 uint64_t pat; 1208 uint32_t smbase; 1209 uint64_t msr_smi_count; 1210 1211 uint32_t pkru; 1212 1213 uint64_t spec_ctrl; 1214 uint64_t virt_ssbd; 1215 1216 /* End of state preserved by INIT (dummy marker). */ 1217 struct {} end_init_save; 1218 1219 uint64_t system_time_msr; 1220 uint64_t wall_clock_msr; 1221 uint64_t steal_time_msr; 1222 uint64_t async_pf_en_msr; 1223 uint64_t pv_eoi_en_msr; 1224 1225 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1226 uint64_t msr_hv_hypercall; 1227 uint64_t msr_hv_guest_os_id; 1228 uint64_t msr_hv_tsc; 1229 1230 /* Per-VCPU HV MSRs */ 1231 uint64_t msr_hv_vapic; 1232 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1233 uint64_t msr_hv_runtime; 1234 uint64_t msr_hv_synic_control; 1235 uint64_t msr_hv_synic_evt_page; 1236 uint64_t msr_hv_synic_msg_page; 1237 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1238 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1239 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1240 uint64_t msr_hv_reenlightenment_control; 1241 uint64_t msr_hv_tsc_emulation_control; 1242 uint64_t msr_hv_tsc_emulation_status; 1243 1244 uint64_t msr_rtit_ctrl; 1245 uint64_t msr_rtit_status; 1246 uint64_t msr_rtit_output_base; 1247 uint64_t msr_rtit_output_mask; 1248 uint64_t msr_rtit_cr3_match; 1249 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1250 1251 /* exception/interrupt handling */ 1252 int error_code; 1253 int exception_is_int; 1254 target_ulong exception_next_eip; 1255 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1256 union { 1257 struct CPUBreakpoint *cpu_breakpoint[4]; 1258 struct CPUWatchpoint *cpu_watchpoint[4]; 1259 }; /* break/watchpoints for dr[0..3] */ 1260 int old_exception; /* exception in flight */ 1261 1262 uint64_t vm_vmcb; 1263 uint64_t tsc_offset; 1264 uint64_t intercept; 1265 uint16_t intercept_cr_read; 1266 uint16_t intercept_cr_write; 1267 uint16_t intercept_dr_read; 1268 uint16_t intercept_dr_write; 1269 uint32_t intercept_exceptions; 1270 uint64_t nested_cr3; 1271 uint32_t nested_pg_mode; 1272 uint8_t v_tpr; 1273 1274 /* KVM states, automatically cleared on reset */ 1275 uint8_t nmi_injected; 1276 uint8_t nmi_pending; 1277 1278 uintptr_t retaddr; 1279 1280 /* Fields up to this point are cleared by a CPU reset */ 1281 struct {} end_reset_fields; 1282 1283 CPU_COMMON 1284 1285 /* Fields after CPU_COMMON are preserved across CPU reset. */ 1286 1287 /* processor features (e.g. for CPUID insn) */ 1288 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1289 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1290 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1291 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1292 /* Actual level/xlevel/xlevel2 value: */ 1293 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1294 uint32_t cpuid_vendor1; 1295 uint32_t cpuid_vendor2; 1296 uint32_t cpuid_vendor3; 1297 uint32_t cpuid_version; 1298 FeatureWordArray features; 1299 /* Features that were explicitly enabled/disabled */ 1300 FeatureWordArray user_features; 1301 uint32_t cpuid_model[12]; 1302 /* Cache information for CPUID. When legacy-cache=on, the cache data 1303 * on each CPUID leaf will be different, because we keep compatibility 1304 * with old QEMU versions. 1305 */ 1306 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1307 1308 /* MTRRs */ 1309 uint64_t mtrr_fixed[11]; 1310 uint64_t mtrr_deftype; 1311 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1312 1313 /* For KVM */ 1314 uint32_t mp_state; 1315 int32_t exception_injected; 1316 int32_t interrupt_injected; 1317 uint8_t soft_interrupt; 1318 uint8_t has_error_code; 1319 uint32_t ins_len; 1320 uint32_t sipi_vector; 1321 bool tsc_valid; 1322 int64_t tsc_khz; 1323 int64_t user_tsc_khz; /* for sanity check only */ 1324 void *kvm_xsave_buf; 1325 #if defined(CONFIG_HVF) 1326 HVFX86EmulatorState *hvf_emul; 1327 #endif 1328 1329 uint64_t mcg_cap; 1330 uint64_t mcg_ctl; 1331 uint64_t mcg_ext_ctl; 1332 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1333 uint64_t xstate_bv; 1334 1335 /* vmstate */ 1336 uint16_t fpus_vmstate; 1337 uint16_t fptag_vmstate; 1338 uint16_t fpregs_format_vmstate; 1339 1340 uint64_t xss; 1341 1342 TPRAccess tpr_access_type; 1343 } CPUX86State; 1344 1345 struct kvm_msrs; 1346 1347 /** 1348 * X86CPU: 1349 * @env: #CPUX86State 1350 * @migratable: If set, only migratable flags will be accepted when "enforce" 1351 * mode is used, and only migratable flags will be included in the "host" 1352 * CPU model. 1353 * 1354 * An x86 CPU. 1355 */ 1356 struct X86CPU { 1357 /*< private >*/ 1358 CPUState parent_obj; 1359 /*< public >*/ 1360 1361 CPUX86State env; 1362 1363 bool hyperv_vapic; 1364 bool hyperv_relaxed_timing; 1365 int hyperv_spinlock_attempts; 1366 char *hyperv_vendor_id; 1367 bool hyperv_time; 1368 bool hyperv_crash; 1369 bool hyperv_reset; 1370 bool hyperv_vpindex; 1371 bool hyperv_runtime; 1372 bool hyperv_synic; 1373 bool hyperv_stimer; 1374 bool hyperv_frequencies; 1375 bool hyperv_reenlightenment; 1376 bool hyperv_tlbflush; 1377 bool check_cpuid; 1378 bool enforce_cpuid; 1379 bool expose_kvm; 1380 bool expose_tcg; 1381 bool migratable; 1382 bool migrate_smi_count; 1383 bool max_features; /* Enable all supported features automatically */ 1384 uint32_t apic_id; 1385 1386 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1387 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1388 bool vmware_cpuid_freq; 1389 1390 /* if true the CPUID code directly forward host cache leaves to the guest */ 1391 bool cache_info_passthrough; 1392 1393 /* if true the CPUID code directly forwards 1394 * host monitor/mwait leaves to the guest */ 1395 struct { 1396 uint32_t eax; 1397 uint32_t ebx; 1398 uint32_t ecx; 1399 uint32_t edx; 1400 } mwait; 1401 1402 /* Features that were filtered out because of missing host capabilities */ 1403 uint32_t filtered_features[FEATURE_WORDS]; 1404 1405 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1406 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1407 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1408 * capabilities) directly to the guest. 1409 */ 1410 bool enable_pmu; 1411 1412 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1413 * disabled by default to avoid breaking migration between QEMU with 1414 * different LMCE configurations. 1415 */ 1416 bool enable_lmce; 1417 1418 /* Compatibility bits for old machine types. 1419 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1420 * socket share an virtual l3 cache. 1421 */ 1422 bool enable_l3_cache; 1423 1424 /* Compatibility bits for old machine types. 1425 * If true present the old cache topology information 1426 */ 1427 bool legacy_cache; 1428 1429 /* Compatibility bits for old machine types: */ 1430 bool enable_cpuid_0xb; 1431 1432 /* Enable auto level-increase for all CPUID leaves */ 1433 bool full_cpuid_auto_level; 1434 1435 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1436 bool fill_mtrr_mask; 1437 1438 /* if true override the phys_bits value with a value read from the host */ 1439 bool host_phys_bits; 1440 1441 /* Stop SMI delivery for migration compatibility with old machines */ 1442 bool kvm_no_smi_migration; 1443 1444 /* Number of physical address bits supported */ 1445 uint32_t phys_bits; 1446 1447 /* in order to simplify APIC support, we leave this pointer to the 1448 user */ 1449 struct DeviceState *apic_state; 1450 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1451 Notifier machine_done; 1452 1453 struct kvm_msrs *kvm_msr_buf; 1454 1455 int32_t node_id; /* NUMA node this CPU belongs to */ 1456 int32_t socket_id; 1457 int32_t core_id; 1458 int32_t thread_id; 1459 1460 int32_t hv_max_vps; 1461 }; 1462 1463 static inline X86CPU *x86_env_get_cpu(CPUX86State *env) 1464 { 1465 return container_of(env, X86CPU, env); 1466 } 1467 1468 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) 1469 1470 #define ENV_OFFSET offsetof(X86CPU, env) 1471 1472 #ifndef CONFIG_USER_ONLY 1473 extern struct VMStateDescription vmstate_x86_cpu; 1474 #endif 1475 1476 /** 1477 * x86_cpu_do_interrupt: 1478 * @cpu: vCPU the interrupt is to be handled by. 1479 */ 1480 void x86_cpu_do_interrupt(CPUState *cpu); 1481 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1482 1483 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1484 int cpuid, void *opaque); 1485 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1486 int cpuid, void *opaque); 1487 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1488 void *opaque); 1489 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1490 void *opaque); 1491 1492 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1493 Error **errp); 1494 1495 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 1496 int flags); 1497 1498 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1499 1500 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1501 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1502 1503 void x86_cpu_exec_enter(CPUState *cpu); 1504 void x86_cpu_exec_exit(CPUState *cpu); 1505 1506 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1507 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1508 1509 int cpu_get_pic_interrupt(CPUX86State *s); 1510 /* MSDOS compatibility mode FPU exception support */ 1511 void cpu_set_ferr(CPUX86State *s); 1512 1513 /* this function must always be used to load data in the segment 1514 cache: it synchronizes the hflags with the segment cache values */ 1515 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1516 int seg_reg, unsigned int selector, 1517 target_ulong base, 1518 unsigned int limit, 1519 unsigned int flags) 1520 { 1521 SegmentCache *sc; 1522 unsigned int new_hflags; 1523 1524 sc = &env->segs[seg_reg]; 1525 sc->selector = selector; 1526 sc->base = base; 1527 sc->limit = limit; 1528 sc->flags = flags; 1529 1530 /* update the hidden flags */ 1531 { 1532 if (seg_reg == R_CS) { 1533 #ifdef TARGET_X86_64 1534 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1535 /* long mode */ 1536 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1537 env->hflags &= ~(HF_ADDSEG_MASK); 1538 } else 1539 #endif 1540 { 1541 /* legacy / compatibility case */ 1542 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1543 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1544 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1545 new_hflags; 1546 } 1547 } 1548 if (seg_reg == R_SS) { 1549 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1550 #if HF_CPL_MASK != 3 1551 #error HF_CPL_MASK is hardcoded 1552 #endif 1553 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1554 } 1555 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1556 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1557 if (env->hflags & HF_CS64_MASK) { 1558 /* zero base assumed for DS, ES and SS in long mode */ 1559 } else if (!(env->cr[0] & CR0_PE_MASK) || 1560 (env->eflags & VM_MASK) || 1561 !(env->hflags & HF_CS32_MASK)) { 1562 /* XXX: try to avoid this test. The problem comes from the 1563 fact that is real mode or vm86 mode we only modify the 1564 'base' and 'selector' fields of the segment cache to go 1565 faster. A solution may be to force addseg to one in 1566 translate-i386.c. */ 1567 new_hflags |= HF_ADDSEG_MASK; 1568 } else { 1569 new_hflags |= ((env->segs[R_DS].base | 1570 env->segs[R_ES].base | 1571 env->segs[R_SS].base) != 0) << 1572 HF_ADDSEG_SHIFT; 1573 } 1574 env->hflags = (env->hflags & 1575 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1576 } 1577 } 1578 1579 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1580 uint8_t sipi_vector) 1581 { 1582 CPUState *cs = CPU(cpu); 1583 CPUX86State *env = &cpu->env; 1584 1585 env->eip = 0; 1586 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1587 sipi_vector << 12, 1588 env->segs[R_CS].limit, 1589 env->segs[R_CS].flags); 1590 cs->halted = 0; 1591 } 1592 1593 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1594 target_ulong *base, unsigned int *limit, 1595 unsigned int *flags); 1596 1597 /* op_helper.c */ 1598 /* used for debug or cpu save/restore */ 1599 1600 /* cpu-exec.c */ 1601 /* the following helpers are only usable in user mode simulation as 1602 they can trigger unexpected exceptions */ 1603 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1604 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1605 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1606 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1607 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1608 1609 /* you can call this signal handler from your SIGBUS and SIGSEGV 1610 signal handlers to inform the virtual CPU of exceptions. non zero 1611 is returned if the signal was handled by the virtual CPU. */ 1612 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1613 void *puc); 1614 1615 /* cpu.c */ 1616 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1617 uint32_t *eax, uint32_t *ebx, 1618 uint32_t *ecx, uint32_t *edx); 1619 void cpu_clear_apic_feature(CPUX86State *env); 1620 void host_cpuid(uint32_t function, uint32_t count, 1621 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1622 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1623 1624 /* helper.c */ 1625 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, 1626 int is_write, int mmu_idx); 1627 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1628 1629 #ifndef CONFIG_USER_ONLY 1630 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1631 { 1632 return !!attrs.secure; 1633 } 1634 1635 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1636 { 1637 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1638 } 1639 1640 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1641 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1642 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1643 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1644 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1645 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1646 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1647 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1648 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1649 #endif 1650 1651 void breakpoint_handler(CPUState *cs); 1652 1653 /* will be suppressed */ 1654 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1655 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1656 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1657 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1658 1659 /* hw/pc.c */ 1660 uint64_t cpu_get_tsc(CPUX86State *env); 1661 1662 #define TARGET_PAGE_BITS 12 1663 1664 #ifdef TARGET_X86_64 1665 #define TARGET_PHYS_ADDR_SPACE_BITS 52 1666 /* ??? This is really 48 bits, sign-extended, but the only thing 1667 accessible to userland with bit 48 set is the VSYSCALL, and that 1668 is handled via other mechanisms. */ 1669 #define TARGET_VIRT_ADDR_SPACE_BITS 47 1670 #else 1671 #define TARGET_PHYS_ADDR_SPACE_BITS 36 1672 #define TARGET_VIRT_ADDR_SPACE_BITS 32 1673 #endif 1674 1675 /* XXX: This value should match the one returned by CPUID 1676 * and in exec.c */ 1677 # if defined(TARGET_X86_64) 1678 # define TCG_PHYS_ADDR_BITS 40 1679 # else 1680 # define TCG_PHYS_ADDR_BITS 36 1681 # endif 1682 1683 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1684 1685 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1686 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1687 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1688 1689 #ifdef TARGET_X86_64 1690 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1691 #else 1692 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1693 #endif 1694 1695 #define cpu_signal_handler cpu_x86_signal_handler 1696 #define cpu_list x86_cpu_list 1697 1698 /* MMU modes definitions */ 1699 #define MMU_MODE0_SUFFIX _ksmap 1700 #define MMU_MODE1_SUFFIX _user 1701 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1702 #define MMU_KSMAP_IDX 0 1703 #define MMU_USER_IDX 1 1704 #define MMU_KNOSMAP_IDX 2 1705 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1706 { 1707 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1708 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1709 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1710 } 1711 1712 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1713 { 1714 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1715 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1716 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1717 } 1718 1719 #define CC_DST (env->cc_dst) 1720 #define CC_SRC (env->cc_src) 1721 #define CC_SRC2 (env->cc_src2) 1722 #define CC_OP (env->cc_op) 1723 1724 /* n must be a constant to be efficient */ 1725 static inline target_long lshift(target_long x, int n) 1726 { 1727 if (n >= 0) { 1728 return x << n; 1729 } else { 1730 return x >> (-n); 1731 } 1732 } 1733 1734 /* float macros */ 1735 #define FT0 (env->ft0) 1736 #define ST0 (env->fpregs[env->fpstt].d) 1737 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1738 #define ST1 ST(1) 1739 1740 /* translate.c */ 1741 void tcg_x86_init(void); 1742 1743 #include "exec/cpu-all.h" 1744 #include "svm.h" 1745 1746 #if !defined(CONFIG_USER_ONLY) 1747 #include "hw/i386/apic.h" 1748 #endif 1749 1750 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1751 target_ulong *cs_base, uint32_t *flags) 1752 { 1753 *cs_base = env->segs[R_CS].base; 1754 *pc = *cs_base + env->eip; 1755 *flags = env->hflags | 1756 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1757 } 1758 1759 void do_cpu_init(X86CPU *cpu); 1760 void do_cpu_sipi(X86CPU *cpu); 1761 1762 #define MCE_INJECT_BROADCAST 1 1763 #define MCE_INJECT_UNCOND_AO 2 1764 1765 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1766 uint64_t status, uint64_t mcg_status, uint64_t addr, 1767 uint64_t misc, int flags); 1768 1769 /* excp_helper.c */ 1770 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1771 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1772 uintptr_t retaddr); 1773 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1774 int error_code); 1775 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1776 int error_code, uintptr_t retaddr); 1777 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1778 int error_code, int next_eip_addend); 1779 1780 /* cc_helper.c */ 1781 extern const uint8_t parity_table[256]; 1782 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1783 1784 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1785 { 1786 uint32_t eflags = env->eflags; 1787 if (tcg_enabled()) { 1788 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 1789 } 1790 return eflags; 1791 } 1792 1793 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1794 * after generating a call to a helper that uses this. 1795 */ 1796 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1797 int update_mask) 1798 { 1799 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1800 CC_OP = CC_OP_EFLAGS; 1801 env->df = 1 - (2 * ((eflags >> 10) & 1)); 1802 env->eflags = (env->eflags & ~update_mask) | 1803 (eflags & update_mask) | 0x2; 1804 } 1805 1806 /* load efer and update the corresponding hflags. XXX: do consistency 1807 checks with cpuid bits? */ 1808 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1809 { 1810 env->efer = val; 1811 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1812 if (env->efer & MSR_EFER_LMA) { 1813 env->hflags |= HF_LMA_MASK; 1814 } 1815 if (env->efer & MSR_EFER_SVME) { 1816 env->hflags |= HF_SVME_MASK; 1817 } 1818 } 1819 1820 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 1821 { 1822 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 1823 } 1824 1825 static inline int32_t x86_get_a20_mask(CPUX86State *env) 1826 { 1827 if (env->hflags & HF_SMM_MASK) { 1828 return -1; 1829 } else { 1830 return env->a20_mask; 1831 } 1832 } 1833 1834 /* fpu_helper.c */ 1835 void update_fp_status(CPUX86State *env); 1836 void update_mxcsr_status(CPUX86State *env); 1837 1838 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 1839 { 1840 env->mxcsr = mxcsr; 1841 if (tcg_enabled()) { 1842 update_mxcsr_status(env); 1843 } 1844 } 1845 1846 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 1847 { 1848 env->fpuc = fpuc; 1849 if (tcg_enabled()) { 1850 update_fp_status(env); 1851 } 1852 } 1853 1854 /* mem_helper.c */ 1855 void helper_lock_init(void); 1856 1857 /* svm_helper.c */ 1858 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 1859 uint64_t param, uintptr_t retaddr); 1860 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, 1861 uint64_t exit_info_1, uintptr_t retaddr); 1862 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 1863 1864 /* seg_helper.c */ 1865 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 1866 1867 /* smm_helper.c */ 1868 void do_smm_enter(X86CPU *cpu); 1869 1870 /* apic.c */ 1871 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 1872 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 1873 TPRAccess access); 1874 1875 1876 /* Change the value of a KVM-specific default 1877 * 1878 * If value is NULL, no default will be set and the original 1879 * value from the CPU model table will be kept. 1880 * 1881 * It is valid to call this function only for properties that 1882 * are already present in the kvm_default_props table. 1883 */ 1884 void x86_cpu_change_kvm_default(const char *prop, const char *value); 1885 1886 /* mpx_helper.c */ 1887 void cpu_sync_bndcs_hflags(CPUX86State *env); 1888 1889 /* Return name of 32-bit register, from a R_* constant */ 1890 const char *get_register_name_32(unsigned int reg); 1891 1892 void enable_compat_apic_id_mode(void); 1893 1894 #define APIC_DEFAULT_ADDRESS 0xfee00000 1895 #define APIC_SPACE_SIZE 0x100000 1896 1897 void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, 1898 fprintf_function cpu_fprintf, int flags); 1899 1900 /* cpu.c */ 1901 bool cpu_is_bsp(X86CPU *cpu); 1902 1903 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 1904 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 1905 void x86_update_hflags(CPUX86State* env); 1906 1907 #endif /* I386_CPU_H */ 1908