xref: /openbmc/qemu/target/i386/cpu.h (revision bb154e3e0cc715605d915f0761e0cd7a4e64d1bd)
1 /*
2  * i386 virtual CPU header
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef I386_CPU_H
21 #define I386_CPU_H
22 
23 #include "sysemu/tcg.h"
24 #include "cpu-qom.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "hw/i386/topology.h"
28 #include "qapi/qapi-types-common.h"
29 #include "qemu/cpu-float.h"
30 #include "qemu/timer.h"
31 
32 #define XEN_NR_VIRQS 24
33 
34 #define KVM_HAVE_MCE_INJECTION 1
35 
36 /* support for self modifying code even if the modified instruction is
37    close to the modifying instruction */
38 #define TARGET_HAS_PRECISE_SMC
39 
40 #ifdef TARGET_X86_64
41 #define I386_ELF_MACHINE  EM_X86_64
42 #define ELF_MACHINE_UNAME "x86_64"
43 #else
44 #define I386_ELF_MACHINE  EM_386
45 #define ELF_MACHINE_UNAME "i686"
46 #endif
47 
48 enum {
49     R_EAX = 0,
50     R_ECX = 1,
51     R_EDX = 2,
52     R_EBX = 3,
53     R_ESP = 4,
54     R_EBP = 5,
55     R_ESI = 6,
56     R_EDI = 7,
57     R_R8 = 8,
58     R_R9 = 9,
59     R_R10 = 10,
60     R_R11 = 11,
61     R_R12 = 12,
62     R_R13 = 13,
63     R_R14 = 14,
64     R_R15 = 15,
65 
66     R_AL = 0,
67     R_CL = 1,
68     R_DL = 2,
69     R_BL = 3,
70     R_AH = 4,
71     R_CH = 5,
72     R_DH = 6,
73     R_BH = 7,
74 };
75 
76 typedef enum X86Seg {
77     R_ES = 0,
78     R_CS = 1,
79     R_SS = 2,
80     R_DS = 3,
81     R_FS = 4,
82     R_GS = 5,
83     R_LDTR = 6,
84     R_TR = 7,
85 } X86Seg;
86 
87 /* segment descriptor fields */
88 #define DESC_G_SHIFT    23
89 #define DESC_G_MASK     (1 << DESC_G_SHIFT)
90 #define DESC_B_SHIFT    22
91 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
92 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
93 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
94 #define DESC_AVL_SHIFT  20
95 #define DESC_AVL_MASK   (1 << DESC_AVL_SHIFT)
96 #define DESC_P_SHIFT    15
97 #define DESC_P_MASK     (1 << DESC_P_SHIFT)
98 #define DESC_DPL_SHIFT  13
99 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
100 #define DESC_S_SHIFT    12
101 #define DESC_S_MASK     (1 << DESC_S_SHIFT)
102 #define DESC_TYPE_SHIFT 8
103 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
104 #define DESC_A_MASK     (1 << 8)
105 
106 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
107 #define DESC_C_MASK     (1 << 10) /* code: conforming */
108 #define DESC_R_MASK     (1 << 9)  /* code: readable */
109 
110 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
111 #define DESC_W_MASK     (1 << 9)  /* data: writable */
112 
113 #define DESC_TSS_BUSY_MASK (1 << 9)
114 
115 /* eflags masks */
116 #define CC_C    0x0001
117 #define CC_P    0x0004
118 #define CC_A    0x0010
119 #define CC_Z    0x0040
120 #define CC_S    0x0080
121 #define CC_O    0x0800
122 
123 #define TF_SHIFT   8
124 #define IOPL_SHIFT 12
125 #define VM_SHIFT   17
126 
127 #define TF_MASK                 0x00000100
128 #define IF_MASK                 0x00000200
129 #define DF_MASK                 0x00000400
130 #define IOPL_MASK               0x00003000
131 #define NT_MASK                 0x00004000
132 #define RF_MASK                 0x00010000
133 #define VM_MASK                 0x00020000
134 #define AC_MASK                 0x00040000
135 #define VIF_MASK                0x00080000
136 #define VIP_MASK                0x00100000
137 #define ID_MASK                 0x00200000
138 
139 /* hidden flags - used internally by qemu to represent additional cpu
140    states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
141    avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
142    positions to ease oring with eflags. */
143 /* current cpl */
144 #define HF_CPL_SHIFT         0
145 /* true if hardware interrupts must be disabled for next instruction */
146 #define HF_INHIBIT_IRQ_SHIFT 3
147 /* 16 or 32 segments */
148 #define HF_CS32_SHIFT        4
149 #define HF_SS32_SHIFT        5
150 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
151 #define HF_ADDSEG_SHIFT      6
152 /* copy of CR0.PE (protected mode) */
153 #define HF_PE_SHIFT          7
154 #define HF_TF_SHIFT          8 /* must be same as eflags */
155 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
156 #define HF_EM_SHIFT         10
157 #define HF_TS_SHIFT         11
158 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
159 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
160 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
161 #define HF_RF_SHIFT         16 /* must be same as eflags */
162 #define HF_VM_SHIFT         17 /* must be same as eflags */
163 #define HF_AC_SHIFT         18 /* must be same as eflags */
164 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
165 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
166 #define HF_GUEST_SHIFT      21 /* SVM intercepts are active */
167 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
168 #define HF_SMAP_SHIFT       23 /* CR4.SMAP */
169 #define HF_IOBPT_SHIFT      24 /* an io breakpoint enabled */
170 #define HF_MPX_EN_SHIFT     25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
171 #define HF_MPX_IU_SHIFT     26 /* BND registers in-use */
172 #define HF_UMIP_SHIFT       27 /* CR4.UMIP */
173 #define HF_AVX_EN_SHIFT     28 /* AVX Enabled (CR4+XCR0) */
174 
175 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
176 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
177 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
178 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
179 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
180 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
181 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
182 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
183 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
184 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
185 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
186 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
187 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
188 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
189 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
190 #define HF_AC_MASK           (1 << HF_AC_SHIFT)
191 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
192 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
193 #define HF_GUEST_MASK        (1 << HF_GUEST_SHIFT)
194 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
195 #define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
196 #define HF_IOBPT_MASK        (1 << HF_IOBPT_SHIFT)
197 #define HF_MPX_EN_MASK       (1 << HF_MPX_EN_SHIFT)
198 #define HF_MPX_IU_MASK       (1 << HF_MPX_IU_SHIFT)
199 #define HF_UMIP_MASK         (1 << HF_UMIP_SHIFT)
200 #define HF_AVX_EN_MASK       (1 << HF_AVX_EN_SHIFT)
201 
202 /* hflags2 */
203 
204 #define HF2_GIF_SHIFT            0 /* if set CPU takes interrupts */
205 #define HF2_HIF_SHIFT            1 /* value of IF_MASK when entering SVM */
206 #define HF2_NMI_SHIFT            2 /* CPU serving NMI */
207 #define HF2_VINTR_SHIFT          3 /* value of V_INTR_MASKING bit */
208 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
209 #define HF2_MPX_PR_SHIFT         5 /* BNDCFGx.BNDPRESERVE */
210 #define HF2_NPT_SHIFT            6 /* Nested Paging enabled */
211 #define HF2_IGNNE_SHIFT          7 /* Ignore CR0.NE=0 */
212 #define HF2_VGIF_SHIFT           8 /* Can take VIRQ*/
213 
214 #define HF2_GIF_MASK            (1 << HF2_GIF_SHIFT)
215 #define HF2_HIF_MASK            (1 << HF2_HIF_SHIFT)
216 #define HF2_NMI_MASK            (1 << HF2_NMI_SHIFT)
217 #define HF2_VINTR_MASK          (1 << HF2_VINTR_SHIFT)
218 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
219 #define HF2_MPX_PR_MASK         (1 << HF2_MPX_PR_SHIFT)
220 #define HF2_NPT_MASK            (1 << HF2_NPT_SHIFT)
221 #define HF2_IGNNE_MASK          (1 << HF2_IGNNE_SHIFT)
222 #define HF2_VGIF_MASK           (1 << HF2_VGIF_SHIFT)
223 
224 #define CR0_PE_SHIFT 0
225 #define CR0_MP_SHIFT 1
226 
227 #define CR0_PE_MASK  (1U << 0)
228 #define CR0_MP_MASK  (1U << 1)
229 #define CR0_EM_MASK  (1U << 2)
230 #define CR0_TS_MASK  (1U << 3)
231 #define CR0_ET_MASK  (1U << 4)
232 #define CR0_NE_MASK  (1U << 5)
233 #define CR0_WP_MASK  (1U << 16)
234 #define CR0_AM_MASK  (1U << 18)
235 #define CR0_NW_MASK  (1U << 29)
236 #define CR0_CD_MASK  (1U << 30)
237 #define CR0_PG_MASK  (1U << 31)
238 
239 #define CR4_VME_MASK  (1U << 0)
240 #define CR4_PVI_MASK  (1U << 1)
241 #define CR4_TSD_MASK  (1U << 2)
242 #define CR4_DE_MASK   (1U << 3)
243 #define CR4_PSE_MASK  (1U << 4)
244 #define CR4_PAE_MASK  (1U << 5)
245 #define CR4_MCE_MASK  (1U << 6)
246 #define CR4_PGE_MASK  (1U << 7)
247 #define CR4_PCE_MASK  (1U << 8)
248 #define CR4_OSFXSR_SHIFT 9
249 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
250 #define CR4_OSXMMEXCPT_MASK  (1U << 10)
251 #define CR4_UMIP_MASK   (1U << 11)
252 #define CR4_LA57_MASK   (1U << 12)
253 #define CR4_VMXE_MASK   (1U << 13)
254 #define CR4_SMXE_MASK   (1U << 14)
255 #define CR4_FSGSBASE_MASK (1U << 16)
256 #define CR4_PCIDE_MASK  (1U << 17)
257 #define CR4_OSXSAVE_MASK (1U << 18)
258 #define CR4_SMEP_MASK   (1U << 20)
259 #define CR4_SMAP_MASK   (1U << 21)
260 #define CR4_PKE_MASK   (1U << 22)
261 #define CR4_PKS_MASK   (1U << 24)
262 #define CR4_LAM_SUP_MASK (1U << 28)
263 
264 #ifdef TARGET_X86_64
265 #define CR4_FRED_MASK   (1ULL << 32)
266 #else
267 #define CR4_FRED_MASK   0
268 #endif
269 
270 #define CR4_RESERVED_MASK \
271 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
272                 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
273                 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
274                 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
275                 | CR4_LA57_MASK \
276                 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
277                 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \
278                 | CR4_LAM_SUP_MASK | CR4_FRED_MASK))
279 
280 #define DR6_BD          (1 << 13)
281 #define DR6_BS          (1 << 14)
282 #define DR6_BT          (1 << 15)
283 #define DR6_FIXED_1     0xffff0ff0
284 
285 #define DR7_GD          (1 << 13)
286 #define DR7_TYPE_SHIFT  16
287 #define DR7_LEN_SHIFT   18
288 #define DR7_FIXED_1     0x00000400
289 #define DR7_GLOBAL_BP_MASK   0xaa
290 #define DR7_LOCAL_BP_MASK    0x55
291 #define DR7_MAX_BP           4
292 #define DR7_TYPE_BP_INST     0x0
293 #define DR7_TYPE_DATA_WR     0x1
294 #define DR7_TYPE_IO_RW       0x2
295 #define DR7_TYPE_DATA_RW     0x3
296 
297 #define DR_RESERVED_MASK 0xffffffff00000000ULL
298 
299 #define PG_PRESENT_BIT  0
300 #define PG_RW_BIT       1
301 #define PG_USER_BIT     2
302 #define PG_PWT_BIT      3
303 #define PG_PCD_BIT      4
304 #define PG_ACCESSED_BIT 5
305 #define PG_DIRTY_BIT    6
306 #define PG_PSE_BIT      7
307 #define PG_GLOBAL_BIT   8
308 #define PG_PSE_PAT_BIT  12
309 #define PG_PKRU_BIT     59
310 #define PG_NX_BIT       63
311 
312 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
313 #define PG_RW_MASK       (1 << PG_RW_BIT)
314 #define PG_USER_MASK     (1 << PG_USER_BIT)
315 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
316 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
317 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
318 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
319 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
320 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
321 #define PG_PSE_PAT_MASK  (1 << PG_PSE_PAT_BIT)
322 #define PG_ADDRESS_MASK  0x000ffffffffff000LL
323 #define PG_HI_USER_MASK  0x7ff0000000000000LL
324 #define PG_PKRU_MASK     (15ULL << PG_PKRU_BIT)
325 #define PG_NX_MASK       (1ULL << PG_NX_BIT)
326 
327 #define PG_ERROR_W_BIT     1
328 
329 #define PG_ERROR_P_MASK    0x01
330 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
331 #define PG_ERROR_U_MASK    0x04
332 #define PG_ERROR_RSVD_MASK 0x08
333 #define PG_ERROR_I_D_MASK  0x10
334 #define PG_ERROR_PK_MASK   0x20
335 
336 #define PG_MODE_PAE      (1 << 0)
337 #define PG_MODE_LMA      (1 << 1)
338 #define PG_MODE_NXE      (1 << 2)
339 #define PG_MODE_PSE      (1 << 3)
340 #define PG_MODE_LA57     (1 << 4)
341 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
342 
343 /* Bits of CR4 that do not affect the NPT page format.  */
344 #define PG_MODE_WP       (1 << 16)
345 #define PG_MODE_PKE      (1 << 17)
346 #define PG_MODE_PKS      (1 << 18)
347 #define PG_MODE_SMEP     (1 << 19)
348 
349 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
350 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
351 #define MCG_LMCE_P      (1ULL<<27) /* Local Machine Check Supported */
352 
353 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
354 #define MCE_BANKS_DEF   10
355 
356 #define MCG_CAP_BANKS_MASK 0xff
357 
358 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
359 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
360 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
361 #define MCG_STATUS_LMCE (1ULL<<3)   /* Local MCE signaled */
362 
363 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
364 
365 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
366 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
367 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
368 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
369 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
370 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
371 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
372 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
373 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
374 #define MCI_STATUS_DEFERRED    (1ULL<<44)  /* Deferred error */
375 #define MCI_STATUS_POISON      (1ULL<<43)  /* Poisoned data consumed */
376 
377 /* MISC register defines */
378 #define MCM_ADDR_SEGOFF  0      /* segment offset */
379 #define MCM_ADDR_LINEAR  1      /* linear address */
380 #define MCM_ADDR_PHYS    2      /* physical address */
381 #define MCM_ADDR_MEM     3      /* memory address */
382 #define MCM_ADDR_GENERIC 7      /* generic */
383 
384 #define MSR_IA32_TSC                    0x10
385 #define MSR_IA32_APICBASE               0x1b
386 #define MSR_IA32_APICBASE_BSP           (1<<8)
387 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
388 #define MSR_IA32_APICBASE_EXTD          (1 << 10)
389 #define MSR_IA32_APICBASE_BASE          (0xfffffU<<12)
390 #define MSR_IA32_APICBASE_RESERVED \
391         (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
392                      | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE))
393 
394 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
395 #define MSR_TSC_ADJUST                  0x0000003b
396 #define MSR_IA32_SPEC_CTRL              0x48
397 #define MSR_VIRT_SSBD                   0xc001011f
398 #define MSR_IA32_PRED_CMD               0x49
399 #define MSR_IA32_UCODE_REV              0x8b
400 #define MSR_IA32_CORE_CAPABILITY        0xcf
401 
402 #define MSR_IA32_ARCH_CAPABILITIES      0x10a
403 #define ARCH_CAP_TSX_CTRL_MSR		(1<<7)
404 
405 #define MSR_IA32_PERF_CAPABILITIES      0x345
406 #define PERF_CAP_LBR_FMT                0x3f
407 
408 #define MSR_IA32_TSX_CTRL		0x122
409 #define MSR_IA32_TSCDEADLINE            0x6e0
410 #define MSR_IA32_PKRS                   0x6e1
411 #define MSR_RAPL_POWER_UNIT             0x00000606
412 #define MSR_PKG_POWER_LIMIT             0x00000610
413 #define MSR_PKG_ENERGY_STATUS           0x00000611
414 #define MSR_PKG_POWER_INFO              0x00000614
415 #define MSR_ARCH_LBR_CTL                0x000014ce
416 #define MSR_ARCH_LBR_DEPTH              0x000014cf
417 #define MSR_ARCH_LBR_FROM_0             0x00001500
418 #define MSR_ARCH_LBR_TO_0               0x00001600
419 #define MSR_ARCH_LBR_INFO_0             0x00001200
420 
421 #define FEATURE_CONTROL_LOCKED                    (1<<0)
422 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX  (1ULL << 1)
423 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
424 #define FEATURE_CONTROL_SGX_LC                    (1ULL << 17)
425 #define FEATURE_CONTROL_SGX                       (1ULL << 18)
426 #define FEATURE_CONTROL_LMCE                      (1<<20)
427 
428 #define MSR_IA32_SGXLEPUBKEYHASH0       0x8c
429 #define MSR_IA32_SGXLEPUBKEYHASH1       0x8d
430 #define MSR_IA32_SGXLEPUBKEYHASH2       0x8e
431 #define MSR_IA32_SGXLEPUBKEYHASH3       0x8f
432 
433 #define MSR_P6_PERFCTR0                 0xc1
434 
435 #define MSR_IA32_SMBASE                 0x9e
436 #define MSR_SMI_COUNT                   0x34
437 #define MSR_CORE_THREAD_COUNT           0x35
438 #define MSR_MTRRcap                     0xfe
439 #define MSR_MTRRcap_VCNT                8
440 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
441 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
442 
443 #define MSR_IA32_SYSENTER_CS            0x174
444 #define MSR_IA32_SYSENTER_ESP           0x175
445 #define MSR_IA32_SYSENTER_EIP           0x176
446 
447 #define MSR_MCG_CAP                     0x179
448 #define MSR_MCG_STATUS                  0x17a
449 #define MSR_MCG_CTL                     0x17b
450 #define MSR_MCG_EXT_CTL                 0x4d0
451 
452 #define MSR_P6_EVNTSEL0                 0x186
453 
454 #define MSR_IA32_PERF_STATUS            0x198
455 
456 #define MSR_IA32_MISC_ENABLE            0x1a0
457 /* Indicates good rep/movs microcode on some processors: */
458 #define MSR_IA32_MISC_ENABLE_DEFAULT    1
459 #define MSR_IA32_MISC_ENABLE_MWAIT      (1ULL << 18)
460 
461 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
462 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
463 
464 #define MSR_MTRRphysIndex(addr)         ((((addr) & ~1u) - 0x200) / 2)
465 
466 #define MSR_MTRRfix64K_00000            0x250
467 #define MSR_MTRRfix16K_80000            0x258
468 #define MSR_MTRRfix16K_A0000            0x259
469 #define MSR_MTRRfix4K_C0000             0x268
470 #define MSR_MTRRfix4K_C8000             0x269
471 #define MSR_MTRRfix4K_D0000             0x26a
472 #define MSR_MTRRfix4K_D8000             0x26b
473 #define MSR_MTRRfix4K_E0000             0x26c
474 #define MSR_MTRRfix4K_E8000             0x26d
475 #define MSR_MTRRfix4K_F0000             0x26e
476 #define MSR_MTRRfix4K_F8000             0x26f
477 
478 #define MSR_PAT                         0x277
479 
480 #define MSR_MTRRdefType                 0x2ff
481 
482 #define MSR_CORE_PERF_FIXED_CTR0        0x309
483 #define MSR_CORE_PERF_FIXED_CTR1        0x30a
484 #define MSR_CORE_PERF_FIXED_CTR2        0x30b
485 #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
486 #define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
487 #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
488 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
489 
490 #define MSR_MC0_CTL                     0x400
491 #define MSR_MC0_STATUS                  0x401
492 #define MSR_MC0_ADDR                    0x402
493 #define MSR_MC0_MISC                    0x403
494 
495 #define MSR_IA32_RTIT_OUTPUT_BASE       0x560
496 #define MSR_IA32_RTIT_OUTPUT_MASK       0x561
497 #define MSR_IA32_RTIT_CTL               0x570
498 #define MSR_IA32_RTIT_STATUS            0x571
499 #define MSR_IA32_RTIT_CR3_MATCH         0x572
500 #define MSR_IA32_RTIT_ADDR0_A           0x580
501 #define MSR_IA32_RTIT_ADDR0_B           0x581
502 #define MSR_IA32_RTIT_ADDR1_A           0x582
503 #define MSR_IA32_RTIT_ADDR1_B           0x583
504 #define MSR_IA32_RTIT_ADDR2_A           0x584
505 #define MSR_IA32_RTIT_ADDR2_B           0x585
506 #define MSR_IA32_RTIT_ADDR3_A           0x586
507 #define MSR_IA32_RTIT_ADDR3_B           0x587
508 #define MAX_RTIT_ADDRS                  8
509 
510 #define MSR_EFER                        0xc0000080
511 
512 #define MSR_EFER_SCE   (1 << 0)
513 #define MSR_EFER_LME   (1 << 8)
514 #define MSR_EFER_LMA   (1 << 10)
515 #define MSR_EFER_NXE   (1 << 11)
516 #define MSR_EFER_SVME  (1 << 12)
517 #define MSR_EFER_FFXSR (1 << 14)
518 
519 #define MSR_EFER_RESERVED\
520         (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
521             | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
522             | MSR_EFER_FFXSR))
523 
524 #define MSR_STAR                        0xc0000081
525 #define MSR_LSTAR                       0xc0000082
526 #define MSR_CSTAR                       0xc0000083
527 #define MSR_FMASK                       0xc0000084
528 #define MSR_FSBASE                      0xc0000100
529 #define MSR_GSBASE                      0xc0000101
530 #define MSR_KERNELGSBASE                0xc0000102
531 #define MSR_TSC_AUX                     0xc0000103
532 #define MSR_AMD64_TSC_RATIO             0xc0000104
533 
534 #define MSR_AMD64_TSC_RATIO_DEFAULT     0x100000000ULL
535 
536 #define MSR_K7_HWCR                     0xc0010015
537 
538 #define MSR_VM_HSAVE_PA                 0xc0010117
539 
540 #define MSR_IA32_XFD                    0x000001c4
541 #define MSR_IA32_XFD_ERR                0x000001c5
542 
543 /* FRED MSRs */
544 #define MSR_IA32_FRED_RSP0              0x000001cc       /* Stack level 0 regular stack pointer */
545 #define MSR_IA32_FRED_RSP1              0x000001cd       /* Stack level 1 regular stack pointer */
546 #define MSR_IA32_FRED_RSP2              0x000001ce       /* Stack level 2 regular stack pointer */
547 #define MSR_IA32_FRED_RSP3              0x000001cf       /* Stack level 3 regular stack pointer */
548 #define MSR_IA32_FRED_STKLVLS           0x000001d0       /* FRED exception stack levels */
549 #define MSR_IA32_FRED_SSP1              0x000001d1       /* Stack level 1 shadow stack pointer in ring 0 */
550 #define MSR_IA32_FRED_SSP2              0x000001d2       /* Stack level 2 shadow stack pointer in ring 0 */
551 #define MSR_IA32_FRED_SSP3              0x000001d3       /* Stack level 3 shadow stack pointer in ring 0 */
552 #define MSR_IA32_FRED_CONFIG            0x000001d4       /* FRED Entrypoint and interrupt stack level */
553 
554 #define MSR_IA32_BNDCFGS                0x00000d90
555 #define MSR_IA32_XSS                    0x00000da0
556 #define MSR_IA32_UMWAIT_CONTROL         0xe1
557 
558 #define MSR_IA32_VMX_BASIC              0x00000480
559 #define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
560 #define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
561 #define MSR_IA32_VMX_EXIT_CTLS          0x00000483
562 #define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
563 #define MSR_IA32_VMX_MISC               0x00000485
564 #define MSR_IA32_VMX_CR0_FIXED0         0x00000486
565 #define MSR_IA32_VMX_CR0_FIXED1         0x00000487
566 #define MSR_IA32_VMX_CR4_FIXED0         0x00000488
567 #define MSR_IA32_VMX_CR4_FIXED1         0x00000489
568 #define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
569 #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
570 #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
571 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
572 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
573 #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
574 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
575 #define MSR_IA32_VMX_VMFUNC             0x00000491
576 
577 #define MSR_APIC_START                  0x00000800
578 #define MSR_APIC_END                    0x000008ff
579 
580 #define XSTATE_FP_BIT                   0
581 #define XSTATE_SSE_BIT                  1
582 #define XSTATE_YMM_BIT                  2
583 #define XSTATE_BNDREGS_BIT              3
584 #define XSTATE_BNDCSR_BIT               4
585 #define XSTATE_OPMASK_BIT               5
586 #define XSTATE_ZMM_Hi256_BIT            6
587 #define XSTATE_Hi16_ZMM_BIT             7
588 #define XSTATE_PKRU_BIT                 9
589 #define XSTATE_ARCH_LBR_BIT             15
590 #define XSTATE_XTILE_CFG_BIT            17
591 #define XSTATE_XTILE_DATA_BIT           18
592 
593 #define XSTATE_FP_MASK                  (1ULL << XSTATE_FP_BIT)
594 #define XSTATE_SSE_MASK                 (1ULL << XSTATE_SSE_BIT)
595 #define XSTATE_YMM_MASK                 (1ULL << XSTATE_YMM_BIT)
596 #define XSTATE_BNDREGS_MASK             (1ULL << XSTATE_BNDREGS_BIT)
597 #define XSTATE_BNDCSR_MASK              (1ULL << XSTATE_BNDCSR_BIT)
598 #define XSTATE_OPMASK_MASK              (1ULL << XSTATE_OPMASK_BIT)
599 #define XSTATE_ZMM_Hi256_MASK           (1ULL << XSTATE_ZMM_Hi256_BIT)
600 #define XSTATE_Hi16_ZMM_MASK            (1ULL << XSTATE_Hi16_ZMM_BIT)
601 #define XSTATE_PKRU_MASK                (1ULL << XSTATE_PKRU_BIT)
602 #define XSTATE_ARCH_LBR_MASK            (1ULL << XSTATE_ARCH_LBR_BIT)
603 #define XSTATE_XTILE_CFG_MASK           (1ULL << XSTATE_XTILE_CFG_BIT)
604 #define XSTATE_XTILE_DATA_MASK          (1ULL << XSTATE_XTILE_DATA_BIT)
605 
606 #define XSTATE_DYNAMIC_MASK             (XSTATE_XTILE_DATA_MASK)
607 
608 #define ESA_FEATURE_ALIGN64_BIT         1
609 #define ESA_FEATURE_XFD_BIT             2
610 
611 #define ESA_FEATURE_ALIGN64_MASK        (1U << ESA_FEATURE_ALIGN64_BIT)
612 #define ESA_FEATURE_XFD_MASK            (1U << ESA_FEATURE_XFD_BIT)
613 
614 
615 /* CPUID feature bits available in XCR0 */
616 #define CPUID_XSTATE_XCR0_MASK  (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
617                                  XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
618                                  XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
619                                  XSTATE_ZMM_Hi256_MASK | \
620                                  XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
621                                  XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
622 
623 /* CPUID feature words */
624 typedef enum FeatureWord {
625     FEAT_1_EDX,         /* CPUID[1].EDX */
626     FEAT_1_ECX,         /* CPUID[1].ECX */
627     FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
628     FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */
629     FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */
630     FEAT_7_1_EAX,       /* CPUID[EAX=7,ECX=1].EAX */
631     FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
632     FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
633     FEAT_8000_0007_EBX, /* CPUID[8000_0007].EBX */
634     FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
635     FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
636     FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
637     FEAT_8000_0021_EBX, /* CPUID[8000_0021].EBX */
638     FEAT_8000_0022_EAX, /* CPUID[8000_0022].EAX */
639     FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
640     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
641     FEAT_KVM_HINTS,     /* CPUID[4000_0001].EDX */
642     FEAT_SVM,           /* CPUID[8000_000A].EDX */
643     FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */
644     FEAT_6_EAX,         /* CPUID[6].EAX */
645     FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
646     FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
647     FEAT_ARCH_CAPABILITIES,
648     FEAT_CORE_CAPABILITY,
649     FEAT_PERF_CAPABILITIES,
650     FEAT_VMX_PROCBASED_CTLS,
651     FEAT_VMX_SECONDARY_CTLS,
652     FEAT_VMX_PINBASED_CTLS,
653     FEAT_VMX_EXIT_CTLS,
654     FEAT_VMX_ENTRY_CTLS,
655     FEAT_VMX_MISC,
656     FEAT_VMX_EPT_VPID_CAPS,
657     FEAT_VMX_BASIC,
658     FEAT_VMX_VMFUNC,
659     FEAT_14_0_ECX,
660     FEAT_SGX_12_0_EAX,  /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
661     FEAT_SGX_12_0_EBX,  /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
662     FEAT_SGX_12_1_EAX,  /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
663     FEAT_XSAVE_XSS_LO,     /* CPUID[EAX=0xd,ECX=1].ECX */
664     FEAT_XSAVE_XSS_HI,     /* CPUID[EAX=0xd,ECX=1].EDX */
665     FEAT_7_1_EDX,       /* CPUID[EAX=7,ECX=1].EDX */
666     FEAT_7_2_EDX,       /* CPUID[EAX=7,ECX=2].EDX */
667     FEATURE_WORDS,
668 } FeatureWord;
669 
670 typedef uint64_t FeatureWordArray[FEATURE_WORDS];
671 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
672 
673 /* cpuid_features bits */
674 #define CPUID_FP87 (1U << 0)
675 #define CPUID_VME  (1U << 1)
676 #define CPUID_DE   (1U << 2)
677 #define CPUID_PSE  (1U << 3)
678 #define CPUID_TSC  (1U << 4)
679 #define CPUID_MSR  (1U << 5)
680 #define CPUID_PAE  (1U << 6)
681 #define CPUID_MCE  (1U << 7)
682 #define CPUID_CX8  (1U << 8)
683 #define CPUID_APIC (1U << 9)
684 #define CPUID_SEP  (1U << 11) /* sysenter/sysexit */
685 #define CPUID_MTRR (1U << 12)
686 #define CPUID_PGE  (1U << 13)
687 #define CPUID_MCA  (1U << 14)
688 #define CPUID_CMOV (1U << 15)
689 #define CPUID_PAT  (1U << 16)
690 #define CPUID_PSE36   (1U << 17)
691 #define CPUID_PN   (1U << 18)
692 #define CPUID_CLFLUSH (1U << 19)
693 #define CPUID_DTS (1U << 21)
694 #define CPUID_ACPI (1U << 22)
695 #define CPUID_MMX  (1U << 23)
696 #define CPUID_FXSR (1U << 24)
697 #define CPUID_SSE  (1U << 25)
698 #define CPUID_SSE2 (1U << 26)
699 #define CPUID_SS (1U << 27)
700 #define CPUID_HT (1U << 28)
701 #define CPUID_TM (1U << 29)
702 #define CPUID_IA64 (1U << 30)
703 #define CPUID_PBE (1U << 31)
704 
705 #define CPUID_EXT_SSE3     (1U << 0)
706 #define CPUID_EXT_PCLMULQDQ (1U << 1)
707 #define CPUID_EXT_DTES64   (1U << 2)
708 #define CPUID_EXT_MONITOR  (1U << 3)
709 #define CPUID_EXT_DSCPL    (1U << 4)
710 #define CPUID_EXT_VMX      (1U << 5)
711 #define CPUID_EXT_SMX      (1U << 6)
712 #define CPUID_EXT_EST      (1U << 7)
713 #define CPUID_EXT_TM2      (1U << 8)
714 #define CPUID_EXT_SSSE3    (1U << 9)
715 #define CPUID_EXT_CID      (1U << 10)
716 #define CPUID_EXT_FMA      (1U << 12)
717 #define CPUID_EXT_CX16     (1U << 13)
718 #define CPUID_EXT_XTPR     (1U << 14)
719 #define CPUID_EXT_PDCM     (1U << 15)
720 #define CPUID_EXT_PCID     (1U << 17)
721 #define CPUID_EXT_DCA      (1U << 18)
722 #define CPUID_EXT_SSE41    (1U << 19)
723 #define CPUID_EXT_SSE42    (1U << 20)
724 #define CPUID_EXT_X2APIC   (1U << 21)
725 #define CPUID_EXT_MOVBE    (1U << 22)
726 #define CPUID_EXT_POPCNT   (1U << 23)
727 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
728 #define CPUID_EXT_AES      (1U << 25)
729 #define CPUID_EXT_XSAVE    (1U << 26)
730 #define CPUID_EXT_OSXSAVE  (1U << 27)
731 #define CPUID_EXT_AVX      (1U << 28)
732 #define CPUID_EXT_F16C     (1U << 29)
733 #define CPUID_EXT_RDRAND   (1U << 30)
734 #define CPUID_EXT_HYPERVISOR  (1U << 31)
735 
736 #define CPUID_EXT2_FPU     (1U << 0)
737 #define CPUID_EXT2_VME     (1U << 1)
738 #define CPUID_EXT2_DE      (1U << 2)
739 #define CPUID_EXT2_PSE     (1U << 3)
740 #define CPUID_EXT2_TSC     (1U << 4)
741 #define CPUID_EXT2_MSR     (1U << 5)
742 #define CPUID_EXT2_PAE     (1U << 6)
743 #define CPUID_EXT2_MCE     (1U << 7)
744 #define CPUID_EXT2_CX8     (1U << 8)
745 #define CPUID_EXT2_APIC    (1U << 9)
746 #define CPUID_EXT2_SYSCALL (1U << 11)
747 #define CPUID_EXT2_MTRR    (1U << 12)
748 #define CPUID_EXT2_PGE     (1U << 13)
749 #define CPUID_EXT2_MCA     (1U << 14)
750 #define CPUID_EXT2_CMOV    (1U << 15)
751 #define CPUID_EXT2_PAT     (1U << 16)
752 #define CPUID_EXT2_PSE36   (1U << 17)
753 #define CPUID_EXT2_MP      (1U << 19)
754 #define CPUID_EXT2_NX      (1U << 20)
755 #define CPUID_EXT2_MMXEXT  (1U << 22)
756 #define CPUID_EXT2_MMX     (1U << 23)
757 #define CPUID_EXT2_FXSR    (1U << 24)
758 #define CPUID_EXT2_FFXSR   (1U << 25)
759 #define CPUID_EXT2_PDPE1GB (1U << 26)
760 #define CPUID_EXT2_RDTSCP  (1U << 27)
761 #define CPUID_EXT2_LM      (1U << 29)
762 #define CPUID_EXT2_3DNOWEXT (1U << 30)
763 #define CPUID_EXT2_3DNOW   (1U << 31)
764 
765 /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */
766 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
767                                 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
768                                 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
769                                 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
770                                 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
771                                 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
772                                 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
773                                 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
774                                 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
775 
776 #define CPUID_EXT3_LAHF_LM (1U << 0)
777 #define CPUID_EXT3_CMP_LEG (1U << 1)
778 #define CPUID_EXT3_SVM     (1U << 2)
779 #define CPUID_EXT3_EXTAPIC (1U << 3)
780 #define CPUID_EXT3_CR8LEG  (1U << 4)
781 #define CPUID_EXT3_ABM     (1U << 5)
782 #define CPUID_EXT3_SSE4A   (1U << 6)
783 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
784 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
785 #define CPUID_EXT3_OSVW    (1U << 9)
786 #define CPUID_EXT3_IBS     (1U << 10)
787 #define CPUID_EXT3_XOP     (1U << 11)
788 #define CPUID_EXT3_SKINIT  (1U << 12)
789 #define CPUID_EXT3_WDT     (1U << 13)
790 #define CPUID_EXT3_LWP     (1U << 15)
791 #define CPUID_EXT3_FMA4    (1U << 16)
792 #define CPUID_EXT3_TCE     (1U << 17)
793 #define CPUID_EXT3_NODEID  (1U << 19)
794 #define CPUID_EXT3_TBM     (1U << 21)
795 #define CPUID_EXT3_TOPOEXT (1U << 22)
796 #define CPUID_EXT3_PERFCORE (1U << 23)
797 #define CPUID_EXT3_PERFNB  (1U << 24)
798 
799 #define CPUID_SVM_NPT             (1U << 0)
800 #define CPUID_SVM_LBRV            (1U << 1)
801 #define CPUID_SVM_SVMLOCK         (1U << 2)
802 #define CPUID_SVM_NRIPSAVE        (1U << 3)
803 #define CPUID_SVM_TSCSCALE        (1U << 4)
804 #define CPUID_SVM_VMCBCLEAN       (1U << 5)
805 #define CPUID_SVM_FLUSHASID       (1U << 6)
806 #define CPUID_SVM_DECODEASSIST    (1U << 7)
807 #define CPUID_SVM_PAUSEFILTER     (1U << 10)
808 #define CPUID_SVM_PFTHRESHOLD     (1U << 12)
809 #define CPUID_SVM_AVIC            (1U << 13)
810 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
811 #define CPUID_SVM_VGIF            (1U << 16)
812 #define CPUID_SVM_VNMI            (1U << 25)
813 #define CPUID_SVM_SVME_ADDR_CHK   (1U << 28)
814 
815 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
816 #define CPUID_7_0_EBX_FSGSBASE          (1U << 0)
817 /* Support TSC adjust MSR */
818 #define CPUID_7_0_EBX_TSC_ADJUST        (1U << 1)
819 /* Support SGX */
820 #define CPUID_7_0_EBX_SGX               (1U << 2)
821 /* 1st Group of Advanced Bit Manipulation Extensions */
822 #define CPUID_7_0_EBX_BMI1              (1U << 3)
823 /* Hardware Lock Elision */
824 #define CPUID_7_0_EBX_HLE               (1U << 4)
825 /* Intel Advanced Vector Extensions 2 */
826 #define CPUID_7_0_EBX_AVX2              (1U << 5)
827 /* FPU data pointer updated only on x87 exceptions */
828 #define CPUID_7_0_EBX_FDP_EXCPTN_ONLY (1u << 6)
829 /* Supervisor-mode Execution Prevention */
830 #define CPUID_7_0_EBX_SMEP              (1U << 7)
831 /* 2nd Group of Advanced Bit Manipulation Extensions */
832 #define CPUID_7_0_EBX_BMI2              (1U << 8)
833 /* Enhanced REP MOVSB/STOSB */
834 #define CPUID_7_0_EBX_ERMS              (1U << 9)
835 /* Invalidate Process-Context Identifier */
836 #define CPUID_7_0_EBX_INVPCID           (1U << 10)
837 /* Restricted Transactional Memory */
838 #define CPUID_7_0_EBX_RTM               (1U << 11)
839 /* Zero out FPU CS and FPU DS */
840 #define CPUID_7_0_EBX_ZERO_FCS_FDS      (1U << 13)
841 /* Memory Protection Extension */
842 #define CPUID_7_0_EBX_MPX               (1U << 14)
843 /* AVX-512 Foundation */
844 #define CPUID_7_0_EBX_AVX512F           (1U << 16)
845 /* AVX-512 Doubleword & Quadword Instruction */
846 #define CPUID_7_0_EBX_AVX512DQ          (1U << 17)
847 /* Read Random SEED */
848 #define CPUID_7_0_EBX_RDSEED            (1U << 18)
849 /* ADCX and ADOX instructions */
850 #define CPUID_7_0_EBX_ADX               (1U << 19)
851 /* Supervisor Mode Access Prevention */
852 #define CPUID_7_0_EBX_SMAP              (1U << 20)
853 /* AVX-512 Integer Fused Multiply Add */
854 #define CPUID_7_0_EBX_AVX512IFMA        (1U << 21)
855 /* Flush a Cache Line Optimized */
856 #define CPUID_7_0_EBX_CLFLUSHOPT        (1U << 23)
857 /* Cache Line Write Back */
858 #define CPUID_7_0_EBX_CLWB              (1U << 24)
859 /* Intel Processor Trace */
860 #define CPUID_7_0_EBX_INTEL_PT          (1U << 25)
861 /* AVX-512 Prefetch */
862 #define CPUID_7_0_EBX_AVX512PF          (1U << 26)
863 /* AVX-512 Exponential and Reciprocal */
864 #define CPUID_7_0_EBX_AVX512ER          (1U << 27)
865 /* AVX-512 Conflict Detection */
866 #define CPUID_7_0_EBX_AVX512CD          (1U << 28)
867 /* SHA1/SHA256 Instruction Extensions */
868 #define CPUID_7_0_EBX_SHA_NI            (1U << 29)
869 /* AVX-512 Byte and Word Instructions */
870 #define CPUID_7_0_EBX_AVX512BW          (1U << 30)
871 /* AVX-512 Vector Length Extensions */
872 #define CPUID_7_0_EBX_AVX512VL          (1U << 31)
873 
874 /* AVX-512 Vector Byte Manipulation Instruction */
875 #define CPUID_7_0_ECX_AVX512_VBMI       (1U << 1)
876 /* User-Mode Instruction Prevention */
877 #define CPUID_7_0_ECX_UMIP              (1U << 2)
878 /* Protection Keys for User-mode Pages */
879 #define CPUID_7_0_ECX_PKU               (1U << 3)
880 /* OS Enable Protection Keys */
881 #define CPUID_7_0_ECX_OSPKE             (1U << 4)
882 /* UMONITOR/UMWAIT/TPAUSE Instructions */
883 #define CPUID_7_0_ECX_WAITPKG           (1U << 5)
884 /* Additional AVX-512 Vector Byte Manipulation Instruction */
885 #define CPUID_7_0_ECX_AVX512_VBMI2      (1U << 6)
886 /* Galois Field New Instructions */
887 #define CPUID_7_0_ECX_GFNI              (1U << 8)
888 /* Vector AES Instructions */
889 #define CPUID_7_0_ECX_VAES              (1U << 9)
890 /* Carry-Less Multiplication Quadword */
891 #define CPUID_7_0_ECX_VPCLMULQDQ        (1U << 10)
892 /* Vector Neural Network Instructions */
893 #define CPUID_7_0_ECX_AVX512VNNI        (1U << 11)
894 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
895 #define CPUID_7_0_ECX_AVX512BITALG      (1U << 12)
896 /* POPCNT for vectors of DW/QW */
897 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ  (1U << 14)
898 /* 5-level Page Tables */
899 #define CPUID_7_0_ECX_LA57              (1U << 16)
900 /* Read Processor ID */
901 #define CPUID_7_0_ECX_RDPID             (1U << 22)
902 /* Bus Lock Debug Exception */
903 #define CPUID_7_0_ECX_BUS_LOCK_DETECT   (1U << 24)
904 /* Cache Line Demote Instruction */
905 #define CPUID_7_0_ECX_CLDEMOTE          (1U << 25)
906 /* Move Doubleword as Direct Store Instruction */
907 #define CPUID_7_0_ECX_MOVDIRI           (1U << 27)
908 /* Move 64 Bytes as Direct Store Instruction */
909 #define CPUID_7_0_ECX_MOVDIR64B         (1U << 28)
910 /* Support SGX Launch Control */
911 #define CPUID_7_0_ECX_SGX_LC            (1U << 30)
912 /* Protection Keys for Supervisor-mode Pages */
913 #define CPUID_7_0_ECX_PKS               (1U << 31)
914 
915 /* AVX512 Neural Network Instructions */
916 #define CPUID_7_0_EDX_AVX512_4VNNIW     (1U << 2)
917 /* AVX512 Multiply Accumulation Single Precision */
918 #define CPUID_7_0_EDX_AVX512_4FMAPS     (1U << 3)
919 /* Fast Short Rep Mov */
920 #define CPUID_7_0_EDX_FSRM              (1U << 4)
921 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
922 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
923 /* SERIALIZE instruction */
924 #define CPUID_7_0_EDX_SERIALIZE         (1U << 14)
925 /* TSX Suspend Load Address Tracking instruction */
926 #define CPUID_7_0_EDX_TSX_LDTRK         (1U << 16)
927 /* Architectural LBRs */
928 #define CPUID_7_0_EDX_ARCH_LBR          (1U << 19)
929 /* AMX_BF16 instruction */
930 #define CPUID_7_0_EDX_AMX_BF16          (1U << 22)
931 /* AVX512_FP16 instruction */
932 #define CPUID_7_0_EDX_AVX512_FP16       (1U << 23)
933 /* AMX tile (two-dimensional register) */
934 #define CPUID_7_0_EDX_AMX_TILE          (1U << 24)
935 /* AMX_INT8 instruction */
936 #define CPUID_7_0_EDX_AMX_INT8          (1U << 25)
937 /* Speculation Control */
938 #define CPUID_7_0_EDX_SPEC_CTRL         (1U << 26)
939 /* Single Thread Indirect Branch Predictors */
940 #define CPUID_7_0_EDX_STIBP             (1U << 27)
941 /* Flush L1D cache */
942 #define CPUID_7_0_EDX_FLUSH_L1D         (1U << 28)
943 /* Arch Capabilities */
944 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
945 /* Core Capability */
946 #define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)
947 /* Speculative Store Bypass Disable */
948 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD    (1U << 31)
949 
950 /* AVX VNNI Instruction */
951 #define CPUID_7_1_EAX_AVX_VNNI          (1U << 4)
952 /* AVX512 BFloat16 Instruction */
953 #define CPUID_7_1_EAX_AVX512_BF16       (1U << 5)
954 /* CMPCCXADD Instructions */
955 #define CPUID_7_1_EAX_CMPCCXADD         (1U << 7)
956 /* Fast Zero REP MOVS */
957 #define CPUID_7_1_EAX_FZRM              (1U << 10)
958 /* Fast Short REP STOS */
959 #define CPUID_7_1_EAX_FSRS              (1U << 11)
960 /* Fast Short REP CMPS/SCAS */
961 #define CPUID_7_1_EAX_FSRC              (1U << 12)
962 /* Support Tile Computational Operations on FP16 Numbers */
963 #define CPUID_7_1_EAX_AMX_FP16          (1U << 21)
964 /* Support for VPMADD52[H,L]UQ */
965 #define CPUID_7_1_EAX_AVX_IFMA          (1U << 23)
966 /* Linear Address Masking */
967 #define CPUID_7_1_EAX_LAM               (1U << 26)
968 
969 /* Support for VPDPB[SU,UU,SS]D[,S] */
970 #define CPUID_7_1_EDX_AVX_VNNI_INT8     (1U << 4)
971 /* AVX NE CONVERT Instructions */
972 #define CPUID_7_1_EDX_AVX_NE_CONVERT    (1U << 5)
973 /* AMX COMPLEX Instructions */
974 #define CPUID_7_1_EDX_AMX_COMPLEX       (1U << 8)
975 /* PREFETCHIT0/1 Instructions */
976 #define CPUID_7_1_EDX_PREFETCHITI       (1U << 14)
977 /* Flexible return and event delivery (FRED) */
978 #define CPUID_7_1_EAX_FRED              (1U << 17)
979 /* Load into IA32_KERNEL_GS_BASE (LKGS) */
980 #define CPUID_7_1_EAX_LKGS              (1U << 18)
981 /* Non-Serializing Write to Model Specific Register (WRMSRNS) */
982 #define CPUID_7_1_EAX_WRMSRNS           (1U << 19)
983 
984 /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
985 #define CPUID_7_2_EDX_MCDT_NO           (1U << 5)
986 
987 /* XFD Extend Feature Disabled */
988 #define CPUID_D_1_EAX_XFD               (1U << 4)
989 
990 /* Packets which contain IP payload have LIP values */
991 #define CPUID_14_0_ECX_LIP              (1U << 31)
992 
993 /* RAS Features */
994 #define CPUID_8000_0007_EBX_OVERFLOW_RECOV    (1U << 0)
995 #define CPUID_8000_0007_EBX_SUCCOR      (1U << 1)
996 
997 /* CLZERO instruction */
998 #define CPUID_8000_0008_EBX_CLZERO      (1U << 0)
999 /* Always save/restore FP error pointers */
1000 #define CPUID_8000_0008_EBX_XSAVEERPTR  (1U << 2)
1001 /* Write back and do not invalidate cache */
1002 #define CPUID_8000_0008_EBX_WBNOINVD    (1U << 9)
1003 /* Indirect Branch Prediction Barrier */
1004 #define CPUID_8000_0008_EBX_IBPB        (1U << 12)
1005 /* Indirect Branch Restricted Speculation */
1006 #define CPUID_8000_0008_EBX_IBRS        (1U << 14)
1007 /* Single Thread Indirect Branch Predictors */
1008 #define CPUID_8000_0008_EBX_STIBP       (1U << 15)
1009 /* STIBP mode has enhanced performance and may be left always on */
1010 #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON    (1U << 17)
1011 /* Speculative Store Bypass Disable */
1012 #define CPUID_8000_0008_EBX_AMD_SSBD    (1U << 24)
1013 /* Paravirtualized Speculative Store Bypass Disable MSR */
1014 #define CPUID_8000_0008_EBX_VIRT_SSBD   (1U << 25)
1015 /* Predictive Store Forwarding Disable */
1016 #define CPUID_8000_0008_EBX_AMD_PSFD    (1U << 28)
1017 
1018 /* Processor ignores nested data breakpoints */
1019 #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP            (1U << 0)
1020 /* LFENCE is always serializing */
1021 #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING    (1U << 2)
1022 /* Null Selector Clears Base */
1023 #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE            (1U << 6)
1024 /* Automatic IBRS */
1025 #define CPUID_8000_0021_EAX_AUTO_IBRS                    (1U << 8)
1026 /* Enhanced Return Address Predictor Scurity */
1027 #define CPUID_8000_0021_EAX_ERAPS                        (1U << 24)
1028 /* Selective Branch Predictor Barrier */
1029 #define CPUID_8000_0021_EAX_SBPB                         (1U << 27)
1030 /* IBPB includes branch type prediction flushing */
1031 #define CPUID_8000_0021_EAX_IBPB_BRTYPE                  (1U << 28)
1032 /* Not vulnerable to Speculative Return Stack Overflow */
1033 #define CPUID_8000_0021_EAX_SRSO_NO                      (1U << 29)
1034 /* Not vulnerable to SRSO at the user-kernel boundary */
1035 #define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO          (1U << 30)
1036 
1037 /*
1038  * Return Address Predictor size. RapSize x 8 is the minimum number of
1039  * CALL instructions software needs to execute to flush the RAP.
1040  */
1041 #define CPUID_8000_0021_EBX_RAPSIZE    (8U << 16)
1042 
1043 /* Performance Monitoring Version 2 */
1044 #define CPUID_8000_0022_EAX_PERFMON_V2  (1U << 0)
1045 
1046 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
1047 #define CPUID_XSAVE_XSAVEC     (1U << 1)
1048 #define CPUID_XSAVE_XGETBV1    (1U << 2)
1049 #define CPUID_XSAVE_XSAVES     (1U << 3)
1050 
1051 #define CPUID_6_EAX_ARAT       (1U << 2)
1052 
1053 /* CPUID[0x80000007].EDX flags: */
1054 #define CPUID_APM_INVTSC       (1U << 8)
1055 
1056 #define CPUID_VENDOR_SZ      12
1057 
1058 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
1059 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
1060 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
1061 #define CPUID_VENDOR_INTEL "GenuineIntel"
1062 
1063 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
1064 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
1065 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
1066 #define CPUID_VENDOR_AMD   "AuthenticAMD"
1067 
1068 #define CPUID_VENDOR_VIA   "CentaurHauls"
1069 
1070 #define CPUID_VENDOR_HYGON    "HygonGenuine"
1071 
1072 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
1073                            (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
1074                            (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
1075 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
1076                          (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
1077                          (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
1078 
1079 #define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
1080 #define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
1081 
1082 /* CPUID[0xB].ECX level types */
1083 #define CPUID_B_ECX_TOPO_LEVEL_INVALID  0
1084 #define CPUID_B_ECX_TOPO_LEVEL_SMT      1
1085 #define CPUID_B_ECX_TOPO_LEVEL_CORE     2
1086 
1087 /* COUID[0x1F].ECX level types */
1088 #define CPUID_1F_ECX_TOPO_LEVEL_INVALID  CPUID_B_ECX_TOPO_LEVEL_INVALID
1089 #define CPUID_1F_ECX_TOPO_LEVEL_SMT      CPUID_B_ECX_TOPO_LEVEL_SMT
1090 #define CPUID_1F_ECX_TOPO_LEVEL_CORE     CPUID_B_ECX_TOPO_LEVEL_CORE
1091 #define CPUID_1F_ECX_TOPO_LEVEL_MODULE   3
1092 #define CPUID_1F_ECX_TOPO_LEVEL_DIE      5
1093 
1094 /* MSR Feature Bits */
1095 #define MSR_ARCH_CAP_RDCL_NO            (1U << 0)
1096 #define MSR_ARCH_CAP_IBRS_ALL           (1U << 1)
1097 #define MSR_ARCH_CAP_RSBA               (1U << 2)
1098 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1099 #define MSR_ARCH_CAP_SSB_NO             (1U << 4)
1100 #define MSR_ARCH_CAP_MDS_NO             (1U << 5)
1101 #define MSR_ARCH_CAP_PSCHANGE_MC_NO     (1U << 6)
1102 #define MSR_ARCH_CAP_TSX_CTRL_MSR       (1U << 7)
1103 #define MSR_ARCH_CAP_TAA_NO             (1U << 8)
1104 #define MSR_ARCH_CAP_SBDR_SSDP_NO       (1U << 13)
1105 #define MSR_ARCH_CAP_FBSDP_NO           (1U << 14)
1106 #define MSR_ARCH_CAP_PSDP_NO            (1U << 15)
1107 #define MSR_ARCH_CAP_FB_CLEAR           (1U << 17)
1108 #define MSR_ARCH_CAP_PBRSB_NO           (1U << 24)
1109 
1110 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
1111 
1112 /* VMX MSR features */
1113 #define MSR_VMX_BASIC_VMCS_REVISION_MASK             0x7FFFFFFFull
1114 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK         (0x00001FFFull << 32)
1115 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK             (0x003C0000ull << 32)
1116 #define MSR_VMX_BASIC_DUAL_MONITOR                   (1ULL << 49)
1117 #define MSR_VMX_BASIC_INS_OUTS                       (1ULL << 54)
1118 #define MSR_VMX_BASIC_TRUE_CTLS                      (1ULL << 55)
1119 #define MSR_VMX_BASIC_ANY_ERRCODE                    (1ULL << 56)
1120 #define MSR_VMX_BASIC_NESTED_EXCEPTION               (1ULL << 58)
1121 
1122 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK     0x1Full
1123 #define MSR_VMX_MISC_STORE_LMA                       (1ULL << 5)
1124 #define MSR_VMX_MISC_ACTIVITY_HLT                    (1ULL << 6)
1125 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN               (1ULL << 7)
1126 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI              (1ULL << 8)
1127 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK          0x0E000000ull
1128 #define MSR_VMX_MISC_VMWRITE_VMEXIT                  (1ULL << 29)
1129 #define MSR_VMX_MISC_ZERO_LEN_INJECT                 (1ULL << 30)
1130 
1131 #define MSR_VMX_EPT_EXECONLY                         (1ULL << 0)
1132 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4               (1ULL << 6)
1133 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5               (1ULL << 7)
1134 #define MSR_VMX_EPT_UC                               (1ULL << 8)
1135 #define MSR_VMX_EPT_WB                               (1ULL << 14)
1136 #define MSR_VMX_EPT_2MB                              (1ULL << 16)
1137 #define MSR_VMX_EPT_1GB                              (1ULL << 17)
1138 #define MSR_VMX_EPT_INVEPT                           (1ULL << 20)
1139 #define MSR_VMX_EPT_AD_BITS                          (1ULL << 21)
1140 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO             (1ULL << 22)
1141 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT            (1ULL << 25)
1142 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT               (1ULL << 26)
1143 #define MSR_VMX_EPT_INVVPID                          (1ULL << 32)
1144 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR              (1ULL << 40)
1145 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT           (1ULL << 41)
1146 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT              (1ULL << 42)
1147 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1148 
1149 #define MSR_VMX_VMFUNC_EPT_SWITCHING                 (1ULL << 0)
1150 
1151 
1152 /* VMX controls */
1153 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
1154 #define VMX_CPU_BASED_USE_TSC_OFFSETING             0x00000008
1155 #define VMX_CPU_BASED_HLT_EXITING                   0x00000080
1156 #define VMX_CPU_BASED_INVLPG_EXITING                0x00000200
1157 #define VMX_CPU_BASED_MWAIT_EXITING                 0x00000400
1158 #define VMX_CPU_BASED_RDPMC_EXITING                 0x00000800
1159 #define VMX_CPU_BASED_RDTSC_EXITING                 0x00001000
1160 #define VMX_CPU_BASED_CR3_LOAD_EXITING              0x00008000
1161 #define VMX_CPU_BASED_CR3_STORE_EXITING             0x00010000
1162 #define VMX_CPU_BASED_CR8_LOAD_EXITING              0x00080000
1163 #define VMX_CPU_BASED_CR8_STORE_EXITING             0x00100000
1164 #define VMX_CPU_BASED_TPR_SHADOW                    0x00200000
1165 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
1166 #define VMX_CPU_BASED_MOV_DR_EXITING                0x00800000
1167 #define VMX_CPU_BASED_UNCOND_IO_EXITING             0x01000000
1168 #define VMX_CPU_BASED_USE_IO_BITMAPS                0x02000000
1169 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG             0x08000000
1170 #define VMX_CPU_BASED_USE_MSR_BITMAPS               0x10000000
1171 #define VMX_CPU_BASED_MONITOR_EXITING               0x20000000
1172 #define VMX_CPU_BASED_PAUSE_EXITING                 0x40000000
1173 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
1174 
1175 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1176 #define VMX_SECONDARY_EXEC_ENABLE_EPT               0x00000002
1177 #define VMX_SECONDARY_EXEC_DESC                     0x00000004
1178 #define VMX_SECONDARY_EXEC_RDTSCP                   0x00000008
1179 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
1180 #define VMX_SECONDARY_EXEC_ENABLE_VPID              0x00000020
1181 #define VMX_SECONDARY_EXEC_WBINVD_EXITING           0x00000040
1182 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
1183 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
1184 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
1185 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
1186 #define VMX_SECONDARY_EXEC_RDRAND_EXITING           0x00000800
1187 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
1188 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC            0x00002000
1189 #define VMX_SECONDARY_EXEC_SHADOW_VMCS              0x00004000
1190 #define VMX_SECONDARY_EXEC_ENCLS_EXITING            0x00008000
1191 #define VMX_SECONDARY_EXEC_RDSEED_EXITING           0x00010000
1192 #define VMX_SECONDARY_EXEC_ENABLE_PML               0x00020000
1193 #define VMX_SECONDARY_EXEC_XSAVES                   0x00100000
1194 #define VMX_SECONDARY_EXEC_TSC_SCALING              0x02000000
1195 #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE   0x04000000
1196 
1197 #define VMX_PIN_BASED_EXT_INTR_MASK                 0x00000001
1198 #define VMX_PIN_BASED_NMI_EXITING                   0x00000008
1199 #define VMX_PIN_BASED_VIRTUAL_NMIS                  0x00000020
1200 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
1201 #define VMX_PIN_BASED_POSTED_INTR                   0x00000080
1202 
1203 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
1204 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
1205 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
1206 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
1207 #define VMX_VM_EXIT_SAVE_IA32_PAT                   0x00040000
1208 #define VMX_VM_EXIT_LOAD_IA32_PAT                   0x00080000
1209 #define VMX_VM_EXIT_SAVE_IA32_EFER                  0x00100000
1210 #define VMX_VM_EXIT_LOAD_IA32_EFER                  0x00200000
1211 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
1212 #define VMX_VM_EXIT_CLEAR_BNDCFGS                   0x00800000
1213 #define VMX_VM_EXIT_PT_CONCEAL_PIP                  0x01000000
1214 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL             0x02000000
1215 #define VMX_VM_EXIT_LOAD_IA32_PKRS                  0x20000000
1216 #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS     0x80000000
1217 
1218 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
1219 #define VMX_VM_ENTRY_IA32E_MODE                     0x00000200
1220 #define VMX_VM_ENTRY_SMM                            0x00000400
1221 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
1222 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
1223 #define VMX_VM_ENTRY_LOAD_IA32_PAT                  0x00004000
1224 #define VMX_VM_ENTRY_LOAD_IA32_EFER                 0x00008000
1225 #define VMX_VM_ENTRY_LOAD_BNDCFGS                   0x00010000
1226 #define VMX_VM_ENTRY_PT_CONCEAL_PIP                 0x00020000
1227 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL             0x00040000
1228 #define VMX_VM_ENTRY_LOAD_IA32_PKRS                 0x00400000
1229 
1230 /* Supported Hyper-V Enlightenments */
1231 #define HYPERV_FEAT_RELAXED             0
1232 #define HYPERV_FEAT_VAPIC               1
1233 #define HYPERV_FEAT_TIME                2
1234 #define HYPERV_FEAT_CRASH               3
1235 #define HYPERV_FEAT_RESET               4
1236 #define HYPERV_FEAT_VPINDEX             5
1237 #define HYPERV_FEAT_RUNTIME             6
1238 #define HYPERV_FEAT_SYNIC               7
1239 #define HYPERV_FEAT_STIMER              8
1240 #define HYPERV_FEAT_FREQUENCIES         9
1241 #define HYPERV_FEAT_REENLIGHTENMENT     10
1242 #define HYPERV_FEAT_TLBFLUSH            11
1243 #define HYPERV_FEAT_EVMCS               12
1244 #define HYPERV_FEAT_IPI                 13
1245 #define HYPERV_FEAT_STIMER_DIRECT       14
1246 #define HYPERV_FEAT_AVIC                15
1247 #define HYPERV_FEAT_SYNDBG              16
1248 #define HYPERV_FEAT_MSR_BITMAP          17
1249 #define HYPERV_FEAT_XMM_INPUT           18
1250 #define HYPERV_FEAT_TLBFLUSH_EXT        19
1251 #define HYPERV_FEAT_TLBFLUSH_DIRECT     20
1252 
1253 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1254 #define HYPERV_SPINLOCK_NEVER_NOTIFY             0xFFFFFFFF
1255 #endif
1256 
1257 #define EXCP00_DIVZ	0
1258 #define EXCP01_DB	1
1259 #define EXCP02_NMI	2
1260 #define EXCP03_INT3	3
1261 #define EXCP04_INTO	4
1262 #define EXCP05_BOUND	5
1263 #define EXCP06_ILLOP	6
1264 #define EXCP07_PREX	7
1265 #define EXCP08_DBLE	8
1266 #define EXCP09_XERR	9
1267 #define EXCP0A_TSS	10
1268 #define EXCP0B_NOSEG	11
1269 #define EXCP0C_STACK	12
1270 #define EXCP0D_GPF	13
1271 #define EXCP0E_PAGE	14
1272 #define EXCP10_COPR	16
1273 #define EXCP11_ALGN	17
1274 #define EXCP12_MCHK	18
1275 
1276 #define EXCP_VMEXIT     0x100 /* only for system emulation */
1277 #define EXCP_SYSCALL    0x101 /* only for user emulation */
1278 #define EXCP_VSYSCALL   0x102 /* only for user emulation */
1279 
1280 /* i386-specific interrupt pending bits.  */
1281 #define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
1282 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
1283 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
1284 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
1285 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
1286 #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_1
1287 #define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_2
1288 
1289 /* Use a clearer name for this.  */
1290 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_RESET
1291 
1292 #define CC_OP_HAS_EFLAGS(op) ((op) >= CC_OP_EFLAGS && (op) <= CC_OP_ADCOX)
1293 
1294 /* Instead of computing the condition codes after each x86 instruction,
1295  * QEMU just stores one operand (called CC_SRC), the result
1296  * (called CC_DST) and the type of operation (called CC_OP). When the
1297  * condition codes are needed, the condition codes can be calculated
1298  * using this information. Condition codes are not generated if they
1299  * are only needed for conditional branches.
1300  */
1301 typedef enum {
1302     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1303     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
1304     CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest.  */
1305     CC_OP_ADOX, /* CC_SRC2 = O, CC_SRC = rest.  */
1306     CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */
1307     CC_OP_CLR, /* Z and P set, all other flags clear.  */
1308 
1309     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
1310     CC_OP_MULW,
1311     CC_OP_MULL,
1312     CC_OP_MULQ,
1313 
1314     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1315     CC_OP_ADDW,
1316     CC_OP_ADDL,
1317     CC_OP_ADDQ,
1318 
1319     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1320     CC_OP_ADCW,
1321     CC_OP_ADCL,
1322     CC_OP_ADCQ,
1323 
1324     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1325     CC_OP_SUBW,
1326     CC_OP_SUBL,
1327     CC_OP_SUBQ,
1328 
1329     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1330     CC_OP_SBBW,
1331     CC_OP_SBBL,
1332     CC_OP_SBBQ,
1333 
1334     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1335     CC_OP_LOGICW,
1336     CC_OP_LOGICL,
1337     CC_OP_LOGICQ,
1338 
1339     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1340     CC_OP_INCW,
1341     CC_OP_INCL,
1342     CC_OP_INCQ,
1343 
1344     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
1345     CC_OP_DECW,
1346     CC_OP_DECL,
1347     CC_OP_DECQ,
1348 
1349     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1350     CC_OP_SHLW,
1351     CC_OP_SHLL,
1352     CC_OP_SHLQ,
1353 
1354     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1355     CC_OP_SARW,
1356     CC_OP_SARL,
1357     CC_OP_SARQ,
1358 
1359     CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1360     CC_OP_BMILGW,
1361     CC_OP_BMILGL,
1362     CC_OP_BMILGQ,
1363 
1364     CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */
1365     CC_OP_BLSIW,
1366     CC_OP_BLSIL,
1367     CC_OP_BLSIQ,
1368 
1369     /*
1370      * Note that only CC_OP_POPCNT (i.e. the one with MO_TL size)
1371      * is used or implemented, because the translation needs
1372      * to zero-extend CC_DST anyway.
1373      */
1374     CC_OP_POPCNTB__, /* Z via CC_DST, all other flags clear.  */
1375     CC_OP_POPCNTW__,
1376     CC_OP_POPCNTL__,
1377     CC_OP_POPCNTQ__,
1378     CC_OP_POPCNT = sizeof(target_ulong) == 8 ? CC_OP_POPCNTQ__ : CC_OP_POPCNTL__,
1379 
1380     CC_OP_NB,
1381 } CCOp;
1382 QEMU_BUILD_BUG_ON(CC_OP_NB >= 128);
1383 
1384 typedef struct SegmentCache {
1385     uint32_t selector;
1386     target_ulong base;
1387     uint32_t limit;
1388     uint32_t flags;
1389 } SegmentCache;
1390 
1391 typedef union MMXReg {
1392     uint8_t  _b_MMXReg[64 / 8];
1393     uint16_t _w_MMXReg[64 / 16];
1394     uint32_t _l_MMXReg[64 / 32];
1395     uint64_t _q_MMXReg[64 / 64];
1396     float32  _s_MMXReg[64 / 32];
1397     float64  _d_MMXReg[64 / 64];
1398 } MMXReg;
1399 
1400 typedef union XMMReg {
1401     uint64_t _q_XMMReg[128 / 64];
1402 } XMMReg;
1403 
1404 typedef union YMMReg {
1405     uint64_t _q_YMMReg[256 / 64];
1406     XMMReg   _x_YMMReg[256 / 128];
1407 } YMMReg;
1408 
1409 typedef union ZMMReg {
1410     uint8_t  _b_ZMMReg[512 / 8];
1411     uint16_t _w_ZMMReg[512 / 16];
1412     uint32_t _l_ZMMReg[512 / 32];
1413     uint64_t _q_ZMMReg[512 / 64];
1414     float16  _h_ZMMReg[512 / 16];
1415     float32  _s_ZMMReg[512 / 32];
1416     float64  _d_ZMMReg[512 / 64];
1417     XMMReg   _x_ZMMReg[512 / 128];
1418     YMMReg   _y_ZMMReg[512 / 256];
1419 } ZMMReg;
1420 
1421 typedef struct BNDReg {
1422     uint64_t lb;
1423     uint64_t ub;
1424 } BNDReg;
1425 
1426 typedef struct BNDCSReg {
1427     uint64_t cfgu;
1428     uint64_t sts;
1429 } BNDCSReg;
1430 
1431 #define BNDCFG_ENABLE       1ULL
1432 #define BNDCFG_BNDPRESERVE  2ULL
1433 #define BNDCFG_BDIR_MASK    TARGET_PAGE_MASK
1434 
1435 #if HOST_BIG_ENDIAN
1436 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1437 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1438 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1439 #define ZMM_H(n) _h_ZMMReg[31 - (n)]
1440 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1441 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1442 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1443 #define ZMM_X(n) _x_ZMMReg[3 - (n)]
1444 #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1445 
1446 #define XMM_Q(n) _q_XMMReg[1 - (n)]
1447 
1448 #define YMM_Q(n) _q_YMMReg[3 - (n)]
1449 #define YMM_X(n) _x_YMMReg[1 - (n)]
1450 
1451 #define MMX_B(n) _b_MMXReg[7 - (n)]
1452 #define MMX_W(n) _w_MMXReg[3 - (n)]
1453 #define MMX_L(n) _l_MMXReg[1 - (n)]
1454 #define MMX_S(n) _s_MMXReg[1 - (n)]
1455 #else
1456 #define ZMM_B(n) _b_ZMMReg[n]
1457 #define ZMM_W(n) _w_ZMMReg[n]
1458 #define ZMM_L(n) _l_ZMMReg[n]
1459 #define ZMM_H(n) _h_ZMMReg[n]
1460 #define ZMM_S(n) _s_ZMMReg[n]
1461 #define ZMM_Q(n) _q_ZMMReg[n]
1462 #define ZMM_D(n) _d_ZMMReg[n]
1463 #define ZMM_X(n) _x_ZMMReg[n]
1464 #define ZMM_Y(n) _y_ZMMReg[n]
1465 
1466 #define XMM_Q(n) _q_XMMReg[n]
1467 
1468 #define YMM_Q(n) _q_YMMReg[n]
1469 #define YMM_X(n) _x_YMMReg[n]
1470 
1471 #define MMX_B(n) _b_MMXReg[n]
1472 #define MMX_W(n) _w_MMXReg[n]
1473 #define MMX_L(n) _l_MMXReg[n]
1474 #define MMX_S(n) _s_MMXReg[n]
1475 #endif
1476 #define MMX_Q(n) _q_MMXReg[n]
1477 
1478 typedef union {
1479     floatx80 d __attribute__((aligned(16)));
1480     MMXReg mmx;
1481 } FPReg;
1482 
1483 typedef struct {
1484     uint64_t base;
1485     uint64_t mask;
1486 } MTRRVar;
1487 
1488 #define CPU_NB_REGS64 16
1489 #define CPU_NB_REGS32 8
1490 
1491 #ifdef TARGET_X86_64
1492 #define CPU_NB_REGS CPU_NB_REGS64
1493 #else
1494 #define CPU_NB_REGS CPU_NB_REGS32
1495 #endif
1496 
1497 #define MAX_FIXED_COUNTERS 3
1498 #define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1499 
1500 #define TARGET_INSN_START_EXTRA_WORDS 1
1501 
1502 #define NB_OPMASK_REGS 8
1503 
1504 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1505  * that APIC ID hasn't been set yet
1506  */
1507 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1508 
1509 typedef struct X86LegacyXSaveArea {
1510     uint16_t fcw;
1511     uint16_t fsw;
1512     uint8_t ftw;
1513     uint8_t reserved;
1514     uint16_t fpop;
1515     union {
1516         struct {
1517             uint64_t fpip;
1518             uint64_t fpdp;
1519         };
1520         struct {
1521             uint32_t fip;
1522             uint32_t fcs;
1523             uint32_t foo;
1524             uint32_t fos;
1525         };
1526     };
1527     uint32_t mxcsr;
1528     uint32_t mxcsr_mask;
1529     FPReg fpregs[8];
1530     uint8_t xmm_regs[16][16];
1531     uint32_t hw_reserved[12];
1532     uint32_t sw_reserved[12];
1533 } X86LegacyXSaveArea;
1534 
1535 QEMU_BUILD_BUG_ON(sizeof(X86LegacyXSaveArea) != 512);
1536 
1537 typedef struct X86XSaveHeader {
1538     uint64_t xstate_bv;
1539     uint64_t xcomp_bv;
1540     uint64_t reserve0;
1541     uint8_t reserved[40];
1542 } X86XSaveHeader;
1543 
1544 /* Ext. save area 2: AVX State */
1545 typedef struct XSaveAVX {
1546     uint8_t ymmh[16][16];
1547 } XSaveAVX;
1548 
1549 /* Ext. save area 3: BNDREG */
1550 typedef struct XSaveBNDREG {
1551     BNDReg bnd_regs[4];
1552 } XSaveBNDREG;
1553 
1554 /* Ext. save area 4: BNDCSR */
1555 typedef union XSaveBNDCSR {
1556     BNDCSReg bndcsr;
1557     uint8_t data[64];
1558 } XSaveBNDCSR;
1559 
1560 /* Ext. save area 5: Opmask */
1561 typedef struct XSaveOpmask {
1562     uint64_t opmask_regs[NB_OPMASK_REGS];
1563 } XSaveOpmask;
1564 
1565 /* Ext. save area 6: ZMM_Hi256 */
1566 typedef struct XSaveZMM_Hi256 {
1567     uint8_t zmm_hi256[16][32];
1568 } XSaveZMM_Hi256;
1569 
1570 /* Ext. save area 7: Hi16_ZMM */
1571 typedef struct XSaveHi16_ZMM {
1572     uint8_t hi16_zmm[16][64];
1573 } XSaveHi16_ZMM;
1574 
1575 /* Ext. save area 9: PKRU state */
1576 typedef struct XSavePKRU {
1577     uint32_t pkru;
1578     uint32_t padding;
1579 } XSavePKRU;
1580 
1581 /* Ext. save area 17: AMX XTILECFG state */
1582 typedef struct XSaveXTILECFG {
1583     uint8_t xtilecfg[64];
1584 } XSaveXTILECFG;
1585 
1586 /* Ext. save area 18: AMX XTILEDATA state */
1587 typedef struct XSaveXTILEDATA {
1588     uint8_t xtiledata[8][1024];
1589 } XSaveXTILEDATA;
1590 
1591 typedef struct {
1592        uint64_t from;
1593        uint64_t to;
1594        uint64_t info;
1595 } LBREntry;
1596 
1597 #define ARCH_LBR_NR_ENTRIES            32
1598 
1599 /* Ext. save area 19: Supervisor mode Arch LBR state */
1600 typedef struct XSavesArchLBR {
1601     uint64_t lbr_ctl;
1602     uint64_t lbr_depth;
1603     uint64_t ler_from;
1604     uint64_t ler_to;
1605     uint64_t ler_info;
1606     LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1607 } XSavesArchLBR;
1608 
1609 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1610 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1611 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1612 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1613 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1614 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1615 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1616 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1617 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1618 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1619 
1620 typedef struct ExtSaveArea {
1621     uint32_t feature, bits;
1622     uint32_t offset, size;
1623     uint32_t ecx;
1624 } ExtSaveArea;
1625 
1626 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1627 
1628 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
1629 
1630 typedef enum TPRAccess {
1631     TPR_ACCESS_READ,
1632     TPR_ACCESS_WRITE,
1633 } TPRAccess;
1634 
1635 /* Cache information data structures: */
1636 
1637 enum CacheType {
1638     DATA_CACHE,
1639     INSTRUCTION_CACHE,
1640     UNIFIED_CACHE
1641 };
1642 
1643 typedef struct CPUCacheInfo {
1644     enum CacheType type;
1645     uint8_t level;
1646     /* Size in bytes */
1647     uint32_t size;
1648     /* Line size, in bytes */
1649     uint16_t line_size;
1650     /*
1651      * Associativity.
1652      * Note: representation of fully-associative caches is not implemented
1653      */
1654     uint8_t associativity;
1655     /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1656     uint8_t partitions;
1657     /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1658     uint32_t sets;
1659     /*
1660      * Lines per tag.
1661      * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1662      * (Is this synonym to @partitions?)
1663      */
1664     uint8_t lines_per_tag;
1665 
1666     /* Self-initializing cache */
1667     bool self_init;
1668     /*
1669      * WBINVD/INVD is not guaranteed to act upon lower level caches of
1670      * non-originating threads sharing this cache.
1671      * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1672      */
1673     bool no_invd_sharing;
1674     /*
1675      * Cache is inclusive of lower cache levels.
1676      * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1677      */
1678     bool inclusive;
1679     /*
1680      * A complex function is used to index the cache, potentially using all
1681      * address bits.  CPUID[4].EDX[bit 2].
1682      */
1683     bool complex_indexing;
1684 
1685     /*
1686      * Cache Topology. The level that cache is shared in.
1687      * Used to encode CPUID[4].EAX[bits 25:14] or
1688      * CPUID[0x8000001D].EAX[bits 25:14].
1689      */
1690     enum CPUTopoLevel share_level;
1691 } CPUCacheInfo;
1692 
1693 
1694 typedef struct CPUCaches {
1695         CPUCacheInfo *l1d_cache;
1696         CPUCacheInfo *l1i_cache;
1697         CPUCacheInfo *l2_cache;
1698         CPUCacheInfo *l3_cache;
1699 } CPUCaches;
1700 
1701 typedef struct HVFX86LazyFlags {
1702     target_ulong result;
1703     target_ulong auxbits;
1704 } HVFX86LazyFlags;
1705 
1706 typedef struct CPUArchState {
1707     /* standard registers */
1708     target_ulong regs[CPU_NB_REGS];
1709     target_ulong eip;
1710     target_ulong eflags; /* eflags register. During CPU emulation, CC
1711                         flags and DF are set to zero because they are
1712                         stored elsewhere */
1713 
1714     /* emulator internal eflags handling */
1715     target_ulong cc_dst;
1716     target_ulong cc_src;
1717     target_ulong cc_src2;
1718     uint32_t cc_op;
1719     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1720     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1721                         are known at translation time. */
1722     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1723 
1724     /* segments */
1725     SegmentCache segs[6]; /* selector values */
1726     SegmentCache ldt;
1727     SegmentCache tr;
1728     SegmentCache gdt; /* only base and limit are used */
1729     SegmentCache idt; /* only base and limit are used */
1730 
1731     target_ulong cr[5]; /* NOTE: cr1 is unused */
1732 
1733     bool pdptrs_valid;
1734     uint64_t pdptrs[4];
1735     int32_t a20_mask;
1736 
1737     BNDReg bnd_regs[4];
1738     BNDCSReg bndcs_regs;
1739     uint64_t msr_bndcfgs;
1740     uint64_t efer;
1741 
1742     /* Beginning of state preserved by INIT (dummy marker).  */
1743     struct {} start_init_save;
1744 
1745     /* FPU state */
1746     unsigned int fpstt; /* top of stack index */
1747     uint16_t fpus;
1748     uint16_t fpuc;
1749     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
1750     FPReg fpregs[8];
1751     /* KVM-only so far */
1752     uint16_t fpop;
1753     uint16_t fpcs;
1754     uint16_t fpds;
1755     uint64_t fpip;
1756     uint64_t fpdp;
1757 
1758     /* emulator internal variables */
1759     float_status fp_status;
1760     floatx80 ft0;
1761 
1762     float_status mmx_status; /* for 3DNow! float ops */
1763     float_status sse_status;
1764     uint32_t mxcsr;
1765     ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
1766     ZMMReg xmm_t0 QEMU_ALIGNED(16);
1767     MMXReg mmx_t0;
1768 
1769     uint64_t opmask_regs[NB_OPMASK_REGS];
1770 #ifdef TARGET_X86_64
1771     uint8_t xtilecfg[64];
1772     uint8_t xtiledata[8192];
1773 #endif
1774 
1775     /* sysenter registers */
1776     uint32_t sysenter_cs;
1777     target_ulong sysenter_esp;
1778     target_ulong sysenter_eip;
1779     uint64_t star;
1780 
1781     uint64_t vm_hsave;
1782 
1783 #ifdef TARGET_X86_64
1784     target_ulong lstar;
1785     target_ulong cstar;
1786     target_ulong fmask;
1787     target_ulong kernelgsbase;
1788 
1789     /* FRED MSRs */
1790     uint64_t fred_rsp0;
1791     uint64_t fred_rsp1;
1792     uint64_t fred_rsp2;
1793     uint64_t fred_rsp3;
1794     uint64_t fred_stklvls;
1795     uint64_t fred_ssp1;
1796     uint64_t fred_ssp2;
1797     uint64_t fred_ssp3;
1798     uint64_t fred_config;
1799 #endif
1800 
1801     uint64_t tsc_adjust;
1802     uint64_t tsc_deadline;
1803     uint64_t tsc_aux;
1804 
1805     uint64_t xcr0;
1806 
1807     uint64_t mcg_status;
1808     uint64_t msr_ia32_misc_enable;
1809     uint64_t msr_ia32_feature_control;
1810     uint64_t msr_ia32_sgxlepubkeyhash[4];
1811 
1812     uint64_t msr_fixed_ctr_ctrl;
1813     uint64_t msr_global_ctrl;
1814     uint64_t msr_global_status;
1815     uint64_t msr_global_ovf_ctrl;
1816     uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1817     uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1818     uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1819 
1820     uint64_t pat;
1821     uint32_t smbase;
1822     uint64_t msr_smi_count;
1823 
1824     uint32_t pkru;
1825     uint32_t pkrs;
1826     uint32_t tsx_ctrl;
1827 
1828     uint64_t spec_ctrl;
1829     uint64_t amd_tsc_scale_msr;
1830     uint64_t virt_ssbd;
1831 
1832     /* End of state preserved by INIT (dummy marker).  */
1833     struct {} end_init_save;
1834 
1835     uint64_t system_time_msr;
1836     uint64_t wall_clock_msr;
1837     uint64_t steal_time_msr;
1838     uint64_t async_pf_en_msr;
1839     uint64_t async_pf_int_msr;
1840     uint64_t pv_eoi_en_msr;
1841     uint64_t poll_control_msr;
1842 
1843     /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1844     uint64_t msr_hv_hypercall;
1845     uint64_t msr_hv_guest_os_id;
1846     uint64_t msr_hv_tsc;
1847     uint64_t msr_hv_syndbg_control;
1848     uint64_t msr_hv_syndbg_status;
1849     uint64_t msr_hv_syndbg_send_page;
1850     uint64_t msr_hv_syndbg_recv_page;
1851     uint64_t msr_hv_syndbg_pending_page;
1852     uint64_t msr_hv_syndbg_options;
1853 
1854     /* Per-VCPU HV MSRs */
1855     uint64_t msr_hv_vapic;
1856     uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1857     uint64_t msr_hv_runtime;
1858     uint64_t msr_hv_synic_control;
1859     uint64_t msr_hv_synic_evt_page;
1860     uint64_t msr_hv_synic_msg_page;
1861     uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1862     uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1863     uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1864     uint64_t msr_hv_reenlightenment_control;
1865     uint64_t msr_hv_tsc_emulation_control;
1866     uint64_t msr_hv_tsc_emulation_status;
1867 
1868     uint64_t msr_rtit_ctrl;
1869     uint64_t msr_rtit_status;
1870     uint64_t msr_rtit_output_base;
1871     uint64_t msr_rtit_output_mask;
1872     uint64_t msr_rtit_cr3_match;
1873     uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1874 
1875     /* Per-VCPU XFD MSRs */
1876     uint64_t msr_xfd;
1877     uint64_t msr_xfd_err;
1878 
1879     /* Per-VCPU Arch LBR MSRs */
1880     uint64_t msr_lbr_ctl;
1881     uint64_t msr_lbr_depth;
1882     LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1883 
1884     /* AMD MSRC001_0015 Hardware Configuration */
1885     uint64_t msr_hwcr;
1886 
1887     /* exception/interrupt handling */
1888     int error_code;
1889     int exception_is_int;
1890     target_ulong exception_next_eip;
1891     target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1892     union {
1893         struct CPUBreakpoint *cpu_breakpoint[4];
1894         struct CPUWatchpoint *cpu_watchpoint[4];
1895     }; /* break/watchpoints for dr[0..3] */
1896     int old_exception;  /* exception in flight */
1897 
1898     uint64_t vm_vmcb;
1899     uint64_t tsc_offset;
1900     uint64_t intercept;
1901     uint16_t intercept_cr_read;
1902     uint16_t intercept_cr_write;
1903     uint16_t intercept_dr_read;
1904     uint16_t intercept_dr_write;
1905     uint32_t intercept_exceptions;
1906     uint64_t nested_cr3;
1907     uint32_t nested_pg_mode;
1908     uint8_t v_tpr;
1909     uint32_t int_ctl;
1910 
1911     /* KVM states, automatically cleared on reset */
1912     uint8_t nmi_injected;
1913     uint8_t nmi_pending;
1914 
1915     uintptr_t retaddr;
1916 
1917     /* RAPL MSR */
1918     uint64_t msr_rapl_power_unit;
1919     uint64_t msr_pkg_energy_status;
1920 
1921     /* Fields up to this point are cleared by a CPU reset */
1922     struct {} end_reset_fields;
1923 
1924     /* Fields after this point are preserved across CPU reset. */
1925 
1926     /* processor features (e.g. for CPUID insn) */
1927     /* Minimum cpuid leaf 7 value */
1928     uint32_t cpuid_level_func7;
1929     /* Actual cpuid leaf 7 value */
1930     uint32_t cpuid_min_level_func7;
1931     /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1932     uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1933     /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1934     uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1935     /* Actual level/xlevel/xlevel2 value: */
1936     uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1937     uint32_t cpuid_vendor1;
1938     uint32_t cpuid_vendor2;
1939     uint32_t cpuid_vendor3;
1940     uint32_t cpuid_version;
1941     FeatureWordArray features;
1942     /* Features that were explicitly enabled/disabled */
1943     FeatureWordArray user_features;
1944     uint32_t cpuid_model[12];
1945     /* Cache information for CPUID.  When legacy-cache=on, the cache data
1946      * on each CPUID leaf will be different, because we keep compatibility
1947      * with old QEMU versions.
1948      */
1949     CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1950 
1951     /* MTRRs */
1952     uint64_t mtrr_fixed[11];
1953     uint64_t mtrr_deftype;
1954     MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1955 
1956     /* For KVM */
1957     uint32_t mp_state;
1958     int32_t exception_nr;
1959     int32_t interrupt_injected;
1960     uint8_t soft_interrupt;
1961     uint8_t exception_pending;
1962     uint8_t exception_injected;
1963     uint8_t has_error_code;
1964     uint8_t exception_has_payload;
1965     uint64_t exception_payload;
1966     uint8_t triple_fault_pending;
1967     uint32_t ins_len;
1968     uint32_t sipi_vector;
1969     bool tsc_valid;
1970     int64_t tsc_khz;
1971     int64_t user_tsc_khz; /* for sanity check only */
1972     uint64_t apic_bus_freq;
1973     uint64_t tsc;
1974 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1975     void *xsave_buf;
1976     uint32_t xsave_buf_len;
1977 #endif
1978 #if defined(CONFIG_KVM)
1979     struct kvm_nested_state *nested_state;
1980     MemoryRegion *xen_vcpu_info_mr;
1981     void *xen_vcpu_info_hva;
1982     uint64_t xen_vcpu_info_gpa;
1983     uint64_t xen_vcpu_info_default_gpa;
1984     uint64_t xen_vcpu_time_info_gpa;
1985     uint64_t xen_vcpu_runstate_gpa;
1986     uint8_t xen_vcpu_callback_vector;
1987     bool xen_callback_asserted;
1988     uint16_t xen_virq[XEN_NR_VIRQS];
1989     uint64_t xen_singleshot_timer_ns;
1990     QEMUTimer *xen_singleshot_timer;
1991     uint64_t xen_periodic_timer_period;
1992     QEMUTimer *xen_periodic_timer;
1993     QemuMutex xen_timers_lock;
1994 #endif
1995 #if defined(CONFIG_HVF)
1996     HVFX86LazyFlags hvf_lflags;
1997     void *hvf_mmio_buf;
1998 #endif
1999 
2000     uint64_t mcg_cap;
2001     uint64_t mcg_ctl;
2002     uint64_t mcg_ext_ctl;
2003     uint64_t mce_banks[MCE_BANKS_DEF*4];
2004     uint64_t xstate_bv;
2005 
2006     /* vmstate */
2007     uint16_t fpus_vmstate;
2008     uint16_t fptag_vmstate;
2009     uint16_t fpregs_format_vmstate;
2010 
2011     uint64_t xss;
2012     uint32_t umwait;
2013 
2014     TPRAccess tpr_access_type;
2015 
2016     /* Number of dies within this CPU package. */
2017     unsigned nr_dies;
2018 
2019     /* Number of modules within one die. */
2020     unsigned nr_modules;
2021 
2022     /* Bitmap of available CPU topology levels for this CPU. */
2023     DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX);
2024 } CPUX86State;
2025 
2026 struct kvm_msrs;
2027 
2028 /**
2029  * X86CPU:
2030  * @env: #CPUX86State
2031  * @migratable: If set, only migratable flags will be accepted when "enforce"
2032  * mode is used, and only migratable flags will be included in the "host"
2033  * CPU model.
2034  *
2035  * An x86 CPU.
2036  */
2037 struct ArchCPU {
2038     CPUState parent_obj;
2039 
2040     CPUX86State env;
2041     VMChangeStateEntry *vmsentry;
2042 
2043     uint64_t ucode_rev;
2044 
2045     uint32_t hyperv_spinlock_attempts;
2046     char *hyperv_vendor;
2047     bool hyperv_synic_kvm_only;
2048     uint64_t hyperv_features;
2049     bool hyperv_passthrough;
2050     OnOffAuto hyperv_no_nonarch_cs;
2051     uint32_t hyperv_vendor_id[3];
2052     uint32_t hyperv_interface_id[4];
2053     uint32_t hyperv_limits[3];
2054     bool hyperv_enforce_cpuid;
2055     uint32_t hyperv_ver_id_build;
2056     uint16_t hyperv_ver_id_major;
2057     uint16_t hyperv_ver_id_minor;
2058     uint32_t hyperv_ver_id_sp;
2059     uint8_t hyperv_ver_id_sb;
2060     uint32_t hyperv_ver_id_sn;
2061 
2062     bool check_cpuid;
2063     bool enforce_cpuid;
2064     /*
2065      * Force features to be enabled even if the host doesn't support them.
2066      * This is dangerous and should be done only for testing CPUID
2067      * compatibility.
2068      */
2069     bool force_features;
2070     bool expose_kvm;
2071     bool expose_tcg;
2072     bool migratable;
2073     bool migrate_smi_count;
2074     bool max_features; /* Enable all supported features automatically */
2075     uint32_t apic_id;
2076 
2077     /* Enables publishing of TSC increment and Local APIC bus frequencies to
2078      * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
2079     bool vmware_cpuid_freq;
2080 
2081     /* if true the CPUID code directly forward host cache leaves to the guest */
2082     bool cache_info_passthrough;
2083 
2084     /* if true the CPUID code directly forwards
2085      * host monitor/mwait leaves to the guest */
2086     struct {
2087         uint32_t eax;
2088         uint32_t ebx;
2089         uint32_t ecx;
2090         uint32_t edx;
2091     } mwait;
2092 
2093     /* Features that were filtered out because of missing host capabilities */
2094     FeatureWordArray filtered_features;
2095 
2096     /* Enable PMU CPUID bits. This can't be enabled by default yet because
2097      * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
2098      * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
2099      * capabilities) directly to the guest.
2100      */
2101     bool enable_pmu;
2102 
2103     /*
2104      * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
2105      * This can't be initialized with a default because it doesn't have
2106      * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
2107      * returned by kvm_arch_get_supported_msr_feature()(which depends on both
2108      * host CPU and kernel capabilities) to the guest.
2109      */
2110     uint64_t lbr_fmt;
2111 
2112     /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
2113      * disabled by default to avoid breaking migration between QEMU with
2114      * different LMCE configurations.
2115      */
2116     bool enable_lmce;
2117 
2118     /* Compatibility bits for old machine types.
2119      * If true present virtual l3 cache for VM, the vcpus in the same virtual
2120      * socket share an virtual l3 cache.
2121      */
2122     bool enable_l3_cache;
2123 
2124     /* Compatibility bits for old machine types.
2125      * If true present L1 cache as per-thread, not per-core.
2126      */
2127     bool l1_cache_per_core;
2128 
2129     /* Compatibility bits for old machine types.
2130      * If true present the old cache topology information
2131      */
2132     bool legacy_cache;
2133 
2134     /* Compatibility bits for old machine types.
2135      * If true decode the CPUID Function 0x8000001E_ECX to support multiple
2136      * nodes per processor
2137      */
2138     bool legacy_multi_node;
2139 
2140     /* Compatibility bits for old machine types: */
2141     bool enable_cpuid_0xb;
2142 
2143     /* Enable auto level-increase for all CPUID leaves */
2144     bool full_cpuid_auto_level;
2145 
2146     /* Only advertise CPUID leaves defined by the vendor */
2147     bool vendor_cpuid_only;
2148 
2149     /* Only advertise TOPOEXT features that AMD defines */
2150     bool amd_topoext_features_only;
2151 
2152     /* Enable auto level-increase for Intel Processor Trace leave */
2153     bool intel_pt_auto_level;
2154 
2155     /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
2156     bool fill_mtrr_mask;
2157 
2158     /* if true override the phys_bits value with a value read from the host */
2159     bool host_phys_bits;
2160 
2161     /* if set, limit maximum value for phys_bits when host_phys_bits is true */
2162     uint8_t host_phys_bits_limit;
2163 
2164     /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
2165     bool kvm_pv_enforce_cpuid;
2166 
2167     /* Number of physical address bits supported */
2168     uint32_t phys_bits;
2169 
2170     /*
2171      * Number of guest physical address bits available. Usually this is
2172      * identical to host physical address bits. With NPT or EPT 4-level
2173      * paging, guest physical address space might be restricted to 48 bits
2174      * even if the host cpu supports more physical address bits.
2175      */
2176     uint32_t guest_phys_bits;
2177 
2178     /* in order to simplify APIC support, we leave this pointer to the
2179        user */
2180     struct DeviceState *apic_state;
2181     struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
2182     Notifier machine_done;
2183 
2184     struct kvm_msrs *kvm_msr_buf;
2185 
2186     int32_t node_id; /* NUMA node this CPU belongs to */
2187     int32_t socket_id;
2188     int32_t die_id;
2189     int32_t module_id;
2190     int32_t core_id;
2191     int32_t thread_id;
2192 
2193     int32_t hv_max_vps;
2194 
2195     bool xen_vapic;
2196 };
2197 
2198 typedef struct X86CPUModel X86CPUModel;
2199 
2200 /**
2201  * X86CPUClass:
2202  * @cpu_def: CPU model definition
2203  * @host_cpuid_required: Whether CPU model requires cpuid from host.
2204  * @ordering: Ordering on the "-cpu help" CPU model list.
2205  * @migration_safe: See CpuDefinitionInfo::migration_safe
2206  * @static_model: See CpuDefinitionInfo::static
2207  * @parent_realize: The parent class' realize handler.
2208  * @parent_phases: The parent class' reset phase handlers.
2209  *
2210  * An x86 CPU model or family.
2211  */
2212 struct X86CPUClass {
2213     CPUClass parent_class;
2214 
2215     /*
2216      * CPU definition, automatically loaded by instance_init if not NULL.
2217      * Should be eventually replaced by subclass-specific property defaults.
2218      */
2219     X86CPUModel *model;
2220 
2221     bool host_cpuid_required;
2222     int ordering;
2223     bool migration_safe;
2224     bool static_model;
2225 
2226     /*
2227      * Optional description of CPU model.
2228      * If unavailable, cpu_def->model_id is used.
2229      */
2230     const char *model_description;
2231 
2232     DeviceRealize parent_realize;
2233     DeviceUnrealize parent_unrealize;
2234     ResettablePhases parent_phases;
2235 };
2236 
2237 #ifndef CONFIG_USER_ONLY
2238 extern const VMStateDescription vmstate_x86_cpu;
2239 #endif
2240 
2241 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
2242 
2243 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
2244                              int cpuid, DumpState *s);
2245 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
2246                              int cpuid, DumpState *s);
2247 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2248                                  DumpState *s);
2249 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2250                                  DumpState *s);
2251 
2252 bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
2253                                 Error **errp);
2254 
2255 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
2256 
2257 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
2258 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
2259 void x86_cpu_gdb_init(CPUState *cs);
2260 
2261 void x86_cpu_list(void);
2262 int cpu_x86_support_mca_broadcast(CPUX86State *env);
2263 
2264 #ifndef CONFIG_USER_ONLY
2265 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
2266                                          MemTxAttrs *attrs);
2267 int cpu_get_pic_interrupt(CPUX86State *s);
2268 
2269 /* MS-DOS compatibility mode FPU exception support */
2270 void x86_register_ferr_irq(qemu_irq irq);
2271 void fpu_check_raise_ferr_irq(CPUX86State *s);
2272 void cpu_set_ignne(void);
2273 void cpu_clear_ignne(void);
2274 #endif
2275 
2276 /* mpx_helper.c */
2277 void cpu_sync_bndcs_hflags(CPUX86State *env);
2278 
2279 /* this function must always be used to load data in the segment
2280    cache: it synchronizes the hflags with the segment cache values */
2281 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
2282                                           X86Seg seg_reg, unsigned int selector,
2283                                           target_ulong base,
2284                                           unsigned int limit,
2285                                           unsigned int flags)
2286 {
2287     SegmentCache *sc;
2288     unsigned int new_hflags;
2289 
2290     sc = &env->segs[seg_reg];
2291     sc->selector = selector;
2292     sc->base = base;
2293     sc->limit = limit;
2294     sc->flags = flags;
2295 
2296     /* update the hidden flags */
2297     {
2298         if (seg_reg == R_CS) {
2299 #ifdef TARGET_X86_64
2300             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
2301                 /* long mode */
2302                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2303                 env->hflags &= ~(HF_ADDSEG_MASK);
2304             } else
2305 #endif
2306             {
2307                 /* legacy / compatibility case */
2308                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
2309                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
2310                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
2311                     new_hflags;
2312             }
2313         }
2314         if (seg_reg == R_SS) {
2315             int cpl = (flags >> DESC_DPL_SHIFT) & 3;
2316 #if HF_CPL_MASK != 3
2317 #error HF_CPL_MASK is hardcoded
2318 #endif
2319             env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
2320             /* Possibly switch between BNDCFGS and BNDCFGU */
2321             cpu_sync_bndcs_hflags(env);
2322         }
2323         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
2324             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
2325         if (env->hflags & HF_CS64_MASK) {
2326             /* zero base assumed for DS, ES and SS in long mode */
2327         } else if (!(env->cr[0] & CR0_PE_MASK) ||
2328                    (env->eflags & VM_MASK) ||
2329                    !(env->hflags & HF_CS32_MASK)) {
2330             /* XXX: try to avoid this test. The problem comes from the
2331                fact that is real mode or vm86 mode we only modify the
2332                'base' and 'selector' fields of the segment cache to go
2333                faster. A solution may be to force addseg to one in
2334                translate-i386.c. */
2335             new_hflags |= HF_ADDSEG_MASK;
2336         } else {
2337             new_hflags |= ((env->segs[R_DS].base |
2338                             env->segs[R_ES].base |
2339                             env->segs[R_SS].base) != 0) <<
2340                 HF_ADDSEG_SHIFT;
2341         }
2342         env->hflags = (env->hflags &
2343                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
2344     }
2345 }
2346 
2347 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
2348                                                uint8_t sipi_vector)
2349 {
2350     CPUState *cs = CPU(cpu);
2351     CPUX86State *env = &cpu->env;
2352 
2353     env->eip = 0;
2354     cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
2355                            sipi_vector << 12,
2356                            env->segs[R_CS].limit,
2357                            env->segs[R_CS].flags);
2358     cs->halted = 0;
2359 }
2360 
2361 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
2362                             target_ulong *base, unsigned int *limit,
2363                             unsigned int *flags);
2364 
2365 /* op_helper.c */
2366 /* used for debug or cpu save/restore */
2367 
2368 /* cpu-exec.c */
2369 /*
2370  * The following helpers are only usable in user mode simulation.
2371  * The host pointers should come from lock_user().
2372  */
2373 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
2374 void cpu_x86_fsave(CPUX86State *s, void *host, size_t len);
2375 void cpu_x86_frstor(CPUX86State *s, void *host, size_t len);
2376 void cpu_x86_fxsave(CPUX86State *s, void *host, size_t len);
2377 void cpu_x86_fxrstor(CPUX86State *s, void *host, size_t len);
2378 void cpu_x86_xsave(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2379 bool cpu_x86_xrstor(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2380 
2381 /* cpu.c */
2382 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
2383                               uint32_t vendor2, uint32_t vendor3);
2384 typedef struct PropValue {
2385     const char *prop, *value;
2386 } PropValue;
2387 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
2388 
2389 void x86_cpu_after_reset(X86CPU *cpu);
2390 
2391 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env);
2392 
2393 /* cpu.c other functions (cpuid) */
2394 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2395                    uint32_t *eax, uint32_t *ebx,
2396                    uint32_t *ecx, uint32_t *edx);
2397 void cpu_clear_apic_feature(CPUX86State *env);
2398 void cpu_set_apic_feature(CPUX86State *env);
2399 void host_cpuid(uint32_t function, uint32_t count,
2400                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
2401 bool cpu_has_x2apic_feature(CPUX86State *env);
2402 
2403 /* helper.c */
2404 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
2405 void cpu_sync_avx_hflag(CPUX86State *env);
2406 
2407 #ifndef CONFIG_USER_ONLY
2408 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2409 {
2410     return !!attrs.secure;
2411 }
2412 
2413 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
2414 {
2415     return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
2416 }
2417 
2418 /*
2419  * load efer and update the corresponding hflags. XXX: do consistency
2420  * checks with cpuid bits?
2421  */
2422 void cpu_load_efer(CPUX86State *env, uint64_t val);
2423 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
2424 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
2425 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
2426 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
2427 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
2428 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
2429 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
2430 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
2431 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
2432 #endif
2433 
2434 /* will be suppressed */
2435 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
2436 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
2437 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
2438 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
2439 
2440 /* hw/pc.c */
2441 uint64_t cpu_get_tsc(CPUX86State *env);
2442 
2443 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2444 
2445 #ifdef TARGET_X86_64
2446 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2447 #else
2448 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2449 #endif
2450 
2451 #define cpu_list x86_cpu_list
2452 
2453 /* MMU modes definitions */
2454 #define MMU_KSMAP64_IDX    0
2455 #define MMU_KSMAP32_IDX    1
2456 #define MMU_USER64_IDX     2
2457 #define MMU_USER32_IDX     3
2458 #define MMU_KNOSMAP64_IDX  4
2459 #define MMU_KNOSMAP32_IDX  5
2460 #define MMU_PHYS_IDX       6
2461 #define MMU_NESTED_IDX     7
2462 
2463 #ifdef CONFIG_USER_ONLY
2464 #ifdef TARGET_X86_64
2465 #define MMU_USER_IDX MMU_USER64_IDX
2466 #else
2467 #define MMU_USER_IDX MMU_USER32_IDX
2468 #endif
2469 #endif
2470 
2471 static inline bool is_mmu_index_smap(int mmu_index)
2472 {
2473     return (mmu_index & ~1) == MMU_KSMAP64_IDX;
2474 }
2475 
2476 static inline bool is_mmu_index_user(int mmu_index)
2477 {
2478     return (mmu_index & ~1) == MMU_USER64_IDX;
2479 }
2480 
2481 static inline bool is_mmu_index_32(int mmu_index)
2482 {
2483     assert(mmu_index < MMU_PHYS_IDX);
2484     return mmu_index & 1;
2485 }
2486 
2487 int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
2488 int cpu_mmu_index_kernel(CPUX86State *env);
2489 
2490 #define CC_DST  (env->cc_dst)
2491 #define CC_SRC  (env->cc_src)
2492 #define CC_SRC2 (env->cc_src2)
2493 #define CC_OP   (env->cc_op)
2494 
2495 #include "exec/cpu-all.h"
2496 #include "svm.h"
2497 
2498 #if !defined(CONFIG_USER_ONLY)
2499 #include "hw/i386/apic.h"
2500 #endif
2501 
2502 static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
2503                                         uint64_t *cs_base, uint32_t *flags)
2504 {
2505     *flags = env->hflags |
2506         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2507     if (env->hflags & HF_CS64_MASK) {
2508         *cs_base = 0;
2509         *pc = env->eip;
2510     } else {
2511         *cs_base = env->segs[R_CS].base;
2512         *pc = (uint32_t)(*cs_base + env->eip);
2513     }
2514 }
2515 
2516 void do_cpu_init(X86CPU *cpu);
2517 
2518 #define MCE_INJECT_BROADCAST    1
2519 #define MCE_INJECT_UNCOND_AO    2
2520 
2521 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2522                         uint64_t status, uint64_t mcg_status, uint64_t addr,
2523                         uint64_t misc, int flags);
2524 
2525 uint32_t cpu_cc_compute_all(CPUX86State *env1);
2526 
2527 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2528 {
2529     uint32_t eflags = env->eflags;
2530     if (tcg_enabled()) {
2531         eflags |= cpu_cc_compute_all(env) | (env->df & DF_MASK);
2532     }
2533     return eflags;
2534 }
2535 
2536 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2537 {
2538     return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2539 }
2540 
2541 static inline int32_t x86_get_a20_mask(CPUX86State *env)
2542 {
2543     if (env->hflags & HF_SMM_MASK) {
2544         return -1;
2545     } else {
2546         return env->a20_mask;
2547     }
2548 }
2549 
2550 static inline bool cpu_has_vmx(CPUX86State *env)
2551 {
2552     return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2553 }
2554 
2555 static inline bool cpu_has_svm(CPUX86State *env)
2556 {
2557     return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2558 }
2559 
2560 /*
2561  * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2562  * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2563  * VMX operation. This is because CR4.VMXE is one of the bits set
2564  * in MSR_IA32_VMX_CR4_FIXED1.
2565  *
2566  * There is one exception to above statement when vCPU enters SMM mode.
2567  * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2568  * may also reset CR4.VMXE during execution in SMM mode.
2569  * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2570  * and CR4.VMXE is restored to it's original value of being set.
2571  *
2572  * Therefore, when vCPU is not in SMM mode, we can infer whether
2573  * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2574  * know for certain.
2575  */
2576 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2577 {
2578     return cpu_has_vmx(env) &&
2579            ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2580 }
2581 
2582 /* excp_helper.c */
2583 int get_pg_mode(CPUX86State *env);
2584 
2585 /* fpu_helper.c */
2586 void update_fp_status(CPUX86State *env);
2587 void update_mxcsr_status(CPUX86State *env);
2588 void update_mxcsr_from_sse_status(CPUX86State *env);
2589 
2590 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2591 {
2592     env->mxcsr = mxcsr;
2593     if (tcg_enabled()) {
2594         update_mxcsr_status(env);
2595     }
2596 }
2597 
2598 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2599 {
2600      env->fpuc = fpuc;
2601      if (tcg_enabled()) {
2602         update_fp_status(env);
2603      }
2604 }
2605 
2606 /* svm_helper.c */
2607 #ifdef CONFIG_USER_ONLY
2608 static inline void
2609 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2610                               uint64_t param, uintptr_t retaddr)
2611 { /* no-op */ }
2612 static inline bool
2613 cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
2614 { return false; }
2615 #else
2616 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2617                                    uint64_t param, uintptr_t retaddr);
2618 bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type);
2619 #endif
2620 
2621 /* apic.c */
2622 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2623 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2624                                    TPRAccess access);
2625 
2626 /* Special values for X86CPUVersion: */
2627 
2628 /* Resolve to latest CPU version */
2629 #define CPU_VERSION_LATEST -1
2630 
2631 /*
2632  * Resolve to version defined by current machine type.
2633  * See x86_cpu_set_default_version()
2634  */
2635 #define CPU_VERSION_AUTO   -2
2636 
2637 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2638 #define CPU_VERSION_LEGACY  0
2639 
2640 typedef int X86CPUVersion;
2641 
2642 /*
2643  * Set default CPU model version for CPU models having
2644  * version == CPU_VERSION_AUTO.
2645  */
2646 void x86_cpu_set_default_version(X86CPUVersion version);
2647 
2648 #ifndef CONFIG_USER_ONLY
2649 
2650 void do_cpu_sipi(X86CPU *cpu);
2651 
2652 #define APIC_DEFAULT_ADDRESS 0xfee00000
2653 #define APIC_SPACE_SIZE      0x100000
2654 
2655 /* cpu-dump.c */
2656 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2657 
2658 #endif
2659 
2660 /* cpu.c */
2661 bool cpu_is_bsp(X86CPU *cpu);
2662 
2663 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen);
2664 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen);
2665 uint32_t xsave_area_size(uint64_t mask, bool compacted);
2666 void x86_update_hflags(CPUX86State* env);
2667 
2668 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2669 {
2670     return !!(cpu->hyperv_features & BIT(feat));
2671 }
2672 
2673 static inline uint64_t cr4_reserved_bits(CPUX86State *env)
2674 {
2675     uint64_t reserved_bits = CR4_RESERVED_MASK;
2676     if (!env->features[FEAT_XSAVE]) {
2677         reserved_bits |= CR4_OSXSAVE_MASK;
2678     }
2679     if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) {
2680         reserved_bits |= CR4_SMEP_MASK;
2681     }
2682     if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
2683         reserved_bits |= CR4_SMAP_MASK;
2684     }
2685     if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) {
2686         reserved_bits |= CR4_FSGSBASE_MASK;
2687     }
2688     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
2689         reserved_bits |= CR4_PKE_MASK;
2690     }
2691     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) {
2692         reserved_bits |= CR4_LA57_MASK;
2693     }
2694     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
2695         reserved_bits |= CR4_UMIP_MASK;
2696     }
2697     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
2698         reserved_bits |= CR4_PKS_MASK;
2699     }
2700     if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
2701         reserved_bits |= CR4_LAM_SUP_MASK;
2702     }
2703     if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) {
2704         reserved_bits |= CR4_FRED_MASK;
2705     }
2706     return reserved_bits;
2707 }
2708 
2709 static inline bool ctl_has_irq(CPUX86State *env)
2710 {
2711     uint32_t int_prio;
2712     uint32_t tpr;
2713 
2714     int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
2715     tpr = env->int_ctl & V_TPR_MASK;
2716 
2717     if (env->int_ctl & V_IGN_TPR_MASK) {
2718         return (env->int_ctl & V_IRQ_MASK);
2719     }
2720 
2721     return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
2722 }
2723 
2724 #if defined(TARGET_X86_64) && \
2725     defined(CONFIG_USER_ONLY) && \
2726     defined(CONFIG_LINUX)
2727 # define TARGET_VSYSCALL_PAGE  (UINT64_C(-10) << 20)
2728 #endif
2729 
2730 #endif /* I386_CPU_H */
2731