1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "kvm/hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 #define KVM_HAVE_MCE_INJECTION 1 33 34 /* support for self modifying code even if the modified instruction is 35 close to the modifying instruction */ 36 #define TARGET_HAS_PRECISE_SMC 37 38 #ifdef TARGET_X86_64 39 #define I386_ELF_MACHINE EM_X86_64 40 #define ELF_MACHINE_UNAME "x86_64" 41 #else 42 #define I386_ELF_MACHINE EM_386 43 #define ELF_MACHINE_UNAME "i686" 44 #endif 45 46 enum { 47 R_EAX = 0, 48 R_ECX = 1, 49 R_EDX = 2, 50 R_EBX = 3, 51 R_ESP = 4, 52 R_EBP = 5, 53 R_ESI = 6, 54 R_EDI = 7, 55 R_R8 = 8, 56 R_R9 = 9, 57 R_R10 = 10, 58 R_R11 = 11, 59 R_R12 = 12, 60 R_R13 = 13, 61 R_R14 = 14, 62 R_R15 = 15, 63 64 R_AL = 0, 65 R_CL = 1, 66 R_DL = 2, 67 R_BL = 3, 68 R_AH = 4, 69 R_CH = 5, 70 R_DH = 6, 71 R_BH = 7, 72 }; 73 74 typedef enum X86Seg { 75 R_ES = 0, 76 R_CS = 1, 77 R_SS = 2, 78 R_DS = 3, 79 R_FS = 4, 80 R_GS = 5, 81 R_LDTR = 6, 82 R_TR = 7, 83 } X86Seg; 84 85 /* segment descriptor fields */ 86 #define DESC_G_SHIFT 23 87 #define DESC_G_MASK (1 << DESC_G_SHIFT) 88 #define DESC_B_SHIFT 22 89 #define DESC_B_MASK (1 << DESC_B_SHIFT) 90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91 #define DESC_L_MASK (1 << DESC_L_SHIFT) 92 #define DESC_AVL_SHIFT 20 93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94 #define DESC_P_SHIFT 15 95 #define DESC_P_MASK (1 << DESC_P_SHIFT) 96 #define DESC_DPL_SHIFT 13 97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98 #define DESC_S_SHIFT 12 99 #define DESC_S_MASK (1 << DESC_S_SHIFT) 100 #define DESC_TYPE_SHIFT 8 101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102 #define DESC_A_MASK (1 << 8) 103 104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105 #define DESC_C_MASK (1 << 10) /* code: conforming */ 106 #define DESC_R_MASK (1 << 9) /* code: readable */ 107 108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109 #define DESC_W_MASK (1 << 9) /* data: writable */ 110 111 #define DESC_TSS_BUSY_MASK (1 << 9) 112 113 /* eflags masks */ 114 #define CC_C 0x0001 115 #define CC_P 0x0004 116 #define CC_A 0x0010 117 #define CC_Z 0x0040 118 #define CC_S 0x0080 119 #define CC_O 0x0800 120 121 #define TF_SHIFT 8 122 #define IOPL_SHIFT 12 123 #define VM_SHIFT 17 124 125 #define TF_MASK 0x00000100 126 #define IF_MASK 0x00000200 127 #define DF_MASK 0x00000400 128 #define IOPL_MASK 0x00003000 129 #define NT_MASK 0x00004000 130 #define RF_MASK 0x00010000 131 #define VM_MASK 0x00020000 132 #define AC_MASK 0x00040000 133 #define VIF_MASK 0x00080000 134 #define VIP_MASK 0x00100000 135 #define ID_MASK 0x00200000 136 137 /* hidden flags - used internally by qemu to represent additional cpu 138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140 positions to ease oring with eflags. */ 141 /* current cpl */ 142 #define HF_CPL_SHIFT 0 143 /* true if hardware interrupts must be disabled for next instruction */ 144 #define HF_INHIBIT_IRQ_SHIFT 3 145 /* 16 or 32 segments */ 146 #define HF_CS32_SHIFT 4 147 #define HF_SS32_SHIFT 5 148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149 #define HF_ADDSEG_SHIFT 6 150 /* copy of CR0.PE (protected mode) */ 151 #define HF_PE_SHIFT 7 152 #define HF_TF_SHIFT 8 /* must be same as eflags */ 153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154 #define HF_EM_SHIFT 10 155 #define HF_TS_SHIFT 11 156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159 #define HF_RF_SHIFT 16 /* must be same as eflags */ 160 #define HF_VM_SHIFT 17 /* must be same as eflags */ 161 #define HF_AC_SHIFT 18 /* must be same as eflags */ 162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170 171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176 #define HF_PE_MASK (1 << HF_PE_SHIFT) 177 #define HF_TF_MASK (1 << HF_TF_SHIFT) 178 #define HF_MP_MASK (1 << HF_MP_SHIFT) 179 #define HF_EM_MASK (1 << HF_EM_SHIFT) 180 #define HF_TS_MASK (1 << HF_TS_SHIFT) 181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184 #define HF_RF_MASK (1 << HF_RF_SHIFT) 185 #define HF_VM_MASK (1 << HF_VM_SHIFT) 186 #define HF_AC_MASK (1 << HF_AC_SHIFT) 187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195 196 /* hflags2 */ 197 198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 206 207 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 208 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 209 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 210 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 211 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 212 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 213 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 214 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 215 216 #define CR0_PE_SHIFT 0 217 #define CR0_MP_SHIFT 1 218 219 #define CR0_PE_MASK (1U << 0) 220 #define CR0_MP_MASK (1U << 1) 221 #define CR0_EM_MASK (1U << 2) 222 #define CR0_TS_MASK (1U << 3) 223 #define CR0_ET_MASK (1U << 4) 224 #define CR0_NE_MASK (1U << 5) 225 #define CR0_WP_MASK (1U << 16) 226 #define CR0_AM_MASK (1U << 18) 227 #define CR0_PG_MASK (1U << 31) 228 229 #define CR4_VME_MASK (1U << 0) 230 #define CR4_PVI_MASK (1U << 1) 231 #define CR4_TSD_MASK (1U << 2) 232 #define CR4_DE_MASK (1U << 3) 233 #define CR4_PSE_MASK (1U << 4) 234 #define CR4_PAE_MASK (1U << 5) 235 #define CR4_MCE_MASK (1U << 6) 236 #define CR4_PGE_MASK (1U << 7) 237 #define CR4_PCE_MASK (1U << 8) 238 #define CR4_OSFXSR_SHIFT 9 239 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 240 #define CR4_OSXMMEXCPT_MASK (1U << 10) 241 #define CR4_LA57_MASK (1U << 12) 242 #define CR4_VMXE_MASK (1U << 13) 243 #define CR4_SMXE_MASK (1U << 14) 244 #define CR4_FSGSBASE_MASK (1U << 16) 245 #define CR4_PCIDE_MASK (1U << 17) 246 #define CR4_OSXSAVE_MASK (1U << 18) 247 #define CR4_SMEP_MASK (1U << 20) 248 #define CR4_SMAP_MASK (1U << 21) 249 #define CR4_PKE_MASK (1U << 22) 250 #define CR4_PKS_MASK (1U << 24) 251 252 #define DR6_BD (1 << 13) 253 #define DR6_BS (1 << 14) 254 #define DR6_BT (1 << 15) 255 #define DR6_FIXED_1 0xffff0ff0 256 257 #define DR7_GD (1 << 13) 258 #define DR7_TYPE_SHIFT 16 259 #define DR7_LEN_SHIFT 18 260 #define DR7_FIXED_1 0x00000400 261 #define DR7_GLOBAL_BP_MASK 0xaa 262 #define DR7_LOCAL_BP_MASK 0x55 263 #define DR7_MAX_BP 4 264 #define DR7_TYPE_BP_INST 0x0 265 #define DR7_TYPE_DATA_WR 0x1 266 #define DR7_TYPE_IO_RW 0x2 267 #define DR7_TYPE_DATA_RW 0x3 268 269 #define PG_PRESENT_BIT 0 270 #define PG_RW_BIT 1 271 #define PG_USER_BIT 2 272 #define PG_PWT_BIT 3 273 #define PG_PCD_BIT 4 274 #define PG_ACCESSED_BIT 5 275 #define PG_DIRTY_BIT 6 276 #define PG_PSE_BIT 7 277 #define PG_GLOBAL_BIT 8 278 #define PG_PSE_PAT_BIT 12 279 #define PG_PKRU_BIT 59 280 #define PG_NX_BIT 63 281 282 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 283 #define PG_RW_MASK (1 << PG_RW_BIT) 284 #define PG_USER_MASK (1 << PG_USER_BIT) 285 #define PG_PWT_MASK (1 << PG_PWT_BIT) 286 #define PG_PCD_MASK (1 << PG_PCD_BIT) 287 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 288 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 289 #define PG_PSE_MASK (1 << PG_PSE_BIT) 290 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 291 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 292 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 293 #define PG_HI_USER_MASK 0x7ff0000000000000LL 294 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 295 #define PG_NX_MASK (1ULL << PG_NX_BIT) 296 297 #define PG_ERROR_W_BIT 1 298 299 #define PG_ERROR_P_MASK 0x01 300 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 301 #define PG_ERROR_U_MASK 0x04 302 #define PG_ERROR_RSVD_MASK 0x08 303 #define PG_ERROR_I_D_MASK 0x10 304 #define PG_ERROR_PK_MASK 0x20 305 306 #define PG_MODE_PAE (1 << 0) 307 #define PG_MODE_LMA (1 << 1) 308 #define PG_MODE_NXE (1 << 2) 309 #define PG_MODE_PSE (1 << 3) 310 #define PG_MODE_LA57 (1 << 4) 311 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) 312 313 /* Bits of CR4 that do not affect the NPT page format. */ 314 #define PG_MODE_WP (1 << 16) 315 #define PG_MODE_PKE (1 << 17) 316 #define PG_MODE_PKS (1 << 18) 317 #define PG_MODE_SMEP (1 << 19) 318 319 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 320 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 321 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 322 323 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 324 #define MCE_BANKS_DEF 10 325 326 #define MCG_CAP_BANKS_MASK 0xff 327 328 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 329 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 330 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 331 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 332 333 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 334 335 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 336 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 337 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 338 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 339 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 340 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 341 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 342 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 343 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 344 345 /* MISC register defines */ 346 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 347 #define MCM_ADDR_LINEAR 1 /* linear address */ 348 #define MCM_ADDR_PHYS 2 /* physical address */ 349 #define MCM_ADDR_MEM 3 /* memory address */ 350 #define MCM_ADDR_GENERIC 7 /* generic */ 351 352 #define MSR_IA32_TSC 0x10 353 #define MSR_IA32_APICBASE 0x1b 354 #define MSR_IA32_APICBASE_BSP (1<<8) 355 #define MSR_IA32_APICBASE_ENABLE (1<<11) 356 #define MSR_IA32_APICBASE_EXTD (1 << 10) 357 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 358 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 359 #define MSR_TSC_ADJUST 0x0000003b 360 #define MSR_IA32_SPEC_CTRL 0x48 361 #define MSR_VIRT_SSBD 0xc001011f 362 #define MSR_IA32_PRED_CMD 0x49 363 #define MSR_IA32_UCODE_REV 0x8b 364 #define MSR_IA32_CORE_CAPABILITY 0xcf 365 366 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 367 #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 368 369 #define MSR_IA32_PERF_CAPABILITIES 0x345 370 371 #define MSR_IA32_TSX_CTRL 0x122 372 #define MSR_IA32_TSCDEADLINE 0x6e0 373 #define MSR_IA32_PKRS 0x6e1 374 375 #define FEATURE_CONTROL_LOCKED (1<<0) 376 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 377 #define FEATURE_CONTROL_LMCE (1<<20) 378 379 #define MSR_P6_PERFCTR0 0xc1 380 381 #define MSR_IA32_SMBASE 0x9e 382 #define MSR_SMI_COUNT 0x34 383 #define MSR_CORE_THREAD_COUNT 0x35 384 #define MSR_MTRRcap 0xfe 385 #define MSR_MTRRcap_VCNT 8 386 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 387 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 388 389 #define MSR_IA32_SYSENTER_CS 0x174 390 #define MSR_IA32_SYSENTER_ESP 0x175 391 #define MSR_IA32_SYSENTER_EIP 0x176 392 393 #define MSR_MCG_CAP 0x179 394 #define MSR_MCG_STATUS 0x17a 395 #define MSR_MCG_CTL 0x17b 396 #define MSR_MCG_EXT_CTL 0x4d0 397 398 #define MSR_P6_EVNTSEL0 0x186 399 400 #define MSR_IA32_PERF_STATUS 0x198 401 402 #define MSR_IA32_MISC_ENABLE 0x1a0 403 /* Indicates good rep/movs microcode on some processors: */ 404 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 405 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 406 407 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 408 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 409 410 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 411 412 #define MSR_MTRRfix64K_00000 0x250 413 #define MSR_MTRRfix16K_80000 0x258 414 #define MSR_MTRRfix16K_A0000 0x259 415 #define MSR_MTRRfix4K_C0000 0x268 416 #define MSR_MTRRfix4K_C8000 0x269 417 #define MSR_MTRRfix4K_D0000 0x26a 418 #define MSR_MTRRfix4K_D8000 0x26b 419 #define MSR_MTRRfix4K_E0000 0x26c 420 #define MSR_MTRRfix4K_E8000 0x26d 421 #define MSR_MTRRfix4K_F0000 0x26e 422 #define MSR_MTRRfix4K_F8000 0x26f 423 424 #define MSR_PAT 0x277 425 426 #define MSR_MTRRdefType 0x2ff 427 428 #define MSR_CORE_PERF_FIXED_CTR0 0x309 429 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 430 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 431 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 432 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 433 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 434 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 435 436 #define MSR_MC0_CTL 0x400 437 #define MSR_MC0_STATUS 0x401 438 #define MSR_MC0_ADDR 0x402 439 #define MSR_MC0_MISC 0x403 440 441 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 442 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 443 #define MSR_IA32_RTIT_CTL 0x570 444 #define MSR_IA32_RTIT_STATUS 0x571 445 #define MSR_IA32_RTIT_CR3_MATCH 0x572 446 #define MSR_IA32_RTIT_ADDR0_A 0x580 447 #define MSR_IA32_RTIT_ADDR0_B 0x581 448 #define MSR_IA32_RTIT_ADDR1_A 0x582 449 #define MSR_IA32_RTIT_ADDR1_B 0x583 450 #define MSR_IA32_RTIT_ADDR2_A 0x584 451 #define MSR_IA32_RTIT_ADDR2_B 0x585 452 #define MSR_IA32_RTIT_ADDR3_A 0x586 453 #define MSR_IA32_RTIT_ADDR3_B 0x587 454 #define MAX_RTIT_ADDRS 8 455 456 #define MSR_EFER 0xc0000080 457 458 #define MSR_EFER_SCE (1 << 0) 459 #define MSR_EFER_LME (1 << 8) 460 #define MSR_EFER_LMA (1 << 10) 461 #define MSR_EFER_NXE (1 << 11) 462 #define MSR_EFER_SVME (1 << 12) 463 #define MSR_EFER_FFXSR (1 << 14) 464 465 #define MSR_STAR 0xc0000081 466 #define MSR_LSTAR 0xc0000082 467 #define MSR_CSTAR 0xc0000083 468 #define MSR_FMASK 0xc0000084 469 #define MSR_FSBASE 0xc0000100 470 #define MSR_GSBASE 0xc0000101 471 #define MSR_KERNELGSBASE 0xc0000102 472 #define MSR_TSC_AUX 0xc0000103 473 474 #define MSR_VM_HSAVE_PA 0xc0010117 475 476 #define MSR_IA32_BNDCFGS 0x00000d90 477 #define MSR_IA32_XSS 0x00000da0 478 #define MSR_IA32_UMWAIT_CONTROL 0xe1 479 480 #define MSR_IA32_VMX_BASIC 0x00000480 481 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 482 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 483 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 484 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 485 #define MSR_IA32_VMX_MISC 0x00000485 486 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 487 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 488 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 489 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 490 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 491 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 492 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 493 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 494 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 495 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 496 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 497 #define MSR_IA32_VMX_VMFUNC 0x00000491 498 499 #define XSTATE_FP_BIT 0 500 #define XSTATE_SSE_BIT 1 501 #define XSTATE_YMM_BIT 2 502 #define XSTATE_BNDREGS_BIT 3 503 #define XSTATE_BNDCSR_BIT 4 504 #define XSTATE_OPMASK_BIT 5 505 #define XSTATE_ZMM_Hi256_BIT 6 506 #define XSTATE_Hi16_ZMM_BIT 7 507 #define XSTATE_PKRU_BIT 9 508 509 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 510 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 511 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 512 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 513 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 514 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 515 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 516 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 517 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 518 519 /* CPUID feature words */ 520 typedef enum FeatureWord { 521 FEAT_1_EDX, /* CPUID[1].EDX */ 522 FEAT_1_ECX, /* CPUID[1].ECX */ 523 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 524 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 525 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 526 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 527 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 528 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 529 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 530 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 531 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 532 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 533 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 534 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 535 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 536 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 537 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ 538 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ 539 FEAT_SVM, /* CPUID[8000_000A].EDX */ 540 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 541 FEAT_6_EAX, /* CPUID[6].EAX */ 542 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 543 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 544 FEAT_ARCH_CAPABILITIES, 545 FEAT_CORE_CAPABILITY, 546 FEAT_PERF_CAPABILITIES, 547 FEAT_VMX_PROCBASED_CTLS, 548 FEAT_VMX_SECONDARY_CTLS, 549 FEAT_VMX_PINBASED_CTLS, 550 FEAT_VMX_EXIT_CTLS, 551 FEAT_VMX_ENTRY_CTLS, 552 FEAT_VMX_MISC, 553 FEAT_VMX_EPT_VPID_CAPS, 554 FEAT_VMX_BASIC, 555 FEAT_VMX_VMFUNC, 556 FEAT_14_0_ECX, 557 FEATURE_WORDS, 558 } FeatureWord; 559 560 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 561 562 /* cpuid_features bits */ 563 #define CPUID_FP87 (1U << 0) 564 #define CPUID_VME (1U << 1) 565 #define CPUID_DE (1U << 2) 566 #define CPUID_PSE (1U << 3) 567 #define CPUID_TSC (1U << 4) 568 #define CPUID_MSR (1U << 5) 569 #define CPUID_PAE (1U << 6) 570 #define CPUID_MCE (1U << 7) 571 #define CPUID_CX8 (1U << 8) 572 #define CPUID_APIC (1U << 9) 573 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 574 #define CPUID_MTRR (1U << 12) 575 #define CPUID_PGE (1U << 13) 576 #define CPUID_MCA (1U << 14) 577 #define CPUID_CMOV (1U << 15) 578 #define CPUID_PAT (1U << 16) 579 #define CPUID_PSE36 (1U << 17) 580 #define CPUID_PN (1U << 18) 581 #define CPUID_CLFLUSH (1U << 19) 582 #define CPUID_DTS (1U << 21) 583 #define CPUID_ACPI (1U << 22) 584 #define CPUID_MMX (1U << 23) 585 #define CPUID_FXSR (1U << 24) 586 #define CPUID_SSE (1U << 25) 587 #define CPUID_SSE2 (1U << 26) 588 #define CPUID_SS (1U << 27) 589 #define CPUID_HT (1U << 28) 590 #define CPUID_TM (1U << 29) 591 #define CPUID_IA64 (1U << 30) 592 #define CPUID_PBE (1U << 31) 593 594 #define CPUID_EXT_SSE3 (1U << 0) 595 #define CPUID_EXT_PCLMULQDQ (1U << 1) 596 #define CPUID_EXT_DTES64 (1U << 2) 597 #define CPUID_EXT_MONITOR (1U << 3) 598 #define CPUID_EXT_DSCPL (1U << 4) 599 #define CPUID_EXT_VMX (1U << 5) 600 #define CPUID_EXT_SMX (1U << 6) 601 #define CPUID_EXT_EST (1U << 7) 602 #define CPUID_EXT_TM2 (1U << 8) 603 #define CPUID_EXT_SSSE3 (1U << 9) 604 #define CPUID_EXT_CID (1U << 10) 605 #define CPUID_EXT_FMA (1U << 12) 606 #define CPUID_EXT_CX16 (1U << 13) 607 #define CPUID_EXT_XTPR (1U << 14) 608 #define CPUID_EXT_PDCM (1U << 15) 609 #define CPUID_EXT_PCID (1U << 17) 610 #define CPUID_EXT_DCA (1U << 18) 611 #define CPUID_EXT_SSE41 (1U << 19) 612 #define CPUID_EXT_SSE42 (1U << 20) 613 #define CPUID_EXT_X2APIC (1U << 21) 614 #define CPUID_EXT_MOVBE (1U << 22) 615 #define CPUID_EXT_POPCNT (1U << 23) 616 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 617 #define CPUID_EXT_AES (1U << 25) 618 #define CPUID_EXT_XSAVE (1U << 26) 619 #define CPUID_EXT_OSXSAVE (1U << 27) 620 #define CPUID_EXT_AVX (1U << 28) 621 #define CPUID_EXT_F16C (1U << 29) 622 #define CPUID_EXT_RDRAND (1U << 30) 623 #define CPUID_EXT_HYPERVISOR (1U << 31) 624 625 #define CPUID_EXT2_FPU (1U << 0) 626 #define CPUID_EXT2_VME (1U << 1) 627 #define CPUID_EXT2_DE (1U << 2) 628 #define CPUID_EXT2_PSE (1U << 3) 629 #define CPUID_EXT2_TSC (1U << 4) 630 #define CPUID_EXT2_MSR (1U << 5) 631 #define CPUID_EXT2_PAE (1U << 6) 632 #define CPUID_EXT2_MCE (1U << 7) 633 #define CPUID_EXT2_CX8 (1U << 8) 634 #define CPUID_EXT2_APIC (1U << 9) 635 #define CPUID_EXT2_SYSCALL (1U << 11) 636 #define CPUID_EXT2_MTRR (1U << 12) 637 #define CPUID_EXT2_PGE (1U << 13) 638 #define CPUID_EXT2_MCA (1U << 14) 639 #define CPUID_EXT2_CMOV (1U << 15) 640 #define CPUID_EXT2_PAT (1U << 16) 641 #define CPUID_EXT2_PSE36 (1U << 17) 642 #define CPUID_EXT2_MP (1U << 19) 643 #define CPUID_EXT2_NX (1U << 20) 644 #define CPUID_EXT2_MMXEXT (1U << 22) 645 #define CPUID_EXT2_MMX (1U << 23) 646 #define CPUID_EXT2_FXSR (1U << 24) 647 #define CPUID_EXT2_FFXSR (1U << 25) 648 #define CPUID_EXT2_PDPE1GB (1U << 26) 649 #define CPUID_EXT2_RDTSCP (1U << 27) 650 #define CPUID_EXT2_LM (1U << 29) 651 #define CPUID_EXT2_3DNOWEXT (1U << 30) 652 #define CPUID_EXT2_3DNOW (1U << 31) 653 654 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 655 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 656 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 657 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 658 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 659 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 660 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 661 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 662 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 663 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 664 665 #define CPUID_EXT3_LAHF_LM (1U << 0) 666 #define CPUID_EXT3_CMP_LEG (1U << 1) 667 #define CPUID_EXT3_SVM (1U << 2) 668 #define CPUID_EXT3_EXTAPIC (1U << 3) 669 #define CPUID_EXT3_CR8LEG (1U << 4) 670 #define CPUID_EXT3_ABM (1U << 5) 671 #define CPUID_EXT3_SSE4A (1U << 6) 672 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 673 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 674 #define CPUID_EXT3_OSVW (1U << 9) 675 #define CPUID_EXT3_IBS (1U << 10) 676 #define CPUID_EXT3_XOP (1U << 11) 677 #define CPUID_EXT3_SKINIT (1U << 12) 678 #define CPUID_EXT3_WDT (1U << 13) 679 #define CPUID_EXT3_LWP (1U << 15) 680 #define CPUID_EXT3_FMA4 (1U << 16) 681 #define CPUID_EXT3_TCE (1U << 17) 682 #define CPUID_EXT3_NODEID (1U << 19) 683 #define CPUID_EXT3_TBM (1U << 21) 684 #define CPUID_EXT3_TOPOEXT (1U << 22) 685 #define CPUID_EXT3_PERFCORE (1U << 23) 686 #define CPUID_EXT3_PERFNB (1U << 24) 687 688 #define CPUID_SVM_NPT (1U << 0) 689 #define CPUID_SVM_LBRV (1U << 1) 690 #define CPUID_SVM_SVMLOCK (1U << 2) 691 #define CPUID_SVM_NRIPSAVE (1U << 3) 692 #define CPUID_SVM_TSCSCALE (1U << 4) 693 #define CPUID_SVM_VMCBCLEAN (1U << 5) 694 #define CPUID_SVM_FLUSHASID (1U << 6) 695 #define CPUID_SVM_DECODEASSIST (1U << 7) 696 #define CPUID_SVM_PAUSEFILTER (1U << 10) 697 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 698 #define CPUID_SVM_AVIC (1U << 13) 699 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) 700 #define CPUID_SVM_VGIF (1U << 16) 701 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) 702 703 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 704 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 705 /* 1st Group of Advanced Bit Manipulation Extensions */ 706 #define CPUID_7_0_EBX_BMI1 (1U << 3) 707 /* Hardware Lock Elision */ 708 #define CPUID_7_0_EBX_HLE (1U << 4) 709 /* Intel Advanced Vector Extensions 2 */ 710 #define CPUID_7_0_EBX_AVX2 (1U << 5) 711 /* Supervisor-mode Execution Prevention */ 712 #define CPUID_7_0_EBX_SMEP (1U << 7) 713 /* 2nd Group of Advanced Bit Manipulation Extensions */ 714 #define CPUID_7_0_EBX_BMI2 (1U << 8) 715 /* Enhanced REP MOVSB/STOSB */ 716 #define CPUID_7_0_EBX_ERMS (1U << 9) 717 /* Invalidate Process-Context Identifier */ 718 #define CPUID_7_0_EBX_INVPCID (1U << 10) 719 /* Restricted Transactional Memory */ 720 #define CPUID_7_0_EBX_RTM (1U << 11) 721 /* Memory Protection Extension */ 722 #define CPUID_7_0_EBX_MPX (1U << 14) 723 /* AVX-512 Foundation */ 724 #define CPUID_7_0_EBX_AVX512F (1U << 16) 725 /* AVX-512 Doubleword & Quadword Instruction */ 726 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 727 /* Read Random SEED */ 728 #define CPUID_7_0_EBX_RDSEED (1U << 18) 729 /* ADCX and ADOX instructions */ 730 #define CPUID_7_0_EBX_ADX (1U << 19) 731 /* Supervisor Mode Access Prevention */ 732 #define CPUID_7_0_EBX_SMAP (1U << 20) 733 /* AVX-512 Integer Fused Multiply Add */ 734 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 735 /* Persistent Commit */ 736 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 737 /* Flush a Cache Line Optimized */ 738 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 739 /* Cache Line Write Back */ 740 #define CPUID_7_0_EBX_CLWB (1U << 24) 741 /* Intel Processor Trace */ 742 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 743 /* AVX-512 Prefetch */ 744 #define CPUID_7_0_EBX_AVX512PF (1U << 26) 745 /* AVX-512 Exponential and Reciprocal */ 746 #define CPUID_7_0_EBX_AVX512ER (1U << 27) 747 /* AVX-512 Conflict Detection */ 748 #define CPUID_7_0_EBX_AVX512CD (1U << 28) 749 /* SHA1/SHA256 Instruction Extensions */ 750 #define CPUID_7_0_EBX_SHA_NI (1U << 29) 751 /* AVX-512 Byte and Word Instructions */ 752 #define CPUID_7_0_EBX_AVX512BW (1U << 30) 753 /* AVX-512 Vector Length Extensions */ 754 #define CPUID_7_0_EBX_AVX512VL (1U << 31) 755 756 /* AVX-512 Vector Byte Manipulation Instruction */ 757 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 758 /* User-Mode Instruction Prevention */ 759 #define CPUID_7_0_ECX_UMIP (1U << 2) 760 /* Protection Keys for User-mode Pages */ 761 #define CPUID_7_0_ECX_PKU (1U << 3) 762 /* OS Enable Protection Keys */ 763 #define CPUID_7_0_ECX_OSPKE (1U << 4) 764 /* UMONITOR/UMWAIT/TPAUSE Instructions */ 765 #define CPUID_7_0_ECX_WAITPKG (1U << 5) 766 /* Additional AVX-512 Vector Byte Manipulation Instruction */ 767 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 768 /* Galois Field New Instructions */ 769 #define CPUID_7_0_ECX_GFNI (1U << 8) 770 /* Vector AES Instructions */ 771 #define CPUID_7_0_ECX_VAES (1U << 9) 772 /* Carry-Less Multiplication Quadword */ 773 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 774 /* Vector Neural Network Instructions */ 775 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 776 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 777 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 778 /* POPCNT for vectors of DW/QW */ 779 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 780 /* 5-level Page Tables */ 781 #define CPUID_7_0_ECX_LA57 (1U << 16) 782 /* Read Processor ID */ 783 #define CPUID_7_0_ECX_RDPID (1U << 22) 784 /* Bus Lock Debug Exception */ 785 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) 786 /* Cache Line Demote Instruction */ 787 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 788 /* Move Doubleword as Direct Store Instruction */ 789 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 790 /* Move 64 Bytes as Direct Store Instruction */ 791 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 792 /* Protection Keys for Supervisor-mode Pages */ 793 #define CPUID_7_0_ECX_PKS (1U << 31) 794 795 /* AVX512 Neural Network Instructions */ 796 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 797 /* AVX512 Multiply Accumulation Single Precision */ 798 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 799 /* Fast Short Rep Mov */ 800 #define CPUID_7_0_EDX_FSRM (1U << 4) 801 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 802 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 803 /* SERIALIZE instruction */ 804 #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 805 /* TSX Suspend Load Address Tracking instruction */ 806 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 807 /* AVX512_FP16 instruction */ 808 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) 809 /* Speculation Control */ 810 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 811 /* Single Thread Indirect Branch Predictors */ 812 #define CPUID_7_0_EDX_STIBP (1U << 27) 813 /* Arch Capabilities */ 814 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 815 /* Core Capability */ 816 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 817 /* Speculative Store Bypass Disable */ 818 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 819 820 /* AVX VNNI Instruction */ 821 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) 822 /* AVX512 BFloat16 Instruction */ 823 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 824 825 /* Packets which contain IP payload have LIP values */ 826 #define CPUID_14_0_ECX_LIP (1U << 31) 827 828 /* CLZERO instruction */ 829 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 830 /* Always save/restore FP error pointers */ 831 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 832 /* Write back and do not invalidate cache */ 833 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 834 /* Indirect Branch Prediction Barrier */ 835 #define CPUID_8000_0008_EBX_IBPB (1U << 12) 836 /* Indirect Branch Restricted Speculation */ 837 #define CPUID_8000_0008_EBX_IBRS (1U << 14) 838 /* Single Thread Indirect Branch Predictors */ 839 #define CPUID_8000_0008_EBX_STIBP (1U << 15) 840 /* Speculative Store Bypass Disable */ 841 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) 842 843 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 844 #define CPUID_XSAVE_XSAVEC (1U << 1) 845 #define CPUID_XSAVE_XGETBV1 (1U << 2) 846 #define CPUID_XSAVE_XSAVES (1U << 3) 847 848 #define CPUID_6_EAX_ARAT (1U << 2) 849 850 /* CPUID[0x80000007].EDX flags: */ 851 #define CPUID_APM_INVTSC (1U << 8) 852 853 #define CPUID_VENDOR_SZ 12 854 855 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 856 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 857 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 858 #define CPUID_VENDOR_INTEL "GenuineIntel" 859 860 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 861 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 862 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 863 #define CPUID_VENDOR_AMD "AuthenticAMD" 864 865 #define CPUID_VENDOR_VIA "CentaurHauls" 866 867 #define CPUID_VENDOR_HYGON "HygonGenuine" 868 869 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 870 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 871 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 872 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 873 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 874 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 875 876 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 877 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 878 879 /* CPUID[0xB].ECX level types */ 880 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 881 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 882 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 883 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 884 885 /* MSR Feature Bits */ 886 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 887 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 888 #define MSR_ARCH_CAP_RSBA (1U << 2) 889 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 890 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 891 #define MSR_ARCH_CAP_MDS_NO (1U << 5) 892 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 893 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 894 #define MSR_ARCH_CAP_TAA_NO (1U << 8) 895 896 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 897 898 /* VMX MSR features */ 899 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 900 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 901 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 902 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 903 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 904 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 905 906 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 907 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 908 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 909 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 910 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 911 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 912 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 913 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 914 915 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 916 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 917 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 918 #define MSR_VMX_EPT_UC (1ULL << 8) 919 #define MSR_VMX_EPT_WB (1ULL << 14) 920 #define MSR_VMX_EPT_2MB (1ULL << 16) 921 #define MSR_VMX_EPT_1GB (1ULL << 17) 922 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 923 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 924 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 925 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 926 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 927 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 928 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 929 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 930 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 931 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 932 933 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 934 935 936 /* VMX controls */ 937 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 938 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 939 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 940 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 941 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 942 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 943 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 944 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 945 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 946 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 947 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 948 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 949 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 950 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 951 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 952 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 953 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 954 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 955 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 956 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 957 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 958 959 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 960 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 961 #define VMX_SECONDARY_EXEC_DESC 0x00000004 962 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 963 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 964 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 965 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 966 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 967 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 968 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 969 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 970 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 971 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 972 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 973 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 974 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 975 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 976 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 977 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 978 979 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 980 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 981 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 982 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 983 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 984 985 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 986 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 987 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 988 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 989 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 990 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 991 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 992 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 993 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 994 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 995 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 996 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 997 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 998 999 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 1000 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 1001 #define VMX_VM_ENTRY_SMM 0x00000400 1002 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 1003 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 1004 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 1005 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 1006 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 1007 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 1008 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 1009 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 1010 1011 /* Supported Hyper-V Enlightenments */ 1012 #define HYPERV_FEAT_RELAXED 0 1013 #define HYPERV_FEAT_VAPIC 1 1014 #define HYPERV_FEAT_TIME 2 1015 #define HYPERV_FEAT_CRASH 3 1016 #define HYPERV_FEAT_RESET 4 1017 #define HYPERV_FEAT_VPINDEX 5 1018 #define HYPERV_FEAT_RUNTIME 6 1019 #define HYPERV_FEAT_SYNIC 7 1020 #define HYPERV_FEAT_STIMER 8 1021 #define HYPERV_FEAT_FREQUENCIES 9 1022 #define HYPERV_FEAT_REENLIGHTENMENT 10 1023 #define HYPERV_FEAT_TLBFLUSH 11 1024 #define HYPERV_FEAT_EVMCS 12 1025 #define HYPERV_FEAT_IPI 13 1026 #define HYPERV_FEAT_STIMER_DIRECT 14 1027 1028 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY 1029 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF 1030 #endif 1031 1032 #define EXCP00_DIVZ 0 1033 #define EXCP01_DB 1 1034 #define EXCP02_NMI 2 1035 #define EXCP03_INT3 3 1036 #define EXCP04_INTO 4 1037 #define EXCP05_BOUND 5 1038 #define EXCP06_ILLOP 6 1039 #define EXCP07_PREX 7 1040 #define EXCP08_DBLE 8 1041 #define EXCP09_XERR 9 1042 #define EXCP0A_TSS 10 1043 #define EXCP0B_NOSEG 11 1044 #define EXCP0C_STACK 12 1045 #define EXCP0D_GPF 13 1046 #define EXCP0E_PAGE 14 1047 #define EXCP10_COPR 16 1048 #define EXCP11_ALGN 17 1049 #define EXCP12_MCHK 18 1050 1051 #define EXCP_VMEXIT 0x100 /* only for system emulation */ 1052 #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1053 #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1054 1055 /* i386-specific interrupt pending bits. */ 1056 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1057 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1058 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1059 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1060 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1061 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1062 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1063 1064 /* Use a clearer name for this. */ 1065 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1066 1067 /* Instead of computing the condition codes after each x86 instruction, 1068 * QEMU just stores one operand (called CC_SRC), the result 1069 * (called CC_DST) and the type of operation (called CC_OP). When the 1070 * condition codes are needed, the condition codes can be calculated 1071 * using this information. Condition codes are not generated if they 1072 * are only needed for conditional branches. 1073 */ 1074 typedef enum { 1075 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1076 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1077 1078 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1079 CC_OP_MULW, 1080 CC_OP_MULL, 1081 CC_OP_MULQ, 1082 1083 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1084 CC_OP_ADDW, 1085 CC_OP_ADDL, 1086 CC_OP_ADDQ, 1087 1088 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1089 CC_OP_ADCW, 1090 CC_OP_ADCL, 1091 CC_OP_ADCQ, 1092 1093 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1094 CC_OP_SUBW, 1095 CC_OP_SUBL, 1096 CC_OP_SUBQ, 1097 1098 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1099 CC_OP_SBBW, 1100 CC_OP_SBBL, 1101 CC_OP_SBBQ, 1102 1103 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1104 CC_OP_LOGICW, 1105 CC_OP_LOGICL, 1106 CC_OP_LOGICQ, 1107 1108 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1109 CC_OP_INCW, 1110 CC_OP_INCL, 1111 CC_OP_INCQ, 1112 1113 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1114 CC_OP_DECW, 1115 CC_OP_DECL, 1116 CC_OP_DECQ, 1117 1118 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1119 CC_OP_SHLW, 1120 CC_OP_SHLL, 1121 CC_OP_SHLQ, 1122 1123 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1124 CC_OP_SARW, 1125 CC_OP_SARL, 1126 CC_OP_SARQ, 1127 1128 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1129 CC_OP_BMILGW, 1130 CC_OP_BMILGL, 1131 CC_OP_BMILGQ, 1132 1133 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1134 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1135 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1136 1137 CC_OP_CLR, /* Z set, all other flags clear. */ 1138 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1139 1140 CC_OP_NB, 1141 } CCOp; 1142 1143 typedef struct SegmentCache { 1144 uint32_t selector; 1145 target_ulong base; 1146 uint32_t limit; 1147 uint32_t flags; 1148 } SegmentCache; 1149 1150 #define MMREG_UNION(n, bits) \ 1151 union n { \ 1152 uint8_t _b_##n[(bits)/8]; \ 1153 uint16_t _w_##n[(bits)/16]; \ 1154 uint32_t _l_##n[(bits)/32]; \ 1155 uint64_t _q_##n[(bits)/64]; \ 1156 float32 _s_##n[(bits)/32]; \ 1157 float64 _d_##n[(bits)/64]; \ 1158 } 1159 1160 typedef union { 1161 uint8_t _b[16]; 1162 uint16_t _w[8]; 1163 uint32_t _l[4]; 1164 uint64_t _q[2]; 1165 } XMMReg; 1166 1167 typedef union { 1168 uint8_t _b[32]; 1169 uint16_t _w[16]; 1170 uint32_t _l[8]; 1171 uint64_t _q[4]; 1172 } YMMReg; 1173 1174 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1175 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1176 1177 typedef struct BNDReg { 1178 uint64_t lb; 1179 uint64_t ub; 1180 } BNDReg; 1181 1182 typedef struct BNDCSReg { 1183 uint64_t cfgu; 1184 uint64_t sts; 1185 } BNDCSReg; 1186 1187 #define BNDCFG_ENABLE 1ULL 1188 #define BNDCFG_BNDPRESERVE 2ULL 1189 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1190 1191 #ifdef HOST_WORDS_BIGENDIAN 1192 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1193 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1194 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1195 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1196 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1197 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1198 1199 #define MMX_B(n) _b_MMXReg[7 - (n)] 1200 #define MMX_W(n) _w_MMXReg[3 - (n)] 1201 #define MMX_L(n) _l_MMXReg[1 - (n)] 1202 #define MMX_S(n) _s_MMXReg[1 - (n)] 1203 #else 1204 #define ZMM_B(n) _b_ZMMReg[n] 1205 #define ZMM_W(n) _w_ZMMReg[n] 1206 #define ZMM_L(n) _l_ZMMReg[n] 1207 #define ZMM_S(n) _s_ZMMReg[n] 1208 #define ZMM_Q(n) _q_ZMMReg[n] 1209 #define ZMM_D(n) _d_ZMMReg[n] 1210 1211 #define MMX_B(n) _b_MMXReg[n] 1212 #define MMX_W(n) _w_MMXReg[n] 1213 #define MMX_L(n) _l_MMXReg[n] 1214 #define MMX_S(n) _s_MMXReg[n] 1215 #endif 1216 #define MMX_Q(n) _q_MMXReg[n] 1217 1218 typedef union { 1219 floatx80 d __attribute__((aligned(16))); 1220 MMXReg mmx; 1221 } FPReg; 1222 1223 typedef struct { 1224 uint64_t base; 1225 uint64_t mask; 1226 } MTRRVar; 1227 1228 #define CPU_NB_REGS64 16 1229 #define CPU_NB_REGS32 8 1230 1231 #ifdef TARGET_X86_64 1232 #define CPU_NB_REGS CPU_NB_REGS64 1233 #else 1234 #define CPU_NB_REGS CPU_NB_REGS32 1235 #endif 1236 1237 #define MAX_FIXED_COUNTERS 3 1238 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1239 1240 #define TARGET_INSN_START_EXTRA_WORDS 1 1241 1242 #define NB_OPMASK_REGS 8 1243 1244 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1245 * that APIC ID hasn't been set yet 1246 */ 1247 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1248 1249 typedef union X86LegacyXSaveArea { 1250 struct { 1251 uint16_t fcw; 1252 uint16_t fsw; 1253 uint8_t ftw; 1254 uint8_t reserved; 1255 uint16_t fpop; 1256 uint64_t fpip; 1257 uint64_t fpdp; 1258 uint32_t mxcsr; 1259 uint32_t mxcsr_mask; 1260 FPReg fpregs[8]; 1261 uint8_t xmm_regs[16][16]; 1262 }; 1263 uint8_t data[512]; 1264 } X86LegacyXSaveArea; 1265 1266 typedef struct X86XSaveHeader { 1267 uint64_t xstate_bv; 1268 uint64_t xcomp_bv; 1269 uint64_t reserve0; 1270 uint8_t reserved[40]; 1271 } X86XSaveHeader; 1272 1273 /* Ext. save area 2: AVX State */ 1274 typedef struct XSaveAVX { 1275 uint8_t ymmh[16][16]; 1276 } XSaveAVX; 1277 1278 /* Ext. save area 3: BNDREG */ 1279 typedef struct XSaveBNDREG { 1280 BNDReg bnd_regs[4]; 1281 } XSaveBNDREG; 1282 1283 /* Ext. save area 4: BNDCSR */ 1284 typedef union XSaveBNDCSR { 1285 BNDCSReg bndcsr; 1286 uint8_t data[64]; 1287 } XSaveBNDCSR; 1288 1289 /* Ext. save area 5: Opmask */ 1290 typedef struct XSaveOpmask { 1291 uint64_t opmask_regs[NB_OPMASK_REGS]; 1292 } XSaveOpmask; 1293 1294 /* Ext. save area 6: ZMM_Hi256 */ 1295 typedef struct XSaveZMM_Hi256 { 1296 uint8_t zmm_hi256[16][32]; 1297 } XSaveZMM_Hi256; 1298 1299 /* Ext. save area 7: Hi16_ZMM */ 1300 typedef struct XSaveHi16_ZMM { 1301 uint8_t hi16_zmm[16][64]; 1302 } XSaveHi16_ZMM; 1303 1304 /* Ext. save area 9: PKRU state */ 1305 typedef struct XSavePKRU { 1306 uint32_t pkru; 1307 uint32_t padding; 1308 } XSavePKRU; 1309 1310 typedef struct X86XSaveArea { 1311 X86LegacyXSaveArea legacy; 1312 X86XSaveHeader header; 1313 1314 /* Extended save areas: */ 1315 1316 /* AVX State: */ 1317 XSaveAVX avx_state; 1318 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1319 /* MPX State: */ 1320 XSaveBNDREG bndreg_state; 1321 XSaveBNDCSR bndcsr_state; 1322 /* AVX-512 State: */ 1323 XSaveOpmask opmask_state; 1324 XSaveZMM_Hi256 zmm_hi256_state; 1325 XSaveHi16_ZMM hi16_zmm_state; 1326 /* PKRU State: */ 1327 XSavePKRU pkru_state; 1328 } X86XSaveArea; 1329 1330 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1331 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1332 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1333 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1334 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1335 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1336 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1337 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1338 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1339 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1340 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1341 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1342 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1343 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1344 1345 typedef enum TPRAccess { 1346 TPR_ACCESS_READ, 1347 TPR_ACCESS_WRITE, 1348 } TPRAccess; 1349 1350 /* Cache information data structures: */ 1351 1352 enum CacheType { 1353 DATA_CACHE, 1354 INSTRUCTION_CACHE, 1355 UNIFIED_CACHE 1356 }; 1357 1358 typedef struct CPUCacheInfo { 1359 enum CacheType type; 1360 uint8_t level; 1361 /* Size in bytes */ 1362 uint32_t size; 1363 /* Line size, in bytes */ 1364 uint16_t line_size; 1365 /* 1366 * Associativity. 1367 * Note: representation of fully-associative caches is not implemented 1368 */ 1369 uint8_t associativity; 1370 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1371 uint8_t partitions; 1372 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1373 uint32_t sets; 1374 /* 1375 * Lines per tag. 1376 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1377 * (Is this synonym to @partitions?) 1378 */ 1379 uint8_t lines_per_tag; 1380 1381 /* Self-initializing cache */ 1382 bool self_init; 1383 /* 1384 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1385 * non-originating threads sharing this cache. 1386 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1387 */ 1388 bool no_invd_sharing; 1389 /* 1390 * Cache is inclusive of lower cache levels. 1391 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1392 */ 1393 bool inclusive; 1394 /* 1395 * A complex function is used to index the cache, potentially using all 1396 * address bits. CPUID[4].EDX[bit 2]. 1397 */ 1398 bool complex_indexing; 1399 } CPUCacheInfo; 1400 1401 1402 typedef struct CPUCaches { 1403 CPUCacheInfo *l1d_cache; 1404 CPUCacheInfo *l1i_cache; 1405 CPUCacheInfo *l2_cache; 1406 CPUCacheInfo *l3_cache; 1407 } CPUCaches; 1408 1409 typedef struct HVFX86LazyFlags { 1410 target_ulong result; 1411 target_ulong auxbits; 1412 } HVFX86LazyFlags; 1413 1414 typedef struct CPUX86State { 1415 /* standard registers */ 1416 target_ulong regs[CPU_NB_REGS]; 1417 target_ulong eip; 1418 target_ulong eflags; /* eflags register. During CPU emulation, CC 1419 flags and DF are set to zero because they are 1420 stored elsewhere */ 1421 1422 /* emulator internal eflags handling */ 1423 target_ulong cc_dst; 1424 target_ulong cc_src; 1425 target_ulong cc_src2; 1426 uint32_t cc_op; 1427 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1428 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1429 are known at translation time. */ 1430 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1431 1432 /* segments */ 1433 SegmentCache segs[6]; /* selector values */ 1434 SegmentCache ldt; 1435 SegmentCache tr; 1436 SegmentCache gdt; /* only base and limit are used */ 1437 SegmentCache idt; /* only base and limit are used */ 1438 1439 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1440 int32_t a20_mask; 1441 1442 BNDReg bnd_regs[4]; 1443 BNDCSReg bndcs_regs; 1444 uint64_t msr_bndcfgs; 1445 uint64_t efer; 1446 1447 /* Beginning of state preserved by INIT (dummy marker). */ 1448 struct {} start_init_save; 1449 1450 /* FPU state */ 1451 unsigned int fpstt; /* top of stack index */ 1452 uint16_t fpus; 1453 uint16_t fpuc; 1454 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1455 FPReg fpregs[8]; 1456 /* KVM-only so far */ 1457 uint16_t fpop; 1458 uint64_t fpip; 1459 uint64_t fpdp; 1460 1461 /* emulator internal variables */ 1462 float_status fp_status; 1463 floatx80 ft0; 1464 1465 float_status mmx_status; /* for 3DNow! float ops */ 1466 float_status sse_status; 1467 uint32_t mxcsr; 1468 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1469 ZMMReg xmm_t0; 1470 MMXReg mmx_t0; 1471 1472 XMMReg ymmh_regs[CPU_NB_REGS]; 1473 1474 uint64_t opmask_regs[NB_OPMASK_REGS]; 1475 YMMReg zmmh_regs[CPU_NB_REGS]; 1476 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1477 1478 /* sysenter registers */ 1479 uint32_t sysenter_cs; 1480 target_ulong sysenter_esp; 1481 target_ulong sysenter_eip; 1482 uint64_t star; 1483 1484 uint64_t vm_hsave; 1485 1486 #ifdef TARGET_X86_64 1487 target_ulong lstar; 1488 target_ulong cstar; 1489 target_ulong fmask; 1490 target_ulong kernelgsbase; 1491 #endif 1492 1493 uint64_t tsc; 1494 uint64_t tsc_adjust; 1495 uint64_t tsc_deadline; 1496 uint64_t tsc_aux; 1497 1498 uint64_t xcr0; 1499 1500 uint64_t mcg_status; 1501 uint64_t msr_ia32_misc_enable; 1502 uint64_t msr_ia32_feature_control; 1503 1504 uint64_t msr_fixed_ctr_ctrl; 1505 uint64_t msr_global_ctrl; 1506 uint64_t msr_global_status; 1507 uint64_t msr_global_ovf_ctrl; 1508 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1509 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1510 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1511 1512 uint64_t pat; 1513 uint32_t smbase; 1514 uint64_t msr_smi_count; 1515 1516 uint32_t pkru; 1517 uint32_t pkrs; 1518 uint32_t tsx_ctrl; 1519 1520 uint64_t spec_ctrl; 1521 uint64_t virt_ssbd; 1522 1523 /* End of state preserved by INIT (dummy marker). */ 1524 struct {} end_init_save; 1525 1526 uint64_t system_time_msr; 1527 uint64_t wall_clock_msr; 1528 uint64_t steal_time_msr; 1529 uint64_t async_pf_en_msr; 1530 uint64_t async_pf_int_msr; 1531 uint64_t pv_eoi_en_msr; 1532 uint64_t poll_control_msr; 1533 1534 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1535 uint64_t msr_hv_hypercall; 1536 uint64_t msr_hv_guest_os_id; 1537 uint64_t msr_hv_tsc; 1538 1539 /* Per-VCPU HV MSRs */ 1540 uint64_t msr_hv_vapic; 1541 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1542 uint64_t msr_hv_runtime; 1543 uint64_t msr_hv_synic_control; 1544 uint64_t msr_hv_synic_evt_page; 1545 uint64_t msr_hv_synic_msg_page; 1546 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1547 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1548 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1549 uint64_t msr_hv_reenlightenment_control; 1550 uint64_t msr_hv_tsc_emulation_control; 1551 uint64_t msr_hv_tsc_emulation_status; 1552 1553 uint64_t msr_rtit_ctrl; 1554 uint64_t msr_rtit_status; 1555 uint64_t msr_rtit_output_base; 1556 uint64_t msr_rtit_output_mask; 1557 uint64_t msr_rtit_cr3_match; 1558 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1559 1560 /* exception/interrupt handling */ 1561 int error_code; 1562 int exception_is_int; 1563 target_ulong exception_next_eip; 1564 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1565 union { 1566 struct CPUBreakpoint *cpu_breakpoint[4]; 1567 struct CPUWatchpoint *cpu_watchpoint[4]; 1568 }; /* break/watchpoints for dr[0..3] */ 1569 int old_exception; /* exception in flight */ 1570 1571 uint64_t vm_vmcb; 1572 uint64_t tsc_offset; 1573 uint64_t intercept; 1574 uint16_t intercept_cr_read; 1575 uint16_t intercept_cr_write; 1576 uint16_t intercept_dr_read; 1577 uint16_t intercept_dr_write; 1578 uint32_t intercept_exceptions; 1579 uint64_t nested_cr3; 1580 uint32_t nested_pg_mode; 1581 uint8_t v_tpr; 1582 1583 /* KVM states, automatically cleared on reset */ 1584 uint8_t nmi_injected; 1585 uint8_t nmi_pending; 1586 1587 uintptr_t retaddr; 1588 1589 /* Fields up to this point are cleared by a CPU reset */ 1590 struct {} end_reset_fields; 1591 1592 /* Fields after this point are preserved across CPU reset. */ 1593 1594 /* processor features (e.g. for CPUID insn) */ 1595 /* Minimum cpuid leaf 7 value */ 1596 uint32_t cpuid_level_func7; 1597 /* Actual cpuid leaf 7 value */ 1598 uint32_t cpuid_min_level_func7; 1599 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1600 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1601 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1602 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1603 /* Actual level/xlevel/xlevel2 value: */ 1604 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1605 uint32_t cpuid_vendor1; 1606 uint32_t cpuid_vendor2; 1607 uint32_t cpuid_vendor3; 1608 uint32_t cpuid_version; 1609 FeatureWordArray features; 1610 /* Features that were explicitly enabled/disabled */ 1611 FeatureWordArray user_features; 1612 uint32_t cpuid_model[12]; 1613 /* Cache information for CPUID. When legacy-cache=on, the cache data 1614 * on each CPUID leaf will be different, because we keep compatibility 1615 * with old QEMU versions. 1616 */ 1617 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1618 1619 /* MTRRs */ 1620 uint64_t mtrr_fixed[11]; 1621 uint64_t mtrr_deftype; 1622 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1623 1624 /* For KVM */ 1625 uint32_t mp_state; 1626 int32_t exception_nr; 1627 int32_t interrupt_injected; 1628 uint8_t soft_interrupt; 1629 uint8_t exception_pending; 1630 uint8_t exception_injected; 1631 uint8_t has_error_code; 1632 uint8_t exception_has_payload; 1633 uint64_t exception_payload; 1634 uint32_t ins_len; 1635 uint32_t sipi_vector; 1636 bool tsc_valid; 1637 int64_t tsc_khz; 1638 int64_t user_tsc_khz; /* for sanity check only */ 1639 uint64_t apic_bus_freq; 1640 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1641 void *xsave_buf; 1642 #endif 1643 #if defined(CONFIG_KVM) 1644 struct kvm_nested_state *nested_state; 1645 #endif 1646 #if defined(CONFIG_HVF) 1647 HVFX86LazyFlags hvf_lflags; 1648 void *hvf_mmio_buf; 1649 #endif 1650 1651 uint64_t mcg_cap; 1652 uint64_t mcg_ctl; 1653 uint64_t mcg_ext_ctl; 1654 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1655 uint64_t xstate_bv; 1656 1657 /* vmstate */ 1658 uint16_t fpus_vmstate; 1659 uint16_t fptag_vmstate; 1660 uint16_t fpregs_format_vmstate; 1661 1662 uint64_t xss; 1663 uint32_t umwait; 1664 1665 TPRAccess tpr_access_type; 1666 1667 unsigned nr_dies; 1668 } CPUX86State; 1669 1670 struct kvm_msrs; 1671 1672 /** 1673 * X86CPU: 1674 * @env: #CPUX86State 1675 * @migratable: If set, only migratable flags will be accepted when "enforce" 1676 * mode is used, and only migratable flags will be included in the "host" 1677 * CPU model. 1678 * 1679 * An x86 CPU. 1680 */ 1681 struct X86CPU { 1682 /*< private >*/ 1683 CPUState parent_obj; 1684 /*< public >*/ 1685 1686 CPUNegativeOffsetState neg; 1687 CPUX86State env; 1688 VMChangeStateEntry *vmsentry; 1689 1690 uint64_t ucode_rev; 1691 1692 uint32_t hyperv_spinlock_attempts; 1693 char *hyperv_vendor; 1694 bool hyperv_synic_kvm_only; 1695 uint64_t hyperv_features; 1696 bool hyperv_passthrough; 1697 OnOffAuto hyperv_no_nonarch_cs; 1698 uint32_t hyperv_vendor_id[3]; 1699 uint32_t hyperv_interface_id[4]; 1700 uint32_t hyperv_version_id[4]; 1701 uint32_t hyperv_limits[3]; 1702 1703 bool check_cpuid; 1704 bool enforce_cpuid; 1705 /* 1706 * Force features to be enabled even if the host doesn't support them. 1707 * This is dangerous and should be done only for testing CPUID 1708 * compatibility. 1709 */ 1710 bool force_features; 1711 bool expose_kvm; 1712 bool expose_tcg; 1713 bool migratable; 1714 bool migrate_smi_count; 1715 bool max_features; /* Enable all supported features automatically */ 1716 uint32_t apic_id; 1717 1718 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1719 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1720 bool vmware_cpuid_freq; 1721 1722 /* if true the CPUID code directly forward host cache leaves to the guest */ 1723 bool cache_info_passthrough; 1724 1725 /* if true the CPUID code directly forwards 1726 * host monitor/mwait leaves to the guest */ 1727 struct { 1728 uint32_t eax; 1729 uint32_t ebx; 1730 uint32_t ecx; 1731 uint32_t edx; 1732 } mwait; 1733 1734 /* Features that were filtered out because of missing host capabilities */ 1735 FeatureWordArray filtered_features; 1736 1737 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1738 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1739 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1740 * capabilities) directly to the guest. 1741 */ 1742 bool enable_pmu; 1743 1744 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1745 * disabled by default to avoid breaking migration between QEMU with 1746 * different LMCE configurations. 1747 */ 1748 bool enable_lmce; 1749 1750 /* Compatibility bits for old machine types. 1751 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1752 * socket share an virtual l3 cache. 1753 */ 1754 bool enable_l3_cache; 1755 1756 /* Compatibility bits for old machine types. 1757 * If true present the old cache topology information 1758 */ 1759 bool legacy_cache; 1760 1761 /* Compatibility bits for old machine types: */ 1762 bool enable_cpuid_0xb; 1763 1764 /* Enable auto level-increase for all CPUID leaves */ 1765 bool full_cpuid_auto_level; 1766 1767 /* Enable auto level-increase for Intel Processor Trace leave */ 1768 bool intel_pt_auto_level; 1769 1770 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1771 bool fill_mtrr_mask; 1772 1773 /* if true override the phys_bits value with a value read from the host */ 1774 bool host_phys_bits; 1775 1776 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1777 uint8_t host_phys_bits_limit; 1778 1779 /* Stop SMI delivery for migration compatibility with old machines */ 1780 bool kvm_no_smi_migration; 1781 1782 /* Number of physical address bits supported */ 1783 uint32_t phys_bits; 1784 1785 /* in order to simplify APIC support, we leave this pointer to the 1786 user */ 1787 struct DeviceState *apic_state; 1788 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1789 Notifier machine_done; 1790 1791 struct kvm_msrs *kvm_msr_buf; 1792 1793 int32_t node_id; /* NUMA node this CPU belongs to */ 1794 int32_t socket_id; 1795 int32_t die_id; 1796 int32_t core_id; 1797 int32_t thread_id; 1798 1799 int32_t hv_max_vps; 1800 }; 1801 1802 1803 #ifndef CONFIG_USER_ONLY 1804 extern const VMStateDescription vmstate_x86_cpu; 1805 #endif 1806 1807 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1808 1809 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1810 int cpuid, void *opaque); 1811 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1812 int cpuid, void *opaque); 1813 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1814 void *opaque); 1815 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1816 void *opaque); 1817 1818 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1819 Error **errp); 1820 1821 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1822 1823 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1824 MemTxAttrs *attrs); 1825 1826 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1827 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1828 1829 void x86_cpu_list(void); 1830 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1831 1832 int cpu_get_pic_interrupt(CPUX86State *s); 1833 /* MSDOS compatibility mode FPU exception support */ 1834 void x86_register_ferr_irq(qemu_irq irq); 1835 void fpu_check_raise_ferr_irq(CPUX86State *s); 1836 void cpu_set_ignne(void); 1837 void cpu_clear_ignne(void); 1838 1839 /* mpx_helper.c */ 1840 void cpu_sync_bndcs_hflags(CPUX86State *env); 1841 1842 /* this function must always be used to load data in the segment 1843 cache: it synchronizes the hflags with the segment cache values */ 1844 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1845 X86Seg seg_reg, unsigned int selector, 1846 target_ulong base, 1847 unsigned int limit, 1848 unsigned int flags) 1849 { 1850 SegmentCache *sc; 1851 unsigned int new_hflags; 1852 1853 sc = &env->segs[seg_reg]; 1854 sc->selector = selector; 1855 sc->base = base; 1856 sc->limit = limit; 1857 sc->flags = flags; 1858 1859 /* update the hidden flags */ 1860 { 1861 if (seg_reg == R_CS) { 1862 #ifdef TARGET_X86_64 1863 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1864 /* long mode */ 1865 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1866 env->hflags &= ~(HF_ADDSEG_MASK); 1867 } else 1868 #endif 1869 { 1870 /* legacy / compatibility case */ 1871 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1872 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1873 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1874 new_hflags; 1875 } 1876 } 1877 if (seg_reg == R_SS) { 1878 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1879 #if HF_CPL_MASK != 3 1880 #error HF_CPL_MASK is hardcoded 1881 #endif 1882 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1883 /* Possibly switch between BNDCFGS and BNDCFGU */ 1884 cpu_sync_bndcs_hflags(env); 1885 } 1886 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1887 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1888 if (env->hflags & HF_CS64_MASK) { 1889 /* zero base assumed for DS, ES and SS in long mode */ 1890 } else if (!(env->cr[0] & CR0_PE_MASK) || 1891 (env->eflags & VM_MASK) || 1892 !(env->hflags & HF_CS32_MASK)) { 1893 /* XXX: try to avoid this test. The problem comes from the 1894 fact that is real mode or vm86 mode we only modify the 1895 'base' and 'selector' fields of the segment cache to go 1896 faster. A solution may be to force addseg to one in 1897 translate-i386.c. */ 1898 new_hflags |= HF_ADDSEG_MASK; 1899 } else { 1900 new_hflags |= ((env->segs[R_DS].base | 1901 env->segs[R_ES].base | 1902 env->segs[R_SS].base) != 0) << 1903 HF_ADDSEG_SHIFT; 1904 } 1905 env->hflags = (env->hflags & 1906 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1907 } 1908 } 1909 1910 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1911 uint8_t sipi_vector) 1912 { 1913 CPUState *cs = CPU(cpu); 1914 CPUX86State *env = &cpu->env; 1915 1916 env->eip = 0; 1917 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1918 sipi_vector << 12, 1919 env->segs[R_CS].limit, 1920 env->segs[R_CS].flags); 1921 cs->halted = 0; 1922 } 1923 1924 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1925 target_ulong *base, unsigned int *limit, 1926 unsigned int *flags); 1927 1928 /* op_helper.c */ 1929 /* used for debug or cpu save/restore */ 1930 1931 /* cpu-exec.c */ 1932 /* the following helpers are only usable in user mode simulation as 1933 they can trigger unexpected exceptions */ 1934 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); 1935 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1936 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1937 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1938 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1939 1940 /* you can call this signal handler from your SIGBUS and SIGSEGV 1941 signal handlers to inform the virtual CPU of exceptions. non zero 1942 is returned if the signal was handled by the virtual CPU. */ 1943 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1944 void *puc); 1945 1946 /* cpu.c */ 1947 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 1948 uint32_t vendor2, uint32_t vendor3); 1949 typedef struct PropValue { 1950 const char *prop, *value; 1951 } PropValue; 1952 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); 1953 1954 /* cpu.c other functions (cpuid) */ 1955 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1956 uint32_t *eax, uint32_t *ebx, 1957 uint32_t *ecx, uint32_t *edx); 1958 void cpu_clear_apic_feature(CPUX86State *env); 1959 void host_cpuid(uint32_t function, uint32_t count, 1960 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1961 1962 /* helper.c */ 1963 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1964 1965 #ifndef CONFIG_USER_ONLY 1966 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1967 { 1968 return !!attrs.secure; 1969 } 1970 1971 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1972 { 1973 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1974 } 1975 1976 /* 1977 * load efer and update the corresponding hflags. XXX: do consistency 1978 * checks with cpuid bits? 1979 */ 1980 void cpu_load_efer(CPUX86State *env, uint64_t val); 1981 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1982 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1983 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1984 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1985 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1986 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1987 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1988 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1989 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1990 #endif 1991 1992 /* will be suppressed */ 1993 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1994 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1995 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1996 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1997 1998 /* hw/pc.c */ 1999 uint64_t cpu_get_tsc(CPUX86State *env); 2000 2001 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 2002 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 2003 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 2004 2005 #ifdef TARGET_X86_64 2006 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 2007 #else 2008 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 2009 #endif 2010 2011 #define cpu_signal_handler cpu_x86_signal_handler 2012 #define cpu_list x86_cpu_list 2013 2014 /* MMU modes definitions */ 2015 #define MMU_KSMAP_IDX 0 2016 #define MMU_USER_IDX 1 2017 #define MMU_KNOSMAP_IDX 2 2018 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 2019 { 2020 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 2021 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 2022 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2023 } 2024 2025 static inline int cpu_mmu_index_kernel(CPUX86State *env) 2026 { 2027 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 2028 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 2029 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2030 } 2031 2032 #define CC_DST (env->cc_dst) 2033 #define CC_SRC (env->cc_src) 2034 #define CC_SRC2 (env->cc_src2) 2035 #define CC_OP (env->cc_op) 2036 2037 typedef CPUX86State CPUArchState; 2038 typedef X86CPU ArchCPU; 2039 2040 #include "exec/cpu-all.h" 2041 #include "svm.h" 2042 2043 #if !defined(CONFIG_USER_ONLY) 2044 #include "hw/i386/apic.h" 2045 #endif 2046 2047 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2048 target_ulong *cs_base, uint32_t *flags) 2049 { 2050 *cs_base = env->segs[R_CS].base; 2051 *pc = *cs_base + env->eip; 2052 *flags = env->hflags | 2053 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2054 } 2055 2056 void do_cpu_init(X86CPU *cpu); 2057 void do_cpu_sipi(X86CPU *cpu); 2058 2059 #define MCE_INJECT_BROADCAST 1 2060 #define MCE_INJECT_UNCOND_AO 2 2061 2062 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2063 uint64_t status, uint64_t mcg_status, uint64_t addr, 2064 uint64_t misc, int flags); 2065 2066 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2067 2068 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2069 { 2070 uint32_t eflags = env->eflags; 2071 if (tcg_enabled()) { 2072 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 2073 } 2074 return eflags; 2075 } 2076 2077 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2078 { 2079 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2080 } 2081 2082 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2083 { 2084 if (env->hflags & HF_SMM_MASK) { 2085 return -1; 2086 } else { 2087 return env->a20_mask; 2088 } 2089 } 2090 2091 static inline bool cpu_has_vmx(CPUX86State *env) 2092 { 2093 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2094 } 2095 2096 static inline bool cpu_has_svm(CPUX86State *env) 2097 { 2098 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2099 } 2100 2101 /* 2102 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2103 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2104 * VMX operation. This is because CR4.VMXE is one of the bits set 2105 * in MSR_IA32_VMX_CR4_FIXED1. 2106 * 2107 * There is one exception to above statement when vCPU enters SMM mode. 2108 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2109 * may also reset CR4.VMXE during execution in SMM mode. 2110 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2111 * and CR4.VMXE is restored to it's original value of being set. 2112 * 2113 * Therefore, when vCPU is not in SMM mode, we can infer whether 2114 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2115 * know for certain. 2116 */ 2117 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2118 { 2119 return cpu_has_vmx(env) && 2120 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2121 } 2122 2123 /* excp_helper.c */ 2124 int get_pg_mode(CPUX86State *env); 2125 2126 /* fpu_helper.c */ 2127 void update_fp_status(CPUX86State *env); 2128 void update_mxcsr_status(CPUX86State *env); 2129 void update_mxcsr_from_sse_status(CPUX86State *env); 2130 2131 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2132 { 2133 env->mxcsr = mxcsr; 2134 if (tcg_enabled()) { 2135 update_mxcsr_status(env); 2136 } 2137 } 2138 2139 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2140 { 2141 env->fpuc = fpuc; 2142 if (tcg_enabled()) { 2143 update_fp_status(env); 2144 } 2145 } 2146 2147 /* mem_helper.c */ 2148 void helper_lock_init(void); 2149 2150 /* svm_helper.c */ 2151 #ifdef CONFIG_USER_ONLY 2152 static inline void 2153 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2154 uint64_t param, uintptr_t retaddr) 2155 { /* no-op */ } 2156 #else 2157 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2158 uint64_t param, uintptr_t retaddr); 2159 #endif 2160 2161 /* apic.c */ 2162 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2163 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2164 TPRAccess access); 2165 2166 /* Special values for X86CPUVersion: */ 2167 2168 /* Resolve to latest CPU version */ 2169 #define CPU_VERSION_LATEST -1 2170 2171 /* 2172 * Resolve to version defined by current machine type. 2173 * See x86_cpu_set_default_version() 2174 */ 2175 #define CPU_VERSION_AUTO -2 2176 2177 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2178 #define CPU_VERSION_LEGACY 0 2179 2180 typedef int X86CPUVersion; 2181 2182 /* 2183 * Set default CPU model version for CPU models having 2184 * version == CPU_VERSION_AUTO. 2185 */ 2186 void x86_cpu_set_default_version(X86CPUVersion version); 2187 2188 #define APIC_DEFAULT_ADDRESS 0xfee00000 2189 #define APIC_SPACE_SIZE 0x100000 2190 2191 /* cpu-dump.c */ 2192 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2193 2194 /* cpu.c */ 2195 bool cpu_is_bsp(X86CPU *cpu); 2196 2197 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 2198 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 2199 void x86_update_hflags(CPUX86State* env); 2200 2201 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2202 { 2203 return !!(cpu->hyperv_features & BIT(feat)); 2204 } 2205 2206 #if defined(TARGET_X86_64) && \ 2207 defined(CONFIG_USER_ONLY) && \ 2208 defined(CONFIG_LINUX) 2209 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2210 #endif 2211 2212 #endif /* I386_CPU_H */ 2213