1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 28 /* The x86 has a strong memory model with some store-after-load re-ordering */ 29 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 30 31 /* Maximum instruction code size */ 32 #define TARGET_MAX_INSN_SIZE 16 33 34 /* support for self modifying code even if the modified instruction is 35 close to the modifying instruction */ 36 #define TARGET_HAS_PRECISE_SMC 37 38 #ifdef TARGET_X86_64 39 #define I386_ELF_MACHINE EM_X86_64 40 #define ELF_MACHINE_UNAME "x86_64" 41 #else 42 #define I386_ELF_MACHINE EM_386 43 #define ELF_MACHINE_UNAME "i686" 44 #endif 45 46 enum { 47 R_EAX = 0, 48 R_ECX = 1, 49 R_EDX = 2, 50 R_EBX = 3, 51 R_ESP = 4, 52 R_EBP = 5, 53 R_ESI = 6, 54 R_EDI = 7, 55 R_R8 = 8, 56 R_R9 = 9, 57 R_R10 = 10, 58 R_R11 = 11, 59 R_R12 = 12, 60 R_R13 = 13, 61 R_R14 = 14, 62 R_R15 = 15, 63 64 R_AL = 0, 65 R_CL = 1, 66 R_DL = 2, 67 R_BL = 3, 68 R_AH = 4, 69 R_CH = 5, 70 R_DH = 6, 71 R_BH = 7, 72 }; 73 74 typedef enum X86Seg { 75 R_ES = 0, 76 R_CS = 1, 77 R_SS = 2, 78 R_DS = 3, 79 R_FS = 4, 80 R_GS = 5, 81 R_LDTR = 6, 82 R_TR = 7, 83 } X86Seg; 84 85 /* segment descriptor fields */ 86 #define DESC_G_SHIFT 23 87 #define DESC_G_MASK (1 << DESC_G_SHIFT) 88 #define DESC_B_SHIFT 22 89 #define DESC_B_MASK (1 << DESC_B_SHIFT) 90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91 #define DESC_L_MASK (1 << DESC_L_SHIFT) 92 #define DESC_AVL_SHIFT 20 93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94 #define DESC_P_SHIFT 15 95 #define DESC_P_MASK (1 << DESC_P_SHIFT) 96 #define DESC_DPL_SHIFT 13 97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98 #define DESC_S_SHIFT 12 99 #define DESC_S_MASK (1 << DESC_S_SHIFT) 100 #define DESC_TYPE_SHIFT 8 101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102 #define DESC_A_MASK (1 << 8) 103 104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105 #define DESC_C_MASK (1 << 10) /* code: conforming */ 106 #define DESC_R_MASK (1 << 9) /* code: readable */ 107 108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109 #define DESC_W_MASK (1 << 9) /* data: writable */ 110 111 #define DESC_TSS_BUSY_MASK (1 << 9) 112 113 /* eflags masks */ 114 #define CC_C 0x0001 115 #define CC_P 0x0004 116 #define CC_A 0x0010 117 #define CC_Z 0x0040 118 #define CC_S 0x0080 119 #define CC_O 0x0800 120 121 #define TF_SHIFT 8 122 #define IOPL_SHIFT 12 123 #define VM_SHIFT 17 124 125 #define TF_MASK 0x00000100 126 #define IF_MASK 0x00000200 127 #define DF_MASK 0x00000400 128 #define IOPL_MASK 0x00003000 129 #define NT_MASK 0x00004000 130 #define RF_MASK 0x00010000 131 #define VM_MASK 0x00020000 132 #define AC_MASK 0x00040000 133 #define VIF_MASK 0x00080000 134 #define VIP_MASK 0x00100000 135 #define ID_MASK 0x00200000 136 137 /* hidden flags - used internally by qemu to represent additional cpu 138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140 positions to ease oring with eflags. */ 141 /* current cpl */ 142 #define HF_CPL_SHIFT 0 143 /* true if hardware interrupts must be disabled for next instruction */ 144 #define HF_INHIBIT_IRQ_SHIFT 3 145 /* 16 or 32 segments */ 146 #define HF_CS32_SHIFT 4 147 #define HF_SS32_SHIFT 5 148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149 #define HF_ADDSEG_SHIFT 6 150 /* copy of CR0.PE (protected mode) */ 151 #define HF_PE_SHIFT 7 152 #define HF_TF_SHIFT 8 /* must be same as eflags */ 153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154 #define HF_EM_SHIFT 10 155 #define HF_TS_SHIFT 11 156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159 #define HF_RF_SHIFT 16 /* must be same as eflags */ 160 #define HF_VM_SHIFT 17 /* must be same as eflags */ 161 #define HF_AC_SHIFT 18 /* must be same as eflags */ 162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170 171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176 #define HF_PE_MASK (1 << HF_PE_SHIFT) 177 #define HF_TF_MASK (1 << HF_TF_SHIFT) 178 #define HF_MP_MASK (1 << HF_MP_SHIFT) 179 #define HF_EM_MASK (1 << HF_EM_SHIFT) 180 #define HF_TS_MASK (1 << HF_TS_SHIFT) 181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184 #define HF_RF_MASK (1 << HF_RF_SHIFT) 185 #define HF_VM_MASK (1 << HF_VM_SHIFT) 186 #define HF_AC_MASK (1 << HF_AC_SHIFT) 187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195 196 /* hflags2 */ 197 198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205 206 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 207 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 208 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 209 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 210 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 211 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 212 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 213 214 #define CR0_PE_SHIFT 0 215 #define CR0_MP_SHIFT 1 216 217 #define CR0_PE_MASK (1U << 0) 218 #define CR0_MP_MASK (1U << 1) 219 #define CR0_EM_MASK (1U << 2) 220 #define CR0_TS_MASK (1U << 3) 221 #define CR0_ET_MASK (1U << 4) 222 #define CR0_NE_MASK (1U << 5) 223 #define CR0_WP_MASK (1U << 16) 224 #define CR0_AM_MASK (1U << 18) 225 #define CR0_PG_MASK (1U << 31) 226 227 #define CR4_VME_MASK (1U << 0) 228 #define CR4_PVI_MASK (1U << 1) 229 #define CR4_TSD_MASK (1U << 2) 230 #define CR4_DE_MASK (1U << 3) 231 #define CR4_PSE_MASK (1U << 4) 232 #define CR4_PAE_MASK (1U << 5) 233 #define CR4_MCE_MASK (1U << 6) 234 #define CR4_PGE_MASK (1U << 7) 235 #define CR4_PCE_MASK (1U << 8) 236 #define CR4_OSFXSR_SHIFT 9 237 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 238 #define CR4_OSXMMEXCPT_MASK (1U << 10) 239 #define CR4_LA57_MASK (1U << 12) 240 #define CR4_VMXE_MASK (1U << 13) 241 #define CR4_SMXE_MASK (1U << 14) 242 #define CR4_FSGSBASE_MASK (1U << 16) 243 #define CR4_PCIDE_MASK (1U << 17) 244 #define CR4_OSXSAVE_MASK (1U << 18) 245 #define CR4_SMEP_MASK (1U << 20) 246 #define CR4_SMAP_MASK (1U << 21) 247 #define CR4_PKE_MASK (1U << 22) 248 249 #define DR6_BD (1 << 13) 250 #define DR6_BS (1 << 14) 251 #define DR6_BT (1 << 15) 252 #define DR6_FIXED_1 0xffff0ff0 253 254 #define DR7_GD (1 << 13) 255 #define DR7_TYPE_SHIFT 16 256 #define DR7_LEN_SHIFT 18 257 #define DR7_FIXED_1 0x00000400 258 #define DR7_GLOBAL_BP_MASK 0xaa 259 #define DR7_LOCAL_BP_MASK 0x55 260 #define DR7_MAX_BP 4 261 #define DR7_TYPE_BP_INST 0x0 262 #define DR7_TYPE_DATA_WR 0x1 263 #define DR7_TYPE_IO_RW 0x2 264 #define DR7_TYPE_DATA_RW 0x3 265 266 #define PG_PRESENT_BIT 0 267 #define PG_RW_BIT 1 268 #define PG_USER_BIT 2 269 #define PG_PWT_BIT 3 270 #define PG_PCD_BIT 4 271 #define PG_ACCESSED_BIT 5 272 #define PG_DIRTY_BIT 6 273 #define PG_PSE_BIT 7 274 #define PG_GLOBAL_BIT 8 275 #define PG_PSE_PAT_BIT 12 276 #define PG_PKRU_BIT 59 277 #define PG_NX_BIT 63 278 279 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 280 #define PG_RW_MASK (1 << PG_RW_BIT) 281 #define PG_USER_MASK (1 << PG_USER_BIT) 282 #define PG_PWT_MASK (1 << PG_PWT_BIT) 283 #define PG_PCD_MASK (1 << PG_PCD_BIT) 284 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 285 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 286 #define PG_PSE_MASK (1 << PG_PSE_BIT) 287 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 288 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 289 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 290 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 291 #define PG_HI_USER_MASK 0x7ff0000000000000LL 292 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 293 #define PG_NX_MASK (1ULL << PG_NX_BIT) 294 295 #define PG_ERROR_W_BIT 1 296 297 #define PG_ERROR_P_MASK 0x01 298 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 299 #define PG_ERROR_U_MASK 0x04 300 #define PG_ERROR_RSVD_MASK 0x08 301 #define PG_ERROR_I_D_MASK 0x10 302 #define PG_ERROR_PK_MASK 0x20 303 304 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 305 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 306 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 307 308 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 309 #define MCE_BANKS_DEF 10 310 311 #define MCG_CAP_BANKS_MASK 0xff 312 313 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 314 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 315 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 316 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 317 318 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 319 320 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 321 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 322 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 323 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 324 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 325 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 326 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 327 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 328 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 329 330 /* MISC register defines */ 331 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 332 #define MCM_ADDR_LINEAR 1 /* linear address */ 333 #define MCM_ADDR_PHYS 2 /* physical address */ 334 #define MCM_ADDR_MEM 3 /* memory address */ 335 #define MCM_ADDR_GENERIC 7 /* generic */ 336 337 #define MSR_IA32_TSC 0x10 338 #define MSR_IA32_APICBASE 0x1b 339 #define MSR_IA32_APICBASE_BSP (1<<8) 340 #define MSR_IA32_APICBASE_ENABLE (1<<11) 341 #define MSR_IA32_APICBASE_EXTD (1 << 10) 342 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 343 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 344 #define MSR_TSC_ADJUST 0x0000003b 345 #define MSR_IA32_SPEC_CTRL 0x48 346 #define MSR_VIRT_SSBD 0xc001011f 347 #define MSR_IA32_PRED_CMD 0x49 348 #define MSR_IA32_CORE_CAPABILITY 0xcf 349 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 350 #define MSR_IA32_TSCDEADLINE 0x6e0 351 352 #define FEATURE_CONTROL_LOCKED (1<<0) 353 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 354 #define FEATURE_CONTROL_LMCE (1<<20) 355 356 #define MSR_P6_PERFCTR0 0xc1 357 358 #define MSR_IA32_SMBASE 0x9e 359 #define MSR_SMI_COUNT 0x34 360 #define MSR_MTRRcap 0xfe 361 #define MSR_MTRRcap_VCNT 8 362 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 363 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 364 365 #define MSR_IA32_SYSENTER_CS 0x174 366 #define MSR_IA32_SYSENTER_ESP 0x175 367 #define MSR_IA32_SYSENTER_EIP 0x176 368 369 #define MSR_MCG_CAP 0x179 370 #define MSR_MCG_STATUS 0x17a 371 #define MSR_MCG_CTL 0x17b 372 #define MSR_MCG_EXT_CTL 0x4d0 373 374 #define MSR_P6_EVNTSEL0 0x186 375 376 #define MSR_IA32_PERF_STATUS 0x198 377 378 #define MSR_IA32_MISC_ENABLE 0x1a0 379 /* Indicates good rep/movs microcode on some processors: */ 380 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 381 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 382 383 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 384 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 385 386 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 387 388 #define MSR_MTRRfix64K_00000 0x250 389 #define MSR_MTRRfix16K_80000 0x258 390 #define MSR_MTRRfix16K_A0000 0x259 391 #define MSR_MTRRfix4K_C0000 0x268 392 #define MSR_MTRRfix4K_C8000 0x269 393 #define MSR_MTRRfix4K_D0000 0x26a 394 #define MSR_MTRRfix4K_D8000 0x26b 395 #define MSR_MTRRfix4K_E0000 0x26c 396 #define MSR_MTRRfix4K_E8000 0x26d 397 #define MSR_MTRRfix4K_F0000 0x26e 398 #define MSR_MTRRfix4K_F8000 0x26f 399 400 #define MSR_PAT 0x277 401 402 #define MSR_MTRRdefType 0x2ff 403 404 #define MSR_CORE_PERF_FIXED_CTR0 0x309 405 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 406 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 407 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 408 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 409 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 410 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 411 412 #define MSR_MC0_CTL 0x400 413 #define MSR_MC0_STATUS 0x401 414 #define MSR_MC0_ADDR 0x402 415 #define MSR_MC0_MISC 0x403 416 417 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 418 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 419 #define MSR_IA32_RTIT_CTL 0x570 420 #define MSR_IA32_RTIT_STATUS 0x571 421 #define MSR_IA32_RTIT_CR3_MATCH 0x572 422 #define MSR_IA32_RTIT_ADDR0_A 0x580 423 #define MSR_IA32_RTIT_ADDR0_B 0x581 424 #define MSR_IA32_RTIT_ADDR1_A 0x582 425 #define MSR_IA32_RTIT_ADDR1_B 0x583 426 #define MSR_IA32_RTIT_ADDR2_A 0x584 427 #define MSR_IA32_RTIT_ADDR2_B 0x585 428 #define MSR_IA32_RTIT_ADDR3_A 0x586 429 #define MSR_IA32_RTIT_ADDR3_B 0x587 430 #define MAX_RTIT_ADDRS 8 431 432 #define MSR_EFER 0xc0000080 433 434 #define MSR_EFER_SCE (1 << 0) 435 #define MSR_EFER_LME (1 << 8) 436 #define MSR_EFER_LMA (1 << 10) 437 #define MSR_EFER_NXE (1 << 11) 438 #define MSR_EFER_SVME (1 << 12) 439 #define MSR_EFER_FFXSR (1 << 14) 440 441 #define MSR_STAR 0xc0000081 442 #define MSR_LSTAR 0xc0000082 443 #define MSR_CSTAR 0xc0000083 444 #define MSR_FMASK 0xc0000084 445 #define MSR_FSBASE 0xc0000100 446 #define MSR_GSBASE 0xc0000101 447 #define MSR_KERNELGSBASE 0xc0000102 448 #define MSR_TSC_AUX 0xc0000103 449 450 #define MSR_VM_HSAVE_PA 0xc0010117 451 452 #define MSR_IA32_BNDCFGS 0x00000d90 453 #define MSR_IA32_XSS 0x00000da0 454 455 #define MSR_IA32_VMX_BASIC 0x00000480 456 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 457 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 458 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 459 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 460 #define MSR_IA32_VMX_MISC 0x00000485 461 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 462 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 463 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 464 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 465 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 466 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 467 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 468 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 469 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 470 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 471 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 472 #define MSR_IA32_VMX_VMFUNC 0x00000491 473 474 #define XSTATE_FP_BIT 0 475 #define XSTATE_SSE_BIT 1 476 #define XSTATE_YMM_BIT 2 477 #define XSTATE_BNDREGS_BIT 3 478 #define XSTATE_BNDCSR_BIT 4 479 #define XSTATE_OPMASK_BIT 5 480 #define XSTATE_ZMM_Hi256_BIT 6 481 #define XSTATE_Hi16_ZMM_BIT 7 482 #define XSTATE_PKRU_BIT 9 483 484 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 485 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 486 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 487 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 488 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 489 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 490 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 491 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 492 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 493 494 /* CPUID feature words */ 495 typedef enum FeatureWord { 496 FEAT_1_EDX, /* CPUID[1].EDX */ 497 FEAT_1_ECX, /* CPUID[1].ECX */ 498 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 499 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 500 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 501 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 502 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 503 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 504 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 505 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 506 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 507 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 508 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 509 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 510 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 511 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 512 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ 513 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ 514 FEAT_SVM, /* CPUID[8000_000A].EDX */ 515 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 516 FEAT_6_EAX, /* CPUID[6].EAX */ 517 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 518 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 519 FEAT_ARCH_CAPABILITIES, 520 FEAT_CORE_CAPABILITY, 521 FEAT_VMX_PROCBASED_CTLS, 522 FEAT_VMX_SECONDARY_CTLS, 523 FEAT_VMX_PINBASED_CTLS, 524 FEAT_VMX_EXIT_CTLS, 525 FEAT_VMX_ENTRY_CTLS, 526 FEAT_VMX_MISC, 527 FEAT_VMX_EPT_VPID_CAPS, 528 FEAT_VMX_BASIC, 529 FEAT_VMX_VMFUNC, 530 FEATURE_WORDS, 531 } FeatureWord; 532 533 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 534 535 /* cpuid_features bits */ 536 #define CPUID_FP87 (1U << 0) 537 #define CPUID_VME (1U << 1) 538 #define CPUID_DE (1U << 2) 539 #define CPUID_PSE (1U << 3) 540 #define CPUID_TSC (1U << 4) 541 #define CPUID_MSR (1U << 5) 542 #define CPUID_PAE (1U << 6) 543 #define CPUID_MCE (1U << 7) 544 #define CPUID_CX8 (1U << 8) 545 #define CPUID_APIC (1U << 9) 546 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 547 #define CPUID_MTRR (1U << 12) 548 #define CPUID_PGE (1U << 13) 549 #define CPUID_MCA (1U << 14) 550 #define CPUID_CMOV (1U << 15) 551 #define CPUID_PAT (1U << 16) 552 #define CPUID_PSE36 (1U << 17) 553 #define CPUID_PN (1U << 18) 554 #define CPUID_CLFLUSH (1U << 19) 555 #define CPUID_DTS (1U << 21) 556 #define CPUID_ACPI (1U << 22) 557 #define CPUID_MMX (1U << 23) 558 #define CPUID_FXSR (1U << 24) 559 #define CPUID_SSE (1U << 25) 560 #define CPUID_SSE2 (1U << 26) 561 #define CPUID_SS (1U << 27) 562 #define CPUID_HT (1U << 28) 563 #define CPUID_TM (1U << 29) 564 #define CPUID_IA64 (1U << 30) 565 #define CPUID_PBE (1U << 31) 566 567 #define CPUID_EXT_SSE3 (1U << 0) 568 #define CPUID_EXT_PCLMULQDQ (1U << 1) 569 #define CPUID_EXT_DTES64 (1U << 2) 570 #define CPUID_EXT_MONITOR (1U << 3) 571 #define CPUID_EXT_DSCPL (1U << 4) 572 #define CPUID_EXT_VMX (1U << 5) 573 #define CPUID_EXT_SMX (1U << 6) 574 #define CPUID_EXT_EST (1U << 7) 575 #define CPUID_EXT_TM2 (1U << 8) 576 #define CPUID_EXT_SSSE3 (1U << 9) 577 #define CPUID_EXT_CID (1U << 10) 578 #define CPUID_EXT_FMA (1U << 12) 579 #define CPUID_EXT_CX16 (1U << 13) 580 #define CPUID_EXT_XTPR (1U << 14) 581 #define CPUID_EXT_PDCM (1U << 15) 582 #define CPUID_EXT_PCID (1U << 17) 583 #define CPUID_EXT_DCA (1U << 18) 584 #define CPUID_EXT_SSE41 (1U << 19) 585 #define CPUID_EXT_SSE42 (1U << 20) 586 #define CPUID_EXT_X2APIC (1U << 21) 587 #define CPUID_EXT_MOVBE (1U << 22) 588 #define CPUID_EXT_POPCNT (1U << 23) 589 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 590 #define CPUID_EXT_AES (1U << 25) 591 #define CPUID_EXT_XSAVE (1U << 26) 592 #define CPUID_EXT_OSXSAVE (1U << 27) 593 #define CPUID_EXT_AVX (1U << 28) 594 #define CPUID_EXT_F16C (1U << 29) 595 #define CPUID_EXT_RDRAND (1U << 30) 596 #define CPUID_EXT_HYPERVISOR (1U << 31) 597 598 #define CPUID_EXT2_FPU (1U << 0) 599 #define CPUID_EXT2_VME (1U << 1) 600 #define CPUID_EXT2_DE (1U << 2) 601 #define CPUID_EXT2_PSE (1U << 3) 602 #define CPUID_EXT2_TSC (1U << 4) 603 #define CPUID_EXT2_MSR (1U << 5) 604 #define CPUID_EXT2_PAE (1U << 6) 605 #define CPUID_EXT2_MCE (1U << 7) 606 #define CPUID_EXT2_CX8 (1U << 8) 607 #define CPUID_EXT2_APIC (1U << 9) 608 #define CPUID_EXT2_SYSCALL (1U << 11) 609 #define CPUID_EXT2_MTRR (1U << 12) 610 #define CPUID_EXT2_PGE (1U << 13) 611 #define CPUID_EXT2_MCA (1U << 14) 612 #define CPUID_EXT2_CMOV (1U << 15) 613 #define CPUID_EXT2_PAT (1U << 16) 614 #define CPUID_EXT2_PSE36 (1U << 17) 615 #define CPUID_EXT2_MP (1U << 19) 616 #define CPUID_EXT2_NX (1U << 20) 617 #define CPUID_EXT2_MMXEXT (1U << 22) 618 #define CPUID_EXT2_MMX (1U << 23) 619 #define CPUID_EXT2_FXSR (1U << 24) 620 #define CPUID_EXT2_FFXSR (1U << 25) 621 #define CPUID_EXT2_PDPE1GB (1U << 26) 622 #define CPUID_EXT2_RDTSCP (1U << 27) 623 #define CPUID_EXT2_LM (1U << 29) 624 #define CPUID_EXT2_3DNOWEXT (1U << 30) 625 #define CPUID_EXT2_3DNOW (1U << 31) 626 627 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 628 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 629 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 630 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 631 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 632 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 633 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 634 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 635 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 636 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 637 638 #define CPUID_EXT3_LAHF_LM (1U << 0) 639 #define CPUID_EXT3_CMP_LEG (1U << 1) 640 #define CPUID_EXT3_SVM (1U << 2) 641 #define CPUID_EXT3_EXTAPIC (1U << 3) 642 #define CPUID_EXT3_CR8LEG (1U << 4) 643 #define CPUID_EXT3_ABM (1U << 5) 644 #define CPUID_EXT3_SSE4A (1U << 6) 645 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 646 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 647 #define CPUID_EXT3_OSVW (1U << 9) 648 #define CPUID_EXT3_IBS (1U << 10) 649 #define CPUID_EXT3_XOP (1U << 11) 650 #define CPUID_EXT3_SKINIT (1U << 12) 651 #define CPUID_EXT3_WDT (1U << 13) 652 #define CPUID_EXT3_LWP (1U << 15) 653 #define CPUID_EXT3_FMA4 (1U << 16) 654 #define CPUID_EXT3_TCE (1U << 17) 655 #define CPUID_EXT3_NODEID (1U << 19) 656 #define CPUID_EXT3_TBM (1U << 21) 657 #define CPUID_EXT3_TOPOEXT (1U << 22) 658 #define CPUID_EXT3_PERFCORE (1U << 23) 659 #define CPUID_EXT3_PERFNB (1U << 24) 660 661 #define CPUID_SVM_NPT (1U << 0) 662 #define CPUID_SVM_LBRV (1U << 1) 663 #define CPUID_SVM_SVMLOCK (1U << 2) 664 #define CPUID_SVM_NRIPSAVE (1U << 3) 665 #define CPUID_SVM_TSCSCALE (1U << 4) 666 #define CPUID_SVM_VMCBCLEAN (1U << 5) 667 #define CPUID_SVM_FLUSHASID (1U << 6) 668 #define CPUID_SVM_DECODEASSIST (1U << 7) 669 #define CPUID_SVM_PAUSEFILTER (1U << 10) 670 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 671 672 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 673 #define CPUID_7_0_EBX_BMI1 (1U << 3) 674 #define CPUID_7_0_EBX_HLE (1U << 4) 675 #define CPUID_7_0_EBX_AVX2 (1U << 5) 676 #define CPUID_7_0_EBX_SMEP (1U << 7) 677 #define CPUID_7_0_EBX_BMI2 (1U << 8) 678 #define CPUID_7_0_EBX_ERMS (1U << 9) 679 #define CPUID_7_0_EBX_INVPCID (1U << 10) 680 #define CPUID_7_0_EBX_RTM (1U << 11) 681 #define CPUID_7_0_EBX_MPX (1U << 14) 682 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 683 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 684 #define CPUID_7_0_EBX_RDSEED (1U << 18) 685 #define CPUID_7_0_EBX_ADX (1U << 19) 686 #define CPUID_7_0_EBX_SMAP (1U << 20) 687 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 688 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 689 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 690 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 691 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */ 692 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 693 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 694 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 695 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 696 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 697 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 698 699 #define CPUID_7_0_ECX_AVX512BMI (1U << 1) 700 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 701 #define CPUID_7_0_ECX_UMIP (1U << 2) 702 #define CPUID_7_0_ECX_PKU (1U << 3) 703 #define CPUID_7_0_ECX_OSPKE (1U << 4) 704 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ 705 #define CPUID_7_0_ECX_GFNI (1U << 8) 706 #define CPUID_7_0_ECX_VAES (1U << 9) 707 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 708 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 709 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 710 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 711 #define CPUID_7_0_ECX_LA57 (1U << 16) 712 #define CPUID_7_0_ECX_RDPID (1U << 22) 713 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ 714 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ 715 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ 716 717 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 718 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 719 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ 720 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ 721 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/ 722 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ 723 724 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */ 725 726 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* CLZERO instruction */ 727 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */ 728 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and 729 do not invalidate cache */ 730 #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ 731 732 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 733 #define CPUID_XSAVE_XSAVEC (1U << 1) 734 #define CPUID_XSAVE_XGETBV1 (1U << 2) 735 #define CPUID_XSAVE_XSAVES (1U << 3) 736 737 #define CPUID_6_EAX_ARAT (1U << 2) 738 739 /* CPUID[0x80000007].EDX flags: */ 740 #define CPUID_APM_INVTSC (1U << 8) 741 742 #define CPUID_VENDOR_SZ 12 743 744 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 745 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 746 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 747 #define CPUID_VENDOR_INTEL "GenuineIntel" 748 749 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 750 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 751 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 752 #define CPUID_VENDOR_AMD "AuthenticAMD" 753 754 #define CPUID_VENDOR_VIA "CentaurHauls" 755 756 #define CPUID_VENDOR_HYGON "HygonGenuine" 757 758 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 759 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 760 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 761 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 762 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 763 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 764 765 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 766 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 767 768 /* CPUID[0xB].ECX level types */ 769 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 770 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 771 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 772 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 773 774 /* MSR Feature Bits */ 775 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 776 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 777 #define MSR_ARCH_CAP_RSBA (1U << 2) 778 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 779 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 780 781 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 782 783 /* VMX MSR features */ 784 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 785 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 786 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 787 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 788 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 789 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 790 791 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 792 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 793 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 794 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 795 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 796 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 797 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 798 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 799 800 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 801 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 802 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 803 #define MSR_VMX_EPT_UC (1ULL << 8) 804 #define MSR_VMX_EPT_WB (1ULL << 14) 805 #define MSR_VMX_EPT_2MB (1ULL << 16) 806 #define MSR_VMX_EPT_1GB (1ULL << 17) 807 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 808 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 809 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 810 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 811 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 812 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 813 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 814 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 815 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 816 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 817 818 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 819 820 821 /* VMX controls */ 822 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 823 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 824 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 825 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 826 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 827 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 828 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 829 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 830 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 831 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 832 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 833 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 834 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 835 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 836 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 837 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 838 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 839 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 840 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 841 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 842 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 843 844 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 845 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 846 #define VMX_SECONDARY_EXEC_DESC 0x00000004 847 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 848 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 849 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 850 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 851 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 852 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 853 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 854 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 855 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 856 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 857 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 858 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 859 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 860 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 861 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 862 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 863 864 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 865 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 866 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 867 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 868 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 869 870 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 871 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 872 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 873 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 874 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 875 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 876 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 877 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 878 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 879 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 880 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 881 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 882 883 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 884 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 885 #define VMX_VM_ENTRY_SMM 0x00000400 886 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 887 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 888 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 889 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 890 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 891 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 892 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 893 894 /* Supported Hyper-V Enlightenments */ 895 #define HYPERV_FEAT_RELAXED 0 896 #define HYPERV_FEAT_VAPIC 1 897 #define HYPERV_FEAT_TIME 2 898 #define HYPERV_FEAT_CRASH 3 899 #define HYPERV_FEAT_RESET 4 900 #define HYPERV_FEAT_VPINDEX 5 901 #define HYPERV_FEAT_RUNTIME 6 902 #define HYPERV_FEAT_SYNIC 7 903 #define HYPERV_FEAT_STIMER 8 904 #define HYPERV_FEAT_FREQUENCIES 9 905 #define HYPERV_FEAT_REENLIGHTENMENT 10 906 #define HYPERV_FEAT_TLBFLUSH 11 907 #define HYPERV_FEAT_EVMCS 12 908 #define HYPERV_FEAT_IPI 13 909 #define HYPERV_FEAT_STIMER_DIRECT 14 910 911 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 912 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 913 #endif 914 915 #define EXCP00_DIVZ 0 916 #define EXCP01_DB 1 917 #define EXCP02_NMI 2 918 #define EXCP03_INT3 3 919 #define EXCP04_INTO 4 920 #define EXCP05_BOUND 5 921 #define EXCP06_ILLOP 6 922 #define EXCP07_PREX 7 923 #define EXCP08_DBLE 8 924 #define EXCP09_XERR 9 925 #define EXCP0A_TSS 10 926 #define EXCP0B_NOSEG 11 927 #define EXCP0C_STACK 12 928 #define EXCP0D_GPF 13 929 #define EXCP0E_PAGE 14 930 #define EXCP10_COPR 16 931 #define EXCP11_ALGN 17 932 #define EXCP12_MCHK 18 933 934 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 935 for syscall instruction */ 936 #define EXCP_VMEXIT 0x100 937 938 /* i386-specific interrupt pending bits. */ 939 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 940 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 941 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 942 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 943 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 944 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 945 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 946 947 /* Use a clearer name for this. */ 948 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 949 950 /* Instead of computing the condition codes after each x86 instruction, 951 * QEMU just stores one operand (called CC_SRC), the result 952 * (called CC_DST) and the type of operation (called CC_OP). When the 953 * condition codes are needed, the condition codes can be calculated 954 * using this information. Condition codes are not generated if they 955 * are only needed for conditional branches. 956 */ 957 typedef enum { 958 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 959 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 960 961 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 962 CC_OP_MULW, 963 CC_OP_MULL, 964 CC_OP_MULQ, 965 966 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 967 CC_OP_ADDW, 968 CC_OP_ADDL, 969 CC_OP_ADDQ, 970 971 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 972 CC_OP_ADCW, 973 CC_OP_ADCL, 974 CC_OP_ADCQ, 975 976 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 977 CC_OP_SUBW, 978 CC_OP_SUBL, 979 CC_OP_SUBQ, 980 981 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 982 CC_OP_SBBW, 983 CC_OP_SBBL, 984 CC_OP_SBBQ, 985 986 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 987 CC_OP_LOGICW, 988 CC_OP_LOGICL, 989 CC_OP_LOGICQ, 990 991 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 992 CC_OP_INCW, 993 CC_OP_INCL, 994 CC_OP_INCQ, 995 996 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 997 CC_OP_DECW, 998 CC_OP_DECL, 999 CC_OP_DECQ, 1000 1001 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1002 CC_OP_SHLW, 1003 CC_OP_SHLL, 1004 CC_OP_SHLQ, 1005 1006 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1007 CC_OP_SARW, 1008 CC_OP_SARL, 1009 CC_OP_SARQ, 1010 1011 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1012 CC_OP_BMILGW, 1013 CC_OP_BMILGL, 1014 CC_OP_BMILGQ, 1015 1016 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1017 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1018 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1019 1020 CC_OP_CLR, /* Z set, all other flags clear. */ 1021 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1022 1023 CC_OP_NB, 1024 } CCOp; 1025 1026 typedef struct SegmentCache { 1027 uint32_t selector; 1028 target_ulong base; 1029 uint32_t limit; 1030 uint32_t flags; 1031 } SegmentCache; 1032 1033 #define MMREG_UNION(n, bits) \ 1034 union n { \ 1035 uint8_t _b_##n[(bits)/8]; \ 1036 uint16_t _w_##n[(bits)/16]; \ 1037 uint32_t _l_##n[(bits)/32]; \ 1038 uint64_t _q_##n[(bits)/64]; \ 1039 float32 _s_##n[(bits)/32]; \ 1040 float64 _d_##n[(bits)/64]; \ 1041 } 1042 1043 typedef union { 1044 uint8_t _b[16]; 1045 uint16_t _w[8]; 1046 uint32_t _l[4]; 1047 uint64_t _q[2]; 1048 } XMMReg; 1049 1050 typedef union { 1051 uint8_t _b[32]; 1052 uint16_t _w[16]; 1053 uint32_t _l[8]; 1054 uint64_t _q[4]; 1055 } YMMReg; 1056 1057 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1058 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1059 1060 typedef struct BNDReg { 1061 uint64_t lb; 1062 uint64_t ub; 1063 } BNDReg; 1064 1065 typedef struct BNDCSReg { 1066 uint64_t cfgu; 1067 uint64_t sts; 1068 } BNDCSReg; 1069 1070 #define BNDCFG_ENABLE 1ULL 1071 #define BNDCFG_BNDPRESERVE 2ULL 1072 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1073 1074 #ifdef HOST_WORDS_BIGENDIAN 1075 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1076 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1077 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1078 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1079 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1080 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1081 1082 #define MMX_B(n) _b_MMXReg[7 - (n)] 1083 #define MMX_W(n) _w_MMXReg[3 - (n)] 1084 #define MMX_L(n) _l_MMXReg[1 - (n)] 1085 #define MMX_S(n) _s_MMXReg[1 - (n)] 1086 #else 1087 #define ZMM_B(n) _b_ZMMReg[n] 1088 #define ZMM_W(n) _w_ZMMReg[n] 1089 #define ZMM_L(n) _l_ZMMReg[n] 1090 #define ZMM_S(n) _s_ZMMReg[n] 1091 #define ZMM_Q(n) _q_ZMMReg[n] 1092 #define ZMM_D(n) _d_ZMMReg[n] 1093 1094 #define MMX_B(n) _b_MMXReg[n] 1095 #define MMX_W(n) _w_MMXReg[n] 1096 #define MMX_L(n) _l_MMXReg[n] 1097 #define MMX_S(n) _s_MMXReg[n] 1098 #endif 1099 #define MMX_Q(n) _q_MMXReg[n] 1100 1101 typedef union { 1102 floatx80 d __attribute__((aligned(16))); 1103 MMXReg mmx; 1104 } FPReg; 1105 1106 typedef struct { 1107 uint64_t base; 1108 uint64_t mask; 1109 } MTRRVar; 1110 1111 #define CPU_NB_REGS64 16 1112 #define CPU_NB_REGS32 8 1113 1114 #ifdef TARGET_X86_64 1115 #define CPU_NB_REGS CPU_NB_REGS64 1116 #else 1117 #define CPU_NB_REGS CPU_NB_REGS32 1118 #endif 1119 1120 #define MAX_FIXED_COUNTERS 3 1121 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1122 1123 #define TARGET_INSN_START_EXTRA_WORDS 1 1124 1125 #define NB_OPMASK_REGS 8 1126 1127 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1128 * that APIC ID hasn't been set yet 1129 */ 1130 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1131 1132 typedef union X86LegacyXSaveArea { 1133 struct { 1134 uint16_t fcw; 1135 uint16_t fsw; 1136 uint8_t ftw; 1137 uint8_t reserved; 1138 uint16_t fpop; 1139 uint64_t fpip; 1140 uint64_t fpdp; 1141 uint32_t mxcsr; 1142 uint32_t mxcsr_mask; 1143 FPReg fpregs[8]; 1144 uint8_t xmm_regs[16][16]; 1145 }; 1146 uint8_t data[512]; 1147 } X86LegacyXSaveArea; 1148 1149 typedef struct X86XSaveHeader { 1150 uint64_t xstate_bv; 1151 uint64_t xcomp_bv; 1152 uint64_t reserve0; 1153 uint8_t reserved[40]; 1154 } X86XSaveHeader; 1155 1156 /* Ext. save area 2: AVX State */ 1157 typedef struct XSaveAVX { 1158 uint8_t ymmh[16][16]; 1159 } XSaveAVX; 1160 1161 /* Ext. save area 3: BNDREG */ 1162 typedef struct XSaveBNDREG { 1163 BNDReg bnd_regs[4]; 1164 } XSaveBNDREG; 1165 1166 /* Ext. save area 4: BNDCSR */ 1167 typedef union XSaveBNDCSR { 1168 BNDCSReg bndcsr; 1169 uint8_t data[64]; 1170 } XSaveBNDCSR; 1171 1172 /* Ext. save area 5: Opmask */ 1173 typedef struct XSaveOpmask { 1174 uint64_t opmask_regs[NB_OPMASK_REGS]; 1175 } XSaveOpmask; 1176 1177 /* Ext. save area 6: ZMM_Hi256 */ 1178 typedef struct XSaveZMM_Hi256 { 1179 uint8_t zmm_hi256[16][32]; 1180 } XSaveZMM_Hi256; 1181 1182 /* Ext. save area 7: Hi16_ZMM */ 1183 typedef struct XSaveHi16_ZMM { 1184 uint8_t hi16_zmm[16][64]; 1185 } XSaveHi16_ZMM; 1186 1187 /* Ext. save area 9: PKRU state */ 1188 typedef struct XSavePKRU { 1189 uint32_t pkru; 1190 uint32_t padding; 1191 } XSavePKRU; 1192 1193 typedef struct X86XSaveArea { 1194 X86LegacyXSaveArea legacy; 1195 X86XSaveHeader header; 1196 1197 /* Extended save areas: */ 1198 1199 /* AVX State: */ 1200 XSaveAVX avx_state; 1201 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1202 /* MPX State: */ 1203 XSaveBNDREG bndreg_state; 1204 XSaveBNDCSR bndcsr_state; 1205 /* AVX-512 State: */ 1206 XSaveOpmask opmask_state; 1207 XSaveZMM_Hi256 zmm_hi256_state; 1208 XSaveHi16_ZMM hi16_zmm_state; 1209 /* PKRU State: */ 1210 XSavePKRU pkru_state; 1211 } X86XSaveArea; 1212 1213 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1214 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1215 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1216 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1217 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1218 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1219 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1220 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1221 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1222 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1223 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1224 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1225 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1226 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1227 1228 typedef enum TPRAccess { 1229 TPR_ACCESS_READ, 1230 TPR_ACCESS_WRITE, 1231 } TPRAccess; 1232 1233 /* Cache information data structures: */ 1234 1235 enum CacheType { 1236 DATA_CACHE, 1237 INSTRUCTION_CACHE, 1238 UNIFIED_CACHE 1239 }; 1240 1241 typedef struct CPUCacheInfo { 1242 enum CacheType type; 1243 uint8_t level; 1244 /* Size in bytes */ 1245 uint32_t size; 1246 /* Line size, in bytes */ 1247 uint16_t line_size; 1248 /* 1249 * Associativity. 1250 * Note: representation of fully-associative caches is not implemented 1251 */ 1252 uint8_t associativity; 1253 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1254 uint8_t partitions; 1255 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1256 uint32_t sets; 1257 /* 1258 * Lines per tag. 1259 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1260 * (Is this synonym to @partitions?) 1261 */ 1262 uint8_t lines_per_tag; 1263 1264 /* Self-initializing cache */ 1265 bool self_init; 1266 /* 1267 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1268 * non-originating threads sharing this cache. 1269 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1270 */ 1271 bool no_invd_sharing; 1272 /* 1273 * Cache is inclusive of lower cache levels. 1274 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1275 */ 1276 bool inclusive; 1277 /* 1278 * A complex function is used to index the cache, potentially using all 1279 * address bits. CPUID[4].EDX[bit 2]. 1280 */ 1281 bool complex_indexing; 1282 } CPUCacheInfo; 1283 1284 1285 typedef struct CPUCaches { 1286 CPUCacheInfo *l1d_cache; 1287 CPUCacheInfo *l1i_cache; 1288 CPUCacheInfo *l2_cache; 1289 CPUCacheInfo *l3_cache; 1290 } CPUCaches; 1291 1292 typedef struct CPUX86State { 1293 /* standard registers */ 1294 target_ulong regs[CPU_NB_REGS]; 1295 target_ulong eip; 1296 target_ulong eflags; /* eflags register. During CPU emulation, CC 1297 flags and DF are set to zero because they are 1298 stored elsewhere */ 1299 1300 /* emulator internal eflags handling */ 1301 target_ulong cc_dst; 1302 target_ulong cc_src; 1303 target_ulong cc_src2; 1304 uint32_t cc_op; 1305 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1306 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1307 are known at translation time. */ 1308 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1309 1310 /* segments */ 1311 SegmentCache segs[6]; /* selector values */ 1312 SegmentCache ldt; 1313 SegmentCache tr; 1314 SegmentCache gdt; /* only base and limit are used */ 1315 SegmentCache idt; /* only base and limit are used */ 1316 1317 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1318 int32_t a20_mask; 1319 1320 BNDReg bnd_regs[4]; 1321 BNDCSReg bndcs_regs; 1322 uint64_t msr_bndcfgs; 1323 uint64_t efer; 1324 1325 /* Beginning of state preserved by INIT (dummy marker). */ 1326 struct {} start_init_save; 1327 1328 /* FPU state */ 1329 unsigned int fpstt; /* top of stack index */ 1330 uint16_t fpus; 1331 uint16_t fpuc; 1332 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1333 FPReg fpregs[8]; 1334 /* KVM-only so far */ 1335 uint16_t fpop; 1336 uint64_t fpip; 1337 uint64_t fpdp; 1338 1339 /* emulator internal variables */ 1340 float_status fp_status; 1341 floatx80 ft0; 1342 1343 float_status mmx_status; /* for 3DNow! float ops */ 1344 float_status sse_status; 1345 uint32_t mxcsr; 1346 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1347 ZMMReg xmm_t0; 1348 MMXReg mmx_t0; 1349 1350 XMMReg ymmh_regs[CPU_NB_REGS]; 1351 1352 uint64_t opmask_regs[NB_OPMASK_REGS]; 1353 YMMReg zmmh_regs[CPU_NB_REGS]; 1354 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1355 1356 /* sysenter registers */ 1357 uint32_t sysenter_cs; 1358 target_ulong sysenter_esp; 1359 target_ulong sysenter_eip; 1360 uint64_t star; 1361 1362 uint64_t vm_hsave; 1363 1364 #ifdef TARGET_X86_64 1365 target_ulong lstar; 1366 target_ulong cstar; 1367 target_ulong fmask; 1368 target_ulong kernelgsbase; 1369 #endif 1370 1371 uint64_t tsc; 1372 uint64_t tsc_adjust; 1373 uint64_t tsc_deadline; 1374 uint64_t tsc_aux; 1375 1376 uint64_t xcr0; 1377 1378 uint64_t mcg_status; 1379 uint64_t msr_ia32_misc_enable; 1380 uint64_t msr_ia32_feature_control; 1381 1382 uint64_t msr_fixed_ctr_ctrl; 1383 uint64_t msr_global_ctrl; 1384 uint64_t msr_global_status; 1385 uint64_t msr_global_ovf_ctrl; 1386 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1387 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1388 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1389 1390 uint64_t pat; 1391 uint32_t smbase; 1392 uint64_t msr_smi_count; 1393 1394 uint32_t pkru; 1395 1396 uint64_t spec_ctrl; 1397 uint64_t virt_ssbd; 1398 1399 /* End of state preserved by INIT (dummy marker). */ 1400 struct {} end_init_save; 1401 1402 uint64_t system_time_msr; 1403 uint64_t wall_clock_msr; 1404 uint64_t steal_time_msr; 1405 uint64_t async_pf_en_msr; 1406 uint64_t pv_eoi_en_msr; 1407 uint64_t poll_control_msr; 1408 1409 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1410 uint64_t msr_hv_hypercall; 1411 uint64_t msr_hv_guest_os_id; 1412 uint64_t msr_hv_tsc; 1413 1414 /* Per-VCPU HV MSRs */ 1415 uint64_t msr_hv_vapic; 1416 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1417 uint64_t msr_hv_runtime; 1418 uint64_t msr_hv_synic_control; 1419 uint64_t msr_hv_synic_evt_page; 1420 uint64_t msr_hv_synic_msg_page; 1421 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1422 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1423 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1424 uint64_t msr_hv_reenlightenment_control; 1425 uint64_t msr_hv_tsc_emulation_control; 1426 uint64_t msr_hv_tsc_emulation_status; 1427 1428 uint64_t msr_rtit_ctrl; 1429 uint64_t msr_rtit_status; 1430 uint64_t msr_rtit_output_base; 1431 uint64_t msr_rtit_output_mask; 1432 uint64_t msr_rtit_cr3_match; 1433 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1434 1435 /* exception/interrupt handling */ 1436 int error_code; 1437 int exception_is_int; 1438 target_ulong exception_next_eip; 1439 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1440 union { 1441 struct CPUBreakpoint *cpu_breakpoint[4]; 1442 struct CPUWatchpoint *cpu_watchpoint[4]; 1443 }; /* break/watchpoints for dr[0..3] */ 1444 int old_exception; /* exception in flight */ 1445 1446 uint64_t vm_vmcb; 1447 uint64_t tsc_offset; 1448 uint64_t intercept; 1449 uint16_t intercept_cr_read; 1450 uint16_t intercept_cr_write; 1451 uint16_t intercept_dr_read; 1452 uint16_t intercept_dr_write; 1453 uint32_t intercept_exceptions; 1454 uint64_t nested_cr3; 1455 uint32_t nested_pg_mode; 1456 uint8_t v_tpr; 1457 1458 /* KVM states, automatically cleared on reset */ 1459 uint8_t nmi_injected; 1460 uint8_t nmi_pending; 1461 1462 uintptr_t retaddr; 1463 1464 /* Fields up to this point are cleared by a CPU reset */ 1465 struct {} end_reset_fields; 1466 1467 /* Fields after this point are preserved across CPU reset. */ 1468 1469 /* processor features (e.g. for CPUID insn) */ 1470 /* Minimum cpuid leaf 7 value */ 1471 uint32_t cpuid_level_func7; 1472 /* Actual cpuid leaf 7 value */ 1473 uint32_t cpuid_min_level_func7; 1474 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1475 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1476 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1477 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1478 /* Actual level/xlevel/xlevel2 value: */ 1479 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1480 uint32_t cpuid_vendor1; 1481 uint32_t cpuid_vendor2; 1482 uint32_t cpuid_vendor3; 1483 uint32_t cpuid_version; 1484 FeatureWordArray features; 1485 /* Features that were explicitly enabled/disabled */ 1486 FeatureWordArray user_features; 1487 uint32_t cpuid_model[12]; 1488 /* Cache information for CPUID. When legacy-cache=on, the cache data 1489 * on each CPUID leaf will be different, because we keep compatibility 1490 * with old QEMU versions. 1491 */ 1492 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1493 1494 /* MTRRs */ 1495 uint64_t mtrr_fixed[11]; 1496 uint64_t mtrr_deftype; 1497 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1498 1499 /* For KVM */ 1500 uint32_t mp_state; 1501 int32_t exception_nr; 1502 int32_t interrupt_injected; 1503 uint8_t soft_interrupt; 1504 uint8_t exception_pending; 1505 uint8_t exception_injected; 1506 uint8_t has_error_code; 1507 uint8_t exception_has_payload; 1508 uint64_t exception_payload; 1509 uint32_t ins_len; 1510 uint32_t sipi_vector; 1511 bool tsc_valid; 1512 int64_t tsc_khz; 1513 int64_t user_tsc_khz; /* for sanity check only */ 1514 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1515 void *xsave_buf; 1516 #endif 1517 #if defined(CONFIG_KVM) 1518 struct kvm_nested_state *nested_state; 1519 #endif 1520 #if defined(CONFIG_HVF) 1521 HVFX86EmulatorState *hvf_emul; 1522 #endif 1523 1524 uint64_t mcg_cap; 1525 uint64_t mcg_ctl; 1526 uint64_t mcg_ext_ctl; 1527 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1528 uint64_t xstate_bv; 1529 1530 /* vmstate */ 1531 uint16_t fpus_vmstate; 1532 uint16_t fptag_vmstate; 1533 uint16_t fpregs_format_vmstate; 1534 1535 uint64_t xss; 1536 1537 TPRAccess tpr_access_type; 1538 1539 unsigned nr_dies; 1540 } CPUX86State; 1541 1542 struct kvm_msrs; 1543 1544 /** 1545 * X86CPU: 1546 * @env: #CPUX86State 1547 * @migratable: If set, only migratable flags will be accepted when "enforce" 1548 * mode is used, and only migratable flags will be included in the "host" 1549 * CPU model. 1550 * 1551 * An x86 CPU. 1552 */ 1553 struct X86CPU { 1554 /*< private >*/ 1555 CPUState parent_obj; 1556 /*< public >*/ 1557 1558 CPUNegativeOffsetState neg; 1559 CPUX86State env; 1560 1561 uint32_t hyperv_spinlock_attempts; 1562 char *hyperv_vendor_id; 1563 bool hyperv_synic_kvm_only; 1564 uint64_t hyperv_features; 1565 bool hyperv_passthrough; 1566 1567 bool check_cpuid; 1568 bool enforce_cpuid; 1569 /* 1570 * Force features to be enabled even if the host doesn't support them. 1571 * This is dangerous and should be done only for testing CPUID 1572 * compatibility. 1573 */ 1574 bool force_features; 1575 bool expose_kvm; 1576 bool expose_tcg; 1577 bool migratable; 1578 bool migrate_smi_count; 1579 bool max_features; /* Enable all supported features automatically */ 1580 uint32_t apic_id; 1581 1582 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1583 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1584 bool vmware_cpuid_freq; 1585 1586 /* if true the CPUID code directly forward host cache leaves to the guest */ 1587 bool cache_info_passthrough; 1588 1589 /* if true the CPUID code directly forwards 1590 * host monitor/mwait leaves to the guest */ 1591 struct { 1592 uint32_t eax; 1593 uint32_t ebx; 1594 uint32_t ecx; 1595 uint32_t edx; 1596 } mwait; 1597 1598 /* Features that were filtered out because of missing host capabilities */ 1599 FeatureWordArray filtered_features; 1600 1601 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1602 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1603 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1604 * capabilities) directly to the guest. 1605 */ 1606 bool enable_pmu; 1607 1608 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1609 * disabled by default to avoid breaking migration between QEMU with 1610 * different LMCE configurations. 1611 */ 1612 bool enable_lmce; 1613 1614 /* Compatibility bits for old machine types. 1615 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1616 * socket share an virtual l3 cache. 1617 */ 1618 bool enable_l3_cache; 1619 1620 /* Compatibility bits for old machine types. 1621 * If true present the old cache topology information 1622 */ 1623 bool legacy_cache; 1624 1625 /* Compatibility bits for old machine types: */ 1626 bool enable_cpuid_0xb; 1627 1628 /* Enable auto level-increase for all CPUID leaves */ 1629 bool full_cpuid_auto_level; 1630 1631 /* Enable auto level-increase for Intel Processor Trace leave */ 1632 bool intel_pt_auto_level; 1633 1634 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1635 bool fill_mtrr_mask; 1636 1637 /* if true override the phys_bits value with a value read from the host */ 1638 bool host_phys_bits; 1639 1640 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1641 uint8_t host_phys_bits_limit; 1642 1643 /* Stop SMI delivery for migration compatibility with old machines */ 1644 bool kvm_no_smi_migration; 1645 1646 /* Number of physical address bits supported */ 1647 uint32_t phys_bits; 1648 1649 /* in order to simplify APIC support, we leave this pointer to the 1650 user */ 1651 struct DeviceState *apic_state; 1652 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1653 Notifier machine_done; 1654 1655 struct kvm_msrs *kvm_msr_buf; 1656 1657 int32_t node_id; /* NUMA node this CPU belongs to */ 1658 int32_t socket_id; 1659 int32_t die_id; 1660 int32_t core_id; 1661 int32_t thread_id; 1662 1663 int32_t hv_max_vps; 1664 }; 1665 1666 1667 #ifndef CONFIG_USER_ONLY 1668 extern VMStateDescription vmstate_x86_cpu; 1669 #endif 1670 1671 /** 1672 * x86_cpu_do_interrupt: 1673 * @cpu: vCPU the interrupt is to be handled by. 1674 */ 1675 void x86_cpu_do_interrupt(CPUState *cpu); 1676 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1677 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1678 1679 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1680 int cpuid, void *opaque); 1681 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1682 int cpuid, void *opaque); 1683 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1684 void *opaque); 1685 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1686 void *opaque); 1687 1688 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1689 Error **errp); 1690 1691 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1692 1693 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1694 MemTxAttrs *attrs); 1695 1696 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1697 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1698 1699 void x86_cpu_exec_enter(CPUState *cpu); 1700 void x86_cpu_exec_exit(CPUState *cpu); 1701 1702 void x86_cpu_list(void); 1703 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1704 1705 int cpu_get_pic_interrupt(CPUX86State *s); 1706 /* MSDOS compatibility mode FPU exception support */ 1707 void cpu_set_ferr(CPUX86State *s); 1708 /* mpx_helper.c */ 1709 void cpu_sync_bndcs_hflags(CPUX86State *env); 1710 1711 /* this function must always be used to load data in the segment 1712 cache: it synchronizes the hflags with the segment cache values */ 1713 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1714 int seg_reg, unsigned int selector, 1715 target_ulong base, 1716 unsigned int limit, 1717 unsigned int flags) 1718 { 1719 SegmentCache *sc; 1720 unsigned int new_hflags; 1721 1722 sc = &env->segs[seg_reg]; 1723 sc->selector = selector; 1724 sc->base = base; 1725 sc->limit = limit; 1726 sc->flags = flags; 1727 1728 /* update the hidden flags */ 1729 { 1730 if (seg_reg == R_CS) { 1731 #ifdef TARGET_X86_64 1732 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1733 /* long mode */ 1734 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1735 env->hflags &= ~(HF_ADDSEG_MASK); 1736 } else 1737 #endif 1738 { 1739 /* legacy / compatibility case */ 1740 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1741 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1742 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1743 new_hflags; 1744 } 1745 } 1746 if (seg_reg == R_SS) { 1747 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1748 #if HF_CPL_MASK != 3 1749 #error HF_CPL_MASK is hardcoded 1750 #endif 1751 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1752 /* Possibly switch between BNDCFGS and BNDCFGU */ 1753 cpu_sync_bndcs_hflags(env); 1754 } 1755 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1756 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1757 if (env->hflags & HF_CS64_MASK) { 1758 /* zero base assumed for DS, ES and SS in long mode */ 1759 } else if (!(env->cr[0] & CR0_PE_MASK) || 1760 (env->eflags & VM_MASK) || 1761 !(env->hflags & HF_CS32_MASK)) { 1762 /* XXX: try to avoid this test. The problem comes from the 1763 fact that is real mode or vm86 mode we only modify the 1764 'base' and 'selector' fields of the segment cache to go 1765 faster. A solution may be to force addseg to one in 1766 translate-i386.c. */ 1767 new_hflags |= HF_ADDSEG_MASK; 1768 } else { 1769 new_hflags |= ((env->segs[R_DS].base | 1770 env->segs[R_ES].base | 1771 env->segs[R_SS].base) != 0) << 1772 HF_ADDSEG_SHIFT; 1773 } 1774 env->hflags = (env->hflags & 1775 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1776 } 1777 } 1778 1779 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1780 uint8_t sipi_vector) 1781 { 1782 CPUState *cs = CPU(cpu); 1783 CPUX86State *env = &cpu->env; 1784 1785 env->eip = 0; 1786 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1787 sipi_vector << 12, 1788 env->segs[R_CS].limit, 1789 env->segs[R_CS].flags); 1790 cs->halted = 0; 1791 } 1792 1793 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1794 target_ulong *base, unsigned int *limit, 1795 unsigned int *flags); 1796 1797 /* op_helper.c */ 1798 /* used for debug or cpu save/restore */ 1799 1800 /* cpu-exec.c */ 1801 /* the following helpers are only usable in user mode simulation as 1802 they can trigger unexpected exceptions */ 1803 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1804 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1805 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1806 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1807 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1808 1809 /* you can call this signal handler from your SIGBUS and SIGSEGV 1810 signal handlers to inform the virtual CPU of exceptions. non zero 1811 is returned if the signal was handled by the virtual CPU. */ 1812 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1813 void *puc); 1814 1815 /* cpu.c */ 1816 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1817 uint32_t *eax, uint32_t *ebx, 1818 uint32_t *ecx, uint32_t *edx); 1819 void cpu_clear_apic_feature(CPUX86State *env); 1820 void host_cpuid(uint32_t function, uint32_t count, 1821 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1822 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1823 1824 /* helper.c */ 1825 bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1826 MMUAccessType access_type, int mmu_idx, 1827 bool probe, uintptr_t retaddr); 1828 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1829 1830 #ifndef CONFIG_USER_ONLY 1831 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1832 { 1833 return !!attrs.secure; 1834 } 1835 1836 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1837 { 1838 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1839 } 1840 1841 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1842 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1843 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1844 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1845 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1846 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1847 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1848 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1849 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1850 #endif 1851 1852 void breakpoint_handler(CPUState *cs); 1853 1854 /* will be suppressed */ 1855 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1856 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1857 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1858 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1859 1860 /* hw/pc.c */ 1861 uint64_t cpu_get_tsc(CPUX86State *env); 1862 1863 /* XXX: This value should match the one returned by CPUID 1864 * and in exec.c */ 1865 # if defined(TARGET_X86_64) 1866 # define TCG_PHYS_ADDR_BITS 40 1867 # else 1868 # define TCG_PHYS_ADDR_BITS 36 1869 # endif 1870 1871 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1872 1873 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1874 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1875 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1876 1877 #ifdef TARGET_X86_64 1878 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1879 #else 1880 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1881 #endif 1882 1883 #define cpu_signal_handler cpu_x86_signal_handler 1884 #define cpu_list x86_cpu_list 1885 1886 /* MMU modes definitions */ 1887 #define MMU_MODE0_SUFFIX _ksmap 1888 #define MMU_MODE1_SUFFIX _user 1889 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1890 #define MMU_KSMAP_IDX 0 1891 #define MMU_USER_IDX 1 1892 #define MMU_KNOSMAP_IDX 2 1893 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1894 { 1895 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1896 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1897 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1898 } 1899 1900 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1901 { 1902 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1903 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1904 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1905 } 1906 1907 #define CC_DST (env->cc_dst) 1908 #define CC_SRC (env->cc_src) 1909 #define CC_SRC2 (env->cc_src2) 1910 #define CC_OP (env->cc_op) 1911 1912 /* n must be a constant to be efficient */ 1913 static inline target_long lshift(target_long x, int n) 1914 { 1915 if (n >= 0) { 1916 return x << n; 1917 } else { 1918 return x >> (-n); 1919 } 1920 } 1921 1922 /* float macros */ 1923 #define FT0 (env->ft0) 1924 #define ST0 (env->fpregs[env->fpstt].d) 1925 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1926 #define ST1 ST(1) 1927 1928 /* translate.c */ 1929 void tcg_x86_init(void); 1930 1931 typedef CPUX86State CPUArchState; 1932 typedef X86CPU ArchCPU; 1933 1934 #include "exec/cpu-all.h" 1935 #include "svm.h" 1936 1937 #if !defined(CONFIG_USER_ONLY) 1938 #include "hw/i386/apic.h" 1939 #endif 1940 1941 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1942 target_ulong *cs_base, uint32_t *flags) 1943 { 1944 *cs_base = env->segs[R_CS].base; 1945 *pc = *cs_base + env->eip; 1946 *flags = env->hflags | 1947 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1948 } 1949 1950 void do_cpu_init(X86CPU *cpu); 1951 void do_cpu_sipi(X86CPU *cpu); 1952 1953 #define MCE_INJECT_BROADCAST 1 1954 #define MCE_INJECT_UNCOND_AO 2 1955 1956 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1957 uint64_t status, uint64_t mcg_status, uint64_t addr, 1958 uint64_t misc, int flags); 1959 1960 /* excp_helper.c */ 1961 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1962 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1963 uintptr_t retaddr); 1964 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1965 int error_code); 1966 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1967 int error_code, uintptr_t retaddr); 1968 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1969 int error_code, int next_eip_addend); 1970 1971 /* cc_helper.c */ 1972 extern const uint8_t parity_table[256]; 1973 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1974 1975 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1976 { 1977 uint32_t eflags = env->eflags; 1978 if (tcg_enabled()) { 1979 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 1980 } 1981 return eflags; 1982 } 1983 1984 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1985 * after generating a call to a helper that uses this. 1986 */ 1987 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1988 int update_mask) 1989 { 1990 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1991 CC_OP = CC_OP_EFLAGS; 1992 env->df = 1 - (2 * ((eflags >> 10) & 1)); 1993 env->eflags = (env->eflags & ~update_mask) | 1994 (eflags & update_mask) | 0x2; 1995 } 1996 1997 /* load efer and update the corresponding hflags. XXX: do consistency 1998 checks with cpuid bits? */ 1999 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 2000 { 2001 env->efer = val; 2002 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 2003 if (env->efer & MSR_EFER_LMA) { 2004 env->hflags |= HF_LMA_MASK; 2005 } 2006 if (env->efer & MSR_EFER_SVME) { 2007 env->hflags |= HF_SVME_MASK; 2008 } 2009 } 2010 2011 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2012 { 2013 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2014 } 2015 2016 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2017 { 2018 if (env->hflags & HF_SMM_MASK) { 2019 return -1; 2020 } else { 2021 return env->a20_mask; 2022 } 2023 } 2024 2025 static inline bool cpu_has_vmx(CPUX86State *env) 2026 { 2027 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2028 } 2029 2030 /* 2031 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2032 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2033 * VMX operation. This is because CR4.VMXE is one of the bits set 2034 * in MSR_IA32_VMX_CR4_FIXED1. 2035 * 2036 * There is one exception to above statement when vCPU enters SMM mode. 2037 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2038 * may also reset CR4.VMXE during execution in SMM mode. 2039 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2040 * and CR4.VMXE is restored to it's original value of being set. 2041 * 2042 * Therefore, when vCPU is not in SMM mode, we can infer whether 2043 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2044 * know for certain. 2045 */ 2046 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2047 { 2048 return cpu_has_vmx(env) && 2049 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2050 } 2051 2052 /* fpu_helper.c */ 2053 void update_fp_status(CPUX86State *env); 2054 void update_mxcsr_status(CPUX86State *env); 2055 2056 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2057 { 2058 env->mxcsr = mxcsr; 2059 if (tcg_enabled()) { 2060 update_mxcsr_status(env); 2061 } 2062 } 2063 2064 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2065 { 2066 env->fpuc = fpuc; 2067 if (tcg_enabled()) { 2068 update_fp_status(env); 2069 } 2070 } 2071 2072 /* mem_helper.c */ 2073 void helper_lock_init(void); 2074 2075 /* svm_helper.c */ 2076 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2077 uint64_t param, uintptr_t retaddr); 2078 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, 2079 uint64_t exit_info_1, uintptr_t retaddr); 2080 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 2081 2082 /* seg_helper.c */ 2083 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 2084 2085 /* smm_helper.c */ 2086 void do_smm_enter(X86CPU *cpu); 2087 2088 /* apic.c */ 2089 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2090 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2091 TPRAccess access); 2092 2093 2094 /* Change the value of a KVM-specific default 2095 * 2096 * If value is NULL, no default will be set and the original 2097 * value from the CPU model table will be kept. 2098 * 2099 * It is valid to call this function only for properties that 2100 * are already present in the kvm_default_props table. 2101 */ 2102 void x86_cpu_change_kvm_default(const char *prop, const char *value); 2103 2104 /* Special values for X86CPUVersion: */ 2105 2106 /* Resolve to latest CPU version */ 2107 #define CPU_VERSION_LATEST -1 2108 2109 /* 2110 * Resolve to version defined by current machine type. 2111 * See x86_cpu_set_default_version() 2112 */ 2113 #define CPU_VERSION_AUTO -2 2114 2115 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2116 #define CPU_VERSION_LEGACY 0 2117 2118 typedef int X86CPUVersion; 2119 2120 /* 2121 * Set default CPU model version for CPU models having 2122 * version == CPU_VERSION_AUTO. 2123 */ 2124 void x86_cpu_set_default_version(X86CPUVersion version); 2125 2126 /* Return name of 32-bit register, from a R_* constant */ 2127 const char *get_register_name_32(unsigned int reg); 2128 2129 void enable_compat_apic_id_mode(void); 2130 2131 #define APIC_DEFAULT_ADDRESS 0xfee00000 2132 #define APIC_SPACE_SIZE 0x100000 2133 2134 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2135 2136 /* cpu.c */ 2137 bool cpu_is_bsp(X86CPU *cpu); 2138 2139 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 2140 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 2141 void x86_update_hflags(CPUX86State* env); 2142 2143 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2144 { 2145 return !!(cpu->hyperv_features & BIT(feat)); 2146 } 2147 2148 #endif /* I386_CPU_H */ 2149