1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "kvm/hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 #define KVM_HAVE_MCE_INJECTION 1 33 34 /* support for self modifying code even if the modified instruction is 35 close to the modifying instruction */ 36 #define TARGET_HAS_PRECISE_SMC 37 38 #ifdef TARGET_X86_64 39 #define I386_ELF_MACHINE EM_X86_64 40 #define ELF_MACHINE_UNAME "x86_64" 41 #else 42 #define I386_ELF_MACHINE EM_386 43 #define ELF_MACHINE_UNAME "i686" 44 #endif 45 46 enum { 47 R_EAX = 0, 48 R_ECX = 1, 49 R_EDX = 2, 50 R_EBX = 3, 51 R_ESP = 4, 52 R_EBP = 5, 53 R_ESI = 6, 54 R_EDI = 7, 55 R_R8 = 8, 56 R_R9 = 9, 57 R_R10 = 10, 58 R_R11 = 11, 59 R_R12 = 12, 60 R_R13 = 13, 61 R_R14 = 14, 62 R_R15 = 15, 63 64 R_AL = 0, 65 R_CL = 1, 66 R_DL = 2, 67 R_BL = 3, 68 R_AH = 4, 69 R_CH = 5, 70 R_DH = 6, 71 R_BH = 7, 72 }; 73 74 typedef enum X86Seg { 75 R_ES = 0, 76 R_CS = 1, 77 R_SS = 2, 78 R_DS = 3, 79 R_FS = 4, 80 R_GS = 5, 81 R_LDTR = 6, 82 R_TR = 7, 83 } X86Seg; 84 85 /* segment descriptor fields */ 86 #define DESC_G_SHIFT 23 87 #define DESC_G_MASK (1 << DESC_G_SHIFT) 88 #define DESC_B_SHIFT 22 89 #define DESC_B_MASK (1 << DESC_B_SHIFT) 90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91 #define DESC_L_MASK (1 << DESC_L_SHIFT) 92 #define DESC_AVL_SHIFT 20 93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94 #define DESC_P_SHIFT 15 95 #define DESC_P_MASK (1 << DESC_P_SHIFT) 96 #define DESC_DPL_SHIFT 13 97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98 #define DESC_S_SHIFT 12 99 #define DESC_S_MASK (1 << DESC_S_SHIFT) 100 #define DESC_TYPE_SHIFT 8 101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102 #define DESC_A_MASK (1 << 8) 103 104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105 #define DESC_C_MASK (1 << 10) /* code: conforming */ 106 #define DESC_R_MASK (1 << 9) /* code: readable */ 107 108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109 #define DESC_W_MASK (1 << 9) /* data: writable */ 110 111 #define DESC_TSS_BUSY_MASK (1 << 9) 112 113 /* eflags masks */ 114 #define CC_C 0x0001 115 #define CC_P 0x0004 116 #define CC_A 0x0010 117 #define CC_Z 0x0040 118 #define CC_S 0x0080 119 #define CC_O 0x0800 120 121 #define TF_SHIFT 8 122 #define IOPL_SHIFT 12 123 #define VM_SHIFT 17 124 125 #define TF_MASK 0x00000100 126 #define IF_MASK 0x00000200 127 #define DF_MASK 0x00000400 128 #define IOPL_MASK 0x00003000 129 #define NT_MASK 0x00004000 130 #define RF_MASK 0x00010000 131 #define VM_MASK 0x00020000 132 #define AC_MASK 0x00040000 133 #define VIF_MASK 0x00080000 134 #define VIP_MASK 0x00100000 135 #define ID_MASK 0x00200000 136 137 /* hidden flags - used internally by qemu to represent additional cpu 138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140 positions to ease oring with eflags. */ 141 /* current cpl */ 142 #define HF_CPL_SHIFT 0 143 /* true if hardware interrupts must be disabled for next instruction */ 144 #define HF_INHIBIT_IRQ_SHIFT 3 145 /* 16 or 32 segments */ 146 #define HF_CS32_SHIFT 4 147 #define HF_SS32_SHIFT 5 148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149 #define HF_ADDSEG_SHIFT 6 150 /* copy of CR0.PE (protected mode) */ 151 #define HF_PE_SHIFT 7 152 #define HF_TF_SHIFT 8 /* must be same as eflags */ 153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154 #define HF_EM_SHIFT 10 155 #define HF_TS_SHIFT 11 156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159 #define HF_RF_SHIFT 16 /* must be same as eflags */ 160 #define HF_VM_SHIFT 17 /* must be same as eflags */ 161 #define HF_AC_SHIFT 18 /* must be same as eflags */ 162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170 171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176 #define HF_PE_MASK (1 << HF_PE_SHIFT) 177 #define HF_TF_MASK (1 << HF_TF_SHIFT) 178 #define HF_MP_MASK (1 << HF_MP_SHIFT) 179 #define HF_EM_MASK (1 << HF_EM_SHIFT) 180 #define HF_TS_MASK (1 << HF_TS_SHIFT) 181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184 #define HF_RF_MASK (1 << HF_RF_SHIFT) 185 #define HF_VM_MASK (1 << HF_VM_SHIFT) 186 #define HF_AC_MASK (1 << HF_AC_SHIFT) 187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195 196 /* hflags2 */ 197 198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 206 #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/ 207 208 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 209 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 210 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 211 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 212 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 213 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 214 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 215 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 216 #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT) 217 218 #define CR0_PE_SHIFT 0 219 #define CR0_MP_SHIFT 1 220 221 #define CR0_PE_MASK (1U << 0) 222 #define CR0_MP_MASK (1U << 1) 223 #define CR0_EM_MASK (1U << 2) 224 #define CR0_TS_MASK (1U << 3) 225 #define CR0_ET_MASK (1U << 4) 226 #define CR0_NE_MASK (1U << 5) 227 #define CR0_WP_MASK (1U << 16) 228 #define CR0_AM_MASK (1U << 18) 229 #define CR0_NW_MASK (1U << 29) 230 #define CR0_CD_MASK (1U << 30) 231 #define CR0_PG_MASK (1U << 31) 232 233 #define CR4_VME_MASK (1U << 0) 234 #define CR4_PVI_MASK (1U << 1) 235 #define CR4_TSD_MASK (1U << 2) 236 #define CR4_DE_MASK (1U << 3) 237 #define CR4_PSE_MASK (1U << 4) 238 #define CR4_PAE_MASK (1U << 5) 239 #define CR4_MCE_MASK (1U << 6) 240 #define CR4_PGE_MASK (1U << 7) 241 #define CR4_PCE_MASK (1U << 8) 242 #define CR4_OSFXSR_SHIFT 9 243 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 244 #define CR4_OSXMMEXCPT_MASK (1U << 10) 245 #define CR4_UMIP_MASK (1U << 11) 246 #define CR4_LA57_MASK (1U << 12) 247 #define CR4_VMXE_MASK (1U << 13) 248 #define CR4_SMXE_MASK (1U << 14) 249 #define CR4_FSGSBASE_MASK (1U << 16) 250 #define CR4_PCIDE_MASK (1U << 17) 251 #define CR4_OSXSAVE_MASK (1U << 18) 252 #define CR4_SMEP_MASK (1U << 20) 253 #define CR4_SMAP_MASK (1U << 21) 254 #define CR4_PKE_MASK (1U << 22) 255 #define CR4_PKS_MASK (1U << 24) 256 257 #define CR4_RESERVED_MASK \ 258 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ 259 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ 260 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ 261 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK |CR4_UMIP_MASK \ 262 | CR4_LA57_MASK \ 263 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ 264 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) 265 266 #define DR6_BD (1 << 13) 267 #define DR6_BS (1 << 14) 268 #define DR6_BT (1 << 15) 269 #define DR6_FIXED_1 0xffff0ff0 270 271 #define DR7_GD (1 << 13) 272 #define DR7_TYPE_SHIFT 16 273 #define DR7_LEN_SHIFT 18 274 #define DR7_FIXED_1 0x00000400 275 #define DR7_GLOBAL_BP_MASK 0xaa 276 #define DR7_LOCAL_BP_MASK 0x55 277 #define DR7_MAX_BP 4 278 #define DR7_TYPE_BP_INST 0x0 279 #define DR7_TYPE_DATA_WR 0x1 280 #define DR7_TYPE_IO_RW 0x2 281 #define DR7_TYPE_DATA_RW 0x3 282 283 #define DR_RESERVED_MASK 0xffffffff00000000ULL 284 285 #define PG_PRESENT_BIT 0 286 #define PG_RW_BIT 1 287 #define PG_USER_BIT 2 288 #define PG_PWT_BIT 3 289 #define PG_PCD_BIT 4 290 #define PG_ACCESSED_BIT 5 291 #define PG_DIRTY_BIT 6 292 #define PG_PSE_BIT 7 293 #define PG_GLOBAL_BIT 8 294 #define PG_PSE_PAT_BIT 12 295 #define PG_PKRU_BIT 59 296 #define PG_NX_BIT 63 297 298 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 299 #define PG_RW_MASK (1 << PG_RW_BIT) 300 #define PG_USER_MASK (1 << PG_USER_BIT) 301 #define PG_PWT_MASK (1 << PG_PWT_BIT) 302 #define PG_PCD_MASK (1 << PG_PCD_BIT) 303 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 304 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 305 #define PG_PSE_MASK (1 << PG_PSE_BIT) 306 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 307 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 308 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 309 #define PG_HI_USER_MASK 0x7ff0000000000000LL 310 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 311 #define PG_NX_MASK (1ULL << PG_NX_BIT) 312 313 #define PG_ERROR_W_BIT 1 314 315 #define PG_ERROR_P_MASK 0x01 316 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 317 #define PG_ERROR_U_MASK 0x04 318 #define PG_ERROR_RSVD_MASK 0x08 319 #define PG_ERROR_I_D_MASK 0x10 320 #define PG_ERROR_PK_MASK 0x20 321 322 #define PG_MODE_PAE (1 << 0) 323 #define PG_MODE_LMA (1 << 1) 324 #define PG_MODE_NXE (1 << 2) 325 #define PG_MODE_PSE (1 << 3) 326 #define PG_MODE_LA57 (1 << 4) 327 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) 328 329 /* Bits of CR4 that do not affect the NPT page format. */ 330 #define PG_MODE_WP (1 << 16) 331 #define PG_MODE_PKE (1 << 17) 332 #define PG_MODE_PKS (1 << 18) 333 #define PG_MODE_SMEP (1 << 19) 334 335 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 336 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 337 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 338 339 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 340 #define MCE_BANKS_DEF 10 341 342 #define MCG_CAP_BANKS_MASK 0xff 343 344 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 345 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 346 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 347 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 348 349 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 350 351 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 352 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 353 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 354 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 355 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 356 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 357 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 358 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 359 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 360 361 /* MISC register defines */ 362 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 363 #define MCM_ADDR_LINEAR 1 /* linear address */ 364 #define MCM_ADDR_PHYS 2 /* physical address */ 365 #define MCM_ADDR_MEM 3 /* memory address */ 366 #define MCM_ADDR_GENERIC 7 /* generic */ 367 368 #define MSR_IA32_TSC 0x10 369 #define MSR_IA32_APICBASE 0x1b 370 #define MSR_IA32_APICBASE_BSP (1<<8) 371 #define MSR_IA32_APICBASE_ENABLE (1<<11) 372 #define MSR_IA32_APICBASE_EXTD (1 << 10) 373 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 374 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 375 #define MSR_TSC_ADJUST 0x0000003b 376 #define MSR_IA32_SPEC_CTRL 0x48 377 #define MSR_VIRT_SSBD 0xc001011f 378 #define MSR_IA32_PRED_CMD 0x49 379 #define MSR_IA32_UCODE_REV 0x8b 380 #define MSR_IA32_CORE_CAPABILITY 0xcf 381 382 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 383 #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 384 385 #define MSR_IA32_PERF_CAPABILITIES 0x345 386 387 #define MSR_IA32_TSX_CTRL 0x122 388 #define MSR_IA32_TSCDEADLINE 0x6e0 389 #define MSR_IA32_PKRS 0x6e1 390 391 #define FEATURE_CONTROL_LOCKED (1<<0) 392 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 393 #define FEATURE_CONTROL_LMCE (1<<20) 394 395 #define MSR_P6_PERFCTR0 0xc1 396 397 #define MSR_IA32_SMBASE 0x9e 398 #define MSR_SMI_COUNT 0x34 399 #define MSR_CORE_THREAD_COUNT 0x35 400 #define MSR_MTRRcap 0xfe 401 #define MSR_MTRRcap_VCNT 8 402 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 403 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 404 405 #define MSR_IA32_SYSENTER_CS 0x174 406 #define MSR_IA32_SYSENTER_ESP 0x175 407 #define MSR_IA32_SYSENTER_EIP 0x176 408 409 #define MSR_MCG_CAP 0x179 410 #define MSR_MCG_STATUS 0x17a 411 #define MSR_MCG_CTL 0x17b 412 #define MSR_MCG_EXT_CTL 0x4d0 413 414 #define MSR_P6_EVNTSEL0 0x186 415 416 #define MSR_IA32_PERF_STATUS 0x198 417 418 #define MSR_IA32_MISC_ENABLE 0x1a0 419 /* Indicates good rep/movs microcode on some processors: */ 420 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 421 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 422 423 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 424 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 425 426 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 427 428 #define MSR_MTRRfix64K_00000 0x250 429 #define MSR_MTRRfix16K_80000 0x258 430 #define MSR_MTRRfix16K_A0000 0x259 431 #define MSR_MTRRfix4K_C0000 0x268 432 #define MSR_MTRRfix4K_C8000 0x269 433 #define MSR_MTRRfix4K_D0000 0x26a 434 #define MSR_MTRRfix4K_D8000 0x26b 435 #define MSR_MTRRfix4K_E0000 0x26c 436 #define MSR_MTRRfix4K_E8000 0x26d 437 #define MSR_MTRRfix4K_F0000 0x26e 438 #define MSR_MTRRfix4K_F8000 0x26f 439 440 #define MSR_PAT 0x277 441 442 #define MSR_MTRRdefType 0x2ff 443 444 #define MSR_CORE_PERF_FIXED_CTR0 0x309 445 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 446 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 447 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 448 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 449 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 450 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 451 452 #define MSR_MC0_CTL 0x400 453 #define MSR_MC0_STATUS 0x401 454 #define MSR_MC0_ADDR 0x402 455 #define MSR_MC0_MISC 0x403 456 457 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 458 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 459 #define MSR_IA32_RTIT_CTL 0x570 460 #define MSR_IA32_RTIT_STATUS 0x571 461 #define MSR_IA32_RTIT_CR3_MATCH 0x572 462 #define MSR_IA32_RTIT_ADDR0_A 0x580 463 #define MSR_IA32_RTIT_ADDR0_B 0x581 464 #define MSR_IA32_RTIT_ADDR1_A 0x582 465 #define MSR_IA32_RTIT_ADDR1_B 0x583 466 #define MSR_IA32_RTIT_ADDR2_A 0x584 467 #define MSR_IA32_RTIT_ADDR2_B 0x585 468 #define MSR_IA32_RTIT_ADDR3_A 0x586 469 #define MSR_IA32_RTIT_ADDR3_B 0x587 470 #define MAX_RTIT_ADDRS 8 471 472 #define MSR_EFER 0xc0000080 473 474 #define MSR_EFER_SCE (1 << 0) 475 #define MSR_EFER_LME (1 << 8) 476 #define MSR_EFER_LMA (1 << 10) 477 #define MSR_EFER_NXE (1 << 11) 478 #define MSR_EFER_SVME (1 << 12) 479 #define MSR_EFER_FFXSR (1 << 14) 480 481 #define MSR_EFER_RESERVED\ 482 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\ 483 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\ 484 | MSR_EFER_FFXSR)) 485 486 #define MSR_STAR 0xc0000081 487 #define MSR_LSTAR 0xc0000082 488 #define MSR_CSTAR 0xc0000083 489 #define MSR_FMASK 0xc0000084 490 #define MSR_FSBASE 0xc0000100 491 #define MSR_GSBASE 0xc0000101 492 #define MSR_KERNELGSBASE 0xc0000102 493 #define MSR_TSC_AUX 0xc0000103 494 495 #define MSR_VM_HSAVE_PA 0xc0010117 496 497 #define MSR_IA32_BNDCFGS 0x00000d90 498 #define MSR_IA32_XSS 0x00000da0 499 #define MSR_IA32_UMWAIT_CONTROL 0xe1 500 501 #define MSR_IA32_VMX_BASIC 0x00000480 502 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 503 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 504 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 505 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 506 #define MSR_IA32_VMX_MISC 0x00000485 507 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 508 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 509 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 510 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 511 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 512 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 513 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 514 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 515 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 516 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 517 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 518 #define MSR_IA32_VMX_VMFUNC 0x00000491 519 520 #define XSTATE_FP_BIT 0 521 #define XSTATE_SSE_BIT 1 522 #define XSTATE_YMM_BIT 2 523 #define XSTATE_BNDREGS_BIT 3 524 #define XSTATE_BNDCSR_BIT 4 525 #define XSTATE_OPMASK_BIT 5 526 #define XSTATE_ZMM_Hi256_BIT 6 527 #define XSTATE_Hi16_ZMM_BIT 7 528 #define XSTATE_PKRU_BIT 9 529 530 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 531 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 532 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 533 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 534 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 535 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 536 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 537 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 538 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 539 540 /* CPUID feature words */ 541 typedef enum FeatureWord { 542 FEAT_1_EDX, /* CPUID[1].EDX */ 543 FEAT_1_ECX, /* CPUID[1].ECX */ 544 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 545 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 546 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 547 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 548 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 549 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 550 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 551 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 552 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 553 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 554 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 555 FEAT_SVM, /* CPUID[8000_000A].EDX */ 556 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 557 FEAT_6_EAX, /* CPUID[6].EAX */ 558 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 559 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 560 FEAT_ARCH_CAPABILITIES, 561 FEAT_CORE_CAPABILITY, 562 FEAT_PERF_CAPABILITIES, 563 FEAT_VMX_PROCBASED_CTLS, 564 FEAT_VMX_SECONDARY_CTLS, 565 FEAT_VMX_PINBASED_CTLS, 566 FEAT_VMX_EXIT_CTLS, 567 FEAT_VMX_ENTRY_CTLS, 568 FEAT_VMX_MISC, 569 FEAT_VMX_EPT_VPID_CAPS, 570 FEAT_VMX_BASIC, 571 FEAT_VMX_VMFUNC, 572 FEAT_14_0_ECX, 573 FEATURE_WORDS, 574 } FeatureWord; 575 576 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 577 578 /* cpuid_features bits */ 579 #define CPUID_FP87 (1U << 0) 580 #define CPUID_VME (1U << 1) 581 #define CPUID_DE (1U << 2) 582 #define CPUID_PSE (1U << 3) 583 #define CPUID_TSC (1U << 4) 584 #define CPUID_MSR (1U << 5) 585 #define CPUID_PAE (1U << 6) 586 #define CPUID_MCE (1U << 7) 587 #define CPUID_CX8 (1U << 8) 588 #define CPUID_APIC (1U << 9) 589 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 590 #define CPUID_MTRR (1U << 12) 591 #define CPUID_PGE (1U << 13) 592 #define CPUID_MCA (1U << 14) 593 #define CPUID_CMOV (1U << 15) 594 #define CPUID_PAT (1U << 16) 595 #define CPUID_PSE36 (1U << 17) 596 #define CPUID_PN (1U << 18) 597 #define CPUID_CLFLUSH (1U << 19) 598 #define CPUID_DTS (1U << 21) 599 #define CPUID_ACPI (1U << 22) 600 #define CPUID_MMX (1U << 23) 601 #define CPUID_FXSR (1U << 24) 602 #define CPUID_SSE (1U << 25) 603 #define CPUID_SSE2 (1U << 26) 604 #define CPUID_SS (1U << 27) 605 #define CPUID_HT (1U << 28) 606 #define CPUID_TM (1U << 29) 607 #define CPUID_IA64 (1U << 30) 608 #define CPUID_PBE (1U << 31) 609 610 #define CPUID_EXT_SSE3 (1U << 0) 611 #define CPUID_EXT_PCLMULQDQ (1U << 1) 612 #define CPUID_EXT_DTES64 (1U << 2) 613 #define CPUID_EXT_MONITOR (1U << 3) 614 #define CPUID_EXT_DSCPL (1U << 4) 615 #define CPUID_EXT_VMX (1U << 5) 616 #define CPUID_EXT_SMX (1U << 6) 617 #define CPUID_EXT_EST (1U << 7) 618 #define CPUID_EXT_TM2 (1U << 8) 619 #define CPUID_EXT_SSSE3 (1U << 9) 620 #define CPUID_EXT_CID (1U << 10) 621 #define CPUID_EXT_FMA (1U << 12) 622 #define CPUID_EXT_CX16 (1U << 13) 623 #define CPUID_EXT_XTPR (1U << 14) 624 #define CPUID_EXT_PDCM (1U << 15) 625 #define CPUID_EXT_PCID (1U << 17) 626 #define CPUID_EXT_DCA (1U << 18) 627 #define CPUID_EXT_SSE41 (1U << 19) 628 #define CPUID_EXT_SSE42 (1U << 20) 629 #define CPUID_EXT_X2APIC (1U << 21) 630 #define CPUID_EXT_MOVBE (1U << 22) 631 #define CPUID_EXT_POPCNT (1U << 23) 632 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 633 #define CPUID_EXT_AES (1U << 25) 634 #define CPUID_EXT_XSAVE (1U << 26) 635 #define CPUID_EXT_OSXSAVE (1U << 27) 636 #define CPUID_EXT_AVX (1U << 28) 637 #define CPUID_EXT_F16C (1U << 29) 638 #define CPUID_EXT_RDRAND (1U << 30) 639 #define CPUID_EXT_HYPERVISOR (1U << 31) 640 641 #define CPUID_EXT2_FPU (1U << 0) 642 #define CPUID_EXT2_VME (1U << 1) 643 #define CPUID_EXT2_DE (1U << 2) 644 #define CPUID_EXT2_PSE (1U << 3) 645 #define CPUID_EXT2_TSC (1U << 4) 646 #define CPUID_EXT2_MSR (1U << 5) 647 #define CPUID_EXT2_PAE (1U << 6) 648 #define CPUID_EXT2_MCE (1U << 7) 649 #define CPUID_EXT2_CX8 (1U << 8) 650 #define CPUID_EXT2_APIC (1U << 9) 651 #define CPUID_EXT2_SYSCALL (1U << 11) 652 #define CPUID_EXT2_MTRR (1U << 12) 653 #define CPUID_EXT2_PGE (1U << 13) 654 #define CPUID_EXT2_MCA (1U << 14) 655 #define CPUID_EXT2_CMOV (1U << 15) 656 #define CPUID_EXT2_PAT (1U << 16) 657 #define CPUID_EXT2_PSE36 (1U << 17) 658 #define CPUID_EXT2_MP (1U << 19) 659 #define CPUID_EXT2_NX (1U << 20) 660 #define CPUID_EXT2_MMXEXT (1U << 22) 661 #define CPUID_EXT2_MMX (1U << 23) 662 #define CPUID_EXT2_FXSR (1U << 24) 663 #define CPUID_EXT2_FFXSR (1U << 25) 664 #define CPUID_EXT2_PDPE1GB (1U << 26) 665 #define CPUID_EXT2_RDTSCP (1U << 27) 666 #define CPUID_EXT2_LM (1U << 29) 667 #define CPUID_EXT2_3DNOWEXT (1U << 30) 668 #define CPUID_EXT2_3DNOW (1U << 31) 669 670 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 671 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 672 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 673 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 674 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 675 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 676 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 677 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 678 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 679 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 680 681 #define CPUID_EXT3_LAHF_LM (1U << 0) 682 #define CPUID_EXT3_CMP_LEG (1U << 1) 683 #define CPUID_EXT3_SVM (1U << 2) 684 #define CPUID_EXT3_EXTAPIC (1U << 3) 685 #define CPUID_EXT3_CR8LEG (1U << 4) 686 #define CPUID_EXT3_ABM (1U << 5) 687 #define CPUID_EXT3_SSE4A (1U << 6) 688 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 689 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 690 #define CPUID_EXT3_OSVW (1U << 9) 691 #define CPUID_EXT3_IBS (1U << 10) 692 #define CPUID_EXT3_XOP (1U << 11) 693 #define CPUID_EXT3_SKINIT (1U << 12) 694 #define CPUID_EXT3_WDT (1U << 13) 695 #define CPUID_EXT3_LWP (1U << 15) 696 #define CPUID_EXT3_FMA4 (1U << 16) 697 #define CPUID_EXT3_TCE (1U << 17) 698 #define CPUID_EXT3_NODEID (1U << 19) 699 #define CPUID_EXT3_TBM (1U << 21) 700 #define CPUID_EXT3_TOPOEXT (1U << 22) 701 #define CPUID_EXT3_PERFCORE (1U << 23) 702 #define CPUID_EXT3_PERFNB (1U << 24) 703 704 #define CPUID_SVM_NPT (1U << 0) 705 #define CPUID_SVM_LBRV (1U << 1) 706 #define CPUID_SVM_SVMLOCK (1U << 2) 707 #define CPUID_SVM_NRIPSAVE (1U << 3) 708 #define CPUID_SVM_TSCSCALE (1U << 4) 709 #define CPUID_SVM_VMCBCLEAN (1U << 5) 710 #define CPUID_SVM_FLUSHASID (1U << 6) 711 #define CPUID_SVM_DECODEASSIST (1U << 7) 712 #define CPUID_SVM_PAUSEFILTER (1U << 10) 713 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 714 #define CPUID_SVM_AVIC (1U << 13) 715 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) 716 #define CPUID_SVM_VGIF (1U << 16) 717 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) 718 719 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 720 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 721 /* 1st Group of Advanced Bit Manipulation Extensions */ 722 #define CPUID_7_0_EBX_BMI1 (1U << 3) 723 /* Hardware Lock Elision */ 724 #define CPUID_7_0_EBX_HLE (1U << 4) 725 /* Intel Advanced Vector Extensions 2 */ 726 #define CPUID_7_0_EBX_AVX2 (1U << 5) 727 /* Supervisor-mode Execution Prevention */ 728 #define CPUID_7_0_EBX_SMEP (1U << 7) 729 /* 2nd Group of Advanced Bit Manipulation Extensions */ 730 #define CPUID_7_0_EBX_BMI2 (1U << 8) 731 /* Enhanced REP MOVSB/STOSB */ 732 #define CPUID_7_0_EBX_ERMS (1U << 9) 733 /* Invalidate Process-Context Identifier */ 734 #define CPUID_7_0_EBX_INVPCID (1U << 10) 735 /* Restricted Transactional Memory */ 736 #define CPUID_7_0_EBX_RTM (1U << 11) 737 /* Memory Protection Extension */ 738 #define CPUID_7_0_EBX_MPX (1U << 14) 739 /* AVX-512 Foundation */ 740 #define CPUID_7_0_EBX_AVX512F (1U << 16) 741 /* AVX-512 Doubleword & Quadword Instruction */ 742 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 743 /* Read Random SEED */ 744 #define CPUID_7_0_EBX_RDSEED (1U << 18) 745 /* ADCX and ADOX instructions */ 746 #define CPUID_7_0_EBX_ADX (1U << 19) 747 /* Supervisor Mode Access Prevention */ 748 #define CPUID_7_0_EBX_SMAP (1U << 20) 749 /* AVX-512 Integer Fused Multiply Add */ 750 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 751 /* Persistent Commit */ 752 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 753 /* Flush a Cache Line Optimized */ 754 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 755 /* Cache Line Write Back */ 756 #define CPUID_7_0_EBX_CLWB (1U << 24) 757 /* Intel Processor Trace */ 758 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 759 /* AVX-512 Prefetch */ 760 #define CPUID_7_0_EBX_AVX512PF (1U << 26) 761 /* AVX-512 Exponential and Reciprocal */ 762 #define CPUID_7_0_EBX_AVX512ER (1U << 27) 763 /* AVX-512 Conflict Detection */ 764 #define CPUID_7_0_EBX_AVX512CD (1U << 28) 765 /* SHA1/SHA256 Instruction Extensions */ 766 #define CPUID_7_0_EBX_SHA_NI (1U << 29) 767 /* AVX-512 Byte and Word Instructions */ 768 #define CPUID_7_0_EBX_AVX512BW (1U << 30) 769 /* AVX-512 Vector Length Extensions */ 770 #define CPUID_7_0_EBX_AVX512VL (1U << 31) 771 772 /* AVX-512 Vector Byte Manipulation Instruction */ 773 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 774 /* User-Mode Instruction Prevention */ 775 #define CPUID_7_0_ECX_UMIP (1U << 2) 776 /* Protection Keys for User-mode Pages */ 777 #define CPUID_7_0_ECX_PKU (1U << 3) 778 /* OS Enable Protection Keys */ 779 #define CPUID_7_0_ECX_OSPKE (1U << 4) 780 /* UMONITOR/UMWAIT/TPAUSE Instructions */ 781 #define CPUID_7_0_ECX_WAITPKG (1U << 5) 782 /* Additional AVX-512 Vector Byte Manipulation Instruction */ 783 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 784 /* Galois Field New Instructions */ 785 #define CPUID_7_0_ECX_GFNI (1U << 8) 786 /* Vector AES Instructions */ 787 #define CPUID_7_0_ECX_VAES (1U << 9) 788 /* Carry-Less Multiplication Quadword */ 789 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 790 /* Vector Neural Network Instructions */ 791 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 792 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 793 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 794 /* POPCNT for vectors of DW/QW */ 795 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 796 /* 5-level Page Tables */ 797 #define CPUID_7_0_ECX_LA57 (1U << 16) 798 /* Read Processor ID */ 799 #define CPUID_7_0_ECX_RDPID (1U << 22) 800 /* Bus Lock Debug Exception */ 801 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) 802 /* Cache Line Demote Instruction */ 803 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 804 /* Move Doubleword as Direct Store Instruction */ 805 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 806 /* Move 64 Bytes as Direct Store Instruction */ 807 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 808 /* Protection Keys for Supervisor-mode Pages */ 809 #define CPUID_7_0_ECX_PKS (1U << 31) 810 811 /* AVX512 Neural Network Instructions */ 812 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 813 /* AVX512 Multiply Accumulation Single Precision */ 814 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 815 /* Fast Short Rep Mov */ 816 #define CPUID_7_0_EDX_FSRM (1U << 4) 817 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 818 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 819 /* SERIALIZE instruction */ 820 #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 821 /* TSX Suspend Load Address Tracking instruction */ 822 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 823 /* AVX512_FP16 instruction */ 824 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) 825 /* Speculation Control */ 826 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 827 /* Single Thread Indirect Branch Predictors */ 828 #define CPUID_7_0_EDX_STIBP (1U << 27) 829 /* Arch Capabilities */ 830 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 831 /* Core Capability */ 832 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 833 /* Speculative Store Bypass Disable */ 834 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 835 836 /* AVX VNNI Instruction */ 837 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) 838 /* AVX512 BFloat16 Instruction */ 839 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 840 841 /* Packets which contain IP payload have LIP values */ 842 #define CPUID_14_0_ECX_LIP (1U << 31) 843 844 /* CLZERO instruction */ 845 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 846 /* Always save/restore FP error pointers */ 847 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 848 /* Write back and do not invalidate cache */ 849 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 850 /* Indirect Branch Prediction Barrier */ 851 #define CPUID_8000_0008_EBX_IBPB (1U << 12) 852 /* Indirect Branch Restricted Speculation */ 853 #define CPUID_8000_0008_EBX_IBRS (1U << 14) 854 /* Single Thread Indirect Branch Predictors */ 855 #define CPUID_8000_0008_EBX_STIBP (1U << 15) 856 /* Speculative Store Bypass Disable */ 857 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) 858 859 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 860 #define CPUID_XSAVE_XSAVEC (1U << 1) 861 #define CPUID_XSAVE_XGETBV1 (1U << 2) 862 #define CPUID_XSAVE_XSAVES (1U << 3) 863 864 #define CPUID_6_EAX_ARAT (1U << 2) 865 866 /* CPUID[0x80000007].EDX flags: */ 867 #define CPUID_APM_INVTSC (1U << 8) 868 869 #define CPUID_VENDOR_SZ 12 870 871 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 872 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 873 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 874 #define CPUID_VENDOR_INTEL "GenuineIntel" 875 876 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 877 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 878 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 879 #define CPUID_VENDOR_AMD "AuthenticAMD" 880 881 #define CPUID_VENDOR_VIA "CentaurHauls" 882 883 #define CPUID_VENDOR_HYGON "HygonGenuine" 884 885 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 886 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 887 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 888 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 889 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 890 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 891 892 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 893 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 894 895 /* CPUID[0xB].ECX level types */ 896 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 897 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 898 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 899 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 900 901 /* MSR Feature Bits */ 902 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 903 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 904 #define MSR_ARCH_CAP_RSBA (1U << 2) 905 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 906 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 907 #define MSR_ARCH_CAP_MDS_NO (1U << 5) 908 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 909 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 910 #define MSR_ARCH_CAP_TAA_NO (1U << 8) 911 912 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 913 914 /* VMX MSR features */ 915 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 916 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 917 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 918 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 919 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 920 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 921 922 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 923 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 924 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 925 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 926 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 927 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 928 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 929 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 930 931 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 932 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 933 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 934 #define MSR_VMX_EPT_UC (1ULL << 8) 935 #define MSR_VMX_EPT_WB (1ULL << 14) 936 #define MSR_VMX_EPT_2MB (1ULL << 16) 937 #define MSR_VMX_EPT_1GB (1ULL << 17) 938 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 939 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 940 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 941 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 942 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 943 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 944 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 945 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 946 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 947 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 948 949 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 950 951 952 /* VMX controls */ 953 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 954 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 955 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 956 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 957 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 958 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 959 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 960 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 961 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 962 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 963 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 964 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 965 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 966 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 967 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 968 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 969 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 970 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 971 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 972 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 973 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 974 975 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 976 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 977 #define VMX_SECONDARY_EXEC_DESC 0x00000004 978 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 979 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 980 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 981 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 982 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 983 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 984 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 985 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 986 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 987 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 988 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 989 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 990 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 991 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 992 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 993 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 994 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000 995 996 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 997 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 998 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 999 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 1000 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 1001 1002 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 1003 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 1004 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 1005 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 1006 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 1007 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 1008 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 1009 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 1010 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 1011 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 1012 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 1013 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 1014 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 1015 1016 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 1017 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 1018 #define VMX_VM_ENTRY_SMM 0x00000400 1019 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 1020 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 1021 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 1022 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 1023 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 1024 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 1025 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 1026 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 1027 1028 /* Supported Hyper-V Enlightenments */ 1029 #define HYPERV_FEAT_RELAXED 0 1030 #define HYPERV_FEAT_VAPIC 1 1031 #define HYPERV_FEAT_TIME 2 1032 #define HYPERV_FEAT_CRASH 3 1033 #define HYPERV_FEAT_RESET 4 1034 #define HYPERV_FEAT_VPINDEX 5 1035 #define HYPERV_FEAT_RUNTIME 6 1036 #define HYPERV_FEAT_SYNIC 7 1037 #define HYPERV_FEAT_STIMER 8 1038 #define HYPERV_FEAT_FREQUENCIES 9 1039 #define HYPERV_FEAT_REENLIGHTENMENT 10 1040 #define HYPERV_FEAT_TLBFLUSH 11 1041 #define HYPERV_FEAT_EVMCS 12 1042 #define HYPERV_FEAT_IPI 13 1043 #define HYPERV_FEAT_STIMER_DIRECT 14 1044 1045 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY 1046 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF 1047 #endif 1048 1049 #define EXCP00_DIVZ 0 1050 #define EXCP01_DB 1 1051 #define EXCP02_NMI 2 1052 #define EXCP03_INT3 3 1053 #define EXCP04_INTO 4 1054 #define EXCP05_BOUND 5 1055 #define EXCP06_ILLOP 6 1056 #define EXCP07_PREX 7 1057 #define EXCP08_DBLE 8 1058 #define EXCP09_XERR 9 1059 #define EXCP0A_TSS 10 1060 #define EXCP0B_NOSEG 11 1061 #define EXCP0C_STACK 12 1062 #define EXCP0D_GPF 13 1063 #define EXCP0E_PAGE 14 1064 #define EXCP10_COPR 16 1065 #define EXCP11_ALGN 17 1066 #define EXCP12_MCHK 18 1067 1068 #define EXCP_VMEXIT 0x100 /* only for system emulation */ 1069 #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1070 #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1071 1072 /* i386-specific interrupt pending bits. */ 1073 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1074 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1075 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1076 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1077 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1078 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1079 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1080 1081 /* Use a clearer name for this. */ 1082 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1083 1084 /* Instead of computing the condition codes after each x86 instruction, 1085 * QEMU just stores one operand (called CC_SRC), the result 1086 * (called CC_DST) and the type of operation (called CC_OP). When the 1087 * condition codes are needed, the condition codes can be calculated 1088 * using this information. Condition codes are not generated if they 1089 * are only needed for conditional branches. 1090 */ 1091 typedef enum { 1092 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1093 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1094 1095 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1096 CC_OP_MULW, 1097 CC_OP_MULL, 1098 CC_OP_MULQ, 1099 1100 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1101 CC_OP_ADDW, 1102 CC_OP_ADDL, 1103 CC_OP_ADDQ, 1104 1105 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1106 CC_OP_ADCW, 1107 CC_OP_ADCL, 1108 CC_OP_ADCQ, 1109 1110 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1111 CC_OP_SUBW, 1112 CC_OP_SUBL, 1113 CC_OP_SUBQ, 1114 1115 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1116 CC_OP_SBBW, 1117 CC_OP_SBBL, 1118 CC_OP_SBBQ, 1119 1120 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1121 CC_OP_LOGICW, 1122 CC_OP_LOGICL, 1123 CC_OP_LOGICQ, 1124 1125 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1126 CC_OP_INCW, 1127 CC_OP_INCL, 1128 CC_OP_INCQ, 1129 1130 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1131 CC_OP_DECW, 1132 CC_OP_DECL, 1133 CC_OP_DECQ, 1134 1135 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1136 CC_OP_SHLW, 1137 CC_OP_SHLL, 1138 CC_OP_SHLQ, 1139 1140 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1141 CC_OP_SARW, 1142 CC_OP_SARL, 1143 CC_OP_SARQ, 1144 1145 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1146 CC_OP_BMILGW, 1147 CC_OP_BMILGL, 1148 CC_OP_BMILGQ, 1149 1150 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1151 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1152 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1153 1154 CC_OP_CLR, /* Z set, all other flags clear. */ 1155 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1156 1157 CC_OP_NB, 1158 } CCOp; 1159 1160 typedef struct SegmentCache { 1161 uint32_t selector; 1162 target_ulong base; 1163 uint32_t limit; 1164 uint32_t flags; 1165 } SegmentCache; 1166 1167 #define MMREG_UNION(n, bits) \ 1168 union n { \ 1169 uint8_t _b_##n[(bits)/8]; \ 1170 uint16_t _w_##n[(bits)/16]; \ 1171 uint32_t _l_##n[(bits)/32]; \ 1172 uint64_t _q_##n[(bits)/64]; \ 1173 float32 _s_##n[(bits)/32]; \ 1174 float64 _d_##n[(bits)/64]; \ 1175 } 1176 1177 typedef union { 1178 uint8_t _b[16]; 1179 uint16_t _w[8]; 1180 uint32_t _l[4]; 1181 uint64_t _q[2]; 1182 } XMMReg; 1183 1184 typedef union { 1185 uint8_t _b[32]; 1186 uint16_t _w[16]; 1187 uint32_t _l[8]; 1188 uint64_t _q[4]; 1189 } YMMReg; 1190 1191 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1192 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1193 1194 typedef struct BNDReg { 1195 uint64_t lb; 1196 uint64_t ub; 1197 } BNDReg; 1198 1199 typedef struct BNDCSReg { 1200 uint64_t cfgu; 1201 uint64_t sts; 1202 } BNDCSReg; 1203 1204 #define BNDCFG_ENABLE 1ULL 1205 #define BNDCFG_BNDPRESERVE 2ULL 1206 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1207 1208 #ifdef HOST_WORDS_BIGENDIAN 1209 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1210 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1211 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1212 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1213 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1214 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1215 1216 #define MMX_B(n) _b_MMXReg[7 - (n)] 1217 #define MMX_W(n) _w_MMXReg[3 - (n)] 1218 #define MMX_L(n) _l_MMXReg[1 - (n)] 1219 #define MMX_S(n) _s_MMXReg[1 - (n)] 1220 #else 1221 #define ZMM_B(n) _b_ZMMReg[n] 1222 #define ZMM_W(n) _w_ZMMReg[n] 1223 #define ZMM_L(n) _l_ZMMReg[n] 1224 #define ZMM_S(n) _s_ZMMReg[n] 1225 #define ZMM_Q(n) _q_ZMMReg[n] 1226 #define ZMM_D(n) _d_ZMMReg[n] 1227 1228 #define MMX_B(n) _b_MMXReg[n] 1229 #define MMX_W(n) _w_MMXReg[n] 1230 #define MMX_L(n) _l_MMXReg[n] 1231 #define MMX_S(n) _s_MMXReg[n] 1232 #endif 1233 #define MMX_Q(n) _q_MMXReg[n] 1234 1235 typedef union { 1236 floatx80 d __attribute__((aligned(16))); 1237 MMXReg mmx; 1238 } FPReg; 1239 1240 typedef struct { 1241 uint64_t base; 1242 uint64_t mask; 1243 } MTRRVar; 1244 1245 #define CPU_NB_REGS64 16 1246 #define CPU_NB_REGS32 8 1247 1248 #ifdef TARGET_X86_64 1249 #define CPU_NB_REGS CPU_NB_REGS64 1250 #else 1251 #define CPU_NB_REGS CPU_NB_REGS32 1252 #endif 1253 1254 #define MAX_FIXED_COUNTERS 3 1255 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1256 1257 #define TARGET_INSN_START_EXTRA_WORDS 1 1258 1259 #define NB_OPMASK_REGS 8 1260 1261 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1262 * that APIC ID hasn't been set yet 1263 */ 1264 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1265 1266 typedef union X86LegacyXSaveArea { 1267 struct { 1268 uint16_t fcw; 1269 uint16_t fsw; 1270 uint8_t ftw; 1271 uint8_t reserved; 1272 uint16_t fpop; 1273 uint64_t fpip; 1274 uint64_t fpdp; 1275 uint32_t mxcsr; 1276 uint32_t mxcsr_mask; 1277 FPReg fpregs[8]; 1278 uint8_t xmm_regs[16][16]; 1279 }; 1280 uint8_t data[512]; 1281 } X86LegacyXSaveArea; 1282 1283 typedef struct X86XSaveHeader { 1284 uint64_t xstate_bv; 1285 uint64_t xcomp_bv; 1286 uint64_t reserve0; 1287 uint8_t reserved[40]; 1288 } X86XSaveHeader; 1289 1290 /* Ext. save area 2: AVX State */ 1291 typedef struct XSaveAVX { 1292 uint8_t ymmh[16][16]; 1293 } XSaveAVX; 1294 1295 /* Ext. save area 3: BNDREG */ 1296 typedef struct XSaveBNDREG { 1297 BNDReg bnd_regs[4]; 1298 } XSaveBNDREG; 1299 1300 /* Ext. save area 4: BNDCSR */ 1301 typedef union XSaveBNDCSR { 1302 BNDCSReg bndcsr; 1303 uint8_t data[64]; 1304 } XSaveBNDCSR; 1305 1306 /* Ext. save area 5: Opmask */ 1307 typedef struct XSaveOpmask { 1308 uint64_t opmask_regs[NB_OPMASK_REGS]; 1309 } XSaveOpmask; 1310 1311 /* Ext. save area 6: ZMM_Hi256 */ 1312 typedef struct XSaveZMM_Hi256 { 1313 uint8_t zmm_hi256[16][32]; 1314 } XSaveZMM_Hi256; 1315 1316 /* Ext. save area 7: Hi16_ZMM */ 1317 typedef struct XSaveHi16_ZMM { 1318 uint8_t hi16_zmm[16][64]; 1319 } XSaveHi16_ZMM; 1320 1321 /* Ext. save area 9: PKRU state */ 1322 typedef struct XSavePKRU { 1323 uint32_t pkru; 1324 uint32_t padding; 1325 } XSavePKRU; 1326 1327 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1328 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1329 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1330 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1331 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1332 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1333 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1334 1335 typedef struct ExtSaveArea { 1336 uint32_t feature, bits; 1337 uint32_t offset, size; 1338 } ExtSaveArea; 1339 1340 #define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) 1341 1342 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; 1343 1344 typedef enum TPRAccess { 1345 TPR_ACCESS_READ, 1346 TPR_ACCESS_WRITE, 1347 } TPRAccess; 1348 1349 /* Cache information data structures: */ 1350 1351 enum CacheType { 1352 DATA_CACHE, 1353 INSTRUCTION_CACHE, 1354 UNIFIED_CACHE 1355 }; 1356 1357 typedef struct CPUCacheInfo { 1358 enum CacheType type; 1359 uint8_t level; 1360 /* Size in bytes */ 1361 uint32_t size; 1362 /* Line size, in bytes */ 1363 uint16_t line_size; 1364 /* 1365 * Associativity. 1366 * Note: representation of fully-associative caches is not implemented 1367 */ 1368 uint8_t associativity; 1369 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1370 uint8_t partitions; 1371 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1372 uint32_t sets; 1373 /* 1374 * Lines per tag. 1375 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1376 * (Is this synonym to @partitions?) 1377 */ 1378 uint8_t lines_per_tag; 1379 1380 /* Self-initializing cache */ 1381 bool self_init; 1382 /* 1383 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1384 * non-originating threads sharing this cache. 1385 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1386 */ 1387 bool no_invd_sharing; 1388 /* 1389 * Cache is inclusive of lower cache levels. 1390 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1391 */ 1392 bool inclusive; 1393 /* 1394 * A complex function is used to index the cache, potentially using all 1395 * address bits. CPUID[4].EDX[bit 2]. 1396 */ 1397 bool complex_indexing; 1398 } CPUCacheInfo; 1399 1400 1401 typedef struct CPUCaches { 1402 CPUCacheInfo *l1d_cache; 1403 CPUCacheInfo *l1i_cache; 1404 CPUCacheInfo *l2_cache; 1405 CPUCacheInfo *l3_cache; 1406 } CPUCaches; 1407 1408 typedef struct HVFX86LazyFlags { 1409 target_ulong result; 1410 target_ulong auxbits; 1411 } HVFX86LazyFlags; 1412 1413 typedef struct CPUX86State { 1414 /* standard registers */ 1415 target_ulong regs[CPU_NB_REGS]; 1416 target_ulong eip; 1417 target_ulong eflags; /* eflags register. During CPU emulation, CC 1418 flags and DF are set to zero because they are 1419 stored elsewhere */ 1420 1421 /* emulator internal eflags handling */ 1422 target_ulong cc_dst; 1423 target_ulong cc_src; 1424 target_ulong cc_src2; 1425 uint32_t cc_op; 1426 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1427 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1428 are known at translation time. */ 1429 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1430 1431 /* segments */ 1432 SegmentCache segs[6]; /* selector values */ 1433 SegmentCache ldt; 1434 SegmentCache tr; 1435 SegmentCache gdt; /* only base and limit are used */ 1436 SegmentCache idt; /* only base and limit are used */ 1437 1438 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1439 int32_t a20_mask; 1440 1441 BNDReg bnd_regs[4]; 1442 BNDCSReg bndcs_regs; 1443 uint64_t msr_bndcfgs; 1444 uint64_t efer; 1445 1446 /* Beginning of state preserved by INIT (dummy marker). */ 1447 struct {} start_init_save; 1448 1449 /* FPU state */ 1450 unsigned int fpstt; /* top of stack index */ 1451 uint16_t fpus; 1452 uint16_t fpuc; 1453 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1454 FPReg fpregs[8]; 1455 /* KVM-only so far */ 1456 uint16_t fpop; 1457 uint16_t fpcs; 1458 uint16_t fpds; 1459 uint64_t fpip; 1460 uint64_t fpdp; 1461 1462 /* emulator internal variables */ 1463 float_status fp_status; 1464 floatx80 ft0; 1465 1466 float_status mmx_status; /* for 3DNow! float ops */ 1467 float_status sse_status; 1468 uint32_t mxcsr; 1469 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1470 ZMMReg xmm_t0; 1471 MMXReg mmx_t0; 1472 1473 XMMReg ymmh_regs[CPU_NB_REGS]; 1474 1475 uint64_t opmask_regs[NB_OPMASK_REGS]; 1476 YMMReg zmmh_regs[CPU_NB_REGS]; 1477 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1478 1479 /* sysenter registers */ 1480 uint32_t sysenter_cs; 1481 target_ulong sysenter_esp; 1482 target_ulong sysenter_eip; 1483 uint64_t star; 1484 1485 uint64_t vm_hsave; 1486 1487 #ifdef TARGET_X86_64 1488 target_ulong lstar; 1489 target_ulong cstar; 1490 target_ulong fmask; 1491 target_ulong kernelgsbase; 1492 #endif 1493 1494 uint64_t tsc; 1495 uint64_t tsc_adjust; 1496 uint64_t tsc_deadline; 1497 uint64_t tsc_aux; 1498 1499 uint64_t xcr0; 1500 1501 uint64_t mcg_status; 1502 uint64_t msr_ia32_misc_enable; 1503 uint64_t msr_ia32_feature_control; 1504 1505 uint64_t msr_fixed_ctr_ctrl; 1506 uint64_t msr_global_ctrl; 1507 uint64_t msr_global_status; 1508 uint64_t msr_global_ovf_ctrl; 1509 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1510 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1511 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1512 1513 uint64_t pat; 1514 uint32_t smbase; 1515 uint64_t msr_smi_count; 1516 1517 uint32_t pkru; 1518 uint32_t pkrs; 1519 uint32_t tsx_ctrl; 1520 1521 uint64_t spec_ctrl; 1522 uint64_t virt_ssbd; 1523 1524 /* End of state preserved by INIT (dummy marker). */ 1525 struct {} end_init_save; 1526 1527 uint64_t system_time_msr; 1528 uint64_t wall_clock_msr; 1529 uint64_t steal_time_msr; 1530 uint64_t async_pf_en_msr; 1531 uint64_t async_pf_int_msr; 1532 uint64_t pv_eoi_en_msr; 1533 uint64_t poll_control_msr; 1534 1535 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1536 uint64_t msr_hv_hypercall; 1537 uint64_t msr_hv_guest_os_id; 1538 uint64_t msr_hv_tsc; 1539 1540 /* Per-VCPU HV MSRs */ 1541 uint64_t msr_hv_vapic; 1542 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1543 uint64_t msr_hv_runtime; 1544 uint64_t msr_hv_synic_control; 1545 uint64_t msr_hv_synic_evt_page; 1546 uint64_t msr_hv_synic_msg_page; 1547 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1548 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1549 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1550 uint64_t msr_hv_reenlightenment_control; 1551 uint64_t msr_hv_tsc_emulation_control; 1552 uint64_t msr_hv_tsc_emulation_status; 1553 1554 uint64_t msr_rtit_ctrl; 1555 uint64_t msr_rtit_status; 1556 uint64_t msr_rtit_output_base; 1557 uint64_t msr_rtit_output_mask; 1558 uint64_t msr_rtit_cr3_match; 1559 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1560 1561 /* exception/interrupt handling */ 1562 int error_code; 1563 int exception_is_int; 1564 target_ulong exception_next_eip; 1565 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1566 union { 1567 struct CPUBreakpoint *cpu_breakpoint[4]; 1568 struct CPUWatchpoint *cpu_watchpoint[4]; 1569 }; /* break/watchpoints for dr[0..3] */ 1570 int old_exception; /* exception in flight */ 1571 1572 uint64_t vm_vmcb; 1573 uint64_t tsc_offset; 1574 uint64_t intercept; 1575 uint16_t intercept_cr_read; 1576 uint16_t intercept_cr_write; 1577 uint16_t intercept_dr_read; 1578 uint16_t intercept_dr_write; 1579 uint32_t intercept_exceptions; 1580 uint64_t nested_cr3; 1581 uint32_t nested_pg_mode; 1582 uint8_t v_tpr; 1583 uint32_t int_ctl; 1584 1585 /* KVM states, automatically cleared on reset */ 1586 uint8_t nmi_injected; 1587 uint8_t nmi_pending; 1588 1589 uintptr_t retaddr; 1590 1591 /* Fields up to this point are cleared by a CPU reset */ 1592 struct {} end_reset_fields; 1593 1594 /* Fields after this point are preserved across CPU reset. */ 1595 1596 /* processor features (e.g. for CPUID insn) */ 1597 /* Minimum cpuid leaf 7 value */ 1598 uint32_t cpuid_level_func7; 1599 /* Actual cpuid leaf 7 value */ 1600 uint32_t cpuid_min_level_func7; 1601 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1602 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1603 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1604 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1605 /* Actual level/xlevel/xlevel2 value: */ 1606 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1607 uint32_t cpuid_vendor1; 1608 uint32_t cpuid_vendor2; 1609 uint32_t cpuid_vendor3; 1610 uint32_t cpuid_version; 1611 FeatureWordArray features; 1612 /* Features that were explicitly enabled/disabled */ 1613 FeatureWordArray user_features; 1614 uint32_t cpuid_model[12]; 1615 /* Cache information for CPUID. When legacy-cache=on, the cache data 1616 * on each CPUID leaf will be different, because we keep compatibility 1617 * with old QEMU versions. 1618 */ 1619 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1620 1621 /* MTRRs */ 1622 uint64_t mtrr_fixed[11]; 1623 uint64_t mtrr_deftype; 1624 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1625 1626 /* For KVM */ 1627 uint32_t mp_state; 1628 int32_t exception_nr; 1629 int32_t interrupt_injected; 1630 uint8_t soft_interrupt; 1631 uint8_t exception_pending; 1632 uint8_t exception_injected; 1633 uint8_t has_error_code; 1634 uint8_t exception_has_payload; 1635 uint64_t exception_payload; 1636 uint32_t ins_len; 1637 uint32_t sipi_vector; 1638 bool tsc_valid; 1639 int64_t tsc_khz; 1640 int64_t user_tsc_khz; /* for sanity check only */ 1641 uint64_t apic_bus_freq; 1642 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1643 void *xsave_buf; 1644 uint32_t xsave_buf_len; 1645 #endif 1646 #if defined(CONFIG_KVM) 1647 struct kvm_nested_state *nested_state; 1648 #endif 1649 #if defined(CONFIG_HVF) 1650 HVFX86LazyFlags hvf_lflags; 1651 void *hvf_mmio_buf; 1652 #endif 1653 1654 uint64_t mcg_cap; 1655 uint64_t mcg_ctl; 1656 uint64_t mcg_ext_ctl; 1657 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1658 uint64_t xstate_bv; 1659 1660 /* vmstate */ 1661 uint16_t fpus_vmstate; 1662 uint16_t fptag_vmstate; 1663 uint16_t fpregs_format_vmstate; 1664 1665 uint64_t xss; 1666 uint32_t umwait; 1667 1668 TPRAccess tpr_access_type; 1669 1670 unsigned nr_dies; 1671 } CPUX86State; 1672 1673 struct kvm_msrs; 1674 1675 /** 1676 * X86CPU: 1677 * @env: #CPUX86State 1678 * @migratable: If set, only migratable flags will be accepted when "enforce" 1679 * mode is used, and only migratable flags will be included in the "host" 1680 * CPU model. 1681 * 1682 * An x86 CPU. 1683 */ 1684 struct X86CPU { 1685 /*< private >*/ 1686 CPUState parent_obj; 1687 /*< public >*/ 1688 1689 CPUNegativeOffsetState neg; 1690 CPUX86State env; 1691 VMChangeStateEntry *vmsentry; 1692 1693 uint64_t ucode_rev; 1694 1695 uint32_t hyperv_spinlock_attempts; 1696 char *hyperv_vendor; 1697 bool hyperv_synic_kvm_only; 1698 uint64_t hyperv_features; 1699 bool hyperv_passthrough; 1700 OnOffAuto hyperv_no_nonarch_cs; 1701 uint32_t hyperv_vendor_id[3]; 1702 uint32_t hyperv_interface_id[4]; 1703 uint32_t hyperv_version_id[4]; 1704 uint32_t hyperv_limits[3]; 1705 uint32_t hyperv_nested[4]; 1706 1707 bool check_cpuid; 1708 bool enforce_cpuid; 1709 /* 1710 * Force features to be enabled even if the host doesn't support them. 1711 * This is dangerous and should be done only for testing CPUID 1712 * compatibility. 1713 */ 1714 bool force_features; 1715 bool expose_kvm; 1716 bool expose_tcg; 1717 bool migratable; 1718 bool migrate_smi_count; 1719 bool max_features; /* Enable all supported features automatically */ 1720 uint32_t apic_id; 1721 1722 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1723 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1724 bool vmware_cpuid_freq; 1725 1726 /* if true the CPUID code directly forward host cache leaves to the guest */ 1727 bool cache_info_passthrough; 1728 1729 /* if true the CPUID code directly forwards 1730 * host monitor/mwait leaves to the guest */ 1731 struct { 1732 uint32_t eax; 1733 uint32_t ebx; 1734 uint32_t ecx; 1735 uint32_t edx; 1736 } mwait; 1737 1738 /* Features that were filtered out because of missing host capabilities */ 1739 FeatureWordArray filtered_features; 1740 1741 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1742 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1743 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1744 * capabilities) directly to the guest. 1745 */ 1746 bool enable_pmu; 1747 1748 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1749 * disabled by default to avoid breaking migration between QEMU with 1750 * different LMCE configurations. 1751 */ 1752 bool enable_lmce; 1753 1754 /* Compatibility bits for old machine types. 1755 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1756 * socket share an virtual l3 cache. 1757 */ 1758 bool enable_l3_cache; 1759 1760 /* Compatibility bits for old machine types. 1761 * If true present the old cache topology information 1762 */ 1763 bool legacy_cache; 1764 1765 /* Compatibility bits for old machine types: */ 1766 bool enable_cpuid_0xb; 1767 1768 /* Enable auto level-increase for all CPUID leaves */ 1769 bool full_cpuid_auto_level; 1770 1771 /* Only advertise CPUID leaves defined by the vendor */ 1772 bool vendor_cpuid_only; 1773 1774 /* Enable auto level-increase for Intel Processor Trace leave */ 1775 bool intel_pt_auto_level; 1776 1777 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1778 bool fill_mtrr_mask; 1779 1780 /* if true override the phys_bits value with a value read from the host */ 1781 bool host_phys_bits; 1782 1783 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1784 uint8_t host_phys_bits_limit; 1785 1786 /* Stop SMI delivery for migration compatibility with old machines */ 1787 bool kvm_no_smi_migration; 1788 1789 /* Number of physical address bits supported */ 1790 uint32_t phys_bits; 1791 1792 /* in order to simplify APIC support, we leave this pointer to the 1793 user */ 1794 struct DeviceState *apic_state; 1795 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1796 Notifier machine_done; 1797 1798 struct kvm_msrs *kvm_msr_buf; 1799 1800 int32_t node_id; /* NUMA node this CPU belongs to */ 1801 int32_t socket_id; 1802 int32_t die_id; 1803 int32_t core_id; 1804 int32_t thread_id; 1805 1806 int32_t hv_max_vps; 1807 }; 1808 1809 1810 #ifndef CONFIG_USER_ONLY 1811 extern const VMStateDescription vmstate_x86_cpu; 1812 #endif 1813 1814 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1815 1816 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1817 int cpuid, void *opaque); 1818 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1819 int cpuid, void *opaque); 1820 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1821 void *opaque); 1822 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1823 void *opaque); 1824 1825 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1826 Error **errp); 1827 1828 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1829 1830 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1831 MemTxAttrs *attrs); 1832 1833 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1834 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1835 1836 void x86_cpu_list(void); 1837 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1838 1839 #ifndef CONFIG_USER_ONLY 1840 int cpu_get_pic_interrupt(CPUX86State *s); 1841 1842 /* MSDOS compatibility mode FPU exception support */ 1843 void x86_register_ferr_irq(qemu_irq irq); 1844 void fpu_check_raise_ferr_irq(CPUX86State *s); 1845 void cpu_set_ignne(void); 1846 void cpu_clear_ignne(void); 1847 #endif 1848 1849 /* mpx_helper.c */ 1850 void cpu_sync_bndcs_hflags(CPUX86State *env); 1851 1852 /* this function must always be used to load data in the segment 1853 cache: it synchronizes the hflags with the segment cache values */ 1854 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1855 X86Seg seg_reg, unsigned int selector, 1856 target_ulong base, 1857 unsigned int limit, 1858 unsigned int flags) 1859 { 1860 SegmentCache *sc; 1861 unsigned int new_hflags; 1862 1863 sc = &env->segs[seg_reg]; 1864 sc->selector = selector; 1865 sc->base = base; 1866 sc->limit = limit; 1867 sc->flags = flags; 1868 1869 /* update the hidden flags */ 1870 { 1871 if (seg_reg == R_CS) { 1872 #ifdef TARGET_X86_64 1873 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1874 /* long mode */ 1875 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1876 env->hflags &= ~(HF_ADDSEG_MASK); 1877 } else 1878 #endif 1879 { 1880 /* legacy / compatibility case */ 1881 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1882 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1883 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1884 new_hflags; 1885 } 1886 } 1887 if (seg_reg == R_SS) { 1888 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1889 #if HF_CPL_MASK != 3 1890 #error HF_CPL_MASK is hardcoded 1891 #endif 1892 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1893 /* Possibly switch between BNDCFGS and BNDCFGU */ 1894 cpu_sync_bndcs_hflags(env); 1895 } 1896 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1897 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1898 if (env->hflags & HF_CS64_MASK) { 1899 /* zero base assumed for DS, ES and SS in long mode */ 1900 } else if (!(env->cr[0] & CR0_PE_MASK) || 1901 (env->eflags & VM_MASK) || 1902 !(env->hflags & HF_CS32_MASK)) { 1903 /* XXX: try to avoid this test. The problem comes from the 1904 fact that is real mode or vm86 mode we only modify the 1905 'base' and 'selector' fields of the segment cache to go 1906 faster. A solution may be to force addseg to one in 1907 translate-i386.c. */ 1908 new_hflags |= HF_ADDSEG_MASK; 1909 } else { 1910 new_hflags |= ((env->segs[R_DS].base | 1911 env->segs[R_ES].base | 1912 env->segs[R_SS].base) != 0) << 1913 HF_ADDSEG_SHIFT; 1914 } 1915 env->hflags = (env->hflags & 1916 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1917 } 1918 } 1919 1920 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1921 uint8_t sipi_vector) 1922 { 1923 CPUState *cs = CPU(cpu); 1924 CPUX86State *env = &cpu->env; 1925 1926 env->eip = 0; 1927 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1928 sipi_vector << 12, 1929 env->segs[R_CS].limit, 1930 env->segs[R_CS].flags); 1931 cs->halted = 0; 1932 } 1933 1934 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1935 target_ulong *base, unsigned int *limit, 1936 unsigned int *flags); 1937 1938 /* op_helper.c */ 1939 /* used for debug or cpu save/restore */ 1940 1941 /* cpu-exec.c */ 1942 /* the following helpers are only usable in user mode simulation as 1943 they can trigger unexpected exceptions */ 1944 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); 1945 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1946 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1947 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1948 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1949 1950 /* you can call this signal handler from your SIGBUS and SIGSEGV 1951 signal handlers to inform the virtual CPU of exceptions. non zero 1952 is returned if the signal was handled by the virtual CPU. */ 1953 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1954 void *puc); 1955 1956 /* cpu.c */ 1957 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 1958 uint32_t vendor2, uint32_t vendor3); 1959 typedef struct PropValue { 1960 const char *prop, *value; 1961 } PropValue; 1962 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); 1963 1964 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env); 1965 1966 /* cpu.c other functions (cpuid) */ 1967 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1968 uint32_t *eax, uint32_t *ebx, 1969 uint32_t *ecx, uint32_t *edx); 1970 void cpu_clear_apic_feature(CPUX86State *env); 1971 void host_cpuid(uint32_t function, uint32_t count, 1972 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1973 1974 /* helper.c */ 1975 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1976 1977 #ifndef CONFIG_USER_ONLY 1978 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1979 { 1980 return !!attrs.secure; 1981 } 1982 1983 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1984 { 1985 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1986 } 1987 1988 /* 1989 * load efer and update the corresponding hflags. XXX: do consistency 1990 * checks with cpuid bits? 1991 */ 1992 void cpu_load_efer(CPUX86State *env, uint64_t val); 1993 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1994 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1995 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1996 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1997 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1998 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1999 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 2000 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 2001 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 2002 #endif 2003 2004 /* will be suppressed */ 2005 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 2006 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 2007 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 2008 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 2009 2010 /* hw/pc.c */ 2011 uint64_t cpu_get_tsc(CPUX86State *env); 2012 2013 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 2014 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 2015 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 2016 2017 #ifdef TARGET_X86_64 2018 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 2019 #else 2020 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 2021 #endif 2022 2023 #define cpu_signal_handler cpu_x86_signal_handler 2024 #define cpu_list x86_cpu_list 2025 2026 /* MMU modes definitions */ 2027 #define MMU_KSMAP_IDX 0 2028 #define MMU_USER_IDX 1 2029 #define MMU_KNOSMAP_IDX 2 2030 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 2031 { 2032 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 2033 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 2034 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2035 } 2036 2037 static inline int cpu_mmu_index_kernel(CPUX86State *env) 2038 { 2039 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 2040 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 2041 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2042 } 2043 2044 #define CC_DST (env->cc_dst) 2045 #define CC_SRC (env->cc_src) 2046 #define CC_SRC2 (env->cc_src2) 2047 #define CC_OP (env->cc_op) 2048 2049 typedef CPUX86State CPUArchState; 2050 typedef X86CPU ArchCPU; 2051 2052 #include "exec/cpu-all.h" 2053 #include "svm.h" 2054 2055 #if !defined(CONFIG_USER_ONLY) 2056 #include "hw/i386/apic.h" 2057 #endif 2058 2059 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2060 target_ulong *cs_base, uint32_t *flags) 2061 { 2062 *cs_base = env->segs[R_CS].base; 2063 *pc = *cs_base + env->eip; 2064 *flags = env->hflags | 2065 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2066 } 2067 2068 void do_cpu_init(X86CPU *cpu); 2069 void do_cpu_sipi(X86CPU *cpu); 2070 2071 #define MCE_INJECT_BROADCAST 1 2072 #define MCE_INJECT_UNCOND_AO 2 2073 2074 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2075 uint64_t status, uint64_t mcg_status, uint64_t addr, 2076 uint64_t misc, int flags); 2077 2078 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2079 2080 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2081 { 2082 uint32_t eflags = env->eflags; 2083 if (tcg_enabled()) { 2084 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 2085 } 2086 return eflags; 2087 } 2088 2089 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2090 { 2091 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2092 } 2093 2094 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2095 { 2096 if (env->hflags & HF_SMM_MASK) { 2097 return -1; 2098 } else { 2099 return env->a20_mask; 2100 } 2101 } 2102 2103 static inline bool cpu_has_vmx(CPUX86State *env) 2104 { 2105 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2106 } 2107 2108 static inline bool cpu_has_svm(CPUX86State *env) 2109 { 2110 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2111 } 2112 2113 /* 2114 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2115 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2116 * VMX operation. This is because CR4.VMXE is one of the bits set 2117 * in MSR_IA32_VMX_CR4_FIXED1. 2118 * 2119 * There is one exception to above statement when vCPU enters SMM mode. 2120 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2121 * may also reset CR4.VMXE during execution in SMM mode. 2122 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2123 * and CR4.VMXE is restored to it's original value of being set. 2124 * 2125 * Therefore, when vCPU is not in SMM mode, we can infer whether 2126 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2127 * know for certain. 2128 */ 2129 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2130 { 2131 return cpu_has_vmx(env) && 2132 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2133 } 2134 2135 /* excp_helper.c */ 2136 int get_pg_mode(CPUX86State *env); 2137 2138 /* fpu_helper.c */ 2139 void update_fp_status(CPUX86State *env); 2140 void update_mxcsr_status(CPUX86State *env); 2141 void update_mxcsr_from_sse_status(CPUX86State *env); 2142 2143 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2144 { 2145 env->mxcsr = mxcsr; 2146 if (tcg_enabled()) { 2147 update_mxcsr_status(env); 2148 } 2149 } 2150 2151 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2152 { 2153 env->fpuc = fpuc; 2154 if (tcg_enabled()) { 2155 update_fp_status(env); 2156 } 2157 } 2158 2159 /* mem_helper.c */ 2160 void helper_lock_init(void); 2161 2162 /* svm_helper.c */ 2163 #ifdef CONFIG_USER_ONLY 2164 static inline void 2165 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2166 uint64_t param, uintptr_t retaddr) 2167 { /* no-op */ } 2168 static inline bool 2169 cpu_svm_has_intercept(CPUX86State *env, uint32_t type) 2170 { return false; } 2171 #else 2172 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2173 uint64_t param, uintptr_t retaddr); 2174 bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); 2175 #endif 2176 2177 /* apic.c */ 2178 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2179 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2180 TPRAccess access); 2181 2182 /* Special values for X86CPUVersion: */ 2183 2184 /* Resolve to latest CPU version */ 2185 #define CPU_VERSION_LATEST -1 2186 2187 /* 2188 * Resolve to version defined by current machine type. 2189 * See x86_cpu_set_default_version() 2190 */ 2191 #define CPU_VERSION_AUTO -2 2192 2193 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2194 #define CPU_VERSION_LEGACY 0 2195 2196 typedef int X86CPUVersion; 2197 2198 /* 2199 * Set default CPU model version for CPU models having 2200 * version == CPU_VERSION_AUTO. 2201 */ 2202 void x86_cpu_set_default_version(X86CPUVersion version); 2203 2204 #define APIC_DEFAULT_ADDRESS 0xfee00000 2205 #define APIC_SPACE_SIZE 0x100000 2206 2207 /* cpu-dump.c */ 2208 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2209 2210 /* cpu.c */ 2211 bool cpu_is_bsp(X86CPU *cpu); 2212 2213 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen); 2214 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); 2215 void x86_update_hflags(CPUX86State* env); 2216 2217 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2218 { 2219 return !!(cpu->hyperv_features & BIT(feat)); 2220 } 2221 2222 static inline uint64_t cr4_reserved_bits(CPUX86State *env) 2223 { 2224 uint64_t reserved_bits = CR4_RESERVED_MASK; 2225 if (!env->features[FEAT_XSAVE]) { 2226 reserved_bits |= CR4_OSXSAVE_MASK; 2227 } 2228 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) { 2229 reserved_bits |= CR4_SMEP_MASK; 2230 } 2231 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { 2232 reserved_bits |= CR4_SMAP_MASK; 2233 } 2234 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) { 2235 reserved_bits |= CR4_FSGSBASE_MASK; 2236 } 2237 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { 2238 reserved_bits |= CR4_PKE_MASK; 2239 } 2240 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) { 2241 reserved_bits |= CR4_LA57_MASK; 2242 } 2243 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { 2244 reserved_bits |= CR4_UMIP_MASK; 2245 } 2246 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { 2247 reserved_bits |= CR4_PKS_MASK; 2248 } 2249 return reserved_bits; 2250 } 2251 2252 static inline bool ctl_has_irq(CPUX86State *env) 2253 { 2254 uint32_t int_prio; 2255 uint32_t tpr; 2256 2257 int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; 2258 tpr = env->int_ctl & V_TPR_MASK; 2259 2260 if (env->int_ctl & V_IGN_TPR_MASK) { 2261 return (env->int_ctl & V_IRQ_MASK); 2262 } 2263 2264 return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr); 2265 } 2266 2267 hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, 2268 int *prot); 2269 #if defined(TARGET_X86_64) && \ 2270 defined(CONFIG_USER_ONLY) && \ 2271 defined(CONFIG_LINUX) 2272 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2273 #endif 2274 2275 #endif /* I386_CPU_H */ 2276