1 2 /* 3 * i386 virtual CPU header 4 * 5 * Copyright (c) 2003 Fabrice Bellard 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef I386_CPU_H 22 #define I386_CPU_H 23 24 #include "qemu-common.h" 25 #include "cpu-qom.h" 26 #include "hyperv-proto.h" 27 28 #ifdef TARGET_X86_64 29 #define TARGET_LONG_BITS 64 30 #else 31 #define TARGET_LONG_BITS 32 32 #endif 33 34 #include "exec/cpu-defs.h" 35 36 /* The x86 has a strong memory model with some store-after-load re-ordering */ 37 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 38 39 /* Maximum instruction code size */ 40 #define TARGET_MAX_INSN_SIZE 16 41 42 /* support for self modifying code even if the modified instruction is 43 close to the modifying instruction */ 44 #define TARGET_HAS_PRECISE_SMC 45 46 #ifdef TARGET_X86_64 47 #define I386_ELF_MACHINE EM_X86_64 48 #define ELF_MACHINE_UNAME "x86_64" 49 #else 50 #define I386_ELF_MACHINE EM_386 51 #define ELF_MACHINE_UNAME "i686" 52 #endif 53 54 #define CPUArchState struct CPUX86State 55 56 enum { 57 R_EAX = 0, 58 R_ECX = 1, 59 R_EDX = 2, 60 R_EBX = 3, 61 R_ESP = 4, 62 R_EBP = 5, 63 R_ESI = 6, 64 R_EDI = 7, 65 R_R8 = 8, 66 R_R9 = 9, 67 R_R10 = 10, 68 R_R11 = 11, 69 R_R12 = 12, 70 R_R13 = 13, 71 R_R14 = 14, 72 R_R15 = 15, 73 74 R_AL = 0, 75 R_CL = 1, 76 R_DL = 2, 77 R_BL = 3, 78 R_AH = 4, 79 R_CH = 5, 80 R_DH = 6, 81 R_BH = 7, 82 }; 83 84 typedef enum X86Seg { 85 R_ES = 0, 86 R_CS = 1, 87 R_SS = 2, 88 R_DS = 3, 89 R_FS = 4, 90 R_GS = 5, 91 R_LDTR = 6, 92 R_TR = 7, 93 } X86Seg; 94 95 /* segment descriptor fields */ 96 #define DESC_G_SHIFT 23 97 #define DESC_G_MASK (1 << DESC_G_SHIFT) 98 #define DESC_B_SHIFT 22 99 #define DESC_B_MASK (1 << DESC_B_SHIFT) 100 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 101 #define DESC_L_MASK (1 << DESC_L_SHIFT) 102 #define DESC_AVL_SHIFT 20 103 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 104 #define DESC_P_SHIFT 15 105 #define DESC_P_MASK (1 << DESC_P_SHIFT) 106 #define DESC_DPL_SHIFT 13 107 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 108 #define DESC_S_SHIFT 12 109 #define DESC_S_MASK (1 << DESC_S_SHIFT) 110 #define DESC_TYPE_SHIFT 8 111 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 112 #define DESC_A_MASK (1 << 8) 113 114 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 115 #define DESC_C_MASK (1 << 10) /* code: conforming */ 116 #define DESC_R_MASK (1 << 9) /* code: readable */ 117 118 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 119 #define DESC_W_MASK (1 << 9) /* data: writable */ 120 121 #define DESC_TSS_BUSY_MASK (1 << 9) 122 123 /* eflags masks */ 124 #define CC_C 0x0001 125 #define CC_P 0x0004 126 #define CC_A 0x0010 127 #define CC_Z 0x0040 128 #define CC_S 0x0080 129 #define CC_O 0x0800 130 131 #define TF_SHIFT 8 132 #define IOPL_SHIFT 12 133 #define VM_SHIFT 17 134 135 #define TF_MASK 0x00000100 136 #define IF_MASK 0x00000200 137 #define DF_MASK 0x00000400 138 #define IOPL_MASK 0x00003000 139 #define NT_MASK 0x00004000 140 #define RF_MASK 0x00010000 141 #define VM_MASK 0x00020000 142 #define AC_MASK 0x00040000 143 #define VIF_MASK 0x00080000 144 #define VIP_MASK 0x00100000 145 #define ID_MASK 0x00200000 146 147 /* hidden flags - used internally by qemu to represent additional cpu 148 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 149 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 150 positions to ease oring with eflags. */ 151 /* current cpl */ 152 #define HF_CPL_SHIFT 0 153 /* true if hardware interrupts must be disabled for next instruction */ 154 #define HF_INHIBIT_IRQ_SHIFT 3 155 /* 16 or 32 segments */ 156 #define HF_CS32_SHIFT 4 157 #define HF_SS32_SHIFT 5 158 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 159 #define HF_ADDSEG_SHIFT 6 160 /* copy of CR0.PE (protected mode) */ 161 #define HF_PE_SHIFT 7 162 #define HF_TF_SHIFT 8 /* must be same as eflags */ 163 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 164 #define HF_EM_SHIFT 10 165 #define HF_TS_SHIFT 11 166 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 167 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 168 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 169 #define HF_RF_SHIFT 16 /* must be same as eflags */ 170 #define HF_VM_SHIFT 17 /* must be same as eflags */ 171 #define HF_AC_SHIFT 18 /* must be same as eflags */ 172 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 173 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 174 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 175 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 176 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 177 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 178 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 179 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 180 181 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 182 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 183 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 184 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 185 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 186 #define HF_PE_MASK (1 << HF_PE_SHIFT) 187 #define HF_TF_MASK (1 << HF_TF_SHIFT) 188 #define HF_MP_MASK (1 << HF_MP_SHIFT) 189 #define HF_EM_MASK (1 << HF_EM_SHIFT) 190 #define HF_TS_MASK (1 << HF_TS_SHIFT) 191 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 192 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 193 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 194 #define HF_RF_MASK (1 << HF_RF_SHIFT) 195 #define HF_VM_MASK (1 << HF_VM_SHIFT) 196 #define HF_AC_MASK (1 << HF_AC_SHIFT) 197 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 198 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 199 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 200 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 201 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 202 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 203 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 204 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 205 206 /* hflags2 */ 207 208 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 209 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 210 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 211 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 212 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 213 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 214 215 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 216 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 217 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 218 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 219 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 220 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 221 222 #define CR0_PE_SHIFT 0 223 #define CR0_MP_SHIFT 1 224 225 #define CR0_PE_MASK (1U << 0) 226 #define CR0_MP_MASK (1U << 1) 227 #define CR0_EM_MASK (1U << 2) 228 #define CR0_TS_MASK (1U << 3) 229 #define CR0_ET_MASK (1U << 4) 230 #define CR0_NE_MASK (1U << 5) 231 #define CR0_WP_MASK (1U << 16) 232 #define CR0_AM_MASK (1U << 18) 233 #define CR0_PG_MASK (1U << 31) 234 235 #define CR4_VME_MASK (1U << 0) 236 #define CR4_PVI_MASK (1U << 1) 237 #define CR4_TSD_MASK (1U << 2) 238 #define CR4_DE_MASK (1U << 3) 239 #define CR4_PSE_MASK (1U << 4) 240 #define CR4_PAE_MASK (1U << 5) 241 #define CR4_MCE_MASK (1U << 6) 242 #define CR4_PGE_MASK (1U << 7) 243 #define CR4_PCE_MASK (1U << 8) 244 #define CR4_OSFXSR_SHIFT 9 245 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 246 #define CR4_OSXMMEXCPT_MASK (1U << 10) 247 #define CR4_LA57_MASK (1U << 12) 248 #define CR4_VMXE_MASK (1U << 13) 249 #define CR4_SMXE_MASK (1U << 14) 250 #define CR4_FSGSBASE_MASK (1U << 16) 251 #define CR4_PCIDE_MASK (1U << 17) 252 #define CR4_OSXSAVE_MASK (1U << 18) 253 #define CR4_SMEP_MASK (1U << 20) 254 #define CR4_SMAP_MASK (1U << 21) 255 #define CR4_PKE_MASK (1U << 22) 256 257 #define DR6_BD (1 << 13) 258 #define DR6_BS (1 << 14) 259 #define DR6_BT (1 << 15) 260 #define DR6_FIXED_1 0xffff0ff0 261 262 #define DR7_GD (1 << 13) 263 #define DR7_TYPE_SHIFT 16 264 #define DR7_LEN_SHIFT 18 265 #define DR7_FIXED_1 0x00000400 266 #define DR7_GLOBAL_BP_MASK 0xaa 267 #define DR7_LOCAL_BP_MASK 0x55 268 #define DR7_MAX_BP 4 269 #define DR7_TYPE_BP_INST 0x0 270 #define DR7_TYPE_DATA_WR 0x1 271 #define DR7_TYPE_IO_RW 0x2 272 #define DR7_TYPE_DATA_RW 0x3 273 274 #define PG_PRESENT_BIT 0 275 #define PG_RW_BIT 1 276 #define PG_USER_BIT 2 277 #define PG_PWT_BIT 3 278 #define PG_PCD_BIT 4 279 #define PG_ACCESSED_BIT 5 280 #define PG_DIRTY_BIT 6 281 #define PG_PSE_BIT 7 282 #define PG_GLOBAL_BIT 8 283 #define PG_PSE_PAT_BIT 12 284 #define PG_PKRU_BIT 59 285 #define PG_NX_BIT 63 286 287 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 288 #define PG_RW_MASK (1 << PG_RW_BIT) 289 #define PG_USER_MASK (1 << PG_USER_BIT) 290 #define PG_PWT_MASK (1 << PG_PWT_BIT) 291 #define PG_PCD_MASK (1 << PG_PCD_BIT) 292 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 293 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 294 #define PG_PSE_MASK (1 << PG_PSE_BIT) 295 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 296 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 297 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 298 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 299 #define PG_HI_USER_MASK 0x7ff0000000000000LL 300 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 301 #define PG_NX_MASK (1ULL << PG_NX_BIT) 302 303 #define PG_ERROR_W_BIT 1 304 305 #define PG_ERROR_P_MASK 0x01 306 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 307 #define PG_ERROR_U_MASK 0x04 308 #define PG_ERROR_RSVD_MASK 0x08 309 #define PG_ERROR_I_D_MASK 0x10 310 #define PG_ERROR_PK_MASK 0x20 311 312 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 313 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 314 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 315 316 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 317 #define MCE_BANKS_DEF 10 318 319 #define MCG_CAP_BANKS_MASK 0xff 320 321 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 322 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 323 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 324 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 325 326 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 327 328 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 329 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 330 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 331 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 332 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 333 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 334 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 335 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 336 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 337 338 /* MISC register defines */ 339 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 340 #define MCM_ADDR_LINEAR 1 /* linear address */ 341 #define MCM_ADDR_PHYS 2 /* physical address */ 342 #define MCM_ADDR_MEM 3 /* memory address */ 343 #define MCM_ADDR_GENERIC 7 /* generic */ 344 345 #define MSR_IA32_TSC 0x10 346 #define MSR_IA32_APICBASE 0x1b 347 #define MSR_IA32_APICBASE_BSP (1<<8) 348 #define MSR_IA32_APICBASE_ENABLE (1<<11) 349 #define MSR_IA32_APICBASE_EXTD (1 << 10) 350 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 351 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 352 #define MSR_TSC_ADJUST 0x0000003b 353 #define MSR_IA32_SPEC_CTRL 0x48 354 #define MSR_IA32_TSCDEADLINE 0x6e0 355 356 #define FEATURE_CONTROL_LOCKED (1<<0) 357 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 358 #define FEATURE_CONTROL_LMCE (1<<20) 359 360 #define MSR_P6_PERFCTR0 0xc1 361 362 #define MSR_IA32_SMBASE 0x9e 363 #define MSR_SMI_COUNT 0x34 364 #define MSR_MTRRcap 0xfe 365 #define MSR_MTRRcap_VCNT 8 366 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 367 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 368 369 #define MSR_IA32_SYSENTER_CS 0x174 370 #define MSR_IA32_SYSENTER_ESP 0x175 371 #define MSR_IA32_SYSENTER_EIP 0x176 372 373 #define MSR_MCG_CAP 0x179 374 #define MSR_MCG_STATUS 0x17a 375 #define MSR_MCG_CTL 0x17b 376 #define MSR_MCG_EXT_CTL 0x4d0 377 378 #define MSR_P6_EVNTSEL0 0x186 379 380 #define MSR_IA32_PERF_STATUS 0x198 381 382 #define MSR_IA32_MISC_ENABLE 0x1a0 383 /* Indicates good rep/movs microcode on some processors: */ 384 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 385 386 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 387 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 388 389 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 390 391 #define MSR_MTRRfix64K_00000 0x250 392 #define MSR_MTRRfix16K_80000 0x258 393 #define MSR_MTRRfix16K_A0000 0x259 394 #define MSR_MTRRfix4K_C0000 0x268 395 #define MSR_MTRRfix4K_C8000 0x269 396 #define MSR_MTRRfix4K_D0000 0x26a 397 #define MSR_MTRRfix4K_D8000 0x26b 398 #define MSR_MTRRfix4K_E0000 0x26c 399 #define MSR_MTRRfix4K_E8000 0x26d 400 #define MSR_MTRRfix4K_F0000 0x26e 401 #define MSR_MTRRfix4K_F8000 0x26f 402 403 #define MSR_PAT 0x277 404 405 #define MSR_MTRRdefType 0x2ff 406 407 #define MSR_CORE_PERF_FIXED_CTR0 0x309 408 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 409 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 410 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 411 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 412 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 413 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 414 415 #define MSR_MC0_CTL 0x400 416 #define MSR_MC0_STATUS 0x401 417 #define MSR_MC0_ADDR 0x402 418 #define MSR_MC0_MISC 0x403 419 420 #define MSR_EFER 0xc0000080 421 422 #define MSR_EFER_SCE (1 << 0) 423 #define MSR_EFER_LME (1 << 8) 424 #define MSR_EFER_LMA (1 << 10) 425 #define MSR_EFER_NXE (1 << 11) 426 #define MSR_EFER_SVME (1 << 12) 427 #define MSR_EFER_FFXSR (1 << 14) 428 429 #define MSR_STAR 0xc0000081 430 #define MSR_LSTAR 0xc0000082 431 #define MSR_CSTAR 0xc0000083 432 #define MSR_FMASK 0xc0000084 433 #define MSR_FSBASE 0xc0000100 434 #define MSR_GSBASE 0xc0000101 435 #define MSR_KERNELGSBASE 0xc0000102 436 #define MSR_TSC_AUX 0xc0000103 437 438 #define MSR_VM_HSAVE_PA 0xc0010117 439 440 #define MSR_IA32_BNDCFGS 0x00000d90 441 #define MSR_IA32_XSS 0x00000da0 442 443 #define XSTATE_FP_BIT 0 444 #define XSTATE_SSE_BIT 1 445 #define XSTATE_YMM_BIT 2 446 #define XSTATE_BNDREGS_BIT 3 447 #define XSTATE_BNDCSR_BIT 4 448 #define XSTATE_OPMASK_BIT 5 449 #define XSTATE_ZMM_Hi256_BIT 6 450 #define XSTATE_Hi16_ZMM_BIT 7 451 #define XSTATE_PKRU_BIT 9 452 453 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 454 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 455 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 456 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 457 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 458 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 459 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 460 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 461 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 462 463 /* CPUID feature words */ 464 typedef enum FeatureWord { 465 FEAT_1_EDX, /* CPUID[1].EDX */ 466 FEAT_1_ECX, /* CPUID[1].ECX */ 467 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 468 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 469 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 470 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 471 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 472 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 473 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 474 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 475 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 476 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 477 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 478 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 479 FEAT_SVM, /* CPUID[8000_000A].EDX */ 480 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 481 FEAT_6_EAX, /* CPUID[6].EAX */ 482 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 483 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 484 FEATURE_WORDS, 485 } FeatureWord; 486 487 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 488 489 /* cpuid_features bits */ 490 #define CPUID_FP87 (1U << 0) 491 #define CPUID_VME (1U << 1) 492 #define CPUID_DE (1U << 2) 493 #define CPUID_PSE (1U << 3) 494 #define CPUID_TSC (1U << 4) 495 #define CPUID_MSR (1U << 5) 496 #define CPUID_PAE (1U << 6) 497 #define CPUID_MCE (1U << 7) 498 #define CPUID_CX8 (1U << 8) 499 #define CPUID_APIC (1U << 9) 500 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 501 #define CPUID_MTRR (1U << 12) 502 #define CPUID_PGE (1U << 13) 503 #define CPUID_MCA (1U << 14) 504 #define CPUID_CMOV (1U << 15) 505 #define CPUID_PAT (1U << 16) 506 #define CPUID_PSE36 (1U << 17) 507 #define CPUID_PN (1U << 18) 508 #define CPUID_CLFLUSH (1U << 19) 509 #define CPUID_DTS (1U << 21) 510 #define CPUID_ACPI (1U << 22) 511 #define CPUID_MMX (1U << 23) 512 #define CPUID_FXSR (1U << 24) 513 #define CPUID_SSE (1U << 25) 514 #define CPUID_SSE2 (1U << 26) 515 #define CPUID_SS (1U << 27) 516 #define CPUID_HT (1U << 28) 517 #define CPUID_TM (1U << 29) 518 #define CPUID_IA64 (1U << 30) 519 #define CPUID_PBE (1U << 31) 520 521 #define CPUID_EXT_SSE3 (1U << 0) 522 #define CPUID_EXT_PCLMULQDQ (1U << 1) 523 #define CPUID_EXT_DTES64 (1U << 2) 524 #define CPUID_EXT_MONITOR (1U << 3) 525 #define CPUID_EXT_DSCPL (1U << 4) 526 #define CPUID_EXT_VMX (1U << 5) 527 #define CPUID_EXT_SMX (1U << 6) 528 #define CPUID_EXT_EST (1U << 7) 529 #define CPUID_EXT_TM2 (1U << 8) 530 #define CPUID_EXT_SSSE3 (1U << 9) 531 #define CPUID_EXT_CID (1U << 10) 532 #define CPUID_EXT_FMA (1U << 12) 533 #define CPUID_EXT_CX16 (1U << 13) 534 #define CPUID_EXT_XTPR (1U << 14) 535 #define CPUID_EXT_PDCM (1U << 15) 536 #define CPUID_EXT_PCID (1U << 17) 537 #define CPUID_EXT_DCA (1U << 18) 538 #define CPUID_EXT_SSE41 (1U << 19) 539 #define CPUID_EXT_SSE42 (1U << 20) 540 #define CPUID_EXT_X2APIC (1U << 21) 541 #define CPUID_EXT_MOVBE (1U << 22) 542 #define CPUID_EXT_POPCNT (1U << 23) 543 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 544 #define CPUID_EXT_AES (1U << 25) 545 #define CPUID_EXT_XSAVE (1U << 26) 546 #define CPUID_EXT_OSXSAVE (1U << 27) 547 #define CPUID_EXT_AVX (1U << 28) 548 #define CPUID_EXT_F16C (1U << 29) 549 #define CPUID_EXT_RDRAND (1U << 30) 550 #define CPUID_EXT_HYPERVISOR (1U << 31) 551 552 #define CPUID_EXT2_FPU (1U << 0) 553 #define CPUID_EXT2_VME (1U << 1) 554 #define CPUID_EXT2_DE (1U << 2) 555 #define CPUID_EXT2_PSE (1U << 3) 556 #define CPUID_EXT2_TSC (1U << 4) 557 #define CPUID_EXT2_MSR (1U << 5) 558 #define CPUID_EXT2_PAE (1U << 6) 559 #define CPUID_EXT2_MCE (1U << 7) 560 #define CPUID_EXT2_CX8 (1U << 8) 561 #define CPUID_EXT2_APIC (1U << 9) 562 #define CPUID_EXT2_SYSCALL (1U << 11) 563 #define CPUID_EXT2_MTRR (1U << 12) 564 #define CPUID_EXT2_PGE (1U << 13) 565 #define CPUID_EXT2_MCA (1U << 14) 566 #define CPUID_EXT2_CMOV (1U << 15) 567 #define CPUID_EXT2_PAT (1U << 16) 568 #define CPUID_EXT2_PSE36 (1U << 17) 569 #define CPUID_EXT2_MP (1U << 19) 570 #define CPUID_EXT2_NX (1U << 20) 571 #define CPUID_EXT2_MMXEXT (1U << 22) 572 #define CPUID_EXT2_MMX (1U << 23) 573 #define CPUID_EXT2_FXSR (1U << 24) 574 #define CPUID_EXT2_FFXSR (1U << 25) 575 #define CPUID_EXT2_PDPE1GB (1U << 26) 576 #define CPUID_EXT2_RDTSCP (1U << 27) 577 #define CPUID_EXT2_LM (1U << 29) 578 #define CPUID_EXT2_3DNOWEXT (1U << 30) 579 #define CPUID_EXT2_3DNOW (1U << 31) 580 581 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 582 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 583 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 584 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 585 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 586 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 587 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 588 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 589 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 590 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 591 592 #define CPUID_EXT3_LAHF_LM (1U << 0) 593 #define CPUID_EXT3_CMP_LEG (1U << 1) 594 #define CPUID_EXT3_SVM (1U << 2) 595 #define CPUID_EXT3_EXTAPIC (1U << 3) 596 #define CPUID_EXT3_CR8LEG (1U << 4) 597 #define CPUID_EXT3_ABM (1U << 5) 598 #define CPUID_EXT3_SSE4A (1U << 6) 599 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 600 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 601 #define CPUID_EXT3_OSVW (1U << 9) 602 #define CPUID_EXT3_IBS (1U << 10) 603 #define CPUID_EXT3_XOP (1U << 11) 604 #define CPUID_EXT3_SKINIT (1U << 12) 605 #define CPUID_EXT3_WDT (1U << 13) 606 #define CPUID_EXT3_LWP (1U << 15) 607 #define CPUID_EXT3_FMA4 (1U << 16) 608 #define CPUID_EXT3_TCE (1U << 17) 609 #define CPUID_EXT3_NODEID (1U << 19) 610 #define CPUID_EXT3_TBM (1U << 21) 611 #define CPUID_EXT3_TOPOEXT (1U << 22) 612 #define CPUID_EXT3_PERFCORE (1U << 23) 613 #define CPUID_EXT3_PERFNB (1U << 24) 614 615 #define CPUID_SVM_NPT (1U << 0) 616 #define CPUID_SVM_LBRV (1U << 1) 617 #define CPUID_SVM_SVMLOCK (1U << 2) 618 #define CPUID_SVM_NRIPSAVE (1U << 3) 619 #define CPUID_SVM_TSCSCALE (1U << 4) 620 #define CPUID_SVM_VMCBCLEAN (1U << 5) 621 #define CPUID_SVM_FLUSHASID (1U << 6) 622 #define CPUID_SVM_DECODEASSIST (1U << 7) 623 #define CPUID_SVM_PAUSEFILTER (1U << 10) 624 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 625 626 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 627 #define CPUID_7_0_EBX_BMI1 (1U << 3) 628 #define CPUID_7_0_EBX_HLE (1U << 4) 629 #define CPUID_7_0_EBX_AVX2 (1U << 5) 630 #define CPUID_7_0_EBX_SMEP (1U << 7) 631 #define CPUID_7_0_EBX_BMI2 (1U << 8) 632 #define CPUID_7_0_EBX_ERMS (1U << 9) 633 #define CPUID_7_0_EBX_INVPCID (1U << 10) 634 #define CPUID_7_0_EBX_RTM (1U << 11) 635 #define CPUID_7_0_EBX_MPX (1U << 14) 636 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 637 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 638 #define CPUID_7_0_EBX_RDSEED (1U << 18) 639 #define CPUID_7_0_EBX_ADX (1U << 19) 640 #define CPUID_7_0_EBX_SMAP (1U << 20) 641 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 642 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 643 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 644 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 645 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 646 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 647 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 648 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 649 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 650 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 651 652 #define CPUID_7_0_ECX_AVX512BMI (1U << 1) 653 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 654 #define CPUID_7_0_ECX_UMIP (1U << 2) 655 #define CPUID_7_0_ECX_PKU (1U << 3) 656 #define CPUID_7_0_ECX_OSPKE (1U << 4) 657 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ 658 #define CPUID_7_0_ECX_GFNI (1U << 8) 659 #define CPUID_7_0_ECX_VAES (1U << 9) 660 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 661 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 662 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 663 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 664 #define CPUID_7_0_ECX_LA57 (1U << 16) 665 #define CPUID_7_0_ECX_RDPID (1U << 22) 666 667 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 668 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 669 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ 670 671 #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ 672 673 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 674 #define CPUID_XSAVE_XSAVEC (1U << 1) 675 #define CPUID_XSAVE_XGETBV1 (1U << 2) 676 #define CPUID_XSAVE_XSAVES (1U << 3) 677 678 #define CPUID_6_EAX_ARAT (1U << 2) 679 680 /* CPUID[0x80000007].EDX flags: */ 681 #define CPUID_APM_INVTSC (1U << 8) 682 683 #define CPUID_VENDOR_SZ 12 684 685 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 686 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 687 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 688 #define CPUID_VENDOR_INTEL "GenuineIntel" 689 690 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 691 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 692 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 693 #define CPUID_VENDOR_AMD "AuthenticAMD" 694 695 #define CPUID_VENDOR_VIA "CentaurHauls" 696 697 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 698 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 699 700 /* CPUID[0xB].ECX level types */ 701 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 702 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 703 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 704 705 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 706 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 707 #endif 708 709 #define EXCP00_DIVZ 0 710 #define EXCP01_DB 1 711 #define EXCP02_NMI 2 712 #define EXCP03_INT3 3 713 #define EXCP04_INTO 4 714 #define EXCP05_BOUND 5 715 #define EXCP06_ILLOP 6 716 #define EXCP07_PREX 7 717 #define EXCP08_DBLE 8 718 #define EXCP09_XERR 9 719 #define EXCP0A_TSS 10 720 #define EXCP0B_NOSEG 11 721 #define EXCP0C_STACK 12 722 #define EXCP0D_GPF 13 723 #define EXCP0E_PAGE 14 724 #define EXCP10_COPR 16 725 #define EXCP11_ALGN 17 726 #define EXCP12_MCHK 18 727 728 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 729 for syscall instruction */ 730 #define EXCP_VMEXIT 0x100 731 732 /* i386-specific interrupt pending bits. */ 733 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 734 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 735 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 736 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 737 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 738 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 739 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 740 741 /* Use a clearer name for this. */ 742 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 743 744 /* Instead of computing the condition codes after each x86 instruction, 745 * QEMU just stores one operand (called CC_SRC), the result 746 * (called CC_DST) and the type of operation (called CC_OP). When the 747 * condition codes are needed, the condition codes can be calculated 748 * using this information. Condition codes are not generated if they 749 * are only needed for conditional branches. 750 */ 751 typedef enum { 752 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 753 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 754 755 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 756 CC_OP_MULW, 757 CC_OP_MULL, 758 CC_OP_MULQ, 759 760 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 761 CC_OP_ADDW, 762 CC_OP_ADDL, 763 CC_OP_ADDQ, 764 765 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 766 CC_OP_ADCW, 767 CC_OP_ADCL, 768 CC_OP_ADCQ, 769 770 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 771 CC_OP_SUBW, 772 CC_OP_SUBL, 773 CC_OP_SUBQ, 774 775 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 776 CC_OP_SBBW, 777 CC_OP_SBBL, 778 CC_OP_SBBQ, 779 780 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 781 CC_OP_LOGICW, 782 CC_OP_LOGICL, 783 CC_OP_LOGICQ, 784 785 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 786 CC_OP_INCW, 787 CC_OP_INCL, 788 CC_OP_INCQ, 789 790 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 791 CC_OP_DECW, 792 CC_OP_DECL, 793 CC_OP_DECQ, 794 795 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 796 CC_OP_SHLW, 797 CC_OP_SHLL, 798 CC_OP_SHLQ, 799 800 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 801 CC_OP_SARW, 802 CC_OP_SARL, 803 CC_OP_SARQ, 804 805 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 806 CC_OP_BMILGW, 807 CC_OP_BMILGL, 808 CC_OP_BMILGQ, 809 810 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 811 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 812 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 813 814 CC_OP_CLR, /* Z set, all other flags clear. */ 815 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 816 817 CC_OP_NB, 818 } CCOp; 819 820 typedef struct SegmentCache { 821 uint32_t selector; 822 target_ulong base; 823 uint32_t limit; 824 uint32_t flags; 825 } SegmentCache; 826 827 #define MMREG_UNION(n, bits) \ 828 union n { \ 829 uint8_t _b_##n[(bits)/8]; \ 830 uint16_t _w_##n[(bits)/16]; \ 831 uint32_t _l_##n[(bits)/32]; \ 832 uint64_t _q_##n[(bits)/64]; \ 833 float32 _s_##n[(bits)/32]; \ 834 float64 _d_##n[(bits)/64]; \ 835 } 836 837 typedef union { 838 uint8_t _b[16]; 839 uint16_t _w[8]; 840 uint32_t _l[4]; 841 uint64_t _q[2]; 842 } XMMReg; 843 844 typedef union { 845 uint8_t _b[32]; 846 uint16_t _w[16]; 847 uint32_t _l[8]; 848 uint64_t _q[4]; 849 } YMMReg; 850 851 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 852 typedef MMREG_UNION(MMXReg, 64) MMXReg; 853 854 typedef struct BNDReg { 855 uint64_t lb; 856 uint64_t ub; 857 } BNDReg; 858 859 typedef struct BNDCSReg { 860 uint64_t cfgu; 861 uint64_t sts; 862 } BNDCSReg; 863 864 #define BNDCFG_ENABLE 1ULL 865 #define BNDCFG_BNDPRESERVE 2ULL 866 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 867 868 #ifdef HOST_WORDS_BIGENDIAN 869 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 870 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 871 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 872 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 873 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 874 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 875 876 #define MMX_B(n) _b_MMXReg[7 - (n)] 877 #define MMX_W(n) _w_MMXReg[3 - (n)] 878 #define MMX_L(n) _l_MMXReg[1 - (n)] 879 #define MMX_S(n) _s_MMXReg[1 - (n)] 880 #else 881 #define ZMM_B(n) _b_ZMMReg[n] 882 #define ZMM_W(n) _w_ZMMReg[n] 883 #define ZMM_L(n) _l_ZMMReg[n] 884 #define ZMM_S(n) _s_ZMMReg[n] 885 #define ZMM_Q(n) _q_ZMMReg[n] 886 #define ZMM_D(n) _d_ZMMReg[n] 887 888 #define MMX_B(n) _b_MMXReg[n] 889 #define MMX_W(n) _w_MMXReg[n] 890 #define MMX_L(n) _l_MMXReg[n] 891 #define MMX_S(n) _s_MMXReg[n] 892 #endif 893 #define MMX_Q(n) _q_MMXReg[n] 894 895 typedef union { 896 floatx80 d __attribute__((aligned(16))); 897 MMXReg mmx; 898 } FPReg; 899 900 typedef struct { 901 uint64_t base; 902 uint64_t mask; 903 } MTRRVar; 904 905 #define CPU_NB_REGS64 16 906 #define CPU_NB_REGS32 8 907 908 #ifdef TARGET_X86_64 909 #define CPU_NB_REGS CPU_NB_REGS64 910 #else 911 #define CPU_NB_REGS CPU_NB_REGS32 912 #endif 913 914 #define MAX_FIXED_COUNTERS 3 915 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 916 917 #define NB_MMU_MODES 3 918 #define TARGET_INSN_START_EXTRA_WORDS 1 919 920 #define NB_OPMASK_REGS 8 921 922 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 923 * that APIC ID hasn't been set yet 924 */ 925 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 926 927 typedef union X86LegacyXSaveArea { 928 struct { 929 uint16_t fcw; 930 uint16_t fsw; 931 uint8_t ftw; 932 uint8_t reserved; 933 uint16_t fpop; 934 uint64_t fpip; 935 uint64_t fpdp; 936 uint32_t mxcsr; 937 uint32_t mxcsr_mask; 938 FPReg fpregs[8]; 939 uint8_t xmm_regs[16][16]; 940 }; 941 uint8_t data[512]; 942 } X86LegacyXSaveArea; 943 944 typedef struct X86XSaveHeader { 945 uint64_t xstate_bv; 946 uint64_t xcomp_bv; 947 uint64_t reserve0; 948 uint8_t reserved[40]; 949 } X86XSaveHeader; 950 951 /* Ext. save area 2: AVX State */ 952 typedef struct XSaveAVX { 953 uint8_t ymmh[16][16]; 954 } XSaveAVX; 955 956 /* Ext. save area 3: BNDREG */ 957 typedef struct XSaveBNDREG { 958 BNDReg bnd_regs[4]; 959 } XSaveBNDREG; 960 961 /* Ext. save area 4: BNDCSR */ 962 typedef union XSaveBNDCSR { 963 BNDCSReg bndcsr; 964 uint8_t data[64]; 965 } XSaveBNDCSR; 966 967 /* Ext. save area 5: Opmask */ 968 typedef struct XSaveOpmask { 969 uint64_t opmask_regs[NB_OPMASK_REGS]; 970 } XSaveOpmask; 971 972 /* Ext. save area 6: ZMM_Hi256 */ 973 typedef struct XSaveZMM_Hi256 { 974 uint8_t zmm_hi256[16][32]; 975 } XSaveZMM_Hi256; 976 977 /* Ext. save area 7: Hi16_ZMM */ 978 typedef struct XSaveHi16_ZMM { 979 uint8_t hi16_zmm[16][64]; 980 } XSaveHi16_ZMM; 981 982 /* Ext. save area 9: PKRU state */ 983 typedef struct XSavePKRU { 984 uint32_t pkru; 985 uint32_t padding; 986 } XSavePKRU; 987 988 typedef struct X86XSaveArea { 989 X86LegacyXSaveArea legacy; 990 X86XSaveHeader header; 991 992 /* Extended save areas: */ 993 994 /* AVX State: */ 995 XSaveAVX avx_state; 996 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 997 /* MPX State: */ 998 XSaveBNDREG bndreg_state; 999 XSaveBNDCSR bndcsr_state; 1000 /* AVX-512 State: */ 1001 XSaveOpmask opmask_state; 1002 XSaveZMM_Hi256 zmm_hi256_state; 1003 XSaveHi16_ZMM hi16_zmm_state; 1004 /* PKRU State: */ 1005 XSavePKRU pkru_state; 1006 } X86XSaveArea; 1007 1008 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1009 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1010 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1011 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1012 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1013 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1014 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1015 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1016 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1017 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1018 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1019 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1020 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1021 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1022 1023 typedef enum TPRAccess { 1024 TPR_ACCESS_READ, 1025 TPR_ACCESS_WRITE, 1026 } TPRAccess; 1027 1028 typedef struct CPUX86State { 1029 /* standard registers */ 1030 target_ulong regs[CPU_NB_REGS]; 1031 target_ulong eip; 1032 target_ulong eflags; /* eflags register. During CPU emulation, CC 1033 flags and DF are set to zero because they are 1034 stored elsewhere */ 1035 1036 /* emulator internal eflags handling */ 1037 target_ulong cc_dst; 1038 target_ulong cc_src; 1039 target_ulong cc_src2; 1040 uint32_t cc_op; 1041 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1042 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1043 are known at translation time. */ 1044 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1045 1046 /* segments */ 1047 SegmentCache segs[6]; /* selector values */ 1048 SegmentCache ldt; 1049 SegmentCache tr; 1050 SegmentCache gdt; /* only base and limit are used */ 1051 SegmentCache idt; /* only base and limit are used */ 1052 1053 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1054 int32_t a20_mask; 1055 1056 BNDReg bnd_regs[4]; 1057 BNDCSReg bndcs_regs; 1058 uint64_t msr_bndcfgs; 1059 uint64_t efer; 1060 1061 /* Beginning of state preserved by INIT (dummy marker). */ 1062 struct {} start_init_save; 1063 1064 /* FPU state */ 1065 unsigned int fpstt; /* top of stack index */ 1066 uint16_t fpus; 1067 uint16_t fpuc; 1068 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1069 FPReg fpregs[8]; 1070 /* KVM-only so far */ 1071 uint16_t fpop; 1072 uint64_t fpip; 1073 uint64_t fpdp; 1074 1075 /* emulator internal variables */ 1076 float_status fp_status; 1077 floatx80 ft0; 1078 1079 float_status mmx_status; /* for 3DNow! float ops */ 1080 float_status sse_status; 1081 uint32_t mxcsr; 1082 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1083 ZMMReg xmm_t0; 1084 MMXReg mmx_t0; 1085 1086 XMMReg ymmh_regs[CPU_NB_REGS]; 1087 1088 uint64_t opmask_regs[NB_OPMASK_REGS]; 1089 YMMReg zmmh_regs[CPU_NB_REGS]; 1090 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1091 1092 /* sysenter registers */ 1093 uint32_t sysenter_cs; 1094 target_ulong sysenter_esp; 1095 target_ulong sysenter_eip; 1096 uint64_t star; 1097 1098 uint64_t vm_hsave; 1099 1100 #ifdef TARGET_X86_64 1101 target_ulong lstar; 1102 target_ulong cstar; 1103 target_ulong fmask; 1104 target_ulong kernelgsbase; 1105 #endif 1106 1107 uint64_t tsc; 1108 uint64_t tsc_adjust; 1109 uint64_t tsc_deadline; 1110 uint64_t tsc_aux; 1111 1112 uint64_t xcr0; 1113 1114 uint64_t mcg_status; 1115 uint64_t msr_ia32_misc_enable; 1116 uint64_t msr_ia32_feature_control; 1117 1118 uint64_t msr_fixed_ctr_ctrl; 1119 uint64_t msr_global_ctrl; 1120 uint64_t msr_global_status; 1121 uint64_t msr_global_ovf_ctrl; 1122 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1123 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1124 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1125 1126 uint64_t pat; 1127 uint32_t smbase; 1128 uint64_t msr_smi_count; 1129 1130 uint32_t pkru; 1131 1132 uint64_t spec_ctrl; 1133 1134 /* End of state preserved by INIT (dummy marker). */ 1135 struct {} end_init_save; 1136 1137 uint64_t system_time_msr; 1138 uint64_t wall_clock_msr; 1139 uint64_t steal_time_msr; 1140 uint64_t async_pf_en_msr; 1141 uint64_t pv_eoi_en_msr; 1142 1143 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1144 uint64_t msr_hv_hypercall; 1145 uint64_t msr_hv_guest_os_id; 1146 uint64_t msr_hv_tsc; 1147 1148 /* Per-VCPU HV MSRs */ 1149 uint64_t msr_hv_vapic; 1150 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1151 uint64_t msr_hv_runtime; 1152 uint64_t msr_hv_synic_control; 1153 uint64_t msr_hv_synic_evt_page; 1154 uint64_t msr_hv_synic_msg_page; 1155 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1156 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1157 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1158 1159 /* exception/interrupt handling */ 1160 int error_code; 1161 int exception_is_int; 1162 target_ulong exception_next_eip; 1163 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1164 union { 1165 struct CPUBreakpoint *cpu_breakpoint[4]; 1166 struct CPUWatchpoint *cpu_watchpoint[4]; 1167 }; /* break/watchpoints for dr[0..3] */ 1168 int old_exception; /* exception in flight */ 1169 1170 uint64_t vm_vmcb; 1171 uint64_t tsc_offset; 1172 uint64_t intercept; 1173 uint16_t intercept_cr_read; 1174 uint16_t intercept_cr_write; 1175 uint16_t intercept_dr_read; 1176 uint16_t intercept_dr_write; 1177 uint32_t intercept_exceptions; 1178 uint8_t v_tpr; 1179 1180 /* KVM states, automatically cleared on reset */ 1181 uint8_t nmi_injected; 1182 uint8_t nmi_pending; 1183 1184 /* Fields up to this point are cleared by a CPU reset */ 1185 struct {} end_reset_fields; 1186 1187 CPU_COMMON 1188 1189 /* Fields after CPU_COMMON are preserved across CPU reset. */ 1190 1191 /* processor features (e.g. for CPUID insn) */ 1192 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1193 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1194 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1195 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1196 /* Actual level/xlevel/xlevel2 value: */ 1197 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1198 uint32_t cpuid_vendor1; 1199 uint32_t cpuid_vendor2; 1200 uint32_t cpuid_vendor3; 1201 uint32_t cpuid_version; 1202 FeatureWordArray features; 1203 /* Features that were explicitly enabled/disabled */ 1204 FeatureWordArray user_features; 1205 uint32_t cpuid_model[12]; 1206 1207 /* MTRRs */ 1208 uint64_t mtrr_fixed[11]; 1209 uint64_t mtrr_deftype; 1210 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1211 1212 /* For KVM */ 1213 uint32_t mp_state; 1214 int32_t exception_injected; 1215 int32_t interrupt_injected; 1216 uint8_t soft_interrupt; 1217 uint8_t has_error_code; 1218 uint32_t ins_len; 1219 uint32_t sipi_vector; 1220 bool tsc_valid; 1221 int64_t tsc_khz; 1222 int64_t user_tsc_khz; /* for sanity check only */ 1223 void *kvm_xsave_buf; 1224 #if defined(CONFIG_HVF) 1225 HVFX86EmulatorState *hvf_emul; 1226 #endif 1227 1228 uint64_t mcg_cap; 1229 uint64_t mcg_ctl; 1230 uint64_t mcg_ext_ctl; 1231 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1232 uint64_t xstate_bv; 1233 1234 /* vmstate */ 1235 uint16_t fpus_vmstate; 1236 uint16_t fptag_vmstate; 1237 uint16_t fpregs_format_vmstate; 1238 1239 uint64_t xss; 1240 1241 TPRAccess tpr_access_type; 1242 } CPUX86State; 1243 1244 struct kvm_msrs; 1245 1246 /** 1247 * X86CPU: 1248 * @env: #CPUX86State 1249 * @migratable: If set, only migratable flags will be accepted when "enforce" 1250 * mode is used, and only migratable flags will be included in the "host" 1251 * CPU model. 1252 * 1253 * An x86 CPU. 1254 */ 1255 struct X86CPU { 1256 /*< private >*/ 1257 CPUState parent_obj; 1258 /*< public >*/ 1259 1260 CPUX86State env; 1261 1262 bool hyperv_vapic; 1263 bool hyperv_relaxed_timing; 1264 int hyperv_spinlock_attempts; 1265 char *hyperv_vendor_id; 1266 bool hyperv_time; 1267 bool hyperv_crash; 1268 bool hyperv_reset; 1269 bool hyperv_vpindex; 1270 bool hyperv_runtime; 1271 bool hyperv_synic; 1272 bool hyperv_stimer; 1273 bool check_cpuid; 1274 bool enforce_cpuid; 1275 bool expose_kvm; 1276 bool expose_tcg; 1277 bool migratable; 1278 bool max_features; /* Enable all supported features automatically */ 1279 uint32_t apic_id; 1280 1281 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1282 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1283 bool vmware_cpuid_freq; 1284 1285 /* if true the CPUID code directly forward host cache leaves to the guest */ 1286 bool cache_info_passthrough; 1287 1288 /* Features that were filtered out because of missing host capabilities */ 1289 uint32_t filtered_features[FEATURE_WORDS]; 1290 1291 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1292 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1293 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1294 * capabilities) directly to the guest. 1295 */ 1296 bool enable_pmu; 1297 1298 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1299 * disabled by default to avoid breaking migration between QEMU with 1300 * different LMCE configurations. 1301 */ 1302 bool enable_lmce; 1303 1304 /* Compatibility bits for old machine types. 1305 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1306 * socket share an virtual l3 cache. 1307 */ 1308 bool enable_l3_cache; 1309 1310 /* Compatibility bits for old machine types: */ 1311 bool enable_cpuid_0xb; 1312 1313 /* Enable auto level-increase for all CPUID leaves */ 1314 bool full_cpuid_auto_level; 1315 1316 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1317 bool fill_mtrr_mask; 1318 1319 /* if true override the phys_bits value with a value read from the host */ 1320 bool host_phys_bits; 1321 1322 /* Stop SMI delivery for migration compatibility with old machines */ 1323 bool kvm_no_smi_migration; 1324 1325 /* Number of physical address bits supported */ 1326 uint32_t phys_bits; 1327 1328 /* in order to simplify APIC support, we leave this pointer to the 1329 user */ 1330 struct DeviceState *apic_state; 1331 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1332 Notifier machine_done; 1333 1334 struct kvm_msrs *kvm_msr_buf; 1335 1336 int32_t node_id; /* NUMA node this CPU belongs to */ 1337 int32_t socket_id; 1338 int32_t core_id; 1339 int32_t thread_id; 1340 1341 int32_t hv_max_vps; 1342 }; 1343 1344 static inline X86CPU *x86_env_get_cpu(CPUX86State *env) 1345 { 1346 return container_of(env, X86CPU, env); 1347 } 1348 1349 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) 1350 1351 #define ENV_OFFSET offsetof(X86CPU, env) 1352 1353 #ifndef CONFIG_USER_ONLY 1354 extern struct VMStateDescription vmstate_x86_cpu; 1355 #endif 1356 1357 /** 1358 * x86_cpu_do_interrupt: 1359 * @cpu: vCPU the interrupt is to be handled by. 1360 */ 1361 void x86_cpu_do_interrupt(CPUState *cpu); 1362 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1363 1364 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1365 int cpuid, void *opaque); 1366 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1367 int cpuid, void *opaque); 1368 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1369 void *opaque); 1370 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1371 void *opaque); 1372 1373 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1374 Error **errp); 1375 1376 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 1377 int flags); 1378 1379 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1380 1381 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1382 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1383 1384 void x86_cpu_exec_enter(CPUState *cpu); 1385 void x86_cpu_exec_exit(CPUState *cpu); 1386 1387 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1388 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1389 1390 int cpu_get_pic_interrupt(CPUX86State *s); 1391 /* MSDOS compatibility mode FPU exception support */ 1392 void cpu_set_ferr(CPUX86State *s); 1393 1394 /* this function must always be used to load data in the segment 1395 cache: it synchronizes the hflags with the segment cache values */ 1396 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1397 int seg_reg, unsigned int selector, 1398 target_ulong base, 1399 unsigned int limit, 1400 unsigned int flags) 1401 { 1402 SegmentCache *sc; 1403 unsigned int new_hflags; 1404 1405 sc = &env->segs[seg_reg]; 1406 sc->selector = selector; 1407 sc->base = base; 1408 sc->limit = limit; 1409 sc->flags = flags; 1410 1411 /* update the hidden flags */ 1412 { 1413 if (seg_reg == R_CS) { 1414 #ifdef TARGET_X86_64 1415 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1416 /* long mode */ 1417 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1418 env->hflags &= ~(HF_ADDSEG_MASK); 1419 } else 1420 #endif 1421 { 1422 /* legacy / compatibility case */ 1423 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1424 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1425 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1426 new_hflags; 1427 } 1428 } 1429 if (seg_reg == R_SS) { 1430 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1431 #if HF_CPL_MASK != 3 1432 #error HF_CPL_MASK is hardcoded 1433 #endif 1434 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1435 } 1436 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1437 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1438 if (env->hflags & HF_CS64_MASK) { 1439 /* zero base assumed for DS, ES and SS in long mode */ 1440 } else if (!(env->cr[0] & CR0_PE_MASK) || 1441 (env->eflags & VM_MASK) || 1442 !(env->hflags & HF_CS32_MASK)) { 1443 /* XXX: try to avoid this test. The problem comes from the 1444 fact that is real mode or vm86 mode we only modify the 1445 'base' and 'selector' fields of the segment cache to go 1446 faster. A solution may be to force addseg to one in 1447 translate-i386.c. */ 1448 new_hflags |= HF_ADDSEG_MASK; 1449 } else { 1450 new_hflags |= ((env->segs[R_DS].base | 1451 env->segs[R_ES].base | 1452 env->segs[R_SS].base) != 0) << 1453 HF_ADDSEG_SHIFT; 1454 } 1455 env->hflags = (env->hflags & 1456 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1457 } 1458 } 1459 1460 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1461 uint8_t sipi_vector) 1462 { 1463 CPUState *cs = CPU(cpu); 1464 CPUX86State *env = &cpu->env; 1465 1466 env->eip = 0; 1467 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1468 sipi_vector << 12, 1469 env->segs[R_CS].limit, 1470 env->segs[R_CS].flags); 1471 cs->halted = 0; 1472 } 1473 1474 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1475 target_ulong *base, unsigned int *limit, 1476 unsigned int *flags); 1477 1478 /* op_helper.c */ 1479 /* used for debug or cpu save/restore */ 1480 1481 /* cpu-exec.c */ 1482 /* the following helpers are only usable in user mode simulation as 1483 they can trigger unexpected exceptions */ 1484 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1485 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1486 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1487 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1488 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1489 1490 /* you can call this signal handler from your SIGBUS and SIGSEGV 1491 signal handlers to inform the virtual CPU of exceptions. non zero 1492 is returned if the signal was handled by the virtual CPU. */ 1493 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1494 void *puc); 1495 1496 /* cpu.c */ 1497 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1498 uint32_t *eax, uint32_t *ebx, 1499 uint32_t *ecx, uint32_t *edx); 1500 void cpu_clear_apic_feature(CPUX86State *env); 1501 void host_cpuid(uint32_t function, uint32_t count, 1502 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1503 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1504 1505 /* helper.c */ 1506 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, 1507 int is_write, int mmu_idx); 1508 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1509 1510 #ifndef CONFIG_USER_ONLY 1511 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1512 { 1513 return !!attrs.secure; 1514 } 1515 1516 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1517 { 1518 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1519 } 1520 1521 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1522 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1523 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1524 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1525 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1526 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1527 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1528 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1529 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1530 #endif 1531 1532 void breakpoint_handler(CPUState *cs); 1533 1534 /* will be suppressed */ 1535 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1536 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1537 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1538 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1539 1540 /* hw/pc.c */ 1541 uint64_t cpu_get_tsc(CPUX86State *env); 1542 1543 #define TARGET_PAGE_BITS 12 1544 1545 #ifdef TARGET_X86_64 1546 #define TARGET_PHYS_ADDR_SPACE_BITS 52 1547 /* ??? This is really 48 bits, sign-extended, but the only thing 1548 accessible to userland with bit 48 set is the VSYSCALL, and that 1549 is handled via other mechanisms. */ 1550 #define TARGET_VIRT_ADDR_SPACE_BITS 47 1551 #else 1552 #define TARGET_PHYS_ADDR_SPACE_BITS 36 1553 #define TARGET_VIRT_ADDR_SPACE_BITS 32 1554 #endif 1555 1556 /* XXX: This value should match the one returned by CPUID 1557 * and in exec.c */ 1558 # if defined(TARGET_X86_64) 1559 # define TCG_PHYS_ADDR_BITS 40 1560 # else 1561 # define TCG_PHYS_ADDR_BITS 36 1562 # endif 1563 1564 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1565 1566 #define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model) 1567 1568 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1569 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1570 1571 #ifdef TARGET_X86_64 1572 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1573 #else 1574 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1575 #endif 1576 1577 #define cpu_signal_handler cpu_x86_signal_handler 1578 #define cpu_list x86_cpu_list 1579 1580 /* MMU modes definitions */ 1581 #define MMU_MODE0_SUFFIX _ksmap 1582 #define MMU_MODE1_SUFFIX _user 1583 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1584 #define MMU_KSMAP_IDX 0 1585 #define MMU_USER_IDX 1 1586 #define MMU_KNOSMAP_IDX 2 1587 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1588 { 1589 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1590 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1591 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1592 } 1593 1594 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1595 { 1596 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1597 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1598 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1599 } 1600 1601 #define CC_DST (env->cc_dst) 1602 #define CC_SRC (env->cc_src) 1603 #define CC_SRC2 (env->cc_src2) 1604 #define CC_OP (env->cc_op) 1605 1606 /* n must be a constant to be efficient */ 1607 static inline target_long lshift(target_long x, int n) 1608 { 1609 if (n >= 0) { 1610 return x << n; 1611 } else { 1612 return x >> (-n); 1613 } 1614 } 1615 1616 /* float macros */ 1617 #define FT0 (env->ft0) 1618 #define ST0 (env->fpregs[env->fpstt].d) 1619 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1620 #define ST1 ST(1) 1621 1622 /* translate.c */ 1623 void tcg_x86_init(void); 1624 1625 #include "exec/cpu-all.h" 1626 #include "svm.h" 1627 1628 #if !defined(CONFIG_USER_ONLY) 1629 #include "hw/i386/apic.h" 1630 #endif 1631 1632 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1633 target_ulong *cs_base, uint32_t *flags) 1634 { 1635 *cs_base = env->segs[R_CS].base; 1636 *pc = *cs_base + env->eip; 1637 *flags = env->hflags | 1638 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1639 } 1640 1641 void do_cpu_init(X86CPU *cpu); 1642 void do_cpu_sipi(X86CPU *cpu); 1643 1644 #define MCE_INJECT_BROADCAST 1 1645 #define MCE_INJECT_UNCOND_AO 2 1646 1647 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1648 uint64_t status, uint64_t mcg_status, uint64_t addr, 1649 uint64_t misc, int flags); 1650 1651 /* excp_helper.c */ 1652 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1653 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1654 uintptr_t retaddr); 1655 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1656 int error_code); 1657 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1658 int error_code, uintptr_t retaddr); 1659 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1660 int error_code, int next_eip_addend); 1661 1662 /* cc_helper.c */ 1663 extern const uint8_t parity_table[256]; 1664 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1665 1666 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1667 { 1668 uint32_t eflags = env->eflags; 1669 if (tcg_enabled()) { 1670 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 1671 } 1672 return eflags; 1673 } 1674 1675 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1676 * after generating a call to a helper that uses this. 1677 */ 1678 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1679 int update_mask) 1680 { 1681 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1682 CC_OP = CC_OP_EFLAGS; 1683 env->df = 1 - (2 * ((eflags >> 10) & 1)); 1684 env->eflags = (env->eflags & ~update_mask) | 1685 (eflags & update_mask) | 0x2; 1686 } 1687 1688 /* load efer and update the corresponding hflags. XXX: do consistency 1689 checks with cpuid bits? */ 1690 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1691 { 1692 env->efer = val; 1693 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1694 if (env->efer & MSR_EFER_LMA) { 1695 env->hflags |= HF_LMA_MASK; 1696 } 1697 if (env->efer & MSR_EFER_SVME) { 1698 env->hflags |= HF_SVME_MASK; 1699 } 1700 } 1701 1702 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 1703 { 1704 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 1705 } 1706 1707 static inline int32_t x86_get_a20_mask(CPUX86State *env) 1708 { 1709 if (env->hflags & HF_SMM_MASK) { 1710 return -1; 1711 } else { 1712 return env->a20_mask; 1713 } 1714 } 1715 1716 /* fpu_helper.c */ 1717 void update_fp_status(CPUX86State *env); 1718 void update_mxcsr_status(CPUX86State *env); 1719 1720 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 1721 { 1722 env->mxcsr = mxcsr; 1723 if (tcg_enabled()) { 1724 update_mxcsr_status(env); 1725 } 1726 } 1727 1728 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 1729 { 1730 env->fpuc = fpuc; 1731 if (tcg_enabled()) { 1732 update_fp_status(env); 1733 } 1734 } 1735 1736 /* mem_helper.c */ 1737 void helper_lock_init(void); 1738 1739 /* svm_helper.c */ 1740 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 1741 uint64_t param, uintptr_t retaddr); 1742 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, 1743 uintptr_t retaddr); 1744 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 1745 1746 /* seg_helper.c */ 1747 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 1748 1749 /* smm_helper.c */ 1750 void do_smm_enter(X86CPU *cpu); 1751 1752 /* apic.c */ 1753 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 1754 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 1755 TPRAccess access); 1756 1757 1758 /* Change the value of a KVM-specific default 1759 * 1760 * If value is NULL, no default will be set and the original 1761 * value from the CPU model table will be kept. 1762 * 1763 * It is valid to call this function only for properties that 1764 * are already present in the kvm_default_props table. 1765 */ 1766 void x86_cpu_change_kvm_default(const char *prop, const char *value); 1767 1768 /* mpx_helper.c */ 1769 void cpu_sync_bndcs_hflags(CPUX86State *env); 1770 1771 /* Return name of 32-bit register, from a R_* constant */ 1772 const char *get_register_name_32(unsigned int reg); 1773 1774 void enable_compat_apic_id_mode(void); 1775 1776 #define APIC_DEFAULT_ADDRESS 0xfee00000 1777 #define APIC_SPACE_SIZE 0x100000 1778 1779 void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, 1780 fprintf_function cpu_fprintf, int flags); 1781 1782 /* cpu.c */ 1783 bool cpu_is_bsp(X86CPU *cpu); 1784 1785 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 1786 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 1787 void x86_update_hflags(CPUX86State* env); 1788 1789 #endif /* I386_CPU_H */ 1790