1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "hyperv-proto.h" 26 27 #ifdef TARGET_X86_64 28 #define TARGET_LONG_BITS 64 29 #else 30 #define TARGET_LONG_BITS 32 31 #endif 32 33 #include "exec/cpu-defs.h" 34 35 /* The x86 has a strong memory model with some store-after-load re-ordering */ 36 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 37 38 /* Maximum instruction code size */ 39 #define TARGET_MAX_INSN_SIZE 16 40 41 /* support for self modifying code even if the modified instruction is 42 close to the modifying instruction */ 43 #define TARGET_HAS_PRECISE_SMC 44 45 #ifdef TARGET_X86_64 46 #define I386_ELF_MACHINE EM_X86_64 47 #define ELF_MACHINE_UNAME "x86_64" 48 #else 49 #define I386_ELF_MACHINE EM_386 50 #define ELF_MACHINE_UNAME "i686" 51 #endif 52 53 #define CPUArchState struct CPUX86State 54 55 #ifdef CONFIG_TCG 56 #include "fpu/softfloat.h" 57 #endif 58 59 enum { 60 R_EAX = 0, 61 R_ECX = 1, 62 R_EDX = 2, 63 R_EBX = 3, 64 R_ESP = 4, 65 R_EBP = 5, 66 R_ESI = 6, 67 R_EDI = 7, 68 R_R8 = 8, 69 R_R9 = 9, 70 R_R10 = 10, 71 R_R11 = 11, 72 R_R12 = 12, 73 R_R13 = 13, 74 R_R14 = 14, 75 R_R15 = 15, 76 77 R_AL = 0, 78 R_CL = 1, 79 R_DL = 2, 80 R_BL = 3, 81 R_AH = 4, 82 R_CH = 5, 83 R_DH = 6, 84 R_BH = 7, 85 }; 86 87 typedef enum X86Seg { 88 R_ES = 0, 89 R_CS = 1, 90 R_SS = 2, 91 R_DS = 3, 92 R_FS = 4, 93 R_GS = 5, 94 R_LDTR = 6, 95 R_TR = 7, 96 } X86Seg; 97 98 /* segment descriptor fields */ 99 #define DESC_G_SHIFT 23 100 #define DESC_G_MASK (1 << DESC_G_SHIFT) 101 #define DESC_B_SHIFT 22 102 #define DESC_B_MASK (1 << DESC_B_SHIFT) 103 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 104 #define DESC_L_MASK (1 << DESC_L_SHIFT) 105 #define DESC_AVL_SHIFT 20 106 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 107 #define DESC_P_SHIFT 15 108 #define DESC_P_MASK (1 << DESC_P_SHIFT) 109 #define DESC_DPL_SHIFT 13 110 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 111 #define DESC_S_SHIFT 12 112 #define DESC_S_MASK (1 << DESC_S_SHIFT) 113 #define DESC_TYPE_SHIFT 8 114 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 115 #define DESC_A_MASK (1 << 8) 116 117 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 118 #define DESC_C_MASK (1 << 10) /* code: conforming */ 119 #define DESC_R_MASK (1 << 9) /* code: readable */ 120 121 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 122 #define DESC_W_MASK (1 << 9) /* data: writable */ 123 124 #define DESC_TSS_BUSY_MASK (1 << 9) 125 126 /* eflags masks */ 127 #define CC_C 0x0001 128 #define CC_P 0x0004 129 #define CC_A 0x0010 130 #define CC_Z 0x0040 131 #define CC_S 0x0080 132 #define CC_O 0x0800 133 134 #define TF_SHIFT 8 135 #define IOPL_SHIFT 12 136 #define VM_SHIFT 17 137 138 #define TF_MASK 0x00000100 139 #define IF_MASK 0x00000200 140 #define DF_MASK 0x00000400 141 #define IOPL_MASK 0x00003000 142 #define NT_MASK 0x00004000 143 #define RF_MASK 0x00010000 144 #define VM_MASK 0x00020000 145 #define AC_MASK 0x00040000 146 #define VIF_MASK 0x00080000 147 #define VIP_MASK 0x00100000 148 #define ID_MASK 0x00200000 149 150 /* hidden flags - used internally by qemu to represent additional cpu 151 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 152 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 153 positions to ease oring with eflags. */ 154 /* current cpl */ 155 #define HF_CPL_SHIFT 0 156 /* true if hardware interrupts must be disabled for next instruction */ 157 #define HF_INHIBIT_IRQ_SHIFT 3 158 /* 16 or 32 segments */ 159 #define HF_CS32_SHIFT 4 160 #define HF_SS32_SHIFT 5 161 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 162 #define HF_ADDSEG_SHIFT 6 163 /* copy of CR0.PE (protected mode) */ 164 #define HF_PE_SHIFT 7 165 #define HF_TF_SHIFT 8 /* must be same as eflags */ 166 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 167 #define HF_EM_SHIFT 10 168 #define HF_TS_SHIFT 11 169 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 170 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 171 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 172 #define HF_RF_SHIFT 16 /* must be same as eflags */ 173 #define HF_VM_SHIFT 17 /* must be same as eflags */ 174 #define HF_AC_SHIFT 18 /* must be same as eflags */ 175 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 176 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 177 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 178 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 179 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 180 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 181 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 182 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 183 184 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 185 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 186 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 187 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 188 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 189 #define HF_PE_MASK (1 << HF_PE_SHIFT) 190 #define HF_TF_MASK (1 << HF_TF_SHIFT) 191 #define HF_MP_MASK (1 << HF_MP_SHIFT) 192 #define HF_EM_MASK (1 << HF_EM_SHIFT) 193 #define HF_TS_MASK (1 << HF_TS_SHIFT) 194 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 195 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 196 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 197 #define HF_RF_MASK (1 << HF_RF_SHIFT) 198 #define HF_VM_MASK (1 << HF_VM_SHIFT) 199 #define HF_AC_MASK (1 << HF_AC_SHIFT) 200 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 201 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 202 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 203 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 204 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 205 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 206 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 207 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 208 209 /* hflags2 */ 210 211 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 212 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 213 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 214 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 215 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 216 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 217 218 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 219 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 220 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 221 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 222 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 223 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 224 225 #define CR0_PE_SHIFT 0 226 #define CR0_MP_SHIFT 1 227 228 #define CR0_PE_MASK (1U << 0) 229 #define CR0_MP_MASK (1U << 1) 230 #define CR0_EM_MASK (1U << 2) 231 #define CR0_TS_MASK (1U << 3) 232 #define CR0_ET_MASK (1U << 4) 233 #define CR0_NE_MASK (1U << 5) 234 #define CR0_WP_MASK (1U << 16) 235 #define CR0_AM_MASK (1U << 18) 236 #define CR0_PG_MASK (1U << 31) 237 238 #define CR4_VME_MASK (1U << 0) 239 #define CR4_PVI_MASK (1U << 1) 240 #define CR4_TSD_MASK (1U << 2) 241 #define CR4_DE_MASK (1U << 3) 242 #define CR4_PSE_MASK (1U << 4) 243 #define CR4_PAE_MASK (1U << 5) 244 #define CR4_MCE_MASK (1U << 6) 245 #define CR4_PGE_MASK (1U << 7) 246 #define CR4_PCE_MASK (1U << 8) 247 #define CR4_OSFXSR_SHIFT 9 248 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 249 #define CR4_OSXMMEXCPT_MASK (1U << 10) 250 #define CR4_LA57_MASK (1U << 12) 251 #define CR4_VMXE_MASK (1U << 13) 252 #define CR4_SMXE_MASK (1U << 14) 253 #define CR4_FSGSBASE_MASK (1U << 16) 254 #define CR4_PCIDE_MASK (1U << 17) 255 #define CR4_OSXSAVE_MASK (1U << 18) 256 #define CR4_SMEP_MASK (1U << 20) 257 #define CR4_SMAP_MASK (1U << 21) 258 #define CR4_PKE_MASK (1U << 22) 259 260 #define DR6_BD (1 << 13) 261 #define DR6_BS (1 << 14) 262 #define DR6_BT (1 << 15) 263 #define DR6_FIXED_1 0xffff0ff0 264 265 #define DR7_GD (1 << 13) 266 #define DR7_TYPE_SHIFT 16 267 #define DR7_LEN_SHIFT 18 268 #define DR7_FIXED_1 0x00000400 269 #define DR7_GLOBAL_BP_MASK 0xaa 270 #define DR7_LOCAL_BP_MASK 0x55 271 #define DR7_MAX_BP 4 272 #define DR7_TYPE_BP_INST 0x0 273 #define DR7_TYPE_DATA_WR 0x1 274 #define DR7_TYPE_IO_RW 0x2 275 #define DR7_TYPE_DATA_RW 0x3 276 277 #define PG_PRESENT_BIT 0 278 #define PG_RW_BIT 1 279 #define PG_USER_BIT 2 280 #define PG_PWT_BIT 3 281 #define PG_PCD_BIT 4 282 #define PG_ACCESSED_BIT 5 283 #define PG_DIRTY_BIT 6 284 #define PG_PSE_BIT 7 285 #define PG_GLOBAL_BIT 8 286 #define PG_PSE_PAT_BIT 12 287 #define PG_PKRU_BIT 59 288 #define PG_NX_BIT 63 289 290 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 291 #define PG_RW_MASK (1 << PG_RW_BIT) 292 #define PG_USER_MASK (1 << PG_USER_BIT) 293 #define PG_PWT_MASK (1 << PG_PWT_BIT) 294 #define PG_PCD_MASK (1 << PG_PCD_BIT) 295 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 296 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 297 #define PG_PSE_MASK (1 << PG_PSE_BIT) 298 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 299 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 300 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 301 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 302 #define PG_HI_USER_MASK 0x7ff0000000000000LL 303 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 304 #define PG_NX_MASK (1ULL << PG_NX_BIT) 305 306 #define PG_ERROR_W_BIT 1 307 308 #define PG_ERROR_P_MASK 0x01 309 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 310 #define PG_ERROR_U_MASK 0x04 311 #define PG_ERROR_RSVD_MASK 0x08 312 #define PG_ERROR_I_D_MASK 0x10 313 #define PG_ERROR_PK_MASK 0x20 314 315 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 316 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 317 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 318 319 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 320 #define MCE_BANKS_DEF 10 321 322 #define MCG_CAP_BANKS_MASK 0xff 323 324 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 325 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 326 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 327 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 328 329 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 330 331 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 332 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 333 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 334 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 335 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 336 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 337 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 338 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 339 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 340 341 /* MISC register defines */ 342 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 343 #define MCM_ADDR_LINEAR 1 /* linear address */ 344 #define MCM_ADDR_PHYS 2 /* physical address */ 345 #define MCM_ADDR_MEM 3 /* memory address */ 346 #define MCM_ADDR_GENERIC 7 /* generic */ 347 348 #define MSR_IA32_TSC 0x10 349 #define MSR_IA32_APICBASE 0x1b 350 #define MSR_IA32_APICBASE_BSP (1<<8) 351 #define MSR_IA32_APICBASE_ENABLE (1<<11) 352 #define MSR_IA32_APICBASE_EXTD (1 << 10) 353 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 354 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 355 #define MSR_TSC_ADJUST 0x0000003b 356 #define MSR_IA32_SPEC_CTRL 0x48 357 #define MSR_IA32_TSCDEADLINE 0x6e0 358 359 #define FEATURE_CONTROL_LOCKED (1<<0) 360 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 361 #define FEATURE_CONTROL_LMCE (1<<20) 362 363 #define MSR_P6_PERFCTR0 0xc1 364 365 #define MSR_IA32_SMBASE 0x9e 366 #define MSR_MTRRcap 0xfe 367 #define MSR_MTRRcap_VCNT 8 368 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 369 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 370 371 #define MSR_IA32_SYSENTER_CS 0x174 372 #define MSR_IA32_SYSENTER_ESP 0x175 373 #define MSR_IA32_SYSENTER_EIP 0x176 374 375 #define MSR_MCG_CAP 0x179 376 #define MSR_MCG_STATUS 0x17a 377 #define MSR_MCG_CTL 0x17b 378 #define MSR_MCG_EXT_CTL 0x4d0 379 380 #define MSR_P6_EVNTSEL0 0x186 381 382 #define MSR_IA32_PERF_STATUS 0x198 383 384 #define MSR_IA32_MISC_ENABLE 0x1a0 385 /* Indicates good rep/movs microcode on some processors: */ 386 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 387 388 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 389 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 390 391 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 392 393 #define MSR_MTRRfix64K_00000 0x250 394 #define MSR_MTRRfix16K_80000 0x258 395 #define MSR_MTRRfix16K_A0000 0x259 396 #define MSR_MTRRfix4K_C0000 0x268 397 #define MSR_MTRRfix4K_C8000 0x269 398 #define MSR_MTRRfix4K_D0000 0x26a 399 #define MSR_MTRRfix4K_D8000 0x26b 400 #define MSR_MTRRfix4K_E0000 0x26c 401 #define MSR_MTRRfix4K_E8000 0x26d 402 #define MSR_MTRRfix4K_F0000 0x26e 403 #define MSR_MTRRfix4K_F8000 0x26f 404 405 #define MSR_PAT 0x277 406 407 #define MSR_MTRRdefType 0x2ff 408 409 #define MSR_CORE_PERF_FIXED_CTR0 0x309 410 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 411 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 412 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 413 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 414 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 415 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 416 417 #define MSR_MC0_CTL 0x400 418 #define MSR_MC0_STATUS 0x401 419 #define MSR_MC0_ADDR 0x402 420 #define MSR_MC0_MISC 0x403 421 422 #define MSR_EFER 0xc0000080 423 424 #define MSR_EFER_SCE (1 << 0) 425 #define MSR_EFER_LME (1 << 8) 426 #define MSR_EFER_LMA (1 << 10) 427 #define MSR_EFER_NXE (1 << 11) 428 #define MSR_EFER_SVME (1 << 12) 429 #define MSR_EFER_FFXSR (1 << 14) 430 431 #define MSR_STAR 0xc0000081 432 #define MSR_LSTAR 0xc0000082 433 #define MSR_CSTAR 0xc0000083 434 #define MSR_FMASK 0xc0000084 435 #define MSR_FSBASE 0xc0000100 436 #define MSR_GSBASE 0xc0000101 437 #define MSR_KERNELGSBASE 0xc0000102 438 #define MSR_TSC_AUX 0xc0000103 439 440 #define MSR_VM_HSAVE_PA 0xc0010117 441 442 #define MSR_IA32_BNDCFGS 0x00000d90 443 #define MSR_IA32_XSS 0x00000da0 444 445 #define XSTATE_FP_BIT 0 446 #define XSTATE_SSE_BIT 1 447 #define XSTATE_YMM_BIT 2 448 #define XSTATE_BNDREGS_BIT 3 449 #define XSTATE_BNDCSR_BIT 4 450 #define XSTATE_OPMASK_BIT 5 451 #define XSTATE_ZMM_Hi256_BIT 6 452 #define XSTATE_Hi16_ZMM_BIT 7 453 #define XSTATE_PKRU_BIT 9 454 455 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 456 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 457 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 458 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 459 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 460 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 461 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 462 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 463 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 464 465 /* CPUID feature words */ 466 typedef enum FeatureWord { 467 FEAT_1_EDX, /* CPUID[1].EDX */ 468 FEAT_1_ECX, /* CPUID[1].ECX */ 469 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 470 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 471 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 472 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 473 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 474 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 475 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 476 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 477 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 478 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 479 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 480 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 481 FEAT_SVM, /* CPUID[8000_000A].EDX */ 482 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 483 FEAT_6_EAX, /* CPUID[6].EAX */ 484 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 485 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 486 FEATURE_WORDS, 487 } FeatureWord; 488 489 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 490 491 /* cpuid_features bits */ 492 #define CPUID_FP87 (1U << 0) 493 #define CPUID_VME (1U << 1) 494 #define CPUID_DE (1U << 2) 495 #define CPUID_PSE (1U << 3) 496 #define CPUID_TSC (1U << 4) 497 #define CPUID_MSR (1U << 5) 498 #define CPUID_PAE (1U << 6) 499 #define CPUID_MCE (1U << 7) 500 #define CPUID_CX8 (1U << 8) 501 #define CPUID_APIC (1U << 9) 502 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 503 #define CPUID_MTRR (1U << 12) 504 #define CPUID_PGE (1U << 13) 505 #define CPUID_MCA (1U << 14) 506 #define CPUID_CMOV (1U << 15) 507 #define CPUID_PAT (1U << 16) 508 #define CPUID_PSE36 (1U << 17) 509 #define CPUID_PN (1U << 18) 510 #define CPUID_CLFLUSH (1U << 19) 511 #define CPUID_DTS (1U << 21) 512 #define CPUID_ACPI (1U << 22) 513 #define CPUID_MMX (1U << 23) 514 #define CPUID_FXSR (1U << 24) 515 #define CPUID_SSE (1U << 25) 516 #define CPUID_SSE2 (1U << 26) 517 #define CPUID_SS (1U << 27) 518 #define CPUID_HT (1U << 28) 519 #define CPUID_TM (1U << 29) 520 #define CPUID_IA64 (1U << 30) 521 #define CPUID_PBE (1U << 31) 522 523 #define CPUID_EXT_SSE3 (1U << 0) 524 #define CPUID_EXT_PCLMULQDQ (1U << 1) 525 #define CPUID_EXT_DTES64 (1U << 2) 526 #define CPUID_EXT_MONITOR (1U << 3) 527 #define CPUID_EXT_DSCPL (1U << 4) 528 #define CPUID_EXT_VMX (1U << 5) 529 #define CPUID_EXT_SMX (1U << 6) 530 #define CPUID_EXT_EST (1U << 7) 531 #define CPUID_EXT_TM2 (1U << 8) 532 #define CPUID_EXT_SSSE3 (1U << 9) 533 #define CPUID_EXT_CID (1U << 10) 534 #define CPUID_EXT_FMA (1U << 12) 535 #define CPUID_EXT_CX16 (1U << 13) 536 #define CPUID_EXT_XTPR (1U << 14) 537 #define CPUID_EXT_PDCM (1U << 15) 538 #define CPUID_EXT_PCID (1U << 17) 539 #define CPUID_EXT_DCA (1U << 18) 540 #define CPUID_EXT_SSE41 (1U << 19) 541 #define CPUID_EXT_SSE42 (1U << 20) 542 #define CPUID_EXT_X2APIC (1U << 21) 543 #define CPUID_EXT_MOVBE (1U << 22) 544 #define CPUID_EXT_POPCNT (1U << 23) 545 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 546 #define CPUID_EXT_AES (1U << 25) 547 #define CPUID_EXT_XSAVE (1U << 26) 548 #define CPUID_EXT_OSXSAVE (1U << 27) 549 #define CPUID_EXT_AVX (1U << 28) 550 #define CPUID_EXT_F16C (1U << 29) 551 #define CPUID_EXT_RDRAND (1U << 30) 552 #define CPUID_EXT_HYPERVISOR (1U << 31) 553 554 #define CPUID_EXT2_FPU (1U << 0) 555 #define CPUID_EXT2_VME (1U << 1) 556 #define CPUID_EXT2_DE (1U << 2) 557 #define CPUID_EXT2_PSE (1U << 3) 558 #define CPUID_EXT2_TSC (1U << 4) 559 #define CPUID_EXT2_MSR (1U << 5) 560 #define CPUID_EXT2_PAE (1U << 6) 561 #define CPUID_EXT2_MCE (1U << 7) 562 #define CPUID_EXT2_CX8 (1U << 8) 563 #define CPUID_EXT2_APIC (1U << 9) 564 #define CPUID_EXT2_SYSCALL (1U << 11) 565 #define CPUID_EXT2_MTRR (1U << 12) 566 #define CPUID_EXT2_PGE (1U << 13) 567 #define CPUID_EXT2_MCA (1U << 14) 568 #define CPUID_EXT2_CMOV (1U << 15) 569 #define CPUID_EXT2_PAT (1U << 16) 570 #define CPUID_EXT2_PSE36 (1U << 17) 571 #define CPUID_EXT2_MP (1U << 19) 572 #define CPUID_EXT2_NX (1U << 20) 573 #define CPUID_EXT2_MMXEXT (1U << 22) 574 #define CPUID_EXT2_MMX (1U << 23) 575 #define CPUID_EXT2_FXSR (1U << 24) 576 #define CPUID_EXT2_FFXSR (1U << 25) 577 #define CPUID_EXT2_PDPE1GB (1U << 26) 578 #define CPUID_EXT2_RDTSCP (1U << 27) 579 #define CPUID_EXT2_LM (1U << 29) 580 #define CPUID_EXT2_3DNOWEXT (1U << 30) 581 #define CPUID_EXT2_3DNOW (1U << 31) 582 583 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 584 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 585 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 586 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 587 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 588 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 589 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 590 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 591 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 592 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 593 594 #define CPUID_EXT3_LAHF_LM (1U << 0) 595 #define CPUID_EXT3_CMP_LEG (1U << 1) 596 #define CPUID_EXT3_SVM (1U << 2) 597 #define CPUID_EXT3_EXTAPIC (1U << 3) 598 #define CPUID_EXT3_CR8LEG (1U << 4) 599 #define CPUID_EXT3_ABM (1U << 5) 600 #define CPUID_EXT3_SSE4A (1U << 6) 601 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 602 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 603 #define CPUID_EXT3_OSVW (1U << 9) 604 #define CPUID_EXT3_IBS (1U << 10) 605 #define CPUID_EXT3_XOP (1U << 11) 606 #define CPUID_EXT3_SKINIT (1U << 12) 607 #define CPUID_EXT3_WDT (1U << 13) 608 #define CPUID_EXT3_LWP (1U << 15) 609 #define CPUID_EXT3_FMA4 (1U << 16) 610 #define CPUID_EXT3_TCE (1U << 17) 611 #define CPUID_EXT3_NODEID (1U << 19) 612 #define CPUID_EXT3_TBM (1U << 21) 613 #define CPUID_EXT3_TOPOEXT (1U << 22) 614 #define CPUID_EXT3_PERFCORE (1U << 23) 615 #define CPUID_EXT3_PERFNB (1U << 24) 616 617 #define CPUID_SVM_NPT (1U << 0) 618 #define CPUID_SVM_LBRV (1U << 1) 619 #define CPUID_SVM_SVMLOCK (1U << 2) 620 #define CPUID_SVM_NRIPSAVE (1U << 3) 621 #define CPUID_SVM_TSCSCALE (1U << 4) 622 #define CPUID_SVM_VMCBCLEAN (1U << 5) 623 #define CPUID_SVM_FLUSHASID (1U << 6) 624 #define CPUID_SVM_DECODEASSIST (1U << 7) 625 #define CPUID_SVM_PAUSEFILTER (1U << 10) 626 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 627 628 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 629 #define CPUID_7_0_EBX_BMI1 (1U << 3) 630 #define CPUID_7_0_EBX_HLE (1U << 4) 631 #define CPUID_7_0_EBX_AVX2 (1U << 5) 632 #define CPUID_7_0_EBX_SMEP (1U << 7) 633 #define CPUID_7_0_EBX_BMI2 (1U << 8) 634 #define CPUID_7_0_EBX_ERMS (1U << 9) 635 #define CPUID_7_0_EBX_INVPCID (1U << 10) 636 #define CPUID_7_0_EBX_RTM (1U << 11) 637 #define CPUID_7_0_EBX_MPX (1U << 14) 638 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 639 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 640 #define CPUID_7_0_EBX_RDSEED (1U << 18) 641 #define CPUID_7_0_EBX_ADX (1U << 19) 642 #define CPUID_7_0_EBX_SMAP (1U << 20) 643 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 644 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 645 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 646 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 647 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 648 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 649 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 650 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 651 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 652 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 653 654 #define CPUID_7_0_ECX_AVX512BMI (1U << 1) 655 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 656 #define CPUID_7_0_ECX_UMIP (1U << 2) 657 #define CPUID_7_0_ECX_PKU (1U << 3) 658 #define CPUID_7_0_ECX_OSPKE (1U << 4) 659 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ 660 #define CPUID_7_0_ECX_GFNI (1U << 8) 661 #define CPUID_7_0_ECX_VAES (1U << 9) 662 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 663 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 664 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 665 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 666 #define CPUID_7_0_ECX_LA57 (1U << 16) 667 #define CPUID_7_0_ECX_RDPID (1U << 22) 668 669 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 670 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 671 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ 672 673 #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ 674 675 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 676 #define CPUID_XSAVE_XSAVEC (1U << 1) 677 #define CPUID_XSAVE_XGETBV1 (1U << 2) 678 #define CPUID_XSAVE_XSAVES (1U << 3) 679 680 #define CPUID_6_EAX_ARAT (1U << 2) 681 682 /* CPUID[0x80000007].EDX flags: */ 683 #define CPUID_APM_INVTSC (1U << 8) 684 685 #define CPUID_VENDOR_SZ 12 686 687 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 688 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 689 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 690 #define CPUID_VENDOR_INTEL "GenuineIntel" 691 692 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 693 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 694 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 695 #define CPUID_VENDOR_AMD "AuthenticAMD" 696 697 #define CPUID_VENDOR_VIA "CentaurHauls" 698 699 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 700 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 701 702 /* CPUID[0xB].ECX level types */ 703 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 704 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 705 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 706 707 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 708 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 709 #endif 710 711 #define EXCP00_DIVZ 0 712 #define EXCP01_DB 1 713 #define EXCP02_NMI 2 714 #define EXCP03_INT3 3 715 #define EXCP04_INTO 4 716 #define EXCP05_BOUND 5 717 #define EXCP06_ILLOP 6 718 #define EXCP07_PREX 7 719 #define EXCP08_DBLE 8 720 #define EXCP09_XERR 9 721 #define EXCP0A_TSS 10 722 #define EXCP0B_NOSEG 11 723 #define EXCP0C_STACK 12 724 #define EXCP0D_GPF 13 725 #define EXCP0E_PAGE 14 726 #define EXCP10_COPR 16 727 #define EXCP11_ALGN 17 728 #define EXCP12_MCHK 18 729 730 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 731 for syscall instruction */ 732 #define EXCP_VMEXIT 0x100 733 734 /* i386-specific interrupt pending bits. */ 735 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 736 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 737 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 738 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 739 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 740 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 741 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 742 743 /* Use a clearer name for this. */ 744 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 745 746 /* Instead of computing the condition codes after each x86 instruction, 747 * QEMU just stores one operand (called CC_SRC), the result 748 * (called CC_DST) and the type of operation (called CC_OP). When the 749 * condition codes are needed, the condition codes can be calculated 750 * using this information. Condition codes are not generated if they 751 * are only needed for conditional branches. 752 */ 753 typedef enum { 754 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 755 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 756 757 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 758 CC_OP_MULW, 759 CC_OP_MULL, 760 CC_OP_MULQ, 761 762 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 763 CC_OP_ADDW, 764 CC_OP_ADDL, 765 CC_OP_ADDQ, 766 767 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 768 CC_OP_ADCW, 769 CC_OP_ADCL, 770 CC_OP_ADCQ, 771 772 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 773 CC_OP_SUBW, 774 CC_OP_SUBL, 775 CC_OP_SUBQ, 776 777 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 778 CC_OP_SBBW, 779 CC_OP_SBBL, 780 CC_OP_SBBQ, 781 782 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 783 CC_OP_LOGICW, 784 CC_OP_LOGICL, 785 CC_OP_LOGICQ, 786 787 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 788 CC_OP_INCW, 789 CC_OP_INCL, 790 CC_OP_INCQ, 791 792 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 793 CC_OP_DECW, 794 CC_OP_DECL, 795 CC_OP_DECQ, 796 797 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 798 CC_OP_SHLW, 799 CC_OP_SHLL, 800 CC_OP_SHLQ, 801 802 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 803 CC_OP_SARW, 804 CC_OP_SARL, 805 CC_OP_SARQ, 806 807 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 808 CC_OP_BMILGW, 809 CC_OP_BMILGL, 810 CC_OP_BMILGQ, 811 812 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 813 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 814 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 815 816 CC_OP_CLR, /* Z set, all other flags clear. */ 817 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 818 819 CC_OP_NB, 820 } CCOp; 821 822 typedef struct SegmentCache { 823 uint32_t selector; 824 target_ulong base; 825 uint32_t limit; 826 uint32_t flags; 827 } SegmentCache; 828 829 #define MMREG_UNION(n, bits) \ 830 union n { \ 831 uint8_t _b_##n[(bits)/8]; \ 832 uint16_t _w_##n[(bits)/16]; \ 833 uint32_t _l_##n[(bits)/32]; \ 834 uint64_t _q_##n[(bits)/64]; \ 835 float32 _s_##n[(bits)/32]; \ 836 float64 _d_##n[(bits)/64]; \ 837 } 838 839 typedef union { 840 uint8_t _b[16]; 841 uint16_t _w[8]; 842 uint32_t _l[4]; 843 uint64_t _q[2]; 844 } XMMReg; 845 846 typedef union { 847 uint8_t _b[32]; 848 uint16_t _w[16]; 849 uint32_t _l[8]; 850 uint64_t _q[4]; 851 } YMMReg; 852 853 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 854 typedef MMREG_UNION(MMXReg, 64) MMXReg; 855 856 typedef struct BNDReg { 857 uint64_t lb; 858 uint64_t ub; 859 } BNDReg; 860 861 typedef struct BNDCSReg { 862 uint64_t cfgu; 863 uint64_t sts; 864 } BNDCSReg; 865 866 #define BNDCFG_ENABLE 1ULL 867 #define BNDCFG_BNDPRESERVE 2ULL 868 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 869 870 #ifdef HOST_WORDS_BIGENDIAN 871 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 872 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 873 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 874 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 875 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 876 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 877 878 #define MMX_B(n) _b_MMXReg[7 - (n)] 879 #define MMX_W(n) _w_MMXReg[3 - (n)] 880 #define MMX_L(n) _l_MMXReg[1 - (n)] 881 #define MMX_S(n) _s_MMXReg[1 - (n)] 882 #else 883 #define ZMM_B(n) _b_ZMMReg[n] 884 #define ZMM_W(n) _w_ZMMReg[n] 885 #define ZMM_L(n) _l_ZMMReg[n] 886 #define ZMM_S(n) _s_ZMMReg[n] 887 #define ZMM_Q(n) _q_ZMMReg[n] 888 #define ZMM_D(n) _d_ZMMReg[n] 889 890 #define MMX_B(n) _b_MMXReg[n] 891 #define MMX_W(n) _w_MMXReg[n] 892 #define MMX_L(n) _l_MMXReg[n] 893 #define MMX_S(n) _s_MMXReg[n] 894 #endif 895 #define MMX_Q(n) _q_MMXReg[n] 896 897 typedef union { 898 floatx80 d __attribute__((aligned(16))); 899 MMXReg mmx; 900 } FPReg; 901 902 typedef struct { 903 uint64_t base; 904 uint64_t mask; 905 } MTRRVar; 906 907 #define CPU_NB_REGS64 16 908 #define CPU_NB_REGS32 8 909 910 #ifdef TARGET_X86_64 911 #define CPU_NB_REGS CPU_NB_REGS64 912 #else 913 #define CPU_NB_REGS CPU_NB_REGS32 914 #endif 915 916 #define MAX_FIXED_COUNTERS 3 917 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 918 919 #define NB_MMU_MODES 3 920 #define TARGET_INSN_START_EXTRA_WORDS 1 921 922 #define NB_OPMASK_REGS 8 923 924 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 925 * that APIC ID hasn't been set yet 926 */ 927 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 928 929 typedef union X86LegacyXSaveArea { 930 struct { 931 uint16_t fcw; 932 uint16_t fsw; 933 uint8_t ftw; 934 uint8_t reserved; 935 uint16_t fpop; 936 uint64_t fpip; 937 uint64_t fpdp; 938 uint32_t mxcsr; 939 uint32_t mxcsr_mask; 940 FPReg fpregs[8]; 941 uint8_t xmm_regs[16][16]; 942 }; 943 uint8_t data[512]; 944 } X86LegacyXSaveArea; 945 946 typedef struct X86XSaveHeader { 947 uint64_t xstate_bv; 948 uint64_t xcomp_bv; 949 uint64_t reserve0; 950 uint8_t reserved[40]; 951 } X86XSaveHeader; 952 953 /* Ext. save area 2: AVX State */ 954 typedef struct XSaveAVX { 955 uint8_t ymmh[16][16]; 956 } XSaveAVX; 957 958 /* Ext. save area 3: BNDREG */ 959 typedef struct XSaveBNDREG { 960 BNDReg bnd_regs[4]; 961 } XSaveBNDREG; 962 963 /* Ext. save area 4: BNDCSR */ 964 typedef union XSaveBNDCSR { 965 BNDCSReg bndcsr; 966 uint8_t data[64]; 967 } XSaveBNDCSR; 968 969 /* Ext. save area 5: Opmask */ 970 typedef struct XSaveOpmask { 971 uint64_t opmask_regs[NB_OPMASK_REGS]; 972 } XSaveOpmask; 973 974 /* Ext. save area 6: ZMM_Hi256 */ 975 typedef struct XSaveZMM_Hi256 { 976 uint8_t zmm_hi256[16][32]; 977 } XSaveZMM_Hi256; 978 979 /* Ext. save area 7: Hi16_ZMM */ 980 typedef struct XSaveHi16_ZMM { 981 uint8_t hi16_zmm[16][64]; 982 } XSaveHi16_ZMM; 983 984 /* Ext. save area 9: PKRU state */ 985 typedef struct XSavePKRU { 986 uint32_t pkru; 987 uint32_t padding; 988 } XSavePKRU; 989 990 typedef struct X86XSaveArea { 991 X86LegacyXSaveArea legacy; 992 X86XSaveHeader header; 993 994 /* Extended save areas: */ 995 996 /* AVX State: */ 997 XSaveAVX avx_state; 998 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 999 /* MPX State: */ 1000 XSaveBNDREG bndreg_state; 1001 XSaveBNDCSR bndcsr_state; 1002 /* AVX-512 State: */ 1003 XSaveOpmask opmask_state; 1004 XSaveZMM_Hi256 zmm_hi256_state; 1005 XSaveHi16_ZMM hi16_zmm_state; 1006 /* PKRU State: */ 1007 XSavePKRU pkru_state; 1008 } X86XSaveArea; 1009 1010 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1011 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1012 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1013 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1014 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1015 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1016 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1017 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1018 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1019 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1020 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1021 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1022 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1023 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1024 1025 typedef enum TPRAccess { 1026 TPR_ACCESS_READ, 1027 TPR_ACCESS_WRITE, 1028 } TPRAccess; 1029 1030 typedef struct CPUX86State { 1031 /* standard registers */ 1032 target_ulong regs[CPU_NB_REGS]; 1033 target_ulong eip; 1034 target_ulong eflags; /* eflags register. During CPU emulation, CC 1035 flags and DF are set to zero because they are 1036 stored elsewhere */ 1037 1038 /* emulator internal eflags handling */ 1039 target_ulong cc_dst; 1040 target_ulong cc_src; 1041 target_ulong cc_src2; 1042 uint32_t cc_op; 1043 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1044 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1045 are known at translation time. */ 1046 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1047 1048 /* segments */ 1049 SegmentCache segs[6]; /* selector values */ 1050 SegmentCache ldt; 1051 SegmentCache tr; 1052 SegmentCache gdt; /* only base and limit are used */ 1053 SegmentCache idt; /* only base and limit are used */ 1054 1055 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1056 int32_t a20_mask; 1057 1058 BNDReg bnd_regs[4]; 1059 BNDCSReg bndcs_regs; 1060 uint64_t msr_bndcfgs; 1061 uint64_t efer; 1062 1063 /* Beginning of state preserved by INIT (dummy marker). */ 1064 struct {} start_init_save; 1065 1066 /* FPU state */ 1067 unsigned int fpstt; /* top of stack index */ 1068 uint16_t fpus; 1069 uint16_t fpuc; 1070 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1071 FPReg fpregs[8]; 1072 /* KVM-only so far */ 1073 uint16_t fpop; 1074 uint64_t fpip; 1075 uint64_t fpdp; 1076 1077 /* emulator internal variables */ 1078 float_status fp_status; 1079 floatx80 ft0; 1080 1081 float_status mmx_status; /* for 3DNow! float ops */ 1082 float_status sse_status; 1083 uint32_t mxcsr; 1084 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1085 ZMMReg xmm_t0; 1086 MMXReg mmx_t0; 1087 1088 XMMReg ymmh_regs[CPU_NB_REGS]; 1089 1090 uint64_t opmask_regs[NB_OPMASK_REGS]; 1091 YMMReg zmmh_regs[CPU_NB_REGS]; 1092 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1093 1094 /* sysenter registers */ 1095 uint32_t sysenter_cs; 1096 target_ulong sysenter_esp; 1097 target_ulong sysenter_eip; 1098 uint64_t star; 1099 1100 uint64_t vm_hsave; 1101 1102 #ifdef TARGET_X86_64 1103 target_ulong lstar; 1104 target_ulong cstar; 1105 target_ulong fmask; 1106 target_ulong kernelgsbase; 1107 #endif 1108 1109 uint64_t tsc; 1110 uint64_t tsc_adjust; 1111 uint64_t tsc_deadline; 1112 uint64_t tsc_aux; 1113 1114 uint64_t xcr0; 1115 1116 uint64_t mcg_status; 1117 uint64_t msr_ia32_misc_enable; 1118 uint64_t msr_ia32_feature_control; 1119 1120 uint64_t msr_fixed_ctr_ctrl; 1121 uint64_t msr_global_ctrl; 1122 uint64_t msr_global_status; 1123 uint64_t msr_global_ovf_ctrl; 1124 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1125 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1126 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1127 1128 uint64_t pat; 1129 uint32_t smbase; 1130 1131 uint32_t pkru; 1132 1133 uint64_t spec_ctrl; 1134 1135 /* End of state preserved by INIT (dummy marker). */ 1136 struct {} end_init_save; 1137 1138 uint64_t system_time_msr; 1139 uint64_t wall_clock_msr; 1140 uint64_t steal_time_msr; 1141 uint64_t async_pf_en_msr; 1142 uint64_t pv_eoi_en_msr; 1143 1144 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1145 uint64_t msr_hv_hypercall; 1146 uint64_t msr_hv_guest_os_id; 1147 uint64_t msr_hv_tsc; 1148 1149 /* Per-VCPU HV MSRs */ 1150 uint64_t msr_hv_vapic; 1151 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1152 uint64_t msr_hv_runtime; 1153 uint64_t msr_hv_synic_control; 1154 uint64_t msr_hv_synic_evt_page; 1155 uint64_t msr_hv_synic_msg_page; 1156 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1157 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1158 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1159 1160 /* exception/interrupt handling */ 1161 int error_code; 1162 int exception_is_int; 1163 target_ulong exception_next_eip; 1164 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1165 union { 1166 struct CPUBreakpoint *cpu_breakpoint[4]; 1167 struct CPUWatchpoint *cpu_watchpoint[4]; 1168 }; /* break/watchpoints for dr[0..3] */ 1169 int old_exception; /* exception in flight */ 1170 1171 uint64_t vm_vmcb; 1172 uint64_t tsc_offset; 1173 uint64_t intercept; 1174 uint16_t intercept_cr_read; 1175 uint16_t intercept_cr_write; 1176 uint16_t intercept_dr_read; 1177 uint16_t intercept_dr_write; 1178 uint32_t intercept_exceptions; 1179 uint8_t v_tpr; 1180 1181 /* KVM states, automatically cleared on reset */ 1182 uint8_t nmi_injected; 1183 uint8_t nmi_pending; 1184 1185 /* Fields up to this point are cleared by a CPU reset */ 1186 struct {} end_reset_fields; 1187 1188 CPU_COMMON 1189 1190 /* Fields after CPU_COMMON are preserved across CPU reset. */ 1191 1192 /* processor features (e.g. for CPUID insn) */ 1193 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1194 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1195 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1196 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1197 /* Actual level/xlevel/xlevel2 value: */ 1198 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1199 uint32_t cpuid_vendor1; 1200 uint32_t cpuid_vendor2; 1201 uint32_t cpuid_vendor3; 1202 uint32_t cpuid_version; 1203 FeatureWordArray features; 1204 /* Features that were explicitly enabled/disabled */ 1205 FeatureWordArray user_features; 1206 uint32_t cpuid_model[12]; 1207 1208 /* MTRRs */ 1209 uint64_t mtrr_fixed[11]; 1210 uint64_t mtrr_deftype; 1211 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1212 1213 /* For KVM */ 1214 uint32_t mp_state; 1215 int32_t exception_injected; 1216 int32_t interrupt_injected; 1217 uint8_t soft_interrupt; 1218 uint8_t has_error_code; 1219 uint32_t ins_len; 1220 uint32_t sipi_vector; 1221 bool tsc_valid; 1222 int64_t tsc_khz; 1223 int64_t user_tsc_khz; /* for sanity check only */ 1224 void *kvm_xsave_buf; 1225 #if defined(CONFIG_HVF) 1226 HVFX86EmulatorState *hvf_emul; 1227 #endif 1228 1229 uint64_t mcg_cap; 1230 uint64_t mcg_ctl; 1231 uint64_t mcg_ext_ctl; 1232 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1233 uint64_t xstate_bv; 1234 1235 /* vmstate */ 1236 uint16_t fpus_vmstate; 1237 uint16_t fptag_vmstate; 1238 uint16_t fpregs_format_vmstate; 1239 1240 uint64_t xss; 1241 1242 TPRAccess tpr_access_type; 1243 } CPUX86State; 1244 1245 struct kvm_msrs; 1246 1247 /** 1248 * X86CPU: 1249 * @env: #CPUX86State 1250 * @migratable: If set, only migratable flags will be accepted when "enforce" 1251 * mode is used, and only migratable flags will be included in the "host" 1252 * CPU model. 1253 * 1254 * An x86 CPU. 1255 */ 1256 struct X86CPU { 1257 /*< private >*/ 1258 CPUState parent_obj; 1259 /*< public >*/ 1260 1261 CPUX86State env; 1262 1263 bool hyperv_vapic; 1264 bool hyperv_relaxed_timing; 1265 int hyperv_spinlock_attempts; 1266 char *hyperv_vendor_id; 1267 bool hyperv_time; 1268 bool hyperv_crash; 1269 bool hyperv_reset; 1270 bool hyperv_vpindex; 1271 bool hyperv_runtime; 1272 bool hyperv_synic; 1273 bool hyperv_stimer; 1274 bool check_cpuid; 1275 bool enforce_cpuid; 1276 bool expose_kvm; 1277 bool expose_tcg; 1278 bool migratable; 1279 bool max_features; /* Enable all supported features automatically */ 1280 uint32_t apic_id; 1281 1282 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1283 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1284 bool vmware_cpuid_freq; 1285 1286 /* if true the CPUID code directly forward host cache leaves to the guest */ 1287 bool cache_info_passthrough; 1288 1289 /* Features that were filtered out because of missing host capabilities */ 1290 uint32_t filtered_features[FEATURE_WORDS]; 1291 1292 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1293 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1294 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1295 * capabilities) directly to the guest. 1296 */ 1297 bool enable_pmu; 1298 1299 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1300 * disabled by default to avoid breaking migration between QEMU with 1301 * different LMCE configurations. 1302 */ 1303 bool enable_lmce; 1304 1305 /* Compatibility bits for old machine types. 1306 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1307 * socket share an virtual l3 cache. 1308 */ 1309 bool enable_l3_cache; 1310 1311 /* Compatibility bits for old machine types: */ 1312 bool enable_cpuid_0xb; 1313 1314 /* Enable auto level-increase for all CPUID leaves */ 1315 bool full_cpuid_auto_level; 1316 1317 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1318 bool fill_mtrr_mask; 1319 1320 /* if true override the phys_bits value with a value read from the host */ 1321 bool host_phys_bits; 1322 1323 /* Stop SMI delivery for migration compatibility with old machines */ 1324 bool kvm_no_smi_migration; 1325 1326 /* Number of physical address bits supported */ 1327 uint32_t phys_bits; 1328 1329 /* in order to simplify APIC support, we leave this pointer to the 1330 user */ 1331 struct DeviceState *apic_state; 1332 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1333 Notifier machine_done; 1334 1335 struct kvm_msrs *kvm_msr_buf; 1336 1337 int32_t node_id; /* NUMA node this CPU belongs to */ 1338 int32_t socket_id; 1339 int32_t core_id; 1340 int32_t thread_id; 1341 1342 int32_t hv_max_vps; 1343 }; 1344 1345 static inline X86CPU *x86_env_get_cpu(CPUX86State *env) 1346 { 1347 return container_of(env, X86CPU, env); 1348 } 1349 1350 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) 1351 1352 #define ENV_OFFSET offsetof(X86CPU, env) 1353 1354 #ifndef CONFIG_USER_ONLY 1355 extern struct VMStateDescription vmstate_x86_cpu; 1356 #endif 1357 1358 /** 1359 * x86_cpu_do_interrupt: 1360 * @cpu: vCPU the interrupt is to be handled by. 1361 */ 1362 void x86_cpu_do_interrupt(CPUState *cpu); 1363 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1364 1365 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1366 int cpuid, void *opaque); 1367 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1368 int cpuid, void *opaque); 1369 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1370 void *opaque); 1371 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1372 void *opaque); 1373 1374 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1375 Error **errp); 1376 1377 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 1378 int flags); 1379 1380 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1381 1382 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1383 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1384 1385 void x86_cpu_exec_enter(CPUState *cpu); 1386 void x86_cpu_exec_exit(CPUState *cpu); 1387 1388 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1389 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1390 1391 int cpu_get_pic_interrupt(CPUX86State *s); 1392 /* MSDOS compatibility mode FPU exception support */ 1393 void cpu_set_ferr(CPUX86State *s); 1394 1395 /* this function must always be used to load data in the segment 1396 cache: it synchronizes the hflags with the segment cache values */ 1397 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1398 int seg_reg, unsigned int selector, 1399 target_ulong base, 1400 unsigned int limit, 1401 unsigned int flags) 1402 { 1403 SegmentCache *sc; 1404 unsigned int new_hflags; 1405 1406 sc = &env->segs[seg_reg]; 1407 sc->selector = selector; 1408 sc->base = base; 1409 sc->limit = limit; 1410 sc->flags = flags; 1411 1412 /* update the hidden flags */ 1413 { 1414 if (seg_reg == R_CS) { 1415 #ifdef TARGET_X86_64 1416 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1417 /* long mode */ 1418 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1419 env->hflags &= ~(HF_ADDSEG_MASK); 1420 } else 1421 #endif 1422 { 1423 /* legacy / compatibility case */ 1424 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1425 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1426 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1427 new_hflags; 1428 } 1429 } 1430 if (seg_reg == R_SS) { 1431 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1432 #if HF_CPL_MASK != 3 1433 #error HF_CPL_MASK is hardcoded 1434 #endif 1435 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1436 } 1437 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1438 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1439 if (env->hflags & HF_CS64_MASK) { 1440 /* zero base assumed for DS, ES and SS in long mode */ 1441 } else if (!(env->cr[0] & CR0_PE_MASK) || 1442 (env->eflags & VM_MASK) || 1443 !(env->hflags & HF_CS32_MASK)) { 1444 /* XXX: try to avoid this test. The problem comes from the 1445 fact that is real mode or vm86 mode we only modify the 1446 'base' and 'selector' fields of the segment cache to go 1447 faster. A solution may be to force addseg to one in 1448 translate-i386.c. */ 1449 new_hflags |= HF_ADDSEG_MASK; 1450 } else { 1451 new_hflags |= ((env->segs[R_DS].base | 1452 env->segs[R_ES].base | 1453 env->segs[R_SS].base) != 0) << 1454 HF_ADDSEG_SHIFT; 1455 } 1456 env->hflags = (env->hflags & 1457 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1458 } 1459 } 1460 1461 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1462 uint8_t sipi_vector) 1463 { 1464 CPUState *cs = CPU(cpu); 1465 CPUX86State *env = &cpu->env; 1466 1467 env->eip = 0; 1468 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1469 sipi_vector << 12, 1470 env->segs[R_CS].limit, 1471 env->segs[R_CS].flags); 1472 cs->halted = 0; 1473 } 1474 1475 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1476 target_ulong *base, unsigned int *limit, 1477 unsigned int *flags); 1478 1479 /* op_helper.c */ 1480 /* used for debug or cpu save/restore */ 1481 1482 /* cpu-exec.c */ 1483 /* the following helpers are only usable in user mode simulation as 1484 they can trigger unexpected exceptions */ 1485 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1486 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1487 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1488 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1489 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1490 1491 /* you can call this signal handler from your SIGBUS and SIGSEGV 1492 signal handlers to inform the virtual CPU of exceptions. non zero 1493 is returned if the signal was handled by the virtual CPU. */ 1494 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1495 void *puc); 1496 1497 /* cpu.c */ 1498 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1499 uint32_t *eax, uint32_t *ebx, 1500 uint32_t *ecx, uint32_t *edx); 1501 void cpu_clear_apic_feature(CPUX86State *env); 1502 void host_cpuid(uint32_t function, uint32_t count, 1503 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1504 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1505 1506 /* helper.c */ 1507 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, 1508 int is_write, int mmu_idx); 1509 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1510 1511 #ifndef CONFIG_USER_ONLY 1512 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1513 { 1514 return !!attrs.secure; 1515 } 1516 1517 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1518 { 1519 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1520 } 1521 1522 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1523 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1524 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1525 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1526 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1527 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1528 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1529 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1530 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1531 #endif 1532 1533 void breakpoint_handler(CPUState *cs); 1534 1535 /* will be suppressed */ 1536 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1537 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1538 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1539 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1540 1541 /* hw/pc.c */ 1542 uint64_t cpu_get_tsc(CPUX86State *env); 1543 1544 #define TARGET_PAGE_BITS 12 1545 1546 #ifdef TARGET_X86_64 1547 #define TARGET_PHYS_ADDR_SPACE_BITS 52 1548 /* ??? This is really 48 bits, sign-extended, but the only thing 1549 accessible to userland with bit 48 set is the VSYSCALL, and that 1550 is handled via other mechanisms. */ 1551 #define TARGET_VIRT_ADDR_SPACE_BITS 47 1552 #else 1553 #define TARGET_PHYS_ADDR_SPACE_BITS 36 1554 #define TARGET_VIRT_ADDR_SPACE_BITS 32 1555 #endif 1556 1557 /* XXX: This value should match the one returned by CPUID 1558 * and in exec.c */ 1559 # if defined(TARGET_X86_64) 1560 # define TCG_PHYS_ADDR_BITS 40 1561 # else 1562 # define TCG_PHYS_ADDR_BITS 36 1563 # endif 1564 1565 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1566 1567 #define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model) 1568 1569 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1570 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1571 1572 #ifdef TARGET_X86_64 1573 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1574 #else 1575 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1576 #endif 1577 1578 #define cpu_signal_handler cpu_x86_signal_handler 1579 #define cpu_list x86_cpu_list 1580 1581 /* MMU modes definitions */ 1582 #define MMU_MODE0_SUFFIX _ksmap 1583 #define MMU_MODE1_SUFFIX _user 1584 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1585 #define MMU_KSMAP_IDX 0 1586 #define MMU_USER_IDX 1 1587 #define MMU_KNOSMAP_IDX 2 1588 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1589 { 1590 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1591 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1592 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1593 } 1594 1595 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1596 { 1597 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1598 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1599 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1600 } 1601 1602 #define CC_DST (env->cc_dst) 1603 #define CC_SRC (env->cc_src) 1604 #define CC_SRC2 (env->cc_src2) 1605 #define CC_OP (env->cc_op) 1606 1607 /* n must be a constant to be efficient */ 1608 static inline target_long lshift(target_long x, int n) 1609 { 1610 if (n >= 0) { 1611 return x << n; 1612 } else { 1613 return x >> (-n); 1614 } 1615 } 1616 1617 /* float macros */ 1618 #define FT0 (env->ft0) 1619 #define ST0 (env->fpregs[env->fpstt].d) 1620 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1621 #define ST1 ST(1) 1622 1623 /* translate.c */ 1624 void tcg_x86_init(void); 1625 1626 #include "exec/cpu-all.h" 1627 #include "svm.h" 1628 1629 #if !defined(CONFIG_USER_ONLY) 1630 #include "hw/i386/apic.h" 1631 #endif 1632 1633 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1634 target_ulong *cs_base, uint32_t *flags) 1635 { 1636 *cs_base = env->segs[R_CS].base; 1637 *pc = *cs_base + env->eip; 1638 *flags = env->hflags | 1639 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1640 } 1641 1642 void do_cpu_init(X86CPU *cpu); 1643 void do_cpu_sipi(X86CPU *cpu); 1644 1645 #define MCE_INJECT_BROADCAST 1 1646 #define MCE_INJECT_UNCOND_AO 2 1647 1648 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1649 uint64_t status, uint64_t mcg_status, uint64_t addr, 1650 uint64_t misc, int flags); 1651 1652 /* excp_helper.c */ 1653 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1654 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1655 uintptr_t retaddr); 1656 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1657 int error_code); 1658 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1659 int error_code, uintptr_t retaddr); 1660 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1661 int error_code, int next_eip_addend); 1662 1663 /* cc_helper.c */ 1664 extern const uint8_t parity_table[256]; 1665 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1666 1667 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1668 { 1669 uint32_t eflags = env->eflags; 1670 if (tcg_enabled()) { 1671 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 1672 } 1673 return eflags; 1674 } 1675 1676 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1677 * after generating a call to a helper that uses this. 1678 */ 1679 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1680 int update_mask) 1681 { 1682 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1683 CC_OP = CC_OP_EFLAGS; 1684 env->df = 1 - (2 * ((eflags >> 10) & 1)); 1685 env->eflags = (env->eflags & ~update_mask) | 1686 (eflags & update_mask) | 0x2; 1687 } 1688 1689 /* load efer and update the corresponding hflags. XXX: do consistency 1690 checks with cpuid bits? */ 1691 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1692 { 1693 env->efer = val; 1694 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1695 if (env->efer & MSR_EFER_LMA) { 1696 env->hflags |= HF_LMA_MASK; 1697 } 1698 if (env->efer & MSR_EFER_SVME) { 1699 env->hflags |= HF_SVME_MASK; 1700 } 1701 } 1702 1703 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 1704 { 1705 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 1706 } 1707 1708 static inline int32_t x86_get_a20_mask(CPUX86State *env) 1709 { 1710 if (env->hflags & HF_SMM_MASK) { 1711 return -1; 1712 } else { 1713 return env->a20_mask; 1714 } 1715 } 1716 1717 /* fpu_helper.c */ 1718 void update_fp_status(CPUX86State *env); 1719 void update_mxcsr_status(CPUX86State *env); 1720 1721 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 1722 { 1723 env->mxcsr = mxcsr; 1724 if (tcg_enabled()) { 1725 update_mxcsr_status(env); 1726 } 1727 } 1728 1729 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 1730 { 1731 env->fpuc = fpuc; 1732 if (tcg_enabled()) { 1733 update_fp_status(env); 1734 } 1735 } 1736 1737 /* mem_helper.c */ 1738 void helper_lock_init(void); 1739 1740 /* svm_helper.c */ 1741 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 1742 uint64_t param, uintptr_t retaddr); 1743 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, 1744 uintptr_t retaddr); 1745 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 1746 1747 /* seg_helper.c */ 1748 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 1749 1750 /* smm_helper.c */ 1751 void do_smm_enter(X86CPU *cpu); 1752 1753 /* apic.c */ 1754 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 1755 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 1756 TPRAccess access); 1757 1758 1759 /* Change the value of a KVM-specific default 1760 * 1761 * If value is NULL, no default will be set and the original 1762 * value from the CPU model table will be kept. 1763 * 1764 * It is valid to call this function only for properties that 1765 * are already present in the kvm_default_props table. 1766 */ 1767 void x86_cpu_change_kvm_default(const char *prop, const char *value); 1768 1769 /* mpx_helper.c */ 1770 void cpu_sync_bndcs_hflags(CPUX86State *env); 1771 1772 /* Return name of 32-bit register, from a R_* constant */ 1773 const char *get_register_name_32(unsigned int reg); 1774 1775 void enable_compat_apic_id_mode(void); 1776 1777 #define APIC_DEFAULT_ADDRESS 0xfee00000 1778 #define APIC_SPACE_SIZE 0x100000 1779 1780 void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, 1781 fprintf_function cpu_fprintf, int flags); 1782 1783 /* cpu.c */ 1784 bool cpu_is_bsp(X86CPU *cpu); 1785 1786 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 1787 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 1788 void x86_update_hflags(CPUX86State* env); 1789 1790 #endif /* I386_CPU_H */ 1791