xref: /openbmc/qemu/target/i386/cpu.h (revision 8f951a13f0dd801dcf95c822091a7db49b323ca2)
1 
2 /*
3  * i386 virtual CPU header
4  *
5  *  Copyright (c) 2003 Fabrice Bellard
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #ifndef I386_CPU_H
22 #define I386_CPU_H
23 
24 #include "qemu-common.h"
25 #include "cpu-qom.h"
26 #include "hyperv-proto.h"
27 
28 #ifdef TARGET_X86_64
29 #define TARGET_LONG_BITS 64
30 #else
31 #define TARGET_LONG_BITS 32
32 #endif
33 
34 #include "exec/cpu-defs.h"
35 
36 /* The x86 has a strong memory model with some store-after-load re-ordering */
37 #define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
38 
39 /* Maximum instruction code size */
40 #define TARGET_MAX_INSN_SIZE 16
41 
42 /* support for self modifying code even if the modified instruction is
43    close to the modifying instruction */
44 #define TARGET_HAS_PRECISE_SMC
45 
46 #ifdef TARGET_X86_64
47 #define I386_ELF_MACHINE  EM_X86_64
48 #define ELF_MACHINE_UNAME "x86_64"
49 #else
50 #define I386_ELF_MACHINE  EM_386
51 #define ELF_MACHINE_UNAME "i686"
52 #endif
53 
54 #define CPUArchState struct CPUX86State
55 
56 enum {
57     R_EAX = 0,
58     R_ECX = 1,
59     R_EDX = 2,
60     R_EBX = 3,
61     R_ESP = 4,
62     R_EBP = 5,
63     R_ESI = 6,
64     R_EDI = 7,
65     R_R8 = 8,
66     R_R9 = 9,
67     R_R10 = 10,
68     R_R11 = 11,
69     R_R12 = 12,
70     R_R13 = 13,
71     R_R14 = 14,
72     R_R15 = 15,
73 
74     R_AL = 0,
75     R_CL = 1,
76     R_DL = 2,
77     R_BL = 3,
78     R_AH = 4,
79     R_CH = 5,
80     R_DH = 6,
81     R_BH = 7,
82 };
83 
84 typedef enum X86Seg {
85     R_ES = 0,
86     R_CS = 1,
87     R_SS = 2,
88     R_DS = 3,
89     R_FS = 4,
90     R_GS = 5,
91     R_LDTR = 6,
92     R_TR = 7,
93 } X86Seg;
94 
95 /* segment descriptor fields */
96 #define DESC_G_SHIFT    23
97 #define DESC_G_MASK     (1 << DESC_G_SHIFT)
98 #define DESC_B_SHIFT    22
99 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
100 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
101 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
102 #define DESC_AVL_SHIFT  20
103 #define DESC_AVL_MASK   (1 << DESC_AVL_SHIFT)
104 #define DESC_P_SHIFT    15
105 #define DESC_P_MASK     (1 << DESC_P_SHIFT)
106 #define DESC_DPL_SHIFT  13
107 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
108 #define DESC_S_SHIFT    12
109 #define DESC_S_MASK     (1 << DESC_S_SHIFT)
110 #define DESC_TYPE_SHIFT 8
111 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
112 #define DESC_A_MASK     (1 << 8)
113 
114 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
115 #define DESC_C_MASK     (1 << 10) /* code: conforming */
116 #define DESC_R_MASK     (1 << 9)  /* code: readable */
117 
118 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
119 #define DESC_W_MASK     (1 << 9)  /* data: writable */
120 
121 #define DESC_TSS_BUSY_MASK (1 << 9)
122 
123 /* eflags masks */
124 #define CC_C    0x0001
125 #define CC_P    0x0004
126 #define CC_A    0x0010
127 #define CC_Z    0x0040
128 #define CC_S    0x0080
129 #define CC_O    0x0800
130 
131 #define TF_SHIFT   8
132 #define IOPL_SHIFT 12
133 #define VM_SHIFT   17
134 
135 #define TF_MASK                 0x00000100
136 #define IF_MASK                 0x00000200
137 #define DF_MASK                 0x00000400
138 #define IOPL_MASK               0x00003000
139 #define NT_MASK                 0x00004000
140 #define RF_MASK                 0x00010000
141 #define VM_MASK                 0x00020000
142 #define AC_MASK                 0x00040000
143 #define VIF_MASK                0x00080000
144 #define VIP_MASK                0x00100000
145 #define ID_MASK                 0x00200000
146 
147 /* hidden flags - used internally by qemu to represent additional cpu
148    states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
149    avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
150    positions to ease oring with eflags. */
151 /* current cpl */
152 #define HF_CPL_SHIFT         0
153 /* true if hardware interrupts must be disabled for next instruction */
154 #define HF_INHIBIT_IRQ_SHIFT 3
155 /* 16 or 32 segments */
156 #define HF_CS32_SHIFT        4
157 #define HF_SS32_SHIFT        5
158 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
159 #define HF_ADDSEG_SHIFT      6
160 /* copy of CR0.PE (protected mode) */
161 #define HF_PE_SHIFT          7
162 #define HF_TF_SHIFT          8 /* must be same as eflags */
163 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
164 #define HF_EM_SHIFT         10
165 #define HF_TS_SHIFT         11
166 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
167 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
168 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
169 #define HF_RF_SHIFT         16 /* must be same as eflags */
170 #define HF_VM_SHIFT         17 /* must be same as eflags */
171 #define HF_AC_SHIFT         18 /* must be same as eflags */
172 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
173 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
174 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
175 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
176 #define HF_SMAP_SHIFT       23 /* CR4.SMAP */
177 #define HF_IOBPT_SHIFT      24 /* an io breakpoint enabled */
178 #define HF_MPX_EN_SHIFT     25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
179 #define HF_MPX_IU_SHIFT     26 /* BND registers in-use */
180 
181 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
182 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
183 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
184 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
185 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
186 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
187 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
188 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
189 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
190 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
191 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
192 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
193 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
194 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
195 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
196 #define HF_AC_MASK           (1 << HF_AC_SHIFT)
197 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
198 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
199 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
200 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
201 #define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
202 #define HF_IOBPT_MASK        (1 << HF_IOBPT_SHIFT)
203 #define HF_MPX_EN_MASK       (1 << HF_MPX_EN_SHIFT)
204 #define HF_MPX_IU_MASK       (1 << HF_MPX_IU_SHIFT)
205 
206 /* hflags2 */
207 
208 #define HF2_GIF_SHIFT            0 /* if set CPU takes interrupts */
209 #define HF2_HIF_SHIFT            1 /* value of IF_MASK when entering SVM */
210 #define HF2_NMI_SHIFT            2 /* CPU serving NMI */
211 #define HF2_VINTR_SHIFT          3 /* value of V_INTR_MASKING bit */
212 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
213 #define HF2_MPX_PR_SHIFT         5 /* BNDCFGx.BNDPRESERVE */
214 
215 #define HF2_GIF_MASK            (1 << HF2_GIF_SHIFT)
216 #define HF2_HIF_MASK            (1 << HF2_HIF_SHIFT)
217 #define HF2_NMI_MASK            (1 << HF2_NMI_SHIFT)
218 #define HF2_VINTR_MASK          (1 << HF2_VINTR_SHIFT)
219 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
220 #define HF2_MPX_PR_MASK         (1 << HF2_MPX_PR_SHIFT)
221 
222 #define CR0_PE_SHIFT 0
223 #define CR0_MP_SHIFT 1
224 
225 #define CR0_PE_MASK  (1U << 0)
226 #define CR0_MP_MASK  (1U << 1)
227 #define CR0_EM_MASK  (1U << 2)
228 #define CR0_TS_MASK  (1U << 3)
229 #define CR0_ET_MASK  (1U << 4)
230 #define CR0_NE_MASK  (1U << 5)
231 #define CR0_WP_MASK  (1U << 16)
232 #define CR0_AM_MASK  (1U << 18)
233 #define CR0_PG_MASK  (1U << 31)
234 
235 #define CR4_VME_MASK  (1U << 0)
236 #define CR4_PVI_MASK  (1U << 1)
237 #define CR4_TSD_MASK  (1U << 2)
238 #define CR4_DE_MASK   (1U << 3)
239 #define CR4_PSE_MASK  (1U << 4)
240 #define CR4_PAE_MASK  (1U << 5)
241 #define CR4_MCE_MASK  (1U << 6)
242 #define CR4_PGE_MASK  (1U << 7)
243 #define CR4_PCE_MASK  (1U << 8)
244 #define CR4_OSFXSR_SHIFT 9
245 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
246 #define CR4_OSXMMEXCPT_MASK  (1U << 10)
247 #define CR4_LA57_MASK   (1U << 12)
248 #define CR4_VMXE_MASK   (1U << 13)
249 #define CR4_SMXE_MASK   (1U << 14)
250 #define CR4_FSGSBASE_MASK (1U << 16)
251 #define CR4_PCIDE_MASK  (1U << 17)
252 #define CR4_OSXSAVE_MASK (1U << 18)
253 #define CR4_SMEP_MASK   (1U << 20)
254 #define CR4_SMAP_MASK   (1U << 21)
255 #define CR4_PKE_MASK   (1U << 22)
256 
257 #define DR6_BD          (1 << 13)
258 #define DR6_BS          (1 << 14)
259 #define DR6_BT          (1 << 15)
260 #define DR6_FIXED_1     0xffff0ff0
261 
262 #define DR7_GD          (1 << 13)
263 #define DR7_TYPE_SHIFT  16
264 #define DR7_LEN_SHIFT   18
265 #define DR7_FIXED_1     0x00000400
266 #define DR7_GLOBAL_BP_MASK   0xaa
267 #define DR7_LOCAL_BP_MASK    0x55
268 #define DR7_MAX_BP           4
269 #define DR7_TYPE_BP_INST     0x0
270 #define DR7_TYPE_DATA_WR     0x1
271 #define DR7_TYPE_IO_RW       0x2
272 #define DR7_TYPE_DATA_RW     0x3
273 
274 #define PG_PRESENT_BIT  0
275 #define PG_RW_BIT       1
276 #define PG_USER_BIT     2
277 #define PG_PWT_BIT      3
278 #define PG_PCD_BIT      4
279 #define PG_ACCESSED_BIT 5
280 #define PG_DIRTY_BIT    6
281 #define PG_PSE_BIT      7
282 #define PG_GLOBAL_BIT   8
283 #define PG_PSE_PAT_BIT  12
284 #define PG_PKRU_BIT     59
285 #define PG_NX_BIT       63
286 
287 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
288 #define PG_RW_MASK       (1 << PG_RW_BIT)
289 #define PG_USER_MASK     (1 << PG_USER_BIT)
290 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
291 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
292 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
293 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
294 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
295 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
296 #define PG_PSE_PAT_MASK  (1 << PG_PSE_PAT_BIT)
297 #define PG_ADDRESS_MASK  0x000ffffffffff000LL
298 #define PG_HI_RSVD_MASK  (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
299 #define PG_HI_USER_MASK  0x7ff0000000000000LL
300 #define PG_PKRU_MASK     (15ULL << PG_PKRU_BIT)
301 #define PG_NX_MASK       (1ULL << PG_NX_BIT)
302 
303 #define PG_ERROR_W_BIT     1
304 
305 #define PG_ERROR_P_MASK    0x01
306 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
307 #define PG_ERROR_U_MASK    0x04
308 #define PG_ERROR_RSVD_MASK 0x08
309 #define PG_ERROR_I_D_MASK  0x10
310 #define PG_ERROR_PK_MASK   0x20
311 
312 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
313 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
314 #define MCG_LMCE_P      (1ULL<<27) /* Local Machine Check Supported */
315 
316 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
317 #define MCE_BANKS_DEF   10
318 
319 #define MCG_CAP_BANKS_MASK 0xff
320 
321 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
322 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
323 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
324 #define MCG_STATUS_LMCE (1ULL<<3)   /* Local MCE signaled */
325 
326 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
327 
328 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
329 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
330 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
331 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
332 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
333 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
334 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
335 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
336 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
337 
338 /* MISC register defines */
339 #define MCM_ADDR_SEGOFF  0      /* segment offset */
340 #define MCM_ADDR_LINEAR  1      /* linear address */
341 #define MCM_ADDR_PHYS    2      /* physical address */
342 #define MCM_ADDR_MEM     3      /* memory address */
343 #define MCM_ADDR_GENERIC 7      /* generic */
344 
345 #define MSR_IA32_TSC                    0x10
346 #define MSR_IA32_APICBASE               0x1b
347 #define MSR_IA32_APICBASE_BSP           (1<<8)
348 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
349 #define MSR_IA32_APICBASE_EXTD          (1 << 10)
350 #define MSR_IA32_APICBASE_BASE          (0xfffffU<<12)
351 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
352 #define MSR_TSC_ADJUST                  0x0000003b
353 #define MSR_IA32_SPEC_CTRL              0x48
354 #define MSR_VIRT_SSBD                   0xc001011f
355 #define MSR_IA32_TSCDEADLINE            0x6e0
356 
357 #define FEATURE_CONTROL_LOCKED                    (1<<0)
358 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
359 #define FEATURE_CONTROL_LMCE                      (1<<20)
360 
361 #define MSR_P6_PERFCTR0                 0xc1
362 
363 #define MSR_IA32_SMBASE                 0x9e
364 #define MSR_SMI_COUNT                   0x34
365 #define MSR_MTRRcap                     0xfe
366 #define MSR_MTRRcap_VCNT                8
367 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
368 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
369 
370 #define MSR_IA32_SYSENTER_CS            0x174
371 #define MSR_IA32_SYSENTER_ESP           0x175
372 #define MSR_IA32_SYSENTER_EIP           0x176
373 
374 #define MSR_MCG_CAP                     0x179
375 #define MSR_MCG_STATUS                  0x17a
376 #define MSR_MCG_CTL                     0x17b
377 #define MSR_MCG_EXT_CTL                 0x4d0
378 
379 #define MSR_P6_EVNTSEL0                 0x186
380 
381 #define MSR_IA32_PERF_STATUS            0x198
382 
383 #define MSR_IA32_MISC_ENABLE            0x1a0
384 /* Indicates good rep/movs microcode on some processors: */
385 #define MSR_IA32_MISC_ENABLE_DEFAULT    1
386 
387 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
388 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
389 
390 #define MSR_MTRRphysIndex(addr)         ((((addr) & ~1u) - 0x200) / 2)
391 
392 #define MSR_MTRRfix64K_00000            0x250
393 #define MSR_MTRRfix16K_80000            0x258
394 #define MSR_MTRRfix16K_A0000            0x259
395 #define MSR_MTRRfix4K_C0000             0x268
396 #define MSR_MTRRfix4K_C8000             0x269
397 #define MSR_MTRRfix4K_D0000             0x26a
398 #define MSR_MTRRfix4K_D8000             0x26b
399 #define MSR_MTRRfix4K_E0000             0x26c
400 #define MSR_MTRRfix4K_E8000             0x26d
401 #define MSR_MTRRfix4K_F0000             0x26e
402 #define MSR_MTRRfix4K_F8000             0x26f
403 
404 #define MSR_PAT                         0x277
405 
406 #define MSR_MTRRdefType                 0x2ff
407 
408 #define MSR_CORE_PERF_FIXED_CTR0        0x309
409 #define MSR_CORE_PERF_FIXED_CTR1        0x30a
410 #define MSR_CORE_PERF_FIXED_CTR2        0x30b
411 #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
412 #define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
413 #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
414 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
415 
416 #define MSR_MC0_CTL                     0x400
417 #define MSR_MC0_STATUS                  0x401
418 #define MSR_MC0_ADDR                    0x402
419 #define MSR_MC0_MISC                    0x403
420 
421 #define MSR_IA32_RTIT_OUTPUT_BASE       0x560
422 #define MSR_IA32_RTIT_OUTPUT_MASK       0x561
423 #define MSR_IA32_RTIT_CTL               0x570
424 #define MSR_IA32_RTIT_STATUS            0x571
425 #define MSR_IA32_RTIT_CR3_MATCH         0x572
426 #define MSR_IA32_RTIT_ADDR0_A           0x580
427 #define MSR_IA32_RTIT_ADDR0_B           0x581
428 #define MSR_IA32_RTIT_ADDR1_A           0x582
429 #define MSR_IA32_RTIT_ADDR1_B           0x583
430 #define MSR_IA32_RTIT_ADDR2_A           0x584
431 #define MSR_IA32_RTIT_ADDR2_B           0x585
432 #define MSR_IA32_RTIT_ADDR3_A           0x586
433 #define MSR_IA32_RTIT_ADDR3_B           0x587
434 #define MAX_RTIT_ADDRS                  8
435 
436 #define MSR_EFER                        0xc0000080
437 
438 #define MSR_EFER_SCE   (1 << 0)
439 #define MSR_EFER_LME   (1 << 8)
440 #define MSR_EFER_LMA   (1 << 10)
441 #define MSR_EFER_NXE   (1 << 11)
442 #define MSR_EFER_SVME  (1 << 12)
443 #define MSR_EFER_FFXSR (1 << 14)
444 
445 #define MSR_STAR                        0xc0000081
446 #define MSR_LSTAR                       0xc0000082
447 #define MSR_CSTAR                       0xc0000083
448 #define MSR_FMASK                       0xc0000084
449 #define MSR_FSBASE                      0xc0000100
450 #define MSR_GSBASE                      0xc0000101
451 #define MSR_KERNELGSBASE                0xc0000102
452 #define MSR_TSC_AUX                     0xc0000103
453 
454 #define MSR_VM_HSAVE_PA                 0xc0010117
455 
456 #define MSR_IA32_BNDCFGS                0x00000d90
457 #define MSR_IA32_XSS                    0x00000da0
458 
459 #define XSTATE_FP_BIT                   0
460 #define XSTATE_SSE_BIT                  1
461 #define XSTATE_YMM_BIT                  2
462 #define XSTATE_BNDREGS_BIT              3
463 #define XSTATE_BNDCSR_BIT               4
464 #define XSTATE_OPMASK_BIT               5
465 #define XSTATE_ZMM_Hi256_BIT            6
466 #define XSTATE_Hi16_ZMM_BIT             7
467 #define XSTATE_PKRU_BIT                 9
468 
469 #define XSTATE_FP_MASK                  (1ULL << XSTATE_FP_BIT)
470 #define XSTATE_SSE_MASK                 (1ULL << XSTATE_SSE_BIT)
471 #define XSTATE_YMM_MASK                 (1ULL << XSTATE_YMM_BIT)
472 #define XSTATE_BNDREGS_MASK             (1ULL << XSTATE_BNDREGS_BIT)
473 #define XSTATE_BNDCSR_MASK              (1ULL << XSTATE_BNDCSR_BIT)
474 #define XSTATE_OPMASK_MASK              (1ULL << XSTATE_OPMASK_BIT)
475 #define XSTATE_ZMM_Hi256_MASK           (1ULL << XSTATE_ZMM_Hi256_BIT)
476 #define XSTATE_Hi16_ZMM_MASK            (1ULL << XSTATE_Hi16_ZMM_BIT)
477 #define XSTATE_PKRU_MASK                (1ULL << XSTATE_PKRU_BIT)
478 
479 /* CPUID feature words */
480 typedef enum FeatureWord {
481     FEAT_1_EDX,         /* CPUID[1].EDX */
482     FEAT_1_ECX,         /* CPUID[1].ECX */
483     FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
484     FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */
485     FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */
486     FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
487     FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
488     FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
489     FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
490     FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
491     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
492     FEAT_KVM_HINTS,     /* CPUID[4000_0001].EDX */
493     FEAT_HYPERV_EAX,    /* CPUID[4000_0003].EAX */
494     FEAT_HYPERV_EBX,    /* CPUID[4000_0003].EBX */
495     FEAT_HYPERV_EDX,    /* CPUID[4000_0003].EDX */
496     FEAT_SVM,           /* CPUID[8000_000A].EDX */
497     FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */
498     FEAT_6_EAX,         /* CPUID[6].EAX */
499     FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
500     FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
501     FEATURE_WORDS,
502 } FeatureWord;
503 
504 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
505 
506 /* cpuid_features bits */
507 #define CPUID_FP87 (1U << 0)
508 #define CPUID_VME  (1U << 1)
509 #define CPUID_DE   (1U << 2)
510 #define CPUID_PSE  (1U << 3)
511 #define CPUID_TSC  (1U << 4)
512 #define CPUID_MSR  (1U << 5)
513 #define CPUID_PAE  (1U << 6)
514 #define CPUID_MCE  (1U << 7)
515 #define CPUID_CX8  (1U << 8)
516 #define CPUID_APIC (1U << 9)
517 #define CPUID_SEP  (1U << 11) /* sysenter/sysexit */
518 #define CPUID_MTRR (1U << 12)
519 #define CPUID_PGE  (1U << 13)
520 #define CPUID_MCA  (1U << 14)
521 #define CPUID_CMOV (1U << 15)
522 #define CPUID_PAT  (1U << 16)
523 #define CPUID_PSE36   (1U << 17)
524 #define CPUID_PN   (1U << 18)
525 #define CPUID_CLFLUSH (1U << 19)
526 #define CPUID_DTS (1U << 21)
527 #define CPUID_ACPI (1U << 22)
528 #define CPUID_MMX  (1U << 23)
529 #define CPUID_FXSR (1U << 24)
530 #define CPUID_SSE  (1U << 25)
531 #define CPUID_SSE2 (1U << 26)
532 #define CPUID_SS (1U << 27)
533 #define CPUID_HT (1U << 28)
534 #define CPUID_TM (1U << 29)
535 #define CPUID_IA64 (1U << 30)
536 #define CPUID_PBE (1U << 31)
537 
538 #define CPUID_EXT_SSE3     (1U << 0)
539 #define CPUID_EXT_PCLMULQDQ (1U << 1)
540 #define CPUID_EXT_DTES64   (1U << 2)
541 #define CPUID_EXT_MONITOR  (1U << 3)
542 #define CPUID_EXT_DSCPL    (1U << 4)
543 #define CPUID_EXT_VMX      (1U << 5)
544 #define CPUID_EXT_SMX      (1U << 6)
545 #define CPUID_EXT_EST      (1U << 7)
546 #define CPUID_EXT_TM2      (1U << 8)
547 #define CPUID_EXT_SSSE3    (1U << 9)
548 #define CPUID_EXT_CID      (1U << 10)
549 #define CPUID_EXT_FMA      (1U << 12)
550 #define CPUID_EXT_CX16     (1U << 13)
551 #define CPUID_EXT_XTPR     (1U << 14)
552 #define CPUID_EXT_PDCM     (1U << 15)
553 #define CPUID_EXT_PCID     (1U << 17)
554 #define CPUID_EXT_DCA      (1U << 18)
555 #define CPUID_EXT_SSE41    (1U << 19)
556 #define CPUID_EXT_SSE42    (1U << 20)
557 #define CPUID_EXT_X2APIC   (1U << 21)
558 #define CPUID_EXT_MOVBE    (1U << 22)
559 #define CPUID_EXT_POPCNT   (1U << 23)
560 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
561 #define CPUID_EXT_AES      (1U << 25)
562 #define CPUID_EXT_XSAVE    (1U << 26)
563 #define CPUID_EXT_OSXSAVE  (1U << 27)
564 #define CPUID_EXT_AVX      (1U << 28)
565 #define CPUID_EXT_F16C     (1U << 29)
566 #define CPUID_EXT_RDRAND   (1U << 30)
567 #define CPUID_EXT_HYPERVISOR  (1U << 31)
568 
569 #define CPUID_EXT2_FPU     (1U << 0)
570 #define CPUID_EXT2_VME     (1U << 1)
571 #define CPUID_EXT2_DE      (1U << 2)
572 #define CPUID_EXT2_PSE     (1U << 3)
573 #define CPUID_EXT2_TSC     (1U << 4)
574 #define CPUID_EXT2_MSR     (1U << 5)
575 #define CPUID_EXT2_PAE     (1U << 6)
576 #define CPUID_EXT2_MCE     (1U << 7)
577 #define CPUID_EXT2_CX8     (1U << 8)
578 #define CPUID_EXT2_APIC    (1U << 9)
579 #define CPUID_EXT2_SYSCALL (1U << 11)
580 #define CPUID_EXT2_MTRR    (1U << 12)
581 #define CPUID_EXT2_PGE     (1U << 13)
582 #define CPUID_EXT2_MCA     (1U << 14)
583 #define CPUID_EXT2_CMOV    (1U << 15)
584 #define CPUID_EXT2_PAT     (1U << 16)
585 #define CPUID_EXT2_PSE36   (1U << 17)
586 #define CPUID_EXT2_MP      (1U << 19)
587 #define CPUID_EXT2_NX      (1U << 20)
588 #define CPUID_EXT2_MMXEXT  (1U << 22)
589 #define CPUID_EXT2_MMX     (1U << 23)
590 #define CPUID_EXT2_FXSR    (1U << 24)
591 #define CPUID_EXT2_FFXSR   (1U << 25)
592 #define CPUID_EXT2_PDPE1GB (1U << 26)
593 #define CPUID_EXT2_RDTSCP  (1U << 27)
594 #define CPUID_EXT2_LM      (1U << 29)
595 #define CPUID_EXT2_3DNOWEXT (1U << 30)
596 #define CPUID_EXT2_3DNOW   (1U << 31)
597 
598 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
599 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
600                                 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
601                                 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
602                                 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
603                                 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
604                                 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
605                                 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
606                                 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
607                                 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
608 
609 #define CPUID_EXT3_LAHF_LM (1U << 0)
610 #define CPUID_EXT3_CMP_LEG (1U << 1)
611 #define CPUID_EXT3_SVM     (1U << 2)
612 #define CPUID_EXT3_EXTAPIC (1U << 3)
613 #define CPUID_EXT3_CR8LEG  (1U << 4)
614 #define CPUID_EXT3_ABM     (1U << 5)
615 #define CPUID_EXT3_SSE4A   (1U << 6)
616 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
617 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
618 #define CPUID_EXT3_OSVW    (1U << 9)
619 #define CPUID_EXT3_IBS     (1U << 10)
620 #define CPUID_EXT3_XOP     (1U << 11)
621 #define CPUID_EXT3_SKINIT  (1U << 12)
622 #define CPUID_EXT3_WDT     (1U << 13)
623 #define CPUID_EXT3_LWP     (1U << 15)
624 #define CPUID_EXT3_FMA4    (1U << 16)
625 #define CPUID_EXT3_TCE     (1U << 17)
626 #define CPUID_EXT3_NODEID  (1U << 19)
627 #define CPUID_EXT3_TBM     (1U << 21)
628 #define CPUID_EXT3_TOPOEXT (1U << 22)
629 #define CPUID_EXT3_PERFCORE (1U << 23)
630 #define CPUID_EXT3_PERFNB  (1U << 24)
631 
632 #define CPUID_SVM_NPT          (1U << 0)
633 #define CPUID_SVM_LBRV         (1U << 1)
634 #define CPUID_SVM_SVMLOCK      (1U << 2)
635 #define CPUID_SVM_NRIPSAVE     (1U << 3)
636 #define CPUID_SVM_TSCSCALE     (1U << 4)
637 #define CPUID_SVM_VMCBCLEAN    (1U << 5)
638 #define CPUID_SVM_FLUSHASID    (1U << 6)
639 #define CPUID_SVM_DECODEASSIST (1U << 7)
640 #define CPUID_SVM_PAUSEFILTER  (1U << 10)
641 #define CPUID_SVM_PFTHRESHOLD  (1U << 12)
642 
643 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
644 #define CPUID_7_0_EBX_BMI1     (1U << 3)
645 #define CPUID_7_0_EBX_HLE      (1U << 4)
646 #define CPUID_7_0_EBX_AVX2     (1U << 5)
647 #define CPUID_7_0_EBX_SMEP     (1U << 7)
648 #define CPUID_7_0_EBX_BMI2     (1U << 8)
649 #define CPUID_7_0_EBX_ERMS     (1U << 9)
650 #define CPUID_7_0_EBX_INVPCID  (1U << 10)
651 #define CPUID_7_0_EBX_RTM      (1U << 11)
652 #define CPUID_7_0_EBX_MPX      (1U << 14)
653 #define CPUID_7_0_EBX_AVX512F  (1U << 16) /* AVX-512 Foundation */
654 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
655 #define CPUID_7_0_EBX_RDSEED   (1U << 18)
656 #define CPUID_7_0_EBX_ADX      (1U << 19)
657 #define CPUID_7_0_EBX_SMAP     (1U << 20)
658 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
659 #define CPUID_7_0_EBX_PCOMMIT  (1U << 22) /* Persistent Commit */
660 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
661 #define CPUID_7_0_EBX_CLWB     (1U << 24) /* Cache Line Write Back */
662 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
663 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
664 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
665 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
666 #define CPUID_7_0_EBX_SHA_NI   (1U << 29) /* SHA1/SHA256 Instruction Extensions */
667 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
668 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
669 
670 #define CPUID_7_0_ECX_AVX512BMI (1U << 1)
671 #define CPUID_7_0_ECX_VBMI     (1U << 1)  /* AVX-512 Vector Byte Manipulation Instrs */
672 #define CPUID_7_0_ECX_UMIP     (1U << 2)
673 #define CPUID_7_0_ECX_PKU      (1U << 3)
674 #define CPUID_7_0_ECX_OSPKE    (1U << 4)
675 #define CPUID_7_0_ECX_VBMI2    (1U << 6) /* Additional VBMI Instrs */
676 #define CPUID_7_0_ECX_GFNI     (1U << 8)
677 #define CPUID_7_0_ECX_VAES     (1U << 9)
678 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
679 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
680 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
681 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
682 #define CPUID_7_0_ECX_LA57     (1U << 16)
683 #define CPUID_7_0_ECX_RDPID    (1U << 22)
684 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)  /* CLDEMOTE Instruction */
685 
686 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
687 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
688 #define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */
689 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */
690 
691 #define CPUID_8000_0008_EBX_IBPB    (1U << 12) /* Indirect Branch Prediction Barrier */
692 
693 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
694 #define CPUID_XSAVE_XSAVEC     (1U << 1)
695 #define CPUID_XSAVE_XGETBV1    (1U << 2)
696 #define CPUID_XSAVE_XSAVES     (1U << 3)
697 
698 #define CPUID_6_EAX_ARAT       (1U << 2)
699 
700 /* CPUID[0x80000007].EDX flags: */
701 #define CPUID_APM_INVTSC       (1U << 8)
702 
703 #define CPUID_VENDOR_SZ      12
704 
705 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
706 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
707 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
708 #define CPUID_VENDOR_INTEL "GenuineIntel"
709 
710 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
711 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
712 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
713 #define CPUID_VENDOR_AMD   "AuthenticAMD"
714 
715 #define CPUID_VENDOR_VIA   "CentaurHauls"
716 
717 #define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
718 #define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
719 
720 /* CPUID[0xB].ECX level types */
721 #define CPUID_TOPOLOGY_LEVEL_INVALID  (0U << 8)
722 #define CPUID_TOPOLOGY_LEVEL_SMT      (1U << 8)
723 #define CPUID_TOPOLOGY_LEVEL_CORE     (2U << 8)
724 
725 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
726 #define HYPERV_SPINLOCK_NEVER_RETRY             0xFFFFFFFF
727 #endif
728 
729 #define EXCP00_DIVZ	0
730 #define EXCP01_DB	1
731 #define EXCP02_NMI	2
732 #define EXCP03_INT3	3
733 #define EXCP04_INTO	4
734 #define EXCP05_BOUND	5
735 #define EXCP06_ILLOP	6
736 #define EXCP07_PREX	7
737 #define EXCP08_DBLE	8
738 #define EXCP09_XERR	9
739 #define EXCP0A_TSS	10
740 #define EXCP0B_NOSEG	11
741 #define EXCP0C_STACK	12
742 #define EXCP0D_GPF	13
743 #define EXCP0E_PAGE	14
744 #define EXCP10_COPR	16
745 #define EXCP11_ALGN	17
746 #define EXCP12_MCHK	18
747 
748 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
749                                  for syscall instruction */
750 #define EXCP_VMEXIT     0x100
751 
752 /* i386-specific interrupt pending bits.  */
753 #define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
754 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
755 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
756 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
757 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
758 #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_1
759 #define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_2
760 
761 /* Use a clearer name for this.  */
762 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_RESET
763 
764 /* Instead of computing the condition codes after each x86 instruction,
765  * QEMU just stores one operand (called CC_SRC), the result
766  * (called CC_DST) and the type of operation (called CC_OP). When the
767  * condition codes are needed, the condition codes can be calculated
768  * using this information. Condition codes are not generated if they
769  * are only needed for conditional branches.
770  */
771 typedef enum {
772     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
773     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
774 
775     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
776     CC_OP_MULW,
777     CC_OP_MULL,
778     CC_OP_MULQ,
779 
780     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
781     CC_OP_ADDW,
782     CC_OP_ADDL,
783     CC_OP_ADDQ,
784 
785     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
786     CC_OP_ADCW,
787     CC_OP_ADCL,
788     CC_OP_ADCQ,
789 
790     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
791     CC_OP_SUBW,
792     CC_OP_SUBL,
793     CC_OP_SUBQ,
794 
795     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
796     CC_OP_SBBW,
797     CC_OP_SBBL,
798     CC_OP_SBBQ,
799 
800     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
801     CC_OP_LOGICW,
802     CC_OP_LOGICL,
803     CC_OP_LOGICQ,
804 
805     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
806     CC_OP_INCW,
807     CC_OP_INCL,
808     CC_OP_INCQ,
809 
810     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
811     CC_OP_DECW,
812     CC_OP_DECL,
813     CC_OP_DECQ,
814 
815     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
816     CC_OP_SHLW,
817     CC_OP_SHLL,
818     CC_OP_SHLQ,
819 
820     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
821     CC_OP_SARW,
822     CC_OP_SARL,
823     CC_OP_SARQ,
824 
825     CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
826     CC_OP_BMILGW,
827     CC_OP_BMILGL,
828     CC_OP_BMILGQ,
829 
830     CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest.  */
831     CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest.  */
832     CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */
833 
834     CC_OP_CLR, /* Z set, all other flags clear.  */
835     CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear.  */
836 
837     CC_OP_NB,
838 } CCOp;
839 
840 typedef struct SegmentCache {
841     uint32_t selector;
842     target_ulong base;
843     uint32_t limit;
844     uint32_t flags;
845 } SegmentCache;
846 
847 #define MMREG_UNION(n, bits)        \
848     union n {                       \
849         uint8_t  _b_##n[(bits)/8];  \
850         uint16_t _w_##n[(bits)/16]; \
851         uint32_t _l_##n[(bits)/32]; \
852         uint64_t _q_##n[(bits)/64]; \
853         float32  _s_##n[(bits)/32]; \
854         float64  _d_##n[(bits)/64]; \
855     }
856 
857 typedef union {
858     uint8_t _b[16];
859     uint16_t _w[8];
860     uint32_t _l[4];
861     uint64_t _q[2];
862 } XMMReg;
863 
864 typedef union {
865     uint8_t _b[32];
866     uint16_t _w[16];
867     uint32_t _l[8];
868     uint64_t _q[4];
869 } YMMReg;
870 
871 typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
872 typedef MMREG_UNION(MMXReg, 64)  MMXReg;
873 
874 typedef struct BNDReg {
875     uint64_t lb;
876     uint64_t ub;
877 } BNDReg;
878 
879 typedef struct BNDCSReg {
880     uint64_t cfgu;
881     uint64_t sts;
882 } BNDCSReg;
883 
884 #define BNDCFG_ENABLE       1ULL
885 #define BNDCFG_BNDPRESERVE  2ULL
886 #define BNDCFG_BDIR_MASK    TARGET_PAGE_MASK
887 
888 #ifdef HOST_WORDS_BIGENDIAN
889 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
890 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
891 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
892 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
893 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
894 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
895 
896 #define MMX_B(n) _b_MMXReg[7 - (n)]
897 #define MMX_W(n) _w_MMXReg[3 - (n)]
898 #define MMX_L(n) _l_MMXReg[1 - (n)]
899 #define MMX_S(n) _s_MMXReg[1 - (n)]
900 #else
901 #define ZMM_B(n) _b_ZMMReg[n]
902 #define ZMM_W(n) _w_ZMMReg[n]
903 #define ZMM_L(n) _l_ZMMReg[n]
904 #define ZMM_S(n) _s_ZMMReg[n]
905 #define ZMM_Q(n) _q_ZMMReg[n]
906 #define ZMM_D(n) _d_ZMMReg[n]
907 
908 #define MMX_B(n) _b_MMXReg[n]
909 #define MMX_W(n) _w_MMXReg[n]
910 #define MMX_L(n) _l_MMXReg[n]
911 #define MMX_S(n) _s_MMXReg[n]
912 #endif
913 #define MMX_Q(n) _q_MMXReg[n]
914 
915 typedef union {
916     floatx80 d __attribute__((aligned(16)));
917     MMXReg mmx;
918 } FPReg;
919 
920 typedef struct {
921     uint64_t base;
922     uint64_t mask;
923 } MTRRVar;
924 
925 #define CPU_NB_REGS64 16
926 #define CPU_NB_REGS32 8
927 
928 #ifdef TARGET_X86_64
929 #define CPU_NB_REGS CPU_NB_REGS64
930 #else
931 #define CPU_NB_REGS CPU_NB_REGS32
932 #endif
933 
934 #define MAX_FIXED_COUNTERS 3
935 #define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
936 
937 #define NB_MMU_MODES 3
938 #define TARGET_INSN_START_EXTRA_WORDS 1
939 
940 #define NB_OPMASK_REGS 8
941 
942 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
943  * that APIC ID hasn't been set yet
944  */
945 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
946 
947 typedef union X86LegacyXSaveArea {
948     struct {
949         uint16_t fcw;
950         uint16_t fsw;
951         uint8_t ftw;
952         uint8_t reserved;
953         uint16_t fpop;
954         uint64_t fpip;
955         uint64_t fpdp;
956         uint32_t mxcsr;
957         uint32_t mxcsr_mask;
958         FPReg fpregs[8];
959         uint8_t xmm_regs[16][16];
960     };
961     uint8_t data[512];
962 } X86LegacyXSaveArea;
963 
964 typedef struct X86XSaveHeader {
965     uint64_t xstate_bv;
966     uint64_t xcomp_bv;
967     uint64_t reserve0;
968     uint8_t reserved[40];
969 } X86XSaveHeader;
970 
971 /* Ext. save area 2: AVX State */
972 typedef struct XSaveAVX {
973     uint8_t ymmh[16][16];
974 } XSaveAVX;
975 
976 /* Ext. save area 3: BNDREG */
977 typedef struct XSaveBNDREG {
978     BNDReg bnd_regs[4];
979 } XSaveBNDREG;
980 
981 /* Ext. save area 4: BNDCSR */
982 typedef union XSaveBNDCSR {
983     BNDCSReg bndcsr;
984     uint8_t data[64];
985 } XSaveBNDCSR;
986 
987 /* Ext. save area 5: Opmask */
988 typedef struct XSaveOpmask {
989     uint64_t opmask_regs[NB_OPMASK_REGS];
990 } XSaveOpmask;
991 
992 /* Ext. save area 6: ZMM_Hi256 */
993 typedef struct XSaveZMM_Hi256 {
994     uint8_t zmm_hi256[16][32];
995 } XSaveZMM_Hi256;
996 
997 /* Ext. save area 7: Hi16_ZMM */
998 typedef struct XSaveHi16_ZMM {
999     uint8_t hi16_zmm[16][64];
1000 } XSaveHi16_ZMM;
1001 
1002 /* Ext. save area 9: PKRU state */
1003 typedef struct XSavePKRU {
1004     uint32_t pkru;
1005     uint32_t padding;
1006 } XSavePKRU;
1007 
1008 typedef struct X86XSaveArea {
1009     X86LegacyXSaveArea legacy;
1010     X86XSaveHeader header;
1011 
1012     /* Extended save areas: */
1013 
1014     /* AVX State: */
1015     XSaveAVX avx_state;
1016     uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1017     /* MPX State: */
1018     XSaveBNDREG bndreg_state;
1019     XSaveBNDCSR bndcsr_state;
1020     /* AVX-512 State: */
1021     XSaveOpmask opmask_state;
1022     XSaveZMM_Hi256 zmm_hi256_state;
1023     XSaveHi16_ZMM hi16_zmm_state;
1024     /* PKRU State: */
1025     XSavePKRU pkru_state;
1026 } X86XSaveArea;
1027 
1028 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1029 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1030 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1031 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1032 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1033 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1034 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1035 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1036 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1037 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1038 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1039 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1040 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1041 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1042 
1043 typedef enum TPRAccess {
1044     TPR_ACCESS_READ,
1045     TPR_ACCESS_WRITE,
1046 } TPRAccess;
1047 
1048 /* Cache information data structures: */
1049 
1050 enum CacheType {
1051     DCACHE,
1052     ICACHE,
1053     UNIFIED_CACHE
1054 };
1055 
1056 typedef struct CPUCacheInfo {
1057     enum CacheType type;
1058     uint8_t level;
1059     /* Size in bytes */
1060     uint32_t size;
1061     /* Line size, in bytes */
1062     uint16_t line_size;
1063     /*
1064      * Associativity.
1065      * Note: representation of fully-associative caches is not implemented
1066      */
1067     uint8_t associativity;
1068     /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1069     uint8_t partitions;
1070     /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1071     uint32_t sets;
1072     /*
1073      * Lines per tag.
1074      * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1075      * (Is this synonym to @partitions?)
1076      */
1077     uint8_t lines_per_tag;
1078 
1079     /* Self-initializing cache */
1080     bool self_init;
1081     /*
1082      * WBINVD/INVD is not guaranteed to act upon lower level caches of
1083      * non-originating threads sharing this cache.
1084      * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1085      */
1086     bool no_invd_sharing;
1087     /*
1088      * Cache is inclusive of lower cache levels.
1089      * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1090      */
1091     bool inclusive;
1092     /*
1093      * A complex function is used to index the cache, potentially using all
1094      * address bits.  CPUID[4].EDX[bit 2].
1095      */
1096     bool complex_indexing;
1097 } CPUCacheInfo;
1098 
1099 
1100 typedef struct CPUCaches {
1101         CPUCacheInfo *l1d_cache;
1102         CPUCacheInfo *l1i_cache;
1103         CPUCacheInfo *l2_cache;
1104         CPUCacheInfo *l3_cache;
1105 } CPUCaches;
1106 
1107 typedef struct CPUX86State {
1108     /* standard registers */
1109     target_ulong regs[CPU_NB_REGS];
1110     target_ulong eip;
1111     target_ulong eflags; /* eflags register. During CPU emulation, CC
1112                         flags and DF are set to zero because they are
1113                         stored elsewhere */
1114 
1115     /* emulator internal eflags handling */
1116     target_ulong cc_dst;
1117     target_ulong cc_src;
1118     target_ulong cc_src2;
1119     uint32_t cc_op;
1120     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1121     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1122                         are known at translation time. */
1123     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1124 
1125     /* segments */
1126     SegmentCache segs[6]; /* selector values */
1127     SegmentCache ldt;
1128     SegmentCache tr;
1129     SegmentCache gdt; /* only base and limit are used */
1130     SegmentCache idt; /* only base and limit are used */
1131 
1132     target_ulong cr[5]; /* NOTE: cr1 is unused */
1133     int32_t a20_mask;
1134 
1135     BNDReg bnd_regs[4];
1136     BNDCSReg bndcs_regs;
1137     uint64_t msr_bndcfgs;
1138     uint64_t efer;
1139 
1140     /* Beginning of state preserved by INIT (dummy marker).  */
1141     struct {} start_init_save;
1142 
1143     /* FPU state */
1144     unsigned int fpstt; /* top of stack index */
1145     uint16_t fpus;
1146     uint16_t fpuc;
1147     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
1148     FPReg fpregs[8];
1149     /* KVM-only so far */
1150     uint16_t fpop;
1151     uint64_t fpip;
1152     uint64_t fpdp;
1153 
1154     /* emulator internal variables */
1155     float_status fp_status;
1156     floatx80 ft0;
1157 
1158     float_status mmx_status; /* for 3DNow! float ops */
1159     float_status sse_status;
1160     uint32_t mxcsr;
1161     ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1162     ZMMReg xmm_t0;
1163     MMXReg mmx_t0;
1164 
1165     XMMReg ymmh_regs[CPU_NB_REGS];
1166 
1167     uint64_t opmask_regs[NB_OPMASK_REGS];
1168     YMMReg zmmh_regs[CPU_NB_REGS];
1169     ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1170 
1171     /* sysenter registers */
1172     uint32_t sysenter_cs;
1173     target_ulong sysenter_esp;
1174     target_ulong sysenter_eip;
1175     uint64_t star;
1176 
1177     uint64_t vm_hsave;
1178 
1179 #ifdef TARGET_X86_64
1180     target_ulong lstar;
1181     target_ulong cstar;
1182     target_ulong fmask;
1183     target_ulong kernelgsbase;
1184 #endif
1185 
1186     uint64_t tsc;
1187     uint64_t tsc_adjust;
1188     uint64_t tsc_deadline;
1189     uint64_t tsc_aux;
1190 
1191     uint64_t xcr0;
1192 
1193     uint64_t mcg_status;
1194     uint64_t msr_ia32_misc_enable;
1195     uint64_t msr_ia32_feature_control;
1196 
1197     uint64_t msr_fixed_ctr_ctrl;
1198     uint64_t msr_global_ctrl;
1199     uint64_t msr_global_status;
1200     uint64_t msr_global_ovf_ctrl;
1201     uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1202     uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1203     uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1204 
1205     uint64_t pat;
1206     uint32_t smbase;
1207     uint64_t msr_smi_count;
1208 
1209     uint32_t pkru;
1210 
1211     uint64_t spec_ctrl;
1212     uint64_t virt_ssbd;
1213 
1214     /* End of state preserved by INIT (dummy marker).  */
1215     struct {} end_init_save;
1216 
1217     uint64_t system_time_msr;
1218     uint64_t wall_clock_msr;
1219     uint64_t steal_time_msr;
1220     uint64_t async_pf_en_msr;
1221     uint64_t pv_eoi_en_msr;
1222 
1223     /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1224     uint64_t msr_hv_hypercall;
1225     uint64_t msr_hv_guest_os_id;
1226     uint64_t msr_hv_tsc;
1227 
1228     /* Per-VCPU HV MSRs */
1229     uint64_t msr_hv_vapic;
1230     uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1231     uint64_t msr_hv_runtime;
1232     uint64_t msr_hv_synic_control;
1233     uint64_t msr_hv_synic_evt_page;
1234     uint64_t msr_hv_synic_msg_page;
1235     uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1236     uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1237     uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1238     uint64_t msr_hv_reenlightenment_control;
1239     uint64_t msr_hv_tsc_emulation_control;
1240     uint64_t msr_hv_tsc_emulation_status;
1241 
1242     uint64_t msr_rtit_ctrl;
1243     uint64_t msr_rtit_status;
1244     uint64_t msr_rtit_output_base;
1245     uint64_t msr_rtit_output_mask;
1246     uint64_t msr_rtit_cr3_match;
1247     uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1248 
1249     /* exception/interrupt handling */
1250     int error_code;
1251     int exception_is_int;
1252     target_ulong exception_next_eip;
1253     target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1254     union {
1255         struct CPUBreakpoint *cpu_breakpoint[4];
1256         struct CPUWatchpoint *cpu_watchpoint[4];
1257     }; /* break/watchpoints for dr[0..3] */
1258     int old_exception;  /* exception in flight */
1259 
1260     uint64_t vm_vmcb;
1261     uint64_t tsc_offset;
1262     uint64_t intercept;
1263     uint16_t intercept_cr_read;
1264     uint16_t intercept_cr_write;
1265     uint16_t intercept_dr_read;
1266     uint16_t intercept_dr_write;
1267     uint32_t intercept_exceptions;
1268     uint8_t v_tpr;
1269 
1270     /* KVM states, automatically cleared on reset */
1271     uint8_t nmi_injected;
1272     uint8_t nmi_pending;
1273 
1274     /* Fields up to this point are cleared by a CPU reset */
1275     struct {} end_reset_fields;
1276 
1277     CPU_COMMON
1278 
1279     /* Fields after CPU_COMMON are preserved across CPU reset. */
1280 
1281     /* processor features (e.g. for CPUID insn) */
1282     /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1283     uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1284     /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1285     uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1286     /* Actual level/xlevel/xlevel2 value: */
1287     uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1288     uint32_t cpuid_vendor1;
1289     uint32_t cpuid_vendor2;
1290     uint32_t cpuid_vendor3;
1291     uint32_t cpuid_version;
1292     FeatureWordArray features;
1293     /* Features that were explicitly enabled/disabled */
1294     FeatureWordArray user_features;
1295     uint32_t cpuid_model[12];
1296     /* Cache information for CPUID.  When legacy-cache=on, the cache data
1297      * on each CPUID leaf will be different, because we keep compatibility
1298      * with old QEMU versions.
1299      */
1300     CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1301 
1302     /* MTRRs */
1303     uint64_t mtrr_fixed[11];
1304     uint64_t mtrr_deftype;
1305     MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1306 
1307     /* For KVM */
1308     uint32_t mp_state;
1309     int32_t exception_injected;
1310     int32_t interrupt_injected;
1311     uint8_t soft_interrupt;
1312     uint8_t has_error_code;
1313     uint32_t ins_len;
1314     uint32_t sipi_vector;
1315     bool tsc_valid;
1316     int64_t tsc_khz;
1317     int64_t user_tsc_khz; /* for sanity check only */
1318     void *kvm_xsave_buf;
1319 #if defined(CONFIG_HVF)
1320     HVFX86EmulatorState *hvf_emul;
1321 #endif
1322 
1323     uint64_t mcg_cap;
1324     uint64_t mcg_ctl;
1325     uint64_t mcg_ext_ctl;
1326     uint64_t mce_banks[MCE_BANKS_DEF*4];
1327     uint64_t xstate_bv;
1328 
1329     /* vmstate */
1330     uint16_t fpus_vmstate;
1331     uint16_t fptag_vmstate;
1332     uint16_t fpregs_format_vmstate;
1333 
1334     uint64_t xss;
1335 
1336     TPRAccess tpr_access_type;
1337 } CPUX86State;
1338 
1339 struct kvm_msrs;
1340 
1341 /**
1342  * X86CPU:
1343  * @env: #CPUX86State
1344  * @migratable: If set, only migratable flags will be accepted when "enforce"
1345  * mode is used, and only migratable flags will be included in the "host"
1346  * CPU model.
1347  *
1348  * An x86 CPU.
1349  */
1350 struct X86CPU {
1351     /*< private >*/
1352     CPUState parent_obj;
1353     /*< public >*/
1354 
1355     CPUX86State env;
1356 
1357     bool hyperv_vapic;
1358     bool hyperv_relaxed_timing;
1359     int hyperv_spinlock_attempts;
1360     char *hyperv_vendor_id;
1361     bool hyperv_time;
1362     bool hyperv_crash;
1363     bool hyperv_reset;
1364     bool hyperv_vpindex;
1365     bool hyperv_runtime;
1366     bool hyperv_synic;
1367     bool hyperv_stimer;
1368     bool hyperv_frequencies;
1369     bool hyperv_reenlightenment;
1370     bool hyperv_tlbflush;
1371     bool check_cpuid;
1372     bool enforce_cpuid;
1373     bool expose_kvm;
1374     bool expose_tcg;
1375     bool migratable;
1376     bool max_features; /* Enable all supported features automatically */
1377     uint32_t apic_id;
1378 
1379     /* Enables publishing of TSC increment and Local APIC bus frequencies to
1380      * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1381     bool vmware_cpuid_freq;
1382 
1383     /* if true the CPUID code directly forward host cache leaves to the guest */
1384     bool cache_info_passthrough;
1385 
1386     /* if true the CPUID code directly forwards
1387      * host monitor/mwait leaves to the guest */
1388     struct {
1389         uint32_t eax;
1390         uint32_t ebx;
1391         uint32_t ecx;
1392         uint32_t edx;
1393     } mwait;
1394 
1395     /* Features that were filtered out because of missing host capabilities */
1396     uint32_t filtered_features[FEATURE_WORDS];
1397 
1398     /* Enable PMU CPUID bits. This can't be enabled by default yet because
1399      * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1400      * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1401      * capabilities) directly to the guest.
1402      */
1403     bool enable_pmu;
1404 
1405     /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1406      * disabled by default to avoid breaking migration between QEMU with
1407      * different LMCE configurations.
1408      */
1409     bool enable_lmce;
1410 
1411     /* Compatibility bits for old machine types.
1412      * If true present virtual l3 cache for VM, the vcpus in the same virtual
1413      * socket share an virtual l3 cache.
1414      */
1415     bool enable_l3_cache;
1416 
1417     /* Compatibility bits for old machine types.
1418      * If true present the old cache topology information
1419      */
1420     bool legacy_cache;
1421 
1422     /* Compatibility bits for old machine types: */
1423     bool enable_cpuid_0xb;
1424 
1425     /* Enable auto level-increase for all CPUID leaves */
1426     bool full_cpuid_auto_level;
1427 
1428     /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
1429     bool fill_mtrr_mask;
1430 
1431     /* if true override the phys_bits value with a value read from the host */
1432     bool host_phys_bits;
1433 
1434     /* Stop SMI delivery for migration compatibility with old machines */
1435     bool kvm_no_smi_migration;
1436 
1437     /* Number of physical address bits supported */
1438     uint32_t phys_bits;
1439 
1440     /* in order to simplify APIC support, we leave this pointer to the
1441        user */
1442     struct DeviceState *apic_state;
1443     struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1444     Notifier machine_done;
1445 
1446     struct kvm_msrs *kvm_msr_buf;
1447 
1448     int32_t node_id; /* NUMA node this CPU belongs to */
1449     int32_t socket_id;
1450     int32_t core_id;
1451     int32_t thread_id;
1452 
1453     int32_t hv_max_vps;
1454 };
1455 
1456 static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
1457 {
1458     return container_of(env, X86CPU, env);
1459 }
1460 
1461 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1462 
1463 #define ENV_OFFSET offsetof(X86CPU, env)
1464 
1465 #ifndef CONFIG_USER_ONLY
1466 extern struct VMStateDescription vmstate_x86_cpu;
1467 #endif
1468 
1469 /**
1470  * x86_cpu_do_interrupt:
1471  * @cpu: vCPU the interrupt is to be handled by.
1472  */
1473 void x86_cpu_do_interrupt(CPUState *cpu);
1474 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1475 
1476 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1477                              int cpuid, void *opaque);
1478 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1479                              int cpuid, void *opaque);
1480 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1481                                  void *opaque);
1482 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1483                                  void *opaque);
1484 
1485 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1486                                 Error **errp);
1487 
1488 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1489                         int flags);
1490 
1491 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1492 
1493 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1494 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1495 
1496 void x86_cpu_exec_enter(CPUState *cpu);
1497 void x86_cpu_exec_exit(CPUState *cpu);
1498 
1499 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1500 int cpu_x86_support_mca_broadcast(CPUX86State *env);
1501 
1502 int cpu_get_pic_interrupt(CPUX86State *s);
1503 /* MSDOS compatibility mode FPU exception support */
1504 void cpu_set_ferr(CPUX86State *s);
1505 
1506 /* this function must always be used to load data in the segment
1507    cache: it synchronizes the hflags with the segment cache values */
1508 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1509                                           int seg_reg, unsigned int selector,
1510                                           target_ulong base,
1511                                           unsigned int limit,
1512                                           unsigned int flags)
1513 {
1514     SegmentCache *sc;
1515     unsigned int new_hflags;
1516 
1517     sc = &env->segs[seg_reg];
1518     sc->selector = selector;
1519     sc->base = base;
1520     sc->limit = limit;
1521     sc->flags = flags;
1522 
1523     /* update the hidden flags */
1524     {
1525         if (seg_reg == R_CS) {
1526 #ifdef TARGET_X86_64
1527             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1528                 /* long mode */
1529                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1530                 env->hflags &= ~(HF_ADDSEG_MASK);
1531             } else
1532 #endif
1533             {
1534                 /* legacy / compatibility case */
1535                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1536                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1537                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1538                     new_hflags;
1539             }
1540         }
1541         if (seg_reg == R_SS) {
1542             int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1543 #if HF_CPL_MASK != 3
1544 #error HF_CPL_MASK is hardcoded
1545 #endif
1546             env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1547         }
1548         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1549             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1550         if (env->hflags & HF_CS64_MASK) {
1551             /* zero base assumed for DS, ES and SS in long mode */
1552         } else if (!(env->cr[0] & CR0_PE_MASK) ||
1553                    (env->eflags & VM_MASK) ||
1554                    !(env->hflags & HF_CS32_MASK)) {
1555             /* XXX: try to avoid this test. The problem comes from the
1556                fact that is real mode or vm86 mode we only modify the
1557                'base' and 'selector' fields of the segment cache to go
1558                faster. A solution may be to force addseg to one in
1559                translate-i386.c. */
1560             new_hflags |= HF_ADDSEG_MASK;
1561         } else {
1562             new_hflags |= ((env->segs[R_DS].base |
1563                             env->segs[R_ES].base |
1564                             env->segs[R_SS].base) != 0) <<
1565                 HF_ADDSEG_SHIFT;
1566         }
1567         env->hflags = (env->hflags &
1568                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1569     }
1570 }
1571 
1572 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1573                                                uint8_t sipi_vector)
1574 {
1575     CPUState *cs = CPU(cpu);
1576     CPUX86State *env = &cpu->env;
1577 
1578     env->eip = 0;
1579     cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1580                            sipi_vector << 12,
1581                            env->segs[R_CS].limit,
1582                            env->segs[R_CS].flags);
1583     cs->halted = 0;
1584 }
1585 
1586 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1587                             target_ulong *base, unsigned int *limit,
1588                             unsigned int *flags);
1589 
1590 /* op_helper.c */
1591 /* used for debug or cpu save/restore */
1592 
1593 /* cpu-exec.c */
1594 /* the following helpers are only usable in user mode simulation as
1595    they can trigger unexpected exceptions */
1596 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1597 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1598 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1599 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1600 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1601 
1602 /* you can call this signal handler from your SIGBUS and SIGSEGV
1603    signal handlers to inform the virtual CPU of exceptions. non zero
1604    is returned if the signal was handled by the virtual CPU.  */
1605 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1606                            void *puc);
1607 
1608 /* cpu.c */
1609 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1610                    uint32_t *eax, uint32_t *ebx,
1611                    uint32_t *ecx, uint32_t *edx);
1612 void cpu_clear_apic_feature(CPUX86State *env);
1613 void host_cpuid(uint32_t function, uint32_t count,
1614                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1615 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1616 
1617 /* helper.c */
1618 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size,
1619                              int is_write, int mmu_idx);
1620 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1621 
1622 #ifndef CONFIG_USER_ONLY
1623 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1624 {
1625     return !!attrs.secure;
1626 }
1627 
1628 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1629 {
1630     return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1631 }
1632 
1633 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1634 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1635 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1636 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1637 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1638 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1639 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1640 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1641 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1642 #endif
1643 
1644 void breakpoint_handler(CPUState *cs);
1645 
1646 /* will be suppressed */
1647 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1648 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1649 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1650 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1651 
1652 /* hw/pc.c */
1653 uint64_t cpu_get_tsc(CPUX86State *env);
1654 
1655 #define TARGET_PAGE_BITS 12
1656 
1657 #ifdef TARGET_X86_64
1658 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1659 /* ??? This is really 48 bits, sign-extended, but the only thing
1660    accessible to userland with bit 48 set is the VSYSCALL, and that
1661    is handled via other mechanisms.  */
1662 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1663 #else
1664 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1665 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1666 #endif
1667 
1668 /* XXX: This value should match the one returned by CPUID
1669  * and in exec.c */
1670 # if defined(TARGET_X86_64)
1671 # define TCG_PHYS_ADDR_BITS 40
1672 # else
1673 # define TCG_PHYS_ADDR_BITS 36
1674 # endif
1675 
1676 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1677 
1678 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1679 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1680 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
1681 
1682 #ifdef TARGET_X86_64
1683 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1684 #else
1685 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1686 #endif
1687 
1688 #define cpu_signal_handler cpu_x86_signal_handler
1689 #define cpu_list x86_cpu_list
1690 
1691 /* MMU modes definitions */
1692 #define MMU_MODE0_SUFFIX _ksmap
1693 #define MMU_MODE1_SUFFIX _user
1694 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
1695 #define MMU_KSMAP_IDX   0
1696 #define MMU_USER_IDX    1
1697 #define MMU_KNOSMAP_IDX 2
1698 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1699 {
1700     return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1701         (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1702         ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1703 }
1704 
1705 static inline int cpu_mmu_index_kernel(CPUX86State *env)
1706 {
1707     return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1708         ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1709         ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1710 }
1711 
1712 #define CC_DST  (env->cc_dst)
1713 #define CC_SRC  (env->cc_src)
1714 #define CC_SRC2 (env->cc_src2)
1715 #define CC_OP   (env->cc_op)
1716 
1717 /* n must be a constant to be efficient */
1718 static inline target_long lshift(target_long x, int n)
1719 {
1720     if (n >= 0) {
1721         return x << n;
1722     } else {
1723         return x >> (-n);
1724     }
1725 }
1726 
1727 /* float macros */
1728 #define FT0    (env->ft0)
1729 #define ST0    (env->fpregs[env->fpstt].d)
1730 #define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
1731 #define ST1    ST(1)
1732 
1733 /* translate.c */
1734 void tcg_x86_init(void);
1735 
1736 #include "exec/cpu-all.h"
1737 #include "svm.h"
1738 
1739 #if !defined(CONFIG_USER_ONLY)
1740 #include "hw/i386/apic.h"
1741 #endif
1742 
1743 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1744                                         target_ulong *cs_base, uint32_t *flags)
1745 {
1746     *cs_base = env->segs[R_CS].base;
1747     *pc = *cs_base + env->eip;
1748     *flags = env->hflags |
1749         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1750 }
1751 
1752 void do_cpu_init(X86CPU *cpu);
1753 void do_cpu_sipi(X86CPU *cpu);
1754 
1755 #define MCE_INJECT_BROADCAST    1
1756 #define MCE_INJECT_UNCOND_AO    2
1757 
1758 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1759                         uint64_t status, uint64_t mcg_status, uint64_t addr,
1760                         uint64_t misc, int flags);
1761 
1762 /* excp_helper.c */
1763 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1764 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1765                                       uintptr_t retaddr);
1766 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1767                                        int error_code);
1768 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1769                                           int error_code, uintptr_t retaddr);
1770 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1771                                    int error_code, int next_eip_addend);
1772 
1773 /* cc_helper.c */
1774 extern const uint8_t parity_table[256];
1775 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1776 
1777 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1778 {
1779     uint32_t eflags = env->eflags;
1780     if (tcg_enabled()) {
1781         eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1782     }
1783     return eflags;
1784 }
1785 
1786 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
1787  * after generating a call to a helper that uses this.
1788  */
1789 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1790                                    int update_mask)
1791 {
1792     CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1793     CC_OP = CC_OP_EFLAGS;
1794     env->df = 1 - (2 * ((eflags >> 10) & 1));
1795     env->eflags = (env->eflags & ~update_mask) |
1796         (eflags & update_mask) | 0x2;
1797 }
1798 
1799 /* load efer and update the corresponding hflags. XXX: do consistency
1800    checks with cpuid bits? */
1801 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1802 {
1803     env->efer = val;
1804     env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1805     if (env->efer & MSR_EFER_LMA) {
1806         env->hflags |= HF_LMA_MASK;
1807     }
1808     if (env->efer & MSR_EFER_SVME) {
1809         env->hflags |= HF_SVME_MASK;
1810     }
1811 }
1812 
1813 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1814 {
1815     return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1816 }
1817 
1818 static inline int32_t x86_get_a20_mask(CPUX86State *env)
1819 {
1820     if (env->hflags & HF_SMM_MASK) {
1821         return -1;
1822     } else {
1823         return env->a20_mask;
1824     }
1825 }
1826 
1827 /* fpu_helper.c */
1828 void update_fp_status(CPUX86State *env);
1829 void update_mxcsr_status(CPUX86State *env);
1830 
1831 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1832 {
1833     env->mxcsr = mxcsr;
1834     if (tcg_enabled()) {
1835         update_mxcsr_status(env);
1836     }
1837 }
1838 
1839 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
1840 {
1841      env->fpuc = fpuc;
1842      if (tcg_enabled()) {
1843         update_fp_status(env);
1844      }
1845 }
1846 
1847 /* mem_helper.c */
1848 void helper_lock_init(void);
1849 
1850 /* svm_helper.c */
1851 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1852                                    uint64_t param, uintptr_t retaddr);
1853 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
1854                               uint64_t exit_info_1, uintptr_t retaddr);
1855 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
1856 
1857 /* seg_helper.c */
1858 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1859 
1860 /* smm_helper.c */
1861 void do_smm_enter(X86CPU *cpu);
1862 
1863 /* apic.c */
1864 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1865 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1866                                    TPRAccess access);
1867 
1868 
1869 /* Change the value of a KVM-specific default
1870  *
1871  * If value is NULL, no default will be set and the original
1872  * value from the CPU model table will be kept.
1873  *
1874  * It is valid to call this function only for properties that
1875  * are already present in the kvm_default_props table.
1876  */
1877 void x86_cpu_change_kvm_default(const char *prop, const char *value);
1878 
1879 /* mpx_helper.c */
1880 void cpu_sync_bndcs_hflags(CPUX86State *env);
1881 
1882 /* Return name of 32-bit register, from a R_* constant */
1883 const char *get_register_name_32(unsigned int reg);
1884 
1885 void enable_compat_apic_id_mode(void);
1886 
1887 #define APIC_DEFAULT_ADDRESS 0xfee00000
1888 #define APIC_SPACE_SIZE      0x100000
1889 
1890 void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1891                                    fprintf_function cpu_fprintf, int flags);
1892 
1893 /* cpu.c */
1894 bool cpu_is_bsp(X86CPU *cpu);
1895 
1896 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
1897 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
1898 void x86_update_hflags(CPUX86State* env);
1899 
1900 #endif /* I386_CPU_H */
1901