1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 #define KVM_HAVE_MCE_INJECTION 1 33 34 /* Maximum instruction code size */ 35 #define TARGET_MAX_INSN_SIZE 16 36 37 /* support for self modifying code even if the modified instruction is 38 close to the modifying instruction */ 39 #define TARGET_HAS_PRECISE_SMC 40 41 #ifdef TARGET_X86_64 42 #define I386_ELF_MACHINE EM_X86_64 43 #define ELF_MACHINE_UNAME "x86_64" 44 #else 45 #define I386_ELF_MACHINE EM_386 46 #define ELF_MACHINE_UNAME "i686" 47 #endif 48 49 enum { 50 R_EAX = 0, 51 R_ECX = 1, 52 R_EDX = 2, 53 R_EBX = 3, 54 R_ESP = 4, 55 R_EBP = 5, 56 R_ESI = 6, 57 R_EDI = 7, 58 R_R8 = 8, 59 R_R9 = 9, 60 R_R10 = 10, 61 R_R11 = 11, 62 R_R12 = 12, 63 R_R13 = 13, 64 R_R14 = 14, 65 R_R15 = 15, 66 67 R_AL = 0, 68 R_CL = 1, 69 R_DL = 2, 70 R_BL = 3, 71 R_AH = 4, 72 R_CH = 5, 73 R_DH = 6, 74 R_BH = 7, 75 }; 76 77 typedef enum X86Seg { 78 R_ES = 0, 79 R_CS = 1, 80 R_SS = 2, 81 R_DS = 3, 82 R_FS = 4, 83 R_GS = 5, 84 R_LDTR = 6, 85 R_TR = 7, 86 } X86Seg; 87 88 /* segment descriptor fields */ 89 #define DESC_G_SHIFT 23 90 #define DESC_G_MASK (1 << DESC_G_SHIFT) 91 #define DESC_B_SHIFT 22 92 #define DESC_B_MASK (1 << DESC_B_SHIFT) 93 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 94 #define DESC_L_MASK (1 << DESC_L_SHIFT) 95 #define DESC_AVL_SHIFT 20 96 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 97 #define DESC_P_SHIFT 15 98 #define DESC_P_MASK (1 << DESC_P_SHIFT) 99 #define DESC_DPL_SHIFT 13 100 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 101 #define DESC_S_SHIFT 12 102 #define DESC_S_MASK (1 << DESC_S_SHIFT) 103 #define DESC_TYPE_SHIFT 8 104 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 105 #define DESC_A_MASK (1 << 8) 106 107 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 108 #define DESC_C_MASK (1 << 10) /* code: conforming */ 109 #define DESC_R_MASK (1 << 9) /* code: readable */ 110 111 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 112 #define DESC_W_MASK (1 << 9) /* data: writable */ 113 114 #define DESC_TSS_BUSY_MASK (1 << 9) 115 116 /* eflags masks */ 117 #define CC_C 0x0001 118 #define CC_P 0x0004 119 #define CC_A 0x0010 120 #define CC_Z 0x0040 121 #define CC_S 0x0080 122 #define CC_O 0x0800 123 124 #define TF_SHIFT 8 125 #define IOPL_SHIFT 12 126 #define VM_SHIFT 17 127 128 #define TF_MASK 0x00000100 129 #define IF_MASK 0x00000200 130 #define DF_MASK 0x00000400 131 #define IOPL_MASK 0x00003000 132 #define NT_MASK 0x00004000 133 #define RF_MASK 0x00010000 134 #define VM_MASK 0x00020000 135 #define AC_MASK 0x00040000 136 #define VIF_MASK 0x00080000 137 #define VIP_MASK 0x00100000 138 #define ID_MASK 0x00200000 139 140 /* hidden flags - used internally by qemu to represent additional cpu 141 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 142 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 143 positions to ease oring with eflags. */ 144 /* current cpl */ 145 #define HF_CPL_SHIFT 0 146 /* true if hardware interrupts must be disabled for next instruction */ 147 #define HF_INHIBIT_IRQ_SHIFT 3 148 /* 16 or 32 segments */ 149 #define HF_CS32_SHIFT 4 150 #define HF_SS32_SHIFT 5 151 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 152 #define HF_ADDSEG_SHIFT 6 153 /* copy of CR0.PE (protected mode) */ 154 #define HF_PE_SHIFT 7 155 #define HF_TF_SHIFT 8 /* must be same as eflags */ 156 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 157 #define HF_EM_SHIFT 10 158 #define HF_TS_SHIFT 11 159 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 160 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 161 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 162 #define HF_RF_SHIFT 16 /* must be same as eflags */ 163 #define HF_VM_SHIFT 17 /* must be same as eflags */ 164 #define HF_AC_SHIFT 18 /* must be same as eflags */ 165 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 166 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 167 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 168 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 169 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 170 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 171 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 172 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 173 174 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 175 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 176 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 177 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 178 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 179 #define HF_PE_MASK (1 << HF_PE_SHIFT) 180 #define HF_TF_MASK (1 << HF_TF_SHIFT) 181 #define HF_MP_MASK (1 << HF_MP_SHIFT) 182 #define HF_EM_MASK (1 << HF_EM_SHIFT) 183 #define HF_TS_MASK (1 << HF_TS_SHIFT) 184 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 185 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 186 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 187 #define HF_RF_MASK (1 << HF_RF_SHIFT) 188 #define HF_VM_MASK (1 << HF_VM_SHIFT) 189 #define HF_AC_MASK (1 << HF_AC_SHIFT) 190 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 191 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 192 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 193 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 194 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 195 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 196 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 197 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 198 199 /* hflags2 */ 200 201 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 202 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 203 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 204 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 205 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 206 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 207 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 208 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 209 210 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 211 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 212 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 213 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 214 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 215 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 216 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 217 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 218 219 #define CR0_PE_SHIFT 0 220 #define CR0_MP_SHIFT 1 221 222 #define CR0_PE_MASK (1U << 0) 223 #define CR0_MP_MASK (1U << 1) 224 #define CR0_EM_MASK (1U << 2) 225 #define CR0_TS_MASK (1U << 3) 226 #define CR0_ET_MASK (1U << 4) 227 #define CR0_NE_MASK (1U << 5) 228 #define CR0_WP_MASK (1U << 16) 229 #define CR0_AM_MASK (1U << 18) 230 #define CR0_PG_MASK (1U << 31) 231 232 #define CR4_VME_MASK (1U << 0) 233 #define CR4_PVI_MASK (1U << 1) 234 #define CR4_TSD_MASK (1U << 2) 235 #define CR4_DE_MASK (1U << 3) 236 #define CR4_PSE_MASK (1U << 4) 237 #define CR4_PAE_MASK (1U << 5) 238 #define CR4_MCE_MASK (1U << 6) 239 #define CR4_PGE_MASK (1U << 7) 240 #define CR4_PCE_MASK (1U << 8) 241 #define CR4_OSFXSR_SHIFT 9 242 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 243 #define CR4_OSXMMEXCPT_MASK (1U << 10) 244 #define CR4_LA57_MASK (1U << 12) 245 #define CR4_VMXE_MASK (1U << 13) 246 #define CR4_SMXE_MASK (1U << 14) 247 #define CR4_FSGSBASE_MASK (1U << 16) 248 #define CR4_PCIDE_MASK (1U << 17) 249 #define CR4_OSXSAVE_MASK (1U << 18) 250 #define CR4_SMEP_MASK (1U << 20) 251 #define CR4_SMAP_MASK (1U << 21) 252 #define CR4_PKE_MASK (1U << 22) 253 254 #define DR6_BD (1 << 13) 255 #define DR6_BS (1 << 14) 256 #define DR6_BT (1 << 15) 257 #define DR6_FIXED_1 0xffff0ff0 258 259 #define DR7_GD (1 << 13) 260 #define DR7_TYPE_SHIFT 16 261 #define DR7_LEN_SHIFT 18 262 #define DR7_FIXED_1 0x00000400 263 #define DR7_GLOBAL_BP_MASK 0xaa 264 #define DR7_LOCAL_BP_MASK 0x55 265 #define DR7_MAX_BP 4 266 #define DR7_TYPE_BP_INST 0x0 267 #define DR7_TYPE_DATA_WR 0x1 268 #define DR7_TYPE_IO_RW 0x2 269 #define DR7_TYPE_DATA_RW 0x3 270 271 #define PG_PRESENT_BIT 0 272 #define PG_RW_BIT 1 273 #define PG_USER_BIT 2 274 #define PG_PWT_BIT 3 275 #define PG_PCD_BIT 4 276 #define PG_ACCESSED_BIT 5 277 #define PG_DIRTY_BIT 6 278 #define PG_PSE_BIT 7 279 #define PG_GLOBAL_BIT 8 280 #define PG_PSE_PAT_BIT 12 281 #define PG_PKRU_BIT 59 282 #define PG_NX_BIT 63 283 284 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 285 #define PG_RW_MASK (1 << PG_RW_BIT) 286 #define PG_USER_MASK (1 << PG_USER_BIT) 287 #define PG_PWT_MASK (1 << PG_PWT_BIT) 288 #define PG_PCD_MASK (1 << PG_PCD_BIT) 289 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 290 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 291 #define PG_PSE_MASK (1 << PG_PSE_BIT) 292 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 293 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 294 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 295 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 296 #define PG_HI_USER_MASK 0x7ff0000000000000LL 297 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 298 #define PG_NX_MASK (1ULL << PG_NX_BIT) 299 300 #define PG_ERROR_W_BIT 1 301 302 #define PG_ERROR_P_MASK 0x01 303 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 304 #define PG_ERROR_U_MASK 0x04 305 #define PG_ERROR_RSVD_MASK 0x08 306 #define PG_ERROR_I_D_MASK 0x10 307 #define PG_ERROR_PK_MASK 0x20 308 309 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 310 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 311 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 312 313 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 314 #define MCE_BANKS_DEF 10 315 316 #define MCG_CAP_BANKS_MASK 0xff 317 318 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 319 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 320 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 321 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 322 323 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 324 325 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 326 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 327 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 328 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 329 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 330 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 331 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 332 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 333 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 334 335 /* MISC register defines */ 336 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 337 #define MCM_ADDR_LINEAR 1 /* linear address */ 338 #define MCM_ADDR_PHYS 2 /* physical address */ 339 #define MCM_ADDR_MEM 3 /* memory address */ 340 #define MCM_ADDR_GENERIC 7 /* generic */ 341 342 #define MSR_IA32_TSC 0x10 343 #define MSR_IA32_APICBASE 0x1b 344 #define MSR_IA32_APICBASE_BSP (1<<8) 345 #define MSR_IA32_APICBASE_ENABLE (1<<11) 346 #define MSR_IA32_APICBASE_EXTD (1 << 10) 347 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 348 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 349 #define MSR_TSC_ADJUST 0x0000003b 350 #define MSR_IA32_SPEC_CTRL 0x48 351 #define MSR_VIRT_SSBD 0xc001011f 352 #define MSR_IA32_PRED_CMD 0x49 353 #define MSR_IA32_UCODE_REV 0x8b 354 #define MSR_IA32_CORE_CAPABILITY 0xcf 355 356 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 357 #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 358 359 #define MSR_IA32_TSX_CTRL 0x122 360 #define MSR_IA32_TSCDEADLINE 0x6e0 361 362 #define FEATURE_CONTROL_LOCKED (1<<0) 363 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 364 #define FEATURE_CONTROL_LMCE (1<<20) 365 366 #define MSR_P6_PERFCTR0 0xc1 367 368 #define MSR_IA32_SMBASE 0x9e 369 #define MSR_SMI_COUNT 0x34 370 #define MSR_MTRRcap 0xfe 371 #define MSR_MTRRcap_VCNT 8 372 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 373 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 374 375 #define MSR_IA32_SYSENTER_CS 0x174 376 #define MSR_IA32_SYSENTER_ESP 0x175 377 #define MSR_IA32_SYSENTER_EIP 0x176 378 379 #define MSR_MCG_CAP 0x179 380 #define MSR_MCG_STATUS 0x17a 381 #define MSR_MCG_CTL 0x17b 382 #define MSR_MCG_EXT_CTL 0x4d0 383 384 #define MSR_P6_EVNTSEL0 0x186 385 386 #define MSR_IA32_PERF_STATUS 0x198 387 388 #define MSR_IA32_MISC_ENABLE 0x1a0 389 /* Indicates good rep/movs microcode on some processors: */ 390 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 391 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 392 393 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 394 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 395 396 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 397 398 #define MSR_MTRRfix64K_00000 0x250 399 #define MSR_MTRRfix16K_80000 0x258 400 #define MSR_MTRRfix16K_A0000 0x259 401 #define MSR_MTRRfix4K_C0000 0x268 402 #define MSR_MTRRfix4K_C8000 0x269 403 #define MSR_MTRRfix4K_D0000 0x26a 404 #define MSR_MTRRfix4K_D8000 0x26b 405 #define MSR_MTRRfix4K_E0000 0x26c 406 #define MSR_MTRRfix4K_E8000 0x26d 407 #define MSR_MTRRfix4K_F0000 0x26e 408 #define MSR_MTRRfix4K_F8000 0x26f 409 410 #define MSR_PAT 0x277 411 412 #define MSR_MTRRdefType 0x2ff 413 414 #define MSR_CORE_PERF_FIXED_CTR0 0x309 415 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 416 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 417 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 418 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 419 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 420 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 421 422 #define MSR_MC0_CTL 0x400 423 #define MSR_MC0_STATUS 0x401 424 #define MSR_MC0_ADDR 0x402 425 #define MSR_MC0_MISC 0x403 426 427 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 428 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 429 #define MSR_IA32_RTIT_CTL 0x570 430 #define MSR_IA32_RTIT_STATUS 0x571 431 #define MSR_IA32_RTIT_CR3_MATCH 0x572 432 #define MSR_IA32_RTIT_ADDR0_A 0x580 433 #define MSR_IA32_RTIT_ADDR0_B 0x581 434 #define MSR_IA32_RTIT_ADDR1_A 0x582 435 #define MSR_IA32_RTIT_ADDR1_B 0x583 436 #define MSR_IA32_RTIT_ADDR2_A 0x584 437 #define MSR_IA32_RTIT_ADDR2_B 0x585 438 #define MSR_IA32_RTIT_ADDR3_A 0x586 439 #define MSR_IA32_RTIT_ADDR3_B 0x587 440 #define MAX_RTIT_ADDRS 8 441 442 #define MSR_EFER 0xc0000080 443 444 #define MSR_EFER_SCE (1 << 0) 445 #define MSR_EFER_LME (1 << 8) 446 #define MSR_EFER_LMA (1 << 10) 447 #define MSR_EFER_NXE (1 << 11) 448 #define MSR_EFER_SVME (1 << 12) 449 #define MSR_EFER_FFXSR (1 << 14) 450 451 #define MSR_STAR 0xc0000081 452 #define MSR_LSTAR 0xc0000082 453 #define MSR_CSTAR 0xc0000083 454 #define MSR_FMASK 0xc0000084 455 #define MSR_FSBASE 0xc0000100 456 #define MSR_GSBASE 0xc0000101 457 #define MSR_KERNELGSBASE 0xc0000102 458 #define MSR_TSC_AUX 0xc0000103 459 460 #define MSR_VM_HSAVE_PA 0xc0010117 461 462 #define MSR_IA32_BNDCFGS 0x00000d90 463 #define MSR_IA32_XSS 0x00000da0 464 #define MSR_IA32_UMWAIT_CONTROL 0xe1 465 466 #define MSR_IA32_VMX_BASIC 0x00000480 467 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 468 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 469 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 470 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 471 #define MSR_IA32_VMX_MISC 0x00000485 472 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 473 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 474 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 475 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 476 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 477 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 478 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 479 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 480 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 481 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 482 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 483 #define MSR_IA32_VMX_VMFUNC 0x00000491 484 485 #define XSTATE_FP_BIT 0 486 #define XSTATE_SSE_BIT 1 487 #define XSTATE_YMM_BIT 2 488 #define XSTATE_BNDREGS_BIT 3 489 #define XSTATE_BNDCSR_BIT 4 490 #define XSTATE_OPMASK_BIT 5 491 #define XSTATE_ZMM_Hi256_BIT 6 492 #define XSTATE_Hi16_ZMM_BIT 7 493 #define XSTATE_PKRU_BIT 9 494 495 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 496 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 497 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 498 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 499 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 500 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 501 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 502 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 503 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 504 505 /* CPUID feature words */ 506 typedef enum FeatureWord { 507 FEAT_1_EDX, /* CPUID[1].EDX */ 508 FEAT_1_ECX, /* CPUID[1].ECX */ 509 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 510 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 511 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 512 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 513 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 514 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 515 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 516 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 517 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 518 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 519 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 520 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 521 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 522 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 523 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ 524 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ 525 FEAT_SVM, /* CPUID[8000_000A].EDX */ 526 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 527 FEAT_6_EAX, /* CPUID[6].EAX */ 528 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 529 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 530 FEAT_ARCH_CAPABILITIES, 531 FEAT_CORE_CAPABILITY, 532 FEAT_VMX_PROCBASED_CTLS, 533 FEAT_VMX_SECONDARY_CTLS, 534 FEAT_VMX_PINBASED_CTLS, 535 FEAT_VMX_EXIT_CTLS, 536 FEAT_VMX_ENTRY_CTLS, 537 FEAT_VMX_MISC, 538 FEAT_VMX_EPT_VPID_CAPS, 539 FEAT_VMX_BASIC, 540 FEAT_VMX_VMFUNC, 541 FEATURE_WORDS, 542 } FeatureWord; 543 544 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 545 546 /* cpuid_features bits */ 547 #define CPUID_FP87 (1U << 0) 548 #define CPUID_VME (1U << 1) 549 #define CPUID_DE (1U << 2) 550 #define CPUID_PSE (1U << 3) 551 #define CPUID_TSC (1U << 4) 552 #define CPUID_MSR (1U << 5) 553 #define CPUID_PAE (1U << 6) 554 #define CPUID_MCE (1U << 7) 555 #define CPUID_CX8 (1U << 8) 556 #define CPUID_APIC (1U << 9) 557 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 558 #define CPUID_MTRR (1U << 12) 559 #define CPUID_PGE (1U << 13) 560 #define CPUID_MCA (1U << 14) 561 #define CPUID_CMOV (1U << 15) 562 #define CPUID_PAT (1U << 16) 563 #define CPUID_PSE36 (1U << 17) 564 #define CPUID_PN (1U << 18) 565 #define CPUID_CLFLUSH (1U << 19) 566 #define CPUID_DTS (1U << 21) 567 #define CPUID_ACPI (1U << 22) 568 #define CPUID_MMX (1U << 23) 569 #define CPUID_FXSR (1U << 24) 570 #define CPUID_SSE (1U << 25) 571 #define CPUID_SSE2 (1U << 26) 572 #define CPUID_SS (1U << 27) 573 #define CPUID_HT (1U << 28) 574 #define CPUID_TM (1U << 29) 575 #define CPUID_IA64 (1U << 30) 576 #define CPUID_PBE (1U << 31) 577 578 #define CPUID_EXT_SSE3 (1U << 0) 579 #define CPUID_EXT_PCLMULQDQ (1U << 1) 580 #define CPUID_EXT_DTES64 (1U << 2) 581 #define CPUID_EXT_MONITOR (1U << 3) 582 #define CPUID_EXT_DSCPL (1U << 4) 583 #define CPUID_EXT_VMX (1U << 5) 584 #define CPUID_EXT_SMX (1U << 6) 585 #define CPUID_EXT_EST (1U << 7) 586 #define CPUID_EXT_TM2 (1U << 8) 587 #define CPUID_EXT_SSSE3 (1U << 9) 588 #define CPUID_EXT_CID (1U << 10) 589 #define CPUID_EXT_FMA (1U << 12) 590 #define CPUID_EXT_CX16 (1U << 13) 591 #define CPUID_EXT_XTPR (1U << 14) 592 #define CPUID_EXT_PDCM (1U << 15) 593 #define CPUID_EXT_PCID (1U << 17) 594 #define CPUID_EXT_DCA (1U << 18) 595 #define CPUID_EXT_SSE41 (1U << 19) 596 #define CPUID_EXT_SSE42 (1U << 20) 597 #define CPUID_EXT_X2APIC (1U << 21) 598 #define CPUID_EXT_MOVBE (1U << 22) 599 #define CPUID_EXT_POPCNT (1U << 23) 600 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 601 #define CPUID_EXT_AES (1U << 25) 602 #define CPUID_EXT_XSAVE (1U << 26) 603 #define CPUID_EXT_OSXSAVE (1U << 27) 604 #define CPUID_EXT_AVX (1U << 28) 605 #define CPUID_EXT_F16C (1U << 29) 606 #define CPUID_EXT_RDRAND (1U << 30) 607 #define CPUID_EXT_HYPERVISOR (1U << 31) 608 609 #define CPUID_EXT2_FPU (1U << 0) 610 #define CPUID_EXT2_VME (1U << 1) 611 #define CPUID_EXT2_DE (1U << 2) 612 #define CPUID_EXT2_PSE (1U << 3) 613 #define CPUID_EXT2_TSC (1U << 4) 614 #define CPUID_EXT2_MSR (1U << 5) 615 #define CPUID_EXT2_PAE (1U << 6) 616 #define CPUID_EXT2_MCE (1U << 7) 617 #define CPUID_EXT2_CX8 (1U << 8) 618 #define CPUID_EXT2_APIC (1U << 9) 619 #define CPUID_EXT2_SYSCALL (1U << 11) 620 #define CPUID_EXT2_MTRR (1U << 12) 621 #define CPUID_EXT2_PGE (1U << 13) 622 #define CPUID_EXT2_MCA (1U << 14) 623 #define CPUID_EXT2_CMOV (1U << 15) 624 #define CPUID_EXT2_PAT (1U << 16) 625 #define CPUID_EXT2_PSE36 (1U << 17) 626 #define CPUID_EXT2_MP (1U << 19) 627 #define CPUID_EXT2_NX (1U << 20) 628 #define CPUID_EXT2_MMXEXT (1U << 22) 629 #define CPUID_EXT2_MMX (1U << 23) 630 #define CPUID_EXT2_FXSR (1U << 24) 631 #define CPUID_EXT2_FFXSR (1U << 25) 632 #define CPUID_EXT2_PDPE1GB (1U << 26) 633 #define CPUID_EXT2_RDTSCP (1U << 27) 634 #define CPUID_EXT2_LM (1U << 29) 635 #define CPUID_EXT2_3DNOWEXT (1U << 30) 636 #define CPUID_EXT2_3DNOW (1U << 31) 637 638 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 639 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 640 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 641 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 642 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 643 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 644 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 645 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 646 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 647 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 648 649 #define CPUID_EXT3_LAHF_LM (1U << 0) 650 #define CPUID_EXT3_CMP_LEG (1U << 1) 651 #define CPUID_EXT3_SVM (1U << 2) 652 #define CPUID_EXT3_EXTAPIC (1U << 3) 653 #define CPUID_EXT3_CR8LEG (1U << 4) 654 #define CPUID_EXT3_ABM (1U << 5) 655 #define CPUID_EXT3_SSE4A (1U << 6) 656 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 657 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 658 #define CPUID_EXT3_OSVW (1U << 9) 659 #define CPUID_EXT3_IBS (1U << 10) 660 #define CPUID_EXT3_XOP (1U << 11) 661 #define CPUID_EXT3_SKINIT (1U << 12) 662 #define CPUID_EXT3_WDT (1U << 13) 663 #define CPUID_EXT3_LWP (1U << 15) 664 #define CPUID_EXT3_FMA4 (1U << 16) 665 #define CPUID_EXT3_TCE (1U << 17) 666 #define CPUID_EXT3_NODEID (1U << 19) 667 #define CPUID_EXT3_TBM (1U << 21) 668 #define CPUID_EXT3_TOPOEXT (1U << 22) 669 #define CPUID_EXT3_PERFCORE (1U << 23) 670 #define CPUID_EXT3_PERFNB (1U << 24) 671 672 #define CPUID_SVM_NPT (1U << 0) 673 #define CPUID_SVM_LBRV (1U << 1) 674 #define CPUID_SVM_SVMLOCK (1U << 2) 675 #define CPUID_SVM_NRIPSAVE (1U << 3) 676 #define CPUID_SVM_TSCSCALE (1U << 4) 677 #define CPUID_SVM_VMCBCLEAN (1U << 5) 678 #define CPUID_SVM_FLUSHASID (1U << 6) 679 #define CPUID_SVM_DECODEASSIST (1U << 7) 680 #define CPUID_SVM_PAUSEFILTER (1U << 10) 681 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 682 683 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 684 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 685 /* 1st Group of Advanced Bit Manipulation Extensions */ 686 #define CPUID_7_0_EBX_BMI1 (1U << 3) 687 /* Hardware Lock Elision */ 688 #define CPUID_7_0_EBX_HLE (1U << 4) 689 /* Intel Advanced Vector Extensions 2 */ 690 #define CPUID_7_0_EBX_AVX2 (1U << 5) 691 /* Supervisor-mode Execution Prevention */ 692 #define CPUID_7_0_EBX_SMEP (1U << 7) 693 /* 2nd Group of Advanced Bit Manipulation Extensions */ 694 #define CPUID_7_0_EBX_BMI2 (1U << 8) 695 /* Enhanced REP MOVSB/STOSB */ 696 #define CPUID_7_0_EBX_ERMS (1U << 9) 697 /* Invalidate Process-Context Identifier */ 698 #define CPUID_7_0_EBX_INVPCID (1U << 10) 699 /* Restricted Transactional Memory */ 700 #define CPUID_7_0_EBX_RTM (1U << 11) 701 /* Memory Protection Extension */ 702 #define CPUID_7_0_EBX_MPX (1U << 14) 703 /* AVX-512 Foundation */ 704 #define CPUID_7_0_EBX_AVX512F (1U << 16) 705 /* AVX-512 Doubleword & Quadword Instruction */ 706 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 707 /* Read Random SEED */ 708 #define CPUID_7_0_EBX_RDSEED (1U << 18) 709 /* ADCX and ADOX instructions */ 710 #define CPUID_7_0_EBX_ADX (1U << 19) 711 /* Supervisor Mode Access Prevention */ 712 #define CPUID_7_0_EBX_SMAP (1U << 20) 713 /* AVX-512 Integer Fused Multiply Add */ 714 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 715 /* Persistent Commit */ 716 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 717 /* Flush a Cache Line Optimized */ 718 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 719 /* Cache Line Write Back */ 720 #define CPUID_7_0_EBX_CLWB (1U << 24) 721 /* Intel Processor Trace */ 722 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 723 /* AVX-512 Prefetch */ 724 #define CPUID_7_0_EBX_AVX512PF (1U << 26) 725 /* AVX-512 Exponential and Reciprocal */ 726 #define CPUID_7_0_EBX_AVX512ER (1U << 27) 727 /* AVX-512 Conflict Detection */ 728 #define CPUID_7_0_EBX_AVX512CD (1U << 28) 729 /* SHA1/SHA256 Instruction Extensions */ 730 #define CPUID_7_0_EBX_SHA_NI (1U << 29) 731 /* AVX-512 Byte and Word Instructions */ 732 #define CPUID_7_0_EBX_AVX512BW (1U << 30) 733 /* AVX-512 Vector Length Extensions */ 734 #define CPUID_7_0_EBX_AVX512VL (1U << 31) 735 736 /* AVX-512 Vector Byte Manipulation Instruction */ 737 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 738 /* User-Mode Instruction Prevention */ 739 #define CPUID_7_0_ECX_UMIP (1U << 2) 740 /* Protection Keys for User-mode Pages */ 741 #define CPUID_7_0_ECX_PKU (1U << 3) 742 /* OS Enable Protection Keys */ 743 #define CPUID_7_0_ECX_OSPKE (1U << 4) 744 /* UMONITOR/UMWAIT/TPAUSE Instructions */ 745 #define CPUID_7_0_ECX_WAITPKG (1U << 5) 746 /* Additional AVX-512 Vector Byte Manipulation Instruction */ 747 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 748 /* Galois Field New Instructions */ 749 #define CPUID_7_0_ECX_GFNI (1U << 8) 750 /* Vector AES Instructions */ 751 #define CPUID_7_0_ECX_VAES (1U << 9) 752 /* Carry-Less Multiplication Quadword */ 753 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 754 /* Vector Neural Network Instructions */ 755 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 756 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 757 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 758 /* POPCNT for vectors of DW/QW */ 759 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 760 /* 5-level Page Tables */ 761 #define CPUID_7_0_ECX_LA57 (1U << 16) 762 /* Read Processor ID */ 763 #define CPUID_7_0_ECX_RDPID (1U << 22) 764 /* Cache Line Demote Instruction */ 765 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 766 /* Move Doubleword as Direct Store Instruction */ 767 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 768 /* Move 64 Bytes as Direct Store Instruction */ 769 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 770 771 /* AVX512 Neural Network Instructions */ 772 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 773 /* AVX512 Multiply Accumulation Single Precision */ 774 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 775 /* Speculation Control */ 776 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 777 /* Single Thread Indirect Branch Predictors */ 778 #define CPUID_7_0_EDX_STIBP (1U << 27) 779 /* Arch Capabilities */ 780 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 781 /* Core Capability */ 782 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 783 /* Speculative Store Bypass Disable */ 784 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 785 786 /* AVX512 BFloat16 Instruction */ 787 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 788 789 /* CLZERO instruction */ 790 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 791 /* Always save/restore FP error pointers */ 792 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 793 /* Write back and do not invalidate cache */ 794 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 795 /* Indirect Branch Prediction Barrier */ 796 #define CPUID_8000_0008_EBX_IBPB (1U << 12) 797 /* Single Thread Indirect Branch Predictors */ 798 #define CPUID_8000_0008_EBX_STIBP (1U << 15) 799 800 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 801 #define CPUID_XSAVE_XSAVEC (1U << 1) 802 #define CPUID_XSAVE_XGETBV1 (1U << 2) 803 #define CPUID_XSAVE_XSAVES (1U << 3) 804 805 #define CPUID_6_EAX_ARAT (1U << 2) 806 807 /* CPUID[0x80000007].EDX flags: */ 808 #define CPUID_APM_INVTSC (1U << 8) 809 810 #define CPUID_VENDOR_SZ 12 811 812 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 813 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 814 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 815 #define CPUID_VENDOR_INTEL "GenuineIntel" 816 817 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 818 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 819 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 820 #define CPUID_VENDOR_AMD "AuthenticAMD" 821 822 #define CPUID_VENDOR_VIA "CentaurHauls" 823 824 #define CPUID_VENDOR_HYGON "HygonGenuine" 825 826 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 827 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 828 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 829 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 830 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 831 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 832 833 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 834 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 835 836 /* CPUID[0xB].ECX level types */ 837 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 838 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 839 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 840 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 841 842 /* MSR Feature Bits */ 843 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 844 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 845 #define MSR_ARCH_CAP_RSBA (1U << 2) 846 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 847 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 848 #define MSR_ARCH_CAP_MDS_NO (1U << 5) 849 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 850 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 851 #define MSR_ARCH_CAP_TAA_NO (1U << 8) 852 853 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 854 855 /* VMX MSR features */ 856 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 857 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 858 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 859 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 860 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 861 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 862 863 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 864 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 865 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 866 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 867 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 868 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 869 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 870 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 871 872 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 873 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 874 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 875 #define MSR_VMX_EPT_UC (1ULL << 8) 876 #define MSR_VMX_EPT_WB (1ULL << 14) 877 #define MSR_VMX_EPT_2MB (1ULL << 16) 878 #define MSR_VMX_EPT_1GB (1ULL << 17) 879 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 880 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 881 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 882 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 883 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 884 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 885 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 886 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 887 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 888 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 889 890 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 891 892 893 /* VMX controls */ 894 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 895 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 896 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 897 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 898 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 899 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 900 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 901 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 902 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 903 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 904 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 905 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 906 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 907 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 908 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 909 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 910 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 911 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 912 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 913 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 914 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 915 916 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 917 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 918 #define VMX_SECONDARY_EXEC_DESC 0x00000004 919 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 920 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 921 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 922 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 923 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 924 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 925 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 926 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 927 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 928 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 929 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 930 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 931 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 932 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 933 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 934 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 935 936 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 937 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 938 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 939 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 940 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 941 942 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 943 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 944 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 945 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 946 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 947 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 948 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 949 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 950 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 951 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 952 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 953 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 954 955 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 956 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 957 #define VMX_VM_ENTRY_SMM 0x00000400 958 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 959 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 960 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 961 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 962 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 963 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 964 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 965 966 /* Supported Hyper-V Enlightenments */ 967 #define HYPERV_FEAT_RELAXED 0 968 #define HYPERV_FEAT_VAPIC 1 969 #define HYPERV_FEAT_TIME 2 970 #define HYPERV_FEAT_CRASH 3 971 #define HYPERV_FEAT_RESET 4 972 #define HYPERV_FEAT_VPINDEX 5 973 #define HYPERV_FEAT_RUNTIME 6 974 #define HYPERV_FEAT_SYNIC 7 975 #define HYPERV_FEAT_STIMER 8 976 #define HYPERV_FEAT_FREQUENCIES 9 977 #define HYPERV_FEAT_REENLIGHTENMENT 10 978 #define HYPERV_FEAT_TLBFLUSH 11 979 #define HYPERV_FEAT_EVMCS 12 980 #define HYPERV_FEAT_IPI 13 981 #define HYPERV_FEAT_STIMER_DIRECT 14 982 983 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 984 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 985 #endif 986 987 #define EXCP00_DIVZ 0 988 #define EXCP01_DB 1 989 #define EXCP02_NMI 2 990 #define EXCP03_INT3 3 991 #define EXCP04_INTO 4 992 #define EXCP05_BOUND 5 993 #define EXCP06_ILLOP 6 994 #define EXCP07_PREX 7 995 #define EXCP08_DBLE 8 996 #define EXCP09_XERR 9 997 #define EXCP0A_TSS 10 998 #define EXCP0B_NOSEG 11 999 #define EXCP0C_STACK 12 1000 #define EXCP0D_GPF 13 1001 #define EXCP0E_PAGE 14 1002 #define EXCP10_COPR 16 1003 #define EXCP11_ALGN 17 1004 #define EXCP12_MCHK 18 1005 1006 #define EXCP_VMEXIT 0x100 /* only for system emulation */ 1007 #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1008 #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1009 1010 /* i386-specific interrupt pending bits. */ 1011 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1012 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1013 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1014 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1015 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1016 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1017 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1018 1019 /* Use a clearer name for this. */ 1020 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1021 1022 /* Instead of computing the condition codes after each x86 instruction, 1023 * QEMU just stores one operand (called CC_SRC), the result 1024 * (called CC_DST) and the type of operation (called CC_OP). When the 1025 * condition codes are needed, the condition codes can be calculated 1026 * using this information. Condition codes are not generated if they 1027 * are only needed for conditional branches. 1028 */ 1029 typedef enum { 1030 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1031 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1032 1033 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1034 CC_OP_MULW, 1035 CC_OP_MULL, 1036 CC_OP_MULQ, 1037 1038 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1039 CC_OP_ADDW, 1040 CC_OP_ADDL, 1041 CC_OP_ADDQ, 1042 1043 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1044 CC_OP_ADCW, 1045 CC_OP_ADCL, 1046 CC_OP_ADCQ, 1047 1048 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1049 CC_OP_SUBW, 1050 CC_OP_SUBL, 1051 CC_OP_SUBQ, 1052 1053 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1054 CC_OP_SBBW, 1055 CC_OP_SBBL, 1056 CC_OP_SBBQ, 1057 1058 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1059 CC_OP_LOGICW, 1060 CC_OP_LOGICL, 1061 CC_OP_LOGICQ, 1062 1063 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1064 CC_OP_INCW, 1065 CC_OP_INCL, 1066 CC_OP_INCQ, 1067 1068 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1069 CC_OP_DECW, 1070 CC_OP_DECL, 1071 CC_OP_DECQ, 1072 1073 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1074 CC_OP_SHLW, 1075 CC_OP_SHLL, 1076 CC_OP_SHLQ, 1077 1078 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1079 CC_OP_SARW, 1080 CC_OP_SARL, 1081 CC_OP_SARQ, 1082 1083 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1084 CC_OP_BMILGW, 1085 CC_OP_BMILGL, 1086 CC_OP_BMILGQ, 1087 1088 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1089 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1090 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1091 1092 CC_OP_CLR, /* Z set, all other flags clear. */ 1093 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1094 1095 CC_OP_NB, 1096 } CCOp; 1097 1098 typedef struct SegmentCache { 1099 uint32_t selector; 1100 target_ulong base; 1101 uint32_t limit; 1102 uint32_t flags; 1103 } SegmentCache; 1104 1105 #define MMREG_UNION(n, bits) \ 1106 union n { \ 1107 uint8_t _b_##n[(bits)/8]; \ 1108 uint16_t _w_##n[(bits)/16]; \ 1109 uint32_t _l_##n[(bits)/32]; \ 1110 uint64_t _q_##n[(bits)/64]; \ 1111 float32 _s_##n[(bits)/32]; \ 1112 float64 _d_##n[(bits)/64]; \ 1113 } 1114 1115 typedef union { 1116 uint8_t _b[16]; 1117 uint16_t _w[8]; 1118 uint32_t _l[4]; 1119 uint64_t _q[2]; 1120 } XMMReg; 1121 1122 typedef union { 1123 uint8_t _b[32]; 1124 uint16_t _w[16]; 1125 uint32_t _l[8]; 1126 uint64_t _q[4]; 1127 } YMMReg; 1128 1129 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1130 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1131 1132 typedef struct BNDReg { 1133 uint64_t lb; 1134 uint64_t ub; 1135 } BNDReg; 1136 1137 typedef struct BNDCSReg { 1138 uint64_t cfgu; 1139 uint64_t sts; 1140 } BNDCSReg; 1141 1142 #define BNDCFG_ENABLE 1ULL 1143 #define BNDCFG_BNDPRESERVE 2ULL 1144 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1145 1146 #ifdef HOST_WORDS_BIGENDIAN 1147 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1148 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1149 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1150 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1151 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1152 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1153 1154 #define MMX_B(n) _b_MMXReg[7 - (n)] 1155 #define MMX_W(n) _w_MMXReg[3 - (n)] 1156 #define MMX_L(n) _l_MMXReg[1 - (n)] 1157 #define MMX_S(n) _s_MMXReg[1 - (n)] 1158 #else 1159 #define ZMM_B(n) _b_ZMMReg[n] 1160 #define ZMM_W(n) _w_ZMMReg[n] 1161 #define ZMM_L(n) _l_ZMMReg[n] 1162 #define ZMM_S(n) _s_ZMMReg[n] 1163 #define ZMM_Q(n) _q_ZMMReg[n] 1164 #define ZMM_D(n) _d_ZMMReg[n] 1165 1166 #define MMX_B(n) _b_MMXReg[n] 1167 #define MMX_W(n) _w_MMXReg[n] 1168 #define MMX_L(n) _l_MMXReg[n] 1169 #define MMX_S(n) _s_MMXReg[n] 1170 #endif 1171 #define MMX_Q(n) _q_MMXReg[n] 1172 1173 typedef union { 1174 floatx80 d __attribute__((aligned(16))); 1175 MMXReg mmx; 1176 } FPReg; 1177 1178 typedef struct { 1179 uint64_t base; 1180 uint64_t mask; 1181 } MTRRVar; 1182 1183 #define CPU_NB_REGS64 16 1184 #define CPU_NB_REGS32 8 1185 1186 #ifdef TARGET_X86_64 1187 #define CPU_NB_REGS CPU_NB_REGS64 1188 #else 1189 #define CPU_NB_REGS CPU_NB_REGS32 1190 #endif 1191 1192 #define MAX_FIXED_COUNTERS 3 1193 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1194 1195 #define TARGET_INSN_START_EXTRA_WORDS 1 1196 1197 #define NB_OPMASK_REGS 8 1198 1199 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1200 * that APIC ID hasn't been set yet 1201 */ 1202 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1203 1204 typedef union X86LegacyXSaveArea { 1205 struct { 1206 uint16_t fcw; 1207 uint16_t fsw; 1208 uint8_t ftw; 1209 uint8_t reserved; 1210 uint16_t fpop; 1211 uint64_t fpip; 1212 uint64_t fpdp; 1213 uint32_t mxcsr; 1214 uint32_t mxcsr_mask; 1215 FPReg fpregs[8]; 1216 uint8_t xmm_regs[16][16]; 1217 }; 1218 uint8_t data[512]; 1219 } X86LegacyXSaveArea; 1220 1221 typedef struct X86XSaveHeader { 1222 uint64_t xstate_bv; 1223 uint64_t xcomp_bv; 1224 uint64_t reserve0; 1225 uint8_t reserved[40]; 1226 } X86XSaveHeader; 1227 1228 /* Ext. save area 2: AVX State */ 1229 typedef struct XSaveAVX { 1230 uint8_t ymmh[16][16]; 1231 } XSaveAVX; 1232 1233 /* Ext. save area 3: BNDREG */ 1234 typedef struct XSaveBNDREG { 1235 BNDReg bnd_regs[4]; 1236 } XSaveBNDREG; 1237 1238 /* Ext. save area 4: BNDCSR */ 1239 typedef union XSaveBNDCSR { 1240 BNDCSReg bndcsr; 1241 uint8_t data[64]; 1242 } XSaveBNDCSR; 1243 1244 /* Ext. save area 5: Opmask */ 1245 typedef struct XSaveOpmask { 1246 uint64_t opmask_regs[NB_OPMASK_REGS]; 1247 } XSaveOpmask; 1248 1249 /* Ext. save area 6: ZMM_Hi256 */ 1250 typedef struct XSaveZMM_Hi256 { 1251 uint8_t zmm_hi256[16][32]; 1252 } XSaveZMM_Hi256; 1253 1254 /* Ext. save area 7: Hi16_ZMM */ 1255 typedef struct XSaveHi16_ZMM { 1256 uint8_t hi16_zmm[16][64]; 1257 } XSaveHi16_ZMM; 1258 1259 /* Ext. save area 9: PKRU state */ 1260 typedef struct XSavePKRU { 1261 uint32_t pkru; 1262 uint32_t padding; 1263 } XSavePKRU; 1264 1265 typedef struct X86XSaveArea { 1266 X86LegacyXSaveArea legacy; 1267 X86XSaveHeader header; 1268 1269 /* Extended save areas: */ 1270 1271 /* AVX State: */ 1272 XSaveAVX avx_state; 1273 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1274 /* MPX State: */ 1275 XSaveBNDREG bndreg_state; 1276 XSaveBNDCSR bndcsr_state; 1277 /* AVX-512 State: */ 1278 XSaveOpmask opmask_state; 1279 XSaveZMM_Hi256 zmm_hi256_state; 1280 XSaveHi16_ZMM hi16_zmm_state; 1281 /* PKRU State: */ 1282 XSavePKRU pkru_state; 1283 } X86XSaveArea; 1284 1285 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1286 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1287 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1288 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1289 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1290 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1291 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1292 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1293 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1294 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1295 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1296 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1297 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1298 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1299 1300 typedef enum TPRAccess { 1301 TPR_ACCESS_READ, 1302 TPR_ACCESS_WRITE, 1303 } TPRAccess; 1304 1305 /* Cache information data structures: */ 1306 1307 enum CacheType { 1308 DATA_CACHE, 1309 INSTRUCTION_CACHE, 1310 UNIFIED_CACHE 1311 }; 1312 1313 typedef struct CPUCacheInfo { 1314 enum CacheType type; 1315 uint8_t level; 1316 /* Size in bytes */ 1317 uint32_t size; 1318 /* Line size, in bytes */ 1319 uint16_t line_size; 1320 /* 1321 * Associativity. 1322 * Note: representation of fully-associative caches is not implemented 1323 */ 1324 uint8_t associativity; 1325 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1326 uint8_t partitions; 1327 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1328 uint32_t sets; 1329 /* 1330 * Lines per tag. 1331 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1332 * (Is this synonym to @partitions?) 1333 */ 1334 uint8_t lines_per_tag; 1335 1336 /* Self-initializing cache */ 1337 bool self_init; 1338 /* 1339 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1340 * non-originating threads sharing this cache. 1341 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1342 */ 1343 bool no_invd_sharing; 1344 /* 1345 * Cache is inclusive of lower cache levels. 1346 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1347 */ 1348 bool inclusive; 1349 /* 1350 * A complex function is used to index the cache, potentially using all 1351 * address bits. CPUID[4].EDX[bit 2]. 1352 */ 1353 bool complex_indexing; 1354 } CPUCacheInfo; 1355 1356 1357 typedef struct CPUCaches { 1358 CPUCacheInfo *l1d_cache; 1359 CPUCacheInfo *l1i_cache; 1360 CPUCacheInfo *l2_cache; 1361 CPUCacheInfo *l3_cache; 1362 } CPUCaches; 1363 1364 typedef struct CPUX86State { 1365 /* standard registers */ 1366 target_ulong regs[CPU_NB_REGS]; 1367 target_ulong eip; 1368 target_ulong eflags; /* eflags register. During CPU emulation, CC 1369 flags and DF are set to zero because they are 1370 stored elsewhere */ 1371 1372 /* emulator internal eflags handling */ 1373 target_ulong cc_dst; 1374 target_ulong cc_src; 1375 target_ulong cc_src2; 1376 uint32_t cc_op; 1377 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1378 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1379 are known at translation time. */ 1380 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1381 1382 /* segments */ 1383 SegmentCache segs[6]; /* selector values */ 1384 SegmentCache ldt; 1385 SegmentCache tr; 1386 SegmentCache gdt; /* only base and limit are used */ 1387 SegmentCache idt; /* only base and limit are used */ 1388 1389 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1390 int32_t a20_mask; 1391 1392 BNDReg bnd_regs[4]; 1393 BNDCSReg bndcs_regs; 1394 uint64_t msr_bndcfgs; 1395 uint64_t efer; 1396 1397 /* Beginning of state preserved by INIT (dummy marker). */ 1398 struct {} start_init_save; 1399 1400 /* FPU state */ 1401 unsigned int fpstt; /* top of stack index */ 1402 uint16_t fpus; 1403 uint16_t fpuc; 1404 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1405 FPReg fpregs[8]; 1406 /* KVM-only so far */ 1407 uint16_t fpop; 1408 uint64_t fpip; 1409 uint64_t fpdp; 1410 1411 /* emulator internal variables */ 1412 float_status fp_status; 1413 floatx80 ft0; 1414 1415 float_status mmx_status; /* for 3DNow! float ops */ 1416 float_status sse_status; 1417 uint32_t mxcsr; 1418 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1419 ZMMReg xmm_t0; 1420 MMXReg mmx_t0; 1421 1422 XMMReg ymmh_regs[CPU_NB_REGS]; 1423 1424 uint64_t opmask_regs[NB_OPMASK_REGS]; 1425 YMMReg zmmh_regs[CPU_NB_REGS]; 1426 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1427 1428 /* sysenter registers */ 1429 uint32_t sysenter_cs; 1430 target_ulong sysenter_esp; 1431 target_ulong sysenter_eip; 1432 uint64_t star; 1433 1434 uint64_t vm_hsave; 1435 1436 #ifdef TARGET_X86_64 1437 target_ulong lstar; 1438 target_ulong cstar; 1439 target_ulong fmask; 1440 target_ulong kernelgsbase; 1441 #endif 1442 1443 uint64_t tsc; 1444 uint64_t tsc_adjust; 1445 uint64_t tsc_deadline; 1446 uint64_t tsc_aux; 1447 1448 uint64_t xcr0; 1449 1450 uint64_t mcg_status; 1451 uint64_t msr_ia32_misc_enable; 1452 uint64_t msr_ia32_feature_control; 1453 1454 uint64_t msr_fixed_ctr_ctrl; 1455 uint64_t msr_global_ctrl; 1456 uint64_t msr_global_status; 1457 uint64_t msr_global_ovf_ctrl; 1458 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1459 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1460 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1461 1462 uint64_t pat; 1463 uint32_t smbase; 1464 uint64_t msr_smi_count; 1465 1466 uint32_t pkru; 1467 uint32_t tsx_ctrl; 1468 1469 uint64_t spec_ctrl; 1470 uint64_t virt_ssbd; 1471 1472 /* End of state preserved by INIT (dummy marker). */ 1473 struct {} end_init_save; 1474 1475 uint64_t system_time_msr; 1476 uint64_t wall_clock_msr; 1477 uint64_t steal_time_msr; 1478 uint64_t async_pf_en_msr; 1479 uint64_t pv_eoi_en_msr; 1480 uint64_t poll_control_msr; 1481 1482 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1483 uint64_t msr_hv_hypercall; 1484 uint64_t msr_hv_guest_os_id; 1485 uint64_t msr_hv_tsc; 1486 1487 /* Per-VCPU HV MSRs */ 1488 uint64_t msr_hv_vapic; 1489 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1490 uint64_t msr_hv_runtime; 1491 uint64_t msr_hv_synic_control; 1492 uint64_t msr_hv_synic_evt_page; 1493 uint64_t msr_hv_synic_msg_page; 1494 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1495 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1496 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1497 uint64_t msr_hv_reenlightenment_control; 1498 uint64_t msr_hv_tsc_emulation_control; 1499 uint64_t msr_hv_tsc_emulation_status; 1500 1501 uint64_t msr_rtit_ctrl; 1502 uint64_t msr_rtit_status; 1503 uint64_t msr_rtit_output_base; 1504 uint64_t msr_rtit_output_mask; 1505 uint64_t msr_rtit_cr3_match; 1506 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1507 1508 /* exception/interrupt handling */ 1509 int error_code; 1510 int exception_is_int; 1511 target_ulong exception_next_eip; 1512 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1513 union { 1514 struct CPUBreakpoint *cpu_breakpoint[4]; 1515 struct CPUWatchpoint *cpu_watchpoint[4]; 1516 }; /* break/watchpoints for dr[0..3] */ 1517 int old_exception; /* exception in flight */ 1518 1519 uint64_t vm_vmcb; 1520 uint64_t tsc_offset; 1521 uint64_t intercept; 1522 uint16_t intercept_cr_read; 1523 uint16_t intercept_cr_write; 1524 uint16_t intercept_dr_read; 1525 uint16_t intercept_dr_write; 1526 uint32_t intercept_exceptions; 1527 uint64_t nested_cr3; 1528 uint32_t nested_pg_mode; 1529 uint8_t v_tpr; 1530 1531 /* KVM states, automatically cleared on reset */ 1532 uint8_t nmi_injected; 1533 uint8_t nmi_pending; 1534 1535 uintptr_t retaddr; 1536 1537 /* Fields up to this point are cleared by a CPU reset */ 1538 struct {} end_reset_fields; 1539 1540 /* Fields after this point are preserved across CPU reset. */ 1541 1542 /* processor features (e.g. for CPUID insn) */ 1543 /* Minimum cpuid leaf 7 value */ 1544 uint32_t cpuid_level_func7; 1545 /* Actual cpuid leaf 7 value */ 1546 uint32_t cpuid_min_level_func7; 1547 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1548 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1549 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1550 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1551 /* Actual level/xlevel/xlevel2 value: */ 1552 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1553 uint32_t cpuid_vendor1; 1554 uint32_t cpuid_vendor2; 1555 uint32_t cpuid_vendor3; 1556 uint32_t cpuid_version; 1557 FeatureWordArray features; 1558 /* Features that were explicitly enabled/disabled */ 1559 FeatureWordArray user_features; 1560 uint32_t cpuid_model[12]; 1561 /* Cache information for CPUID. When legacy-cache=on, the cache data 1562 * on each CPUID leaf will be different, because we keep compatibility 1563 * with old QEMU versions. 1564 */ 1565 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1566 1567 /* MTRRs */ 1568 uint64_t mtrr_fixed[11]; 1569 uint64_t mtrr_deftype; 1570 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1571 1572 /* For KVM */ 1573 uint32_t mp_state; 1574 int32_t exception_nr; 1575 int32_t interrupt_injected; 1576 uint8_t soft_interrupt; 1577 uint8_t exception_pending; 1578 uint8_t exception_injected; 1579 uint8_t has_error_code; 1580 uint8_t exception_has_payload; 1581 uint64_t exception_payload; 1582 uint32_t ins_len; 1583 uint32_t sipi_vector; 1584 bool tsc_valid; 1585 int64_t tsc_khz; 1586 int64_t user_tsc_khz; /* for sanity check only */ 1587 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1588 void *xsave_buf; 1589 #endif 1590 #if defined(CONFIG_KVM) 1591 struct kvm_nested_state *nested_state; 1592 #endif 1593 #if defined(CONFIG_HVF) 1594 HVFX86EmulatorState *hvf_emul; 1595 #endif 1596 1597 uint64_t mcg_cap; 1598 uint64_t mcg_ctl; 1599 uint64_t mcg_ext_ctl; 1600 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1601 uint64_t xstate_bv; 1602 1603 /* vmstate */ 1604 uint16_t fpus_vmstate; 1605 uint16_t fptag_vmstate; 1606 uint16_t fpregs_format_vmstate; 1607 1608 uint64_t xss; 1609 uint32_t umwait; 1610 1611 TPRAccess tpr_access_type; 1612 1613 unsigned nr_dies; 1614 unsigned nr_nodes; 1615 unsigned pkg_offset; 1616 } CPUX86State; 1617 1618 struct kvm_msrs; 1619 1620 /** 1621 * X86CPU: 1622 * @env: #CPUX86State 1623 * @migratable: If set, only migratable flags will be accepted when "enforce" 1624 * mode is used, and only migratable flags will be included in the "host" 1625 * CPU model. 1626 * 1627 * An x86 CPU. 1628 */ 1629 struct X86CPU { 1630 /*< private >*/ 1631 CPUState parent_obj; 1632 /*< public >*/ 1633 1634 CPUNegativeOffsetState neg; 1635 CPUX86State env; 1636 1637 uint64_t ucode_rev; 1638 1639 uint32_t hyperv_spinlock_attempts; 1640 char *hyperv_vendor_id; 1641 bool hyperv_synic_kvm_only; 1642 uint64_t hyperv_features; 1643 bool hyperv_passthrough; 1644 OnOffAuto hyperv_no_nonarch_cs; 1645 1646 bool check_cpuid; 1647 bool enforce_cpuid; 1648 /* 1649 * Force features to be enabled even if the host doesn't support them. 1650 * This is dangerous and should be done only for testing CPUID 1651 * compatibility. 1652 */ 1653 bool force_features; 1654 bool expose_kvm; 1655 bool expose_tcg; 1656 bool migratable; 1657 bool migrate_smi_count; 1658 bool max_features; /* Enable all supported features automatically */ 1659 uint32_t apic_id; 1660 1661 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1662 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1663 bool vmware_cpuid_freq; 1664 1665 /* if true the CPUID code directly forward host cache leaves to the guest */ 1666 bool cache_info_passthrough; 1667 1668 /* if true the CPUID code directly forwards 1669 * host monitor/mwait leaves to the guest */ 1670 struct { 1671 uint32_t eax; 1672 uint32_t ebx; 1673 uint32_t ecx; 1674 uint32_t edx; 1675 } mwait; 1676 1677 /* Features that were filtered out because of missing host capabilities */ 1678 FeatureWordArray filtered_features; 1679 1680 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1681 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1682 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1683 * capabilities) directly to the guest. 1684 */ 1685 bool enable_pmu; 1686 1687 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1688 * disabled by default to avoid breaking migration between QEMU with 1689 * different LMCE configurations. 1690 */ 1691 bool enable_lmce; 1692 1693 /* Compatibility bits for old machine types. 1694 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1695 * socket share an virtual l3 cache. 1696 */ 1697 bool enable_l3_cache; 1698 1699 /* Compatibility bits for old machine types. 1700 * If true present the old cache topology information 1701 */ 1702 bool legacy_cache; 1703 1704 /* Compatibility bits for old machine types: */ 1705 bool enable_cpuid_0xb; 1706 1707 /* Enable auto level-increase for all CPUID leaves */ 1708 bool full_cpuid_auto_level; 1709 1710 /* Enable auto level-increase for Intel Processor Trace leave */ 1711 bool intel_pt_auto_level; 1712 1713 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1714 bool fill_mtrr_mask; 1715 1716 /* if true override the phys_bits value with a value read from the host */ 1717 bool host_phys_bits; 1718 1719 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1720 uint8_t host_phys_bits_limit; 1721 1722 /* Stop SMI delivery for migration compatibility with old machines */ 1723 bool kvm_no_smi_migration; 1724 1725 /* Number of physical address bits supported */ 1726 uint32_t phys_bits; 1727 1728 /* in order to simplify APIC support, we leave this pointer to the 1729 user */ 1730 struct DeviceState *apic_state; 1731 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1732 Notifier machine_done; 1733 1734 struct kvm_msrs *kvm_msr_buf; 1735 1736 int32_t node_id; /* NUMA node this CPU belongs to */ 1737 int32_t socket_id; 1738 int32_t die_id; 1739 int32_t core_id; 1740 int32_t thread_id; 1741 1742 int32_t hv_max_vps; 1743 }; 1744 1745 1746 #ifndef CONFIG_USER_ONLY 1747 extern VMStateDescription vmstate_x86_cpu; 1748 #endif 1749 1750 /** 1751 * x86_cpu_do_interrupt: 1752 * @cpu: vCPU the interrupt is to be handled by. 1753 */ 1754 void x86_cpu_do_interrupt(CPUState *cpu); 1755 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1756 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1757 1758 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1759 int cpuid, void *opaque); 1760 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1761 int cpuid, void *opaque); 1762 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1763 void *opaque); 1764 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1765 void *opaque); 1766 1767 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1768 Error **errp); 1769 1770 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1771 1772 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1773 MemTxAttrs *attrs); 1774 1775 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1776 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1777 1778 void x86_cpu_exec_enter(CPUState *cpu); 1779 void x86_cpu_exec_exit(CPUState *cpu); 1780 1781 void x86_cpu_list(void); 1782 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1783 1784 int cpu_get_pic_interrupt(CPUX86State *s); 1785 /* MSDOS compatibility mode FPU exception support */ 1786 void x86_register_ferr_irq(qemu_irq irq); 1787 void cpu_set_ignne(void); 1788 /* mpx_helper.c */ 1789 void cpu_sync_bndcs_hflags(CPUX86State *env); 1790 1791 /* this function must always be used to load data in the segment 1792 cache: it synchronizes the hflags with the segment cache values */ 1793 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1794 int seg_reg, unsigned int selector, 1795 target_ulong base, 1796 unsigned int limit, 1797 unsigned int flags) 1798 { 1799 SegmentCache *sc; 1800 unsigned int new_hflags; 1801 1802 sc = &env->segs[seg_reg]; 1803 sc->selector = selector; 1804 sc->base = base; 1805 sc->limit = limit; 1806 sc->flags = flags; 1807 1808 /* update the hidden flags */ 1809 { 1810 if (seg_reg == R_CS) { 1811 #ifdef TARGET_X86_64 1812 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1813 /* long mode */ 1814 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1815 env->hflags &= ~(HF_ADDSEG_MASK); 1816 } else 1817 #endif 1818 { 1819 /* legacy / compatibility case */ 1820 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1821 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1822 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1823 new_hflags; 1824 } 1825 } 1826 if (seg_reg == R_SS) { 1827 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1828 #if HF_CPL_MASK != 3 1829 #error HF_CPL_MASK is hardcoded 1830 #endif 1831 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1832 /* Possibly switch between BNDCFGS and BNDCFGU */ 1833 cpu_sync_bndcs_hflags(env); 1834 } 1835 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1836 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1837 if (env->hflags & HF_CS64_MASK) { 1838 /* zero base assumed for DS, ES and SS in long mode */ 1839 } else if (!(env->cr[0] & CR0_PE_MASK) || 1840 (env->eflags & VM_MASK) || 1841 !(env->hflags & HF_CS32_MASK)) { 1842 /* XXX: try to avoid this test. The problem comes from the 1843 fact that is real mode or vm86 mode we only modify the 1844 'base' and 'selector' fields of the segment cache to go 1845 faster. A solution may be to force addseg to one in 1846 translate-i386.c. */ 1847 new_hflags |= HF_ADDSEG_MASK; 1848 } else { 1849 new_hflags |= ((env->segs[R_DS].base | 1850 env->segs[R_ES].base | 1851 env->segs[R_SS].base) != 0) << 1852 HF_ADDSEG_SHIFT; 1853 } 1854 env->hflags = (env->hflags & 1855 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1856 } 1857 } 1858 1859 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1860 uint8_t sipi_vector) 1861 { 1862 CPUState *cs = CPU(cpu); 1863 CPUX86State *env = &cpu->env; 1864 1865 env->eip = 0; 1866 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1867 sipi_vector << 12, 1868 env->segs[R_CS].limit, 1869 env->segs[R_CS].flags); 1870 cs->halted = 0; 1871 } 1872 1873 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1874 target_ulong *base, unsigned int *limit, 1875 unsigned int *flags); 1876 1877 /* op_helper.c */ 1878 /* used for debug or cpu save/restore */ 1879 1880 /* cpu-exec.c */ 1881 /* the following helpers are only usable in user mode simulation as 1882 they can trigger unexpected exceptions */ 1883 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1884 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1885 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1886 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1887 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1888 1889 /* you can call this signal handler from your SIGBUS and SIGSEGV 1890 signal handlers to inform the virtual CPU of exceptions. non zero 1891 is returned if the signal was handled by the virtual CPU. */ 1892 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1893 void *puc); 1894 1895 /* cpu.c */ 1896 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1897 uint32_t *eax, uint32_t *ebx, 1898 uint32_t *ecx, uint32_t *edx); 1899 void cpu_clear_apic_feature(CPUX86State *env); 1900 void host_cpuid(uint32_t function, uint32_t count, 1901 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1902 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1903 bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type); 1904 1905 /* helper.c */ 1906 bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1907 MMUAccessType access_type, int mmu_idx, 1908 bool probe, uintptr_t retaddr); 1909 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1910 1911 #ifndef CONFIG_USER_ONLY 1912 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1913 { 1914 return !!attrs.secure; 1915 } 1916 1917 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1918 { 1919 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1920 } 1921 1922 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1923 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1924 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1925 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1926 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1927 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1928 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1929 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1930 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1931 #endif 1932 1933 void breakpoint_handler(CPUState *cs); 1934 1935 /* will be suppressed */ 1936 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1937 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1938 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1939 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1940 1941 /* hw/pc.c */ 1942 uint64_t cpu_get_tsc(CPUX86State *env); 1943 1944 /* XXX: This value should match the one returned by CPUID 1945 * and in exec.c */ 1946 # if defined(TARGET_X86_64) 1947 # define TCG_PHYS_ADDR_BITS 40 1948 # else 1949 # define TCG_PHYS_ADDR_BITS 36 1950 # endif 1951 1952 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1953 1954 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1955 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1956 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1957 1958 #ifdef TARGET_X86_64 1959 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1960 #else 1961 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1962 #endif 1963 1964 #define cpu_signal_handler cpu_x86_signal_handler 1965 #define cpu_list x86_cpu_list 1966 1967 /* MMU modes definitions */ 1968 #define MMU_KSMAP_IDX 0 1969 #define MMU_USER_IDX 1 1970 #define MMU_KNOSMAP_IDX 2 1971 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1972 { 1973 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1974 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1975 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1976 } 1977 1978 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1979 { 1980 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1981 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1982 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1983 } 1984 1985 #define CC_DST (env->cc_dst) 1986 #define CC_SRC (env->cc_src) 1987 #define CC_SRC2 (env->cc_src2) 1988 #define CC_OP (env->cc_op) 1989 1990 /* n must be a constant to be efficient */ 1991 static inline target_long lshift(target_long x, int n) 1992 { 1993 if (n >= 0) { 1994 return x << n; 1995 } else { 1996 return x >> (-n); 1997 } 1998 } 1999 2000 /* float macros */ 2001 #define FT0 (env->ft0) 2002 #define ST0 (env->fpregs[env->fpstt].d) 2003 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 2004 #define ST1 ST(1) 2005 2006 /* translate.c */ 2007 void tcg_x86_init(void); 2008 2009 typedef CPUX86State CPUArchState; 2010 typedef X86CPU ArchCPU; 2011 2012 #include "exec/cpu-all.h" 2013 #include "svm.h" 2014 2015 #if !defined(CONFIG_USER_ONLY) 2016 #include "hw/i386/apic.h" 2017 #endif 2018 2019 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2020 target_ulong *cs_base, uint32_t *flags) 2021 { 2022 *cs_base = env->segs[R_CS].base; 2023 *pc = *cs_base + env->eip; 2024 *flags = env->hflags | 2025 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2026 } 2027 2028 void do_cpu_init(X86CPU *cpu); 2029 void do_cpu_sipi(X86CPU *cpu); 2030 2031 #define MCE_INJECT_BROADCAST 1 2032 #define MCE_INJECT_UNCOND_AO 2 2033 2034 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2035 uint64_t status, uint64_t mcg_status, uint64_t addr, 2036 uint64_t misc, int flags); 2037 2038 /* excp_helper.c */ 2039 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 2040 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 2041 uintptr_t retaddr); 2042 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 2043 int error_code); 2044 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 2045 int error_code, uintptr_t retaddr); 2046 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 2047 int error_code, int next_eip_addend); 2048 2049 /* cc_helper.c */ 2050 extern const uint8_t parity_table[256]; 2051 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2052 2053 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2054 { 2055 uint32_t eflags = env->eflags; 2056 if (tcg_enabled()) { 2057 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 2058 } 2059 return eflags; 2060 } 2061 2062 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 2063 * after generating a call to a helper that uses this. 2064 */ 2065 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 2066 int update_mask) 2067 { 2068 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 2069 CC_OP = CC_OP_EFLAGS; 2070 env->df = 1 - (2 * ((eflags >> 10) & 1)); 2071 env->eflags = (env->eflags & ~update_mask) | 2072 (eflags & update_mask) | 0x2; 2073 } 2074 2075 /* load efer and update the corresponding hflags. XXX: do consistency 2076 checks with cpuid bits? */ 2077 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 2078 { 2079 env->efer = val; 2080 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 2081 if (env->efer & MSR_EFER_LMA) { 2082 env->hflags |= HF_LMA_MASK; 2083 } 2084 if (env->efer & MSR_EFER_SVME) { 2085 env->hflags |= HF_SVME_MASK; 2086 } 2087 } 2088 2089 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2090 { 2091 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2092 } 2093 2094 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2095 { 2096 if (env->hflags & HF_SMM_MASK) { 2097 return -1; 2098 } else { 2099 return env->a20_mask; 2100 } 2101 } 2102 2103 static inline bool cpu_has_vmx(CPUX86State *env) 2104 { 2105 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2106 } 2107 2108 /* 2109 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2110 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2111 * VMX operation. This is because CR4.VMXE is one of the bits set 2112 * in MSR_IA32_VMX_CR4_FIXED1. 2113 * 2114 * There is one exception to above statement when vCPU enters SMM mode. 2115 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2116 * may also reset CR4.VMXE during execution in SMM mode. 2117 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2118 * and CR4.VMXE is restored to it's original value of being set. 2119 * 2120 * Therefore, when vCPU is not in SMM mode, we can infer whether 2121 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2122 * know for certain. 2123 */ 2124 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2125 { 2126 return cpu_has_vmx(env) && 2127 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2128 } 2129 2130 /* fpu_helper.c */ 2131 void update_fp_status(CPUX86State *env); 2132 void update_mxcsr_status(CPUX86State *env); 2133 2134 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2135 { 2136 env->mxcsr = mxcsr; 2137 if (tcg_enabled()) { 2138 update_mxcsr_status(env); 2139 } 2140 } 2141 2142 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2143 { 2144 env->fpuc = fpuc; 2145 if (tcg_enabled()) { 2146 update_fp_status(env); 2147 } 2148 } 2149 2150 /* mem_helper.c */ 2151 void helper_lock_init(void); 2152 2153 /* svm_helper.c */ 2154 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2155 uint64_t param, uintptr_t retaddr); 2156 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, 2157 uint64_t exit_info_1, uintptr_t retaddr); 2158 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 2159 2160 /* seg_helper.c */ 2161 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 2162 2163 /* smm_helper.c */ 2164 void do_smm_enter(X86CPU *cpu); 2165 2166 /* apic.c */ 2167 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2168 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2169 TPRAccess access); 2170 2171 2172 /* Change the value of a KVM-specific default 2173 * 2174 * If value is NULL, no default will be set and the original 2175 * value from the CPU model table will be kept. 2176 * 2177 * It is valid to call this function only for properties that 2178 * are already present in the kvm_default_props table. 2179 */ 2180 void x86_cpu_change_kvm_default(const char *prop, const char *value); 2181 2182 /* Special values for X86CPUVersion: */ 2183 2184 /* Resolve to latest CPU version */ 2185 #define CPU_VERSION_LATEST -1 2186 2187 /* 2188 * Resolve to version defined by current machine type. 2189 * See x86_cpu_set_default_version() 2190 */ 2191 #define CPU_VERSION_AUTO -2 2192 2193 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2194 #define CPU_VERSION_LEGACY 0 2195 2196 typedef int X86CPUVersion; 2197 2198 /* 2199 * Set default CPU model version for CPU models having 2200 * version == CPU_VERSION_AUTO. 2201 */ 2202 void x86_cpu_set_default_version(X86CPUVersion version); 2203 2204 /* Return name of 32-bit register, from a R_* constant */ 2205 const char *get_register_name_32(unsigned int reg); 2206 2207 void enable_compat_apic_id_mode(void); 2208 2209 #define APIC_DEFAULT_ADDRESS 0xfee00000 2210 #define APIC_SPACE_SIZE 0x100000 2211 2212 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2213 2214 /* cpu.c */ 2215 bool cpu_is_bsp(X86CPU *cpu); 2216 2217 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 2218 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 2219 void x86_update_hflags(CPUX86State* env); 2220 2221 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2222 { 2223 return !!(cpu->hyperv_features & BIT(feat)); 2224 } 2225 2226 #if defined(TARGET_X86_64) && \ 2227 defined(CONFIG_USER_ONLY) && \ 2228 defined(CONFIG_LINUX) 2229 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2230 #endif 2231 2232 #endif /* I386_CPU_H */ 2233