xref: /openbmc/qemu/target/i386/cpu.h (revision 8835ed32)
1  /*
2   * i386 virtual CPU header
3   *
4   *  Copyright (c) 2003 Fabrice Bellard
5   *
6   * This library is free software; you can redistribute it and/or
7   * modify it under the terms of the GNU Lesser General Public
8   * License as published by the Free Software Foundation; either
9   * version 2.1 of the License, or (at your option) any later version.
10   *
11   * This library is distributed in the hope that it will be useful,
12   * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14   * Lesser General Public License for more details.
15   *
16   * You should have received a copy of the GNU Lesser General Public
17   * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18   */
19  
20  #ifndef I386_CPU_H
21  #define I386_CPU_H
22  
23  #include "sysemu/tcg.h"
24  #include "cpu-qom.h"
25  #include "kvm/hyperv-proto.h"
26  #include "exec/cpu-defs.h"
27  #include "qapi/qapi-types-common.h"
28  #include "qemu/cpu-float.h"
29  #include "qemu/timer.h"
30  
31  #define XEN_NR_VIRQS 24
32  
33  /* The x86 has a strong memory model with some store-after-load re-ordering */
34  #define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
35  
36  #define KVM_HAVE_MCE_INJECTION 1
37  
38  /* support for self modifying code even if the modified instruction is
39     close to the modifying instruction */
40  #define TARGET_HAS_PRECISE_SMC
41  
42  #ifdef TARGET_X86_64
43  #define I386_ELF_MACHINE  EM_X86_64
44  #define ELF_MACHINE_UNAME "x86_64"
45  #else
46  #define I386_ELF_MACHINE  EM_386
47  #define ELF_MACHINE_UNAME "i686"
48  #endif
49  
50  enum {
51      R_EAX = 0,
52      R_ECX = 1,
53      R_EDX = 2,
54      R_EBX = 3,
55      R_ESP = 4,
56      R_EBP = 5,
57      R_ESI = 6,
58      R_EDI = 7,
59      R_R8 = 8,
60      R_R9 = 9,
61      R_R10 = 10,
62      R_R11 = 11,
63      R_R12 = 12,
64      R_R13 = 13,
65      R_R14 = 14,
66      R_R15 = 15,
67  
68      R_AL = 0,
69      R_CL = 1,
70      R_DL = 2,
71      R_BL = 3,
72      R_AH = 4,
73      R_CH = 5,
74      R_DH = 6,
75      R_BH = 7,
76  };
77  
78  typedef enum X86Seg {
79      R_ES = 0,
80      R_CS = 1,
81      R_SS = 2,
82      R_DS = 3,
83      R_FS = 4,
84      R_GS = 5,
85      R_LDTR = 6,
86      R_TR = 7,
87  } X86Seg;
88  
89  /* segment descriptor fields */
90  #define DESC_G_SHIFT    23
91  #define DESC_G_MASK     (1 << DESC_G_SHIFT)
92  #define DESC_B_SHIFT    22
93  #define DESC_B_MASK     (1 << DESC_B_SHIFT)
94  #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
95  #define DESC_L_MASK     (1 << DESC_L_SHIFT)
96  #define DESC_AVL_SHIFT  20
97  #define DESC_AVL_MASK   (1 << DESC_AVL_SHIFT)
98  #define DESC_P_SHIFT    15
99  #define DESC_P_MASK     (1 << DESC_P_SHIFT)
100  #define DESC_DPL_SHIFT  13
101  #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
102  #define DESC_S_SHIFT    12
103  #define DESC_S_MASK     (1 << DESC_S_SHIFT)
104  #define DESC_TYPE_SHIFT 8
105  #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
106  #define DESC_A_MASK     (1 << 8)
107  
108  #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
109  #define DESC_C_MASK     (1 << 10) /* code: conforming */
110  #define DESC_R_MASK     (1 << 9)  /* code: readable */
111  
112  #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
113  #define DESC_W_MASK     (1 << 9)  /* data: writable */
114  
115  #define DESC_TSS_BUSY_MASK (1 << 9)
116  
117  /* eflags masks */
118  #define CC_C    0x0001
119  #define CC_P    0x0004
120  #define CC_A    0x0010
121  #define CC_Z    0x0040
122  #define CC_S    0x0080
123  #define CC_O    0x0800
124  
125  #define TF_SHIFT   8
126  #define IOPL_SHIFT 12
127  #define VM_SHIFT   17
128  
129  #define TF_MASK                 0x00000100
130  #define IF_MASK                 0x00000200
131  #define DF_MASK                 0x00000400
132  #define IOPL_MASK               0x00003000
133  #define NT_MASK                 0x00004000
134  #define RF_MASK                 0x00010000
135  #define VM_MASK                 0x00020000
136  #define AC_MASK                 0x00040000
137  #define VIF_MASK                0x00080000
138  #define VIP_MASK                0x00100000
139  #define ID_MASK                 0x00200000
140  
141  /* hidden flags - used internally by qemu to represent additional cpu
142     states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
143     avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
144     positions to ease oring with eflags. */
145  /* current cpl */
146  #define HF_CPL_SHIFT         0
147  /* true if hardware interrupts must be disabled for next instruction */
148  #define HF_INHIBIT_IRQ_SHIFT 3
149  /* 16 or 32 segments */
150  #define HF_CS32_SHIFT        4
151  #define HF_SS32_SHIFT        5
152  /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
153  #define HF_ADDSEG_SHIFT      6
154  /* copy of CR0.PE (protected mode) */
155  #define HF_PE_SHIFT          7
156  #define HF_TF_SHIFT          8 /* must be same as eflags */
157  #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
158  #define HF_EM_SHIFT         10
159  #define HF_TS_SHIFT         11
160  #define HF_IOPL_SHIFT       12 /* must be same as eflags */
161  #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
162  #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
163  #define HF_RF_SHIFT         16 /* must be same as eflags */
164  #define HF_VM_SHIFT         17 /* must be same as eflags */
165  #define HF_AC_SHIFT         18 /* must be same as eflags */
166  #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
167  #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
168  #define HF_GUEST_SHIFT      21 /* SVM intercepts are active */
169  #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
170  #define HF_SMAP_SHIFT       23 /* CR4.SMAP */
171  #define HF_IOBPT_SHIFT      24 /* an io breakpoint enabled */
172  #define HF_MPX_EN_SHIFT     25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
173  #define HF_MPX_IU_SHIFT     26 /* BND registers in-use */
174  #define HF_UMIP_SHIFT       27 /* CR4.UMIP */
175  #define HF_AVX_EN_SHIFT     28 /* AVX Enabled (CR4+XCR0) */
176  
177  #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
178  #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
179  #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
180  #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
181  #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
182  #define HF_PE_MASK           (1 << HF_PE_SHIFT)
183  #define HF_TF_MASK           (1 << HF_TF_SHIFT)
184  #define HF_MP_MASK           (1 << HF_MP_SHIFT)
185  #define HF_EM_MASK           (1 << HF_EM_SHIFT)
186  #define HF_TS_MASK           (1 << HF_TS_SHIFT)
187  #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
188  #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
189  #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
190  #define HF_RF_MASK           (1 << HF_RF_SHIFT)
191  #define HF_VM_MASK           (1 << HF_VM_SHIFT)
192  #define HF_AC_MASK           (1 << HF_AC_SHIFT)
193  #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
194  #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
195  #define HF_GUEST_MASK        (1 << HF_GUEST_SHIFT)
196  #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
197  #define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
198  #define HF_IOBPT_MASK        (1 << HF_IOBPT_SHIFT)
199  #define HF_MPX_EN_MASK       (1 << HF_MPX_EN_SHIFT)
200  #define HF_MPX_IU_MASK       (1 << HF_MPX_IU_SHIFT)
201  #define HF_UMIP_MASK         (1 << HF_UMIP_SHIFT)
202  #define HF_AVX_EN_MASK       (1 << HF_AVX_EN_SHIFT)
203  
204  /* hflags2 */
205  
206  #define HF2_GIF_SHIFT            0 /* if set CPU takes interrupts */
207  #define HF2_HIF_SHIFT            1 /* value of IF_MASK when entering SVM */
208  #define HF2_NMI_SHIFT            2 /* CPU serving NMI */
209  #define HF2_VINTR_SHIFT          3 /* value of V_INTR_MASKING bit */
210  #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
211  #define HF2_MPX_PR_SHIFT         5 /* BNDCFGx.BNDPRESERVE */
212  #define HF2_NPT_SHIFT            6 /* Nested Paging enabled */
213  #define HF2_IGNNE_SHIFT          7 /* Ignore CR0.NE=0 */
214  #define HF2_VGIF_SHIFT           8 /* Can take VIRQ*/
215  
216  #define HF2_GIF_MASK            (1 << HF2_GIF_SHIFT)
217  #define HF2_HIF_MASK            (1 << HF2_HIF_SHIFT)
218  #define HF2_NMI_MASK            (1 << HF2_NMI_SHIFT)
219  #define HF2_VINTR_MASK          (1 << HF2_VINTR_SHIFT)
220  #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
221  #define HF2_MPX_PR_MASK         (1 << HF2_MPX_PR_SHIFT)
222  #define HF2_NPT_MASK            (1 << HF2_NPT_SHIFT)
223  #define HF2_IGNNE_MASK          (1 << HF2_IGNNE_SHIFT)
224  #define HF2_VGIF_MASK           (1 << HF2_VGIF_SHIFT)
225  
226  #define CR0_PE_SHIFT 0
227  #define CR0_MP_SHIFT 1
228  
229  #define CR0_PE_MASK  (1U << 0)
230  #define CR0_MP_MASK  (1U << 1)
231  #define CR0_EM_MASK  (1U << 2)
232  #define CR0_TS_MASK  (1U << 3)
233  #define CR0_ET_MASK  (1U << 4)
234  #define CR0_NE_MASK  (1U << 5)
235  #define CR0_WP_MASK  (1U << 16)
236  #define CR0_AM_MASK  (1U << 18)
237  #define CR0_NW_MASK  (1U << 29)
238  #define CR0_CD_MASK  (1U << 30)
239  #define CR0_PG_MASK  (1U << 31)
240  
241  #define CR4_VME_MASK  (1U << 0)
242  #define CR4_PVI_MASK  (1U << 1)
243  #define CR4_TSD_MASK  (1U << 2)
244  #define CR4_DE_MASK   (1U << 3)
245  #define CR4_PSE_MASK  (1U << 4)
246  #define CR4_PAE_MASK  (1U << 5)
247  #define CR4_MCE_MASK  (1U << 6)
248  #define CR4_PGE_MASK  (1U << 7)
249  #define CR4_PCE_MASK  (1U << 8)
250  #define CR4_OSFXSR_SHIFT 9
251  #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
252  #define CR4_OSXMMEXCPT_MASK  (1U << 10)
253  #define CR4_UMIP_MASK   (1U << 11)
254  #define CR4_LA57_MASK   (1U << 12)
255  #define CR4_VMXE_MASK   (1U << 13)
256  #define CR4_SMXE_MASK   (1U << 14)
257  #define CR4_FSGSBASE_MASK (1U << 16)
258  #define CR4_PCIDE_MASK  (1U << 17)
259  #define CR4_OSXSAVE_MASK (1U << 18)
260  #define CR4_SMEP_MASK   (1U << 20)
261  #define CR4_SMAP_MASK   (1U << 21)
262  #define CR4_PKE_MASK   (1U << 22)
263  #define CR4_PKS_MASK   (1U << 24)
264  
265  #define CR4_RESERVED_MASK \
266  (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
267                  | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
268                  | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
269                  | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
270                  | CR4_LA57_MASK \
271                  | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
272                  | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
273  
274  #define DR6_BD          (1 << 13)
275  #define DR6_BS          (1 << 14)
276  #define DR6_BT          (1 << 15)
277  #define DR6_FIXED_1     0xffff0ff0
278  
279  #define DR7_GD          (1 << 13)
280  #define DR7_TYPE_SHIFT  16
281  #define DR7_LEN_SHIFT   18
282  #define DR7_FIXED_1     0x00000400
283  #define DR7_GLOBAL_BP_MASK   0xaa
284  #define DR7_LOCAL_BP_MASK    0x55
285  #define DR7_MAX_BP           4
286  #define DR7_TYPE_BP_INST     0x0
287  #define DR7_TYPE_DATA_WR     0x1
288  #define DR7_TYPE_IO_RW       0x2
289  #define DR7_TYPE_DATA_RW     0x3
290  
291  #define DR_RESERVED_MASK 0xffffffff00000000ULL
292  
293  #define PG_PRESENT_BIT  0
294  #define PG_RW_BIT       1
295  #define PG_USER_BIT     2
296  #define PG_PWT_BIT      3
297  #define PG_PCD_BIT      4
298  #define PG_ACCESSED_BIT 5
299  #define PG_DIRTY_BIT    6
300  #define PG_PSE_BIT      7
301  #define PG_GLOBAL_BIT   8
302  #define PG_PSE_PAT_BIT  12
303  #define PG_PKRU_BIT     59
304  #define PG_NX_BIT       63
305  
306  #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
307  #define PG_RW_MASK       (1 << PG_RW_BIT)
308  #define PG_USER_MASK     (1 << PG_USER_BIT)
309  #define PG_PWT_MASK      (1 << PG_PWT_BIT)
310  #define PG_PCD_MASK      (1 << PG_PCD_BIT)
311  #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
312  #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
313  #define PG_PSE_MASK      (1 << PG_PSE_BIT)
314  #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
315  #define PG_PSE_PAT_MASK  (1 << PG_PSE_PAT_BIT)
316  #define PG_ADDRESS_MASK  0x000ffffffffff000LL
317  #define PG_HI_USER_MASK  0x7ff0000000000000LL
318  #define PG_PKRU_MASK     (15ULL << PG_PKRU_BIT)
319  #define PG_NX_MASK       (1ULL << PG_NX_BIT)
320  
321  #define PG_ERROR_W_BIT     1
322  
323  #define PG_ERROR_P_MASK    0x01
324  #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
325  #define PG_ERROR_U_MASK    0x04
326  #define PG_ERROR_RSVD_MASK 0x08
327  #define PG_ERROR_I_D_MASK  0x10
328  #define PG_ERROR_PK_MASK   0x20
329  
330  #define PG_MODE_PAE      (1 << 0)
331  #define PG_MODE_LMA      (1 << 1)
332  #define PG_MODE_NXE      (1 << 2)
333  #define PG_MODE_PSE      (1 << 3)
334  #define PG_MODE_LA57     (1 << 4)
335  #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
336  
337  /* Bits of CR4 that do not affect the NPT page format.  */
338  #define PG_MODE_WP       (1 << 16)
339  #define PG_MODE_PKE      (1 << 17)
340  #define PG_MODE_PKS      (1 << 18)
341  #define PG_MODE_SMEP     (1 << 19)
342  
343  #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
344  #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
345  #define MCG_LMCE_P      (1ULL<<27) /* Local Machine Check Supported */
346  
347  #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
348  #define MCE_BANKS_DEF   10
349  
350  #define MCG_CAP_BANKS_MASK 0xff
351  
352  #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
353  #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
354  #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
355  #define MCG_STATUS_LMCE (1ULL<<3)   /* Local MCE signaled */
356  
357  #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
358  
359  #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
360  #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
361  #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
362  #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
363  #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
364  #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
365  #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
366  #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
367  #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
368  
369  /* MISC register defines */
370  #define MCM_ADDR_SEGOFF  0      /* segment offset */
371  #define MCM_ADDR_LINEAR  1      /* linear address */
372  #define MCM_ADDR_PHYS    2      /* physical address */
373  #define MCM_ADDR_MEM     3      /* memory address */
374  #define MCM_ADDR_GENERIC 7      /* generic */
375  
376  #define MSR_IA32_TSC                    0x10
377  #define MSR_IA32_APICBASE               0x1b
378  #define MSR_IA32_APICBASE_BSP           (1<<8)
379  #define MSR_IA32_APICBASE_ENABLE        (1<<11)
380  #define MSR_IA32_APICBASE_EXTD          (1 << 10)
381  #define MSR_IA32_APICBASE_BASE          (0xfffffU<<12)
382  #define MSR_IA32_FEATURE_CONTROL        0x0000003a
383  #define MSR_TSC_ADJUST                  0x0000003b
384  #define MSR_IA32_SPEC_CTRL              0x48
385  #define MSR_VIRT_SSBD                   0xc001011f
386  #define MSR_IA32_PRED_CMD               0x49
387  #define MSR_IA32_UCODE_REV              0x8b
388  #define MSR_IA32_CORE_CAPABILITY        0xcf
389  
390  #define MSR_IA32_ARCH_CAPABILITIES      0x10a
391  #define ARCH_CAP_TSX_CTRL_MSR		(1<<7)
392  
393  #define MSR_IA32_PERF_CAPABILITIES      0x345
394  #define PERF_CAP_LBR_FMT                0x3f
395  
396  #define MSR_IA32_TSX_CTRL		0x122
397  #define MSR_IA32_TSCDEADLINE            0x6e0
398  #define MSR_IA32_PKRS                   0x6e1
399  #define MSR_ARCH_LBR_CTL                0x000014ce
400  #define MSR_ARCH_LBR_DEPTH              0x000014cf
401  #define MSR_ARCH_LBR_FROM_0             0x00001500
402  #define MSR_ARCH_LBR_TO_0               0x00001600
403  #define MSR_ARCH_LBR_INFO_0             0x00001200
404  
405  #define FEATURE_CONTROL_LOCKED                    (1<<0)
406  #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX  (1ULL << 1)
407  #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
408  #define FEATURE_CONTROL_SGX_LC                    (1ULL << 17)
409  #define FEATURE_CONTROL_SGX                       (1ULL << 18)
410  #define FEATURE_CONTROL_LMCE                      (1<<20)
411  
412  #define MSR_IA32_SGXLEPUBKEYHASH0       0x8c
413  #define MSR_IA32_SGXLEPUBKEYHASH1       0x8d
414  #define MSR_IA32_SGXLEPUBKEYHASH2       0x8e
415  #define MSR_IA32_SGXLEPUBKEYHASH3       0x8f
416  
417  #define MSR_P6_PERFCTR0                 0xc1
418  
419  #define MSR_IA32_SMBASE                 0x9e
420  #define MSR_SMI_COUNT                   0x34
421  #define MSR_CORE_THREAD_COUNT           0x35
422  #define MSR_MTRRcap                     0xfe
423  #define MSR_MTRRcap_VCNT                8
424  #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
425  #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
426  
427  #define MSR_IA32_SYSENTER_CS            0x174
428  #define MSR_IA32_SYSENTER_ESP           0x175
429  #define MSR_IA32_SYSENTER_EIP           0x176
430  
431  #define MSR_MCG_CAP                     0x179
432  #define MSR_MCG_STATUS                  0x17a
433  #define MSR_MCG_CTL                     0x17b
434  #define MSR_MCG_EXT_CTL                 0x4d0
435  
436  #define MSR_P6_EVNTSEL0                 0x186
437  
438  #define MSR_IA32_PERF_STATUS            0x198
439  
440  #define MSR_IA32_MISC_ENABLE            0x1a0
441  /* Indicates good rep/movs microcode on some processors: */
442  #define MSR_IA32_MISC_ENABLE_DEFAULT    1
443  #define MSR_IA32_MISC_ENABLE_MWAIT      (1ULL << 18)
444  
445  #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
446  #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
447  
448  #define MSR_MTRRphysIndex(addr)         ((((addr) & ~1u) - 0x200) / 2)
449  
450  #define MSR_MTRRfix64K_00000            0x250
451  #define MSR_MTRRfix16K_80000            0x258
452  #define MSR_MTRRfix16K_A0000            0x259
453  #define MSR_MTRRfix4K_C0000             0x268
454  #define MSR_MTRRfix4K_C8000             0x269
455  #define MSR_MTRRfix4K_D0000             0x26a
456  #define MSR_MTRRfix4K_D8000             0x26b
457  #define MSR_MTRRfix4K_E0000             0x26c
458  #define MSR_MTRRfix4K_E8000             0x26d
459  #define MSR_MTRRfix4K_F0000             0x26e
460  #define MSR_MTRRfix4K_F8000             0x26f
461  
462  #define MSR_PAT                         0x277
463  
464  #define MSR_MTRRdefType                 0x2ff
465  
466  #define MSR_CORE_PERF_FIXED_CTR0        0x309
467  #define MSR_CORE_PERF_FIXED_CTR1        0x30a
468  #define MSR_CORE_PERF_FIXED_CTR2        0x30b
469  #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
470  #define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
471  #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
472  #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
473  
474  #define MSR_MC0_CTL                     0x400
475  #define MSR_MC0_STATUS                  0x401
476  #define MSR_MC0_ADDR                    0x402
477  #define MSR_MC0_MISC                    0x403
478  
479  #define MSR_IA32_RTIT_OUTPUT_BASE       0x560
480  #define MSR_IA32_RTIT_OUTPUT_MASK       0x561
481  #define MSR_IA32_RTIT_CTL               0x570
482  #define MSR_IA32_RTIT_STATUS            0x571
483  #define MSR_IA32_RTIT_CR3_MATCH         0x572
484  #define MSR_IA32_RTIT_ADDR0_A           0x580
485  #define MSR_IA32_RTIT_ADDR0_B           0x581
486  #define MSR_IA32_RTIT_ADDR1_A           0x582
487  #define MSR_IA32_RTIT_ADDR1_B           0x583
488  #define MSR_IA32_RTIT_ADDR2_A           0x584
489  #define MSR_IA32_RTIT_ADDR2_B           0x585
490  #define MSR_IA32_RTIT_ADDR3_A           0x586
491  #define MSR_IA32_RTIT_ADDR3_B           0x587
492  #define MAX_RTIT_ADDRS                  8
493  
494  #define MSR_EFER                        0xc0000080
495  
496  #define MSR_EFER_SCE   (1 << 0)
497  #define MSR_EFER_LME   (1 << 8)
498  #define MSR_EFER_LMA   (1 << 10)
499  #define MSR_EFER_NXE   (1 << 11)
500  #define MSR_EFER_SVME  (1 << 12)
501  #define MSR_EFER_FFXSR (1 << 14)
502  
503  #define MSR_EFER_RESERVED\
504          (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
505              | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
506              | MSR_EFER_FFXSR))
507  
508  #define MSR_STAR                        0xc0000081
509  #define MSR_LSTAR                       0xc0000082
510  #define MSR_CSTAR                       0xc0000083
511  #define MSR_FMASK                       0xc0000084
512  #define MSR_FSBASE                      0xc0000100
513  #define MSR_GSBASE                      0xc0000101
514  #define MSR_KERNELGSBASE                0xc0000102
515  #define MSR_TSC_AUX                     0xc0000103
516  #define MSR_AMD64_TSC_RATIO             0xc0000104
517  
518  #define MSR_AMD64_TSC_RATIO_DEFAULT     0x100000000ULL
519  
520  #define MSR_VM_HSAVE_PA                 0xc0010117
521  
522  #define MSR_IA32_XFD                    0x000001c4
523  #define MSR_IA32_XFD_ERR                0x000001c5
524  
525  #define MSR_IA32_BNDCFGS                0x00000d90
526  #define MSR_IA32_XSS                    0x00000da0
527  #define MSR_IA32_UMWAIT_CONTROL         0xe1
528  
529  #define MSR_IA32_VMX_BASIC              0x00000480
530  #define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
531  #define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
532  #define MSR_IA32_VMX_EXIT_CTLS          0x00000483
533  #define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
534  #define MSR_IA32_VMX_MISC               0x00000485
535  #define MSR_IA32_VMX_CR0_FIXED0         0x00000486
536  #define MSR_IA32_VMX_CR0_FIXED1         0x00000487
537  #define MSR_IA32_VMX_CR4_FIXED0         0x00000488
538  #define MSR_IA32_VMX_CR4_FIXED1         0x00000489
539  #define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
540  #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
541  #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
542  #define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
543  #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
544  #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
545  #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
546  #define MSR_IA32_VMX_VMFUNC             0x00000491
547  
548  #define XSTATE_FP_BIT                   0
549  #define XSTATE_SSE_BIT                  1
550  #define XSTATE_YMM_BIT                  2
551  #define XSTATE_BNDREGS_BIT              3
552  #define XSTATE_BNDCSR_BIT               4
553  #define XSTATE_OPMASK_BIT               5
554  #define XSTATE_ZMM_Hi256_BIT            6
555  #define XSTATE_Hi16_ZMM_BIT             7
556  #define XSTATE_PKRU_BIT                 9
557  #define XSTATE_ARCH_LBR_BIT             15
558  #define XSTATE_XTILE_CFG_BIT            17
559  #define XSTATE_XTILE_DATA_BIT           18
560  
561  #define XSTATE_FP_MASK                  (1ULL << XSTATE_FP_BIT)
562  #define XSTATE_SSE_MASK                 (1ULL << XSTATE_SSE_BIT)
563  #define XSTATE_YMM_MASK                 (1ULL << XSTATE_YMM_BIT)
564  #define XSTATE_BNDREGS_MASK             (1ULL << XSTATE_BNDREGS_BIT)
565  #define XSTATE_BNDCSR_MASK              (1ULL << XSTATE_BNDCSR_BIT)
566  #define XSTATE_OPMASK_MASK              (1ULL << XSTATE_OPMASK_BIT)
567  #define XSTATE_ZMM_Hi256_MASK           (1ULL << XSTATE_ZMM_Hi256_BIT)
568  #define XSTATE_Hi16_ZMM_MASK            (1ULL << XSTATE_Hi16_ZMM_BIT)
569  #define XSTATE_PKRU_MASK                (1ULL << XSTATE_PKRU_BIT)
570  #define XSTATE_ARCH_LBR_MASK            (1ULL << XSTATE_ARCH_LBR_BIT)
571  #define XSTATE_XTILE_CFG_MASK           (1ULL << XSTATE_XTILE_CFG_BIT)
572  #define XSTATE_XTILE_DATA_MASK          (1ULL << XSTATE_XTILE_DATA_BIT)
573  
574  #define XSTATE_DYNAMIC_MASK             (XSTATE_XTILE_DATA_MASK)
575  
576  #define ESA_FEATURE_ALIGN64_BIT         1
577  #define ESA_FEATURE_XFD_BIT             2
578  
579  #define ESA_FEATURE_ALIGN64_MASK        (1U << ESA_FEATURE_ALIGN64_BIT)
580  #define ESA_FEATURE_XFD_MASK            (1U << ESA_FEATURE_XFD_BIT)
581  
582  
583  /* CPUID feature bits available in XCR0 */
584  #define CPUID_XSTATE_XCR0_MASK  (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
585                                   XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
586                                   XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
587                                   XSTATE_ZMM_Hi256_MASK | \
588                                   XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
589                                   XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
590  
591  /* CPUID feature words */
592  typedef enum FeatureWord {
593      FEAT_1_EDX,         /* CPUID[1].EDX */
594      FEAT_1_ECX,         /* CPUID[1].ECX */
595      FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
596      FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */
597      FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */
598      FEAT_7_1_EAX,       /* CPUID[EAX=7,ECX=1].EAX */
599      FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
600      FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
601      FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
602      FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
603      FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
604      FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
605      FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
606      FEAT_KVM_HINTS,     /* CPUID[4000_0001].EDX */
607      FEAT_SVM,           /* CPUID[8000_000A].EDX */
608      FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */
609      FEAT_6_EAX,         /* CPUID[6].EAX */
610      FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
611      FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
612      FEAT_ARCH_CAPABILITIES,
613      FEAT_CORE_CAPABILITY,
614      FEAT_PERF_CAPABILITIES,
615      FEAT_VMX_PROCBASED_CTLS,
616      FEAT_VMX_SECONDARY_CTLS,
617      FEAT_VMX_PINBASED_CTLS,
618      FEAT_VMX_EXIT_CTLS,
619      FEAT_VMX_ENTRY_CTLS,
620      FEAT_VMX_MISC,
621      FEAT_VMX_EPT_VPID_CAPS,
622      FEAT_VMX_BASIC,
623      FEAT_VMX_VMFUNC,
624      FEAT_14_0_ECX,
625      FEAT_SGX_12_0_EAX,  /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
626      FEAT_SGX_12_0_EBX,  /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
627      FEAT_SGX_12_1_EAX,  /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
628      FEAT_XSAVE_XSS_LO,     /* CPUID[EAX=0xd,ECX=1].ECX */
629      FEAT_XSAVE_XSS_HI,     /* CPUID[EAX=0xd,ECX=1].EDX */
630      FEAT_7_1_EDX,       /* CPUID[EAX=7,ECX=1].EDX */
631      FEAT_7_2_EDX,       /* CPUID[EAX=7,ECX=2].EDX */
632      FEATURE_WORDS,
633  } FeatureWord;
634  
635  typedef uint64_t FeatureWordArray[FEATURE_WORDS];
636  uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
637                                              bool migratable_only);
638  
639  /* cpuid_features bits */
640  #define CPUID_FP87 (1U << 0)
641  #define CPUID_VME  (1U << 1)
642  #define CPUID_DE   (1U << 2)
643  #define CPUID_PSE  (1U << 3)
644  #define CPUID_TSC  (1U << 4)
645  #define CPUID_MSR  (1U << 5)
646  #define CPUID_PAE  (1U << 6)
647  #define CPUID_MCE  (1U << 7)
648  #define CPUID_CX8  (1U << 8)
649  #define CPUID_APIC (1U << 9)
650  #define CPUID_SEP  (1U << 11) /* sysenter/sysexit */
651  #define CPUID_MTRR (1U << 12)
652  #define CPUID_PGE  (1U << 13)
653  #define CPUID_MCA  (1U << 14)
654  #define CPUID_CMOV (1U << 15)
655  #define CPUID_PAT  (1U << 16)
656  #define CPUID_PSE36   (1U << 17)
657  #define CPUID_PN   (1U << 18)
658  #define CPUID_CLFLUSH (1U << 19)
659  #define CPUID_DTS (1U << 21)
660  #define CPUID_ACPI (1U << 22)
661  #define CPUID_MMX  (1U << 23)
662  #define CPUID_FXSR (1U << 24)
663  #define CPUID_SSE  (1U << 25)
664  #define CPUID_SSE2 (1U << 26)
665  #define CPUID_SS (1U << 27)
666  #define CPUID_HT (1U << 28)
667  #define CPUID_TM (1U << 29)
668  #define CPUID_IA64 (1U << 30)
669  #define CPUID_PBE (1U << 31)
670  
671  #define CPUID_EXT_SSE3     (1U << 0)
672  #define CPUID_EXT_PCLMULQDQ (1U << 1)
673  #define CPUID_EXT_DTES64   (1U << 2)
674  #define CPUID_EXT_MONITOR  (1U << 3)
675  #define CPUID_EXT_DSCPL    (1U << 4)
676  #define CPUID_EXT_VMX      (1U << 5)
677  #define CPUID_EXT_SMX      (1U << 6)
678  #define CPUID_EXT_EST      (1U << 7)
679  #define CPUID_EXT_TM2      (1U << 8)
680  #define CPUID_EXT_SSSE3    (1U << 9)
681  #define CPUID_EXT_CID      (1U << 10)
682  #define CPUID_EXT_FMA      (1U << 12)
683  #define CPUID_EXT_CX16     (1U << 13)
684  #define CPUID_EXT_XTPR     (1U << 14)
685  #define CPUID_EXT_PDCM     (1U << 15)
686  #define CPUID_EXT_PCID     (1U << 17)
687  #define CPUID_EXT_DCA      (1U << 18)
688  #define CPUID_EXT_SSE41    (1U << 19)
689  #define CPUID_EXT_SSE42    (1U << 20)
690  #define CPUID_EXT_X2APIC   (1U << 21)
691  #define CPUID_EXT_MOVBE    (1U << 22)
692  #define CPUID_EXT_POPCNT   (1U << 23)
693  #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
694  #define CPUID_EXT_AES      (1U << 25)
695  #define CPUID_EXT_XSAVE    (1U << 26)
696  #define CPUID_EXT_OSXSAVE  (1U << 27)
697  #define CPUID_EXT_AVX      (1U << 28)
698  #define CPUID_EXT_F16C     (1U << 29)
699  #define CPUID_EXT_RDRAND   (1U << 30)
700  #define CPUID_EXT_HYPERVISOR  (1U << 31)
701  
702  #define CPUID_EXT2_FPU     (1U << 0)
703  #define CPUID_EXT2_VME     (1U << 1)
704  #define CPUID_EXT2_DE      (1U << 2)
705  #define CPUID_EXT2_PSE     (1U << 3)
706  #define CPUID_EXT2_TSC     (1U << 4)
707  #define CPUID_EXT2_MSR     (1U << 5)
708  #define CPUID_EXT2_PAE     (1U << 6)
709  #define CPUID_EXT2_MCE     (1U << 7)
710  #define CPUID_EXT2_CX8     (1U << 8)
711  #define CPUID_EXT2_APIC    (1U << 9)
712  #define CPUID_EXT2_SYSCALL (1U << 11)
713  #define CPUID_EXT2_MTRR    (1U << 12)
714  #define CPUID_EXT2_PGE     (1U << 13)
715  #define CPUID_EXT2_MCA     (1U << 14)
716  #define CPUID_EXT2_CMOV    (1U << 15)
717  #define CPUID_EXT2_PAT     (1U << 16)
718  #define CPUID_EXT2_PSE36   (1U << 17)
719  #define CPUID_EXT2_MP      (1U << 19)
720  #define CPUID_EXT2_NX      (1U << 20)
721  #define CPUID_EXT2_MMXEXT  (1U << 22)
722  #define CPUID_EXT2_MMX     (1U << 23)
723  #define CPUID_EXT2_FXSR    (1U << 24)
724  #define CPUID_EXT2_FFXSR   (1U << 25)
725  #define CPUID_EXT2_PDPE1GB (1U << 26)
726  #define CPUID_EXT2_RDTSCP  (1U << 27)
727  #define CPUID_EXT2_LM      (1U << 29)
728  #define CPUID_EXT2_3DNOWEXT (1U << 30)
729  #define CPUID_EXT2_3DNOW   (1U << 31)
730  
731  /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */
732  #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
733                                  CPUID_EXT2_DE | CPUID_EXT2_PSE | \
734                                  CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
735                                  CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
736                                  CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
737                                  CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
738                                  CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
739                                  CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
740                                  CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
741  
742  #define CPUID_EXT3_LAHF_LM (1U << 0)
743  #define CPUID_EXT3_CMP_LEG (1U << 1)
744  #define CPUID_EXT3_SVM     (1U << 2)
745  #define CPUID_EXT3_EXTAPIC (1U << 3)
746  #define CPUID_EXT3_CR8LEG  (1U << 4)
747  #define CPUID_EXT3_ABM     (1U << 5)
748  #define CPUID_EXT3_SSE4A   (1U << 6)
749  #define CPUID_EXT3_MISALIGNSSE (1U << 7)
750  #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
751  #define CPUID_EXT3_OSVW    (1U << 9)
752  #define CPUID_EXT3_IBS     (1U << 10)
753  #define CPUID_EXT3_XOP     (1U << 11)
754  #define CPUID_EXT3_SKINIT  (1U << 12)
755  #define CPUID_EXT3_WDT     (1U << 13)
756  #define CPUID_EXT3_LWP     (1U << 15)
757  #define CPUID_EXT3_FMA4    (1U << 16)
758  #define CPUID_EXT3_TCE     (1U << 17)
759  #define CPUID_EXT3_NODEID  (1U << 19)
760  #define CPUID_EXT3_TBM     (1U << 21)
761  #define CPUID_EXT3_TOPOEXT (1U << 22)
762  #define CPUID_EXT3_PERFCORE (1U << 23)
763  #define CPUID_EXT3_PERFNB  (1U << 24)
764  
765  #define CPUID_SVM_NPT             (1U << 0)
766  #define CPUID_SVM_LBRV            (1U << 1)
767  #define CPUID_SVM_SVMLOCK         (1U << 2)
768  #define CPUID_SVM_NRIPSAVE        (1U << 3)
769  #define CPUID_SVM_TSCSCALE        (1U << 4)
770  #define CPUID_SVM_VMCBCLEAN       (1U << 5)
771  #define CPUID_SVM_FLUSHASID       (1U << 6)
772  #define CPUID_SVM_DECODEASSIST    (1U << 7)
773  #define CPUID_SVM_PAUSEFILTER     (1U << 10)
774  #define CPUID_SVM_PFTHRESHOLD     (1U << 12)
775  #define CPUID_SVM_AVIC            (1U << 13)
776  #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
777  #define CPUID_SVM_VGIF            (1U << 16)
778  #define CPUID_SVM_VNMI            (1U << 25)
779  #define CPUID_SVM_SVME_ADDR_CHK   (1U << 28)
780  
781  /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
782  #define CPUID_7_0_EBX_FSGSBASE          (1U << 0)
783  /* Support SGX */
784  #define CPUID_7_0_EBX_SGX               (1U << 2)
785  /* 1st Group of Advanced Bit Manipulation Extensions */
786  #define CPUID_7_0_EBX_BMI1              (1U << 3)
787  /* Hardware Lock Elision */
788  #define CPUID_7_0_EBX_HLE               (1U << 4)
789  /* Intel Advanced Vector Extensions 2 */
790  #define CPUID_7_0_EBX_AVX2              (1U << 5)
791  /* Supervisor-mode Execution Prevention */
792  #define CPUID_7_0_EBX_SMEP              (1U << 7)
793  /* 2nd Group of Advanced Bit Manipulation Extensions */
794  #define CPUID_7_0_EBX_BMI2              (1U << 8)
795  /* Enhanced REP MOVSB/STOSB */
796  #define CPUID_7_0_EBX_ERMS              (1U << 9)
797  /* Invalidate Process-Context Identifier */
798  #define CPUID_7_0_EBX_INVPCID           (1U << 10)
799  /* Restricted Transactional Memory */
800  #define CPUID_7_0_EBX_RTM               (1U << 11)
801  /* Memory Protection Extension */
802  #define CPUID_7_0_EBX_MPX               (1U << 14)
803  /* AVX-512 Foundation */
804  #define CPUID_7_0_EBX_AVX512F           (1U << 16)
805  /* AVX-512 Doubleword & Quadword Instruction */
806  #define CPUID_7_0_EBX_AVX512DQ          (1U << 17)
807  /* Read Random SEED */
808  #define CPUID_7_0_EBX_RDSEED            (1U << 18)
809  /* ADCX and ADOX instructions */
810  #define CPUID_7_0_EBX_ADX               (1U << 19)
811  /* Supervisor Mode Access Prevention */
812  #define CPUID_7_0_EBX_SMAP              (1U << 20)
813  /* AVX-512 Integer Fused Multiply Add */
814  #define CPUID_7_0_EBX_AVX512IFMA        (1U << 21)
815  /* Persistent Commit */
816  #define CPUID_7_0_EBX_PCOMMIT           (1U << 22)
817  /* Flush a Cache Line Optimized */
818  #define CPUID_7_0_EBX_CLFLUSHOPT        (1U << 23)
819  /* Cache Line Write Back */
820  #define CPUID_7_0_EBX_CLWB              (1U << 24)
821  /* Intel Processor Trace */
822  #define CPUID_7_0_EBX_INTEL_PT          (1U << 25)
823  /* AVX-512 Prefetch */
824  #define CPUID_7_0_EBX_AVX512PF          (1U << 26)
825  /* AVX-512 Exponential and Reciprocal */
826  #define CPUID_7_0_EBX_AVX512ER          (1U << 27)
827  /* AVX-512 Conflict Detection */
828  #define CPUID_7_0_EBX_AVX512CD          (1U << 28)
829  /* SHA1/SHA256 Instruction Extensions */
830  #define CPUID_7_0_EBX_SHA_NI            (1U << 29)
831  /* AVX-512 Byte and Word Instructions */
832  #define CPUID_7_0_EBX_AVX512BW          (1U << 30)
833  /* AVX-512 Vector Length Extensions */
834  #define CPUID_7_0_EBX_AVX512VL          (1U << 31)
835  
836  /* AVX-512 Vector Byte Manipulation Instruction */
837  #define CPUID_7_0_ECX_AVX512_VBMI       (1U << 1)
838  /* User-Mode Instruction Prevention */
839  #define CPUID_7_0_ECX_UMIP              (1U << 2)
840  /* Protection Keys for User-mode Pages */
841  #define CPUID_7_0_ECX_PKU               (1U << 3)
842  /* OS Enable Protection Keys */
843  #define CPUID_7_0_ECX_OSPKE             (1U << 4)
844  /* UMONITOR/UMWAIT/TPAUSE Instructions */
845  #define CPUID_7_0_ECX_WAITPKG           (1U << 5)
846  /* Additional AVX-512 Vector Byte Manipulation Instruction */
847  #define CPUID_7_0_ECX_AVX512_VBMI2      (1U << 6)
848  /* Galois Field New Instructions */
849  #define CPUID_7_0_ECX_GFNI              (1U << 8)
850  /* Vector AES Instructions */
851  #define CPUID_7_0_ECX_VAES              (1U << 9)
852  /* Carry-Less Multiplication Quadword */
853  #define CPUID_7_0_ECX_VPCLMULQDQ        (1U << 10)
854  /* Vector Neural Network Instructions */
855  #define CPUID_7_0_ECX_AVX512VNNI        (1U << 11)
856  /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
857  #define CPUID_7_0_ECX_AVX512BITALG      (1U << 12)
858  /* POPCNT for vectors of DW/QW */
859  #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ  (1U << 14)
860  /* 5-level Page Tables */
861  #define CPUID_7_0_ECX_LA57              (1U << 16)
862  /* Read Processor ID */
863  #define CPUID_7_0_ECX_RDPID             (1U << 22)
864  /* Bus Lock Debug Exception */
865  #define CPUID_7_0_ECX_BUS_LOCK_DETECT   (1U << 24)
866  /* Cache Line Demote Instruction */
867  #define CPUID_7_0_ECX_CLDEMOTE          (1U << 25)
868  /* Move Doubleword as Direct Store Instruction */
869  #define CPUID_7_0_ECX_MOVDIRI           (1U << 27)
870  /* Move 64 Bytes as Direct Store Instruction */
871  #define CPUID_7_0_ECX_MOVDIR64B         (1U << 28)
872  /* Support SGX Launch Control */
873  #define CPUID_7_0_ECX_SGX_LC            (1U << 30)
874  /* Protection Keys for Supervisor-mode Pages */
875  #define CPUID_7_0_ECX_PKS               (1U << 31)
876  
877  /* AVX512 Neural Network Instructions */
878  #define CPUID_7_0_EDX_AVX512_4VNNIW     (1U << 2)
879  /* AVX512 Multiply Accumulation Single Precision */
880  #define CPUID_7_0_EDX_AVX512_4FMAPS     (1U << 3)
881  /* Fast Short Rep Mov */
882  #define CPUID_7_0_EDX_FSRM              (1U << 4)
883  /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
884  #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
885  /* SERIALIZE instruction */
886  #define CPUID_7_0_EDX_SERIALIZE         (1U << 14)
887  /* TSX Suspend Load Address Tracking instruction */
888  #define CPUID_7_0_EDX_TSX_LDTRK         (1U << 16)
889  /* Architectural LBRs */
890  #define CPUID_7_0_EDX_ARCH_LBR          (1U << 19)
891  /* AMX_BF16 instruction */
892  #define CPUID_7_0_EDX_AMX_BF16          (1U << 22)
893  /* AVX512_FP16 instruction */
894  #define CPUID_7_0_EDX_AVX512_FP16       (1U << 23)
895  /* AMX tile (two-dimensional register) */
896  #define CPUID_7_0_EDX_AMX_TILE          (1U << 24)
897  /* AMX_INT8 instruction */
898  #define CPUID_7_0_EDX_AMX_INT8          (1U << 25)
899  /* Speculation Control */
900  #define CPUID_7_0_EDX_SPEC_CTRL         (1U << 26)
901  /* Single Thread Indirect Branch Predictors */
902  #define CPUID_7_0_EDX_STIBP             (1U << 27)
903  /* Flush L1D cache */
904  #define CPUID_7_0_EDX_FLUSH_L1D         (1U << 28)
905  /* Arch Capabilities */
906  #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
907  /* Core Capability */
908  #define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)
909  /* Speculative Store Bypass Disable */
910  #define CPUID_7_0_EDX_SPEC_CTRL_SSBD    (1U << 31)
911  
912  /* AVX VNNI Instruction */
913  #define CPUID_7_1_EAX_AVX_VNNI          (1U << 4)
914  /* AVX512 BFloat16 Instruction */
915  #define CPUID_7_1_EAX_AVX512_BF16       (1U << 5)
916  /* CMPCCXADD Instructions */
917  #define CPUID_7_1_EAX_CMPCCXADD         (1U << 7)
918  /* Fast Zero REP MOVS */
919  #define CPUID_7_1_EAX_FZRM              (1U << 10)
920  /* Fast Short REP STOS */
921  #define CPUID_7_1_EAX_FSRS              (1U << 11)
922  /* Fast Short REP CMPS/SCAS */
923  #define CPUID_7_1_EAX_FSRC              (1U << 12)
924  /* Support Tile Computational Operations on FP16 Numbers */
925  #define CPUID_7_1_EAX_AMX_FP16          (1U << 21)
926  /* Support for VPMADD52[H,L]UQ */
927  #define CPUID_7_1_EAX_AVX_IFMA          (1U << 23)
928  
929  /* Support for VPDPB[SU,UU,SS]D[,S] */
930  #define CPUID_7_1_EDX_AVX_VNNI_INT8     (1U << 4)
931  /* AVX NE CONVERT Instructions */
932  #define CPUID_7_1_EDX_AVX_NE_CONVERT    (1U << 5)
933  /* AMX COMPLEX Instructions */
934  #define CPUID_7_1_EDX_AMX_COMPLEX       (1U << 8)
935  /* PREFETCHIT0/1 Instructions */
936  #define CPUID_7_1_EDX_PREFETCHITI       (1U << 14)
937  
938  /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
939  #define CPUID_7_2_EDX_MCDT_NO           (1U << 5)
940  
941  /* XFD Extend Feature Disabled */
942  #define CPUID_D_1_EAX_XFD               (1U << 4)
943  
944  /* Packets which contain IP payload have LIP values */
945  #define CPUID_14_0_ECX_LIP              (1U << 31)
946  
947  /* CLZERO instruction */
948  #define CPUID_8000_0008_EBX_CLZERO      (1U << 0)
949  /* Always save/restore FP error pointers */
950  #define CPUID_8000_0008_EBX_XSAVEERPTR  (1U << 2)
951  /* Write back and do not invalidate cache */
952  #define CPUID_8000_0008_EBX_WBNOINVD    (1U << 9)
953  /* Indirect Branch Prediction Barrier */
954  #define CPUID_8000_0008_EBX_IBPB        (1U << 12)
955  /* Indirect Branch Restricted Speculation */
956  #define CPUID_8000_0008_EBX_IBRS        (1U << 14)
957  /* Single Thread Indirect Branch Predictors */
958  #define CPUID_8000_0008_EBX_STIBP       (1U << 15)
959  /* STIBP mode has enhanced performance and may be left always on */
960  #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON    (1U << 17)
961  /* Speculative Store Bypass Disable */
962  #define CPUID_8000_0008_EBX_AMD_SSBD    (1U << 24)
963  /* Predictive Store Forwarding Disable */
964  #define CPUID_8000_0008_EBX_AMD_PSFD    (1U << 28)
965  
966  /* Processor ignores nested data breakpoints */
967  #define CPUID_8000_0021_EAX_No_NESTED_DATA_BP    (1U << 0)
968  /* LFENCE is always serializing */
969  #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING    (1U << 2)
970  /* Null Selector Clears Base */
971  #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE    (1U << 6)
972  /* Automatic IBRS */
973  #define CPUID_8000_0021_EAX_AUTO_IBRS   (1U << 8)
974  
975  #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
976  #define CPUID_XSAVE_XSAVEC     (1U << 1)
977  #define CPUID_XSAVE_XGETBV1    (1U << 2)
978  #define CPUID_XSAVE_XSAVES     (1U << 3)
979  
980  #define CPUID_6_EAX_ARAT       (1U << 2)
981  
982  /* CPUID[0x80000007].EDX flags: */
983  #define CPUID_APM_INVTSC       (1U << 8)
984  
985  #define CPUID_VENDOR_SZ      12
986  
987  #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
988  #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
989  #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
990  #define CPUID_VENDOR_INTEL "GenuineIntel"
991  
992  #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
993  #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
994  #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
995  #define CPUID_VENDOR_AMD   "AuthenticAMD"
996  
997  #define CPUID_VENDOR_VIA   "CentaurHauls"
998  
999  #define CPUID_VENDOR_HYGON    "HygonGenuine"
1000  
1001  #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
1002                             (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
1003                             (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
1004  #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
1005                           (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
1006                           (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
1007  
1008  #define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
1009  #define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
1010  
1011  /* CPUID[0xB].ECX level types */
1012  #define CPUID_TOPOLOGY_LEVEL_INVALID  (0U << 8)
1013  #define CPUID_TOPOLOGY_LEVEL_SMT      (1U << 8)
1014  #define CPUID_TOPOLOGY_LEVEL_CORE     (2U << 8)
1015  #define CPUID_TOPOLOGY_LEVEL_DIE      (5U << 8)
1016  
1017  /* MSR Feature Bits */
1018  #define MSR_ARCH_CAP_RDCL_NO            (1U << 0)
1019  #define MSR_ARCH_CAP_IBRS_ALL           (1U << 1)
1020  #define MSR_ARCH_CAP_RSBA               (1U << 2)
1021  #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1022  #define MSR_ARCH_CAP_SSB_NO             (1U << 4)
1023  #define MSR_ARCH_CAP_MDS_NO             (1U << 5)
1024  #define MSR_ARCH_CAP_PSCHANGE_MC_NO     (1U << 6)
1025  #define MSR_ARCH_CAP_TSX_CTRL_MSR       (1U << 7)
1026  #define MSR_ARCH_CAP_TAA_NO             (1U << 8)
1027  #define MSR_ARCH_CAP_SBDR_SSDP_NO       (1U << 13)
1028  #define MSR_ARCH_CAP_FBSDP_NO           (1U << 14)
1029  #define MSR_ARCH_CAP_PSDP_NO            (1U << 15)
1030  #define MSR_ARCH_CAP_FB_CLEAR           (1U << 17)
1031  #define MSR_ARCH_CAP_PBRSB_NO           (1U << 24)
1032  
1033  #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
1034  
1035  /* VMX MSR features */
1036  #define MSR_VMX_BASIC_VMCS_REVISION_MASK             0x7FFFFFFFull
1037  #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK         (0x00001FFFull << 32)
1038  #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK             (0x003C0000ull << 32)
1039  #define MSR_VMX_BASIC_DUAL_MONITOR                   (1ULL << 49)
1040  #define MSR_VMX_BASIC_INS_OUTS                       (1ULL << 54)
1041  #define MSR_VMX_BASIC_TRUE_CTLS                      (1ULL << 55)
1042  #define MSR_VMX_BASIC_ANY_ERRCODE                    (1ULL << 56)
1043  
1044  #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK     0x1Full
1045  #define MSR_VMX_MISC_STORE_LMA                       (1ULL << 5)
1046  #define MSR_VMX_MISC_ACTIVITY_HLT                    (1ULL << 6)
1047  #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN               (1ULL << 7)
1048  #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI              (1ULL << 8)
1049  #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK          0x0E000000ull
1050  #define MSR_VMX_MISC_VMWRITE_VMEXIT                  (1ULL << 29)
1051  #define MSR_VMX_MISC_ZERO_LEN_INJECT                 (1ULL << 30)
1052  
1053  #define MSR_VMX_EPT_EXECONLY                         (1ULL << 0)
1054  #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4               (1ULL << 6)
1055  #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5               (1ULL << 7)
1056  #define MSR_VMX_EPT_UC                               (1ULL << 8)
1057  #define MSR_VMX_EPT_WB                               (1ULL << 14)
1058  #define MSR_VMX_EPT_2MB                              (1ULL << 16)
1059  #define MSR_VMX_EPT_1GB                              (1ULL << 17)
1060  #define MSR_VMX_EPT_INVEPT                           (1ULL << 20)
1061  #define MSR_VMX_EPT_AD_BITS                          (1ULL << 21)
1062  #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO             (1ULL << 22)
1063  #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT            (1ULL << 25)
1064  #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT               (1ULL << 26)
1065  #define MSR_VMX_EPT_INVVPID                          (1ULL << 32)
1066  #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR              (1ULL << 40)
1067  #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT           (1ULL << 41)
1068  #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT              (1ULL << 42)
1069  #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1070  
1071  #define MSR_VMX_VMFUNC_EPT_SWITCHING                 (1ULL << 0)
1072  
1073  
1074  /* VMX controls */
1075  #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
1076  #define VMX_CPU_BASED_USE_TSC_OFFSETING             0x00000008
1077  #define VMX_CPU_BASED_HLT_EXITING                   0x00000080
1078  #define VMX_CPU_BASED_INVLPG_EXITING                0x00000200
1079  #define VMX_CPU_BASED_MWAIT_EXITING                 0x00000400
1080  #define VMX_CPU_BASED_RDPMC_EXITING                 0x00000800
1081  #define VMX_CPU_BASED_RDTSC_EXITING                 0x00001000
1082  #define VMX_CPU_BASED_CR3_LOAD_EXITING              0x00008000
1083  #define VMX_CPU_BASED_CR3_STORE_EXITING             0x00010000
1084  #define VMX_CPU_BASED_CR8_LOAD_EXITING              0x00080000
1085  #define VMX_CPU_BASED_CR8_STORE_EXITING             0x00100000
1086  #define VMX_CPU_BASED_TPR_SHADOW                    0x00200000
1087  #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
1088  #define VMX_CPU_BASED_MOV_DR_EXITING                0x00800000
1089  #define VMX_CPU_BASED_UNCOND_IO_EXITING             0x01000000
1090  #define VMX_CPU_BASED_USE_IO_BITMAPS                0x02000000
1091  #define VMX_CPU_BASED_MONITOR_TRAP_FLAG             0x08000000
1092  #define VMX_CPU_BASED_USE_MSR_BITMAPS               0x10000000
1093  #define VMX_CPU_BASED_MONITOR_EXITING               0x20000000
1094  #define VMX_CPU_BASED_PAUSE_EXITING                 0x40000000
1095  #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
1096  
1097  #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1098  #define VMX_SECONDARY_EXEC_ENABLE_EPT               0x00000002
1099  #define VMX_SECONDARY_EXEC_DESC                     0x00000004
1100  #define VMX_SECONDARY_EXEC_RDTSCP                   0x00000008
1101  #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
1102  #define VMX_SECONDARY_EXEC_ENABLE_VPID              0x00000020
1103  #define VMX_SECONDARY_EXEC_WBINVD_EXITING           0x00000040
1104  #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
1105  #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
1106  #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
1107  #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
1108  #define VMX_SECONDARY_EXEC_RDRAND_EXITING           0x00000800
1109  #define VMX_SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
1110  #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC            0x00002000
1111  #define VMX_SECONDARY_EXEC_SHADOW_VMCS              0x00004000
1112  #define VMX_SECONDARY_EXEC_ENCLS_EXITING            0x00008000
1113  #define VMX_SECONDARY_EXEC_RDSEED_EXITING           0x00010000
1114  #define VMX_SECONDARY_EXEC_ENABLE_PML               0x00020000
1115  #define VMX_SECONDARY_EXEC_XSAVES                   0x00100000
1116  #define VMX_SECONDARY_EXEC_TSC_SCALING              0x02000000
1117  #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE   0x04000000
1118  
1119  #define VMX_PIN_BASED_EXT_INTR_MASK                 0x00000001
1120  #define VMX_PIN_BASED_NMI_EXITING                   0x00000008
1121  #define VMX_PIN_BASED_VIRTUAL_NMIS                  0x00000020
1122  #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
1123  #define VMX_PIN_BASED_POSTED_INTR                   0x00000080
1124  
1125  #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
1126  #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
1127  #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
1128  #define VMX_VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
1129  #define VMX_VM_EXIT_SAVE_IA32_PAT                   0x00040000
1130  #define VMX_VM_EXIT_LOAD_IA32_PAT                   0x00080000
1131  #define VMX_VM_EXIT_SAVE_IA32_EFER                  0x00100000
1132  #define VMX_VM_EXIT_LOAD_IA32_EFER                  0x00200000
1133  #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
1134  #define VMX_VM_EXIT_CLEAR_BNDCFGS                   0x00800000
1135  #define VMX_VM_EXIT_PT_CONCEAL_PIP                  0x01000000
1136  #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL             0x02000000
1137  #define VMX_VM_EXIT_LOAD_IA32_PKRS                  0x20000000
1138  
1139  #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
1140  #define VMX_VM_ENTRY_IA32E_MODE                     0x00000200
1141  #define VMX_VM_ENTRY_SMM                            0x00000400
1142  #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
1143  #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
1144  #define VMX_VM_ENTRY_LOAD_IA32_PAT                  0x00004000
1145  #define VMX_VM_ENTRY_LOAD_IA32_EFER                 0x00008000
1146  #define VMX_VM_ENTRY_LOAD_BNDCFGS                   0x00010000
1147  #define VMX_VM_ENTRY_PT_CONCEAL_PIP                 0x00020000
1148  #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL             0x00040000
1149  #define VMX_VM_ENTRY_LOAD_IA32_PKRS                 0x00400000
1150  
1151  /* Supported Hyper-V Enlightenments */
1152  #define HYPERV_FEAT_RELAXED             0
1153  #define HYPERV_FEAT_VAPIC               1
1154  #define HYPERV_FEAT_TIME                2
1155  #define HYPERV_FEAT_CRASH               3
1156  #define HYPERV_FEAT_RESET               4
1157  #define HYPERV_FEAT_VPINDEX             5
1158  #define HYPERV_FEAT_RUNTIME             6
1159  #define HYPERV_FEAT_SYNIC               7
1160  #define HYPERV_FEAT_STIMER              8
1161  #define HYPERV_FEAT_FREQUENCIES         9
1162  #define HYPERV_FEAT_REENLIGHTENMENT     10
1163  #define HYPERV_FEAT_TLBFLUSH            11
1164  #define HYPERV_FEAT_EVMCS               12
1165  #define HYPERV_FEAT_IPI                 13
1166  #define HYPERV_FEAT_STIMER_DIRECT       14
1167  #define HYPERV_FEAT_AVIC                15
1168  #define HYPERV_FEAT_SYNDBG              16
1169  #define HYPERV_FEAT_MSR_BITMAP          17
1170  #define HYPERV_FEAT_XMM_INPUT           18
1171  #define HYPERV_FEAT_TLBFLUSH_EXT        19
1172  #define HYPERV_FEAT_TLBFLUSH_DIRECT     20
1173  
1174  #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1175  #define HYPERV_SPINLOCK_NEVER_NOTIFY             0xFFFFFFFF
1176  #endif
1177  
1178  #define EXCP00_DIVZ	0
1179  #define EXCP01_DB	1
1180  #define EXCP02_NMI	2
1181  #define EXCP03_INT3	3
1182  #define EXCP04_INTO	4
1183  #define EXCP05_BOUND	5
1184  #define EXCP06_ILLOP	6
1185  #define EXCP07_PREX	7
1186  #define EXCP08_DBLE	8
1187  #define EXCP09_XERR	9
1188  #define EXCP0A_TSS	10
1189  #define EXCP0B_NOSEG	11
1190  #define EXCP0C_STACK	12
1191  #define EXCP0D_GPF	13
1192  #define EXCP0E_PAGE	14
1193  #define EXCP10_COPR	16
1194  #define EXCP11_ALGN	17
1195  #define EXCP12_MCHK	18
1196  
1197  #define EXCP_VMEXIT     0x100 /* only for system emulation */
1198  #define EXCP_SYSCALL    0x101 /* only for user emulation */
1199  #define EXCP_VSYSCALL   0x102 /* only for user emulation */
1200  
1201  /* i386-specific interrupt pending bits.  */
1202  #define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
1203  #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
1204  #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
1205  #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
1206  #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
1207  #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_1
1208  #define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_2
1209  
1210  /* Use a clearer name for this.  */
1211  #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_RESET
1212  
1213  /* Instead of computing the condition codes after each x86 instruction,
1214   * QEMU just stores one operand (called CC_SRC), the result
1215   * (called CC_DST) and the type of operation (called CC_OP). When the
1216   * condition codes are needed, the condition codes can be calculated
1217   * using this information. Condition codes are not generated if they
1218   * are only needed for conditional branches.
1219   */
1220  typedef enum {
1221      CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1222      CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
1223  
1224      CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
1225      CC_OP_MULW,
1226      CC_OP_MULL,
1227      CC_OP_MULQ,
1228  
1229      CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1230      CC_OP_ADDW,
1231      CC_OP_ADDL,
1232      CC_OP_ADDQ,
1233  
1234      CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1235      CC_OP_ADCW,
1236      CC_OP_ADCL,
1237      CC_OP_ADCQ,
1238  
1239      CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1240      CC_OP_SUBW,
1241      CC_OP_SUBL,
1242      CC_OP_SUBQ,
1243  
1244      CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1245      CC_OP_SBBW,
1246      CC_OP_SBBL,
1247      CC_OP_SBBQ,
1248  
1249      CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1250      CC_OP_LOGICW,
1251      CC_OP_LOGICL,
1252      CC_OP_LOGICQ,
1253  
1254      CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1255      CC_OP_INCW,
1256      CC_OP_INCL,
1257      CC_OP_INCQ,
1258  
1259      CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
1260      CC_OP_DECW,
1261      CC_OP_DECL,
1262      CC_OP_DECQ,
1263  
1264      CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1265      CC_OP_SHLW,
1266      CC_OP_SHLL,
1267      CC_OP_SHLQ,
1268  
1269      CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1270      CC_OP_SARW,
1271      CC_OP_SARL,
1272      CC_OP_SARQ,
1273  
1274      CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1275      CC_OP_BMILGW,
1276      CC_OP_BMILGL,
1277      CC_OP_BMILGQ,
1278  
1279      CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest.  */
1280      CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest.  */
1281      CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */
1282  
1283      CC_OP_CLR, /* Z set, all other flags clear.  */
1284      CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear.  */
1285  
1286      CC_OP_NB,
1287  } CCOp;
1288  QEMU_BUILD_BUG_ON(CC_OP_NB >= 128);
1289  
1290  typedef struct SegmentCache {
1291      uint32_t selector;
1292      target_ulong base;
1293      uint32_t limit;
1294      uint32_t flags;
1295  } SegmentCache;
1296  
1297  typedef union MMXReg {
1298      uint8_t  _b_MMXReg[64 / 8];
1299      uint16_t _w_MMXReg[64 / 16];
1300      uint32_t _l_MMXReg[64 / 32];
1301      uint64_t _q_MMXReg[64 / 64];
1302      float32  _s_MMXReg[64 / 32];
1303      float64  _d_MMXReg[64 / 64];
1304  } MMXReg;
1305  
1306  typedef union XMMReg {
1307      uint64_t _q_XMMReg[128 / 64];
1308  } XMMReg;
1309  
1310  typedef union YMMReg {
1311      uint64_t _q_YMMReg[256 / 64];
1312      XMMReg   _x_YMMReg[256 / 128];
1313  } YMMReg;
1314  
1315  typedef union ZMMReg {
1316      uint8_t  _b_ZMMReg[512 / 8];
1317      uint16_t _w_ZMMReg[512 / 16];
1318      uint32_t _l_ZMMReg[512 / 32];
1319      uint64_t _q_ZMMReg[512 / 64];
1320      float16  _h_ZMMReg[512 / 16];
1321      float32  _s_ZMMReg[512 / 32];
1322      float64  _d_ZMMReg[512 / 64];
1323      XMMReg   _x_ZMMReg[512 / 128];
1324      YMMReg   _y_ZMMReg[512 / 256];
1325  } ZMMReg;
1326  
1327  typedef struct BNDReg {
1328      uint64_t lb;
1329      uint64_t ub;
1330  } BNDReg;
1331  
1332  typedef struct BNDCSReg {
1333      uint64_t cfgu;
1334      uint64_t sts;
1335  } BNDCSReg;
1336  
1337  #define BNDCFG_ENABLE       1ULL
1338  #define BNDCFG_BNDPRESERVE  2ULL
1339  #define BNDCFG_BDIR_MASK    TARGET_PAGE_MASK
1340  
1341  #if HOST_BIG_ENDIAN
1342  #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1343  #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1344  #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1345  #define ZMM_H(n) _h_ZMMReg[31 - (n)]
1346  #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1347  #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1348  #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1349  #define ZMM_X(n) _x_ZMMReg[3 - (n)]
1350  #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1351  
1352  #define XMM_Q(n) _q_XMMReg[1 - (n)]
1353  
1354  #define YMM_Q(n) _q_YMMReg[3 - (n)]
1355  #define YMM_X(n) _x_YMMReg[1 - (n)]
1356  
1357  #define MMX_B(n) _b_MMXReg[7 - (n)]
1358  #define MMX_W(n) _w_MMXReg[3 - (n)]
1359  #define MMX_L(n) _l_MMXReg[1 - (n)]
1360  #define MMX_S(n) _s_MMXReg[1 - (n)]
1361  #else
1362  #define ZMM_B(n) _b_ZMMReg[n]
1363  #define ZMM_W(n) _w_ZMMReg[n]
1364  #define ZMM_L(n) _l_ZMMReg[n]
1365  #define ZMM_H(n) _h_ZMMReg[n]
1366  #define ZMM_S(n) _s_ZMMReg[n]
1367  #define ZMM_Q(n) _q_ZMMReg[n]
1368  #define ZMM_D(n) _d_ZMMReg[n]
1369  #define ZMM_X(n) _x_ZMMReg[n]
1370  #define ZMM_Y(n) _y_ZMMReg[n]
1371  
1372  #define XMM_Q(n) _q_XMMReg[n]
1373  
1374  #define YMM_Q(n) _q_YMMReg[n]
1375  #define YMM_X(n) _x_YMMReg[n]
1376  
1377  #define MMX_B(n) _b_MMXReg[n]
1378  #define MMX_W(n) _w_MMXReg[n]
1379  #define MMX_L(n) _l_MMXReg[n]
1380  #define MMX_S(n) _s_MMXReg[n]
1381  #endif
1382  #define MMX_Q(n) _q_MMXReg[n]
1383  
1384  typedef union {
1385      floatx80 d __attribute__((aligned(16)));
1386      MMXReg mmx;
1387  } FPReg;
1388  
1389  typedef struct {
1390      uint64_t base;
1391      uint64_t mask;
1392  } MTRRVar;
1393  
1394  #define CPU_NB_REGS64 16
1395  #define CPU_NB_REGS32 8
1396  
1397  #ifdef TARGET_X86_64
1398  #define CPU_NB_REGS CPU_NB_REGS64
1399  #else
1400  #define CPU_NB_REGS CPU_NB_REGS32
1401  #endif
1402  
1403  #define MAX_FIXED_COUNTERS 3
1404  #define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1405  
1406  #define TARGET_INSN_START_EXTRA_WORDS 1
1407  
1408  #define NB_OPMASK_REGS 8
1409  
1410  /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1411   * that APIC ID hasn't been set yet
1412   */
1413  #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1414  
1415  typedef union X86LegacyXSaveArea {
1416      struct {
1417          uint16_t fcw;
1418          uint16_t fsw;
1419          uint8_t ftw;
1420          uint8_t reserved;
1421          uint16_t fpop;
1422          uint64_t fpip;
1423          uint64_t fpdp;
1424          uint32_t mxcsr;
1425          uint32_t mxcsr_mask;
1426          FPReg fpregs[8];
1427          uint8_t xmm_regs[16][16];
1428      };
1429      uint8_t data[512];
1430  } X86LegacyXSaveArea;
1431  
1432  typedef struct X86XSaveHeader {
1433      uint64_t xstate_bv;
1434      uint64_t xcomp_bv;
1435      uint64_t reserve0;
1436      uint8_t reserved[40];
1437  } X86XSaveHeader;
1438  
1439  /* Ext. save area 2: AVX State */
1440  typedef struct XSaveAVX {
1441      uint8_t ymmh[16][16];
1442  } XSaveAVX;
1443  
1444  /* Ext. save area 3: BNDREG */
1445  typedef struct XSaveBNDREG {
1446      BNDReg bnd_regs[4];
1447  } XSaveBNDREG;
1448  
1449  /* Ext. save area 4: BNDCSR */
1450  typedef union XSaveBNDCSR {
1451      BNDCSReg bndcsr;
1452      uint8_t data[64];
1453  } XSaveBNDCSR;
1454  
1455  /* Ext. save area 5: Opmask */
1456  typedef struct XSaveOpmask {
1457      uint64_t opmask_regs[NB_OPMASK_REGS];
1458  } XSaveOpmask;
1459  
1460  /* Ext. save area 6: ZMM_Hi256 */
1461  typedef struct XSaveZMM_Hi256 {
1462      uint8_t zmm_hi256[16][32];
1463  } XSaveZMM_Hi256;
1464  
1465  /* Ext. save area 7: Hi16_ZMM */
1466  typedef struct XSaveHi16_ZMM {
1467      uint8_t hi16_zmm[16][64];
1468  } XSaveHi16_ZMM;
1469  
1470  /* Ext. save area 9: PKRU state */
1471  typedef struct XSavePKRU {
1472      uint32_t pkru;
1473      uint32_t padding;
1474  } XSavePKRU;
1475  
1476  /* Ext. save area 17: AMX XTILECFG state */
1477  typedef struct XSaveXTILECFG {
1478      uint8_t xtilecfg[64];
1479  } XSaveXTILECFG;
1480  
1481  /* Ext. save area 18: AMX XTILEDATA state */
1482  typedef struct XSaveXTILEDATA {
1483      uint8_t xtiledata[8][1024];
1484  } XSaveXTILEDATA;
1485  
1486  typedef struct {
1487         uint64_t from;
1488         uint64_t to;
1489         uint64_t info;
1490  } LBREntry;
1491  
1492  #define ARCH_LBR_NR_ENTRIES            32
1493  
1494  /* Ext. save area 19: Supervisor mode Arch LBR state */
1495  typedef struct XSavesArchLBR {
1496      uint64_t lbr_ctl;
1497      uint64_t lbr_depth;
1498      uint64_t ler_from;
1499      uint64_t ler_to;
1500      uint64_t ler_info;
1501      LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1502  } XSavesArchLBR;
1503  
1504  QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1505  QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1506  QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1507  QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1508  QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1509  QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1510  QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1511  QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1512  QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1513  QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1514  
1515  typedef struct ExtSaveArea {
1516      uint32_t feature, bits;
1517      uint32_t offset, size;
1518      uint32_t ecx;
1519  } ExtSaveArea;
1520  
1521  #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1522  
1523  extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
1524  
1525  typedef enum TPRAccess {
1526      TPR_ACCESS_READ,
1527      TPR_ACCESS_WRITE,
1528  } TPRAccess;
1529  
1530  /* Cache information data structures: */
1531  
1532  enum CacheType {
1533      DATA_CACHE,
1534      INSTRUCTION_CACHE,
1535      UNIFIED_CACHE
1536  };
1537  
1538  typedef struct CPUCacheInfo {
1539      enum CacheType type;
1540      uint8_t level;
1541      /* Size in bytes */
1542      uint32_t size;
1543      /* Line size, in bytes */
1544      uint16_t line_size;
1545      /*
1546       * Associativity.
1547       * Note: representation of fully-associative caches is not implemented
1548       */
1549      uint8_t associativity;
1550      /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1551      uint8_t partitions;
1552      /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1553      uint32_t sets;
1554      /*
1555       * Lines per tag.
1556       * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1557       * (Is this synonym to @partitions?)
1558       */
1559      uint8_t lines_per_tag;
1560  
1561      /* Self-initializing cache */
1562      bool self_init;
1563      /*
1564       * WBINVD/INVD is not guaranteed to act upon lower level caches of
1565       * non-originating threads sharing this cache.
1566       * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1567       */
1568      bool no_invd_sharing;
1569      /*
1570       * Cache is inclusive of lower cache levels.
1571       * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1572       */
1573      bool inclusive;
1574      /*
1575       * A complex function is used to index the cache, potentially using all
1576       * address bits.  CPUID[4].EDX[bit 2].
1577       */
1578      bool complex_indexing;
1579  } CPUCacheInfo;
1580  
1581  
1582  typedef struct CPUCaches {
1583          CPUCacheInfo *l1d_cache;
1584          CPUCacheInfo *l1i_cache;
1585          CPUCacheInfo *l2_cache;
1586          CPUCacheInfo *l3_cache;
1587  } CPUCaches;
1588  
1589  typedef struct HVFX86LazyFlags {
1590      target_ulong result;
1591      target_ulong auxbits;
1592  } HVFX86LazyFlags;
1593  
1594  typedef struct CPUArchState {
1595      /* standard registers */
1596      target_ulong regs[CPU_NB_REGS];
1597      target_ulong eip;
1598      target_ulong eflags; /* eflags register. During CPU emulation, CC
1599                          flags and DF are set to zero because they are
1600                          stored elsewhere */
1601  
1602      /* emulator internal eflags handling */
1603      target_ulong cc_dst;
1604      target_ulong cc_src;
1605      target_ulong cc_src2;
1606      uint32_t cc_op;
1607      int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1608      uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1609                          are known at translation time. */
1610      uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1611  
1612      /* segments */
1613      SegmentCache segs[6]; /* selector values */
1614      SegmentCache ldt;
1615      SegmentCache tr;
1616      SegmentCache gdt; /* only base and limit are used */
1617      SegmentCache idt; /* only base and limit are used */
1618  
1619      target_ulong cr[5]; /* NOTE: cr1 is unused */
1620  
1621      bool pdptrs_valid;
1622      uint64_t pdptrs[4];
1623      int32_t a20_mask;
1624  
1625      BNDReg bnd_regs[4];
1626      BNDCSReg bndcs_regs;
1627      uint64_t msr_bndcfgs;
1628      uint64_t efer;
1629  
1630      /* Beginning of state preserved by INIT (dummy marker).  */
1631      struct {} start_init_save;
1632  
1633      /* FPU state */
1634      unsigned int fpstt; /* top of stack index */
1635      uint16_t fpus;
1636      uint16_t fpuc;
1637      uint8_t fptags[8];   /* 0 = valid, 1 = empty */
1638      FPReg fpregs[8];
1639      /* KVM-only so far */
1640      uint16_t fpop;
1641      uint16_t fpcs;
1642      uint16_t fpds;
1643      uint64_t fpip;
1644      uint64_t fpdp;
1645  
1646      /* emulator internal variables */
1647      float_status fp_status;
1648      floatx80 ft0;
1649  
1650      float_status mmx_status; /* for 3DNow! float ops */
1651      float_status sse_status;
1652      uint32_t mxcsr;
1653      ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
1654      ZMMReg xmm_t0 QEMU_ALIGNED(16);
1655      MMXReg mmx_t0;
1656  
1657      uint64_t opmask_regs[NB_OPMASK_REGS];
1658  #ifdef TARGET_X86_64
1659      uint8_t xtilecfg[64];
1660      uint8_t xtiledata[8192];
1661  #endif
1662  
1663      /* sysenter registers */
1664      uint32_t sysenter_cs;
1665      target_ulong sysenter_esp;
1666      target_ulong sysenter_eip;
1667      uint64_t star;
1668  
1669      uint64_t vm_hsave;
1670  
1671  #ifdef TARGET_X86_64
1672      target_ulong lstar;
1673      target_ulong cstar;
1674      target_ulong fmask;
1675      target_ulong kernelgsbase;
1676  #endif
1677  
1678      uint64_t tsc_adjust;
1679      uint64_t tsc_deadline;
1680      uint64_t tsc_aux;
1681  
1682      uint64_t xcr0;
1683  
1684      uint64_t mcg_status;
1685      uint64_t msr_ia32_misc_enable;
1686      uint64_t msr_ia32_feature_control;
1687      uint64_t msr_ia32_sgxlepubkeyhash[4];
1688  
1689      uint64_t msr_fixed_ctr_ctrl;
1690      uint64_t msr_global_ctrl;
1691      uint64_t msr_global_status;
1692      uint64_t msr_global_ovf_ctrl;
1693      uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1694      uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1695      uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1696  
1697      uint64_t pat;
1698      uint32_t smbase;
1699      uint64_t msr_smi_count;
1700  
1701      uint32_t pkru;
1702      uint32_t pkrs;
1703      uint32_t tsx_ctrl;
1704  
1705      uint64_t spec_ctrl;
1706      uint64_t amd_tsc_scale_msr;
1707      uint64_t virt_ssbd;
1708  
1709      /* End of state preserved by INIT (dummy marker).  */
1710      struct {} end_init_save;
1711  
1712      uint64_t system_time_msr;
1713      uint64_t wall_clock_msr;
1714      uint64_t steal_time_msr;
1715      uint64_t async_pf_en_msr;
1716      uint64_t async_pf_int_msr;
1717      uint64_t pv_eoi_en_msr;
1718      uint64_t poll_control_msr;
1719  
1720      /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1721      uint64_t msr_hv_hypercall;
1722      uint64_t msr_hv_guest_os_id;
1723      uint64_t msr_hv_tsc;
1724      uint64_t msr_hv_syndbg_control;
1725      uint64_t msr_hv_syndbg_status;
1726      uint64_t msr_hv_syndbg_send_page;
1727      uint64_t msr_hv_syndbg_recv_page;
1728      uint64_t msr_hv_syndbg_pending_page;
1729      uint64_t msr_hv_syndbg_options;
1730  
1731      /* Per-VCPU HV MSRs */
1732      uint64_t msr_hv_vapic;
1733      uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1734      uint64_t msr_hv_runtime;
1735      uint64_t msr_hv_synic_control;
1736      uint64_t msr_hv_synic_evt_page;
1737      uint64_t msr_hv_synic_msg_page;
1738      uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1739      uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1740      uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1741      uint64_t msr_hv_reenlightenment_control;
1742      uint64_t msr_hv_tsc_emulation_control;
1743      uint64_t msr_hv_tsc_emulation_status;
1744  
1745      uint64_t msr_rtit_ctrl;
1746      uint64_t msr_rtit_status;
1747      uint64_t msr_rtit_output_base;
1748      uint64_t msr_rtit_output_mask;
1749      uint64_t msr_rtit_cr3_match;
1750      uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1751  
1752      /* Per-VCPU XFD MSRs */
1753      uint64_t msr_xfd;
1754      uint64_t msr_xfd_err;
1755  
1756      /* Per-VCPU Arch LBR MSRs */
1757      uint64_t msr_lbr_ctl;
1758      uint64_t msr_lbr_depth;
1759      LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1760  
1761      /* exception/interrupt handling */
1762      int error_code;
1763      int exception_is_int;
1764      target_ulong exception_next_eip;
1765      target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1766      union {
1767          struct CPUBreakpoint *cpu_breakpoint[4];
1768          struct CPUWatchpoint *cpu_watchpoint[4];
1769      }; /* break/watchpoints for dr[0..3] */
1770      int old_exception;  /* exception in flight */
1771  
1772      uint64_t vm_vmcb;
1773      uint64_t tsc_offset;
1774      uint64_t intercept;
1775      uint16_t intercept_cr_read;
1776      uint16_t intercept_cr_write;
1777      uint16_t intercept_dr_read;
1778      uint16_t intercept_dr_write;
1779      uint32_t intercept_exceptions;
1780      uint64_t nested_cr3;
1781      uint32_t nested_pg_mode;
1782      uint8_t v_tpr;
1783      uint32_t int_ctl;
1784  
1785      /* KVM states, automatically cleared on reset */
1786      uint8_t nmi_injected;
1787      uint8_t nmi_pending;
1788  
1789      uintptr_t retaddr;
1790  
1791      /* Fields up to this point are cleared by a CPU reset */
1792      struct {} end_reset_fields;
1793  
1794      /* Fields after this point are preserved across CPU reset. */
1795  
1796      /* processor features (e.g. for CPUID insn) */
1797      /* Minimum cpuid leaf 7 value */
1798      uint32_t cpuid_level_func7;
1799      /* Actual cpuid leaf 7 value */
1800      uint32_t cpuid_min_level_func7;
1801      /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1802      uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1803      /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1804      uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1805      /* Actual level/xlevel/xlevel2 value: */
1806      uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1807      uint32_t cpuid_vendor1;
1808      uint32_t cpuid_vendor2;
1809      uint32_t cpuid_vendor3;
1810      uint32_t cpuid_version;
1811      FeatureWordArray features;
1812      /* Features that were explicitly enabled/disabled */
1813      FeatureWordArray user_features;
1814      uint32_t cpuid_model[12];
1815      /* Cache information for CPUID.  When legacy-cache=on, the cache data
1816       * on each CPUID leaf will be different, because we keep compatibility
1817       * with old QEMU versions.
1818       */
1819      CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1820  
1821      /* MTRRs */
1822      uint64_t mtrr_fixed[11];
1823      uint64_t mtrr_deftype;
1824      MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1825  
1826      /* For KVM */
1827      uint32_t mp_state;
1828      int32_t exception_nr;
1829      int32_t interrupt_injected;
1830      uint8_t soft_interrupt;
1831      uint8_t exception_pending;
1832      uint8_t exception_injected;
1833      uint8_t has_error_code;
1834      uint8_t exception_has_payload;
1835      uint64_t exception_payload;
1836      uint8_t triple_fault_pending;
1837      uint32_t ins_len;
1838      uint32_t sipi_vector;
1839      bool tsc_valid;
1840      int64_t tsc_khz;
1841      int64_t user_tsc_khz; /* for sanity check only */
1842      uint64_t apic_bus_freq;
1843      uint64_t tsc;
1844  #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1845      void *xsave_buf;
1846      uint32_t xsave_buf_len;
1847  #endif
1848  #if defined(CONFIG_KVM)
1849      struct kvm_nested_state *nested_state;
1850      MemoryRegion *xen_vcpu_info_mr;
1851      void *xen_vcpu_info_hva;
1852      uint64_t xen_vcpu_info_gpa;
1853      uint64_t xen_vcpu_info_default_gpa;
1854      uint64_t xen_vcpu_time_info_gpa;
1855      uint64_t xen_vcpu_runstate_gpa;
1856      uint8_t xen_vcpu_callback_vector;
1857      bool xen_callback_asserted;
1858      uint16_t xen_virq[XEN_NR_VIRQS];
1859      uint64_t xen_singleshot_timer_ns;
1860      QEMUTimer *xen_singleshot_timer;
1861      uint64_t xen_periodic_timer_period;
1862      QEMUTimer *xen_periodic_timer;
1863      QemuMutex xen_timers_lock;
1864  #endif
1865  #if defined(CONFIG_HVF)
1866      HVFX86LazyFlags hvf_lflags;
1867      void *hvf_mmio_buf;
1868  #endif
1869  
1870      uint64_t mcg_cap;
1871      uint64_t mcg_ctl;
1872      uint64_t mcg_ext_ctl;
1873      uint64_t mce_banks[MCE_BANKS_DEF*4];
1874      uint64_t xstate_bv;
1875  
1876      /* vmstate */
1877      uint16_t fpus_vmstate;
1878      uint16_t fptag_vmstate;
1879      uint16_t fpregs_format_vmstate;
1880  
1881      uint64_t xss;
1882      uint32_t umwait;
1883  
1884      TPRAccess tpr_access_type;
1885  
1886      /* Number of dies within this CPU package. */
1887      unsigned nr_dies;
1888  } CPUX86State;
1889  
1890  struct kvm_msrs;
1891  
1892  /**
1893   * X86CPU:
1894   * @env: #CPUX86State
1895   * @migratable: If set, only migratable flags will be accepted when "enforce"
1896   * mode is used, and only migratable flags will be included in the "host"
1897   * CPU model.
1898   *
1899   * An x86 CPU.
1900   */
1901  struct ArchCPU {
1902      CPUState parent_obj;
1903  
1904      CPUX86State env;
1905      VMChangeStateEntry *vmsentry;
1906  
1907      uint64_t ucode_rev;
1908  
1909      uint32_t hyperv_spinlock_attempts;
1910      char *hyperv_vendor;
1911      bool hyperv_synic_kvm_only;
1912      uint64_t hyperv_features;
1913      bool hyperv_passthrough;
1914      OnOffAuto hyperv_no_nonarch_cs;
1915      uint32_t hyperv_vendor_id[3];
1916      uint32_t hyperv_interface_id[4];
1917      uint32_t hyperv_limits[3];
1918      bool hyperv_enforce_cpuid;
1919      uint32_t hyperv_ver_id_build;
1920      uint16_t hyperv_ver_id_major;
1921      uint16_t hyperv_ver_id_minor;
1922      uint32_t hyperv_ver_id_sp;
1923      uint8_t hyperv_ver_id_sb;
1924      uint32_t hyperv_ver_id_sn;
1925  
1926      bool check_cpuid;
1927      bool enforce_cpuid;
1928      /*
1929       * Force features to be enabled even if the host doesn't support them.
1930       * This is dangerous and should be done only for testing CPUID
1931       * compatibility.
1932       */
1933      bool force_features;
1934      bool expose_kvm;
1935      bool expose_tcg;
1936      bool migratable;
1937      bool migrate_smi_count;
1938      bool max_features; /* Enable all supported features automatically */
1939      uint32_t apic_id;
1940  
1941      /* Enables publishing of TSC increment and Local APIC bus frequencies to
1942       * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1943      bool vmware_cpuid_freq;
1944  
1945      /* if true the CPUID code directly forward host cache leaves to the guest */
1946      bool cache_info_passthrough;
1947  
1948      /* if true the CPUID code directly forwards
1949       * host monitor/mwait leaves to the guest */
1950      struct {
1951          uint32_t eax;
1952          uint32_t ebx;
1953          uint32_t ecx;
1954          uint32_t edx;
1955      } mwait;
1956  
1957      /* Features that were filtered out because of missing host capabilities */
1958      FeatureWordArray filtered_features;
1959  
1960      /* Enable PMU CPUID bits. This can't be enabled by default yet because
1961       * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1962       * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1963       * capabilities) directly to the guest.
1964       */
1965      bool enable_pmu;
1966  
1967      /*
1968       * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
1969       * This can't be initialized with a default because it doesn't have
1970       * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
1971       * returned by kvm_arch_get_supported_msr_feature()(which depends on both
1972       * host CPU and kernel capabilities) to the guest.
1973       */
1974      uint64_t lbr_fmt;
1975  
1976      /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1977       * disabled by default to avoid breaking migration between QEMU with
1978       * different LMCE configurations.
1979       */
1980      bool enable_lmce;
1981  
1982      /* Compatibility bits for old machine types.
1983       * If true present virtual l3 cache for VM, the vcpus in the same virtual
1984       * socket share an virtual l3 cache.
1985       */
1986      bool enable_l3_cache;
1987  
1988      /* Compatibility bits for old machine types.
1989       * If true present the old cache topology information
1990       */
1991      bool legacy_cache;
1992  
1993      /* Compatibility bits for old machine types: */
1994      bool enable_cpuid_0xb;
1995  
1996      /* Enable auto level-increase for all CPUID leaves */
1997      bool full_cpuid_auto_level;
1998  
1999      /* Only advertise CPUID leaves defined by the vendor */
2000      bool vendor_cpuid_only;
2001  
2002      /* Enable auto level-increase for Intel Processor Trace leave */
2003      bool intel_pt_auto_level;
2004  
2005      /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
2006      bool fill_mtrr_mask;
2007  
2008      /* if true override the phys_bits value with a value read from the host */
2009      bool host_phys_bits;
2010  
2011      /* if set, limit maximum value for phys_bits when host_phys_bits is true */
2012      uint8_t host_phys_bits_limit;
2013  
2014      /* Stop SMI delivery for migration compatibility with old machines */
2015      bool kvm_no_smi_migration;
2016  
2017      /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
2018      bool kvm_pv_enforce_cpuid;
2019  
2020      /* Number of physical address bits supported */
2021      uint32_t phys_bits;
2022  
2023      /* in order to simplify APIC support, we leave this pointer to the
2024         user */
2025      struct DeviceState *apic_state;
2026      struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
2027      Notifier machine_done;
2028  
2029      struct kvm_msrs *kvm_msr_buf;
2030  
2031      int32_t node_id; /* NUMA node this CPU belongs to */
2032      int32_t socket_id;
2033      int32_t die_id;
2034      int32_t core_id;
2035      int32_t thread_id;
2036  
2037      int32_t hv_max_vps;
2038  
2039      bool xen_vapic;
2040  };
2041  
2042  typedef struct X86CPUModel X86CPUModel;
2043  
2044  /**
2045   * X86CPUClass:
2046   * @cpu_def: CPU model definition
2047   * @host_cpuid_required: Whether CPU model requires cpuid from host.
2048   * @ordering: Ordering on the "-cpu help" CPU model list.
2049   * @migration_safe: See CpuDefinitionInfo::migration_safe
2050   * @static_model: See CpuDefinitionInfo::static
2051   * @parent_realize: The parent class' realize handler.
2052   * @parent_phases: The parent class' reset phase handlers.
2053   *
2054   * An x86 CPU model or family.
2055   */
2056  struct X86CPUClass {
2057      CPUClass parent_class;
2058  
2059      /*
2060       * CPU definition, automatically loaded by instance_init if not NULL.
2061       * Should be eventually replaced by subclass-specific property defaults.
2062       */
2063      X86CPUModel *model;
2064  
2065      bool host_cpuid_required;
2066      int ordering;
2067      bool migration_safe;
2068      bool static_model;
2069  
2070      /*
2071       * Optional description of CPU model.
2072       * If unavailable, cpu_def->model_id is used.
2073       */
2074      const char *model_description;
2075  
2076      DeviceRealize parent_realize;
2077      DeviceUnrealize parent_unrealize;
2078      ResettablePhases parent_phases;
2079  };
2080  
2081  #ifndef CONFIG_USER_ONLY
2082  extern const VMStateDescription vmstate_x86_cpu;
2083  #endif
2084  
2085  int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
2086  
2087  int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
2088                               int cpuid, DumpState *s);
2089  int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
2090                               int cpuid, DumpState *s);
2091  int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2092                                   DumpState *s);
2093  int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2094                                   DumpState *s);
2095  
2096  bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
2097                                  Error **errp);
2098  
2099  void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
2100  
2101  int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
2102  int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
2103  
2104  void x86_cpu_list(void);
2105  int cpu_x86_support_mca_broadcast(CPUX86State *env);
2106  
2107  #ifndef CONFIG_USER_ONLY
2108  hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
2109                                           MemTxAttrs *attrs);
2110  int cpu_get_pic_interrupt(CPUX86State *s);
2111  
2112  /* MS-DOS compatibility mode FPU exception support */
2113  void x86_register_ferr_irq(qemu_irq irq);
2114  void fpu_check_raise_ferr_irq(CPUX86State *s);
2115  void cpu_set_ignne(void);
2116  void cpu_clear_ignne(void);
2117  #endif
2118  
2119  /* mpx_helper.c */
2120  void cpu_sync_bndcs_hflags(CPUX86State *env);
2121  
2122  /* this function must always be used to load data in the segment
2123     cache: it synchronizes the hflags with the segment cache values */
2124  static inline void cpu_x86_load_seg_cache(CPUX86State *env,
2125                                            X86Seg seg_reg, unsigned int selector,
2126                                            target_ulong base,
2127                                            unsigned int limit,
2128                                            unsigned int flags)
2129  {
2130      SegmentCache *sc;
2131      unsigned int new_hflags;
2132  
2133      sc = &env->segs[seg_reg];
2134      sc->selector = selector;
2135      sc->base = base;
2136      sc->limit = limit;
2137      sc->flags = flags;
2138  
2139      /* update the hidden flags */
2140      {
2141          if (seg_reg == R_CS) {
2142  #ifdef TARGET_X86_64
2143              if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
2144                  /* long mode */
2145                  env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2146                  env->hflags &= ~(HF_ADDSEG_MASK);
2147              } else
2148  #endif
2149              {
2150                  /* legacy / compatibility case */
2151                  new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
2152                      >> (DESC_B_SHIFT - HF_CS32_SHIFT);
2153                  env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
2154                      new_hflags;
2155              }
2156          }
2157          if (seg_reg == R_SS) {
2158              int cpl = (flags >> DESC_DPL_SHIFT) & 3;
2159  #if HF_CPL_MASK != 3
2160  #error HF_CPL_MASK is hardcoded
2161  #endif
2162              env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
2163              /* Possibly switch between BNDCFGS and BNDCFGU */
2164              cpu_sync_bndcs_hflags(env);
2165          }
2166          new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
2167              >> (DESC_B_SHIFT - HF_SS32_SHIFT);
2168          if (env->hflags & HF_CS64_MASK) {
2169              /* zero base assumed for DS, ES and SS in long mode */
2170          } else if (!(env->cr[0] & CR0_PE_MASK) ||
2171                     (env->eflags & VM_MASK) ||
2172                     !(env->hflags & HF_CS32_MASK)) {
2173              /* XXX: try to avoid this test. The problem comes from the
2174                 fact that is real mode or vm86 mode we only modify the
2175                 'base' and 'selector' fields of the segment cache to go
2176                 faster. A solution may be to force addseg to one in
2177                 translate-i386.c. */
2178              new_hflags |= HF_ADDSEG_MASK;
2179          } else {
2180              new_hflags |= ((env->segs[R_DS].base |
2181                              env->segs[R_ES].base |
2182                              env->segs[R_SS].base) != 0) <<
2183                  HF_ADDSEG_SHIFT;
2184          }
2185          env->hflags = (env->hflags &
2186                         ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
2187      }
2188  }
2189  
2190  static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
2191                                                 uint8_t sipi_vector)
2192  {
2193      CPUState *cs = CPU(cpu);
2194      CPUX86State *env = &cpu->env;
2195  
2196      env->eip = 0;
2197      cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
2198                             sipi_vector << 12,
2199                             env->segs[R_CS].limit,
2200                             env->segs[R_CS].flags);
2201      cs->halted = 0;
2202  }
2203  
2204  int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
2205                              target_ulong *base, unsigned int *limit,
2206                              unsigned int *flags);
2207  
2208  /* op_helper.c */
2209  /* used for debug or cpu save/restore */
2210  
2211  /* cpu-exec.c */
2212  /* the following helpers are only usable in user mode simulation as
2213     they can trigger unexpected exceptions */
2214  void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
2215  void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
2216  void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
2217  void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
2218  void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
2219  void cpu_x86_xsave(CPUX86State *s, target_ulong ptr);
2220  void cpu_x86_xrstor(CPUX86State *s, target_ulong ptr);
2221  
2222  /* cpu.c */
2223  void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
2224                                uint32_t vendor2, uint32_t vendor3);
2225  typedef struct PropValue {
2226      const char *prop, *value;
2227  } PropValue;
2228  void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
2229  
2230  void x86_cpu_after_reset(X86CPU *cpu);
2231  
2232  uint32_t cpu_x86_virtual_addr_width(CPUX86State *env);
2233  
2234  /* cpu.c other functions (cpuid) */
2235  void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2236                     uint32_t *eax, uint32_t *ebx,
2237                     uint32_t *ecx, uint32_t *edx);
2238  void cpu_clear_apic_feature(CPUX86State *env);
2239  void host_cpuid(uint32_t function, uint32_t count,
2240                  uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
2241  
2242  /* helper.c */
2243  void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
2244  void cpu_sync_avx_hflag(CPUX86State *env);
2245  
2246  #ifndef CONFIG_USER_ONLY
2247  static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2248  {
2249      return !!attrs.secure;
2250  }
2251  
2252  static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
2253  {
2254      return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
2255  }
2256  
2257  /*
2258   * load efer and update the corresponding hflags. XXX: do consistency
2259   * checks with cpuid bits?
2260   */
2261  void cpu_load_efer(CPUX86State *env, uint64_t val);
2262  uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
2263  uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
2264  uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
2265  uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
2266  void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
2267  void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
2268  void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
2269  void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
2270  void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
2271  #endif
2272  
2273  /* will be suppressed */
2274  void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
2275  void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
2276  void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
2277  void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
2278  
2279  /* hw/pc.c */
2280  uint64_t cpu_get_tsc(CPUX86State *env);
2281  
2282  #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2283  
2284  #ifdef TARGET_X86_64
2285  #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2286  #else
2287  #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2288  #endif
2289  
2290  #define cpu_list x86_cpu_list
2291  
2292  /* MMU modes definitions */
2293  #define MMU_KSMAP_IDX   0
2294  #define MMU_USER_IDX    1
2295  #define MMU_KNOSMAP_IDX 2
2296  #define MMU_NESTED_IDX  3
2297  #define MMU_PHYS_IDX    4
2298  
2299  static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
2300  {
2301      return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
2302          (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
2303          ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2304  }
2305  
2306  static inline int cpu_mmu_index_kernel(CPUX86State *env)
2307  {
2308      return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
2309          ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
2310          ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2311  }
2312  
2313  #define CC_DST  (env->cc_dst)
2314  #define CC_SRC  (env->cc_src)
2315  #define CC_SRC2 (env->cc_src2)
2316  #define CC_OP   (env->cc_op)
2317  
2318  #include "exec/cpu-all.h"
2319  #include "svm.h"
2320  
2321  #if !defined(CONFIG_USER_ONLY)
2322  #include "hw/i386/apic.h"
2323  #endif
2324  
2325  static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
2326                                          uint64_t *cs_base, uint32_t *flags)
2327  {
2328      *flags = env->hflags |
2329          (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2330      if (env->hflags & HF_CS64_MASK) {
2331          *cs_base = 0;
2332          *pc = env->eip;
2333      } else {
2334          *cs_base = env->segs[R_CS].base;
2335          *pc = (uint32_t)(*cs_base + env->eip);
2336      }
2337  }
2338  
2339  void do_cpu_init(X86CPU *cpu);
2340  
2341  #define MCE_INJECT_BROADCAST    1
2342  #define MCE_INJECT_UNCOND_AO    2
2343  
2344  void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2345                          uint64_t status, uint64_t mcg_status, uint64_t addr,
2346                          uint64_t misc, int flags);
2347  
2348  uint32_t cpu_cc_compute_all(CPUX86State *env1);
2349  
2350  static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2351  {
2352      uint32_t eflags = env->eflags;
2353      if (tcg_enabled()) {
2354          eflags |= cpu_cc_compute_all(env) | (env->df & DF_MASK);
2355      }
2356      return eflags;
2357  }
2358  
2359  static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2360  {
2361      return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2362  }
2363  
2364  static inline int32_t x86_get_a20_mask(CPUX86State *env)
2365  {
2366      if (env->hflags & HF_SMM_MASK) {
2367          return -1;
2368      } else {
2369          return env->a20_mask;
2370      }
2371  }
2372  
2373  static inline bool cpu_has_vmx(CPUX86State *env)
2374  {
2375      return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2376  }
2377  
2378  static inline bool cpu_has_svm(CPUX86State *env)
2379  {
2380      return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2381  }
2382  
2383  /*
2384   * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2385   * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2386   * VMX operation. This is because CR4.VMXE is one of the bits set
2387   * in MSR_IA32_VMX_CR4_FIXED1.
2388   *
2389   * There is one exception to above statement when vCPU enters SMM mode.
2390   * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2391   * may also reset CR4.VMXE during execution in SMM mode.
2392   * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2393   * and CR4.VMXE is restored to it's original value of being set.
2394   *
2395   * Therefore, when vCPU is not in SMM mode, we can infer whether
2396   * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2397   * know for certain.
2398   */
2399  static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2400  {
2401      return cpu_has_vmx(env) &&
2402             ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2403  }
2404  
2405  /* excp_helper.c */
2406  int get_pg_mode(CPUX86State *env);
2407  
2408  /* fpu_helper.c */
2409  void update_fp_status(CPUX86State *env);
2410  void update_mxcsr_status(CPUX86State *env);
2411  void update_mxcsr_from_sse_status(CPUX86State *env);
2412  
2413  static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2414  {
2415      env->mxcsr = mxcsr;
2416      if (tcg_enabled()) {
2417          update_mxcsr_status(env);
2418      }
2419  }
2420  
2421  static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2422  {
2423       env->fpuc = fpuc;
2424       if (tcg_enabled()) {
2425          update_fp_status(env);
2426       }
2427  }
2428  
2429  /* svm_helper.c */
2430  #ifdef CONFIG_USER_ONLY
2431  static inline void
2432  cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2433                                uint64_t param, uintptr_t retaddr)
2434  { /* no-op */ }
2435  static inline bool
2436  cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
2437  { return false; }
2438  #else
2439  void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2440                                     uint64_t param, uintptr_t retaddr);
2441  bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type);
2442  #endif
2443  
2444  /* apic.c */
2445  void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2446  void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2447                                     TPRAccess access);
2448  
2449  /* Special values for X86CPUVersion: */
2450  
2451  /* Resolve to latest CPU version */
2452  #define CPU_VERSION_LATEST -1
2453  
2454  /*
2455   * Resolve to version defined by current machine type.
2456   * See x86_cpu_set_default_version()
2457   */
2458  #define CPU_VERSION_AUTO   -2
2459  
2460  /* Don't resolve to any versioned CPU models, like old QEMU versions */
2461  #define CPU_VERSION_LEGACY  0
2462  
2463  typedef int X86CPUVersion;
2464  
2465  /*
2466   * Set default CPU model version for CPU models having
2467   * version == CPU_VERSION_AUTO.
2468   */
2469  void x86_cpu_set_default_version(X86CPUVersion version);
2470  
2471  #ifndef CONFIG_USER_ONLY
2472  
2473  void do_cpu_sipi(X86CPU *cpu);
2474  
2475  #define APIC_DEFAULT_ADDRESS 0xfee00000
2476  #define APIC_SPACE_SIZE      0x100000
2477  
2478  /* cpu-dump.c */
2479  void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2480  
2481  #endif
2482  
2483  /* cpu.c */
2484  bool cpu_is_bsp(X86CPU *cpu);
2485  
2486  void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen);
2487  void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen);
2488  uint32_t xsave_area_size(uint64_t mask, bool compacted);
2489  void x86_update_hflags(CPUX86State* env);
2490  
2491  static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2492  {
2493      return !!(cpu->hyperv_features & BIT(feat));
2494  }
2495  
2496  static inline uint64_t cr4_reserved_bits(CPUX86State *env)
2497  {
2498      uint64_t reserved_bits = CR4_RESERVED_MASK;
2499      if (!env->features[FEAT_XSAVE]) {
2500          reserved_bits |= CR4_OSXSAVE_MASK;
2501      }
2502      if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) {
2503          reserved_bits |= CR4_SMEP_MASK;
2504      }
2505      if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
2506          reserved_bits |= CR4_SMAP_MASK;
2507      }
2508      if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) {
2509          reserved_bits |= CR4_FSGSBASE_MASK;
2510      }
2511      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
2512          reserved_bits |= CR4_PKE_MASK;
2513      }
2514      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) {
2515          reserved_bits |= CR4_LA57_MASK;
2516      }
2517      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
2518          reserved_bits |= CR4_UMIP_MASK;
2519      }
2520      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
2521          reserved_bits |= CR4_PKS_MASK;
2522      }
2523      return reserved_bits;
2524  }
2525  
2526  static inline bool ctl_has_irq(CPUX86State *env)
2527  {
2528      uint32_t int_prio;
2529      uint32_t tpr;
2530  
2531      int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
2532      tpr = env->int_ctl & V_TPR_MASK;
2533  
2534      if (env->int_ctl & V_IGN_TPR_MASK) {
2535          return (env->int_ctl & V_IRQ_MASK);
2536      }
2537  
2538      return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
2539  }
2540  
2541  #if defined(TARGET_X86_64) && \
2542      defined(CONFIG_USER_ONLY) && \
2543      defined(CONFIG_LINUX)
2544  # define TARGET_VSYSCALL_PAGE  (UINT64_C(-10) << 20)
2545  #endif
2546  
2547  #endif /* I386_CPU_H */
2548