1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "standard-headers/asm-x86/hyperv.h" 26 27 #ifdef TARGET_X86_64 28 #define TARGET_LONG_BITS 64 29 #else 30 #define TARGET_LONG_BITS 32 31 #endif 32 33 /* Maximum instruction code size */ 34 #define TARGET_MAX_INSN_SIZE 16 35 36 /* support for self modifying code even if the modified instruction is 37 close to the modifying instruction */ 38 #define TARGET_HAS_PRECISE_SMC 39 40 #ifdef TARGET_X86_64 41 #define I386_ELF_MACHINE EM_X86_64 42 #define ELF_MACHINE_UNAME "x86_64" 43 #else 44 #define I386_ELF_MACHINE EM_386 45 #define ELF_MACHINE_UNAME "i686" 46 #endif 47 48 #define CPUArchState struct CPUX86State 49 50 #include "exec/cpu-defs.h" 51 52 #include "fpu/softfloat.h" 53 54 #define R_EAX 0 55 #define R_ECX 1 56 #define R_EDX 2 57 #define R_EBX 3 58 #define R_ESP 4 59 #define R_EBP 5 60 #define R_ESI 6 61 #define R_EDI 7 62 63 #define R_AL 0 64 #define R_CL 1 65 #define R_DL 2 66 #define R_BL 3 67 #define R_AH 4 68 #define R_CH 5 69 #define R_DH 6 70 #define R_BH 7 71 72 #define R_ES 0 73 #define R_CS 1 74 #define R_SS 2 75 #define R_DS 3 76 #define R_FS 4 77 #define R_GS 5 78 79 /* segment descriptor fields */ 80 #define DESC_G_MASK (1 << 23) 81 #define DESC_B_SHIFT 22 82 #define DESC_B_MASK (1 << DESC_B_SHIFT) 83 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 84 #define DESC_L_MASK (1 << DESC_L_SHIFT) 85 #define DESC_AVL_MASK (1 << 20) 86 #define DESC_P_MASK (1 << 15) 87 #define DESC_DPL_SHIFT 13 88 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 89 #define DESC_S_MASK (1 << 12) 90 #define DESC_TYPE_SHIFT 8 91 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 92 #define DESC_A_MASK (1 << 8) 93 94 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 95 #define DESC_C_MASK (1 << 10) /* code: conforming */ 96 #define DESC_R_MASK (1 << 9) /* code: readable */ 97 98 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 99 #define DESC_W_MASK (1 << 9) /* data: writable */ 100 101 #define DESC_TSS_BUSY_MASK (1 << 9) 102 103 /* eflags masks */ 104 #define CC_C 0x0001 105 #define CC_P 0x0004 106 #define CC_A 0x0010 107 #define CC_Z 0x0040 108 #define CC_S 0x0080 109 #define CC_O 0x0800 110 111 #define TF_SHIFT 8 112 #define IOPL_SHIFT 12 113 #define VM_SHIFT 17 114 115 #define TF_MASK 0x00000100 116 #define IF_MASK 0x00000200 117 #define DF_MASK 0x00000400 118 #define IOPL_MASK 0x00003000 119 #define NT_MASK 0x00004000 120 #define RF_MASK 0x00010000 121 #define VM_MASK 0x00020000 122 #define AC_MASK 0x00040000 123 #define VIF_MASK 0x00080000 124 #define VIP_MASK 0x00100000 125 #define ID_MASK 0x00200000 126 127 /* hidden flags - used internally by qemu to represent additional cpu 128 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 129 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 130 positions to ease oring with eflags. */ 131 /* current cpl */ 132 #define HF_CPL_SHIFT 0 133 /* true if hardware interrupts must be disabled for next instruction */ 134 #define HF_INHIBIT_IRQ_SHIFT 3 135 /* 16 or 32 segments */ 136 #define HF_CS32_SHIFT 4 137 #define HF_SS32_SHIFT 5 138 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 139 #define HF_ADDSEG_SHIFT 6 140 /* copy of CR0.PE (protected mode) */ 141 #define HF_PE_SHIFT 7 142 #define HF_TF_SHIFT 8 /* must be same as eflags */ 143 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 144 #define HF_EM_SHIFT 10 145 #define HF_TS_SHIFT 11 146 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 147 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 148 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 149 #define HF_RF_SHIFT 16 /* must be same as eflags */ 150 #define HF_VM_SHIFT 17 /* must be same as eflags */ 151 #define HF_AC_SHIFT 18 /* must be same as eflags */ 152 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 153 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 154 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 155 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 156 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 157 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 158 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 159 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 160 161 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 162 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 163 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 164 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 165 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 166 #define HF_PE_MASK (1 << HF_PE_SHIFT) 167 #define HF_TF_MASK (1 << HF_TF_SHIFT) 168 #define HF_MP_MASK (1 << HF_MP_SHIFT) 169 #define HF_EM_MASK (1 << HF_EM_SHIFT) 170 #define HF_TS_MASK (1 << HF_TS_SHIFT) 171 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 172 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 173 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 174 #define HF_RF_MASK (1 << HF_RF_SHIFT) 175 #define HF_VM_MASK (1 << HF_VM_SHIFT) 176 #define HF_AC_MASK (1 << HF_AC_SHIFT) 177 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 178 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 179 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 180 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 181 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 182 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 183 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 184 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 185 186 /* hflags2 */ 187 188 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 189 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 190 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 191 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 192 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 193 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 194 195 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 196 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 197 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 198 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 199 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 200 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 201 202 #define CR0_PE_SHIFT 0 203 #define CR0_MP_SHIFT 1 204 205 #define CR0_PE_MASK (1U << 0) 206 #define CR0_MP_MASK (1U << 1) 207 #define CR0_EM_MASK (1U << 2) 208 #define CR0_TS_MASK (1U << 3) 209 #define CR0_ET_MASK (1U << 4) 210 #define CR0_NE_MASK (1U << 5) 211 #define CR0_WP_MASK (1U << 16) 212 #define CR0_AM_MASK (1U << 18) 213 #define CR0_PG_MASK (1U << 31) 214 215 #define CR4_VME_MASK (1U << 0) 216 #define CR4_PVI_MASK (1U << 1) 217 #define CR4_TSD_MASK (1U << 2) 218 #define CR4_DE_MASK (1U << 3) 219 #define CR4_PSE_MASK (1U << 4) 220 #define CR4_PAE_MASK (1U << 5) 221 #define CR4_MCE_MASK (1U << 6) 222 #define CR4_PGE_MASK (1U << 7) 223 #define CR4_PCE_MASK (1U << 8) 224 #define CR4_OSFXSR_SHIFT 9 225 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 226 #define CR4_OSXMMEXCPT_MASK (1U << 10) 227 #define CR4_LA57_MASK (1U << 12) 228 #define CR4_VMXE_MASK (1U << 13) 229 #define CR4_SMXE_MASK (1U << 14) 230 #define CR4_FSGSBASE_MASK (1U << 16) 231 #define CR4_PCIDE_MASK (1U << 17) 232 #define CR4_OSXSAVE_MASK (1U << 18) 233 #define CR4_SMEP_MASK (1U << 20) 234 #define CR4_SMAP_MASK (1U << 21) 235 #define CR4_PKE_MASK (1U << 22) 236 237 #define DR6_BD (1 << 13) 238 #define DR6_BS (1 << 14) 239 #define DR6_BT (1 << 15) 240 #define DR6_FIXED_1 0xffff0ff0 241 242 #define DR7_GD (1 << 13) 243 #define DR7_TYPE_SHIFT 16 244 #define DR7_LEN_SHIFT 18 245 #define DR7_FIXED_1 0x00000400 246 #define DR7_GLOBAL_BP_MASK 0xaa 247 #define DR7_LOCAL_BP_MASK 0x55 248 #define DR7_MAX_BP 4 249 #define DR7_TYPE_BP_INST 0x0 250 #define DR7_TYPE_DATA_WR 0x1 251 #define DR7_TYPE_IO_RW 0x2 252 #define DR7_TYPE_DATA_RW 0x3 253 254 #define PG_PRESENT_BIT 0 255 #define PG_RW_BIT 1 256 #define PG_USER_BIT 2 257 #define PG_PWT_BIT 3 258 #define PG_PCD_BIT 4 259 #define PG_ACCESSED_BIT 5 260 #define PG_DIRTY_BIT 6 261 #define PG_PSE_BIT 7 262 #define PG_GLOBAL_BIT 8 263 #define PG_PSE_PAT_BIT 12 264 #define PG_PKRU_BIT 59 265 #define PG_NX_BIT 63 266 267 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 268 #define PG_RW_MASK (1 << PG_RW_BIT) 269 #define PG_USER_MASK (1 << PG_USER_BIT) 270 #define PG_PWT_MASK (1 << PG_PWT_BIT) 271 #define PG_PCD_MASK (1 << PG_PCD_BIT) 272 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 273 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 274 #define PG_PSE_MASK (1 << PG_PSE_BIT) 275 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 276 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 277 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 278 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 279 #define PG_HI_USER_MASK 0x7ff0000000000000LL 280 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 281 #define PG_NX_MASK (1ULL << PG_NX_BIT) 282 283 #define PG_ERROR_W_BIT 1 284 285 #define PG_ERROR_P_MASK 0x01 286 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 287 #define PG_ERROR_U_MASK 0x04 288 #define PG_ERROR_RSVD_MASK 0x08 289 #define PG_ERROR_I_D_MASK 0x10 290 #define PG_ERROR_PK_MASK 0x20 291 292 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 293 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 294 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 295 296 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 297 #define MCE_BANKS_DEF 10 298 299 #define MCG_CAP_BANKS_MASK 0xff 300 301 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 302 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 303 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 304 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 305 306 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 307 308 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 309 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 310 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 311 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 312 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 313 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 314 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 315 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 316 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 317 318 /* MISC register defines */ 319 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 320 #define MCM_ADDR_LINEAR 1 /* linear address */ 321 #define MCM_ADDR_PHYS 2 /* physical address */ 322 #define MCM_ADDR_MEM 3 /* memory address */ 323 #define MCM_ADDR_GENERIC 7 /* generic */ 324 325 #define MSR_IA32_TSC 0x10 326 #define MSR_IA32_APICBASE 0x1b 327 #define MSR_IA32_APICBASE_BSP (1<<8) 328 #define MSR_IA32_APICBASE_ENABLE (1<<11) 329 #define MSR_IA32_APICBASE_EXTD (1 << 10) 330 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 331 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 332 #define MSR_TSC_ADJUST 0x0000003b 333 #define MSR_IA32_TSCDEADLINE 0x6e0 334 335 #define FEATURE_CONTROL_LOCKED (1<<0) 336 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 337 #define FEATURE_CONTROL_LMCE (1<<20) 338 339 #define MSR_P6_PERFCTR0 0xc1 340 341 #define MSR_IA32_SMBASE 0x9e 342 #define MSR_MTRRcap 0xfe 343 #define MSR_MTRRcap_VCNT 8 344 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 345 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 346 347 #define MSR_IA32_SYSENTER_CS 0x174 348 #define MSR_IA32_SYSENTER_ESP 0x175 349 #define MSR_IA32_SYSENTER_EIP 0x176 350 351 #define MSR_MCG_CAP 0x179 352 #define MSR_MCG_STATUS 0x17a 353 #define MSR_MCG_CTL 0x17b 354 #define MSR_MCG_EXT_CTL 0x4d0 355 356 #define MSR_P6_EVNTSEL0 0x186 357 358 #define MSR_IA32_PERF_STATUS 0x198 359 360 #define MSR_IA32_MISC_ENABLE 0x1a0 361 /* Indicates good rep/movs microcode on some processors: */ 362 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 363 364 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 365 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 366 367 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 368 369 #define MSR_MTRRfix64K_00000 0x250 370 #define MSR_MTRRfix16K_80000 0x258 371 #define MSR_MTRRfix16K_A0000 0x259 372 #define MSR_MTRRfix4K_C0000 0x268 373 #define MSR_MTRRfix4K_C8000 0x269 374 #define MSR_MTRRfix4K_D0000 0x26a 375 #define MSR_MTRRfix4K_D8000 0x26b 376 #define MSR_MTRRfix4K_E0000 0x26c 377 #define MSR_MTRRfix4K_E8000 0x26d 378 #define MSR_MTRRfix4K_F0000 0x26e 379 #define MSR_MTRRfix4K_F8000 0x26f 380 381 #define MSR_PAT 0x277 382 383 #define MSR_MTRRdefType 0x2ff 384 385 #define MSR_CORE_PERF_FIXED_CTR0 0x309 386 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 387 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 388 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 389 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 390 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 391 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 392 393 #define MSR_MC0_CTL 0x400 394 #define MSR_MC0_STATUS 0x401 395 #define MSR_MC0_ADDR 0x402 396 #define MSR_MC0_MISC 0x403 397 398 #define MSR_EFER 0xc0000080 399 400 #define MSR_EFER_SCE (1 << 0) 401 #define MSR_EFER_LME (1 << 8) 402 #define MSR_EFER_LMA (1 << 10) 403 #define MSR_EFER_NXE (1 << 11) 404 #define MSR_EFER_SVME (1 << 12) 405 #define MSR_EFER_FFXSR (1 << 14) 406 407 #define MSR_STAR 0xc0000081 408 #define MSR_LSTAR 0xc0000082 409 #define MSR_CSTAR 0xc0000083 410 #define MSR_FMASK 0xc0000084 411 #define MSR_FSBASE 0xc0000100 412 #define MSR_GSBASE 0xc0000101 413 #define MSR_KERNELGSBASE 0xc0000102 414 #define MSR_TSC_AUX 0xc0000103 415 416 #define MSR_VM_HSAVE_PA 0xc0010117 417 418 #define MSR_IA32_BNDCFGS 0x00000d90 419 #define MSR_IA32_XSS 0x00000da0 420 421 #define XSTATE_FP_BIT 0 422 #define XSTATE_SSE_BIT 1 423 #define XSTATE_YMM_BIT 2 424 #define XSTATE_BNDREGS_BIT 3 425 #define XSTATE_BNDCSR_BIT 4 426 #define XSTATE_OPMASK_BIT 5 427 #define XSTATE_ZMM_Hi256_BIT 6 428 #define XSTATE_Hi16_ZMM_BIT 7 429 #define XSTATE_PKRU_BIT 9 430 431 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 432 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 433 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 434 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 435 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 436 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 437 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 438 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 439 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 440 441 /* CPUID feature words */ 442 typedef enum FeatureWord { 443 FEAT_1_EDX, /* CPUID[1].EDX */ 444 FEAT_1_ECX, /* CPUID[1].ECX */ 445 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 446 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 447 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 448 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 449 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 450 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 451 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 452 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 453 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 454 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 455 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 456 FEAT_SVM, /* CPUID[8000_000A].EDX */ 457 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 458 FEAT_6_EAX, /* CPUID[6].EAX */ 459 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 460 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 461 FEATURE_WORDS, 462 } FeatureWord; 463 464 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 465 466 /* cpuid_features bits */ 467 #define CPUID_FP87 (1U << 0) 468 #define CPUID_VME (1U << 1) 469 #define CPUID_DE (1U << 2) 470 #define CPUID_PSE (1U << 3) 471 #define CPUID_TSC (1U << 4) 472 #define CPUID_MSR (1U << 5) 473 #define CPUID_PAE (1U << 6) 474 #define CPUID_MCE (1U << 7) 475 #define CPUID_CX8 (1U << 8) 476 #define CPUID_APIC (1U << 9) 477 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 478 #define CPUID_MTRR (1U << 12) 479 #define CPUID_PGE (1U << 13) 480 #define CPUID_MCA (1U << 14) 481 #define CPUID_CMOV (1U << 15) 482 #define CPUID_PAT (1U << 16) 483 #define CPUID_PSE36 (1U << 17) 484 #define CPUID_PN (1U << 18) 485 #define CPUID_CLFLUSH (1U << 19) 486 #define CPUID_DTS (1U << 21) 487 #define CPUID_ACPI (1U << 22) 488 #define CPUID_MMX (1U << 23) 489 #define CPUID_FXSR (1U << 24) 490 #define CPUID_SSE (1U << 25) 491 #define CPUID_SSE2 (1U << 26) 492 #define CPUID_SS (1U << 27) 493 #define CPUID_HT (1U << 28) 494 #define CPUID_TM (1U << 29) 495 #define CPUID_IA64 (1U << 30) 496 #define CPUID_PBE (1U << 31) 497 498 #define CPUID_EXT_SSE3 (1U << 0) 499 #define CPUID_EXT_PCLMULQDQ (1U << 1) 500 #define CPUID_EXT_DTES64 (1U << 2) 501 #define CPUID_EXT_MONITOR (1U << 3) 502 #define CPUID_EXT_DSCPL (1U << 4) 503 #define CPUID_EXT_VMX (1U << 5) 504 #define CPUID_EXT_SMX (1U << 6) 505 #define CPUID_EXT_EST (1U << 7) 506 #define CPUID_EXT_TM2 (1U << 8) 507 #define CPUID_EXT_SSSE3 (1U << 9) 508 #define CPUID_EXT_CID (1U << 10) 509 #define CPUID_EXT_FMA (1U << 12) 510 #define CPUID_EXT_CX16 (1U << 13) 511 #define CPUID_EXT_XTPR (1U << 14) 512 #define CPUID_EXT_PDCM (1U << 15) 513 #define CPUID_EXT_PCID (1U << 17) 514 #define CPUID_EXT_DCA (1U << 18) 515 #define CPUID_EXT_SSE41 (1U << 19) 516 #define CPUID_EXT_SSE42 (1U << 20) 517 #define CPUID_EXT_X2APIC (1U << 21) 518 #define CPUID_EXT_MOVBE (1U << 22) 519 #define CPUID_EXT_POPCNT (1U << 23) 520 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 521 #define CPUID_EXT_AES (1U << 25) 522 #define CPUID_EXT_XSAVE (1U << 26) 523 #define CPUID_EXT_OSXSAVE (1U << 27) 524 #define CPUID_EXT_AVX (1U << 28) 525 #define CPUID_EXT_F16C (1U << 29) 526 #define CPUID_EXT_RDRAND (1U << 30) 527 #define CPUID_EXT_HYPERVISOR (1U << 31) 528 529 #define CPUID_EXT2_FPU (1U << 0) 530 #define CPUID_EXT2_VME (1U << 1) 531 #define CPUID_EXT2_DE (1U << 2) 532 #define CPUID_EXT2_PSE (1U << 3) 533 #define CPUID_EXT2_TSC (1U << 4) 534 #define CPUID_EXT2_MSR (1U << 5) 535 #define CPUID_EXT2_PAE (1U << 6) 536 #define CPUID_EXT2_MCE (1U << 7) 537 #define CPUID_EXT2_CX8 (1U << 8) 538 #define CPUID_EXT2_APIC (1U << 9) 539 #define CPUID_EXT2_SYSCALL (1U << 11) 540 #define CPUID_EXT2_MTRR (1U << 12) 541 #define CPUID_EXT2_PGE (1U << 13) 542 #define CPUID_EXT2_MCA (1U << 14) 543 #define CPUID_EXT2_CMOV (1U << 15) 544 #define CPUID_EXT2_PAT (1U << 16) 545 #define CPUID_EXT2_PSE36 (1U << 17) 546 #define CPUID_EXT2_MP (1U << 19) 547 #define CPUID_EXT2_NX (1U << 20) 548 #define CPUID_EXT2_MMXEXT (1U << 22) 549 #define CPUID_EXT2_MMX (1U << 23) 550 #define CPUID_EXT2_FXSR (1U << 24) 551 #define CPUID_EXT2_FFXSR (1U << 25) 552 #define CPUID_EXT2_PDPE1GB (1U << 26) 553 #define CPUID_EXT2_RDTSCP (1U << 27) 554 #define CPUID_EXT2_LM (1U << 29) 555 #define CPUID_EXT2_3DNOWEXT (1U << 30) 556 #define CPUID_EXT2_3DNOW (1U << 31) 557 558 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 559 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 560 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 561 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 562 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 563 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 564 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 565 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 566 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 567 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 568 569 #define CPUID_EXT3_LAHF_LM (1U << 0) 570 #define CPUID_EXT3_CMP_LEG (1U << 1) 571 #define CPUID_EXT3_SVM (1U << 2) 572 #define CPUID_EXT3_EXTAPIC (1U << 3) 573 #define CPUID_EXT3_CR8LEG (1U << 4) 574 #define CPUID_EXT3_ABM (1U << 5) 575 #define CPUID_EXT3_SSE4A (1U << 6) 576 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 577 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 578 #define CPUID_EXT3_OSVW (1U << 9) 579 #define CPUID_EXT3_IBS (1U << 10) 580 #define CPUID_EXT3_XOP (1U << 11) 581 #define CPUID_EXT3_SKINIT (1U << 12) 582 #define CPUID_EXT3_WDT (1U << 13) 583 #define CPUID_EXT3_LWP (1U << 15) 584 #define CPUID_EXT3_FMA4 (1U << 16) 585 #define CPUID_EXT3_TCE (1U << 17) 586 #define CPUID_EXT3_NODEID (1U << 19) 587 #define CPUID_EXT3_TBM (1U << 21) 588 #define CPUID_EXT3_TOPOEXT (1U << 22) 589 #define CPUID_EXT3_PERFCORE (1U << 23) 590 #define CPUID_EXT3_PERFNB (1U << 24) 591 592 #define CPUID_SVM_NPT (1U << 0) 593 #define CPUID_SVM_LBRV (1U << 1) 594 #define CPUID_SVM_SVMLOCK (1U << 2) 595 #define CPUID_SVM_NRIPSAVE (1U << 3) 596 #define CPUID_SVM_TSCSCALE (1U << 4) 597 #define CPUID_SVM_VMCBCLEAN (1U << 5) 598 #define CPUID_SVM_FLUSHASID (1U << 6) 599 #define CPUID_SVM_DECODEASSIST (1U << 7) 600 #define CPUID_SVM_PAUSEFILTER (1U << 10) 601 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 602 603 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 604 #define CPUID_7_0_EBX_BMI1 (1U << 3) 605 #define CPUID_7_0_EBX_HLE (1U << 4) 606 #define CPUID_7_0_EBX_AVX2 (1U << 5) 607 #define CPUID_7_0_EBX_SMEP (1U << 7) 608 #define CPUID_7_0_EBX_BMI2 (1U << 8) 609 #define CPUID_7_0_EBX_ERMS (1U << 9) 610 #define CPUID_7_0_EBX_INVPCID (1U << 10) 611 #define CPUID_7_0_EBX_RTM (1U << 11) 612 #define CPUID_7_0_EBX_MPX (1U << 14) 613 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 614 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 615 #define CPUID_7_0_EBX_RDSEED (1U << 18) 616 #define CPUID_7_0_EBX_ADX (1U << 19) 617 #define CPUID_7_0_EBX_SMAP (1U << 20) 618 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 619 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 620 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 621 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 622 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 623 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 624 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 625 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 626 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 627 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 628 629 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 630 #define CPUID_7_0_ECX_UMIP (1U << 2) 631 #define CPUID_7_0_ECX_PKU (1U << 3) 632 #define CPUID_7_0_ECX_OSPKE (1U << 4) 633 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 634 #define CPUID_7_0_ECX_LA57 (1U << 16) 635 #define CPUID_7_0_ECX_RDPID (1U << 22) 636 637 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 638 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 639 640 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 641 #define CPUID_XSAVE_XSAVEC (1U << 1) 642 #define CPUID_XSAVE_XGETBV1 (1U << 2) 643 #define CPUID_XSAVE_XSAVES (1U << 3) 644 645 #define CPUID_6_EAX_ARAT (1U << 2) 646 647 /* CPUID[0x80000007].EDX flags: */ 648 #define CPUID_APM_INVTSC (1U << 8) 649 650 #define CPUID_VENDOR_SZ 12 651 652 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 653 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 654 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 655 #define CPUID_VENDOR_INTEL "GenuineIntel" 656 657 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 658 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 659 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 660 #define CPUID_VENDOR_AMD "AuthenticAMD" 661 662 #define CPUID_VENDOR_VIA "CentaurHauls" 663 664 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 665 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 666 667 /* CPUID[0xB].ECX level types */ 668 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 669 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 670 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 671 672 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 673 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 674 #endif 675 676 #define EXCP00_DIVZ 0 677 #define EXCP01_DB 1 678 #define EXCP02_NMI 2 679 #define EXCP03_INT3 3 680 #define EXCP04_INTO 4 681 #define EXCP05_BOUND 5 682 #define EXCP06_ILLOP 6 683 #define EXCP07_PREX 7 684 #define EXCP08_DBLE 8 685 #define EXCP09_XERR 9 686 #define EXCP0A_TSS 10 687 #define EXCP0B_NOSEG 11 688 #define EXCP0C_STACK 12 689 #define EXCP0D_GPF 13 690 #define EXCP0E_PAGE 14 691 #define EXCP10_COPR 16 692 #define EXCP11_ALGN 17 693 #define EXCP12_MCHK 18 694 695 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 696 for syscall instruction */ 697 698 /* i386-specific interrupt pending bits. */ 699 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 700 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 701 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 702 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 703 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 704 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 705 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 706 707 /* Use a clearer name for this. */ 708 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 709 710 /* Instead of computing the condition codes after each x86 instruction, 711 * QEMU just stores one operand (called CC_SRC), the result 712 * (called CC_DST) and the type of operation (called CC_OP). When the 713 * condition codes are needed, the condition codes can be calculated 714 * using this information. Condition codes are not generated if they 715 * are only needed for conditional branches. 716 */ 717 typedef enum { 718 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 719 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 720 721 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 722 CC_OP_MULW, 723 CC_OP_MULL, 724 CC_OP_MULQ, 725 726 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 727 CC_OP_ADDW, 728 CC_OP_ADDL, 729 CC_OP_ADDQ, 730 731 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 732 CC_OP_ADCW, 733 CC_OP_ADCL, 734 CC_OP_ADCQ, 735 736 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 737 CC_OP_SUBW, 738 CC_OP_SUBL, 739 CC_OP_SUBQ, 740 741 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 742 CC_OP_SBBW, 743 CC_OP_SBBL, 744 CC_OP_SBBQ, 745 746 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 747 CC_OP_LOGICW, 748 CC_OP_LOGICL, 749 CC_OP_LOGICQ, 750 751 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 752 CC_OP_INCW, 753 CC_OP_INCL, 754 CC_OP_INCQ, 755 756 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 757 CC_OP_DECW, 758 CC_OP_DECL, 759 CC_OP_DECQ, 760 761 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 762 CC_OP_SHLW, 763 CC_OP_SHLL, 764 CC_OP_SHLQ, 765 766 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 767 CC_OP_SARW, 768 CC_OP_SARL, 769 CC_OP_SARQ, 770 771 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 772 CC_OP_BMILGW, 773 CC_OP_BMILGL, 774 CC_OP_BMILGQ, 775 776 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 777 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 778 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 779 780 CC_OP_CLR, /* Z set, all other flags clear. */ 781 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 782 783 CC_OP_NB, 784 } CCOp; 785 786 typedef struct SegmentCache { 787 uint32_t selector; 788 target_ulong base; 789 uint32_t limit; 790 uint32_t flags; 791 } SegmentCache; 792 793 #define MMREG_UNION(n, bits) \ 794 union n { \ 795 uint8_t _b_##n[(bits)/8]; \ 796 uint16_t _w_##n[(bits)/16]; \ 797 uint32_t _l_##n[(bits)/32]; \ 798 uint64_t _q_##n[(bits)/64]; \ 799 float32 _s_##n[(bits)/32]; \ 800 float64 _d_##n[(bits)/64]; \ 801 } 802 803 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 804 typedef MMREG_UNION(MMXReg, 64) MMXReg; 805 806 typedef struct BNDReg { 807 uint64_t lb; 808 uint64_t ub; 809 } BNDReg; 810 811 typedef struct BNDCSReg { 812 uint64_t cfgu; 813 uint64_t sts; 814 } BNDCSReg; 815 816 #define BNDCFG_ENABLE 1ULL 817 #define BNDCFG_BNDPRESERVE 2ULL 818 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 819 820 #ifdef HOST_WORDS_BIGENDIAN 821 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 822 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 823 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 824 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 825 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 826 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 827 828 #define MMX_B(n) _b_MMXReg[7 - (n)] 829 #define MMX_W(n) _w_MMXReg[3 - (n)] 830 #define MMX_L(n) _l_MMXReg[1 - (n)] 831 #define MMX_S(n) _s_MMXReg[1 - (n)] 832 #else 833 #define ZMM_B(n) _b_ZMMReg[n] 834 #define ZMM_W(n) _w_ZMMReg[n] 835 #define ZMM_L(n) _l_ZMMReg[n] 836 #define ZMM_S(n) _s_ZMMReg[n] 837 #define ZMM_Q(n) _q_ZMMReg[n] 838 #define ZMM_D(n) _d_ZMMReg[n] 839 840 #define MMX_B(n) _b_MMXReg[n] 841 #define MMX_W(n) _w_MMXReg[n] 842 #define MMX_L(n) _l_MMXReg[n] 843 #define MMX_S(n) _s_MMXReg[n] 844 #endif 845 #define MMX_Q(n) _q_MMXReg[n] 846 847 typedef union { 848 floatx80 d __attribute__((aligned(16))); 849 MMXReg mmx; 850 } FPReg; 851 852 typedef struct { 853 uint64_t base; 854 uint64_t mask; 855 } MTRRVar; 856 857 #define CPU_NB_REGS64 16 858 #define CPU_NB_REGS32 8 859 860 #ifdef TARGET_X86_64 861 #define CPU_NB_REGS CPU_NB_REGS64 862 #else 863 #define CPU_NB_REGS CPU_NB_REGS32 864 #endif 865 866 #define MAX_FIXED_COUNTERS 3 867 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 868 869 #define NB_MMU_MODES 3 870 #define TARGET_INSN_START_EXTRA_WORDS 1 871 872 #define NB_OPMASK_REGS 8 873 874 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 875 * that APIC ID hasn't been set yet 876 */ 877 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 878 879 typedef union X86LegacyXSaveArea { 880 struct { 881 uint16_t fcw; 882 uint16_t fsw; 883 uint8_t ftw; 884 uint8_t reserved; 885 uint16_t fpop; 886 uint64_t fpip; 887 uint64_t fpdp; 888 uint32_t mxcsr; 889 uint32_t mxcsr_mask; 890 FPReg fpregs[8]; 891 uint8_t xmm_regs[16][16]; 892 }; 893 uint8_t data[512]; 894 } X86LegacyXSaveArea; 895 896 typedef struct X86XSaveHeader { 897 uint64_t xstate_bv; 898 uint64_t xcomp_bv; 899 uint64_t reserve0; 900 uint8_t reserved[40]; 901 } X86XSaveHeader; 902 903 /* Ext. save area 2: AVX State */ 904 typedef struct XSaveAVX { 905 uint8_t ymmh[16][16]; 906 } XSaveAVX; 907 908 /* Ext. save area 3: BNDREG */ 909 typedef struct XSaveBNDREG { 910 BNDReg bnd_regs[4]; 911 } XSaveBNDREG; 912 913 /* Ext. save area 4: BNDCSR */ 914 typedef union XSaveBNDCSR { 915 BNDCSReg bndcsr; 916 uint8_t data[64]; 917 } XSaveBNDCSR; 918 919 /* Ext. save area 5: Opmask */ 920 typedef struct XSaveOpmask { 921 uint64_t opmask_regs[NB_OPMASK_REGS]; 922 } XSaveOpmask; 923 924 /* Ext. save area 6: ZMM_Hi256 */ 925 typedef struct XSaveZMM_Hi256 { 926 uint8_t zmm_hi256[16][32]; 927 } XSaveZMM_Hi256; 928 929 /* Ext. save area 7: Hi16_ZMM */ 930 typedef struct XSaveHi16_ZMM { 931 uint8_t hi16_zmm[16][64]; 932 } XSaveHi16_ZMM; 933 934 /* Ext. save area 9: PKRU state */ 935 typedef struct XSavePKRU { 936 uint32_t pkru; 937 uint32_t padding; 938 } XSavePKRU; 939 940 typedef struct X86XSaveArea { 941 X86LegacyXSaveArea legacy; 942 X86XSaveHeader header; 943 944 /* Extended save areas: */ 945 946 /* AVX State: */ 947 XSaveAVX avx_state; 948 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 949 /* MPX State: */ 950 XSaveBNDREG bndreg_state; 951 XSaveBNDCSR bndcsr_state; 952 /* AVX-512 State: */ 953 XSaveOpmask opmask_state; 954 XSaveZMM_Hi256 zmm_hi256_state; 955 XSaveHi16_ZMM hi16_zmm_state; 956 /* PKRU State: */ 957 XSavePKRU pkru_state; 958 } X86XSaveArea; 959 960 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 961 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 962 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 963 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 964 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 965 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 966 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 967 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 968 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 969 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 970 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 971 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 972 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 973 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 974 975 typedef enum TPRAccess { 976 TPR_ACCESS_READ, 977 TPR_ACCESS_WRITE, 978 } TPRAccess; 979 980 typedef struct CPUX86State { 981 /* standard registers */ 982 target_ulong regs[CPU_NB_REGS]; 983 target_ulong eip; 984 target_ulong eflags; /* eflags register. During CPU emulation, CC 985 flags and DF are set to zero because they are 986 stored elsewhere */ 987 988 /* emulator internal eflags handling */ 989 target_ulong cc_dst; 990 target_ulong cc_src; 991 target_ulong cc_src2; 992 uint32_t cc_op; 993 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 994 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 995 are known at translation time. */ 996 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 997 998 /* segments */ 999 SegmentCache segs[6]; /* selector values */ 1000 SegmentCache ldt; 1001 SegmentCache tr; 1002 SegmentCache gdt; /* only base and limit are used */ 1003 SegmentCache idt; /* only base and limit are used */ 1004 1005 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1006 int32_t a20_mask; 1007 1008 BNDReg bnd_regs[4]; 1009 BNDCSReg bndcs_regs; 1010 uint64_t msr_bndcfgs; 1011 uint64_t efer; 1012 1013 /* Beginning of state preserved by INIT (dummy marker). */ 1014 struct {} start_init_save; 1015 1016 /* FPU state */ 1017 unsigned int fpstt; /* top of stack index */ 1018 uint16_t fpus; 1019 uint16_t fpuc; 1020 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1021 FPReg fpregs[8]; 1022 /* KVM-only so far */ 1023 uint16_t fpop; 1024 uint64_t fpip; 1025 uint64_t fpdp; 1026 1027 /* emulator internal variables */ 1028 float_status fp_status; 1029 floatx80 ft0; 1030 1031 float_status mmx_status; /* for 3DNow! float ops */ 1032 float_status sse_status; 1033 uint32_t mxcsr; 1034 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1035 ZMMReg xmm_t0; 1036 MMXReg mmx_t0; 1037 1038 uint64_t opmask_regs[NB_OPMASK_REGS]; 1039 1040 /* sysenter registers */ 1041 uint32_t sysenter_cs; 1042 target_ulong sysenter_esp; 1043 target_ulong sysenter_eip; 1044 uint64_t star; 1045 1046 uint64_t vm_hsave; 1047 1048 #ifdef TARGET_X86_64 1049 target_ulong lstar; 1050 target_ulong cstar; 1051 target_ulong fmask; 1052 target_ulong kernelgsbase; 1053 #endif 1054 1055 uint64_t tsc; 1056 uint64_t tsc_adjust; 1057 uint64_t tsc_deadline; 1058 uint64_t tsc_aux; 1059 1060 uint64_t xcr0; 1061 1062 uint64_t mcg_status; 1063 uint64_t msr_ia32_misc_enable; 1064 uint64_t msr_ia32_feature_control; 1065 1066 uint64_t msr_fixed_ctr_ctrl; 1067 uint64_t msr_global_ctrl; 1068 uint64_t msr_global_status; 1069 uint64_t msr_global_ovf_ctrl; 1070 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1071 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1072 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1073 1074 uint64_t pat; 1075 uint32_t smbase; 1076 1077 uint32_t pkru; 1078 1079 /* End of state preserved by INIT (dummy marker). */ 1080 struct {} end_init_save; 1081 1082 uint64_t system_time_msr; 1083 uint64_t wall_clock_msr; 1084 uint64_t steal_time_msr; 1085 uint64_t async_pf_en_msr; 1086 uint64_t pv_eoi_en_msr; 1087 1088 uint64_t msr_hv_hypercall; 1089 uint64_t msr_hv_guest_os_id; 1090 uint64_t msr_hv_vapic; 1091 uint64_t msr_hv_tsc; 1092 uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS]; 1093 uint64_t msr_hv_runtime; 1094 uint64_t msr_hv_synic_control; 1095 uint64_t msr_hv_synic_version; 1096 uint64_t msr_hv_synic_evt_page; 1097 uint64_t msr_hv_synic_msg_page; 1098 uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT]; 1099 uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT]; 1100 uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT]; 1101 1102 /* exception/interrupt handling */ 1103 int error_code; 1104 int exception_is_int; 1105 target_ulong exception_next_eip; 1106 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1107 union { 1108 struct CPUBreakpoint *cpu_breakpoint[4]; 1109 struct CPUWatchpoint *cpu_watchpoint[4]; 1110 }; /* break/watchpoints for dr[0..3] */ 1111 int old_exception; /* exception in flight */ 1112 1113 uint64_t vm_vmcb; 1114 uint64_t tsc_offset; 1115 uint64_t intercept; 1116 uint16_t intercept_cr_read; 1117 uint16_t intercept_cr_write; 1118 uint16_t intercept_dr_read; 1119 uint16_t intercept_dr_write; 1120 uint32_t intercept_exceptions; 1121 uint8_t v_tpr; 1122 1123 /* KVM states, automatically cleared on reset */ 1124 uint8_t nmi_injected; 1125 uint8_t nmi_pending; 1126 1127 /* Fields up to this point are cleared by a CPU reset */ 1128 struct {} end_reset_fields; 1129 1130 CPU_COMMON 1131 1132 /* Fields after CPU_COMMON are preserved across CPU reset. */ 1133 1134 /* processor features (e.g. for CPUID insn) */ 1135 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1136 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1137 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1138 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1139 /* Actual level/xlevel/xlevel2 value: */ 1140 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1141 uint32_t cpuid_vendor1; 1142 uint32_t cpuid_vendor2; 1143 uint32_t cpuid_vendor3; 1144 uint32_t cpuid_version; 1145 FeatureWordArray features; 1146 uint32_t cpuid_model[12]; 1147 1148 /* MTRRs */ 1149 uint64_t mtrr_fixed[11]; 1150 uint64_t mtrr_deftype; 1151 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1152 1153 /* For KVM */ 1154 uint32_t mp_state; 1155 int32_t exception_injected; 1156 int32_t interrupt_injected; 1157 uint8_t soft_interrupt; 1158 uint8_t has_error_code; 1159 uint32_t sipi_vector; 1160 bool tsc_valid; 1161 int64_t tsc_khz; 1162 int64_t user_tsc_khz; /* for sanity check only */ 1163 void *kvm_xsave_buf; 1164 1165 uint64_t mcg_cap; 1166 uint64_t mcg_ctl; 1167 uint64_t mcg_ext_ctl; 1168 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1169 uint64_t xstate_bv; 1170 1171 /* vmstate */ 1172 uint16_t fpus_vmstate; 1173 uint16_t fptag_vmstate; 1174 uint16_t fpregs_format_vmstate; 1175 1176 uint64_t xss; 1177 1178 TPRAccess tpr_access_type; 1179 } CPUX86State; 1180 1181 struct kvm_msrs; 1182 1183 /** 1184 * X86CPU: 1185 * @env: #CPUX86State 1186 * @migratable: If set, only migratable flags will be accepted when "enforce" 1187 * mode is used, and only migratable flags will be included in the "host" 1188 * CPU model. 1189 * 1190 * An x86 CPU. 1191 */ 1192 struct X86CPU { 1193 /*< private >*/ 1194 CPUState parent_obj; 1195 /*< public >*/ 1196 1197 CPUX86State env; 1198 1199 bool hyperv_vapic; 1200 bool hyperv_relaxed_timing; 1201 int hyperv_spinlock_attempts; 1202 char *hyperv_vendor_id; 1203 bool hyperv_time; 1204 bool hyperv_crash; 1205 bool hyperv_reset; 1206 bool hyperv_vpindex; 1207 bool hyperv_runtime; 1208 bool hyperv_synic; 1209 bool hyperv_stimer; 1210 bool check_cpuid; 1211 bool enforce_cpuid; 1212 bool expose_kvm; 1213 bool migratable; 1214 bool host_features; 1215 uint32_t apic_id; 1216 1217 /* if true the CPUID code directly forward host cache leaves to the guest */ 1218 bool cache_info_passthrough; 1219 1220 /* Features that were filtered out because of missing host capabilities */ 1221 uint32_t filtered_features[FEATURE_WORDS]; 1222 1223 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1224 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1225 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1226 * capabilities) directly to the guest. 1227 */ 1228 bool enable_pmu; 1229 1230 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1231 * disabled by default to avoid breaking migration between QEMU with 1232 * different LMCE configurations. 1233 */ 1234 bool enable_lmce; 1235 1236 /* Compatibility bits for old machine types. 1237 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1238 * socket share an virtual l3 cache. 1239 */ 1240 bool enable_l3_cache; 1241 1242 /* Compatibility bits for old machine types: */ 1243 bool enable_cpuid_0xb; 1244 1245 /* Enable auto level-increase for all CPUID leaves */ 1246 bool full_cpuid_auto_level; 1247 1248 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1249 bool fill_mtrr_mask; 1250 1251 /* if true override the phys_bits value with a value read from the host */ 1252 bool host_phys_bits; 1253 1254 /* Number of physical address bits supported */ 1255 uint32_t phys_bits; 1256 1257 /* in order to simplify APIC support, we leave this pointer to the 1258 user */ 1259 struct DeviceState *apic_state; 1260 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1261 Notifier machine_done; 1262 1263 struct kvm_msrs *kvm_msr_buf; 1264 1265 int32_t socket_id; 1266 int32_t core_id; 1267 int32_t thread_id; 1268 }; 1269 1270 static inline X86CPU *x86_env_get_cpu(CPUX86State *env) 1271 { 1272 return container_of(env, X86CPU, env); 1273 } 1274 1275 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) 1276 1277 #define ENV_OFFSET offsetof(X86CPU, env) 1278 1279 #ifndef CONFIG_USER_ONLY 1280 extern struct VMStateDescription vmstate_x86_cpu; 1281 #endif 1282 1283 /** 1284 * x86_cpu_do_interrupt: 1285 * @cpu: vCPU the interrupt is to be handled by. 1286 */ 1287 void x86_cpu_do_interrupt(CPUState *cpu); 1288 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1289 1290 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1291 int cpuid, void *opaque); 1292 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1293 int cpuid, void *opaque); 1294 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1295 void *opaque); 1296 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1297 void *opaque); 1298 1299 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1300 Error **errp); 1301 1302 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 1303 int flags); 1304 1305 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1306 1307 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1308 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1309 1310 void x86_cpu_exec_enter(CPUState *cpu); 1311 void x86_cpu_exec_exit(CPUState *cpu); 1312 1313 X86CPU *cpu_x86_init(const char *cpu_model); 1314 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1315 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1316 1317 int cpu_get_pic_interrupt(CPUX86State *s); 1318 /* MSDOS compatibility mode FPU exception support */ 1319 void cpu_set_ferr(CPUX86State *s); 1320 1321 /* this function must always be used to load data in the segment 1322 cache: it synchronizes the hflags with the segment cache values */ 1323 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1324 int seg_reg, unsigned int selector, 1325 target_ulong base, 1326 unsigned int limit, 1327 unsigned int flags) 1328 { 1329 SegmentCache *sc; 1330 unsigned int new_hflags; 1331 1332 sc = &env->segs[seg_reg]; 1333 sc->selector = selector; 1334 sc->base = base; 1335 sc->limit = limit; 1336 sc->flags = flags; 1337 1338 /* update the hidden flags */ 1339 { 1340 if (seg_reg == R_CS) { 1341 #ifdef TARGET_X86_64 1342 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1343 /* long mode */ 1344 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1345 env->hflags &= ~(HF_ADDSEG_MASK); 1346 } else 1347 #endif 1348 { 1349 /* legacy / compatibility case */ 1350 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1351 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1352 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1353 new_hflags; 1354 } 1355 } 1356 if (seg_reg == R_SS) { 1357 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1358 #if HF_CPL_MASK != 3 1359 #error HF_CPL_MASK is hardcoded 1360 #endif 1361 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1362 } 1363 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1364 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1365 if (env->hflags & HF_CS64_MASK) { 1366 /* zero base assumed for DS, ES and SS in long mode */ 1367 } else if (!(env->cr[0] & CR0_PE_MASK) || 1368 (env->eflags & VM_MASK) || 1369 !(env->hflags & HF_CS32_MASK)) { 1370 /* XXX: try to avoid this test. The problem comes from the 1371 fact that is real mode or vm86 mode we only modify the 1372 'base' and 'selector' fields of the segment cache to go 1373 faster. A solution may be to force addseg to one in 1374 translate-i386.c. */ 1375 new_hflags |= HF_ADDSEG_MASK; 1376 } else { 1377 new_hflags |= ((env->segs[R_DS].base | 1378 env->segs[R_ES].base | 1379 env->segs[R_SS].base) != 0) << 1380 HF_ADDSEG_SHIFT; 1381 } 1382 env->hflags = (env->hflags & 1383 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1384 } 1385 } 1386 1387 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1388 uint8_t sipi_vector) 1389 { 1390 CPUState *cs = CPU(cpu); 1391 CPUX86State *env = &cpu->env; 1392 1393 env->eip = 0; 1394 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1395 sipi_vector << 12, 1396 env->segs[R_CS].limit, 1397 env->segs[R_CS].flags); 1398 cs->halted = 0; 1399 } 1400 1401 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1402 target_ulong *base, unsigned int *limit, 1403 unsigned int *flags); 1404 1405 /* op_helper.c */ 1406 /* used for debug or cpu save/restore */ 1407 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f); 1408 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); 1409 1410 /* cpu-exec.c */ 1411 /* the following helpers are only usable in user mode simulation as 1412 they can trigger unexpected exceptions */ 1413 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1414 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1415 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1416 1417 /* you can call this signal handler from your SIGBUS and SIGSEGV 1418 signal handlers to inform the virtual CPU of exceptions. non zero 1419 is returned if the signal was handled by the virtual CPU. */ 1420 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1421 void *puc); 1422 1423 /* cpu.c */ 1424 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1425 uint32_t *eax, uint32_t *ebx, 1426 uint32_t *ecx, uint32_t *edx); 1427 void cpu_clear_apic_feature(CPUX86State *env); 1428 void host_cpuid(uint32_t function, uint32_t count, 1429 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1430 1431 /* helper.c */ 1432 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, 1433 int is_write, int mmu_idx); 1434 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1435 1436 #ifndef CONFIG_USER_ONLY 1437 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1438 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1439 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1440 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1441 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1442 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1443 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1444 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1445 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1446 #endif 1447 1448 void breakpoint_handler(CPUState *cs); 1449 1450 /* will be suppressed */ 1451 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1452 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1453 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1454 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1455 1456 /* hw/pc.c */ 1457 uint64_t cpu_get_tsc(CPUX86State *env); 1458 1459 #define TARGET_PAGE_BITS 12 1460 1461 #ifdef TARGET_X86_64 1462 #define TARGET_PHYS_ADDR_SPACE_BITS 52 1463 /* ??? This is really 48 bits, sign-extended, but the only thing 1464 accessible to userland with bit 48 set is the VSYSCALL, and that 1465 is handled via other mechanisms. */ 1466 #define TARGET_VIRT_ADDR_SPACE_BITS 47 1467 #else 1468 #define TARGET_PHYS_ADDR_SPACE_BITS 36 1469 #define TARGET_VIRT_ADDR_SPACE_BITS 32 1470 #endif 1471 1472 /* XXX: This value should match the one returned by CPUID 1473 * and in exec.c */ 1474 # if defined(TARGET_X86_64) 1475 # define TCG_PHYS_ADDR_BITS 40 1476 # else 1477 # define TCG_PHYS_ADDR_BITS 36 1478 # endif 1479 1480 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1481 1482 #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model)) 1483 1484 #define cpu_signal_handler cpu_x86_signal_handler 1485 #define cpu_list x86_cpu_list 1486 1487 /* MMU modes definitions */ 1488 #define MMU_MODE0_SUFFIX _ksmap 1489 #define MMU_MODE1_SUFFIX _user 1490 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1491 #define MMU_KSMAP_IDX 0 1492 #define MMU_USER_IDX 1 1493 #define MMU_KNOSMAP_IDX 2 1494 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1495 { 1496 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1497 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1498 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1499 } 1500 1501 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1502 { 1503 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1504 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1505 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1506 } 1507 1508 #define CC_DST (env->cc_dst) 1509 #define CC_SRC (env->cc_src) 1510 #define CC_SRC2 (env->cc_src2) 1511 #define CC_OP (env->cc_op) 1512 1513 /* n must be a constant to be efficient */ 1514 static inline target_long lshift(target_long x, int n) 1515 { 1516 if (n >= 0) { 1517 return x << n; 1518 } else { 1519 return x >> (-n); 1520 } 1521 } 1522 1523 /* float macros */ 1524 #define FT0 (env->ft0) 1525 #define ST0 (env->fpregs[env->fpstt].d) 1526 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1527 #define ST1 ST(1) 1528 1529 /* translate.c */ 1530 void tcg_x86_init(void); 1531 1532 #include "exec/cpu-all.h" 1533 #include "svm.h" 1534 1535 #if !defined(CONFIG_USER_ONLY) 1536 #include "hw/i386/apic.h" 1537 #endif 1538 1539 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1540 target_ulong *cs_base, uint32_t *flags) 1541 { 1542 *cs_base = env->segs[R_CS].base; 1543 *pc = *cs_base + env->eip; 1544 *flags = env->hflags | 1545 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1546 } 1547 1548 void do_cpu_init(X86CPU *cpu); 1549 void do_cpu_sipi(X86CPU *cpu); 1550 1551 #define MCE_INJECT_BROADCAST 1 1552 #define MCE_INJECT_UNCOND_AO 2 1553 1554 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1555 uint64_t status, uint64_t mcg_status, uint64_t addr, 1556 uint64_t misc, int flags); 1557 1558 /* excp_helper.c */ 1559 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1560 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1561 uintptr_t retaddr); 1562 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1563 int error_code); 1564 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1565 int error_code, uintptr_t retaddr); 1566 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1567 int error_code, int next_eip_addend); 1568 1569 /* cc_helper.c */ 1570 extern const uint8_t parity_table[256]; 1571 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1572 void update_fp_status(CPUX86State *env); 1573 1574 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1575 { 1576 return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 1577 } 1578 1579 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1580 * after generating a call to a helper that uses this. 1581 */ 1582 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1583 int update_mask) 1584 { 1585 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1586 CC_OP = CC_OP_EFLAGS; 1587 env->df = 1 - (2 * ((eflags >> 10) & 1)); 1588 env->eflags = (env->eflags & ~update_mask) | 1589 (eflags & update_mask) | 0x2; 1590 } 1591 1592 /* load efer and update the corresponding hflags. XXX: do consistency 1593 checks with cpuid bits? */ 1594 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1595 { 1596 env->efer = val; 1597 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1598 if (env->efer & MSR_EFER_LMA) { 1599 env->hflags |= HF_LMA_MASK; 1600 } 1601 if (env->efer & MSR_EFER_SVME) { 1602 env->hflags |= HF_SVME_MASK; 1603 } 1604 } 1605 1606 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 1607 { 1608 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 1609 } 1610 1611 /* fpu_helper.c */ 1612 void cpu_set_mxcsr(CPUX86State *env, uint32_t val); 1613 void cpu_set_fpuc(CPUX86State *env, uint16_t val); 1614 1615 /* mem_helper.c */ 1616 void helper_lock_init(void); 1617 1618 /* svm_helper.c */ 1619 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 1620 uint64_t param); 1621 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1); 1622 1623 /* seg_helper.c */ 1624 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 1625 1626 /* smm_helper.c */ 1627 void do_smm_enter(X86CPU *cpu); 1628 void cpu_smm_update(X86CPU *cpu); 1629 1630 /* apic.c */ 1631 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 1632 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 1633 TPRAccess access); 1634 1635 1636 /* Change the value of a KVM-specific default 1637 * 1638 * If value is NULL, no default will be set and the original 1639 * value from the CPU model table will be kept. 1640 * 1641 * It is valid to call this function only for properties that 1642 * are already present in the kvm_default_props table. 1643 */ 1644 void x86_cpu_change_kvm_default(const char *prop, const char *value); 1645 1646 /* mpx_helper.c */ 1647 void cpu_sync_bndcs_hflags(CPUX86State *env); 1648 1649 /* Return name of 32-bit register, from a R_* constant */ 1650 const char *get_register_name_32(unsigned int reg); 1651 1652 void enable_compat_apic_id_mode(void); 1653 1654 #define APIC_DEFAULT_ADDRESS 0xfee00000 1655 #define APIC_SPACE_SIZE 0x100000 1656 1657 void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, 1658 fprintf_function cpu_fprintf, int flags); 1659 1660 /* cpu.c */ 1661 bool cpu_is_bsp(X86CPU *cpu); 1662 1663 #endif /* I386_CPU_H */ 1664