1 2 /* 3 * i386 virtual CPU header 4 * 5 * Copyright (c) 2003 Fabrice Bellard 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef I386_CPU_H 22 #define I386_CPU_H 23 24 #include "qemu-common.h" 25 #include "cpu-qom.h" 26 #include "hyperv-proto.h" 27 #include "exec/cpu-defs.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 /* Maximum instruction code size */ 33 #define TARGET_MAX_INSN_SIZE 16 34 35 /* support for self modifying code even if the modified instruction is 36 close to the modifying instruction */ 37 #define TARGET_HAS_PRECISE_SMC 38 39 #ifdef TARGET_X86_64 40 #define I386_ELF_MACHINE EM_X86_64 41 #define ELF_MACHINE_UNAME "x86_64" 42 #else 43 #define I386_ELF_MACHINE EM_386 44 #define ELF_MACHINE_UNAME "i686" 45 #endif 46 47 #define CPUArchState struct CPUX86State 48 49 enum { 50 R_EAX = 0, 51 R_ECX = 1, 52 R_EDX = 2, 53 R_EBX = 3, 54 R_ESP = 4, 55 R_EBP = 5, 56 R_ESI = 6, 57 R_EDI = 7, 58 R_R8 = 8, 59 R_R9 = 9, 60 R_R10 = 10, 61 R_R11 = 11, 62 R_R12 = 12, 63 R_R13 = 13, 64 R_R14 = 14, 65 R_R15 = 15, 66 67 R_AL = 0, 68 R_CL = 1, 69 R_DL = 2, 70 R_BL = 3, 71 R_AH = 4, 72 R_CH = 5, 73 R_DH = 6, 74 R_BH = 7, 75 }; 76 77 typedef enum X86Seg { 78 R_ES = 0, 79 R_CS = 1, 80 R_SS = 2, 81 R_DS = 3, 82 R_FS = 4, 83 R_GS = 5, 84 R_LDTR = 6, 85 R_TR = 7, 86 } X86Seg; 87 88 /* segment descriptor fields */ 89 #define DESC_G_SHIFT 23 90 #define DESC_G_MASK (1 << DESC_G_SHIFT) 91 #define DESC_B_SHIFT 22 92 #define DESC_B_MASK (1 << DESC_B_SHIFT) 93 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 94 #define DESC_L_MASK (1 << DESC_L_SHIFT) 95 #define DESC_AVL_SHIFT 20 96 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 97 #define DESC_P_SHIFT 15 98 #define DESC_P_MASK (1 << DESC_P_SHIFT) 99 #define DESC_DPL_SHIFT 13 100 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 101 #define DESC_S_SHIFT 12 102 #define DESC_S_MASK (1 << DESC_S_SHIFT) 103 #define DESC_TYPE_SHIFT 8 104 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 105 #define DESC_A_MASK (1 << 8) 106 107 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 108 #define DESC_C_MASK (1 << 10) /* code: conforming */ 109 #define DESC_R_MASK (1 << 9) /* code: readable */ 110 111 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 112 #define DESC_W_MASK (1 << 9) /* data: writable */ 113 114 #define DESC_TSS_BUSY_MASK (1 << 9) 115 116 /* eflags masks */ 117 #define CC_C 0x0001 118 #define CC_P 0x0004 119 #define CC_A 0x0010 120 #define CC_Z 0x0040 121 #define CC_S 0x0080 122 #define CC_O 0x0800 123 124 #define TF_SHIFT 8 125 #define IOPL_SHIFT 12 126 #define VM_SHIFT 17 127 128 #define TF_MASK 0x00000100 129 #define IF_MASK 0x00000200 130 #define DF_MASK 0x00000400 131 #define IOPL_MASK 0x00003000 132 #define NT_MASK 0x00004000 133 #define RF_MASK 0x00010000 134 #define VM_MASK 0x00020000 135 #define AC_MASK 0x00040000 136 #define VIF_MASK 0x00080000 137 #define VIP_MASK 0x00100000 138 #define ID_MASK 0x00200000 139 140 /* hidden flags - used internally by qemu to represent additional cpu 141 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 142 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 143 positions to ease oring with eflags. */ 144 /* current cpl */ 145 #define HF_CPL_SHIFT 0 146 /* true if hardware interrupts must be disabled for next instruction */ 147 #define HF_INHIBIT_IRQ_SHIFT 3 148 /* 16 or 32 segments */ 149 #define HF_CS32_SHIFT 4 150 #define HF_SS32_SHIFT 5 151 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 152 #define HF_ADDSEG_SHIFT 6 153 /* copy of CR0.PE (protected mode) */ 154 #define HF_PE_SHIFT 7 155 #define HF_TF_SHIFT 8 /* must be same as eflags */ 156 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 157 #define HF_EM_SHIFT 10 158 #define HF_TS_SHIFT 11 159 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 160 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 161 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 162 #define HF_RF_SHIFT 16 /* must be same as eflags */ 163 #define HF_VM_SHIFT 17 /* must be same as eflags */ 164 #define HF_AC_SHIFT 18 /* must be same as eflags */ 165 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 166 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 167 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 168 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 169 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 170 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 171 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 172 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 173 174 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 175 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 176 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 177 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 178 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 179 #define HF_PE_MASK (1 << HF_PE_SHIFT) 180 #define HF_TF_MASK (1 << HF_TF_SHIFT) 181 #define HF_MP_MASK (1 << HF_MP_SHIFT) 182 #define HF_EM_MASK (1 << HF_EM_SHIFT) 183 #define HF_TS_MASK (1 << HF_TS_SHIFT) 184 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 185 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 186 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 187 #define HF_RF_MASK (1 << HF_RF_SHIFT) 188 #define HF_VM_MASK (1 << HF_VM_SHIFT) 189 #define HF_AC_MASK (1 << HF_AC_SHIFT) 190 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 191 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 192 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 193 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 194 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 195 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 196 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 197 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 198 199 /* hflags2 */ 200 201 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 202 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 203 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 204 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 205 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 206 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 207 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 208 209 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 210 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 211 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 212 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 213 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 214 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 215 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 216 217 #define CR0_PE_SHIFT 0 218 #define CR0_MP_SHIFT 1 219 220 #define CR0_PE_MASK (1U << 0) 221 #define CR0_MP_MASK (1U << 1) 222 #define CR0_EM_MASK (1U << 2) 223 #define CR0_TS_MASK (1U << 3) 224 #define CR0_ET_MASK (1U << 4) 225 #define CR0_NE_MASK (1U << 5) 226 #define CR0_WP_MASK (1U << 16) 227 #define CR0_AM_MASK (1U << 18) 228 #define CR0_PG_MASK (1U << 31) 229 230 #define CR4_VME_MASK (1U << 0) 231 #define CR4_PVI_MASK (1U << 1) 232 #define CR4_TSD_MASK (1U << 2) 233 #define CR4_DE_MASK (1U << 3) 234 #define CR4_PSE_MASK (1U << 4) 235 #define CR4_PAE_MASK (1U << 5) 236 #define CR4_MCE_MASK (1U << 6) 237 #define CR4_PGE_MASK (1U << 7) 238 #define CR4_PCE_MASK (1U << 8) 239 #define CR4_OSFXSR_SHIFT 9 240 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 241 #define CR4_OSXMMEXCPT_MASK (1U << 10) 242 #define CR4_LA57_MASK (1U << 12) 243 #define CR4_VMXE_MASK (1U << 13) 244 #define CR4_SMXE_MASK (1U << 14) 245 #define CR4_FSGSBASE_MASK (1U << 16) 246 #define CR4_PCIDE_MASK (1U << 17) 247 #define CR4_OSXSAVE_MASK (1U << 18) 248 #define CR4_SMEP_MASK (1U << 20) 249 #define CR4_SMAP_MASK (1U << 21) 250 #define CR4_PKE_MASK (1U << 22) 251 252 #define DR6_BD (1 << 13) 253 #define DR6_BS (1 << 14) 254 #define DR6_BT (1 << 15) 255 #define DR6_FIXED_1 0xffff0ff0 256 257 #define DR7_GD (1 << 13) 258 #define DR7_TYPE_SHIFT 16 259 #define DR7_LEN_SHIFT 18 260 #define DR7_FIXED_1 0x00000400 261 #define DR7_GLOBAL_BP_MASK 0xaa 262 #define DR7_LOCAL_BP_MASK 0x55 263 #define DR7_MAX_BP 4 264 #define DR7_TYPE_BP_INST 0x0 265 #define DR7_TYPE_DATA_WR 0x1 266 #define DR7_TYPE_IO_RW 0x2 267 #define DR7_TYPE_DATA_RW 0x3 268 269 #define PG_PRESENT_BIT 0 270 #define PG_RW_BIT 1 271 #define PG_USER_BIT 2 272 #define PG_PWT_BIT 3 273 #define PG_PCD_BIT 4 274 #define PG_ACCESSED_BIT 5 275 #define PG_DIRTY_BIT 6 276 #define PG_PSE_BIT 7 277 #define PG_GLOBAL_BIT 8 278 #define PG_PSE_PAT_BIT 12 279 #define PG_PKRU_BIT 59 280 #define PG_NX_BIT 63 281 282 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 283 #define PG_RW_MASK (1 << PG_RW_BIT) 284 #define PG_USER_MASK (1 << PG_USER_BIT) 285 #define PG_PWT_MASK (1 << PG_PWT_BIT) 286 #define PG_PCD_MASK (1 << PG_PCD_BIT) 287 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 288 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 289 #define PG_PSE_MASK (1 << PG_PSE_BIT) 290 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 291 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 292 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 293 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 294 #define PG_HI_USER_MASK 0x7ff0000000000000LL 295 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 296 #define PG_NX_MASK (1ULL << PG_NX_BIT) 297 298 #define PG_ERROR_W_BIT 1 299 300 #define PG_ERROR_P_MASK 0x01 301 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 302 #define PG_ERROR_U_MASK 0x04 303 #define PG_ERROR_RSVD_MASK 0x08 304 #define PG_ERROR_I_D_MASK 0x10 305 #define PG_ERROR_PK_MASK 0x20 306 307 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 308 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 309 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 310 311 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 312 #define MCE_BANKS_DEF 10 313 314 #define MCG_CAP_BANKS_MASK 0xff 315 316 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 317 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 318 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 319 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 320 321 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 322 323 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 324 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 325 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 326 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 327 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 328 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 329 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 330 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 331 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 332 333 /* MISC register defines */ 334 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 335 #define MCM_ADDR_LINEAR 1 /* linear address */ 336 #define MCM_ADDR_PHYS 2 /* physical address */ 337 #define MCM_ADDR_MEM 3 /* memory address */ 338 #define MCM_ADDR_GENERIC 7 /* generic */ 339 340 #define MSR_IA32_TSC 0x10 341 #define MSR_IA32_APICBASE 0x1b 342 #define MSR_IA32_APICBASE_BSP (1<<8) 343 #define MSR_IA32_APICBASE_ENABLE (1<<11) 344 #define MSR_IA32_APICBASE_EXTD (1 << 10) 345 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 346 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 347 #define MSR_TSC_ADJUST 0x0000003b 348 #define MSR_IA32_SPEC_CTRL 0x48 349 #define MSR_VIRT_SSBD 0xc001011f 350 #define MSR_IA32_PRED_CMD 0x49 351 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 352 #define MSR_IA32_TSCDEADLINE 0x6e0 353 354 #define FEATURE_CONTROL_LOCKED (1<<0) 355 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 356 #define FEATURE_CONTROL_LMCE (1<<20) 357 358 #define MSR_P6_PERFCTR0 0xc1 359 360 #define MSR_IA32_SMBASE 0x9e 361 #define MSR_SMI_COUNT 0x34 362 #define MSR_MTRRcap 0xfe 363 #define MSR_MTRRcap_VCNT 8 364 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 365 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 366 367 #define MSR_IA32_SYSENTER_CS 0x174 368 #define MSR_IA32_SYSENTER_ESP 0x175 369 #define MSR_IA32_SYSENTER_EIP 0x176 370 371 #define MSR_MCG_CAP 0x179 372 #define MSR_MCG_STATUS 0x17a 373 #define MSR_MCG_CTL 0x17b 374 #define MSR_MCG_EXT_CTL 0x4d0 375 376 #define MSR_P6_EVNTSEL0 0x186 377 378 #define MSR_IA32_PERF_STATUS 0x198 379 380 #define MSR_IA32_MISC_ENABLE 0x1a0 381 /* Indicates good rep/movs microcode on some processors: */ 382 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 383 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 384 385 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 386 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 387 388 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 389 390 #define MSR_MTRRfix64K_00000 0x250 391 #define MSR_MTRRfix16K_80000 0x258 392 #define MSR_MTRRfix16K_A0000 0x259 393 #define MSR_MTRRfix4K_C0000 0x268 394 #define MSR_MTRRfix4K_C8000 0x269 395 #define MSR_MTRRfix4K_D0000 0x26a 396 #define MSR_MTRRfix4K_D8000 0x26b 397 #define MSR_MTRRfix4K_E0000 0x26c 398 #define MSR_MTRRfix4K_E8000 0x26d 399 #define MSR_MTRRfix4K_F0000 0x26e 400 #define MSR_MTRRfix4K_F8000 0x26f 401 402 #define MSR_PAT 0x277 403 404 #define MSR_MTRRdefType 0x2ff 405 406 #define MSR_CORE_PERF_FIXED_CTR0 0x309 407 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 408 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 409 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 410 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 411 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 412 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 413 414 #define MSR_MC0_CTL 0x400 415 #define MSR_MC0_STATUS 0x401 416 #define MSR_MC0_ADDR 0x402 417 #define MSR_MC0_MISC 0x403 418 419 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 420 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 421 #define MSR_IA32_RTIT_CTL 0x570 422 #define MSR_IA32_RTIT_STATUS 0x571 423 #define MSR_IA32_RTIT_CR3_MATCH 0x572 424 #define MSR_IA32_RTIT_ADDR0_A 0x580 425 #define MSR_IA32_RTIT_ADDR0_B 0x581 426 #define MSR_IA32_RTIT_ADDR1_A 0x582 427 #define MSR_IA32_RTIT_ADDR1_B 0x583 428 #define MSR_IA32_RTIT_ADDR2_A 0x584 429 #define MSR_IA32_RTIT_ADDR2_B 0x585 430 #define MSR_IA32_RTIT_ADDR3_A 0x586 431 #define MSR_IA32_RTIT_ADDR3_B 0x587 432 #define MAX_RTIT_ADDRS 8 433 434 #define MSR_EFER 0xc0000080 435 436 #define MSR_EFER_SCE (1 << 0) 437 #define MSR_EFER_LME (1 << 8) 438 #define MSR_EFER_LMA (1 << 10) 439 #define MSR_EFER_NXE (1 << 11) 440 #define MSR_EFER_SVME (1 << 12) 441 #define MSR_EFER_FFXSR (1 << 14) 442 443 #define MSR_STAR 0xc0000081 444 #define MSR_LSTAR 0xc0000082 445 #define MSR_CSTAR 0xc0000083 446 #define MSR_FMASK 0xc0000084 447 #define MSR_FSBASE 0xc0000100 448 #define MSR_GSBASE 0xc0000101 449 #define MSR_KERNELGSBASE 0xc0000102 450 #define MSR_TSC_AUX 0xc0000103 451 452 #define MSR_VM_HSAVE_PA 0xc0010117 453 454 #define MSR_IA32_BNDCFGS 0x00000d90 455 #define MSR_IA32_XSS 0x00000da0 456 457 #define XSTATE_FP_BIT 0 458 #define XSTATE_SSE_BIT 1 459 #define XSTATE_YMM_BIT 2 460 #define XSTATE_BNDREGS_BIT 3 461 #define XSTATE_BNDCSR_BIT 4 462 #define XSTATE_OPMASK_BIT 5 463 #define XSTATE_ZMM_Hi256_BIT 6 464 #define XSTATE_Hi16_ZMM_BIT 7 465 #define XSTATE_PKRU_BIT 9 466 467 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 468 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 469 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 470 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 471 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 472 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 473 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 474 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 475 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 476 477 /* CPUID feature words */ 478 typedef enum FeatureWord { 479 FEAT_1_EDX, /* CPUID[1].EDX */ 480 FEAT_1_ECX, /* CPUID[1].ECX */ 481 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 482 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 483 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 484 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 485 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 486 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 487 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 488 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 489 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 490 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 491 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 492 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 493 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 494 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ 495 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ 496 FEAT_SVM, /* CPUID[8000_000A].EDX */ 497 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 498 FEAT_6_EAX, /* CPUID[6].EAX */ 499 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 500 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 501 FEAT_ARCH_CAPABILITIES, 502 FEATURE_WORDS, 503 } FeatureWord; 504 505 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 506 507 /* cpuid_features bits */ 508 #define CPUID_FP87 (1U << 0) 509 #define CPUID_VME (1U << 1) 510 #define CPUID_DE (1U << 2) 511 #define CPUID_PSE (1U << 3) 512 #define CPUID_TSC (1U << 4) 513 #define CPUID_MSR (1U << 5) 514 #define CPUID_PAE (1U << 6) 515 #define CPUID_MCE (1U << 7) 516 #define CPUID_CX8 (1U << 8) 517 #define CPUID_APIC (1U << 9) 518 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 519 #define CPUID_MTRR (1U << 12) 520 #define CPUID_PGE (1U << 13) 521 #define CPUID_MCA (1U << 14) 522 #define CPUID_CMOV (1U << 15) 523 #define CPUID_PAT (1U << 16) 524 #define CPUID_PSE36 (1U << 17) 525 #define CPUID_PN (1U << 18) 526 #define CPUID_CLFLUSH (1U << 19) 527 #define CPUID_DTS (1U << 21) 528 #define CPUID_ACPI (1U << 22) 529 #define CPUID_MMX (1U << 23) 530 #define CPUID_FXSR (1U << 24) 531 #define CPUID_SSE (1U << 25) 532 #define CPUID_SSE2 (1U << 26) 533 #define CPUID_SS (1U << 27) 534 #define CPUID_HT (1U << 28) 535 #define CPUID_TM (1U << 29) 536 #define CPUID_IA64 (1U << 30) 537 #define CPUID_PBE (1U << 31) 538 539 #define CPUID_EXT_SSE3 (1U << 0) 540 #define CPUID_EXT_PCLMULQDQ (1U << 1) 541 #define CPUID_EXT_DTES64 (1U << 2) 542 #define CPUID_EXT_MONITOR (1U << 3) 543 #define CPUID_EXT_DSCPL (1U << 4) 544 #define CPUID_EXT_VMX (1U << 5) 545 #define CPUID_EXT_SMX (1U << 6) 546 #define CPUID_EXT_EST (1U << 7) 547 #define CPUID_EXT_TM2 (1U << 8) 548 #define CPUID_EXT_SSSE3 (1U << 9) 549 #define CPUID_EXT_CID (1U << 10) 550 #define CPUID_EXT_FMA (1U << 12) 551 #define CPUID_EXT_CX16 (1U << 13) 552 #define CPUID_EXT_XTPR (1U << 14) 553 #define CPUID_EXT_PDCM (1U << 15) 554 #define CPUID_EXT_PCID (1U << 17) 555 #define CPUID_EXT_DCA (1U << 18) 556 #define CPUID_EXT_SSE41 (1U << 19) 557 #define CPUID_EXT_SSE42 (1U << 20) 558 #define CPUID_EXT_X2APIC (1U << 21) 559 #define CPUID_EXT_MOVBE (1U << 22) 560 #define CPUID_EXT_POPCNT (1U << 23) 561 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 562 #define CPUID_EXT_AES (1U << 25) 563 #define CPUID_EXT_XSAVE (1U << 26) 564 #define CPUID_EXT_OSXSAVE (1U << 27) 565 #define CPUID_EXT_AVX (1U << 28) 566 #define CPUID_EXT_F16C (1U << 29) 567 #define CPUID_EXT_RDRAND (1U << 30) 568 #define CPUID_EXT_HYPERVISOR (1U << 31) 569 570 #define CPUID_EXT2_FPU (1U << 0) 571 #define CPUID_EXT2_VME (1U << 1) 572 #define CPUID_EXT2_DE (1U << 2) 573 #define CPUID_EXT2_PSE (1U << 3) 574 #define CPUID_EXT2_TSC (1U << 4) 575 #define CPUID_EXT2_MSR (1U << 5) 576 #define CPUID_EXT2_PAE (1U << 6) 577 #define CPUID_EXT2_MCE (1U << 7) 578 #define CPUID_EXT2_CX8 (1U << 8) 579 #define CPUID_EXT2_APIC (1U << 9) 580 #define CPUID_EXT2_SYSCALL (1U << 11) 581 #define CPUID_EXT2_MTRR (1U << 12) 582 #define CPUID_EXT2_PGE (1U << 13) 583 #define CPUID_EXT2_MCA (1U << 14) 584 #define CPUID_EXT2_CMOV (1U << 15) 585 #define CPUID_EXT2_PAT (1U << 16) 586 #define CPUID_EXT2_PSE36 (1U << 17) 587 #define CPUID_EXT2_MP (1U << 19) 588 #define CPUID_EXT2_NX (1U << 20) 589 #define CPUID_EXT2_MMXEXT (1U << 22) 590 #define CPUID_EXT2_MMX (1U << 23) 591 #define CPUID_EXT2_FXSR (1U << 24) 592 #define CPUID_EXT2_FFXSR (1U << 25) 593 #define CPUID_EXT2_PDPE1GB (1U << 26) 594 #define CPUID_EXT2_RDTSCP (1U << 27) 595 #define CPUID_EXT2_LM (1U << 29) 596 #define CPUID_EXT2_3DNOWEXT (1U << 30) 597 #define CPUID_EXT2_3DNOW (1U << 31) 598 599 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 600 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 601 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 602 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 603 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 604 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 605 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 606 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 607 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 608 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 609 610 #define CPUID_EXT3_LAHF_LM (1U << 0) 611 #define CPUID_EXT3_CMP_LEG (1U << 1) 612 #define CPUID_EXT3_SVM (1U << 2) 613 #define CPUID_EXT3_EXTAPIC (1U << 3) 614 #define CPUID_EXT3_CR8LEG (1U << 4) 615 #define CPUID_EXT3_ABM (1U << 5) 616 #define CPUID_EXT3_SSE4A (1U << 6) 617 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 618 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 619 #define CPUID_EXT3_OSVW (1U << 9) 620 #define CPUID_EXT3_IBS (1U << 10) 621 #define CPUID_EXT3_XOP (1U << 11) 622 #define CPUID_EXT3_SKINIT (1U << 12) 623 #define CPUID_EXT3_WDT (1U << 13) 624 #define CPUID_EXT3_LWP (1U << 15) 625 #define CPUID_EXT3_FMA4 (1U << 16) 626 #define CPUID_EXT3_TCE (1U << 17) 627 #define CPUID_EXT3_NODEID (1U << 19) 628 #define CPUID_EXT3_TBM (1U << 21) 629 #define CPUID_EXT3_TOPOEXT (1U << 22) 630 #define CPUID_EXT3_PERFCORE (1U << 23) 631 #define CPUID_EXT3_PERFNB (1U << 24) 632 633 #define CPUID_SVM_NPT (1U << 0) 634 #define CPUID_SVM_LBRV (1U << 1) 635 #define CPUID_SVM_SVMLOCK (1U << 2) 636 #define CPUID_SVM_NRIPSAVE (1U << 3) 637 #define CPUID_SVM_TSCSCALE (1U << 4) 638 #define CPUID_SVM_VMCBCLEAN (1U << 5) 639 #define CPUID_SVM_FLUSHASID (1U << 6) 640 #define CPUID_SVM_DECODEASSIST (1U << 7) 641 #define CPUID_SVM_PAUSEFILTER (1U << 10) 642 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 643 644 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 645 #define CPUID_7_0_EBX_BMI1 (1U << 3) 646 #define CPUID_7_0_EBX_HLE (1U << 4) 647 #define CPUID_7_0_EBX_AVX2 (1U << 5) 648 #define CPUID_7_0_EBX_SMEP (1U << 7) 649 #define CPUID_7_0_EBX_BMI2 (1U << 8) 650 #define CPUID_7_0_EBX_ERMS (1U << 9) 651 #define CPUID_7_0_EBX_INVPCID (1U << 10) 652 #define CPUID_7_0_EBX_RTM (1U << 11) 653 #define CPUID_7_0_EBX_MPX (1U << 14) 654 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 655 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 656 #define CPUID_7_0_EBX_RDSEED (1U << 18) 657 #define CPUID_7_0_EBX_ADX (1U << 19) 658 #define CPUID_7_0_EBX_SMAP (1U << 20) 659 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 660 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 661 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 662 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 663 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */ 664 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 665 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 666 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 667 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 668 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 669 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 670 671 #define CPUID_7_0_ECX_AVX512BMI (1U << 1) 672 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 673 #define CPUID_7_0_ECX_UMIP (1U << 2) 674 #define CPUID_7_0_ECX_PKU (1U << 3) 675 #define CPUID_7_0_ECX_OSPKE (1U << 4) 676 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ 677 #define CPUID_7_0_ECX_GFNI (1U << 8) 678 #define CPUID_7_0_ECX_VAES (1U << 9) 679 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 680 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 681 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 682 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 683 #define CPUID_7_0_ECX_LA57 (1U << 16) 684 #define CPUID_7_0_ECX_RDPID (1U << 22) 685 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ 686 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ 687 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ 688 689 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 690 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 691 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ 692 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ 693 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ 694 695 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and 696 do not invalidate cache */ 697 #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ 698 699 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 700 #define CPUID_XSAVE_XSAVEC (1U << 1) 701 #define CPUID_XSAVE_XGETBV1 (1U << 2) 702 #define CPUID_XSAVE_XSAVES (1U << 3) 703 704 #define CPUID_6_EAX_ARAT (1U << 2) 705 706 /* CPUID[0x80000007].EDX flags: */ 707 #define CPUID_APM_INVTSC (1U << 8) 708 709 #define CPUID_VENDOR_SZ 12 710 711 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 712 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 713 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 714 #define CPUID_VENDOR_INTEL "GenuineIntel" 715 716 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 717 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 718 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 719 #define CPUID_VENDOR_AMD "AuthenticAMD" 720 721 #define CPUID_VENDOR_VIA "CentaurHauls" 722 723 #define CPUID_VENDOR_HYGON "HygonGenuine" 724 725 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 726 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 727 728 /* CPUID[0xB].ECX level types */ 729 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 730 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 731 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 732 733 /* MSR Feature Bits */ 734 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 735 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 736 #define MSR_ARCH_CAP_RSBA (1U << 2) 737 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 738 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 739 740 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 741 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 742 #endif 743 744 #define EXCP00_DIVZ 0 745 #define EXCP01_DB 1 746 #define EXCP02_NMI 2 747 #define EXCP03_INT3 3 748 #define EXCP04_INTO 4 749 #define EXCP05_BOUND 5 750 #define EXCP06_ILLOP 6 751 #define EXCP07_PREX 7 752 #define EXCP08_DBLE 8 753 #define EXCP09_XERR 9 754 #define EXCP0A_TSS 10 755 #define EXCP0B_NOSEG 11 756 #define EXCP0C_STACK 12 757 #define EXCP0D_GPF 13 758 #define EXCP0E_PAGE 14 759 #define EXCP10_COPR 16 760 #define EXCP11_ALGN 17 761 #define EXCP12_MCHK 18 762 763 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 764 for syscall instruction */ 765 #define EXCP_VMEXIT 0x100 766 767 /* i386-specific interrupt pending bits. */ 768 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 769 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 770 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 771 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 772 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 773 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 774 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 775 776 /* Use a clearer name for this. */ 777 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 778 779 /* Instead of computing the condition codes after each x86 instruction, 780 * QEMU just stores one operand (called CC_SRC), the result 781 * (called CC_DST) and the type of operation (called CC_OP). When the 782 * condition codes are needed, the condition codes can be calculated 783 * using this information. Condition codes are not generated if they 784 * are only needed for conditional branches. 785 */ 786 typedef enum { 787 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 788 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 789 790 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 791 CC_OP_MULW, 792 CC_OP_MULL, 793 CC_OP_MULQ, 794 795 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 796 CC_OP_ADDW, 797 CC_OP_ADDL, 798 CC_OP_ADDQ, 799 800 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 801 CC_OP_ADCW, 802 CC_OP_ADCL, 803 CC_OP_ADCQ, 804 805 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 806 CC_OP_SUBW, 807 CC_OP_SUBL, 808 CC_OP_SUBQ, 809 810 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 811 CC_OP_SBBW, 812 CC_OP_SBBL, 813 CC_OP_SBBQ, 814 815 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 816 CC_OP_LOGICW, 817 CC_OP_LOGICL, 818 CC_OP_LOGICQ, 819 820 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 821 CC_OP_INCW, 822 CC_OP_INCL, 823 CC_OP_INCQ, 824 825 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 826 CC_OP_DECW, 827 CC_OP_DECL, 828 CC_OP_DECQ, 829 830 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 831 CC_OP_SHLW, 832 CC_OP_SHLL, 833 CC_OP_SHLQ, 834 835 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 836 CC_OP_SARW, 837 CC_OP_SARL, 838 CC_OP_SARQ, 839 840 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 841 CC_OP_BMILGW, 842 CC_OP_BMILGL, 843 CC_OP_BMILGQ, 844 845 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 846 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 847 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 848 849 CC_OP_CLR, /* Z set, all other flags clear. */ 850 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 851 852 CC_OP_NB, 853 } CCOp; 854 855 typedef struct SegmentCache { 856 uint32_t selector; 857 target_ulong base; 858 uint32_t limit; 859 uint32_t flags; 860 } SegmentCache; 861 862 #define MMREG_UNION(n, bits) \ 863 union n { \ 864 uint8_t _b_##n[(bits)/8]; \ 865 uint16_t _w_##n[(bits)/16]; \ 866 uint32_t _l_##n[(bits)/32]; \ 867 uint64_t _q_##n[(bits)/64]; \ 868 float32 _s_##n[(bits)/32]; \ 869 float64 _d_##n[(bits)/64]; \ 870 } 871 872 typedef union { 873 uint8_t _b[16]; 874 uint16_t _w[8]; 875 uint32_t _l[4]; 876 uint64_t _q[2]; 877 } XMMReg; 878 879 typedef union { 880 uint8_t _b[32]; 881 uint16_t _w[16]; 882 uint32_t _l[8]; 883 uint64_t _q[4]; 884 } YMMReg; 885 886 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 887 typedef MMREG_UNION(MMXReg, 64) MMXReg; 888 889 typedef struct BNDReg { 890 uint64_t lb; 891 uint64_t ub; 892 } BNDReg; 893 894 typedef struct BNDCSReg { 895 uint64_t cfgu; 896 uint64_t sts; 897 } BNDCSReg; 898 899 #define BNDCFG_ENABLE 1ULL 900 #define BNDCFG_BNDPRESERVE 2ULL 901 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 902 903 #ifdef HOST_WORDS_BIGENDIAN 904 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 905 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 906 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 907 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 908 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 909 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 910 911 #define MMX_B(n) _b_MMXReg[7 - (n)] 912 #define MMX_W(n) _w_MMXReg[3 - (n)] 913 #define MMX_L(n) _l_MMXReg[1 - (n)] 914 #define MMX_S(n) _s_MMXReg[1 - (n)] 915 #else 916 #define ZMM_B(n) _b_ZMMReg[n] 917 #define ZMM_W(n) _w_ZMMReg[n] 918 #define ZMM_L(n) _l_ZMMReg[n] 919 #define ZMM_S(n) _s_ZMMReg[n] 920 #define ZMM_Q(n) _q_ZMMReg[n] 921 #define ZMM_D(n) _d_ZMMReg[n] 922 923 #define MMX_B(n) _b_MMXReg[n] 924 #define MMX_W(n) _w_MMXReg[n] 925 #define MMX_L(n) _l_MMXReg[n] 926 #define MMX_S(n) _s_MMXReg[n] 927 #endif 928 #define MMX_Q(n) _q_MMXReg[n] 929 930 typedef union { 931 floatx80 d __attribute__((aligned(16))); 932 MMXReg mmx; 933 } FPReg; 934 935 typedef struct { 936 uint64_t base; 937 uint64_t mask; 938 } MTRRVar; 939 940 #define CPU_NB_REGS64 16 941 #define CPU_NB_REGS32 8 942 943 #ifdef TARGET_X86_64 944 #define CPU_NB_REGS CPU_NB_REGS64 945 #else 946 #define CPU_NB_REGS CPU_NB_REGS32 947 #endif 948 949 #define MAX_FIXED_COUNTERS 3 950 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 951 952 #define TARGET_INSN_START_EXTRA_WORDS 1 953 954 #define NB_OPMASK_REGS 8 955 956 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 957 * that APIC ID hasn't been set yet 958 */ 959 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 960 961 typedef union X86LegacyXSaveArea { 962 struct { 963 uint16_t fcw; 964 uint16_t fsw; 965 uint8_t ftw; 966 uint8_t reserved; 967 uint16_t fpop; 968 uint64_t fpip; 969 uint64_t fpdp; 970 uint32_t mxcsr; 971 uint32_t mxcsr_mask; 972 FPReg fpregs[8]; 973 uint8_t xmm_regs[16][16]; 974 }; 975 uint8_t data[512]; 976 } X86LegacyXSaveArea; 977 978 typedef struct X86XSaveHeader { 979 uint64_t xstate_bv; 980 uint64_t xcomp_bv; 981 uint64_t reserve0; 982 uint8_t reserved[40]; 983 } X86XSaveHeader; 984 985 /* Ext. save area 2: AVX State */ 986 typedef struct XSaveAVX { 987 uint8_t ymmh[16][16]; 988 } XSaveAVX; 989 990 /* Ext. save area 3: BNDREG */ 991 typedef struct XSaveBNDREG { 992 BNDReg bnd_regs[4]; 993 } XSaveBNDREG; 994 995 /* Ext. save area 4: BNDCSR */ 996 typedef union XSaveBNDCSR { 997 BNDCSReg bndcsr; 998 uint8_t data[64]; 999 } XSaveBNDCSR; 1000 1001 /* Ext. save area 5: Opmask */ 1002 typedef struct XSaveOpmask { 1003 uint64_t opmask_regs[NB_OPMASK_REGS]; 1004 } XSaveOpmask; 1005 1006 /* Ext. save area 6: ZMM_Hi256 */ 1007 typedef struct XSaveZMM_Hi256 { 1008 uint8_t zmm_hi256[16][32]; 1009 } XSaveZMM_Hi256; 1010 1011 /* Ext. save area 7: Hi16_ZMM */ 1012 typedef struct XSaveHi16_ZMM { 1013 uint8_t hi16_zmm[16][64]; 1014 } XSaveHi16_ZMM; 1015 1016 /* Ext. save area 9: PKRU state */ 1017 typedef struct XSavePKRU { 1018 uint32_t pkru; 1019 uint32_t padding; 1020 } XSavePKRU; 1021 1022 typedef struct X86XSaveArea { 1023 X86LegacyXSaveArea legacy; 1024 X86XSaveHeader header; 1025 1026 /* Extended save areas: */ 1027 1028 /* AVX State: */ 1029 XSaveAVX avx_state; 1030 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1031 /* MPX State: */ 1032 XSaveBNDREG bndreg_state; 1033 XSaveBNDCSR bndcsr_state; 1034 /* AVX-512 State: */ 1035 XSaveOpmask opmask_state; 1036 XSaveZMM_Hi256 zmm_hi256_state; 1037 XSaveHi16_ZMM hi16_zmm_state; 1038 /* PKRU State: */ 1039 XSavePKRU pkru_state; 1040 } X86XSaveArea; 1041 1042 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1043 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1044 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1045 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1046 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1047 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1048 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1049 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1050 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1051 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1052 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1053 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1054 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1055 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1056 1057 typedef enum TPRAccess { 1058 TPR_ACCESS_READ, 1059 TPR_ACCESS_WRITE, 1060 } TPRAccess; 1061 1062 /* Cache information data structures: */ 1063 1064 enum CacheType { 1065 DATA_CACHE, 1066 INSTRUCTION_CACHE, 1067 UNIFIED_CACHE 1068 }; 1069 1070 typedef struct CPUCacheInfo { 1071 enum CacheType type; 1072 uint8_t level; 1073 /* Size in bytes */ 1074 uint32_t size; 1075 /* Line size, in bytes */ 1076 uint16_t line_size; 1077 /* 1078 * Associativity. 1079 * Note: representation of fully-associative caches is not implemented 1080 */ 1081 uint8_t associativity; 1082 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1083 uint8_t partitions; 1084 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1085 uint32_t sets; 1086 /* 1087 * Lines per tag. 1088 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1089 * (Is this synonym to @partitions?) 1090 */ 1091 uint8_t lines_per_tag; 1092 1093 /* Self-initializing cache */ 1094 bool self_init; 1095 /* 1096 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1097 * non-originating threads sharing this cache. 1098 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1099 */ 1100 bool no_invd_sharing; 1101 /* 1102 * Cache is inclusive of lower cache levels. 1103 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1104 */ 1105 bool inclusive; 1106 /* 1107 * A complex function is used to index the cache, potentially using all 1108 * address bits. CPUID[4].EDX[bit 2]. 1109 */ 1110 bool complex_indexing; 1111 } CPUCacheInfo; 1112 1113 1114 typedef struct CPUCaches { 1115 CPUCacheInfo *l1d_cache; 1116 CPUCacheInfo *l1i_cache; 1117 CPUCacheInfo *l2_cache; 1118 CPUCacheInfo *l3_cache; 1119 } CPUCaches; 1120 1121 typedef struct CPUX86State { 1122 /* standard registers */ 1123 target_ulong regs[CPU_NB_REGS]; 1124 target_ulong eip; 1125 target_ulong eflags; /* eflags register. During CPU emulation, CC 1126 flags and DF are set to zero because they are 1127 stored elsewhere */ 1128 1129 /* emulator internal eflags handling */ 1130 target_ulong cc_dst; 1131 target_ulong cc_src; 1132 target_ulong cc_src2; 1133 uint32_t cc_op; 1134 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1135 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1136 are known at translation time. */ 1137 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1138 1139 /* segments */ 1140 SegmentCache segs[6]; /* selector values */ 1141 SegmentCache ldt; 1142 SegmentCache tr; 1143 SegmentCache gdt; /* only base and limit are used */ 1144 SegmentCache idt; /* only base and limit are used */ 1145 1146 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1147 int32_t a20_mask; 1148 1149 BNDReg bnd_regs[4]; 1150 BNDCSReg bndcs_regs; 1151 uint64_t msr_bndcfgs; 1152 uint64_t efer; 1153 1154 /* Beginning of state preserved by INIT (dummy marker). */ 1155 struct {} start_init_save; 1156 1157 /* FPU state */ 1158 unsigned int fpstt; /* top of stack index */ 1159 uint16_t fpus; 1160 uint16_t fpuc; 1161 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1162 FPReg fpregs[8]; 1163 /* KVM-only so far */ 1164 uint16_t fpop; 1165 uint64_t fpip; 1166 uint64_t fpdp; 1167 1168 /* emulator internal variables */ 1169 float_status fp_status; 1170 floatx80 ft0; 1171 1172 float_status mmx_status; /* for 3DNow! float ops */ 1173 float_status sse_status; 1174 uint32_t mxcsr; 1175 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1176 ZMMReg xmm_t0; 1177 MMXReg mmx_t0; 1178 1179 XMMReg ymmh_regs[CPU_NB_REGS]; 1180 1181 uint64_t opmask_regs[NB_OPMASK_REGS]; 1182 YMMReg zmmh_regs[CPU_NB_REGS]; 1183 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1184 1185 /* sysenter registers */ 1186 uint32_t sysenter_cs; 1187 target_ulong sysenter_esp; 1188 target_ulong sysenter_eip; 1189 uint64_t star; 1190 1191 uint64_t vm_hsave; 1192 1193 #ifdef TARGET_X86_64 1194 target_ulong lstar; 1195 target_ulong cstar; 1196 target_ulong fmask; 1197 target_ulong kernelgsbase; 1198 #endif 1199 1200 uint64_t tsc; 1201 uint64_t tsc_adjust; 1202 uint64_t tsc_deadline; 1203 uint64_t tsc_aux; 1204 1205 uint64_t xcr0; 1206 1207 uint64_t mcg_status; 1208 uint64_t msr_ia32_misc_enable; 1209 uint64_t msr_ia32_feature_control; 1210 1211 uint64_t msr_fixed_ctr_ctrl; 1212 uint64_t msr_global_ctrl; 1213 uint64_t msr_global_status; 1214 uint64_t msr_global_ovf_ctrl; 1215 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1216 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1217 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1218 1219 uint64_t pat; 1220 uint32_t smbase; 1221 uint64_t msr_smi_count; 1222 1223 uint32_t pkru; 1224 1225 uint64_t spec_ctrl; 1226 uint64_t virt_ssbd; 1227 1228 /* End of state preserved by INIT (dummy marker). */ 1229 struct {} end_init_save; 1230 1231 uint64_t system_time_msr; 1232 uint64_t wall_clock_msr; 1233 uint64_t steal_time_msr; 1234 uint64_t async_pf_en_msr; 1235 uint64_t pv_eoi_en_msr; 1236 1237 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1238 uint64_t msr_hv_hypercall; 1239 uint64_t msr_hv_guest_os_id; 1240 uint64_t msr_hv_tsc; 1241 1242 /* Per-VCPU HV MSRs */ 1243 uint64_t msr_hv_vapic; 1244 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1245 uint64_t msr_hv_runtime; 1246 uint64_t msr_hv_synic_control; 1247 uint64_t msr_hv_synic_evt_page; 1248 uint64_t msr_hv_synic_msg_page; 1249 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1250 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1251 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1252 uint64_t msr_hv_reenlightenment_control; 1253 uint64_t msr_hv_tsc_emulation_control; 1254 uint64_t msr_hv_tsc_emulation_status; 1255 1256 uint64_t msr_rtit_ctrl; 1257 uint64_t msr_rtit_status; 1258 uint64_t msr_rtit_output_base; 1259 uint64_t msr_rtit_output_mask; 1260 uint64_t msr_rtit_cr3_match; 1261 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1262 1263 /* exception/interrupt handling */ 1264 int error_code; 1265 int exception_is_int; 1266 target_ulong exception_next_eip; 1267 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1268 union { 1269 struct CPUBreakpoint *cpu_breakpoint[4]; 1270 struct CPUWatchpoint *cpu_watchpoint[4]; 1271 }; /* break/watchpoints for dr[0..3] */ 1272 int old_exception; /* exception in flight */ 1273 1274 uint64_t vm_vmcb; 1275 uint64_t tsc_offset; 1276 uint64_t intercept; 1277 uint16_t intercept_cr_read; 1278 uint16_t intercept_cr_write; 1279 uint16_t intercept_dr_read; 1280 uint16_t intercept_dr_write; 1281 uint32_t intercept_exceptions; 1282 uint64_t nested_cr3; 1283 uint32_t nested_pg_mode; 1284 uint8_t v_tpr; 1285 1286 /* KVM states, automatically cleared on reset */ 1287 uint8_t nmi_injected; 1288 uint8_t nmi_pending; 1289 1290 uintptr_t retaddr; 1291 1292 /* Fields up to this point are cleared by a CPU reset */ 1293 struct {} end_reset_fields; 1294 1295 CPU_COMMON 1296 1297 /* Fields after CPU_COMMON are preserved across CPU reset. */ 1298 1299 /* processor features (e.g. for CPUID insn) */ 1300 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1301 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1302 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1303 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1304 /* Actual level/xlevel/xlevel2 value: */ 1305 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1306 uint32_t cpuid_vendor1; 1307 uint32_t cpuid_vendor2; 1308 uint32_t cpuid_vendor3; 1309 uint32_t cpuid_version; 1310 FeatureWordArray features; 1311 /* Features that were explicitly enabled/disabled */ 1312 FeatureWordArray user_features; 1313 uint32_t cpuid_model[12]; 1314 /* Cache information for CPUID. When legacy-cache=on, the cache data 1315 * on each CPUID leaf will be different, because we keep compatibility 1316 * with old QEMU versions. 1317 */ 1318 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1319 1320 /* MTRRs */ 1321 uint64_t mtrr_fixed[11]; 1322 uint64_t mtrr_deftype; 1323 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1324 1325 /* For KVM */ 1326 uint32_t mp_state; 1327 int32_t exception_injected; 1328 int32_t interrupt_injected; 1329 uint8_t soft_interrupt; 1330 uint8_t has_error_code; 1331 uint32_t ins_len; 1332 uint32_t sipi_vector; 1333 bool tsc_valid; 1334 int64_t tsc_khz; 1335 int64_t user_tsc_khz; /* for sanity check only */ 1336 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1337 void *xsave_buf; 1338 #endif 1339 #if defined(CONFIG_HVF) 1340 HVFX86EmulatorState *hvf_emul; 1341 #endif 1342 1343 uint64_t mcg_cap; 1344 uint64_t mcg_ctl; 1345 uint64_t mcg_ext_ctl; 1346 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1347 uint64_t xstate_bv; 1348 1349 /* vmstate */ 1350 uint16_t fpus_vmstate; 1351 uint16_t fptag_vmstate; 1352 uint16_t fpregs_format_vmstate; 1353 1354 uint64_t xss; 1355 1356 TPRAccess tpr_access_type; 1357 } CPUX86State; 1358 1359 struct kvm_msrs; 1360 1361 /** 1362 * X86CPU: 1363 * @env: #CPUX86State 1364 * @migratable: If set, only migratable flags will be accepted when "enforce" 1365 * mode is used, and only migratable flags will be included in the "host" 1366 * CPU model. 1367 * 1368 * An x86 CPU. 1369 */ 1370 struct X86CPU { 1371 /*< private >*/ 1372 CPUState parent_obj; 1373 /*< public >*/ 1374 1375 CPUX86State env; 1376 1377 bool hyperv_vapic; 1378 bool hyperv_relaxed_timing; 1379 int hyperv_spinlock_attempts; 1380 char *hyperv_vendor_id; 1381 bool hyperv_time; 1382 bool hyperv_crash; 1383 bool hyperv_reset; 1384 bool hyperv_vpindex; 1385 bool hyperv_runtime; 1386 bool hyperv_synic; 1387 bool hyperv_synic_kvm_only; 1388 bool hyperv_stimer; 1389 bool hyperv_frequencies; 1390 bool hyperv_reenlightenment; 1391 bool hyperv_tlbflush; 1392 bool hyperv_evmcs; 1393 bool hyperv_ipi; 1394 bool check_cpuid; 1395 bool enforce_cpuid; 1396 bool expose_kvm; 1397 bool expose_tcg; 1398 bool migratable; 1399 bool migrate_smi_count; 1400 bool max_features; /* Enable all supported features automatically */ 1401 uint32_t apic_id; 1402 1403 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1404 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1405 bool vmware_cpuid_freq; 1406 1407 /* if true the CPUID code directly forward host cache leaves to the guest */ 1408 bool cache_info_passthrough; 1409 1410 /* if true the CPUID code directly forwards 1411 * host monitor/mwait leaves to the guest */ 1412 struct { 1413 uint32_t eax; 1414 uint32_t ebx; 1415 uint32_t ecx; 1416 uint32_t edx; 1417 } mwait; 1418 1419 /* Features that were filtered out because of missing host capabilities */ 1420 uint32_t filtered_features[FEATURE_WORDS]; 1421 1422 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1423 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1424 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1425 * capabilities) directly to the guest. 1426 */ 1427 bool enable_pmu; 1428 1429 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1430 * disabled by default to avoid breaking migration between QEMU with 1431 * different LMCE configurations. 1432 */ 1433 bool enable_lmce; 1434 1435 /* Compatibility bits for old machine types. 1436 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1437 * socket share an virtual l3 cache. 1438 */ 1439 bool enable_l3_cache; 1440 1441 /* Compatibility bits for old machine types. 1442 * If true present the old cache topology information 1443 */ 1444 bool legacy_cache; 1445 1446 /* Compatibility bits for old machine types: */ 1447 bool enable_cpuid_0xb; 1448 1449 /* Enable auto level-increase for all CPUID leaves */ 1450 bool full_cpuid_auto_level; 1451 1452 /* Enable auto level-increase for Intel Processor Trace leave */ 1453 bool intel_pt_auto_level; 1454 1455 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1456 bool fill_mtrr_mask; 1457 1458 /* if true override the phys_bits value with a value read from the host */ 1459 bool host_phys_bits; 1460 1461 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1462 uint8_t host_phys_bits_limit; 1463 1464 /* Stop SMI delivery for migration compatibility with old machines */ 1465 bool kvm_no_smi_migration; 1466 1467 /* Number of physical address bits supported */ 1468 uint32_t phys_bits; 1469 1470 /* in order to simplify APIC support, we leave this pointer to the 1471 user */ 1472 struct DeviceState *apic_state; 1473 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1474 Notifier machine_done; 1475 1476 struct kvm_msrs *kvm_msr_buf; 1477 1478 int32_t node_id; /* NUMA node this CPU belongs to */ 1479 int32_t socket_id; 1480 int32_t core_id; 1481 int32_t thread_id; 1482 1483 int32_t hv_max_vps; 1484 }; 1485 1486 static inline X86CPU *x86_env_get_cpu(CPUX86State *env) 1487 { 1488 return container_of(env, X86CPU, env); 1489 } 1490 1491 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) 1492 1493 #define ENV_OFFSET offsetof(X86CPU, env) 1494 1495 #ifndef CONFIG_USER_ONLY 1496 extern struct VMStateDescription vmstate_x86_cpu; 1497 #endif 1498 1499 /** 1500 * x86_cpu_do_interrupt: 1501 * @cpu: vCPU the interrupt is to be handled by. 1502 */ 1503 void x86_cpu_do_interrupt(CPUState *cpu); 1504 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1505 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1506 1507 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1508 int cpuid, void *opaque); 1509 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1510 int cpuid, void *opaque); 1511 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1512 void *opaque); 1513 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1514 void *opaque); 1515 1516 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1517 Error **errp); 1518 1519 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1520 1521 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1522 1523 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1524 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1525 1526 void x86_cpu_exec_enter(CPUState *cpu); 1527 void x86_cpu_exec_exit(CPUState *cpu); 1528 1529 void x86_cpu_list(void); 1530 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1531 1532 int cpu_get_pic_interrupt(CPUX86State *s); 1533 /* MSDOS compatibility mode FPU exception support */ 1534 void cpu_set_ferr(CPUX86State *s); 1535 /* mpx_helper.c */ 1536 void cpu_sync_bndcs_hflags(CPUX86State *env); 1537 1538 /* this function must always be used to load data in the segment 1539 cache: it synchronizes the hflags with the segment cache values */ 1540 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1541 int seg_reg, unsigned int selector, 1542 target_ulong base, 1543 unsigned int limit, 1544 unsigned int flags) 1545 { 1546 SegmentCache *sc; 1547 unsigned int new_hflags; 1548 1549 sc = &env->segs[seg_reg]; 1550 sc->selector = selector; 1551 sc->base = base; 1552 sc->limit = limit; 1553 sc->flags = flags; 1554 1555 /* update the hidden flags */ 1556 { 1557 if (seg_reg == R_CS) { 1558 #ifdef TARGET_X86_64 1559 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1560 /* long mode */ 1561 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1562 env->hflags &= ~(HF_ADDSEG_MASK); 1563 } else 1564 #endif 1565 { 1566 /* legacy / compatibility case */ 1567 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1568 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1569 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1570 new_hflags; 1571 } 1572 } 1573 if (seg_reg == R_SS) { 1574 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1575 #if HF_CPL_MASK != 3 1576 #error HF_CPL_MASK is hardcoded 1577 #endif 1578 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1579 /* Possibly switch between BNDCFGS and BNDCFGU */ 1580 cpu_sync_bndcs_hflags(env); 1581 } 1582 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1583 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1584 if (env->hflags & HF_CS64_MASK) { 1585 /* zero base assumed for DS, ES and SS in long mode */ 1586 } else if (!(env->cr[0] & CR0_PE_MASK) || 1587 (env->eflags & VM_MASK) || 1588 !(env->hflags & HF_CS32_MASK)) { 1589 /* XXX: try to avoid this test. The problem comes from the 1590 fact that is real mode or vm86 mode we only modify the 1591 'base' and 'selector' fields of the segment cache to go 1592 faster. A solution may be to force addseg to one in 1593 translate-i386.c. */ 1594 new_hflags |= HF_ADDSEG_MASK; 1595 } else { 1596 new_hflags |= ((env->segs[R_DS].base | 1597 env->segs[R_ES].base | 1598 env->segs[R_SS].base) != 0) << 1599 HF_ADDSEG_SHIFT; 1600 } 1601 env->hflags = (env->hflags & 1602 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1603 } 1604 } 1605 1606 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1607 uint8_t sipi_vector) 1608 { 1609 CPUState *cs = CPU(cpu); 1610 CPUX86State *env = &cpu->env; 1611 1612 env->eip = 0; 1613 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1614 sipi_vector << 12, 1615 env->segs[R_CS].limit, 1616 env->segs[R_CS].flags); 1617 cs->halted = 0; 1618 } 1619 1620 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1621 target_ulong *base, unsigned int *limit, 1622 unsigned int *flags); 1623 1624 /* op_helper.c */ 1625 /* used for debug or cpu save/restore */ 1626 1627 /* cpu-exec.c */ 1628 /* the following helpers are only usable in user mode simulation as 1629 they can trigger unexpected exceptions */ 1630 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1631 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1632 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1633 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1634 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1635 1636 /* you can call this signal handler from your SIGBUS and SIGSEGV 1637 signal handlers to inform the virtual CPU of exceptions. non zero 1638 is returned if the signal was handled by the virtual CPU. */ 1639 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1640 void *puc); 1641 1642 /* cpu.c */ 1643 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1644 uint32_t *eax, uint32_t *ebx, 1645 uint32_t *ecx, uint32_t *edx); 1646 void cpu_clear_apic_feature(CPUX86State *env); 1647 void host_cpuid(uint32_t function, uint32_t count, 1648 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1649 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1650 1651 /* helper.c */ 1652 bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1653 MMUAccessType access_type, int mmu_idx, 1654 bool probe, uintptr_t retaddr); 1655 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1656 1657 #ifndef CONFIG_USER_ONLY 1658 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1659 { 1660 return !!attrs.secure; 1661 } 1662 1663 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1664 { 1665 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1666 } 1667 1668 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1669 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1670 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1671 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1672 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1673 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1674 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1675 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1676 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1677 #endif 1678 1679 void breakpoint_handler(CPUState *cs); 1680 1681 /* will be suppressed */ 1682 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1683 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1684 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1685 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1686 1687 /* hw/pc.c */ 1688 uint64_t cpu_get_tsc(CPUX86State *env); 1689 1690 /* XXX: This value should match the one returned by CPUID 1691 * and in exec.c */ 1692 # if defined(TARGET_X86_64) 1693 # define TCG_PHYS_ADDR_BITS 40 1694 # else 1695 # define TCG_PHYS_ADDR_BITS 36 1696 # endif 1697 1698 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1699 1700 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1701 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1702 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1703 1704 #ifdef TARGET_X86_64 1705 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1706 #else 1707 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1708 #endif 1709 1710 #define cpu_signal_handler cpu_x86_signal_handler 1711 #define cpu_list x86_cpu_list 1712 1713 /* MMU modes definitions */ 1714 #define MMU_MODE0_SUFFIX _ksmap 1715 #define MMU_MODE1_SUFFIX _user 1716 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1717 #define MMU_KSMAP_IDX 0 1718 #define MMU_USER_IDX 1 1719 #define MMU_KNOSMAP_IDX 2 1720 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1721 { 1722 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1723 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1724 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1725 } 1726 1727 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1728 { 1729 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1730 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1731 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1732 } 1733 1734 #define CC_DST (env->cc_dst) 1735 #define CC_SRC (env->cc_src) 1736 #define CC_SRC2 (env->cc_src2) 1737 #define CC_OP (env->cc_op) 1738 1739 /* n must be a constant to be efficient */ 1740 static inline target_long lshift(target_long x, int n) 1741 { 1742 if (n >= 0) { 1743 return x << n; 1744 } else { 1745 return x >> (-n); 1746 } 1747 } 1748 1749 /* float macros */ 1750 #define FT0 (env->ft0) 1751 #define ST0 (env->fpregs[env->fpstt].d) 1752 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1753 #define ST1 ST(1) 1754 1755 /* translate.c */ 1756 void tcg_x86_init(void); 1757 1758 #include "exec/cpu-all.h" 1759 #include "svm.h" 1760 1761 #if !defined(CONFIG_USER_ONLY) 1762 #include "hw/i386/apic.h" 1763 #endif 1764 1765 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1766 target_ulong *cs_base, uint32_t *flags) 1767 { 1768 *cs_base = env->segs[R_CS].base; 1769 *pc = *cs_base + env->eip; 1770 *flags = env->hflags | 1771 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1772 } 1773 1774 void do_cpu_init(X86CPU *cpu); 1775 void do_cpu_sipi(X86CPU *cpu); 1776 1777 #define MCE_INJECT_BROADCAST 1 1778 #define MCE_INJECT_UNCOND_AO 2 1779 1780 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1781 uint64_t status, uint64_t mcg_status, uint64_t addr, 1782 uint64_t misc, int flags); 1783 1784 /* excp_helper.c */ 1785 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1786 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1787 uintptr_t retaddr); 1788 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1789 int error_code); 1790 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1791 int error_code, uintptr_t retaddr); 1792 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1793 int error_code, int next_eip_addend); 1794 1795 /* cc_helper.c */ 1796 extern const uint8_t parity_table[256]; 1797 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1798 1799 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1800 { 1801 uint32_t eflags = env->eflags; 1802 if (tcg_enabled()) { 1803 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 1804 } 1805 return eflags; 1806 } 1807 1808 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1809 * after generating a call to a helper that uses this. 1810 */ 1811 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1812 int update_mask) 1813 { 1814 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1815 CC_OP = CC_OP_EFLAGS; 1816 env->df = 1 - (2 * ((eflags >> 10) & 1)); 1817 env->eflags = (env->eflags & ~update_mask) | 1818 (eflags & update_mask) | 0x2; 1819 } 1820 1821 /* load efer and update the corresponding hflags. XXX: do consistency 1822 checks with cpuid bits? */ 1823 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1824 { 1825 env->efer = val; 1826 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1827 if (env->efer & MSR_EFER_LMA) { 1828 env->hflags |= HF_LMA_MASK; 1829 } 1830 if (env->efer & MSR_EFER_SVME) { 1831 env->hflags |= HF_SVME_MASK; 1832 } 1833 } 1834 1835 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 1836 { 1837 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 1838 } 1839 1840 static inline int32_t x86_get_a20_mask(CPUX86State *env) 1841 { 1842 if (env->hflags & HF_SMM_MASK) { 1843 return -1; 1844 } else { 1845 return env->a20_mask; 1846 } 1847 } 1848 1849 /* fpu_helper.c */ 1850 void update_fp_status(CPUX86State *env); 1851 void update_mxcsr_status(CPUX86State *env); 1852 1853 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 1854 { 1855 env->mxcsr = mxcsr; 1856 if (tcg_enabled()) { 1857 update_mxcsr_status(env); 1858 } 1859 } 1860 1861 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 1862 { 1863 env->fpuc = fpuc; 1864 if (tcg_enabled()) { 1865 update_fp_status(env); 1866 } 1867 } 1868 1869 /* mem_helper.c */ 1870 void helper_lock_init(void); 1871 1872 /* svm_helper.c */ 1873 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 1874 uint64_t param, uintptr_t retaddr); 1875 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, 1876 uint64_t exit_info_1, uintptr_t retaddr); 1877 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 1878 1879 /* seg_helper.c */ 1880 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 1881 1882 /* smm_helper.c */ 1883 void do_smm_enter(X86CPU *cpu); 1884 1885 /* apic.c */ 1886 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 1887 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 1888 TPRAccess access); 1889 1890 1891 /* Change the value of a KVM-specific default 1892 * 1893 * If value is NULL, no default will be set and the original 1894 * value from the CPU model table will be kept. 1895 * 1896 * It is valid to call this function only for properties that 1897 * are already present in the kvm_default_props table. 1898 */ 1899 void x86_cpu_change_kvm_default(const char *prop, const char *value); 1900 1901 /* Return name of 32-bit register, from a R_* constant */ 1902 const char *get_register_name_32(unsigned int reg); 1903 1904 void enable_compat_apic_id_mode(void); 1905 1906 #define APIC_DEFAULT_ADDRESS 0xfee00000 1907 #define APIC_SPACE_SIZE 0x100000 1908 1909 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 1910 1911 /* cpu.c */ 1912 bool cpu_is_bsp(X86CPU *cpu); 1913 1914 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 1915 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 1916 void x86_update_hflags(CPUX86State* env); 1917 1918 #endif /* I386_CPU_H */ 1919