1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "kvm/hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 #define KVM_HAVE_MCE_INJECTION 1 33 34 /* support for self modifying code even if the modified instruction is 35 close to the modifying instruction */ 36 #define TARGET_HAS_PRECISE_SMC 37 38 #ifdef TARGET_X86_64 39 #define I386_ELF_MACHINE EM_X86_64 40 #define ELF_MACHINE_UNAME "x86_64" 41 #else 42 #define I386_ELF_MACHINE EM_386 43 #define ELF_MACHINE_UNAME "i686" 44 #endif 45 46 enum { 47 R_EAX = 0, 48 R_ECX = 1, 49 R_EDX = 2, 50 R_EBX = 3, 51 R_ESP = 4, 52 R_EBP = 5, 53 R_ESI = 6, 54 R_EDI = 7, 55 R_R8 = 8, 56 R_R9 = 9, 57 R_R10 = 10, 58 R_R11 = 11, 59 R_R12 = 12, 60 R_R13 = 13, 61 R_R14 = 14, 62 R_R15 = 15, 63 64 R_AL = 0, 65 R_CL = 1, 66 R_DL = 2, 67 R_BL = 3, 68 R_AH = 4, 69 R_CH = 5, 70 R_DH = 6, 71 R_BH = 7, 72 }; 73 74 typedef enum X86Seg { 75 R_ES = 0, 76 R_CS = 1, 77 R_SS = 2, 78 R_DS = 3, 79 R_FS = 4, 80 R_GS = 5, 81 R_LDTR = 6, 82 R_TR = 7, 83 } X86Seg; 84 85 /* segment descriptor fields */ 86 #define DESC_G_SHIFT 23 87 #define DESC_G_MASK (1 << DESC_G_SHIFT) 88 #define DESC_B_SHIFT 22 89 #define DESC_B_MASK (1 << DESC_B_SHIFT) 90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91 #define DESC_L_MASK (1 << DESC_L_SHIFT) 92 #define DESC_AVL_SHIFT 20 93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94 #define DESC_P_SHIFT 15 95 #define DESC_P_MASK (1 << DESC_P_SHIFT) 96 #define DESC_DPL_SHIFT 13 97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98 #define DESC_S_SHIFT 12 99 #define DESC_S_MASK (1 << DESC_S_SHIFT) 100 #define DESC_TYPE_SHIFT 8 101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102 #define DESC_A_MASK (1 << 8) 103 104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105 #define DESC_C_MASK (1 << 10) /* code: conforming */ 106 #define DESC_R_MASK (1 << 9) /* code: readable */ 107 108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109 #define DESC_W_MASK (1 << 9) /* data: writable */ 110 111 #define DESC_TSS_BUSY_MASK (1 << 9) 112 113 /* eflags masks */ 114 #define CC_C 0x0001 115 #define CC_P 0x0004 116 #define CC_A 0x0010 117 #define CC_Z 0x0040 118 #define CC_S 0x0080 119 #define CC_O 0x0800 120 121 #define TF_SHIFT 8 122 #define IOPL_SHIFT 12 123 #define VM_SHIFT 17 124 125 #define TF_MASK 0x00000100 126 #define IF_MASK 0x00000200 127 #define DF_MASK 0x00000400 128 #define IOPL_MASK 0x00003000 129 #define NT_MASK 0x00004000 130 #define RF_MASK 0x00010000 131 #define VM_MASK 0x00020000 132 #define AC_MASK 0x00040000 133 #define VIF_MASK 0x00080000 134 #define VIP_MASK 0x00100000 135 #define ID_MASK 0x00200000 136 137 /* hidden flags - used internally by qemu to represent additional cpu 138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140 positions to ease oring with eflags. */ 141 /* current cpl */ 142 #define HF_CPL_SHIFT 0 143 /* true if hardware interrupts must be disabled for next instruction */ 144 #define HF_INHIBIT_IRQ_SHIFT 3 145 /* 16 or 32 segments */ 146 #define HF_CS32_SHIFT 4 147 #define HF_SS32_SHIFT 5 148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149 #define HF_ADDSEG_SHIFT 6 150 /* copy of CR0.PE (protected mode) */ 151 #define HF_PE_SHIFT 7 152 #define HF_TF_SHIFT 8 /* must be same as eflags */ 153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154 #define HF_EM_SHIFT 10 155 #define HF_TS_SHIFT 11 156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159 #define HF_RF_SHIFT 16 /* must be same as eflags */ 160 #define HF_VM_SHIFT 17 /* must be same as eflags */ 161 #define HF_AC_SHIFT 18 /* must be same as eflags */ 162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170 171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176 #define HF_PE_MASK (1 << HF_PE_SHIFT) 177 #define HF_TF_MASK (1 << HF_TF_SHIFT) 178 #define HF_MP_MASK (1 << HF_MP_SHIFT) 179 #define HF_EM_MASK (1 << HF_EM_SHIFT) 180 #define HF_TS_MASK (1 << HF_TS_SHIFT) 181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184 #define HF_RF_MASK (1 << HF_RF_SHIFT) 185 #define HF_VM_MASK (1 << HF_VM_SHIFT) 186 #define HF_AC_MASK (1 << HF_AC_SHIFT) 187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195 196 /* hflags2 */ 197 198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 206 207 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 208 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 209 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 210 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 211 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 212 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 213 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 214 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 215 216 #define CR0_PE_SHIFT 0 217 #define CR0_MP_SHIFT 1 218 219 #define CR0_PE_MASK (1U << 0) 220 #define CR0_MP_MASK (1U << 1) 221 #define CR0_EM_MASK (1U << 2) 222 #define CR0_TS_MASK (1U << 3) 223 #define CR0_ET_MASK (1U << 4) 224 #define CR0_NE_MASK (1U << 5) 225 #define CR0_WP_MASK (1U << 16) 226 #define CR0_AM_MASK (1U << 18) 227 #define CR0_NW_MASK (1U << 29) 228 #define CR0_CD_MASK (1U << 30) 229 #define CR0_PG_MASK (1U << 31) 230 231 #define CR4_VME_MASK (1U << 0) 232 #define CR4_PVI_MASK (1U << 1) 233 #define CR4_TSD_MASK (1U << 2) 234 #define CR4_DE_MASK (1U << 3) 235 #define CR4_PSE_MASK (1U << 4) 236 #define CR4_PAE_MASK (1U << 5) 237 #define CR4_MCE_MASK (1U << 6) 238 #define CR4_PGE_MASK (1U << 7) 239 #define CR4_PCE_MASK (1U << 8) 240 #define CR4_OSFXSR_SHIFT 9 241 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 242 #define CR4_OSXMMEXCPT_MASK (1U << 10) 243 #define CR4_UMIP_MASK (1U << 11) 244 #define CR4_LA57_MASK (1U << 12) 245 #define CR4_VMXE_MASK (1U << 13) 246 #define CR4_SMXE_MASK (1U << 14) 247 #define CR4_FSGSBASE_MASK (1U << 16) 248 #define CR4_PCIDE_MASK (1U << 17) 249 #define CR4_OSXSAVE_MASK (1U << 18) 250 #define CR4_SMEP_MASK (1U << 20) 251 #define CR4_SMAP_MASK (1U << 21) 252 #define CR4_PKE_MASK (1U << 22) 253 #define CR4_PKS_MASK (1U << 24) 254 255 #define CR4_RESERVED_MASK \ 256 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ 257 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ 258 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ 259 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK |CR4_UMIP_MASK \ 260 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ 261 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) 262 263 #define DR6_BD (1 << 13) 264 #define DR6_BS (1 << 14) 265 #define DR6_BT (1 << 15) 266 #define DR6_FIXED_1 0xffff0ff0 267 268 #define DR7_GD (1 << 13) 269 #define DR7_TYPE_SHIFT 16 270 #define DR7_LEN_SHIFT 18 271 #define DR7_FIXED_1 0x00000400 272 #define DR7_GLOBAL_BP_MASK 0xaa 273 #define DR7_LOCAL_BP_MASK 0x55 274 #define DR7_MAX_BP 4 275 #define DR7_TYPE_BP_INST 0x0 276 #define DR7_TYPE_DATA_WR 0x1 277 #define DR7_TYPE_IO_RW 0x2 278 #define DR7_TYPE_DATA_RW 0x3 279 280 #define DR_RESERVED_MASK 0xffffffff00000000ULL 281 282 #define PG_PRESENT_BIT 0 283 #define PG_RW_BIT 1 284 #define PG_USER_BIT 2 285 #define PG_PWT_BIT 3 286 #define PG_PCD_BIT 4 287 #define PG_ACCESSED_BIT 5 288 #define PG_DIRTY_BIT 6 289 #define PG_PSE_BIT 7 290 #define PG_GLOBAL_BIT 8 291 #define PG_PSE_PAT_BIT 12 292 #define PG_PKRU_BIT 59 293 #define PG_NX_BIT 63 294 295 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 296 #define PG_RW_MASK (1 << PG_RW_BIT) 297 #define PG_USER_MASK (1 << PG_USER_BIT) 298 #define PG_PWT_MASK (1 << PG_PWT_BIT) 299 #define PG_PCD_MASK (1 << PG_PCD_BIT) 300 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 301 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 302 #define PG_PSE_MASK (1 << PG_PSE_BIT) 303 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 304 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 305 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 306 #define PG_HI_USER_MASK 0x7ff0000000000000LL 307 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 308 #define PG_NX_MASK (1ULL << PG_NX_BIT) 309 310 #define PG_ERROR_W_BIT 1 311 312 #define PG_ERROR_P_MASK 0x01 313 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 314 #define PG_ERROR_U_MASK 0x04 315 #define PG_ERROR_RSVD_MASK 0x08 316 #define PG_ERROR_I_D_MASK 0x10 317 #define PG_ERROR_PK_MASK 0x20 318 319 #define PG_MODE_PAE (1 << 0) 320 #define PG_MODE_LMA (1 << 1) 321 #define PG_MODE_NXE (1 << 2) 322 #define PG_MODE_PSE (1 << 3) 323 #define PG_MODE_LA57 (1 << 4) 324 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) 325 326 /* Bits of CR4 that do not affect the NPT page format. */ 327 #define PG_MODE_WP (1 << 16) 328 #define PG_MODE_PKE (1 << 17) 329 #define PG_MODE_PKS (1 << 18) 330 #define PG_MODE_SMEP (1 << 19) 331 332 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 333 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 334 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 335 336 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 337 #define MCE_BANKS_DEF 10 338 339 #define MCG_CAP_BANKS_MASK 0xff 340 341 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 342 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 343 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 344 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 345 346 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 347 348 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 349 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 350 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 351 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 352 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 353 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 354 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 355 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 356 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 357 358 /* MISC register defines */ 359 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 360 #define MCM_ADDR_LINEAR 1 /* linear address */ 361 #define MCM_ADDR_PHYS 2 /* physical address */ 362 #define MCM_ADDR_MEM 3 /* memory address */ 363 #define MCM_ADDR_GENERIC 7 /* generic */ 364 365 #define MSR_IA32_TSC 0x10 366 #define MSR_IA32_APICBASE 0x1b 367 #define MSR_IA32_APICBASE_BSP (1<<8) 368 #define MSR_IA32_APICBASE_ENABLE (1<<11) 369 #define MSR_IA32_APICBASE_EXTD (1 << 10) 370 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 371 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 372 #define MSR_TSC_ADJUST 0x0000003b 373 #define MSR_IA32_SPEC_CTRL 0x48 374 #define MSR_VIRT_SSBD 0xc001011f 375 #define MSR_IA32_PRED_CMD 0x49 376 #define MSR_IA32_UCODE_REV 0x8b 377 #define MSR_IA32_CORE_CAPABILITY 0xcf 378 379 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 380 #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 381 382 #define MSR_IA32_PERF_CAPABILITIES 0x345 383 384 #define MSR_IA32_TSX_CTRL 0x122 385 #define MSR_IA32_TSCDEADLINE 0x6e0 386 #define MSR_IA32_PKRS 0x6e1 387 388 #define FEATURE_CONTROL_LOCKED (1<<0) 389 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 390 #define FEATURE_CONTROL_LMCE (1<<20) 391 392 #define MSR_P6_PERFCTR0 0xc1 393 394 #define MSR_IA32_SMBASE 0x9e 395 #define MSR_SMI_COUNT 0x34 396 #define MSR_CORE_THREAD_COUNT 0x35 397 #define MSR_MTRRcap 0xfe 398 #define MSR_MTRRcap_VCNT 8 399 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 400 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 401 402 #define MSR_IA32_SYSENTER_CS 0x174 403 #define MSR_IA32_SYSENTER_ESP 0x175 404 #define MSR_IA32_SYSENTER_EIP 0x176 405 406 #define MSR_MCG_CAP 0x179 407 #define MSR_MCG_STATUS 0x17a 408 #define MSR_MCG_CTL 0x17b 409 #define MSR_MCG_EXT_CTL 0x4d0 410 411 #define MSR_P6_EVNTSEL0 0x186 412 413 #define MSR_IA32_PERF_STATUS 0x198 414 415 #define MSR_IA32_MISC_ENABLE 0x1a0 416 /* Indicates good rep/movs microcode on some processors: */ 417 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 418 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 419 420 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 421 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 422 423 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 424 425 #define MSR_MTRRfix64K_00000 0x250 426 #define MSR_MTRRfix16K_80000 0x258 427 #define MSR_MTRRfix16K_A0000 0x259 428 #define MSR_MTRRfix4K_C0000 0x268 429 #define MSR_MTRRfix4K_C8000 0x269 430 #define MSR_MTRRfix4K_D0000 0x26a 431 #define MSR_MTRRfix4K_D8000 0x26b 432 #define MSR_MTRRfix4K_E0000 0x26c 433 #define MSR_MTRRfix4K_E8000 0x26d 434 #define MSR_MTRRfix4K_F0000 0x26e 435 #define MSR_MTRRfix4K_F8000 0x26f 436 437 #define MSR_PAT 0x277 438 439 #define MSR_MTRRdefType 0x2ff 440 441 #define MSR_CORE_PERF_FIXED_CTR0 0x309 442 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 443 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 444 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 445 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 446 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 447 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 448 449 #define MSR_MC0_CTL 0x400 450 #define MSR_MC0_STATUS 0x401 451 #define MSR_MC0_ADDR 0x402 452 #define MSR_MC0_MISC 0x403 453 454 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 455 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 456 #define MSR_IA32_RTIT_CTL 0x570 457 #define MSR_IA32_RTIT_STATUS 0x571 458 #define MSR_IA32_RTIT_CR3_MATCH 0x572 459 #define MSR_IA32_RTIT_ADDR0_A 0x580 460 #define MSR_IA32_RTIT_ADDR0_B 0x581 461 #define MSR_IA32_RTIT_ADDR1_A 0x582 462 #define MSR_IA32_RTIT_ADDR1_B 0x583 463 #define MSR_IA32_RTIT_ADDR2_A 0x584 464 #define MSR_IA32_RTIT_ADDR2_B 0x585 465 #define MSR_IA32_RTIT_ADDR3_A 0x586 466 #define MSR_IA32_RTIT_ADDR3_B 0x587 467 #define MAX_RTIT_ADDRS 8 468 469 #define MSR_EFER 0xc0000080 470 471 #define MSR_EFER_SCE (1 << 0) 472 #define MSR_EFER_LME (1 << 8) 473 #define MSR_EFER_LMA (1 << 10) 474 #define MSR_EFER_NXE (1 << 11) 475 #define MSR_EFER_SVME (1 << 12) 476 #define MSR_EFER_FFXSR (1 << 14) 477 478 #define MSR_EFER_RESERVED\ 479 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\ 480 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\ 481 | MSR_EFER_FFXSR)) 482 483 #define MSR_STAR 0xc0000081 484 #define MSR_LSTAR 0xc0000082 485 #define MSR_CSTAR 0xc0000083 486 #define MSR_FMASK 0xc0000084 487 #define MSR_FSBASE 0xc0000100 488 #define MSR_GSBASE 0xc0000101 489 #define MSR_KERNELGSBASE 0xc0000102 490 #define MSR_TSC_AUX 0xc0000103 491 492 #define MSR_VM_HSAVE_PA 0xc0010117 493 494 #define MSR_IA32_BNDCFGS 0x00000d90 495 #define MSR_IA32_XSS 0x00000da0 496 #define MSR_IA32_UMWAIT_CONTROL 0xe1 497 498 #define MSR_IA32_VMX_BASIC 0x00000480 499 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 500 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 501 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 502 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 503 #define MSR_IA32_VMX_MISC 0x00000485 504 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 505 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 506 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 507 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 508 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 509 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 510 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 511 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 512 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 513 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 514 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 515 #define MSR_IA32_VMX_VMFUNC 0x00000491 516 517 #define XSTATE_FP_BIT 0 518 #define XSTATE_SSE_BIT 1 519 #define XSTATE_YMM_BIT 2 520 #define XSTATE_BNDREGS_BIT 3 521 #define XSTATE_BNDCSR_BIT 4 522 #define XSTATE_OPMASK_BIT 5 523 #define XSTATE_ZMM_Hi256_BIT 6 524 #define XSTATE_Hi16_ZMM_BIT 7 525 #define XSTATE_PKRU_BIT 9 526 527 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 528 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 529 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 530 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 531 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 532 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 533 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 534 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 535 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 536 537 /* CPUID feature words */ 538 typedef enum FeatureWord { 539 FEAT_1_EDX, /* CPUID[1].EDX */ 540 FEAT_1_ECX, /* CPUID[1].ECX */ 541 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 542 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 543 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 544 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 545 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 546 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 547 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 548 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 549 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 550 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 551 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 552 FEAT_SVM, /* CPUID[8000_000A].EDX */ 553 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 554 FEAT_6_EAX, /* CPUID[6].EAX */ 555 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 556 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 557 FEAT_ARCH_CAPABILITIES, 558 FEAT_CORE_CAPABILITY, 559 FEAT_PERF_CAPABILITIES, 560 FEAT_VMX_PROCBASED_CTLS, 561 FEAT_VMX_SECONDARY_CTLS, 562 FEAT_VMX_PINBASED_CTLS, 563 FEAT_VMX_EXIT_CTLS, 564 FEAT_VMX_ENTRY_CTLS, 565 FEAT_VMX_MISC, 566 FEAT_VMX_EPT_VPID_CAPS, 567 FEAT_VMX_BASIC, 568 FEAT_VMX_VMFUNC, 569 FEAT_14_0_ECX, 570 FEATURE_WORDS, 571 } FeatureWord; 572 573 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 574 575 /* cpuid_features bits */ 576 #define CPUID_FP87 (1U << 0) 577 #define CPUID_VME (1U << 1) 578 #define CPUID_DE (1U << 2) 579 #define CPUID_PSE (1U << 3) 580 #define CPUID_TSC (1U << 4) 581 #define CPUID_MSR (1U << 5) 582 #define CPUID_PAE (1U << 6) 583 #define CPUID_MCE (1U << 7) 584 #define CPUID_CX8 (1U << 8) 585 #define CPUID_APIC (1U << 9) 586 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 587 #define CPUID_MTRR (1U << 12) 588 #define CPUID_PGE (1U << 13) 589 #define CPUID_MCA (1U << 14) 590 #define CPUID_CMOV (1U << 15) 591 #define CPUID_PAT (1U << 16) 592 #define CPUID_PSE36 (1U << 17) 593 #define CPUID_PN (1U << 18) 594 #define CPUID_CLFLUSH (1U << 19) 595 #define CPUID_DTS (1U << 21) 596 #define CPUID_ACPI (1U << 22) 597 #define CPUID_MMX (1U << 23) 598 #define CPUID_FXSR (1U << 24) 599 #define CPUID_SSE (1U << 25) 600 #define CPUID_SSE2 (1U << 26) 601 #define CPUID_SS (1U << 27) 602 #define CPUID_HT (1U << 28) 603 #define CPUID_TM (1U << 29) 604 #define CPUID_IA64 (1U << 30) 605 #define CPUID_PBE (1U << 31) 606 607 #define CPUID_EXT_SSE3 (1U << 0) 608 #define CPUID_EXT_PCLMULQDQ (1U << 1) 609 #define CPUID_EXT_DTES64 (1U << 2) 610 #define CPUID_EXT_MONITOR (1U << 3) 611 #define CPUID_EXT_DSCPL (1U << 4) 612 #define CPUID_EXT_VMX (1U << 5) 613 #define CPUID_EXT_SMX (1U << 6) 614 #define CPUID_EXT_EST (1U << 7) 615 #define CPUID_EXT_TM2 (1U << 8) 616 #define CPUID_EXT_SSSE3 (1U << 9) 617 #define CPUID_EXT_CID (1U << 10) 618 #define CPUID_EXT_FMA (1U << 12) 619 #define CPUID_EXT_CX16 (1U << 13) 620 #define CPUID_EXT_XTPR (1U << 14) 621 #define CPUID_EXT_PDCM (1U << 15) 622 #define CPUID_EXT_PCID (1U << 17) 623 #define CPUID_EXT_DCA (1U << 18) 624 #define CPUID_EXT_SSE41 (1U << 19) 625 #define CPUID_EXT_SSE42 (1U << 20) 626 #define CPUID_EXT_X2APIC (1U << 21) 627 #define CPUID_EXT_MOVBE (1U << 22) 628 #define CPUID_EXT_POPCNT (1U << 23) 629 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 630 #define CPUID_EXT_AES (1U << 25) 631 #define CPUID_EXT_XSAVE (1U << 26) 632 #define CPUID_EXT_OSXSAVE (1U << 27) 633 #define CPUID_EXT_AVX (1U << 28) 634 #define CPUID_EXT_F16C (1U << 29) 635 #define CPUID_EXT_RDRAND (1U << 30) 636 #define CPUID_EXT_HYPERVISOR (1U << 31) 637 638 #define CPUID_EXT2_FPU (1U << 0) 639 #define CPUID_EXT2_VME (1U << 1) 640 #define CPUID_EXT2_DE (1U << 2) 641 #define CPUID_EXT2_PSE (1U << 3) 642 #define CPUID_EXT2_TSC (1U << 4) 643 #define CPUID_EXT2_MSR (1U << 5) 644 #define CPUID_EXT2_PAE (1U << 6) 645 #define CPUID_EXT2_MCE (1U << 7) 646 #define CPUID_EXT2_CX8 (1U << 8) 647 #define CPUID_EXT2_APIC (1U << 9) 648 #define CPUID_EXT2_SYSCALL (1U << 11) 649 #define CPUID_EXT2_MTRR (1U << 12) 650 #define CPUID_EXT2_PGE (1U << 13) 651 #define CPUID_EXT2_MCA (1U << 14) 652 #define CPUID_EXT2_CMOV (1U << 15) 653 #define CPUID_EXT2_PAT (1U << 16) 654 #define CPUID_EXT2_PSE36 (1U << 17) 655 #define CPUID_EXT2_MP (1U << 19) 656 #define CPUID_EXT2_NX (1U << 20) 657 #define CPUID_EXT2_MMXEXT (1U << 22) 658 #define CPUID_EXT2_MMX (1U << 23) 659 #define CPUID_EXT2_FXSR (1U << 24) 660 #define CPUID_EXT2_FFXSR (1U << 25) 661 #define CPUID_EXT2_PDPE1GB (1U << 26) 662 #define CPUID_EXT2_RDTSCP (1U << 27) 663 #define CPUID_EXT2_LM (1U << 29) 664 #define CPUID_EXT2_3DNOWEXT (1U << 30) 665 #define CPUID_EXT2_3DNOW (1U << 31) 666 667 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 668 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 669 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 670 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 671 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 672 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 673 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 674 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 675 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 676 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 677 678 #define CPUID_EXT3_LAHF_LM (1U << 0) 679 #define CPUID_EXT3_CMP_LEG (1U << 1) 680 #define CPUID_EXT3_SVM (1U << 2) 681 #define CPUID_EXT3_EXTAPIC (1U << 3) 682 #define CPUID_EXT3_CR8LEG (1U << 4) 683 #define CPUID_EXT3_ABM (1U << 5) 684 #define CPUID_EXT3_SSE4A (1U << 6) 685 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 686 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 687 #define CPUID_EXT3_OSVW (1U << 9) 688 #define CPUID_EXT3_IBS (1U << 10) 689 #define CPUID_EXT3_XOP (1U << 11) 690 #define CPUID_EXT3_SKINIT (1U << 12) 691 #define CPUID_EXT3_WDT (1U << 13) 692 #define CPUID_EXT3_LWP (1U << 15) 693 #define CPUID_EXT3_FMA4 (1U << 16) 694 #define CPUID_EXT3_TCE (1U << 17) 695 #define CPUID_EXT3_NODEID (1U << 19) 696 #define CPUID_EXT3_TBM (1U << 21) 697 #define CPUID_EXT3_TOPOEXT (1U << 22) 698 #define CPUID_EXT3_PERFCORE (1U << 23) 699 #define CPUID_EXT3_PERFNB (1U << 24) 700 701 #define CPUID_SVM_NPT (1U << 0) 702 #define CPUID_SVM_LBRV (1U << 1) 703 #define CPUID_SVM_SVMLOCK (1U << 2) 704 #define CPUID_SVM_NRIPSAVE (1U << 3) 705 #define CPUID_SVM_TSCSCALE (1U << 4) 706 #define CPUID_SVM_VMCBCLEAN (1U << 5) 707 #define CPUID_SVM_FLUSHASID (1U << 6) 708 #define CPUID_SVM_DECODEASSIST (1U << 7) 709 #define CPUID_SVM_PAUSEFILTER (1U << 10) 710 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 711 #define CPUID_SVM_AVIC (1U << 13) 712 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) 713 #define CPUID_SVM_VGIF (1U << 16) 714 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) 715 716 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 717 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 718 /* 1st Group of Advanced Bit Manipulation Extensions */ 719 #define CPUID_7_0_EBX_BMI1 (1U << 3) 720 /* Hardware Lock Elision */ 721 #define CPUID_7_0_EBX_HLE (1U << 4) 722 /* Intel Advanced Vector Extensions 2 */ 723 #define CPUID_7_0_EBX_AVX2 (1U << 5) 724 /* Supervisor-mode Execution Prevention */ 725 #define CPUID_7_0_EBX_SMEP (1U << 7) 726 /* 2nd Group of Advanced Bit Manipulation Extensions */ 727 #define CPUID_7_0_EBX_BMI2 (1U << 8) 728 /* Enhanced REP MOVSB/STOSB */ 729 #define CPUID_7_0_EBX_ERMS (1U << 9) 730 /* Invalidate Process-Context Identifier */ 731 #define CPUID_7_0_EBX_INVPCID (1U << 10) 732 /* Restricted Transactional Memory */ 733 #define CPUID_7_0_EBX_RTM (1U << 11) 734 /* Memory Protection Extension */ 735 #define CPUID_7_0_EBX_MPX (1U << 14) 736 /* AVX-512 Foundation */ 737 #define CPUID_7_0_EBX_AVX512F (1U << 16) 738 /* AVX-512 Doubleword & Quadword Instruction */ 739 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 740 /* Read Random SEED */ 741 #define CPUID_7_0_EBX_RDSEED (1U << 18) 742 /* ADCX and ADOX instructions */ 743 #define CPUID_7_0_EBX_ADX (1U << 19) 744 /* Supervisor Mode Access Prevention */ 745 #define CPUID_7_0_EBX_SMAP (1U << 20) 746 /* AVX-512 Integer Fused Multiply Add */ 747 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 748 /* Persistent Commit */ 749 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 750 /* Flush a Cache Line Optimized */ 751 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 752 /* Cache Line Write Back */ 753 #define CPUID_7_0_EBX_CLWB (1U << 24) 754 /* Intel Processor Trace */ 755 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 756 /* AVX-512 Prefetch */ 757 #define CPUID_7_0_EBX_AVX512PF (1U << 26) 758 /* AVX-512 Exponential and Reciprocal */ 759 #define CPUID_7_0_EBX_AVX512ER (1U << 27) 760 /* AVX-512 Conflict Detection */ 761 #define CPUID_7_0_EBX_AVX512CD (1U << 28) 762 /* SHA1/SHA256 Instruction Extensions */ 763 #define CPUID_7_0_EBX_SHA_NI (1U << 29) 764 /* AVX-512 Byte and Word Instructions */ 765 #define CPUID_7_0_EBX_AVX512BW (1U << 30) 766 /* AVX-512 Vector Length Extensions */ 767 #define CPUID_7_0_EBX_AVX512VL (1U << 31) 768 769 /* AVX-512 Vector Byte Manipulation Instruction */ 770 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 771 /* User-Mode Instruction Prevention */ 772 #define CPUID_7_0_ECX_UMIP (1U << 2) 773 /* Protection Keys for User-mode Pages */ 774 #define CPUID_7_0_ECX_PKU (1U << 3) 775 /* OS Enable Protection Keys */ 776 #define CPUID_7_0_ECX_OSPKE (1U << 4) 777 /* UMONITOR/UMWAIT/TPAUSE Instructions */ 778 #define CPUID_7_0_ECX_WAITPKG (1U << 5) 779 /* Additional AVX-512 Vector Byte Manipulation Instruction */ 780 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 781 /* Galois Field New Instructions */ 782 #define CPUID_7_0_ECX_GFNI (1U << 8) 783 /* Vector AES Instructions */ 784 #define CPUID_7_0_ECX_VAES (1U << 9) 785 /* Carry-Less Multiplication Quadword */ 786 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 787 /* Vector Neural Network Instructions */ 788 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 789 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 790 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 791 /* POPCNT for vectors of DW/QW */ 792 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 793 /* 5-level Page Tables */ 794 #define CPUID_7_0_ECX_LA57 (1U << 16) 795 /* Read Processor ID */ 796 #define CPUID_7_0_ECX_RDPID (1U << 22) 797 /* Bus Lock Debug Exception */ 798 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) 799 /* Cache Line Demote Instruction */ 800 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 801 /* Move Doubleword as Direct Store Instruction */ 802 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 803 /* Move 64 Bytes as Direct Store Instruction */ 804 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 805 /* Protection Keys for Supervisor-mode Pages */ 806 #define CPUID_7_0_ECX_PKS (1U << 31) 807 808 /* AVX512 Neural Network Instructions */ 809 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 810 /* AVX512 Multiply Accumulation Single Precision */ 811 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 812 /* Fast Short Rep Mov */ 813 #define CPUID_7_0_EDX_FSRM (1U << 4) 814 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 815 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 816 /* SERIALIZE instruction */ 817 #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 818 /* TSX Suspend Load Address Tracking instruction */ 819 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 820 /* AVX512_FP16 instruction */ 821 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) 822 /* Speculation Control */ 823 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 824 /* Single Thread Indirect Branch Predictors */ 825 #define CPUID_7_0_EDX_STIBP (1U << 27) 826 /* Arch Capabilities */ 827 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 828 /* Core Capability */ 829 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 830 /* Speculative Store Bypass Disable */ 831 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 832 833 /* AVX VNNI Instruction */ 834 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) 835 /* AVX512 BFloat16 Instruction */ 836 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 837 838 /* Packets which contain IP payload have LIP values */ 839 #define CPUID_14_0_ECX_LIP (1U << 31) 840 841 /* CLZERO instruction */ 842 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 843 /* Always save/restore FP error pointers */ 844 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 845 /* Write back and do not invalidate cache */ 846 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 847 /* Indirect Branch Prediction Barrier */ 848 #define CPUID_8000_0008_EBX_IBPB (1U << 12) 849 /* Indirect Branch Restricted Speculation */ 850 #define CPUID_8000_0008_EBX_IBRS (1U << 14) 851 /* Single Thread Indirect Branch Predictors */ 852 #define CPUID_8000_0008_EBX_STIBP (1U << 15) 853 /* Speculative Store Bypass Disable */ 854 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) 855 856 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 857 #define CPUID_XSAVE_XSAVEC (1U << 1) 858 #define CPUID_XSAVE_XGETBV1 (1U << 2) 859 #define CPUID_XSAVE_XSAVES (1U << 3) 860 861 #define CPUID_6_EAX_ARAT (1U << 2) 862 863 /* CPUID[0x80000007].EDX flags: */ 864 #define CPUID_APM_INVTSC (1U << 8) 865 866 #define CPUID_VENDOR_SZ 12 867 868 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 869 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 870 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 871 #define CPUID_VENDOR_INTEL "GenuineIntel" 872 873 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 874 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 875 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 876 #define CPUID_VENDOR_AMD "AuthenticAMD" 877 878 #define CPUID_VENDOR_VIA "CentaurHauls" 879 880 #define CPUID_VENDOR_HYGON "HygonGenuine" 881 882 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 883 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 884 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 885 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 886 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 887 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 888 889 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 890 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 891 892 /* CPUID[0xB].ECX level types */ 893 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 894 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 895 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 896 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 897 898 /* MSR Feature Bits */ 899 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 900 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 901 #define MSR_ARCH_CAP_RSBA (1U << 2) 902 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 903 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 904 #define MSR_ARCH_CAP_MDS_NO (1U << 5) 905 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 906 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 907 #define MSR_ARCH_CAP_TAA_NO (1U << 8) 908 909 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 910 911 /* VMX MSR features */ 912 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 913 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 914 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 915 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 916 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 917 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 918 919 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 920 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 921 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 922 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 923 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 924 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 925 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 926 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 927 928 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 929 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 930 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 931 #define MSR_VMX_EPT_UC (1ULL << 8) 932 #define MSR_VMX_EPT_WB (1ULL << 14) 933 #define MSR_VMX_EPT_2MB (1ULL << 16) 934 #define MSR_VMX_EPT_1GB (1ULL << 17) 935 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 936 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 937 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 938 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 939 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 940 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 941 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 942 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 943 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 944 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 945 946 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 947 948 949 /* VMX controls */ 950 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 951 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 952 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 953 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 954 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 955 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 956 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 957 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 958 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 959 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 960 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 961 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 962 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 963 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 964 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 965 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 966 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 967 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 968 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 969 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 970 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 971 972 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 973 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 974 #define VMX_SECONDARY_EXEC_DESC 0x00000004 975 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 976 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 977 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 978 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 979 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 980 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 981 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 982 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 983 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 984 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 985 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 986 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 987 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 988 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 989 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 990 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 991 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000 992 993 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 994 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 995 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 996 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 997 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 998 999 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 1000 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 1001 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 1002 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 1003 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 1004 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 1005 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 1006 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 1007 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 1008 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 1009 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 1010 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 1011 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 1012 1013 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 1014 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 1015 #define VMX_VM_ENTRY_SMM 0x00000400 1016 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 1017 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 1018 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 1019 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 1020 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 1021 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 1022 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 1023 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 1024 1025 /* Supported Hyper-V Enlightenments */ 1026 #define HYPERV_FEAT_RELAXED 0 1027 #define HYPERV_FEAT_VAPIC 1 1028 #define HYPERV_FEAT_TIME 2 1029 #define HYPERV_FEAT_CRASH 3 1030 #define HYPERV_FEAT_RESET 4 1031 #define HYPERV_FEAT_VPINDEX 5 1032 #define HYPERV_FEAT_RUNTIME 6 1033 #define HYPERV_FEAT_SYNIC 7 1034 #define HYPERV_FEAT_STIMER 8 1035 #define HYPERV_FEAT_FREQUENCIES 9 1036 #define HYPERV_FEAT_REENLIGHTENMENT 10 1037 #define HYPERV_FEAT_TLBFLUSH 11 1038 #define HYPERV_FEAT_EVMCS 12 1039 #define HYPERV_FEAT_IPI 13 1040 #define HYPERV_FEAT_STIMER_DIRECT 14 1041 1042 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY 1043 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF 1044 #endif 1045 1046 #define EXCP00_DIVZ 0 1047 #define EXCP01_DB 1 1048 #define EXCP02_NMI 2 1049 #define EXCP03_INT3 3 1050 #define EXCP04_INTO 4 1051 #define EXCP05_BOUND 5 1052 #define EXCP06_ILLOP 6 1053 #define EXCP07_PREX 7 1054 #define EXCP08_DBLE 8 1055 #define EXCP09_XERR 9 1056 #define EXCP0A_TSS 10 1057 #define EXCP0B_NOSEG 11 1058 #define EXCP0C_STACK 12 1059 #define EXCP0D_GPF 13 1060 #define EXCP0E_PAGE 14 1061 #define EXCP10_COPR 16 1062 #define EXCP11_ALGN 17 1063 #define EXCP12_MCHK 18 1064 1065 #define EXCP_VMEXIT 0x100 /* only for system emulation */ 1066 #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1067 #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1068 1069 /* i386-specific interrupt pending bits. */ 1070 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1071 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1072 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1073 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1074 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1075 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1076 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1077 1078 /* Use a clearer name for this. */ 1079 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1080 1081 /* Instead of computing the condition codes after each x86 instruction, 1082 * QEMU just stores one operand (called CC_SRC), the result 1083 * (called CC_DST) and the type of operation (called CC_OP). When the 1084 * condition codes are needed, the condition codes can be calculated 1085 * using this information. Condition codes are not generated if they 1086 * are only needed for conditional branches. 1087 */ 1088 typedef enum { 1089 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1090 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1091 1092 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1093 CC_OP_MULW, 1094 CC_OP_MULL, 1095 CC_OP_MULQ, 1096 1097 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1098 CC_OP_ADDW, 1099 CC_OP_ADDL, 1100 CC_OP_ADDQ, 1101 1102 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1103 CC_OP_ADCW, 1104 CC_OP_ADCL, 1105 CC_OP_ADCQ, 1106 1107 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1108 CC_OP_SUBW, 1109 CC_OP_SUBL, 1110 CC_OP_SUBQ, 1111 1112 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1113 CC_OP_SBBW, 1114 CC_OP_SBBL, 1115 CC_OP_SBBQ, 1116 1117 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1118 CC_OP_LOGICW, 1119 CC_OP_LOGICL, 1120 CC_OP_LOGICQ, 1121 1122 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1123 CC_OP_INCW, 1124 CC_OP_INCL, 1125 CC_OP_INCQ, 1126 1127 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1128 CC_OP_DECW, 1129 CC_OP_DECL, 1130 CC_OP_DECQ, 1131 1132 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1133 CC_OP_SHLW, 1134 CC_OP_SHLL, 1135 CC_OP_SHLQ, 1136 1137 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1138 CC_OP_SARW, 1139 CC_OP_SARL, 1140 CC_OP_SARQ, 1141 1142 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1143 CC_OP_BMILGW, 1144 CC_OP_BMILGL, 1145 CC_OP_BMILGQ, 1146 1147 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1148 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1149 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1150 1151 CC_OP_CLR, /* Z set, all other flags clear. */ 1152 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1153 1154 CC_OP_NB, 1155 } CCOp; 1156 1157 typedef struct SegmentCache { 1158 uint32_t selector; 1159 target_ulong base; 1160 uint32_t limit; 1161 uint32_t flags; 1162 } SegmentCache; 1163 1164 #define MMREG_UNION(n, bits) \ 1165 union n { \ 1166 uint8_t _b_##n[(bits)/8]; \ 1167 uint16_t _w_##n[(bits)/16]; \ 1168 uint32_t _l_##n[(bits)/32]; \ 1169 uint64_t _q_##n[(bits)/64]; \ 1170 float32 _s_##n[(bits)/32]; \ 1171 float64 _d_##n[(bits)/64]; \ 1172 } 1173 1174 typedef union { 1175 uint8_t _b[16]; 1176 uint16_t _w[8]; 1177 uint32_t _l[4]; 1178 uint64_t _q[2]; 1179 } XMMReg; 1180 1181 typedef union { 1182 uint8_t _b[32]; 1183 uint16_t _w[16]; 1184 uint32_t _l[8]; 1185 uint64_t _q[4]; 1186 } YMMReg; 1187 1188 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1189 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1190 1191 typedef struct BNDReg { 1192 uint64_t lb; 1193 uint64_t ub; 1194 } BNDReg; 1195 1196 typedef struct BNDCSReg { 1197 uint64_t cfgu; 1198 uint64_t sts; 1199 } BNDCSReg; 1200 1201 #define BNDCFG_ENABLE 1ULL 1202 #define BNDCFG_BNDPRESERVE 2ULL 1203 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1204 1205 #ifdef HOST_WORDS_BIGENDIAN 1206 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1207 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1208 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1209 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1210 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1211 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1212 1213 #define MMX_B(n) _b_MMXReg[7 - (n)] 1214 #define MMX_W(n) _w_MMXReg[3 - (n)] 1215 #define MMX_L(n) _l_MMXReg[1 - (n)] 1216 #define MMX_S(n) _s_MMXReg[1 - (n)] 1217 #else 1218 #define ZMM_B(n) _b_ZMMReg[n] 1219 #define ZMM_W(n) _w_ZMMReg[n] 1220 #define ZMM_L(n) _l_ZMMReg[n] 1221 #define ZMM_S(n) _s_ZMMReg[n] 1222 #define ZMM_Q(n) _q_ZMMReg[n] 1223 #define ZMM_D(n) _d_ZMMReg[n] 1224 1225 #define MMX_B(n) _b_MMXReg[n] 1226 #define MMX_W(n) _w_MMXReg[n] 1227 #define MMX_L(n) _l_MMXReg[n] 1228 #define MMX_S(n) _s_MMXReg[n] 1229 #endif 1230 #define MMX_Q(n) _q_MMXReg[n] 1231 1232 typedef union { 1233 floatx80 d __attribute__((aligned(16))); 1234 MMXReg mmx; 1235 } FPReg; 1236 1237 typedef struct { 1238 uint64_t base; 1239 uint64_t mask; 1240 } MTRRVar; 1241 1242 #define CPU_NB_REGS64 16 1243 #define CPU_NB_REGS32 8 1244 1245 #ifdef TARGET_X86_64 1246 #define CPU_NB_REGS CPU_NB_REGS64 1247 #else 1248 #define CPU_NB_REGS CPU_NB_REGS32 1249 #endif 1250 1251 #define MAX_FIXED_COUNTERS 3 1252 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1253 1254 #define TARGET_INSN_START_EXTRA_WORDS 1 1255 1256 #define NB_OPMASK_REGS 8 1257 1258 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1259 * that APIC ID hasn't been set yet 1260 */ 1261 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1262 1263 typedef union X86LegacyXSaveArea { 1264 struct { 1265 uint16_t fcw; 1266 uint16_t fsw; 1267 uint8_t ftw; 1268 uint8_t reserved; 1269 uint16_t fpop; 1270 uint64_t fpip; 1271 uint64_t fpdp; 1272 uint32_t mxcsr; 1273 uint32_t mxcsr_mask; 1274 FPReg fpregs[8]; 1275 uint8_t xmm_regs[16][16]; 1276 }; 1277 uint8_t data[512]; 1278 } X86LegacyXSaveArea; 1279 1280 typedef struct X86XSaveHeader { 1281 uint64_t xstate_bv; 1282 uint64_t xcomp_bv; 1283 uint64_t reserve0; 1284 uint8_t reserved[40]; 1285 } X86XSaveHeader; 1286 1287 /* Ext. save area 2: AVX State */ 1288 typedef struct XSaveAVX { 1289 uint8_t ymmh[16][16]; 1290 } XSaveAVX; 1291 1292 /* Ext. save area 3: BNDREG */ 1293 typedef struct XSaveBNDREG { 1294 BNDReg bnd_regs[4]; 1295 } XSaveBNDREG; 1296 1297 /* Ext. save area 4: BNDCSR */ 1298 typedef union XSaveBNDCSR { 1299 BNDCSReg bndcsr; 1300 uint8_t data[64]; 1301 } XSaveBNDCSR; 1302 1303 /* Ext. save area 5: Opmask */ 1304 typedef struct XSaveOpmask { 1305 uint64_t opmask_regs[NB_OPMASK_REGS]; 1306 } XSaveOpmask; 1307 1308 /* Ext. save area 6: ZMM_Hi256 */ 1309 typedef struct XSaveZMM_Hi256 { 1310 uint8_t zmm_hi256[16][32]; 1311 } XSaveZMM_Hi256; 1312 1313 /* Ext. save area 7: Hi16_ZMM */ 1314 typedef struct XSaveHi16_ZMM { 1315 uint8_t hi16_zmm[16][64]; 1316 } XSaveHi16_ZMM; 1317 1318 /* Ext. save area 9: PKRU state */ 1319 typedef struct XSavePKRU { 1320 uint32_t pkru; 1321 uint32_t padding; 1322 } XSavePKRU; 1323 1324 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1325 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1326 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1327 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1328 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1329 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1330 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1331 1332 typedef struct ExtSaveArea { 1333 uint32_t feature, bits; 1334 uint32_t offset, size; 1335 } ExtSaveArea; 1336 1337 #define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) 1338 1339 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; 1340 1341 typedef enum TPRAccess { 1342 TPR_ACCESS_READ, 1343 TPR_ACCESS_WRITE, 1344 } TPRAccess; 1345 1346 /* Cache information data structures: */ 1347 1348 enum CacheType { 1349 DATA_CACHE, 1350 INSTRUCTION_CACHE, 1351 UNIFIED_CACHE 1352 }; 1353 1354 typedef struct CPUCacheInfo { 1355 enum CacheType type; 1356 uint8_t level; 1357 /* Size in bytes */ 1358 uint32_t size; 1359 /* Line size, in bytes */ 1360 uint16_t line_size; 1361 /* 1362 * Associativity. 1363 * Note: representation of fully-associative caches is not implemented 1364 */ 1365 uint8_t associativity; 1366 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1367 uint8_t partitions; 1368 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1369 uint32_t sets; 1370 /* 1371 * Lines per tag. 1372 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1373 * (Is this synonym to @partitions?) 1374 */ 1375 uint8_t lines_per_tag; 1376 1377 /* Self-initializing cache */ 1378 bool self_init; 1379 /* 1380 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1381 * non-originating threads sharing this cache. 1382 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1383 */ 1384 bool no_invd_sharing; 1385 /* 1386 * Cache is inclusive of lower cache levels. 1387 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1388 */ 1389 bool inclusive; 1390 /* 1391 * A complex function is used to index the cache, potentially using all 1392 * address bits. CPUID[4].EDX[bit 2]. 1393 */ 1394 bool complex_indexing; 1395 } CPUCacheInfo; 1396 1397 1398 typedef struct CPUCaches { 1399 CPUCacheInfo *l1d_cache; 1400 CPUCacheInfo *l1i_cache; 1401 CPUCacheInfo *l2_cache; 1402 CPUCacheInfo *l3_cache; 1403 } CPUCaches; 1404 1405 typedef struct HVFX86LazyFlags { 1406 target_ulong result; 1407 target_ulong auxbits; 1408 } HVFX86LazyFlags; 1409 1410 typedef struct CPUX86State { 1411 /* standard registers */ 1412 target_ulong regs[CPU_NB_REGS]; 1413 target_ulong eip; 1414 target_ulong eflags; /* eflags register. During CPU emulation, CC 1415 flags and DF are set to zero because they are 1416 stored elsewhere */ 1417 1418 /* emulator internal eflags handling */ 1419 target_ulong cc_dst; 1420 target_ulong cc_src; 1421 target_ulong cc_src2; 1422 uint32_t cc_op; 1423 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1424 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1425 are known at translation time. */ 1426 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1427 1428 /* segments */ 1429 SegmentCache segs[6]; /* selector values */ 1430 SegmentCache ldt; 1431 SegmentCache tr; 1432 SegmentCache gdt; /* only base and limit are used */ 1433 SegmentCache idt; /* only base and limit are used */ 1434 1435 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1436 int32_t a20_mask; 1437 1438 BNDReg bnd_regs[4]; 1439 BNDCSReg bndcs_regs; 1440 uint64_t msr_bndcfgs; 1441 uint64_t efer; 1442 1443 /* Beginning of state preserved by INIT (dummy marker). */ 1444 struct {} start_init_save; 1445 1446 /* FPU state */ 1447 unsigned int fpstt; /* top of stack index */ 1448 uint16_t fpus; 1449 uint16_t fpuc; 1450 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1451 FPReg fpregs[8]; 1452 /* KVM-only so far */ 1453 uint16_t fpop; 1454 uint16_t fpcs; 1455 uint16_t fpds; 1456 uint64_t fpip; 1457 uint64_t fpdp; 1458 1459 /* emulator internal variables */ 1460 float_status fp_status; 1461 floatx80 ft0; 1462 1463 float_status mmx_status; /* for 3DNow! float ops */ 1464 float_status sse_status; 1465 uint32_t mxcsr; 1466 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1467 ZMMReg xmm_t0; 1468 MMXReg mmx_t0; 1469 1470 XMMReg ymmh_regs[CPU_NB_REGS]; 1471 1472 uint64_t opmask_regs[NB_OPMASK_REGS]; 1473 YMMReg zmmh_regs[CPU_NB_REGS]; 1474 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1475 1476 /* sysenter registers */ 1477 uint32_t sysenter_cs; 1478 target_ulong sysenter_esp; 1479 target_ulong sysenter_eip; 1480 uint64_t star; 1481 1482 uint64_t vm_hsave; 1483 1484 #ifdef TARGET_X86_64 1485 target_ulong lstar; 1486 target_ulong cstar; 1487 target_ulong fmask; 1488 target_ulong kernelgsbase; 1489 #endif 1490 1491 uint64_t tsc; 1492 uint64_t tsc_adjust; 1493 uint64_t tsc_deadline; 1494 uint64_t tsc_aux; 1495 1496 uint64_t xcr0; 1497 1498 uint64_t mcg_status; 1499 uint64_t msr_ia32_misc_enable; 1500 uint64_t msr_ia32_feature_control; 1501 1502 uint64_t msr_fixed_ctr_ctrl; 1503 uint64_t msr_global_ctrl; 1504 uint64_t msr_global_status; 1505 uint64_t msr_global_ovf_ctrl; 1506 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1507 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1508 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1509 1510 uint64_t pat; 1511 uint32_t smbase; 1512 uint64_t msr_smi_count; 1513 1514 uint32_t pkru; 1515 uint32_t pkrs; 1516 uint32_t tsx_ctrl; 1517 1518 uint64_t spec_ctrl; 1519 uint64_t virt_ssbd; 1520 1521 /* End of state preserved by INIT (dummy marker). */ 1522 struct {} end_init_save; 1523 1524 uint64_t system_time_msr; 1525 uint64_t wall_clock_msr; 1526 uint64_t steal_time_msr; 1527 uint64_t async_pf_en_msr; 1528 uint64_t async_pf_int_msr; 1529 uint64_t pv_eoi_en_msr; 1530 uint64_t poll_control_msr; 1531 1532 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1533 uint64_t msr_hv_hypercall; 1534 uint64_t msr_hv_guest_os_id; 1535 uint64_t msr_hv_tsc; 1536 1537 /* Per-VCPU HV MSRs */ 1538 uint64_t msr_hv_vapic; 1539 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1540 uint64_t msr_hv_runtime; 1541 uint64_t msr_hv_synic_control; 1542 uint64_t msr_hv_synic_evt_page; 1543 uint64_t msr_hv_synic_msg_page; 1544 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1545 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1546 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1547 uint64_t msr_hv_reenlightenment_control; 1548 uint64_t msr_hv_tsc_emulation_control; 1549 uint64_t msr_hv_tsc_emulation_status; 1550 1551 uint64_t msr_rtit_ctrl; 1552 uint64_t msr_rtit_status; 1553 uint64_t msr_rtit_output_base; 1554 uint64_t msr_rtit_output_mask; 1555 uint64_t msr_rtit_cr3_match; 1556 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1557 1558 /* exception/interrupt handling */ 1559 int error_code; 1560 int exception_is_int; 1561 target_ulong exception_next_eip; 1562 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1563 union { 1564 struct CPUBreakpoint *cpu_breakpoint[4]; 1565 struct CPUWatchpoint *cpu_watchpoint[4]; 1566 }; /* break/watchpoints for dr[0..3] */ 1567 int old_exception; /* exception in flight */ 1568 1569 uint64_t vm_vmcb; 1570 uint64_t tsc_offset; 1571 uint64_t intercept; 1572 uint16_t intercept_cr_read; 1573 uint16_t intercept_cr_write; 1574 uint16_t intercept_dr_read; 1575 uint16_t intercept_dr_write; 1576 uint32_t intercept_exceptions; 1577 uint64_t nested_cr3; 1578 uint32_t nested_pg_mode; 1579 uint8_t v_tpr; 1580 1581 /* KVM states, automatically cleared on reset */ 1582 uint8_t nmi_injected; 1583 uint8_t nmi_pending; 1584 1585 uintptr_t retaddr; 1586 1587 /* Fields up to this point are cleared by a CPU reset */ 1588 struct {} end_reset_fields; 1589 1590 /* Fields after this point are preserved across CPU reset. */ 1591 1592 /* processor features (e.g. for CPUID insn) */ 1593 /* Minimum cpuid leaf 7 value */ 1594 uint32_t cpuid_level_func7; 1595 /* Actual cpuid leaf 7 value */ 1596 uint32_t cpuid_min_level_func7; 1597 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1598 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1599 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1600 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1601 /* Actual level/xlevel/xlevel2 value: */ 1602 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1603 uint32_t cpuid_vendor1; 1604 uint32_t cpuid_vendor2; 1605 uint32_t cpuid_vendor3; 1606 uint32_t cpuid_version; 1607 FeatureWordArray features; 1608 /* Features that were explicitly enabled/disabled */ 1609 FeatureWordArray user_features; 1610 uint32_t cpuid_model[12]; 1611 /* Cache information for CPUID. When legacy-cache=on, the cache data 1612 * on each CPUID leaf will be different, because we keep compatibility 1613 * with old QEMU versions. 1614 */ 1615 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1616 1617 /* MTRRs */ 1618 uint64_t mtrr_fixed[11]; 1619 uint64_t mtrr_deftype; 1620 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1621 1622 /* For KVM */ 1623 uint32_t mp_state; 1624 int32_t exception_nr; 1625 int32_t interrupt_injected; 1626 uint8_t soft_interrupt; 1627 uint8_t exception_pending; 1628 uint8_t exception_injected; 1629 uint8_t has_error_code; 1630 uint8_t exception_has_payload; 1631 uint64_t exception_payload; 1632 uint32_t ins_len; 1633 uint32_t sipi_vector; 1634 bool tsc_valid; 1635 int64_t tsc_khz; 1636 int64_t user_tsc_khz; /* for sanity check only */ 1637 uint64_t apic_bus_freq; 1638 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1639 void *xsave_buf; 1640 uint32_t xsave_buf_len; 1641 #endif 1642 #if defined(CONFIG_KVM) 1643 struct kvm_nested_state *nested_state; 1644 #endif 1645 #if defined(CONFIG_HVF) 1646 HVFX86LazyFlags hvf_lflags; 1647 void *hvf_mmio_buf; 1648 #endif 1649 1650 uint64_t mcg_cap; 1651 uint64_t mcg_ctl; 1652 uint64_t mcg_ext_ctl; 1653 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1654 uint64_t xstate_bv; 1655 1656 /* vmstate */ 1657 uint16_t fpus_vmstate; 1658 uint16_t fptag_vmstate; 1659 uint16_t fpregs_format_vmstate; 1660 1661 uint64_t xss; 1662 uint32_t umwait; 1663 1664 TPRAccess tpr_access_type; 1665 1666 unsigned nr_dies; 1667 } CPUX86State; 1668 1669 struct kvm_msrs; 1670 1671 /** 1672 * X86CPU: 1673 * @env: #CPUX86State 1674 * @migratable: If set, only migratable flags will be accepted when "enforce" 1675 * mode is used, and only migratable flags will be included in the "host" 1676 * CPU model. 1677 * 1678 * An x86 CPU. 1679 */ 1680 struct X86CPU { 1681 /*< private >*/ 1682 CPUState parent_obj; 1683 /*< public >*/ 1684 1685 CPUNegativeOffsetState neg; 1686 CPUX86State env; 1687 VMChangeStateEntry *vmsentry; 1688 1689 uint64_t ucode_rev; 1690 1691 uint32_t hyperv_spinlock_attempts; 1692 char *hyperv_vendor; 1693 bool hyperv_synic_kvm_only; 1694 uint64_t hyperv_features; 1695 bool hyperv_passthrough; 1696 OnOffAuto hyperv_no_nonarch_cs; 1697 uint32_t hyperv_vendor_id[3]; 1698 uint32_t hyperv_interface_id[4]; 1699 uint32_t hyperv_version_id[4]; 1700 uint32_t hyperv_limits[3]; 1701 uint32_t hyperv_nested[4]; 1702 1703 bool check_cpuid; 1704 bool enforce_cpuid; 1705 /* 1706 * Force features to be enabled even if the host doesn't support them. 1707 * This is dangerous and should be done only for testing CPUID 1708 * compatibility. 1709 */ 1710 bool force_features; 1711 bool expose_kvm; 1712 bool expose_tcg; 1713 bool migratable; 1714 bool migrate_smi_count; 1715 bool max_features; /* Enable all supported features automatically */ 1716 uint32_t apic_id; 1717 1718 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1719 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1720 bool vmware_cpuid_freq; 1721 1722 /* if true the CPUID code directly forward host cache leaves to the guest */ 1723 bool cache_info_passthrough; 1724 1725 /* if true the CPUID code directly forwards 1726 * host monitor/mwait leaves to the guest */ 1727 struct { 1728 uint32_t eax; 1729 uint32_t ebx; 1730 uint32_t ecx; 1731 uint32_t edx; 1732 } mwait; 1733 1734 /* Features that were filtered out because of missing host capabilities */ 1735 FeatureWordArray filtered_features; 1736 1737 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1738 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1739 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1740 * capabilities) directly to the guest. 1741 */ 1742 bool enable_pmu; 1743 1744 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1745 * disabled by default to avoid breaking migration between QEMU with 1746 * different LMCE configurations. 1747 */ 1748 bool enable_lmce; 1749 1750 /* Compatibility bits for old machine types. 1751 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1752 * socket share an virtual l3 cache. 1753 */ 1754 bool enable_l3_cache; 1755 1756 /* Compatibility bits for old machine types. 1757 * If true present the old cache topology information 1758 */ 1759 bool legacy_cache; 1760 1761 /* Compatibility bits for old machine types: */ 1762 bool enable_cpuid_0xb; 1763 1764 /* Enable auto level-increase for all CPUID leaves */ 1765 bool full_cpuid_auto_level; 1766 1767 /* Only advertise CPUID leaves defined by the vendor */ 1768 bool vendor_cpuid_only; 1769 1770 /* Enable auto level-increase for Intel Processor Trace leave */ 1771 bool intel_pt_auto_level; 1772 1773 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1774 bool fill_mtrr_mask; 1775 1776 /* if true override the phys_bits value with a value read from the host */ 1777 bool host_phys_bits; 1778 1779 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1780 uint8_t host_phys_bits_limit; 1781 1782 /* Stop SMI delivery for migration compatibility with old machines */ 1783 bool kvm_no_smi_migration; 1784 1785 /* Number of physical address bits supported */ 1786 uint32_t phys_bits; 1787 1788 /* in order to simplify APIC support, we leave this pointer to the 1789 user */ 1790 struct DeviceState *apic_state; 1791 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1792 Notifier machine_done; 1793 1794 struct kvm_msrs *kvm_msr_buf; 1795 1796 int32_t node_id; /* NUMA node this CPU belongs to */ 1797 int32_t socket_id; 1798 int32_t die_id; 1799 int32_t core_id; 1800 int32_t thread_id; 1801 1802 int32_t hv_max_vps; 1803 }; 1804 1805 1806 #ifndef CONFIG_USER_ONLY 1807 extern const VMStateDescription vmstate_x86_cpu; 1808 #endif 1809 1810 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1811 1812 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1813 int cpuid, void *opaque); 1814 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1815 int cpuid, void *opaque); 1816 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1817 void *opaque); 1818 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1819 void *opaque); 1820 1821 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1822 Error **errp); 1823 1824 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1825 1826 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1827 MemTxAttrs *attrs); 1828 1829 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1830 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1831 1832 void x86_cpu_list(void); 1833 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1834 1835 int cpu_get_pic_interrupt(CPUX86State *s); 1836 /* MSDOS compatibility mode FPU exception support */ 1837 void x86_register_ferr_irq(qemu_irq irq); 1838 void fpu_check_raise_ferr_irq(CPUX86State *s); 1839 void cpu_set_ignne(void); 1840 void cpu_clear_ignne(void); 1841 1842 /* mpx_helper.c */ 1843 void cpu_sync_bndcs_hflags(CPUX86State *env); 1844 1845 /* this function must always be used to load data in the segment 1846 cache: it synchronizes the hflags with the segment cache values */ 1847 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1848 X86Seg seg_reg, unsigned int selector, 1849 target_ulong base, 1850 unsigned int limit, 1851 unsigned int flags) 1852 { 1853 SegmentCache *sc; 1854 unsigned int new_hflags; 1855 1856 sc = &env->segs[seg_reg]; 1857 sc->selector = selector; 1858 sc->base = base; 1859 sc->limit = limit; 1860 sc->flags = flags; 1861 1862 /* update the hidden flags */ 1863 { 1864 if (seg_reg == R_CS) { 1865 #ifdef TARGET_X86_64 1866 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1867 /* long mode */ 1868 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1869 env->hflags &= ~(HF_ADDSEG_MASK); 1870 } else 1871 #endif 1872 { 1873 /* legacy / compatibility case */ 1874 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1875 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1876 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1877 new_hflags; 1878 } 1879 } 1880 if (seg_reg == R_SS) { 1881 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1882 #if HF_CPL_MASK != 3 1883 #error HF_CPL_MASK is hardcoded 1884 #endif 1885 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1886 /* Possibly switch between BNDCFGS and BNDCFGU */ 1887 cpu_sync_bndcs_hflags(env); 1888 } 1889 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1890 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1891 if (env->hflags & HF_CS64_MASK) { 1892 /* zero base assumed for DS, ES and SS in long mode */ 1893 } else if (!(env->cr[0] & CR0_PE_MASK) || 1894 (env->eflags & VM_MASK) || 1895 !(env->hflags & HF_CS32_MASK)) { 1896 /* XXX: try to avoid this test. The problem comes from the 1897 fact that is real mode or vm86 mode we only modify the 1898 'base' and 'selector' fields of the segment cache to go 1899 faster. A solution may be to force addseg to one in 1900 translate-i386.c. */ 1901 new_hflags |= HF_ADDSEG_MASK; 1902 } else { 1903 new_hflags |= ((env->segs[R_DS].base | 1904 env->segs[R_ES].base | 1905 env->segs[R_SS].base) != 0) << 1906 HF_ADDSEG_SHIFT; 1907 } 1908 env->hflags = (env->hflags & 1909 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1910 } 1911 } 1912 1913 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1914 uint8_t sipi_vector) 1915 { 1916 CPUState *cs = CPU(cpu); 1917 CPUX86State *env = &cpu->env; 1918 1919 env->eip = 0; 1920 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1921 sipi_vector << 12, 1922 env->segs[R_CS].limit, 1923 env->segs[R_CS].flags); 1924 cs->halted = 0; 1925 } 1926 1927 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1928 target_ulong *base, unsigned int *limit, 1929 unsigned int *flags); 1930 1931 /* op_helper.c */ 1932 /* used for debug or cpu save/restore */ 1933 1934 /* cpu-exec.c */ 1935 /* the following helpers are only usable in user mode simulation as 1936 they can trigger unexpected exceptions */ 1937 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); 1938 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1939 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1940 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1941 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1942 1943 /* you can call this signal handler from your SIGBUS and SIGSEGV 1944 signal handlers to inform the virtual CPU of exceptions. non zero 1945 is returned if the signal was handled by the virtual CPU. */ 1946 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1947 void *puc); 1948 1949 /* cpu.c */ 1950 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 1951 uint32_t vendor2, uint32_t vendor3); 1952 typedef struct PropValue { 1953 const char *prop, *value; 1954 } PropValue; 1955 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); 1956 1957 /* cpu.c other functions (cpuid) */ 1958 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1959 uint32_t *eax, uint32_t *ebx, 1960 uint32_t *ecx, uint32_t *edx); 1961 void cpu_clear_apic_feature(CPUX86State *env); 1962 void host_cpuid(uint32_t function, uint32_t count, 1963 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1964 1965 /* helper.c */ 1966 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1967 1968 #ifndef CONFIG_USER_ONLY 1969 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1970 { 1971 return !!attrs.secure; 1972 } 1973 1974 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1975 { 1976 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1977 } 1978 1979 /* 1980 * load efer and update the corresponding hflags. XXX: do consistency 1981 * checks with cpuid bits? 1982 */ 1983 void cpu_load_efer(CPUX86State *env, uint64_t val); 1984 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1985 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1986 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1987 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1988 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1989 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1990 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1991 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1992 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1993 #endif 1994 1995 /* will be suppressed */ 1996 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1997 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1998 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1999 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 2000 2001 /* hw/pc.c */ 2002 uint64_t cpu_get_tsc(CPUX86State *env); 2003 2004 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 2005 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 2006 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 2007 2008 #ifdef TARGET_X86_64 2009 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 2010 #else 2011 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 2012 #endif 2013 2014 #define cpu_signal_handler cpu_x86_signal_handler 2015 #define cpu_list x86_cpu_list 2016 2017 /* MMU modes definitions */ 2018 #define MMU_KSMAP_IDX 0 2019 #define MMU_USER_IDX 1 2020 #define MMU_KNOSMAP_IDX 2 2021 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 2022 { 2023 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 2024 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 2025 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2026 } 2027 2028 static inline int cpu_mmu_index_kernel(CPUX86State *env) 2029 { 2030 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 2031 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 2032 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2033 } 2034 2035 #define CC_DST (env->cc_dst) 2036 #define CC_SRC (env->cc_src) 2037 #define CC_SRC2 (env->cc_src2) 2038 #define CC_OP (env->cc_op) 2039 2040 typedef CPUX86State CPUArchState; 2041 typedef X86CPU ArchCPU; 2042 2043 #include "exec/cpu-all.h" 2044 #include "svm.h" 2045 2046 #if !defined(CONFIG_USER_ONLY) 2047 #include "hw/i386/apic.h" 2048 #endif 2049 2050 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2051 target_ulong *cs_base, uint32_t *flags) 2052 { 2053 *cs_base = env->segs[R_CS].base; 2054 *pc = *cs_base + env->eip; 2055 *flags = env->hflags | 2056 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2057 } 2058 2059 void do_cpu_init(X86CPU *cpu); 2060 void do_cpu_sipi(X86CPU *cpu); 2061 2062 #define MCE_INJECT_BROADCAST 1 2063 #define MCE_INJECT_UNCOND_AO 2 2064 2065 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2066 uint64_t status, uint64_t mcg_status, uint64_t addr, 2067 uint64_t misc, int flags); 2068 2069 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2070 2071 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2072 { 2073 uint32_t eflags = env->eflags; 2074 if (tcg_enabled()) { 2075 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 2076 } 2077 return eflags; 2078 } 2079 2080 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2081 { 2082 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2083 } 2084 2085 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2086 { 2087 if (env->hflags & HF_SMM_MASK) { 2088 return -1; 2089 } else { 2090 return env->a20_mask; 2091 } 2092 } 2093 2094 static inline bool cpu_has_vmx(CPUX86State *env) 2095 { 2096 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2097 } 2098 2099 static inline bool cpu_has_svm(CPUX86State *env) 2100 { 2101 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2102 } 2103 2104 /* 2105 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2106 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2107 * VMX operation. This is because CR4.VMXE is one of the bits set 2108 * in MSR_IA32_VMX_CR4_FIXED1. 2109 * 2110 * There is one exception to above statement when vCPU enters SMM mode. 2111 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2112 * may also reset CR4.VMXE during execution in SMM mode. 2113 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2114 * and CR4.VMXE is restored to it's original value of being set. 2115 * 2116 * Therefore, when vCPU is not in SMM mode, we can infer whether 2117 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2118 * know for certain. 2119 */ 2120 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2121 { 2122 return cpu_has_vmx(env) && 2123 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2124 } 2125 2126 /* excp_helper.c */ 2127 int get_pg_mode(CPUX86State *env); 2128 2129 /* fpu_helper.c */ 2130 void update_fp_status(CPUX86State *env); 2131 void update_mxcsr_status(CPUX86State *env); 2132 void update_mxcsr_from_sse_status(CPUX86State *env); 2133 2134 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2135 { 2136 env->mxcsr = mxcsr; 2137 if (tcg_enabled()) { 2138 update_mxcsr_status(env); 2139 } 2140 } 2141 2142 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2143 { 2144 env->fpuc = fpuc; 2145 if (tcg_enabled()) { 2146 update_fp_status(env); 2147 } 2148 } 2149 2150 /* mem_helper.c */ 2151 void helper_lock_init(void); 2152 2153 /* svm_helper.c */ 2154 #ifdef CONFIG_USER_ONLY 2155 static inline void 2156 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2157 uint64_t param, uintptr_t retaddr) 2158 { /* no-op */ } 2159 static inline bool 2160 cpu_svm_has_intercept(CPUX86State *env, uint32_t type) 2161 { return false; } 2162 #else 2163 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2164 uint64_t param, uintptr_t retaddr); 2165 bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); 2166 #endif 2167 2168 /* apic.c */ 2169 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2170 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2171 TPRAccess access); 2172 2173 /* Special values for X86CPUVersion: */ 2174 2175 /* Resolve to latest CPU version */ 2176 #define CPU_VERSION_LATEST -1 2177 2178 /* 2179 * Resolve to version defined by current machine type. 2180 * See x86_cpu_set_default_version() 2181 */ 2182 #define CPU_VERSION_AUTO -2 2183 2184 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2185 #define CPU_VERSION_LEGACY 0 2186 2187 typedef int X86CPUVersion; 2188 2189 /* 2190 * Set default CPU model version for CPU models having 2191 * version == CPU_VERSION_AUTO. 2192 */ 2193 void x86_cpu_set_default_version(X86CPUVersion version); 2194 2195 #define APIC_DEFAULT_ADDRESS 0xfee00000 2196 #define APIC_SPACE_SIZE 0x100000 2197 2198 /* cpu-dump.c */ 2199 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2200 2201 /* cpu.c */ 2202 bool cpu_is_bsp(X86CPU *cpu); 2203 2204 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen); 2205 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); 2206 void x86_update_hflags(CPUX86State* env); 2207 2208 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2209 { 2210 return !!(cpu->hyperv_features & BIT(feat)); 2211 } 2212 2213 static inline uint64_t cr4_reserved_bits(CPUX86State *env) 2214 { 2215 uint64_t reserved_bits = CR4_RESERVED_MASK; 2216 if (!env->features[FEAT_XSAVE]) { 2217 reserved_bits |= CR4_OSXSAVE_MASK; 2218 } 2219 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) { 2220 reserved_bits |= CR4_SMEP_MASK; 2221 } 2222 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { 2223 reserved_bits |= CR4_SMAP_MASK; 2224 } 2225 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) { 2226 reserved_bits |= CR4_FSGSBASE_MASK; 2227 } 2228 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { 2229 reserved_bits |= CR4_PKE_MASK; 2230 } 2231 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) { 2232 reserved_bits |= CR4_LA57_MASK; 2233 } 2234 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { 2235 reserved_bits |= CR4_UMIP_MASK; 2236 } 2237 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { 2238 reserved_bits |= CR4_PKS_MASK; 2239 } 2240 return reserved_bits; 2241 } 2242 2243 #if defined(TARGET_X86_64) && \ 2244 defined(CONFIG_USER_ONLY) && \ 2245 defined(CONFIG_LINUX) 2246 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2247 #endif 2248 2249 #endif /* I386_CPU_H */ 2250