1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "hyperv-proto.h" 26 27 #ifdef TARGET_X86_64 28 #define TARGET_LONG_BITS 64 29 #else 30 #define TARGET_LONG_BITS 32 31 #endif 32 33 #include "exec/cpu-defs.h" 34 35 /* The x86 has a strong memory model with some store-after-load re-ordering */ 36 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 37 38 /* Maximum instruction code size */ 39 #define TARGET_MAX_INSN_SIZE 16 40 41 /* support for self modifying code even if the modified instruction is 42 close to the modifying instruction */ 43 #define TARGET_HAS_PRECISE_SMC 44 45 #ifdef TARGET_X86_64 46 #define I386_ELF_MACHINE EM_X86_64 47 #define ELF_MACHINE_UNAME "x86_64" 48 #else 49 #define I386_ELF_MACHINE EM_386 50 #define ELF_MACHINE_UNAME "i686" 51 #endif 52 53 #define CPUArchState struct CPUX86State 54 55 #ifdef CONFIG_TCG 56 #include "fpu/softfloat.h" 57 #endif 58 59 enum { 60 R_EAX = 0, 61 R_ECX = 1, 62 R_EDX = 2, 63 R_EBX = 3, 64 R_ESP = 4, 65 R_EBP = 5, 66 R_ESI = 6, 67 R_EDI = 7, 68 R_R8 = 8, 69 R_R9 = 9, 70 R_R10 = 10, 71 R_R11 = 11, 72 R_R12 = 12, 73 R_R13 = 13, 74 R_R14 = 14, 75 R_R15 = 15, 76 77 R_AL = 0, 78 R_CL = 1, 79 R_DL = 2, 80 R_BL = 3, 81 R_AH = 4, 82 R_CH = 5, 83 R_DH = 6, 84 R_BH = 7, 85 }; 86 87 typedef enum X86Seg { 88 R_ES = 0, 89 R_CS = 1, 90 R_SS = 2, 91 R_DS = 3, 92 R_FS = 4, 93 R_GS = 5, 94 R_LDTR = 6, 95 R_TR = 7, 96 } X86Seg; 97 98 /* segment descriptor fields */ 99 #define DESC_G_SHIFT 23 100 #define DESC_G_MASK (1 << DESC_G_SHIFT) 101 #define DESC_B_SHIFT 22 102 #define DESC_B_MASK (1 << DESC_B_SHIFT) 103 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 104 #define DESC_L_MASK (1 << DESC_L_SHIFT) 105 #define DESC_AVL_SHIFT 20 106 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 107 #define DESC_P_SHIFT 15 108 #define DESC_P_MASK (1 << DESC_P_SHIFT) 109 #define DESC_DPL_SHIFT 13 110 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 111 #define DESC_S_SHIFT 12 112 #define DESC_S_MASK (1 << DESC_S_SHIFT) 113 #define DESC_TYPE_SHIFT 8 114 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 115 #define DESC_A_MASK (1 << 8) 116 117 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 118 #define DESC_C_MASK (1 << 10) /* code: conforming */ 119 #define DESC_R_MASK (1 << 9) /* code: readable */ 120 121 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 122 #define DESC_W_MASK (1 << 9) /* data: writable */ 123 124 #define DESC_TSS_BUSY_MASK (1 << 9) 125 126 /* eflags masks */ 127 #define CC_C 0x0001 128 #define CC_P 0x0004 129 #define CC_A 0x0010 130 #define CC_Z 0x0040 131 #define CC_S 0x0080 132 #define CC_O 0x0800 133 134 #define TF_SHIFT 8 135 #define IOPL_SHIFT 12 136 #define VM_SHIFT 17 137 138 #define TF_MASK 0x00000100 139 #define IF_MASK 0x00000200 140 #define DF_MASK 0x00000400 141 #define IOPL_MASK 0x00003000 142 #define NT_MASK 0x00004000 143 #define RF_MASK 0x00010000 144 #define VM_MASK 0x00020000 145 #define AC_MASK 0x00040000 146 #define VIF_MASK 0x00080000 147 #define VIP_MASK 0x00100000 148 #define ID_MASK 0x00200000 149 150 /* hidden flags - used internally by qemu to represent additional cpu 151 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 152 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 153 positions to ease oring with eflags. */ 154 /* current cpl */ 155 #define HF_CPL_SHIFT 0 156 /* true if hardware interrupts must be disabled for next instruction */ 157 #define HF_INHIBIT_IRQ_SHIFT 3 158 /* 16 or 32 segments */ 159 #define HF_CS32_SHIFT 4 160 #define HF_SS32_SHIFT 5 161 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 162 #define HF_ADDSEG_SHIFT 6 163 /* copy of CR0.PE (protected mode) */ 164 #define HF_PE_SHIFT 7 165 #define HF_TF_SHIFT 8 /* must be same as eflags */ 166 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 167 #define HF_EM_SHIFT 10 168 #define HF_TS_SHIFT 11 169 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 170 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 171 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 172 #define HF_RF_SHIFT 16 /* must be same as eflags */ 173 #define HF_VM_SHIFT 17 /* must be same as eflags */ 174 #define HF_AC_SHIFT 18 /* must be same as eflags */ 175 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 176 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 177 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 178 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 179 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 180 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 181 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 182 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 183 184 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 185 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 186 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 187 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 188 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 189 #define HF_PE_MASK (1 << HF_PE_SHIFT) 190 #define HF_TF_MASK (1 << HF_TF_SHIFT) 191 #define HF_MP_MASK (1 << HF_MP_SHIFT) 192 #define HF_EM_MASK (1 << HF_EM_SHIFT) 193 #define HF_TS_MASK (1 << HF_TS_SHIFT) 194 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 195 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 196 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 197 #define HF_RF_MASK (1 << HF_RF_SHIFT) 198 #define HF_VM_MASK (1 << HF_VM_SHIFT) 199 #define HF_AC_MASK (1 << HF_AC_SHIFT) 200 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 201 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 202 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 203 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 204 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 205 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 206 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 207 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 208 209 /* hflags2 */ 210 211 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 212 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 213 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 214 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 215 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 216 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 217 218 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 219 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 220 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 221 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 222 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 223 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 224 225 #define CR0_PE_SHIFT 0 226 #define CR0_MP_SHIFT 1 227 228 #define CR0_PE_MASK (1U << 0) 229 #define CR0_MP_MASK (1U << 1) 230 #define CR0_EM_MASK (1U << 2) 231 #define CR0_TS_MASK (1U << 3) 232 #define CR0_ET_MASK (1U << 4) 233 #define CR0_NE_MASK (1U << 5) 234 #define CR0_WP_MASK (1U << 16) 235 #define CR0_AM_MASK (1U << 18) 236 #define CR0_PG_MASK (1U << 31) 237 238 #define CR4_VME_MASK (1U << 0) 239 #define CR4_PVI_MASK (1U << 1) 240 #define CR4_TSD_MASK (1U << 2) 241 #define CR4_DE_MASK (1U << 3) 242 #define CR4_PSE_MASK (1U << 4) 243 #define CR4_PAE_MASK (1U << 5) 244 #define CR4_MCE_MASK (1U << 6) 245 #define CR4_PGE_MASK (1U << 7) 246 #define CR4_PCE_MASK (1U << 8) 247 #define CR4_OSFXSR_SHIFT 9 248 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 249 #define CR4_OSXMMEXCPT_MASK (1U << 10) 250 #define CR4_LA57_MASK (1U << 12) 251 #define CR4_VMXE_MASK (1U << 13) 252 #define CR4_SMXE_MASK (1U << 14) 253 #define CR4_FSGSBASE_MASK (1U << 16) 254 #define CR4_PCIDE_MASK (1U << 17) 255 #define CR4_OSXSAVE_MASK (1U << 18) 256 #define CR4_SMEP_MASK (1U << 20) 257 #define CR4_SMAP_MASK (1U << 21) 258 #define CR4_PKE_MASK (1U << 22) 259 260 #define DR6_BD (1 << 13) 261 #define DR6_BS (1 << 14) 262 #define DR6_BT (1 << 15) 263 #define DR6_FIXED_1 0xffff0ff0 264 265 #define DR7_GD (1 << 13) 266 #define DR7_TYPE_SHIFT 16 267 #define DR7_LEN_SHIFT 18 268 #define DR7_FIXED_1 0x00000400 269 #define DR7_GLOBAL_BP_MASK 0xaa 270 #define DR7_LOCAL_BP_MASK 0x55 271 #define DR7_MAX_BP 4 272 #define DR7_TYPE_BP_INST 0x0 273 #define DR7_TYPE_DATA_WR 0x1 274 #define DR7_TYPE_IO_RW 0x2 275 #define DR7_TYPE_DATA_RW 0x3 276 277 #define PG_PRESENT_BIT 0 278 #define PG_RW_BIT 1 279 #define PG_USER_BIT 2 280 #define PG_PWT_BIT 3 281 #define PG_PCD_BIT 4 282 #define PG_ACCESSED_BIT 5 283 #define PG_DIRTY_BIT 6 284 #define PG_PSE_BIT 7 285 #define PG_GLOBAL_BIT 8 286 #define PG_PSE_PAT_BIT 12 287 #define PG_PKRU_BIT 59 288 #define PG_NX_BIT 63 289 290 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 291 #define PG_RW_MASK (1 << PG_RW_BIT) 292 #define PG_USER_MASK (1 << PG_USER_BIT) 293 #define PG_PWT_MASK (1 << PG_PWT_BIT) 294 #define PG_PCD_MASK (1 << PG_PCD_BIT) 295 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 296 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 297 #define PG_PSE_MASK (1 << PG_PSE_BIT) 298 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 299 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 300 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 301 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 302 #define PG_HI_USER_MASK 0x7ff0000000000000LL 303 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 304 #define PG_NX_MASK (1ULL << PG_NX_BIT) 305 306 #define PG_ERROR_W_BIT 1 307 308 #define PG_ERROR_P_MASK 0x01 309 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 310 #define PG_ERROR_U_MASK 0x04 311 #define PG_ERROR_RSVD_MASK 0x08 312 #define PG_ERROR_I_D_MASK 0x10 313 #define PG_ERROR_PK_MASK 0x20 314 315 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 316 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 317 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 318 319 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 320 #define MCE_BANKS_DEF 10 321 322 #define MCG_CAP_BANKS_MASK 0xff 323 324 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 325 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 326 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 327 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 328 329 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 330 331 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 332 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 333 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 334 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 335 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 336 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 337 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 338 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 339 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 340 341 /* MISC register defines */ 342 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 343 #define MCM_ADDR_LINEAR 1 /* linear address */ 344 #define MCM_ADDR_PHYS 2 /* physical address */ 345 #define MCM_ADDR_MEM 3 /* memory address */ 346 #define MCM_ADDR_GENERIC 7 /* generic */ 347 348 #define MSR_IA32_TSC 0x10 349 #define MSR_IA32_APICBASE 0x1b 350 #define MSR_IA32_APICBASE_BSP (1<<8) 351 #define MSR_IA32_APICBASE_ENABLE (1<<11) 352 #define MSR_IA32_APICBASE_EXTD (1 << 10) 353 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 354 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 355 #define MSR_TSC_ADJUST 0x0000003b 356 #define MSR_IA32_TSCDEADLINE 0x6e0 357 358 #define FEATURE_CONTROL_LOCKED (1<<0) 359 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 360 #define FEATURE_CONTROL_LMCE (1<<20) 361 362 #define MSR_P6_PERFCTR0 0xc1 363 364 #define MSR_IA32_SMBASE 0x9e 365 #define MSR_MTRRcap 0xfe 366 #define MSR_MTRRcap_VCNT 8 367 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 368 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 369 370 #define MSR_IA32_SYSENTER_CS 0x174 371 #define MSR_IA32_SYSENTER_ESP 0x175 372 #define MSR_IA32_SYSENTER_EIP 0x176 373 374 #define MSR_MCG_CAP 0x179 375 #define MSR_MCG_STATUS 0x17a 376 #define MSR_MCG_CTL 0x17b 377 #define MSR_MCG_EXT_CTL 0x4d0 378 379 #define MSR_P6_EVNTSEL0 0x186 380 381 #define MSR_IA32_PERF_STATUS 0x198 382 383 #define MSR_IA32_MISC_ENABLE 0x1a0 384 /* Indicates good rep/movs microcode on some processors: */ 385 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 386 387 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 388 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 389 390 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 391 392 #define MSR_MTRRfix64K_00000 0x250 393 #define MSR_MTRRfix16K_80000 0x258 394 #define MSR_MTRRfix16K_A0000 0x259 395 #define MSR_MTRRfix4K_C0000 0x268 396 #define MSR_MTRRfix4K_C8000 0x269 397 #define MSR_MTRRfix4K_D0000 0x26a 398 #define MSR_MTRRfix4K_D8000 0x26b 399 #define MSR_MTRRfix4K_E0000 0x26c 400 #define MSR_MTRRfix4K_E8000 0x26d 401 #define MSR_MTRRfix4K_F0000 0x26e 402 #define MSR_MTRRfix4K_F8000 0x26f 403 404 #define MSR_PAT 0x277 405 406 #define MSR_MTRRdefType 0x2ff 407 408 #define MSR_CORE_PERF_FIXED_CTR0 0x309 409 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 410 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 411 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 412 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 413 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 414 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 415 416 #define MSR_MC0_CTL 0x400 417 #define MSR_MC0_STATUS 0x401 418 #define MSR_MC0_ADDR 0x402 419 #define MSR_MC0_MISC 0x403 420 421 #define MSR_EFER 0xc0000080 422 423 #define MSR_EFER_SCE (1 << 0) 424 #define MSR_EFER_LME (1 << 8) 425 #define MSR_EFER_LMA (1 << 10) 426 #define MSR_EFER_NXE (1 << 11) 427 #define MSR_EFER_SVME (1 << 12) 428 #define MSR_EFER_FFXSR (1 << 14) 429 430 #define MSR_STAR 0xc0000081 431 #define MSR_LSTAR 0xc0000082 432 #define MSR_CSTAR 0xc0000083 433 #define MSR_FMASK 0xc0000084 434 #define MSR_FSBASE 0xc0000100 435 #define MSR_GSBASE 0xc0000101 436 #define MSR_KERNELGSBASE 0xc0000102 437 #define MSR_TSC_AUX 0xc0000103 438 439 #define MSR_VM_HSAVE_PA 0xc0010117 440 441 #define MSR_IA32_BNDCFGS 0x00000d90 442 #define MSR_IA32_XSS 0x00000da0 443 444 #define XSTATE_FP_BIT 0 445 #define XSTATE_SSE_BIT 1 446 #define XSTATE_YMM_BIT 2 447 #define XSTATE_BNDREGS_BIT 3 448 #define XSTATE_BNDCSR_BIT 4 449 #define XSTATE_OPMASK_BIT 5 450 #define XSTATE_ZMM_Hi256_BIT 6 451 #define XSTATE_Hi16_ZMM_BIT 7 452 #define XSTATE_PKRU_BIT 9 453 454 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 455 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 456 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 457 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 458 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 459 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 460 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 461 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 462 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 463 464 /* CPUID feature words */ 465 typedef enum FeatureWord { 466 FEAT_1_EDX, /* CPUID[1].EDX */ 467 FEAT_1_ECX, /* CPUID[1].ECX */ 468 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 469 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 470 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 471 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 472 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 473 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 474 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 475 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 476 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 477 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 478 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 479 FEAT_SVM, /* CPUID[8000_000A].EDX */ 480 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 481 FEAT_6_EAX, /* CPUID[6].EAX */ 482 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 483 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 484 FEATURE_WORDS, 485 } FeatureWord; 486 487 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 488 489 /* cpuid_features bits */ 490 #define CPUID_FP87 (1U << 0) 491 #define CPUID_VME (1U << 1) 492 #define CPUID_DE (1U << 2) 493 #define CPUID_PSE (1U << 3) 494 #define CPUID_TSC (1U << 4) 495 #define CPUID_MSR (1U << 5) 496 #define CPUID_PAE (1U << 6) 497 #define CPUID_MCE (1U << 7) 498 #define CPUID_CX8 (1U << 8) 499 #define CPUID_APIC (1U << 9) 500 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 501 #define CPUID_MTRR (1U << 12) 502 #define CPUID_PGE (1U << 13) 503 #define CPUID_MCA (1U << 14) 504 #define CPUID_CMOV (1U << 15) 505 #define CPUID_PAT (1U << 16) 506 #define CPUID_PSE36 (1U << 17) 507 #define CPUID_PN (1U << 18) 508 #define CPUID_CLFLUSH (1U << 19) 509 #define CPUID_DTS (1U << 21) 510 #define CPUID_ACPI (1U << 22) 511 #define CPUID_MMX (1U << 23) 512 #define CPUID_FXSR (1U << 24) 513 #define CPUID_SSE (1U << 25) 514 #define CPUID_SSE2 (1U << 26) 515 #define CPUID_SS (1U << 27) 516 #define CPUID_HT (1U << 28) 517 #define CPUID_TM (1U << 29) 518 #define CPUID_IA64 (1U << 30) 519 #define CPUID_PBE (1U << 31) 520 521 #define CPUID_EXT_SSE3 (1U << 0) 522 #define CPUID_EXT_PCLMULQDQ (1U << 1) 523 #define CPUID_EXT_DTES64 (1U << 2) 524 #define CPUID_EXT_MONITOR (1U << 3) 525 #define CPUID_EXT_DSCPL (1U << 4) 526 #define CPUID_EXT_VMX (1U << 5) 527 #define CPUID_EXT_SMX (1U << 6) 528 #define CPUID_EXT_EST (1U << 7) 529 #define CPUID_EXT_TM2 (1U << 8) 530 #define CPUID_EXT_SSSE3 (1U << 9) 531 #define CPUID_EXT_CID (1U << 10) 532 #define CPUID_EXT_FMA (1U << 12) 533 #define CPUID_EXT_CX16 (1U << 13) 534 #define CPUID_EXT_XTPR (1U << 14) 535 #define CPUID_EXT_PDCM (1U << 15) 536 #define CPUID_EXT_PCID (1U << 17) 537 #define CPUID_EXT_DCA (1U << 18) 538 #define CPUID_EXT_SSE41 (1U << 19) 539 #define CPUID_EXT_SSE42 (1U << 20) 540 #define CPUID_EXT_X2APIC (1U << 21) 541 #define CPUID_EXT_MOVBE (1U << 22) 542 #define CPUID_EXT_POPCNT (1U << 23) 543 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 544 #define CPUID_EXT_AES (1U << 25) 545 #define CPUID_EXT_XSAVE (1U << 26) 546 #define CPUID_EXT_OSXSAVE (1U << 27) 547 #define CPUID_EXT_AVX (1U << 28) 548 #define CPUID_EXT_F16C (1U << 29) 549 #define CPUID_EXT_RDRAND (1U << 30) 550 #define CPUID_EXT_HYPERVISOR (1U << 31) 551 552 #define CPUID_EXT2_FPU (1U << 0) 553 #define CPUID_EXT2_VME (1U << 1) 554 #define CPUID_EXT2_DE (1U << 2) 555 #define CPUID_EXT2_PSE (1U << 3) 556 #define CPUID_EXT2_TSC (1U << 4) 557 #define CPUID_EXT2_MSR (1U << 5) 558 #define CPUID_EXT2_PAE (1U << 6) 559 #define CPUID_EXT2_MCE (1U << 7) 560 #define CPUID_EXT2_CX8 (1U << 8) 561 #define CPUID_EXT2_APIC (1U << 9) 562 #define CPUID_EXT2_SYSCALL (1U << 11) 563 #define CPUID_EXT2_MTRR (1U << 12) 564 #define CPUID_EXT2_PGE (1U << 13) 565 #define CPUID_EXT2_MCA (1U << 14) 566 #define CPUID_EXT2_CMOV (1U << 15) 567 #define CPUID_EXT2_PAT (1U << 16) 568 #define CPUID_EXT2_PSE36 (1U << 17) 569 #define CPUID_EXT2_MP (1U << 19) 570 #define CPUID_EXT2_NX (1U << 20) 571 #define CPUID_EXT2_MMXEXT (1U << 22) 572 #define CPUID_EXT2_MMX (1U << 23) 573 #define CPUID_EXT2_FXSR (1U << 24) 574 #define CPUID_EXT2_FFXSR (1U << 25) 575 #define CPUID_EXT2_PDPE1GB (1U << 26) 576 #define CPUID_EXT2_RDTSCP (1U << 27) 577 #define CPUID_EXT2_LM (1U << 29) 578 #define CPUID_EXT2_3DNOWEXT (1U << 30) 579 #define CPUID_EXT2_3DNOW (1U << 31) 580 581 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 582 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 583 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 584 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 585 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 586 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 587 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 588 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 589 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 590 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 591 592 #define CPUID_EXT3_LAHF_LM (1U << 0) 593 #define CPUID_EXT3_CMP_LEG (1U << 1) 594 #define CPUID_EXT3_SVM (1U << 2) 595 #define CPUID_EXT3_EXTAPIC (1U << 3) 596 #define CPUID_EXT3_CR8LEG (1U << 4) 597 #define CPUID_EXT3_ABM (1U << 5) 598 #define CPUID_EXT3_SSE4A (1U << 6) 599 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 600 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 601 #define CPUID_EXT3_OSVW (1U << 9) 602 #define CPUID_EXT3_IBS (1U << 10) 603 #define CPUID_EXT3_XOP (1U << 11) 604 #define CPUID_EXT3_SKINIT (1U << 12) 605 #define CPUID_EXT3_WDT (1U << 13) 606 #define CPUID_EXT3_LWP (1U << 15) 607 #define CPUID_EXT3_FMA4 (1U << 16) 608 #define CPUID_EXT3_TCE (1U << 17) 609 #define CPUID_EXT3_NODEID (1U << 19) 610 #define CPUID_EXT3_TBM (1U << 21) 611 #define CPUID_EXT3_TOPOEXT (1U << 22) 612 #define CPUID_EXT3_PERFCORE (1U << 23) 613 #define CPUID_EXT3_PERFNB (1U << 24) 614 615 #define CPUID_SVM_NPT (1U << 0) 616 #define CPUID_SVM_LBRV (1U << 1) 617 #define CPUID_SVM_SVMLOCK (1U << 2) 618 #define CPUID_SVM_NRIPSAVE (1U << 3) 619 #define CPUID_SVM_TSCSCALE (1U << 4) 620 #define CPUID_SVM_VMCBCLEAN (1U << 5) 621 #define CPUID_SVM_FLUSHASID (1U << 6) 622 #define CPUID_SVM_DECODEASSIST (1U << 7) 623 #define CPUID_SVM_PAUSEFILTER (1U << 10) 624 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 625 626 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 627 #define CPUID_7_0_EBX_BMI1 (1U << 3) 628 #define CPUID_7_0_EBX_HLE (1U << 4) 629 #define CPUID_7_0_EBX_AVX2 (1U << 5) 630 #define CPUID_7_0_EBX_SMEP (1U << 7) 631 #define CPUID_7_0_EBX_BMI2 (1U << 8) 632 #define CPUID_7_0_EBX_ERMS (1U << 9) 633 #define CPUID_7_0_EBX_INVPCID (1U << 10) 634 #define CPUID_7_0_EBX_RTM (1U << 11) 635 #define CPUID_7_0_EBX_MPX (1U << 14) 636 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 637 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 638 #define CPUID_7_0_EBX_RDSEED (1U << 18) 639 #define CPUID_7_0_EBX_ADX (1U << 19) 640 #define CPUID_7_0_EBX_SMAP (1U << 20) 641 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 642 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 643 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 644 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 645 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 646 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 647 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 648 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 649 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 650 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 651 652 #define CPUID_7_0_ECX_AVX512BMI (1U << 1) 653 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 654 #define CPUID_7_0_ECX_UMIP (1U << 2) 655 #define CPUID_7_0_ECX_PKU (1U << 3) 656 #define CPUID_7_0_ECX_OSPKE (1U << 4) 657 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ 658 #define CPUID_7_0_ECX_GFNI (1U << 8) 659 #define CPUID_7_0_ECX_VAES (1U << 9) 660 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 661 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 662 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 663 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 664 #define CPUID_7_0_ECX_LA57 (1U << 16) 665 #define CPUID_7_0_ECX_RDPID (1U << 22) 666 667 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 668 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 669 670 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 671 #define CPUID_XSAVE_XSAVEC (1U << 1) 672 #define CPUID_XSAVE_XGETBV1 (1U << 2) 673 #define CPUID_XSAVE_XSAVES (1U << 3) 674 675 #define CPUID_6_EAX_ARAT (1U << 2) 676 677 /* CPUID[0x80000007].EDX flags: */ 678 #define CPUID_APM_INVTSC (1U << 8) 679 680 #define CPUID_VENDOR_SZ 12 681 682 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 683 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 684 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 685 #define CPUID_VENDOR_INTEL "GenuineIntel" 686 687 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 688 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 689 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 690 #define CPUID_VENDOR_AMD "AuthenticAMD" 691 692 #define CPUID_VENDOR_VIA "CentaurHauls" 693 694 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 695 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 696 697 /* CPUID[0xB].ECX level types */ 698 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 699 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 700 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 701 702 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 703 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 704 #endif 705 706 #define EXCP00_DIVZ 0 707 #define EXCP01_DB 1 708 #define EXCP02_NMI 2 709 #define EXCP03_INT3 3 710 #define EXCP04_INTO 4 711 #define EXCP05_BOUND 5 712 #define EXCP06_ILLOP 6 713 #define EXCP07_PREX 7 714 #define EXCP08_DBLE 8 715 #define EXCP09_XERR 9 716 #define EXCP0A_TSS 10 717 #define EXCP0B_NOSEG 11 718 #define EXCP0C_STACK 12 719 #define EXCP0D_GPF 13 720 #define EXCP0E_PAGE 14 721 #define EXCP10_COPR 16 722 #define EXCP11_ALGN 17 723 #define EXCP12_MCHK 18 724 725 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 726 for syscall instruction */ 727 #define EXCP_VMEXIT 0x100 728 729 /* i386-specific interrupt pending bits. */ 730 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 731 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 732 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 733 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 734 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 735 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 736 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 737 738 /* Use a clearer name for this. */ 739 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 740 741 /* Instead of computing the condition codes after each x86 instruction, 742 * QEMU just stores one operand (called CC_SRC), the result 743 * (called CC_DST) and the type of operation (called CC_OP). When the 744 * condition codes are needed, the condition codes can be calculated 745 * using this information. Condition codes are not generated if they 746 * are only needed for conditional branches. 747 */ 748 typedef enum { 749 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 750 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 751 752 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 753 CC_OP_MULW, 754 CC_OP_MULL, 755 CC_OP_MULQ, 756 757 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 758 CC_OP_ADDW, 759 CC_OP_ADDL, 760 CC_OP_ADDQ, 761 762 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 763 CC_OP_ADCW, 764 CC_OP_ADCL, 765 CC_OP_ADCQ, 766 767 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 768 CC_OP_SUBW, 769 CC_OP_SUBL, 770 CC_OP_SUBQ, 771 772 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 773 CC_OP_SBBW, 774 CC_OP_SBBL, 775 CC_OP_SBBQ, 776 777 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 778 CC_OP_LOGICW, 779 CC_OP_LOGICL, 780 CC_OP_LOGICQ, 781 782 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 783 CC_OP_INCW, 784 CC_OP_INCL, 785 CC_OP_INCQ, 786 787 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 788 CC_OP_DECW, 789 CC_OP_DECL, 790 CC_OP_DECQ, 791 792 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 793 CC_OP_SHLW, 794 CC_OP_SHLL, 795 CC_OP_SHLQ, 796 797 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 798 CC_OP_SARW, 799 CC_OP_SARL, 800 CC_OP_SARQ, 801 802 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 803 CC_OP_BMILGW, 804 CC_OP_BMILGL, 805 CC_OP_BMILGQ, 806 807 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 808 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 809 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 810 811 CC_OP_CLR, /* Z set, all other flags clear. */ 812 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 813 814 CC_OP_NB, 815 } CCOp; 816 817 typedef struct SegmentCache { 818 uint32_t selector; 819 target_ulong base; 820 uint32_t limit; 821 uint32_t flags; 822 } SegmentCache; 823 824 #define MMREG_UNION(n, bits) \ 825 union n { \ 826 uint8_t _b_##n[(bits)/8]; \ 827 uint16_t _w_##n[(bits)/16]; \ 828 uint32_t _l_##n[(bits)/32]; \ 829 uint64_t _q_##n[(bits)/64]; \ 830 float32 _s_##n[(bits)/32]; \ 831 float64 _d_##n[(bits)/64]; \ 832 } 833 834 typedef union { 835 uint8_t _b[16]; 836 uint16_t _w[8]; 837 uint32_t _l[4]; 838 uint64_t _q[2]; 839 } XMMReg; 840 841 typedef union { 842 uint8_t _b[32]; 843 uint16_t _w[16]; 844 uint32_t _l[8]; 845 uint64_t _q[4]; 846 } YMMReg; 847 848 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 849 typedef MMREG_UNION(MMXReg, 64) MMXReg; 850 851 typedef struct BNDReg { 852 uint64_t lb; 853 uint64_t ub; 854 } BNDReg; 855 856 typedef struct BNDCSReg { 857 uint64_t cfgu; 858 uint64_t sts; 859 } BNDCSReg; 860 861 #define BNDCFG_ENABLE 1ULL 862 #define BNDCFG_BNDPRESERVE 2ULL 863 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 864 865 #ifdef HOST_WORDS_BIGENDIAN 866 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 867 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 868 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 869 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 870 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 871 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 872 873 #define MMX_B(n) _b_MMXReg[7 - (n)] 874 #define MMX_W(n) _w_MMXReg[3 - (n)] 875 #define MMX_L(n) _l_MMXReg[1 - (n)] 876 #define MMX_S(n) _s_MMXReg[1 - (n)] 877 #else 878 #define ZMM_B(n) _b_ZMMReg[n] 879 #define ZMM_W(n) _w_ZMMReg[n] 880 #define ZMM_L(n) _l_ZMMReg[n] 881 #define ZMM_S(n) _s_ZMMReg[n] 882 #define ZMM_Q(n) _q_ZMMReg[n] 883 #define ZMM_D(n) _d_ZMMReg[n] 884 885 #define MMX_B(n) _b_MMXReg[n] 886 #define MMX_W(n) _w_MMXReg[n] 887 #define MMX_L(n) _l_MMXReg[n] 888 #define MMX_S(n) _s_MMXReg[n] 889 #endif 890 #define MMX_Q(n) _q_MMXReg[n] 891 892 typedef union { 893 floatx80 d __attribute__((aligned(16))); 894 MMXReg mmx; 895 } FPReg; 896 897 typedef struct { 898 uint64_t base; 899 uint64_t mask; 900 } MTRRVar; 901 902 #define CPU_NB_REGS64 16 903 #define CPU_NB_REGS32 8 904 905 #ifdef TARGET_X86_64 906 #define CPU_NB_REGS CPU_NB_REGS64 907 #else 908 #define CPU_NB_REGS CPU_NB_REGS32 909 #endif 910 911 #define MAX_FIXED_COUNTERS 3 912 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 913 914 #define NB_MMU_MODES 3 915 #define TARGET_INSN_START_EXTRA_WORDS 1 916 917 #define NB_OPMASK_REGS 8 918 919 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 920 * that APIC ID hasn't been set yet 921 */ 922 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 923 924 typedef union X86LegacyXSaveArea { 925 struct { 926 uint16_t fcw; 927 uint16_t fsw; 928 uint8_t ftw; 929 uint8_t reserved; 930 uint16_t fpop; 931 uint64_t fpip; 932 uint64_t fpdp; 933 uint32_t mxcsr; 934 uint32_t mxcsr_mask; 935 FPReg fpregs[8]; 936 uint8_t xmm_regs[16][16]; 937 }; 938 uint8_t data[512]; 939 } X86LegacyXSaveArea; 940 941 typedef struct X86XSaveHeader { 942 uint64_t xstate_bv; 943 uint64_t xcomp_bv; 944 uint64_t reserve0; 945 uint8_t reserved[40]; 946 } X86XSaveHeader; 947 948 /* Ext. save area 2: AVX State */ 949 typedef struct XSaveAVX { 950 uint8_t ymmh[16][16]; 951 } XSaveAVX; 952 953 /* Ext. save area 3: BNDREG */ 954 typedef struct XSaveBNDREG { 955 BNDReg bnd_regs[4]; 956 } XSaveBNDREG; 957 958 /* Ext. save area 4: BNDCSR */ 959 typedef union XSaveBNDCSR { 960 BNDCSReg bndcsr; 961 uint8_t data[64]; 962 } XSaveBNDCSR; 963 964 /* Ext. save area 5: Opmask */ 965 typedef struct XSaveOpmask { 966 uint64_t opmask_regs[NB_OPMASK_REGS]; 967 } XSaveOpmask; 968 969 /* Ext. save area 6: ZMM_Hi256 */ 970 typedef struct XSaveZMM_Hi256 { 971 uint8_t zmm_hi256[16][32]; 972 } XSaveZMM_Hi256; 973 974 /* Ext. save area 7: Hi16_ZMM */ 975 typedef struct XSaveHi16_ZMM { 976 uint8_t hi16_zmm[16][64]; 977 } XSaveHi16_ZMM; 978 979 /* Ext. save area 9: PKRU state */ 980 typedef struct XSavePKRU { 981 uint32_t pkru; 982 uint32_t padding; 983 } XSavePKRU; 984 985 typedef struct X86XSaveArea { 986 X86LegacyXSaveArea legacy; 987 X86XSaveHeader header; 988 989 /* Extended save areas: */ 990 991 /* AVX State: */ 992 XSaveAVX avx_state; 993 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 994 /* MPX State: */ 995 XSaveBNDREG bndreg_state; 996 XSaveBNDCSR bndcsr_state; 997 /* AVX-512 State: */ 998 XSaveOpmask opmask_state; 999 XSaveZMM_Hi256 zmm_hi256_state; 1000 XSaveHi16_ZMM hi16_zmm_state; 1001 /* PKRU State: */ 1002 XSavePKRU pkru_state; 1003 } X86XSaveArea; 1004 1005 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1006 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1007 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1008 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1009 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1010 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1011 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1012 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1013 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1014 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1015 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1016 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1017 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1018 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1019 1020 typedef enum TPRAccess { 1021 TPR_ACCESS_READ, 1022 TPR_ACCESS_WRITE, 1023 } TPRAccess; 1024 1025 typedef struct CPUX86State { 1026 /* standard registers */ 1027 target_ulong regs[CPU_NB_REGS]; 1028 target_ulong eip; 1029 target_ulong eflags; /* eflags register. During CPU emulation, CC 1030 flags and DF are set to zero because they are 1031 stored elsewhere */ 1032 1033 /* emulator internal eflags handling */ 1034 target_ulong cc_dst; 1035 target_ulong cc_src; 1036 target_ulong cc_src2; 1037 uint32_t cc_op; 1038 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1039 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1040 are known at translation time. */ 1041 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1042 1043 /* segments */ 1044 SegmentCache segs[6]; /* selector values */ 1045 SegmentCache ldt; 1046 SegmentCache tr; 1047 SegmentCache gdt; /* only base and limit are used */ 1048 SegmentCache idt; /* only base and limit are used */ 1049 1050 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1051 int32_t a20_mask; 1052 1053 BNDReg bnd_regs[4]; 1054 BNDCSReg bndcs_regs; 1055 uint64_t msr_bndcfgs; 1056 uint64_t efer; 1057 1058 /* Beginning of state preserved by INIT (dummy marker). */ 1059 struct {} start_init_save; 1060 1061 /* FPU state */ 1062 unsigned int fpstt; /* top of stack index */ 1063 uint16_t fpus; 1064 uint16_t fpuc; 1065 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1066 FPReg fpregs[8]; 1067 /* KVM-only so far */ 1068 uint16_t fpop; 1069 uint64_t fpip; 1070 uint64_t fpdp; 1071 1072 /* emulator internal variables */ 1073 float_status fp_status; 1074 floatx80 ft0; 1075 1076 float_status mmx_status; /* for 3DNow! float ops */ 1077 float_status sse_status; 1078 uint32_t mxcsr; 1079 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1080 ZMMReg xmm_t0; 1081 MMXReg mmx_t0; 1082 1083 XMMReg ymmh_regs[CPU_NB_REGS]; 1084 1085 uint64_t opmask_regs[NB_OPMASK_REGS]; 1086 YMMReg zmmh_regs[CPU_NB_REGS]; 1087 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1088 1089 /* sysenter registers */ 1090 uint32_t sysenter_cs; 1091 target_ulong sysenter_esp; 1092 target_ulong sysenter_eip; 1093 uint64_t star; 1094 1095 uint64_t vm_hsave; 1096 1097 #ifdef TARGET_X86_64 1098 target_ulong lstar; 1099 target_ulong cstar; 1100 target_ulong fmask; 1101 target_ulong kernelgsbase; 1102 #endif 1103 1104 uint64_t tsc; 1105 uint64_t tsc_adjust; 1106 uint64_t tsc_deadline; 1107 uint64_t tsc_aux; 1108 1109 uint64_t xcr0; 1110 1111 uint64_t mcg_status; 1112 uint64_t msr_ia32_misc_enable; 1113 uint64_t msr_ia32_feature_control; 1114 1115 uint64_t msr_fixed_ctr_ctrl; 1116 uint64_t msr_global_ctrl; 1117 uint64_t msr_global_status; 1118 uint64_t msr_global_ovf_ctrl; 1119 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1120 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1121 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1122 1123 uint64_t pat; 1124 uint32_t smbase; 1125 1126 uint32_t pkru; 1127 1128 /* End of state preserved by INIT (dummy marker). */ 1129 struct {} end_init_save; 1130 1131 uint64_t system_time_msr; 1132 uint64_t wall_clock_msr; 1133 uint64_t steal_time_msr; 1134 uint64_t async_pf_en_msr; 1135 uint64_t pv_eoi_en_msr; 1136 1137 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1138 uint64_t msr_hv_hypercall; 1139 uint64_t msr_hv_guest_os_id; 1140 uint64_t msr_hv_tsc; 1141 1142 /* Per-VCPU HV MSRs */ 1143 uint64_t msr_hv_vapic; 1144 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1145 uint64_t msr_hv_runtime; 1146 uint64_t msr_hv_synic_control; 1147 uint64_t msr_hv_synic_evt_page; 1148 uint64_t msr_hv_synic_msg_page; 1149 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1150 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1151 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1152 1153 /* exception/interrupt handling */ 1154 int error_code; 1155 int exception_is_int; 1156 target_ulong exception_next_eip; 1157 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1158 union { 1159 struct CPUBreakpoint *cpu_breakpoint[4]; 1160 struct CPUWatchpoint *cpu_watchpoint[4]; 1161 }; /* break/watchpoints for dr[0..3] */ 1162 int old_exception; /* exception in flight */ 1163 1164 uint64_t vm_vmcb; 1165 uint64_t tsc_offset; 1166 uint64_t intercept; 1167 uint16_t intercept_cr_read; 1168 uint16_t intercept_cr_write; 1169 uint16_t intercept_dr_read; 1170 uint16_t intercept_dr_write; 1171 uint32_t intercept_exceptions; 1172 uint8_t v_tpr; 1173 1174 /* KVM states, automatically cleared on reset */ 1175 uint8_t nmi_injected; 1176 uint8_t nmi_pending; 1177 1178 /* Fields up to this point are cleared by a CPU reset */ 1179 struct {} end_reset_fields; 1180 1181 CPU_COMMON 1182 1183 /* Fields after CPU_COMMON are preserved across CPU reset. */ 1184 1185 /* processor features (e.g. for CPUID insn) */ 1186 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1187 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1188 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1189 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1190 /* Actual level/xlevel/xlevel2 value: */ 1191 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1192 uint32_t cpuid_vendor1; 1193 uint32_t cpuid_vendor2; 1194 uint32_t cpuid_vendor3; 1195 uint32_t cpuid_version; 1196 FeatureWordArray features; 1197 /* Features that were explicitly enabled/disabled */ 1198 FeatureWordArray user_features; 1199 uint32_t cpuid_model[12]; 1200 1201 /* MTRRs */ 1202 uint64_t mtrr_fixed[11]; 1203 uint64_t mtrr_deftype; 1204 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1205 1206 /* For KVM */ 1207 uint32_t mp_state; 1208 int32_t exception_injected; 1209 int32_t interrupt_injected; 1210 uint8_t soft_interrupt; 1211 uint8_t has_error_code; 1212 uint32_t ins_len; 1213 uint32_t sipi_vector; 1214 bool tsc_valid; 1215 int64_t tsc_khz; 1216 int64_t user_tsc_khz; /* for sanity check only */ 1217 void *kvm_xsave_buf; 1218 #if defined(CONFIG_HVF) 1219 HVFX86EmulatorState *hvf_emul; 1220 #endif 1221 1222 uint64_t mcg_cap; 1223 uint64_t mcg_ctl; 1224 uint64_t mcg_ext_ctl; 1225 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1226 uint64_t xstate_bv; 1227 1228 /* vmstate */ 1229 uint16_t fpus_vmstate; 1230 uint16_t fptag_vmstate; 1231 uint16_t fpregs_format_vmstate; 1232 1233 uint64_t xss; 1234 1235 TPRAccess tpr_access_type; 1236 } CPUX86State; 1237 1238 struct kvm_msrs; 1239 1240 /** 1241 * X86CPU: 1242 * @env: #CPUX86State 1243 * @migratable: If set, only migratable flags will be accepted when "enforce" 1244 * mode is used, and only migratable flags will be included in the "host" 1245 * CPU model. 1246 * 1247 * An x86 CPU. 1248 */ 1249 struct X86CPU { 1250 /*< private >*/ 1251 CPUState parent_obj; 1252 /*< public >*/ 1253 1254 CPUX86State env; 1255 1256 bool hyperv_vapic; 1257 bool hyperv_relaxed_timing; 1258 int hyperv_spinlock_attempts; 1259 char *hyperv_vendor_id; 1260 bool hyperv_time; 1261 bool hyperv_crash; 1262 bool hyperv_reset; 1263 bool hyperv_vpindex; 1264 bool hyperv_runtime; 1265 bool hyperv_synic; 1266 bool hyperv_stimer; 1267 bool check_cpuid; 1268 bool enforce_cpuid; 1269 bool expose_kvm; 1270 bool expose_tcg; 1271 bool migratable; 1272 bool max_features; /* Enable all supported features automatically */ 1273 uint32_t apic_id; 1274 1275 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1276 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1277 bool vmware_cpuid_freq; 1278 1279 /* if true the CPUID code directly forward host cache leaves to the guest */ 1280 bool cache_info_passthrough; 1281 1282 /* Features that were filtered out because of missing host capabilities */ 1283 uint32_t filtered_features[FEATURE_WORDS]; 1284 1285 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1286 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1287 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1288 * capabilities) directly to the guest. 1289 */ 1290 bool enable_pmu; 1291 1292 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1293 * disabled by default to avoid breaking migration between QEMU with 1294 * different LMCE configurations. 1295 */ 1296 bool enable_lmce; 1297 1298 /* Compatibility bits for old machine types. 1299 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1300 * socket share an virtual l3 cache. 1301 */ 1302 bool enable_l3_cache; 1303 1304 /* Compatibility bits for old machine types: */ 1305 bool enable_cpuid_0xb; 1306 1307 /* Enable auto level-increase for all CPUID leaves */ 1308 bool full_cpuid_auto_level; 1309 1310 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1311 bool fill_mtrr_mask; 1312 1313 /* if true override the phys_bits value with a value read from the host */ 1314 bool host_phys_bits; 1315 1316 /* Stop SMI delivery for migration compatibility with old machines */ 1317 bool kvm_no_smi_migration; 1318 1319 /* Number of physical address bits supported */ 1320 uint32_t phys_bits; 1321 1322 /* in order to simplify APIC support, we leave this pointer to the 1323 user */ 1324 struct DeviceState *apic_state; 1325 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1326 Notifier machine_done; 1327 1328 struct kvm_msrs *kvm_msr_buf; 1329 1330 int32_t node_id; /* NUMA node this CPU belongs to */ 1331 int32_t socket_id; 1332 int32_t core_id; 1333 int32_t thread_id; 1334 1335 int32_t hv_max_vps; 1336 }; 1337 1338 static inline X86CPU *x86_env_get_cpu(CPUX86State *env) 1339 { 1340 return container_of(env, X86CPU, env); 1341 } 1342 1343 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) 1344 1345 #define ENV_OFFSET offsetof(X86CPU, env) 1346 1347 #ifndef CONFIG_USER_ONLY 1348 extern struct VMStateDescription vmstate_x86_cpu; 1349 #endif 1350 1351 /** 1352 * x86_cpu_do_interrupt: 1353 * @cpu: vCPU the interrupt is to be handled by. 1354 */ 1355 void x86_cpu_do_interrupt(CPUState *cpu); 1356 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1357 1358 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1359 int cpuid, void *opaque); 1360 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1361 int cpuid, void *opaque); 1362 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1363 void *opaque); 1364 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1365 void *opaque); 1366 1367 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1368 Error **errp); 1369 1370 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 1371 int flags); 1372 1373 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1374 1375 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1376 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1377 1378 void x86_cpu_exec_enter(CPUState *cpu); 1379 void x86_cpu_exec_exit(CPUState *cpu); 1380 1381 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1382 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1383 1384 int cpu_get_pic_interrupt(CPUX86State *s); 1385 /* MSDOS compatibility mode FPU exception support */ 1386 void cpu_set_ferr(CPUX86State *s); 1387 1388 /* this function must always be used to load data in the segment 1389 cache: it synchronizes the hflags with the segment cache values */ 1390 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1391 int seg_reg, unsigned int selector, 1392 target_ulong base, 1393 unsigned int limit, 1394 unsigned int flags) 1395 { 1396 SegmentCache *sc; 1397 unsigned int new_hflags; 1398 1399 sc = &env->segs[seg_reg]; 1400 sc->selector = selector; 1401 sc->base = base; 1402 sc->limit = limit; 1403 sc->flags = flags; 1404 1405 /* update the hidden flags */ 1406 { 1407 if (seg_reg == R_CS) { 1408 #ifdef TARGET_X86_64 1409 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1410 /* long mode */ 1411 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1412 env->hflags &= ~(HF_ADDSEG_MASK); 1413 } else 1414 #endif 1415 { 1416 /* legacy / compatibility case */ 1417 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1418 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1419 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1420 new_hflags; 1421 } 1422 } 1423 if (seg_reg == R_SS) { 1424 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1425 #if HF_CPL_MASK != 3 1426 #error HF_CPL_MASK is hardcoded 1427 #endif 1428 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1429 } 1430 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1431 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1432 if (env->hflags & HF_CS64_MASK) { 1433 /* zero base assumed for DS, ES and SS in long mode */ 1434 } else if (!(env->cr[0] & CR0_PE_MASK) || 1435 (env->eflags & VM_MASK) || 1436 !(env->hflags & HF_CS32_MASK)) { 1437 /* XXX: try to avoid this test. The problem comes from the 1438 fact that is real mode or vm86 mode we only modify the 1439 'base' and 'selector' fields of the segment cache to go 1440 faster. A solution may be to force addseg to one in 1441 translate-i386.c. */ 1442 new_hflags |= HF_ADDSEG_MASK; 1443 } else { 1444 new_hflags |= ((env->segs[R_DS].base | 1445 env->segs[R_ES].base | 1446 env->segs[R_SS].base) != 0) << 1447 HF_ADDSEG_SHIFT; 1448 } 1449 env->hflags = (env->hflags & 1450 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1451 } 1452 } 1453 1454 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1455 uint8_t sipi_vector) 1456 { 1457 CPUState *cs = CPU(cpu); 1458 CPUX86State *env = &cpu->env; 1459 1460 env->eip = 0; 1461 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1462 sipi_vector << 12, 1463 env->segs[R_CS].limit, 1464 env->segs[R_CS].flags); 1465 cs->halted = 0; 1466 } 1467 1468 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1469 target_ulong *base, unsigned int *limit, 1470 unsigned int *flags); 1471 1472 /* op_helper.c */ 1473 /* used for debug or cpu save/restore */ 1474 1475 /* cpu-exec.c */ 1476 /* the following helpers are only usable in user mode simulation as 1477 they can trigger unexpected exceptions */ 1478 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1479 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1480 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1481 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1482 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1483 1484 /* you can call this signal handler from your SIGBUS and SIGSEGV 1485 signal handlers to inform the virtual CPU of exceptions. non zero 1486 is returned if the signal was handled by the virtual CPU. */ 1487 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1488 void *puc); 1489 1490 /* cpu.c */ 1491 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1492 uint32_t *eax, uint32_t *ebx, 1493 uint32_t *ecx, uint32_t *edx); 1494 void cpu_clear_apic_feature(CPUX86State *env); 1495 void host_cpuid(uint32_t function, uint32_t count, 1496 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1497 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1498 1499 /* helper.c */ 1500 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, 1501 int is_write, int mmu_idx); 1502 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1503 1504 #ifndef CONFIG_USER_ONLY 1505 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1506 { 1507 return !!attrs.secure; 1508 } 1509 1510 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1511 { 1512 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1513 } 1514 1515 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1516 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1517 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1518 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1519 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1520 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1521 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1522 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1523 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1524 #endif 1525 1526 void breakpoint_handler(CPUState *cs); 1527 1528 /* will be suppressed */ 1529 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1530 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1531 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1532 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1533 1534 /* hw/pc.c */ 1535 uint64_t cpu_get_tsc(CPUX86State *env); 1536 1537 #define TARGET_PAGE_BITS 12 1538 1539 #ifdef TARGET_X86_64 1540 #define TARGET_PHYS_ADDR_SPACE_BITS 52 1541 /* ??? This is really 48 bits, sign-extended, but the only thing 1542 accessible to userland with bit 48 set is the VSYSCALL, and that 1543 is handled via other mechanisms. */ 1544 #define TARGET_VIRT_ADDR_SPACE_BITS 47 1545 #else 1546 #define TARGET_PHYS_ADDR_SPACE_BITS 36 1547 #define TARGET_VIRT_ADDR_SPACE_BITS 32 1548 #endif 1549 1550 /* XXX: This value should match the one returned by CPUID 1551 * and in exec.c */ 1552 # if defined(TARGET_X86_64) 1553 # define TCG_PHYS_ADDR_BITS 40 1554 # else 1555 # define TCG_PHYS_ADDR_BITS 36 1556 # endif 1557 1558 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1559 1560 #define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model) 1561 1562 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1563 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1564 1565 #ifdef TARGET_X86_64 1566 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1567 #else 1568 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1569 #endif 1570 1571 #define cpu_signal_handler cpu_x86_signal_handler 1572 #define cpu_list x86_cpu_list 1573 1574 /* MMU modes definitions */ 1575 #define MMU_MODE0_SUFFIX _ksmap 1576 #define MMU_MODE1_SUFFIX _user 1577 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1578 #define MMU_KSMAP_IDX 0 1579 #define MMU_USER_IDX 1 1580 #define MMU_KNOSMAP_IDX 2 1581 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1582 { 1583 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1584 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1585 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1586 } 1587 1588 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1589 { 1590 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1591 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1592 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1593 } 1594 1595 #define CC_DST (env->cc_dst) 1596 #define CC_SRC (env->cc_src) 1597 #define CC_SRC2 (env->cc_src2) 1598 #define CC_OP (env->cc_op) 1599 1600 /* n must be a constant to be efficient */ 1601 static inline target_long lshift(target_long x, int n) 1602 { 1603 if (n >= 0) { 1604 return x << n; 1605 } else { 1606 return x >> (-n); 1607 } 1608 } 1609 1610 /* float macros */ 1611 #define FT0 (env->ft0) 1612 #define ST0 (env->fpregs[env->fpstt].d) 1613 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1614 #define ST1 ST(1) 1615 1616 /* translate.c */ 1617 void tcg_x86_init(void); 1618 1619 #include "exec/cpu-all.h" 1620 #include "svm.h" 1621 1622 #if !defined(CONFIG_USER_ONLY) 1623 #include "hw/i386/apic.h" 1624 #endif 1625 1626 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1627 target_ulong *cs_base, uint32_t *flags) 1628 { 1629 *cs_base = env->segs[R_CS].base; 1630 *pc = *cs_base + env->eip; 1631 *flags = env->hflags | 1632 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1633 } 1634 1635 void do_cpu_init(X86CPU *cpu); 1636 void do_cpu_sipi(X86CPU *cpu); 1637 1638 #define MCE_INJECT_BROADCAST 1 1639 #define MCE_INJECT_UNCOND_AO 2 1640 1641 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1642 uint64_t status, uint64_t mcg_status, uint64_t addr, 1643 uint64_t misc, int flags); 1644 1645 /* excp_helper.c */ 1646 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1647 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1648 uintptr_t retaddr); 1649 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1650 int error_code); 1651 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1652 int error_code, uintptr_t retaddr); 1653 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1654 int error_code, int next_eip_addend); 1655 1656 /* cc_helper.c */ 1657 extern const uint8_t parity_table[256]; 1658 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1659 1660 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1661 { 1662 uint32_t eflags = env->eflags; 1663 if (tcg_enabled()) { 1664 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 1665 } 1666 return eflags; 1667 } 1668 1669 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1670 * after generating a call to a helper that uses this. 1671 */ 1672 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1673 int update_mask) 1674 { 1675 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1676 CC_OP = CC_OP_EFLAGS; 1677 env->df = 1 - (2 * ((eflags >> 10) & 1)); 1678 env->eflags = (env->eflags & ~update_mask) | 1679 (eflags & update_mask) | 0x2; 1680 } 1681 1682 /* load efer and update the corresponding hflags. XXX: do consistency 1683 checks with cpuid bits? */ 1684 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1685 { 1686 env->efer = val; 1687 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1688 if (env->efer & MSR_EFER_LMA) { 1689 env->hflags |= HF_LMA_MASK; 1690 } 1691 if (env->efer & MSR_EFER_SVME) { 1692 env->hflags |= HF_SVME_MASK; 1693 } 1694 } 1695 1696 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 1697 { 1698 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 1699 } 1700 1701 static inline int32_t x86_get_a20_mask(CPUX86State *env) 1702 { 1703 if (env->hflags & HF_SMM_MASK) { 1704 return -1; 1705 } else { 1706 return env->a20_mask; 1707 } 1708 } 1709 1710 /* fpu_helper.c */ 1711 void update_fp_status(CPUX86State *env); 1712 void update_mxcsr_status(CPUX86State *env); 1713 1714 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 1715 { 1716 env->mxcsr = mxcsr; 1717 if (tcg_enabled()) { 1718 update_mxcsr_status(env); 1719 } 1720 } 1721 1722 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 1723 { 1724 env->fpuc = fpuc; 1725 if (tcg_enabled()) { 1726 update_fp_status(env); 1727 } 1728 } 1729 1730 /* mem_helper.c */ 1731 void helper_lock_init(void); 1732 1733 /* svm_helper.c */ 1734 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 1735 uint64_t param, uintptr_t retaddr); 1736 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, 1737 uintptr_t retaddr); 1738 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 1739 1740 /* seg_helper.c */ 1741 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 1742 1743 /* smm_helper.c */ 1744 void do_smm_enter(X86CPU *cpu); 1745 1746 /* apic.c */ 1747 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 1748 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 1749 TPRAccess access); 1750 1751 1752 /* Change the value of a KVM-specific default 1753 * 1754 * If value is NULL, no default will be set and the original 1755 * value from the CPU model table will be kept. 1756 * 1757 * It is valid to call this function only for properties that 1758 * are already present in the kvm_default_props table. 1759 */ 1760 void x86_cpu_change_kvm_default(const char *prop, const char *value); 1761 1762 /* mpx_helper.c */ 1763 void cpu_sync_bndcs_hflags(CPUX86State *env); 1764 1765 /* Return name of 32-bit register, from a R_* constant */ 1766 const char *get_register_name_32(unsigned int reg); 1767 1768 void enable_compat_apic_id_mode(void); 1769 1770 #define APIC_DEFAULT_ADDRESS 0xfee00000 1771 #define APIC_SPACE_SIZE 0x100000 1772 1773 void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, 1774 fprintf_function cpu_fprintf, int flags); 1775 1776 /* cpu.c */ 1777 bool cpu_is_bsp(X86CPU *cpu); 1778 1779 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 1780 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 1781 void x86_update_hflags(CPUX86State* env); 1782 1783 #endif /* I386_CPU_H */ 1784