1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 28 /* The x86 has a strong memory model with some store-after-load re-ordering */ 29 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 30 31 /* Maximum instruction code size */ 32 #define TARGET_MAX_INSN_SIZE 16 33 34 /* support for self modifying code even if the modified instruction is 35 close to the modifying instruction */ 36 #define TARGET_HAS_PRECISE_SMC 37 38 #ifdef TARGET_X86_64 39 #define I386_ELF_MACHINE EM_X86_64 40 #define ELF_MACHINE_UNAME "x86_64" 41 #else 42 #define I386_ELF_MACHINE EM_386 43 #define ELF_MACHINE_UNAME "i686" 44 #endif 45 46 enum { 47 R_EAX = 0, 48 R_ECX = 1, 49 R_EDX = 2, 50 R_EBX = 3, 51 R_ESP = 4, 52 R_EBP = 5, 53 R_ESI = 6, 54 R_EDI = 7, 55 R_R8 = 8, 56 R_R9 = 9, 57 R_R10 = 10, 58 R_R11 = 11, 59 R_R12 = 12, 60 R_R13 = 13, 61 R_R14 = 14, 62 R_R15 = 15, 63 64 R_AL = 0, 65 R_CL = 1, 66 R_DL = 2, 67 R_BL = 3, 68 R_AH = 4, 69 R_CH = 5, 70 R_DH = 6, 71 R_BH = 7, 72 }; 73 74 typedef enum X86Seg { 75 R_ES = 0, 76 R_CS = 1, 77 R_SS = 2, 78 R_DS = 3, 79 R_FS = 4, 80 R_GS = 5, 81 R_LDTR = 6, 82 R_TR = 7, 83 } X86Seg; 84 85 /* segment descriptor fields */ 86 #define DESC_G_SHIFT 23 87 #define DESC_G_MASK (1 << DESC_G_SHIFT) 88 #define DESC_B_SHIFT 22 89 #define DESC_B_MASK (1 << DESC_B_SHIFT) 90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91 #define DESC_L_MASK (1 << DESC_L_SHIFT) 92 #define DESC_AVL_SHIFT 20 93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94 #define DESC_P_SHIFT 15 95 #define DESC_P_MASK (1 << DESC_P_SHIFT) 96 #define DESC_DPL_SHIFT 13 97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98 #define DESC_S_SHIFT 12 99 #define DESC_S_MASK (1 << DESC_S_SHIFT) 100 #define DESC_TYPE_SHIFT 8 101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102 #define DESC_A_MASK (1 << 8) 103 104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105 #define DESC_C_MASK (1 << 10) /* code: conforming */ 106 #define DESC_R_MASK (1 << 9) /* code: readable */ 107 108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109 #define DESC_W_MASK (1 << 9) /* data: writable */ 110 111 #define DESC_TSS_BUSY_MASK (1 << 9) 112 113 /* eflags masks */ 114 #define CC_C 0x0001 115 #define CC_P 0x0004 116 #define CC_A 0x0010 117 #define CC_Z 0x0040 118 #define CC_S 0x0080 119 #define CC_O 0x0800 120 121 #define TF_SHIFT 8 122 #define IOPL_SHIFT 12 123 #define VM_SHIFT 17 124 125 #define TF_MASK 0x00000100 126 #define IF_MASK 0x00000200 127 #define DF_MASK 0x00000400 128 #define IOPL_MASK 0x00003000 129 #define NT_MASK 0x00004000 130 #define RF_MASK 0x00010000 131 #define VM_MASK 0x00020000 132 #define AC_MASK 0x00040000 133 #define VIF_MASK 0x00080000 134 #define VIP_MASK 0x00100000 135 #define ID_MASK 0x00200000 136 137 /* hidden flags - used internally by qemu to represent additional cpu 138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140 positions to ease oring with eflags. */ 141 /* current cpl */ 142 #define HF_CPL_SHIFT 0 143 /* true if hardware interrupts must be disabled for next instruction */ 144 #define HF_INHIBIT_IRQ_SHIFT 3 145 /* 16 or 32 segments */ 146 #define HF_CS32_SHIFT 4 147 #define HF_SS32_SHIFT 5 148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149 #define HF_ADDSEG_SHIFT 6 150 /* copy of CR0.PE (protected mode) */ 151 #define HF_PE_SHIFT 7 152 #define HF_TF_SHIFT 8 /* must be same as eflags */ 153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154 #define HF_EM_SHIFT 10 155 #define HF_TS_SHIFT 11 156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159 #define HF_RF_SHIFT 16 /* must be same as eflags */ 160 #define HF_VM_SHIFT 17 /* must be same as eflags */ 161 #define HF_AC_SHIFT 18 /* must be same as eflags */ 162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170 171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176 #define HF_PE_MASK (1 << HF_PE_SHIFT) 177 #define HF_TF_MASK (1 << HF_TF_SHIFT) 178 #define HF_MP_MASK (1 << HF_MP_SHIFT) 179 #define HF_EM_MASK (1 << HF_EM_SHIFT) 180 #define HF_TS_MASK (1 << HF_TS_SHIFT) 181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184 #define HF_RF_MASK (1 << HF_RF_SHIFT) 185 #define HF_VM_MASK (1 << HF_VM_SHIFT) 186 #define HF_AC_MASK (1 << HF_AC_SHIFT) 187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195 196 /* hflags2 */ 197 198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205 206 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 207 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 208 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 209 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 210 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 211 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 212 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 213 214 #define CR0_PE_SHIFT 0 215 #define CR0_MP_SHIFT 1 216 217 #define CR0_PE_MASK (1U << 0) 218 #define CR0_MP_MASK (1U << 1) 219 #define CR0_EM_MASK (1U << 2) 220 #define CR0_TS_MASK (1U << 3) 221 #define CR0_ET_MASK (1U << 4) 222 #define CR0_NE_MASK (1U << 5) 223 #define CR0_WP_MASK (1U << 16) 224 #define CR0_AM_MASK (1U << 18) 225 #define CR0_PG_MASK (1U << 31) 226 227 #define CR4_VME_MASK (1U << 0) 228 #define CR4_PVI_MASK (1U << 1) 229 #define CR4_TSD_MASK (1U << 2) 230 #define CR4_DE_MASK (1U << 3) 231 #define CR4_PSE_MASK (1U << 4) 232 #define CR4_PAE_MASK (1U << 5) 233 #define CR4_MCE_MASK (1U << 6) 234 #define CR4_PGE_MASK (1U << 7) 235 #define CR4_PCE_MASK (1U << 8) 236 #define CR4_OSFXSR_SHIFT 9 237 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 238 #define CR4_OSXMMEXCPT_MASK (1U << 10) 239 #define CR4_LA57_MASK (1U << 12) 240 #define CR4_VMXE_MASK (1U << 13) 241 #define CR4_SMXE_MASK (1U << 14) 242 #define CR4_FSGSBASE_MASK (1U << 16) 243 #define CR4_PCIDE_MASK (1U << 17) 244 #define CR4_OSXSAVE_MASK (1U << 18) 245 #define CR4_SMEP_MASK (1U << 20) 246 #define CR4_SMAP_MASK (1U << 21) 247 #define CR4_PKE_MASK (1U << 22) 248 249 #define DR6_BD (1 << 13) 250 #define DR6_BS (1 << 14) 251 #define DR6_BT (1 << 15) 252 #define DR6_FIXED_1 0xffff0ff0 253 254 #define DR7_GD (1 << 13) 255 #define DR7_TYPE_SHIFT 16 256 #define DR7_LEN_SHIFT 18 257 #define DR7_FIXED_1 0x00000400 258 #define DR7_GLOBAL_BP_MASK 0xaa 259 #define DR7_LOCAL_BP_MASK 0x55 260 #define DR7_MAX_BP 4 261 #define DR7_TYPE_BP_INST 0x0 262 #define DR7_TYPE_DATA_WR 0x1 263 #define DR7_TYPE_IO_RW 0x2 264 #define DR7_TYPE_DATA_RW 0x3 265 266 #define PG_PRESENT_BIT 0 267 #define PG_RW_BIT 1 268 #define PG_USER_BIT 2 269 #define PG_PWT_BIT 3 270 #define PG_PCD_BIT 4 271 #define PG_ACCESSED_BIT 5 272 #define PG_DIRTY_BIT 6 273 #define PG_PSE_BIT 7 274 #define PG_GLOBAL_BIT 8 275 #define PG_PSE_PAT_BIT 12 276 #define PG_PKRU_BIT 59 277 #define PG_NX_BIT 63 278 279 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 280 #define PG_RW_MASK (1 << PG_RW_BIT) 281 #define PG_USER_MASK (1 << PG_USER_BIT) 282 #define PG_PWT_MASK (1 << PG_PWT_BIT) 283 #define PG_PCD_MASK (1 << PG_PCD_BIT) 284 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 285 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 286 #define PG_PSE_MASK (1 << PG_PSE_BIT) 287 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 288 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 289 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 290 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 291 #define PG_HI_USER_MASK 0x7ff0000000000000LL 292 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 293 #define PG_NX_MASK (1ULL << PG_NX_BIT) 294 295 #define PG_ERROR_W_BIT 1 296 297 #define PG_ERROR_P_MASK 0x01 298 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 299 #define PG_ERROR_U_MASK 0x04 300 #define PG_ERROR_RSVD_MASK 0x08 301 #define PG_ERROR_I_D_MASK 0x10 302 #define PG_ERROR_PK_MASK 0x20 303 304 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 305 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 306 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 307 308 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 309 #define MCE_BANKS_DEF 10 310 311 #define MCG_CAP_BANKS_MASK 0xff 312 313 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 314 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 315 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 316 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 317 318 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 319 320 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 321 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 322 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 323 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 324 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 325 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 326 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 327 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 328 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 329 330 /* MISC register defines */ 331 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 332 #define MCM_ADDR_LINEAR 1 /* linear address */ 333 #define MCM_ADDR_PHYS 2 /* physical address */ 334 #define MCM_ADDR_MEM 3 /* memory address */ 335 #define MCM_ADDR_GENERIC 7 /* generic */ 336 337 #define MSR_IA32_TSC 0x10 338 #define MSR_IA32_APICBASE 0x1b 339 #define MSR_IA32_APICBASE_BSP (1<<8) 340 #define MSR_IA32_APICBASE_ENABLE (1<<11) 341 #define MSR_IA32_APICBASE_EXTD (1 << 10) 342 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 343 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 344 #define MSR_TSC_ADJUST 0x0000003b 345 #define MSR_IA32_SPEC_CTRL 0x48 346 #define MSR_VIRT_SSBD 0xc001011f 347 #define MSR_IA32_PRED_CMD 0x49 348 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 349 #define MSR_IA32_TSCDEADLINE 0x6e0 350 351 #define FEATURE_CONTROL_LOCKED (1<<0) 352 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 353 #define FEATURE_CONTROL_LMCE (1<<20) 354 355 #define MSR_P6_PERFCTR0 0xc1 356 357 #define MSR_IA32_SMBASE 0x9e 358 #define MSR_SMI_COUNT 0x34 359 #define MSR_MTRRcap 0xfe 360 #define MSR_MTRRcap_VCNT 8 361 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 362 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 363 364 #define MSR_IA32_SYSENTER_CS 0x174 365 #define MSR_IA32_SYSENTER_ESP 0x175 366 #define MSR_IA32_SYSENTER_EIP 0x176 367 368 #define MSR_MCG_CAP 0x179 369 #define MSR_MCG_STATUS 0x17a 370 #define MSR_MCG_CTL 0x17b 371 #define MSR_MCG_EXT_CTL 0x4d0 372 373 #define MSR_P6_EVNTSEL0 0x186 374 375 #define MSR_IA32_PERF_STATUS 0x198 376 377 #define MSR_IA32_MISC_ENABLE 0x1a0 378 /* Indicates good rep/movs microcode on some processors: */ 379 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 380 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 381 382 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 383 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 384 385 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 386 387 #define MSR_MTRRfix64K_00000 0x250 388 #define MSR_MTRRfix16K_80000 0x258 389 #define MSR_MTRRfix16K_A0000 0x259 390 #define MSR_MTRRfix4K_C0000 0x268 391 #define MSR_MTRRfix4K_C8000 0x269 392 #define MSR_MTRRfix4K_D0000 0x26a 393 #define MSR_MTRRfix4K_D8000 0x26b 394 #define MSR_MTRRfix4K_E0000 0x26c 395 #define MSR_MTRRfix4K_E8000 0x26d 396 #define MSR_MTRRfix4K_F0000 0x26e 397 #define MSR_MTRRfix4K_F8000 0x26f 398 399 #define MSR_PAT 0x277 400 401 #define MSR_MTRRdefType 0x2ff 402 403 #define MSR_CORE_PERF_FIXED_CTR0 0x309 404 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 405 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 406 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 407 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 408 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 409 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 410 411 #define MSR_MC0_CTL 0x400 412 #define MSR_MC0_STATUS 0x401 413 #define MSR_MC0_ADDR 0x402 414 #define MSR_MC0_MISC 0x403 415 416 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 417 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 418 #define MSR_IA32_RTIT_CTL 0x570 419 #define MSR_IA32_RTIT_STATUS 0x571 420 #define MSR_IA32_RTIT_CR3_MATCH 0x572 421 #define MSR_IA32_RTIT_ADDR0_A 0x580 422 #define MSR_IA32_RTIT_ADDR0_B 0x581 423 #define MSR_IA32_RTIT_ADDR1_A 0x582 424 #define MSR_IA32_RTIT_ADDR1_B 0x583 425 #define MSR_IA32_RTIT_ADDR2_A 0x584 426 #define MSR_IA32_RTIT_ADDR2_B 0x585 427 #define MSR_IA32_RTIT_ADDR3_A 0x586 428 #define MSR_IA32_RTIT_ADDR3_B 0x587 429 #define MAX_RTIT_ADDRS 8 430 431 #define MSR_EFER 0xc0000080 432 433 #define MSR_EFER_SCE (1 << 0) 434 #define MSR_EFER_LME (1 << 8) 435 #define MSR_EFER_LMA (1 << 10) 436 #define MSR_EFER_NXE (1 << 11) 437 #define MSR_EFER_SVME (1 << 12) 438 #define MSR_EFER_FFXSR (1 << 14) 439 440 #define MSR_STAR 0xc0000081 441 #define MSR_LSTAR 0xc0000082 442 #define MSR_CSTAR 0xc0000083 443 #define MSR_FMASK 0xc0000084 444 #define MSR_FSBASE 0xc0000100 445 #define MSR_GSBASE 0xc0000101 446 #define MSR_KERNELGSBASE 0xc0000102 447 #define MSR_TSC_AUX 0xc0000103 448 449 #define MSR_VM_HSAVE_PA 0xc0010117 450 451 #define MSR_IA32_BNDCFGS 0x00000d90 452 #define MSR_IA32_XSS 0x00000da0 453 454 #define XSTATE_FP_BIT 0 455 #define XSTATE_SSE_BIT 1 456 #define XSTATE_YMM_BIT 2 457 #define XSTATE_BNDREGS_BIT 3 458 #define XSTATE_BNDCSR_BIT 4 459 #define XSTATE_OPMASK_BIT 5 460 #define XSTATE_ZMM_Hi256_BIT 6 461 #define XSTATE_Hi16_ZMM_BIT 7 462 #define XSTATE_PKRU_BIT 9 463 464 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 465 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 466 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 467 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 468 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 469 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 470 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 471 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 472 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 473 474 /* CPUID feature words */ 475 typedef enum FeatureWord { 476 FEAT_1_EDX, /* CPUID[1].EDX */ 477 FEAT_1_ECX, /* CPUID[1].ECX */ 478 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 479 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 480 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 481 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 482 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 483 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 484 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 485 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 486 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 487 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 488 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 489 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 490 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 491 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ 492 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ 493 FEAT_SVM, /* CPUID[8000_000A].EDX */ 494 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 495 FEAT_6_EAX, /* CPUID[6].EAX */ 496 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 497 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 498 FEAT_ARCH_CAPABILITIES, 499 FEATURE_WORDS, 500 } FeatureWord; 501 502 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 503 504 /* cpuid_features bits */ 505 #define CPUID_FP87 (1U << 0) 506 #define CPUID_VME (1U << 1) 507 #define CPUID_DE (1U << 2) 508 #define CPUID_PSE (1U << 3) 509 #define CPUID_TSC (1U << 4) 510 #define CPUID_MSR (1U << 5) 511 #define CPUID_PAE (1U << 6) 512 #define CPUID_MCE (1U << 7) 513 #define CPUID_CX8 (1U << 8) 514 #define CPUID_APIC (1U << 9) 515 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 516 #define CPUID_MTRR (1U << 12) 517 #define CPUID_PGE (1U << 13) 518 #define CPUID_MCA (1U << 14) 519 #define CPUID_CMOV (1U << 15) 520 #define CPUID_PAT (1U << 16) 521 #define CPUID_PSE36 (1U << 17) 522 #define CPUID_PN (1U << 18) 523 #define CPUID_CLFLUSH (1U << 19) 524 #define CPUID_DTS (1U << 21) 525 #define CPUID_ACPI (1U << 22) 526 #define CPUID_MMX (1U << 23) 527 #define CPUID_FXSR (1U << 24) 528 #define CPUID_SSE (1U << 25) 529 #define CPUID_SSE2 (1U << 26) 530 #define CPUID_SS (1U << 27) 531 #define CPUID_HT (1U << 28) 532 #define CPUID_TM (1U << 29) 533 #define CPUID_IA64 (1U << 30) 534 #define CPUID_PBE (1U << 31) 535 536 #define CPUID_EXT_SSE3 (1U << 0) 537 #define CPUID_EXT_PCLMULQDQ (1U << 1) 538 #define CPUID_EXT_DTES64 (1U << 2) 539 #define CPUID_EXT_MONITOR (1U << 3) 540 #define CPUID_EXT_DSCPL (1U << 4) 541 #define CPUID_EXT_VMX (1U << 5) 542 #define CPUID_EXT_SMX (1U << 6) 543 #define CPUID_EXT_EST (1U << 7) 544 #define CPUID_EXT_TM2 (1U << 8) 545 #define CPUID_EXT_SSSE3 (1U << 9) 546 #define CPUID_EXT_CID (1U << 10) 547 #define CPUID_EXT_FMA (1U << 12) 548 #define CPUID_EXT_CX16 (1U << 13) 549 #define CPUID_EXT_XTPR (1U << 14) 550 #define CPUID_EXT_PDCM (1U << 15) 551 #define CPUID_EXT_PCID (1U << 17) 552 #define CPUID_EXT_DCA (1U << 18) 553 #define CPUID_EXT_SSE41 (1U << 19) 554 #define CPUID_EXT_SSE42 (1U << 20) 555 #define CPUID_EXT_X2APIC (1U << 21) 556 #define CPUID_EXT_MOVBE (1U << 22) 557 #define CPUID_EXT_POPCNT (1U << 23) 558 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 559 #define CPUID_EXT_AES (1U << 25) 560 #define CPUID_EXT_XSAVE (1U << 26) 561 #define CPUID_EXT_OSXSAVE (1U << 27) 562 #define CPUID_EXT_AVX (1U << 28) 563 #define CPUID_EXT_F16C (1U << 29) 564 #define CPUID_EXT_RDRAND (1U << 30) 565 #define CPUID_EXT_HYPERVISOR (1U << 31) 566 567 #define CPUID_EXT2_FPU (1U << 0) 568 #define CPUID_EXT2_VME (1U << 1) 569 #define CPUID_EXT2_DE (1U << 2) 570 #define CPUID_EXT2_PSE (1U << 3) 571 #define CPUID_EXT2_TSC (1U << 4) 572 #define CPUID_EXT2_MSR (1U << 5) 573 #define CPUID_EXT2_PAE (1U << 6) 574 #define CPUID_EXT2_MCE (1U << 7) 575 #define CPUID_EXT2_CX8 (1U << 8) 576 #define CPUID_EXT2_APIC (1U << 9) 577 #define CPUID_EXT2_SYSCALL (1U << 11) 578 #define CPUID_EXT2_MTRR (1U << 12) 579 #define CPUID_EXT2_PGE (1U << 13) 580 #define CPUID_EXT2_MCA (1U << 14) 581 #define CPUID_EXT2_CMOV (1U << 15) 582 #define CPUID_EXT2_PAT (1U << 16) 583 #define CPUID_EXT2_PSE36 (1U << 17) 584 #define CPUID_EXT2_MP (1U << 19) 585 #define CPUID_EXT2_NX (1U << 20) 586 #define CPUID_EXT2_MMXEXT (1U << 22) 587 #define CPUID_EXT2_MMX (1U << 23) 588 #define CPUID_EXT2_FXSR (1U << 24) 589 #define CPUID_EXT2_FFXSR (1U << 25) 590 #define CPUID_EXT2_PDPE1GB (1U << 26) 591 #define CPUID_EXT2_RDTSCP (1U << 27) 592 #define CPUID_EXT2_LM (1U << 29) 593 #define CPUID_EXT2_3DNOWEXT (1U << 30) 594 #define CPUID_EXT2_3DNOW (1U << 31) 595 596 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 597 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 598 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 599 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 600 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 601 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 602 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 603 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 604 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 605 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 606 607 #define CPUID_EXT3_LAHF_LM (1U << 0) 608 #define CPUID_EXT3_CMP_LEG (1U << 1) 609 #define CPUID_EXT3_SVM (1U << 2) 610 #define CPUID_EXT3_EXTAPIC (1U << 3) 611 #define CPUID_EXT3_CR8LEG (1U << 4) 612 #define CPUID_EXT3_ABM (1U << 5) 613 #define CPUID_EXT3_SSE4A (1U << 6) 614 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 615 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 616 #define CPUID_EXT3_OSVW (1U << 9) 617 #define CPUID_EXT3_IBS (1U << 10) 618 #define CPUID_EXT3_XOP (1U << 11) 619 #define CPUID_EXT3_SKINIT (1U << 12) 620 #define CPUID_EXT3_WDT (1U << 13) 621 #define CPUID_EXT3_LWP (1U << 15) 622 #define CPUID_EXT3_FMA4 (1U << 16) 623 #define CPUID_EXT3_TCE (1U << 17) 624 #define CPUID_EXT3_NODEID (1U << 19) 625 #define CPUID_EXT3_TBM (1U << 21) 626 #define CPUID_EXT3_TOPOEXT (1U << 22) 627 #define CPUID_EXT3_PERFCORE (1U << 23) 628 #define CPUID_EXT3_PERFNB (1U << 24) 629 630 #define CPUID_SVM_NPT (1U << 0) 631 #define CPUID_SVM_LBRV (1U << 1) 632 #define CPUID_SVM_SVMLOCK (1U << 2) 633 #define CPUID_SVM_NRIPSAVE (1U << 3) 634 #define CPUID_SVM_TSCSCALE (1U << 4) 635 #define CPUID_SVM_VMCBCLEAN (1U << 5) 636 #define CPUID_SVM_FLUSHASID (1U << 6) 637 #define CPUID_SVM_DECODEASSIST (1U << 7) 638 #define CPUID_SVM_PAUSEFILTER (1U << 10) 639 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 640 641 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 642 #define CPUID_7_0_EBX_BMI1 (1U << 3) 643 #define CPUID_7_0_EBX_HLE (1U << 4) 644 #define CPUID_7_0_EBX_AVX2 (1U << 5) 645 #define CPUID_7_0_EBX_SMEP (1U << 7) 646 #define CPUID_7_0_EBX_BMI2 (1U << 8) 647 #define CPUID_7_0_EBX_ERMS (1U << 9) 648 #define CPUID_7_0_EBX_INVPCID (1U << 10) 649 #define CPUID_7_0_EBX_RTM (1U << 11) 650 #define CPUID_7_0_EBX_MPX (1U << 14) 651 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 652 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 653 #define CPUID_7_0_EBX_RDSEED (1U << 18) 654 #define CPUID_7_0_EBX_ADX (1U << 19) 655 #define CPUID_7_0_EBX_SMAP (1U << 20) 656 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 657 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 658 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 659 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 660 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */ 661 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 662 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 663 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 664 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 665 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 666 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 667 668 #define CPUID_7_0_ECX_AVX512BMI (1U << 1) 669 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 670 #define CPUID_7_0_ECX_UMIP (1U << 2) 671 #define CPUID_7_0_ECX_PKU (1U << 3) 672 #define CPUID_7_0_ECX_OSPKE (1U << 4) 673 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ 674 #define CPUID_7_0_ECX_GFNI (1U << 8) 675 #define CPUID_7_0_ECX_VAES (1U << 9) 676 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 677 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 678 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 679 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 680 #define CPUID_7_0_ECX_LA57 (1U << 16) 681 #define CPUID_7_0_ECX_RDPID (1U << 22) 682 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ 683 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ 684 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ 685 686 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 687 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 688 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ 689 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ 690 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ 691 692 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and 693 do not invalidate cache */ 694 #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ 695 696 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 697 #define CPUID_XSAVE_XSAVEC (1U << 1) 698 #define CPUID_XSAVE_XGETBV1 (1U << 2) 699 #define CPUID_XSAVE_XSAVES (1U << 3) 700 701 #define CPUID_6_EAX_ARAT (1U << 2) 702 703 /* CPUID[0x80000007].EDX flags: */ 704 #define CPUID_APM_INVTSC (1U << 8) 705 706 #define CPUID_VENDOR_SZ 12 707 708 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 709 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 710 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 711 #define CPUID_VENDOR_INTEL "GenuineIntel" 712 713 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 714 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 715 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 716 #define CPUID_VENDOR_AMD "AuthenticAMD" 717 718 #define CPUID_VENDOR_VIA "CentaurHauls" 719 720 #define CPUID_VENDOR_HYGON "HygonGenuine" 721 722 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 723 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 724 725 /* CPUID[0xB].ECX level types */ 726 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 727 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 728 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 729 730 /* MSR Feature Bits */ 731 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 732 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 733 #define MSR_ARCH_CAP_RSBA (1U << 2) 734 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 735 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 736 737 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 738 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 739 #endif 740 741 #define EXCP00_DIVZ 0 742 #define EXCP01_DB 1 743 #define EXCP02_NMI 2 744 #define EXCP03_INT3 3 745 #define EXCP04_INTO 4 746 #define EXCP05_BOUND 5 747 #define EXCP06_ILLOP 6 748 #define EXCP07_PREX 7 749 #define EXCP08_DBLE 8 750 #define EXCP09_XERR 9 751 #define EXCP0A_TSS 10 752 #define EXCP0B_NOSEG 11 753 #define EXCP0C_STACK 12 754 #define EXCP0D_GPF 13 755 #define EXCP0E_PAGE 14 756 #define EXCP10_COPR 16 757 #define EXCP11_ALGN 17 758 #define EXCP12_MCHK 18 759 760 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 761 for syscall instruction */ 762 #define EXCP_VMEXIT 0x100 763 764 /* i386-specific interrupt pending bits. */ 765 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 766 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 767 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 768 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 769 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 770 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 771 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 772 773 /* Use a clearer name for this. */ 774 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 775 776 /* Instead of computing the condition codes after each x86 instruction, 777 * QEMU just stores one operand (called CC_SRC), the result 778 * (called CC_DST) and the type of operation (called CC_OP). When the 779 * condition codes are needed, the condition codes can be calculated 780 * using this information. Condition codes are not generated if they 781 * are only needed for conditional branches. 782 */ 783 typedef enum { 784 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 785 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 786 787 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 788 CC_OP_MULW, 789 CC_OP_MULL, 790 CC_OP_MULQ, 791 792 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 793 CC_OP_ADDW, 794 CC_OP_ADDL, 795 CC_OP_ADDQ, 796 797 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 798 CC_OP_ADCW, 799 CC_OP_ADCL, 800 CC_OP_ADCQ, 801 802 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 803 CC_OP_SUBW, 804 CC_OP_SUBL, 805 CC_OP_SUBQ, 806 807 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 808 CC_OP_SBBW, 809 CC_OP_SBBL, 810 CC_OP_SBBQ, 811 812 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 813 CC_OP_LOGICW, 814 CC_OP_LOGICL, 815 CC_OP_LOGICQ, 816 817 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 818 CC_OP_INCW, 819 CC_OP_INCL, 820 CC_OP_INCQ, 821 822 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 823 CC_OP_DECW, 824 CC_OP_DECL, 825 CC_OP_DECQ, 826 827 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 828 CC_OP_SHLW, 829 CC_OP_SHLL, 830 CC_OP_SHLQ, 831 832 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 833 CC_OP_SARW, 834 CC_OP_SARL, 835 CC_OP_SARQ, 836 837 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 838 CC_OP_BMILGW, 839 CC_OP_BMILGL, 840 CC_OP_BMILGQ, 841 842 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 843 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 844 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 845 846 CC_OP_CLR, /* Z set, all other flags clear. */ 847 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 848 849 CC_OP_NB, 850 } CCOp; 851 852 typedef struct SegmentCache { 853 uint32_t selector; 854 target_ulong base; 855 uint32_t limit; 856 uint32_t flags; 857 } SegmentCache; 858 859 #define MMREG_UNION(n, bits) \ 860 union n { \ 861 uint8_t _b_##n[(bits)/8]; \ 862 uint16_t _w_##n[(bits)/16]; \ 863 uint32_t _l_##n[(bits)/32]; \ 864 uint64_t _q_##n[(bits)/64]; \ 865 float32 _s_##n[(bits)/32]; \ 866 float64 _d_##n[(bits)/64]; \ 867 } 868 869 typedef union { 870 uint8_t _b[16]; 871 uint16_t _w[8]; 872 uint32_t _l[4]; 873 uint64_t _q[2]; 874 } XMMReg; 875 876 typedef union { 877 uint8_t _b[32]; 878 uint16_t _w[16]; 879 uint32_t _l[8]; 880 uint64_t _q[4]; 881 } YMMReg; 882 883 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 884 typedef MMREG_UNION(MMXReg, 64) MMXReg; 885 886 typedef struct BNDReg { 887 uint64_t lb; 888 uint64_t ub; 889 } BNDReg; 890 891 typedef struct BNDCSReg { 892 uint64_t cfgu; 893 uint64_t sts; 894 } BNDCSReg; 895 896 #define BNDCFG_ENABLE 1ULL 897 #define BNDCFG_BNDPRESERVE 2ULL 898 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 899 900 #ifdef HOST_WORDS_BIGENDIAN 901 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 902 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 903 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 904 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 905 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 906 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 907 908 #define MMX_B(n) _b_MMXReg[7 - (n)] 909 #define MMX_W(n) _w_MMXReg[3 - (n)] 910 #define MMX_L(n) _l_MMXReg[1 - (n)] 911 #define MMX_S(n) _s_MMXReg[1 - (n)] 912 #else 913 #define ZMM_B(n) _b_ZMMReg[n] 914 #define ZMM_W(n) _w_ZMMReg[n] 915 #define ZMM_L(n) _l_ZMMReg[n] 916 #define ZMM_S(n) _s_ZMMReg[n] 917 #define ZMM_Q(n) _q_ZMMReg[n] 918 #define ZMM_D(n) _d_ZMMReg[n] 919 920 #define MMX_B(n) _b_MMXReg[n] 921 #define MMX_W(n) _w_MMXReg[n] 922 #define MMX_L(n) _l_MMXReg[n] 923 #define MMX_S(n) _s_MMXReg[n] 924 #endif 925 #define MMX_Q(n) _q_MMXReg[n] 926 927 typedef union { 928 floatx80 d __attribute__((aligned(16))); 929 MMXReg mmx; 930 } FPReg; 931 932 typedef struct { 933 uint64_t base; 934 uint64_t mask; 935 } MTRRVar; 936 937 #define CPU_NB_REGS64 16 938 #define CPU_NB_REGS32 8 939 940 #ifdef TARGET_X86_64 941 #define CPU_NB_REGS CPU_NB_REGS64 942 #else 943 #define CPU_NB_REGS CPU_NB_REGS32 944 #endif 945 946 #define MAX_FIXED_COUNTERS 3 947 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 948 949 #define TARGET_INSN_START_EXTRA_WORDS 1 950 951 #define NB_OPMASK_REGS 8 952 953 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 954 * that APIC ID hasn't been set yet 955 */ 956 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 957 958 typedef union X86LegacyXSaveArea { 959 struct { 960 uint16_t fcw; 961 uint16_t fsw; 962 uint8_t ftw; 963 uint8_t reserved; 964 uint16_t fpop; 965 uint64_t fpip; 966 uint64_t fpdp; 967 uint32_t mxcsr; 968 uint32_t mxcsr_mask; 969 FPReg fpregs[8]; 970 uint8_t xmm_regs[16][16]; 971 }; 972 uint8_t data[512]; 973 } X86LegacyXSaveArea; 974 975 typedef struct X86XSaveHeader { 976 uint64_t xstate_bv; 977 uint64_t xcomp_bv; 978 uint64_t reserve0; 979 uint8_t reserved[40]; 980 } X86XSaveHeader; 981 982 /* Ext. save area 2: AVX State */ 983 typedef struct XSaveAVX { 984 uint8_t ymmh[16][16]; 985 } XSaveAVX; 986 987 /* Ext. save area 3: BNDREG */ 988 typedef struct XSaveBNDREG { 989 BNDReg bnd_regs[4]; 990 } XSaveBNDREG; 991 992 /* Ext. save area 4: BNDCSR */ 993 typedef union XSaveBNDCSR { 994 BNDCSReg bndcsr; 995 uint8_t data[64]; 996 } XSaveBNDCSR; 997 998 /* Ext. save area 5: Opmask */ 999 typedef struct XSaveOpmask { 1000 uint64_t opmask_regs[NB_OPMASK_REGS]; 1001 } XSaveOpmask; 1002 1003 /* Ext. save area 6: ZMM_Hi256 */ 1004 typedef struct XSaveZMM_Hi256 { 1005 uint8_t zmm_hi256[16][32]; 1006 } XSaveZMM_Hi256; 1007 1008 /* Ext. save area 7: Hi16_ZMM */ 1009 typedef struct XSaveHi16_ZMM { 1010 uint8_t hi16_zmm[16][64]; 1011 } XSaveHi16_ZMM; 1012 1013 /* Ext. save area 9: PKRU state */ 1014 typedef struct XSavePKRU { 1015 uint32_t pkru; 1016 uint32_t padding; 1017 } XSavePKRU; 1018 1019 typedef struct X86XSaveArea { 1020 X86LegacyXSaveArea legacy; 1021 X86XSaveHeader header; 1022 1023 /* Extended save areas: */ 1024 1025 /* AVX State: */ 1026 XSaveAVX avx_state; 1027 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1028 /* MPX State: */ 1029 XSaveBNDREG bndreg_state; 1030 XSaveBNDCSR bndcsr_state; 1031 /* AVX-512 State: */ 1032 XSaveOpmask opmask_state; 1033 XSaveZMM_Hi256 zmm_hi256_state; 1034 XSaveHi16_ZMM hi16_zmm_state; 1035 /* PKRU State: */ 1036 XSavePKRU pkru_state; 1037 } X86XSaveArea; 1038 1039 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1040 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1041 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1042 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1043 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1044 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1045 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1046 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1047 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1048 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1049 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1050 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1051 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1052 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1053 1054 typedef enum TPRAccess { 1055 TPR_ACCESS_READ, 1056 TPR_ACCESS_WRITE, 1057 } TPRAccess; 1058 1059 /* Cache information data structures: */ 1060 1061 enum CacheType { 1062 DATA_CACHE, 1063 INSTRUCTION_CACHE, 1064 UNIFIED_CACHE 1065 }; 1066 1067 typedef struct CPUCacheInfo { 1068 enum CacheType type; 1069 uint8_t level; 1070 /* Size in bytes */ 1071 uint32_t size; 1072 /* Line size, in bytes */ 1073 uint16_t line_size; 1074 /* 1075 * Associativity. 1076 * Note: representation of fully-associative caches is not implemented 1077 */ 1078 uint8_t associativity; 1079 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1080 uint8_t partitions; 1081 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1082 uint32_t sets; 1083 /* 1084 * Lines per tag. 1085 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1086 * (Is this synonym to @partitions?) 1087 */ 1088 uint8_t lines_per_tag; 1089 1090 /* Self-initializing cache */ 1091 bool self_init; 1092 /* 1093 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1094 * non-originating threads sharing this cache. 1095 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1096 */ 1097 bool no_invd_sharing; 1098 /* 1099 * Cache is inclusive of lower cache levels. 1100 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1101 */ 1102 bool inclusive; 1103 /* 1104 * A complex function is used to index the cache, potentially using all 1105 * address bits. CPUID[4].EDX[bit 2]. 1106 */ 1107 bool complex_indexing; 1108 } CPUCacheInfo; 1109 1110 1111 typedef struct CPUCaches { 1112 CPUCacheInfo *l1d_cache; 1113 CPUCacheInfo *l1i_cache; 1114 CPUCacheInfo *l2_cache; 1115 CPUCacheInfo *l3_cache; 1116 } CPUCaches; 1117 1118 typedef struct CPUX86State { 1119 /* standard registers */ 1120 target_ulong regs[CPU_NB_REGS]; 1121 target_ulong eip; 1122 target_ulong eflags; /* eflags register. During CPU emulation, CC 1123 flags and DF are set to zero because they are 1124 stored elsewhere */ 1125 1126 /* emulator internal eflags handling */ 1127 target_ulong cc_dst; 1128 target_ulong cc_src; 1129 target_ulong cc_src2; 1130 uint32_t cc_op; 1131 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1132 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1133 are known at translation time. */ 1134 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1135 1136 /* segments */ 1137 SegmentCache segs[6]; /* selector values */ 1138 SegmentCache ldt; 1139 SegmentCache tr; 1140 SegmentCache gdt; /* only base and limit are used */ 1141 SegmentCache idt; /* only base and limit are used */ 1142 1143 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1144 int32_t a20_mask; 1145 1146 BNDReg bnd_regs[4]; 1147 BNDCSReg bndcs_regs; 1148 uint64_t msr_bndcfgs; 1149 uint64_t efer; 1150 1151 /* Beginning of state preserved by INIT (dummy marker). */ 1152 struct {} start_init_save; 1153 1154 /* FPU state */ 1155 unsigned int fpstt; /* top of stack index */ 1156 uint16_t fpus; 1157 uint16_t fpuc; 1158 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1159 FPReg fpregs[8]; 1160 /* KVM-only so far */ 1161 uint16_t fpop; 1162 uint64_t fpip; 1163 uint64_t fpdp; 1164 1165 /* emulator internal variables */ 1166 float_status fp_status; 1167 floatx80 ft0; 1168 1169 float_status mmx_status; /* for 3DNow! float ops */ 1170 float_status sse_status; 1171 uint32_t mxcsr; 1172 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1173 ZMMReg xmm_t0; 1174 MMXReg mmx_t0; 1175 1176 XMMReg ymmh_regs[CPU_NB_REGS]; 1177 1178 uint64_t opmask_regs[NB_OPMASK_REGS]; 1179 YMMReg zmmh_regs[CPU_NB_REGS]; 1180 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1181 1182 /* sysenter registers */ 1183 uint32_t sysenter_cs; 1184 target_ulong sysenter_esp; 1185 target_ulong sysenter_eip; 1186 uint64_t star; 1187 1188 uint64_t vm_hsave; 1189 1190 #ifdef TARGET_X86_64 1191 target_ulong lstar; 1192 target_ulong cstar; 1193 target_ulong fmask; 1194 target_ulong kernelgsbase; 1195 #endif 1196 1197 uint64_t tsc; 1198 uint64_t tsc_adjust; 1199 uint64_t tsc_deadline; 1200 uint64_t tsc_aux; 1201 1202 uint64_t xcr0; 1203 1204 uint64_t mcg_status; 1205 uint64_t msr_ia32_misc_enable; 1206 uint64_t msr_ia32_feature_control; 1207 1208 uint64_t msr_fixed_ctr_ctrl; 1209 uint64_t msr_global_ctrl; 1210 uint64_t msr_global_status; 1211 uint64_t msr_global_ovf_ctrl; 1212 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1213 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1214 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1215 1216 uint64_t pat; 1217 uint32_t smbase; 1218 uint64_t msr_smi_count; 1219 1220 uint32_t pkru; 1221 1222 uint64_t spec_ctrl; 1223 uint64_t virt_ssbd; 1224 1225 /* End of state preserved by INIT (dummy marker). */ 1226 struct {} end_init_save; 1227 1228 uint64_t system_time_msr; 1229 uint64_t wall_clock_msr; 1230 uint64_t steal_time_msr; 1231 uint64_t async_pf_en_msr; 1232 uint64_t pv_eoi_en_msr; 1233 1234 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1235 uint64_t msr_hv_hypercall; 1236 uint64_t msr_hv_guest_os_id; 1237 uint64_t msr_hv_tsc; 1238 1239 /* Per-VCPU HV MSRs */ 1240 uint64_t msr_hv_vapic; 1241 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1242 uint64_t msr_hv_runtime; 1243 uint64_t msr_hv_synic_control; 1244 uint64_t msr_hv_synic_evt_page; 1245 uint64_t msr_hv_synic_msg_page; 1246 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1247 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1248 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1249 uint64_t msr_hv_reenlightenment_control; 1250 uint64_t msr_hv_tsc_emulation_control; 1251 uint64_t msr_hv_tsc_emulation_status; 1252 1253 uint64_t msr_rtit_ctrl; 1254 uint64_t msr_rtit_status; 1255 uint64_t msr_rtit_output_base; 1256 uint64_t msr_rtit_output_mask; 1257 uint64_t msr_rtit_cr3_match; 1258 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1259 1260 /* exception/interrupt handling */ 1261 int error_code; 1262 int exception_is_int; 1263 target_ulong exception_next_eip; 1264 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1265 union { 1266 struct CPUBreakpoint *cpu_breakpoint[4]; 1267 struct CPUWatchpoint *cpu_watchpoint[4]; 1268 }; /* break/watchpoints for dr[0..3] */ 1269 int old_exception; /* exception in flight */ 1270 1271 uint64_t vm_vmcb; 1272 uint64_t tsc_offset; 1273 uint64_t intercept; 1274 uint16_t intercept_cr_read; 1275 uint16_t intercept_cr_write; 1276 uint16_t intercept_dr_read; 1277 uint16_t intercept_dr_write; 1278 uint32_t intercept_exceptions; 1279 uint64_t nested_cr3; 1280 uint32_t nested_pg_mode; 1281 uint8_t v_tpr; 1282 1283 /* KVM states, automatically cleared on reset */ 1284 uint8_t nmi_injected; 1285 uint8_t nmi_pending; 1286 1287 uintptr_t retaddr; 1288 1289 /* Fields up to this point are cleared by a CPU reset */ 1290 struct {} end_reset_fields; 1291 1292 CPU_COMMON 1293 1294 /* Fields after CPU_COMMON are preserved across CPU reset. */ 1295 1296 /* processor features (e.g. for CPUID insn) */ 1297 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1298 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1299 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1300 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1301 /* Actual level/xlevel/xlevel2 value: */ 1302 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1303 uint32_t cpuid_vendor1; 1304 uint32_t cpuid_vendor2; 1305 uint32_t cpuid_vendor3; 1306 uint32_t cpuid_version; 1307 FeatureWordArray features; 1308 /* Features that were explicitly enabled/disabled */ 1309 FeatureWordArray user_features; 1310 uint32_t cpuid_model[12]; 1311 /* Cache information for CPUID. When legacy-cache=on, the cache data 1312 * on each CPUID leaf will be different, because we keep compatibility 1313 * with old QEMU versions. 1314 */ 1315 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1316 1317 /* MTRRs */ 1318 uint64_t mtrr_fixed[11]; 1319 uint64_t mtrr_deftype; 1320 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1321 1322 /* For KVM */ 1323 uint32_t mp_state; 1324 int32_t exception_injected; 1325 int32_t interrupt_injected; 1326 uint8_t soft_interrupt; 1327 uint8_t has_error_code; 1328 uint32_t ins_len; 1329 uint32_t sipi_vector; 1330 bool tsc_valid; 1331 int64_t tsc_khz; 1332 int64_t user_tsc_khz; /* for sanity check only */ 1333 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1334 void *xsave_buf; 1335 #endif 1336 #if defined(CONFIG_HVF) 1337 HVFX86EmulatorState *hvf_emul; 1338 #endif 1339 1340 uint64_t mcg_cap; 1341 uint64_t mcg_ctl; 1342 uint64_t mcg_ext_ctl; 1343 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1344 uint64_t xstate_bv; 1345 1346 /* vmstate */ 1347 uint16_t fpus_vmstate; 1348 uint16_t fptag_vmstate; 1349 uint16_t fpregs_format_vmstate; 1350 1351 uint64_t xss; 1352 1353 TPRAccess tpr_access_type; 1354 } CPUX86State; 1355 1356 struct kvm_msrs; 1357 1358 /** 1359 * X86CPU: 1360 * @env: #CPUX86State 1361 * @migratable: If set, only migratable flags will be accepted when "enforce" 1362 * mode is used, and only migratable flags will be included in the "host" 1363 * CPU model. 1364 * 1365 * An x86 CPU. 1366 */ 1367 struct X86CPU { 1368 /*< private >*/ 1369 CPUState parent_obj; 1370 /*< public >*/ 1371 1372 CPUNegativeOffsetState neg; 1373 CPUX86State env; 1374 1375 bool hyperv_vapic; 1376 bool hyperv_relaxed_timing; 1377 int hyperv_spinlock_attempts; 1378 char *hyperv_vendor_id; 1379 bool hyperv_time; 1380 bool hyperv_crash; 1381 bool hyperv_reset; 1382 bool hyperv_vpindex; 1383 bool hyperv_runtime; 1384 bool hyperv_synic; 1385 bool hyperv_synic_kvm_only; 1386 bool hyperv_stimer; 1387 bool hyperv_frequencies; 1388 bool hyperv_reenlightenment; 1389 bool hyperv_tlbflush; 1390 bool hyperv_evmcs; 1391 bool hyperv_ipi; 1392 bool check_cpuid; 1393 bool enforce_cpuid; 1394 bool expose_kvm; 1395 bool expose_tcg; 1396 bool migratable; 1397 bool migrate_smi_count; 1398 bool max_features; /* Enable all supported features automatically */ 1399 uint32_t apic_id; 1400 1401 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1402 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1403 bool vmware_cpuid_freq; 1404 1405 /* if true the CPUID code directly forward host cache leaves to the guest */ 1406 bool cache_info_passthrough; 1407 1408 /* if true the CPUID code directly forwards 1409 * host monitor/mwait leaves to the guest */ 1410 struct { 1411 uint32_t eax; 1412 uint32_t ebx; 1413 uint32_t ecx; 1414 uint32_t edx; 1415 } mwait; 1416 1417 /* Features that were filtered out because of missing host capabilities */ 1418 uint32_t filtered_features[FEATURE_WORDS]; 1419 1420 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1421 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1422 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1423 * capabilities) directly to the guest. 1424 */ 1425 bool enable_pmu; 1426 1427 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1428 * disabled by default to avoid breaking migration between QEMU with 1429 * different LMCE configurations. 1430 */ 1431 bool enable_lmce; 1432 1433 /* Compatibility bits for old machine types. 1434 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1435 * socket share an virtual l3 cache. 1436 */ 1437 bool enable_l3_cache; 1438 1439 /* Compatibility bits for old machine types. 1440 * If true present the old cache topology information 1441 */ 1442 bool legacy_cache; 1443 1444 /* Compatibility bits for old machine types: */ 1445 bool enable_cpuid_0xb; 1446 1447 /* Enable auto level-increase for all CPUID leaves */ 1448 bool full_cpuid_auto_level; 1449 1450 /* Enable auto level-increase for Intel Processor Trace leave */ 1451 bool intel_pt_auto_level; 1452 1453 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1454 bool fill_mtrr_mask; 1455 1456 /* if true override the phys_bits value with a value read from the host */ 1457 bool host_phys_bits; 1458 1459 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1460 uint8_t host_phys_bits_limit; 1461 1462 /* Stop SMI delivery for migration compatibility with old machines */ 1463 bool kvm_no_smi_migration; 1464 1465 /* Number of physical address bits supported */ 1466 uint32_t phys_bits; 1467 1468 /* in order to simplify APIC support, we leave this pointer to the 1469 user */ 1470 struct DeviceState *apic_state; 1471 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1472 Notifier machine_done; 1473 1474 struct kvm_msrs *kvm_msr_buf; 1475 1476 int32_t node_id; /* NUMA node this CPU belongs to */ 1477 int32_t socket_id; 1478 int32_t core_id; 1479 int32_t thread_id; 1480 1481 int32_t hv_max_vps; 1482 }; 1483 1484 1485 #ifndef CONFIG_USER_ONLY 1486 extern struct VMStateDescription vmstate_x86_cpu; 1487 #endif 1488 1489 /** 1490 * x86_cpu_do_interrupt: 1491 * @cpu: vCPU the interrupt is to be handled by. 1492 */ 1493 void x86_cpu_do_interrupt(CPUState *cpu); 1494 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1495 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1496 1497 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1498 int cpuid, void *opaque); 1499 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1500 int cpuid, void *opaque); 1501 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1502 void *opaque); 1503 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1504 void *opaque); 1505 1506 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1507 Error **errp); 1508 1509 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1510 1511 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1512 1513 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1514 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1515 1516 void x86_cpu_exec_enter(CPUState *cpu); 1517 void x86_cpu_exec_exit(CPUState *cpu); 1518 1519 void x86_cpu_list(void); 1520 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1521 1522 int cpu_get_pic_interrupt(CPUX86State *s); 1523 /* MSDOS compatibility mode FPU exception support */ 1524 void cpu_set_ferr(CPUX86State *s); 1525 /* mpx_helper.c */ 1526 void cpu_sync_bndcs_hflags(CPUX86State *env); 1527 1528 /* this function must always be used to load data in the segment 1529 cache: it synchronizes the hflags with the segment cache values */ 1530 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1531 int seg_reg, unsigned int selector, 1532 target_ulong base, 1533 unsigned int limit, 1534 unsigned int flags) 1535 { 1536 SegmentCache *sc; 1537 unsigned int new_hflags; 1538 1539 sc = &env->segs[seg_reg]; 1540 sc->selector = selector; 1541 sc->base = base; 1542 sc->limit = limit; 1543 sc->flags = flags; 1544 1545 /* update the hidden flags */ 1546 { 1547 if (seg_reg == R_CS) { 1548 #ifdef TARGET_X86_64 1549 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1550 /* long mode */ 1551 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1552 env->hflags &= ~(HF_ADDSEG_MASK); 1553 } else 1554 #endif 1555 { 1556 /* legacy / compatibility case */ 1557 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1558 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1559 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1560 new_hflags; 1561 } 1562 } 1563 if (seg_reg == R_SS) { 1564 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1565 #if HF_CPL_MASK != 3 1566 #error HF_CPL_MASK is hardcoded 1567 #endif 1568 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1569 /* Possibly switch between BNDCFGS and BNDCFGU */ 1570 cpu_sync_bndcs_hflags(env); 1571 } 1572 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1573 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1574 if (env->hflags & HF_CS64_MASK) { 1575 /* zero base assumed for DS, ES and SS in long mode */ 1576 } else if (!(env->cr[0] & CR0_PE_MASK) || 1577 (env->eflags & VM_MASK) || 1578 !(env->hflags & HF_CS32_MASK)) { 1579 /* XXX: try to avoid this test. The problem comes from the 1580 fact that is real mode or vm86 mode we only modify the 1581 'base' and 'selector' fields of the segment cache to go 1582 faster. A solution may be to force addseg to one in 1583 translate-i386.c. */ 1584 new_hflags |= HF_ADDSEG_MASK; 1585 } else { 1586 new_hflags |= ((env->segs[R_DS].base | 1587 env->segs[R_ES].base | 1588 env->segs[R_SS].base) != 0) << 1589 HF_ADDSEG_SHIFT; 1590 } 1591 env->hflags = (env->hflags & 1592 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1593 } 1594 } 1595 1596 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1597 uint8_t sipi_vector) 1598 { 1599 CPUState *cs = CPU(cpu); 1600 CPUX86State *env = &cpu->env; 1601 1602 env->eip = 0; 1603 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1604 sipi_vector << 12, 1605 env->segs[R_CS].limit, 1606 env->segs[R_CS].flags); 1607 cs->halted = 0; 1608 } 1609 1610 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1611 target_ulong *base, unsigned int *limit, 1612 unsigned int *flags); 1613 1614 /* op_helper.c */ 1615 /* used for debug or cpu save/restore */ 1616 1617 /* cpu-exec.c */ 1618 /* the following helpers are only usable in user mode simulation as 1619 they can trigger unexpected exceptions */ 1620 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1621 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1622 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1623 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1624 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1625 1626 /* you can call this signal handler from your SIGBUS and SIGSEGV 1627 signal handlers to inform the virtual CPU of exceptions. non zero 1628 is returned if the signal was handled by the virtual CPU. */ 1629 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1630 void *puc); 1631 1632 /* cpu.c */ 1633 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1634 uint32_t *eax, uint32_t *ebx, 1635 uint32_t *ecx, uint32_t *edx); 1636 void cpu_clear_apic_feature(CPUX86State *env); 1637 void host_cpuid(uint32_t function, uint32_t count, 1638 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1639 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1640 1641 /* helper.c */ 1642 bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1643 MMUAccessType access_type, int mmu_idx, 1644 bool probe, uintptr_t retaddr); 1645 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1646 1647 #ifndef CONFIG_USER_ONLY 1648 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1649 { 1650 return !!attrs.secure; 1651 } 1652 1653 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1654 { 1655 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1656 } 1657 1658 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1659 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1660 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1661 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1662 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1663 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1664 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1665 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1666 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1667 #endif 1668 1669 void breakpoint_handler(CPUState *cs); 1670 1671 /* will be suppressed */ 1672 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1673 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1674 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1675 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1676 1677 /* hw/pc.c */ 1678 uint64_t cpu_get_tsc(CPUX86State *env); 1679 1680 /* XXX: This value should match the one returned by CPUID 1681 * and in exec.c */ 1682 # if defined(TARGET_X86_64) 1683 # define TCG_PHYS_ADDR_BITS 40 1684 # else 1685 # define TCG_PHYS_ADDR_BITS 36 1686 # endif 1687 1688 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1689 1690 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1691 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1692 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1693 1694 #ifdef TARGET_X86_64 1695 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1696 #else 1697 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1698 #endif 1699 1700 #define cpu_signal_handler cpu_x86_signal_handler 1701 #define cpu_list x86_cpu_list 1702 1703 /* MMU modes definitions */ 1704 #define MMU_MODE0_SUFFIX _ksmap 1705 #define MMU_MODE1_SUFFIX _user 1706 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1707 #define MMU_KSMAP_IDX 0 1708 #define MMU_USER_IDX 1 1709 #define MMU_KNOSMAP_IDX 2 1710 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1711 { 1712 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1713 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1714 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1715 } 1716 1717 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1718 { 1719 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1720 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1721 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1722 } 1723 1724 #define CC_DST (env->cc_dst) 1725 #define CC_SRC (env->cc_src) 1726 #define CC_SRC2 (env->cc_src2) 1727 #define CC_OP (env->cc_op) 1728 1729 /* n must be a constant to be efficient */ 1730 static inline target_long lshift(target_long x, int n) 1731 { 1732 if (n >= 0) { 1733 return x << n; 1734 } else { 1735 return x >> (-n); 1736 } 1737 } 1738 1739 /* float macros */ 1740 #define FT0 (env->ft0) 1741 #define ST0 (env->fpregs[env->fpstt].d) 1742 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1743 #define ST1 ST(1) 1744 1745 /* translate.c */ 1746 void tcg_x86_init(void); 1747 1748 typedef CPUX86State CPUArchState; 1749 typedef X86CPU ArchCPU; 1750 1751 #include "exec/cpu-all.h" 1752 #include "svm.h" 1753 1754 #if !defined(CONFIG_USER_ONLY) 1755 #include "hw/i386/apic.h" 1756 #endif 1757 1758 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1759 target_ulong *cs_base, uint32_t *flags) 1760 { 1761 *cs_base = env->segs[R_CS].base; 1762 *pc = *cs_base + env->eip; 1763 *flags = env->hflags | 1764 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1765 } 1766 1767 void do_cpu_init(X86CPU *cpu); 1768 void do_cpu_sipi(X86CPU *cpu); 1769 1770 #define MCE_INJECT_BROADCAST 1 1771 #define MCE_INJECT_UNCOND_AO 2 1772 1773 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1774 uint64_t status, uint64_t mcg_status, uint64_t addr, 1775 uint64_t misc, int flags); 1776 1777 /* excp_helper.c */ 1778 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1779 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1780 uintptr_t retaddr); 1781 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1782 int error_code); 1783 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1784 int error_code, uintptr_t retaddr); 1785 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1786 int error_code, int next_eip_addend); 1787 1788 /* cc_helper.c */ 1789 extern const uint8_t parity_table[256]; 1790 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1791 1792 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1793 { 1794 uint32_t eflags = env->eflags; 1795 if (tcg_enabled()) { 1796 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 1797 } 1798 return eflags; 1799 } 1800 1801 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1802 * after generating a call to a helper that uses this. 1803 */ 1804 static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1805 int update_mask) 1806 { 1807 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1808 CC_OP = CC_OP_EFLAGS; 1809 env->df = 1 - (2 * ((eflags >> 10) & 1)); 1810 env->eflags = (env->eflags & ~update_mask) | 1811 (eflags & update_mask) | 0x2; 1812 } 1813 1814 /* load efer and update the corresponding hflags. XXX: do consistency 1815 checks with cpuid bits? */ 1816 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1817 { 1818 env->efer = val; 1819 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1820 if (env->efer & MSR_EFER_LMA) { 1821 env->hflags |= HF_LMA_MASK; 1822 } 1823 if (env->efer & MSR_EFER_SVME) { 1824 env->hflags |= HF_SVME_MASK; 1825 } 1826 } 1827 1828 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 1829 { 1830 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 1831 } 1832 1833 static inline int32_t x86_get_a20_mask(CPUX86State *env) 1834 { 1835 if (env->hflags & HF_SMM_MASK) { 1836 return -1; 1837 } else { 1838 return env->a20_mask; 1839 } 1840 } 1841 1842 /* fpu_helper.c */ 1843 void update_fp_status(CPUX86State *env); 1844 void update_mxcsr_status(CPUX86State *env); 1845 1846 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 1847 { 1848 env->mxcsr = mxcsr; 1849 if (tcg_enabled()) { 1850 update_mxcsr_status(env); 1851 } 1852 } 1853 1854 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 1855 { 1856 env->fpuc = fpuc; 1857 if (tcg_enabled()) { 1858 update_fp_status(env); 1859 } 1860 } 1861 1862 /* mem_helper.c */ 1863 void helper_lock_init(void); 1864 1865 /* svm_helper.c */ 1866 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 1867 uint64_t param, uintptr_t retaddr); 1868 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, 1869 uint64_t exit_info_1, uintptr_t retaddr); 1870 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 1871 1872 /* seg_helper.c */ 1873 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 1874 1875 /* smm_helper.c */ 1876 void do_smm_enter(X86CPU *cpu); 1877 1878 /* apic.c */ 1879 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 1880 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 1881 TPRAccess access); 1882 1883 1884 /* Change the value of a KVM-specific default 1885 * 1886 * If value is NULL, no default will be set and the original 1887 * value from the CPU model table will be kept. 1888 * 1889 * It is valid to call this function only for properties that 1890 * are already present in the kvm_default_props table. 1891 */ 1892 void x86_cpu_change_kvm_default(const char *prop, const char *value); 1893 1894 /* Return name of 32-bit register, from a R_* constant */ 1895 const char *get_register_name_32(unsigned int reg); 1896 1897 void enable_compat_apic_id_mode(void); 1898 1899 #define APIC_DEFAULT_ADDRESS 0xfee00000 1900 #define APIC_SPACE_SIZE 0x100000 1901 1902 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 1903 1904 /* cpu.c */ 1905 bool cpu_is_bsp(X86CPU *cpu); 1906 1907 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 1908 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 1909 void x86_update_hflags(CPUX86State* env); 1910 1911 #endif /* I386_CPU_H */ 1912