1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "kvm/hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 #define KVM_HAVE_MCE_INJECTION 1 33 34 /* support for self modifying code even if the modified instruction is 35 close to the modifying instruction */ 36 #define TARGET_HAS_PRECISE_SMC 37 38 #ifdef TARGET_X86_64 39 #define I386_ELF_MACHINE EM_X86_64 40 #define ELF_MACHINE_UNAME "x86_64" 41 #else 42 #define I386_ELF_MACHINE EM_386 43 #define ELF_MACHINE_UNAME "i686" 44 #endif 45 46 enum { 47 R_EAX = 0, 48 R_ECX = 1, 49 R_EDX = 2, 50 R_EBX = 3, 51 R_ESP = 4, 52 R_EBP = 5, 53 R_ESI = 6, 54 R_EDI = 7, 55 R_R8 = 8, 56 R_R9 = 9, 57 R_R10 = 10, 58 R_R11 = 11, 59 R_R12 = 12, 60 R_R13 = 13, 61 R_R14 = 14, 62 R_R15 = 15, 63 64 R_AL = 0, 65 R_CL = 1, 66 R_DL = 2, 67 R_BL = 3, 68 R_AH = 4, 69 R_CH = 5, 70 R_DH = 6, 71 R_BH = 7, 72 }; 73 74 typedef enum X86Seg { 75 R_ES = 0, 76 R_CS = 1, 77 R_SS = 2, 78 R_DS = 3, 79 R_FS = 4, 80 R_GS = 5, 81 R_LDTR = 6, 82 R_TR = 7, 83 } X86Seg; 84 85 /* segment descriptor fields */ 86 #define DESC_G_SHIFT 23 87 #define DESC_G_MASK (1 << DESC_G_SHIFT) 88 #define DESC_B_SHIFT 22 89 #define DESC_B_MASK (1 << DESC_B_SHIFT) 90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91 #define DESC_L_MASK (1 << DESC_L_SHIFT) 92 #define DESC_AVL_SHIFT 20 93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94 #define DESC_P_SHIFT 15 95 #define DESC_P_MASK (1 << DESC_P_SHIFT) 96 #define DESC_DPL_SHIFT 13 97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98 #define DESC_S_SHIFT 12 99 #define DESC_S_MASK (1 << DESC_S_SHIFT) 100 #define DESC_TYPE_SHIFT 8 101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102 #define DESC_A_MASK (1 << 8) 103 104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105 #define DESC_C_MASK (1 << 10) /* code: conforming */ 106 #define DESC_R_MASK (1 << 9) /* code: readable */ 107 108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109 #define DESC_W_MASK (1 << 9) /* data: writable */ 110 111 #define DESC_TSS_BUSY_MASK (1 << 9) 112 113 /* eflags masks */ 114 #define CC_C 0x0001 115 #define CC_P 0x0004 116 #define CC_A 0x0010 117 #define CC_Z 0x0040 118 #define CC_S 0x0080 119 #define CC_O 0x0800 120 121 #define TF_SHIFT 8 122 #define IOPL_SHIFT 12 123 #define VM_SHIFT 17 124 125 #define TF_MASK 0x00000100 126 #define IF_MASK 0x00000200 127 #define DF_MASK 0x00000400 128 #define IOPL_MASK 0x00003000 129 #define NT_MASK 0x00004000 130 #define RF_MASK 0x00010000 131 #define VM_MASK 0x00020000 132 #define AC_MASK 0x00040000 133 #define VIF_MASK 0x00080000 134 #define VIP_MASK 0x00100000 135 #define ID_MASK 0x00200000 136 137 /* hidden flags - used internally by qemu to represent additional cpu 138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140 positions to ease oring with eflags. */ 141 /* current cpl */ 142 #define HF_CPL_SHIFT 0 143 /* true if hardware interrupts must be disabled for next instruction */ 144 #define HF_INHIBIT_IRQ_SHIFT 3 145 /* 16 or 32 segments */ 146 #define HF_CS32_SHIFT 4 147 #define HF_SS32_SHIFT 5 148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149 #define HF_ADDSEG_SHIFT 6 150 /* copy of CR0.PE (protected mode) */ 151 #define HF_PE_SHIFT 7 152 #define HF_TF_SHIFT 8 /* must be same as eflags */ 153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154 #define HF_EM_SHIFT 10 155 #define HF_TS_SHIFT 11 156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159 #define HF_RF_SHIFT 16 /* must be same as eflags */ 160 #define HF_VM_SHIFT 17 /* must be same as eflags */ 161 #define HF_AC_SHIFT 18 /* must be same as eflags */ 162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170 171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176 #define HF_PE_MASK (1 << HF_PE_SHIFT) 177 #define HF_TF_MASK (1 << HF_TF_SHIFT) 178 #define HF_MP_MASK (1 << HF_MP_SHIFT) 179 #define HF_EM_MASK (1 << HF_EM_SHIFT) 180 #define HF_TS_MASK (1 << HF_TS_SHIFT) 181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184 #define HF_RF_MASK (1 << HF_RF_SHIFT) 185 #define HF_VM_MASK (1 << HF_VM_SHIFT) 186 #define HF_AC_MASK (1 << HF_AC_SHIFT) 187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195 196 /* hflags2 */ 197 198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 206 207 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 208 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 209 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 210 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 211 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 212 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 213 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 214 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 215 216 #define CR0_PE_SHIFT 0 217 #define CR0_MP_SHIFT 1 218 219 #define CR0_PE_MASK (1U << 0) 220 #define CR0_MP_MASK (1U << 1) 221 #define CR0_EM_MASK (1U << 2) 222 #define CR0_TS_MASK (1U << 3) 223 #define CR0_ET_MASK (1U << 4) 224 #define CR0_NE_MASK (1U << 5) 225 #define CR0_WP_MASK (1U << 16) 226 #define CR0_AM_MASK (1U << 18) 227 #define CR0_PG_MASK (1U << 31) 228 229 #define CR4_VME_MASK (1U << 0) 230 #define CR4_PVI_MASK (1U << 1) 231 #define CR4_TSD_MASK (1U << 2) 232 #define CR4_DE_MASK (1U << 3) 233 #define CR4_PSE_MASK (1U << 4) 234 #define CR4_PAE_MASK (1U << 5) 235 #define CR4_MCE_MASK (1U << 6) 236 #define CR4_PGE_MASK (1U << 7) 237 #define CR4_PCE_MASK (1U << 8) 238 #define CR4_OSFXSR_SHIFT 9 239 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 240 #define CR4_OSXMMEXCPT_MASK (1U << 10) 241 #define CR4_LA57_MASK (1U << 12) 242 #define CR4_VMXE_MASK (1U << 13) 243 #define CR4_SMXE_MASK (1U << 14) 244 #define CR4_FSGSBASE_MASK (1U << 16) 245 #define CR4_PCIDE_MASK (1U << 17) 246 #define CR4_OSXSAVE_MASK (1U << 18) 247 #define CR4_SMEP_MASK (1U << 20) 248 #define CR4_SMAP_MASK (1U << 21) 249 #define CR4_PKE_MASK (1U << 22) 250 251 #define DR6_BD (1 << 13) 252 #define DR6_BS (1 << 14) 253 #define DR6_BT (1 << 15) 254 #define DR6_FIXED_1 0xffff0ff0 255 256 #define DR7_GD (1 << 13) 257 #define DR7_TYPE_SHIFT 16 258 #define DR7_LEN_SHIFT 18 259 #define DR7_FIXED_1 0x00000400 260 #define DR7_GLOBAL_BP_MASK 0xaa 261 #define DR7_LOCAL_BP_MASK 0x55 262 #define DR7_MAX_BP 4 263 #define DR7_TYPE_BP_INST 0x0 264 #define DR7_TYPE_DATA_WR 0x1 265 #define DR7_TYPE_IO_RW 0x2 266 #define DR7_TYPE_DATA_RW 0x3 267 268 #define PG_PRESENT_BIT 0 269 #define PG_RW_BIT 1 270 #define PG_USER_BIT 2 271 #define PG_PWT_BIT 3 272 #define PG_PCD_BIT 4 273 #define PG_ACCESSED_BIT 5 274 #define PG_DIRTY_BIT 6 275 #define PG_PSE_BIT 7 276 #define PG_GLOBAL_BIT 8 277 #define PG_PSE_PAT_BIT 12 278 #define PG_PKRU_BIT 59 279 #define PG_NX_BIT 63 280 281 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 282 #define PG_RW_MASK (1 << PG_RW_BIT) 283 #define PG_USER_MASK (1 << PG_USER_BIT) 284 #define PG_PWT_MASK (1 << PG_PWT_BIT) 285 #define PG_PCD_MASK (1 << PG_PCD_BIT) 286 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 287 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 288 #define PG_PSE_MASK (1 << PG_PSE_BIT) 289 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 290 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 291 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 292 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 293 #define PG_HI_USER_MASK 0x7ff0000000000000LL 294 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 295 #define PG_NX_MASK (1ULL << PG_NX_BIT) 296 297 #define PG_ERROR_W_BIT 1 298 299 #define PG_ERROR_P_MASK 0x01 300 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 301 #define PG_ERROR_U_MASK 0x04 302 #define PG_ERROR_RSVD_MASK 0x08 303 #define PG_ERROR_I_D_MASK 0x10 304 #define PG_ERROR_PK_MASK 0x20 305 306 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 307 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 308 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 309 310 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 311 #define MCE_BANKS_DEF 10 312 313 #define MCG_CAP_BANKS_MASK 0xff 314 315 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 316 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 317 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 318 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 319 320 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 321 322 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 323 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 324 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 325 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 326 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 327 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 328 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 329 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 330 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 331 332 /* MISC register defines */ 333 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 334 #define MCM_ADDR_LINEAR 1 /* linear address */ 335 #define MCM_ADDR_PHYS 2 /* physical address */ 336 #define MCM_ADDR_MEM 3 /* memory address */ 337 #define MCM_ADDR_GENERIC 7 /* generic */ 338 339 #define MSR_IA32_TSC 0x10 340 #define MSR_IA32_APICBASE 0x1b 341 #define MSR_IA32_APICBASE_BSP (1<<8) 342 #define MSR_IA32_APICBASE_ENABLE (1<<11) 343 #define MSR_IA32_APICBASE_EXTD (1 << 10) 344 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 345 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 346 #define MSR_TSC_ADJUST 0x0000003b 347 #define MSR_IA32_SPEC_CTRL 0x48 348 #define MSR_VIRT_SSBD 0xc001011f 349 #define MSR_IA32_PRED_CMD 0x49 350 #define MSR_IA32_UCODE_REV 0x8b 351 #define MSR_IA32_CORE_CAPABILITY 0xcf 352 353 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 354 #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 355 356 #define MSR_IA32_PERF_CAPABILITIES 0x345 357 358 #define MSR_IA32_TSX_CTRL 0x122 359 #define MSR_IA32_TSCDEADLINE 0x6e0 360 361 #define FEATURE_CONTROL_LOCKED (1<<0) 362 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 363 #define FEATURE_CONTROL_LMCE (1<<20) 364 365 #define MSR_P6_PERFCTR0 0xc1 366 367 #define MSR_IA32_SMBASE 0x9e 368 #define MSR_SMI_COUNT 0x34 369 #define MSR_MTRRcap 0xfe 370 #define MSR_MTRRcap_VCNT 8 371 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 372 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 373 374 #define MSR_IA32_SYSENTER_CS 0x174 375 #define MSR_IA32_SYSENTER_ESP 0x175 376 #define MSR_IA32_SYSENTER_EIP 0x176 377 378 #define MSR_MCG_CAP 0x179 379 #define MSR_MCG_STATUS 0x17a 380 #define MSR_MCG_CTL 0x17b 381 #define MSR_MCG_EXT_CTL 0x4d0 382 383 #define MSR_P6_EVNTSEL0 0x186 384 385 #define MSR_IA32_PERF_STATUS 0x198 386 387 #define MSR_IA32_MISC_ENABLE 0x1a0 388 /* Indicates good rep/movs microcode on some processors: */ 389 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 390 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 391 392 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 393 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 394 395 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 396 397 #define MSR_MTRRfix64K_00000 0x250 398 #define MSR_MTRRfix16K_80000 0x258 399 #define MSR_MTRRfix16K_A0000 0x259 400 #define MSR_MTRRfix4K_C0000 0x268 401 #define MSR_MTRRfix4K_C8000 0x269 402 #define MSR_MTRRfix4K_D0000 0x26a 403 #define MSR_MTRRfix4K_D8000 0x26b 404 #define MSR_MTRRfix4K_E0000 0x26c 405 #define MSR_MTRRfix4K_E8000 0x26d 406 #define MSR_MTRRfix4K_F0000 0x26e 407 #define MSR_MTRRfix4K_F8000 0x26f 408 409 #define MSR_PAT 0x277 410 411 #define MSR_MTRRdefType 0x2ff 412 413 #define MSR_CORE_PERF_FIXED_CTR0 0x309 414 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 415 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 416 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 417 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 418 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 419 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 420 421 #define MSR_MC0_CTL 0x400 422 #define MSR_MC0_STATUS 0x401 423 #define MSR_MC0_ADDR 0x402 424 #define MSR_MC0_MISC 0x403 425 426 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 427 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 428 #define MSR_IA32_RTIT_CTL 0x570 429 #define MSR_IA32_RTIT_STATUS 0x571 430 #define MSR_IA32_RTIT_CR3_MATCH 0x572 431 #define MSR_IA32_RTIT_ADDR0_A 0x580 432 #define MSR_IA32_RTIT_ADDR0_B 0x581 433 #define MSR_IA32_RTIT_ADDR1_A 0x582 434 #define MSR_IA32_RTIT_ADDR1_B 0x583 435 #define MSR_IA32_RTIT_ADDR2_A 0x584 436 #define MSR_IA32_RTIT_ADDR2_B 0x585 437 #define MSR_IA32_RTIT_ADDR3_A 0x586 438 #define MSR_IA32_RTIT_ADDR3_B 0x587 439 #define MAX_RTIT_ADDRS 8 440 441 #define MSR_EFER 0xc0000080 442 443 #define MSR_EFER_SCE (1 << 0) 444 #define MSR_EFER_LME (1 << 8) 445 #define MSR_EFER_LMA (1 << 10) 446 #define MSR_EFER_NXE (1 << 11) 447 #define MSR_EFER_SVME (1 << 12) 448 #define MSR_EFER_FFXSR (1 << 14) 449 450 #define MSR_STAR 0xc0000081 451 #define MSR_LSTAR 0xc0000082 452 #define MSR_CSTAR 0xc0000083 453 #define MSR_FMASK 0xc0000084 454 #define MSR_FSBASE 0xc0000100 455 #define MSR_GSBASE 0xc0000101 456 #define MSR_KERNELGSBASE 0xc0000102 457 #define MSR_TSC_AUX 0xc0000103 458 459 #define MSR_VM_HSAVE_PA 0xc0010117 460 461 #define MSR_IA32_BNDCFGS 0x00000d90 462 #define MSR_IA32_XSS 0x00000da0 463 #define MSR_IA32_UMWAIT_CONTROL 0xe1 464 465 #define MSR_IA32_VMX_BASIC 0x00000480 466 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 467 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 468 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 469 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 470 #define MSR_IA32_VMX_MISC 0x00000485 471 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 472 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 473 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 474 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 475 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 476 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 477 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 478 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 479 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 480 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 481 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 482 #define MSR_IA32_VMX_VMFUNC 0x00000491 483 484 #define XSTATE_FP_BIT 0 485 #define XSTATE_SSE_BIT 1 486 #define XSTATE_YMM_BIT 2 487 #define XSTATE_BNDREGS_BIT 3 488 #define XSTATE_BNDCSR_BIT 4 489 #define XSTATE_OPMASK_BIT 5 490 #define XSTATE_ZMM_Hi256_BIT 6 491 #define XSTATE_Hi16_ZMM_BIT 7 492 #define XSTATE_PKRU_BIT 9 493 494 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 495 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 496 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 497 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 498 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 499 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 500 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 501 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 502 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 503 504 /* CPUID feature words */ 505 typedef enum FeatureWord { 506 FEAT_1_EDX, /* CPUID[1].EDX */ 507 FEAT_1_ECX, /* CPUID[1].ECX */ 508 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 509 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 510 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 511 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 512 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 513 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 514 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 515 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 516 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 517 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 518 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 519 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 520 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 521 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 522 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ 523 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ 524 FEAT_SVM, /* CPUID[8000_000A].EDX */ 525 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 526 FEAT_6_EAX, /* CPUID[6].EAX */ 527 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 528 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 529 FEAT_ARCH_CAPABILITIES, 530 FEAT_CORE_CAPABILITY, 531 FEAT_PERF_CAPABILITIES, 532 FEAT_VMX_PROCBASED_CTLS, 533 FEAT_VMX_SECONDARY_CTLS, 534 FEAT_VMX_PINBASED_CTLS, 535 FEAT_VMX_EXIT_CTLS, 536 FEAT_VMX_ENTRY_CTLS, 537 FEAT_VMX_MISC, 538 FEAT_VMX_EPT_VPID_CAPS, 539 FEAT_VMX_BASIC, 540 FEAT_VMX_VMFUNC, 541 FEAT_14_0_ECX, 542 FEATURE_WORDS, 543 } FeatureWord; 544 545 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 546 547 /* cpuid_features bits */ 548 #define CPUID_FP87 (1U << 0) 549 #define CPUID_VME (1U << 1) 550 #define CPUID_DE (1U << 2) 551 #define CPUID_PSE (1U << 3) 552 #define CPUID_TSC (1U << 4) 553 #define CPUID_MSR (1U << 5) 554 #define CPUID_PAE (1U << 6) 555 #define CPUID_MCE (1U << 7) 556 #define CPUID_CX8 (1U << 8) 557 #define CPUID_APIC (1U << 9) 558 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 559 #define CPUID_MTRR (1U << 12) 560 #define CPUID_PGE (1U << 13) 561 #define CPUID_MCA (1U << 14) 562 #define CPUID_CMOV (1U << 15) 563 #define CPUID_PAT (1U << 16) 564 #define CPUID_PSE36 (1U << 17) 565 #define CPUID_PN (1U << 18) 566 #define CPUID_CLFLUSH (1U << 19) 567 #define CPUID_DTS (1U << 21) 568 #define CPUID_ACPI (1U << 22) 569 #define CPUID_MMX (1U << 23) 570 #define CPUID_FXSR (1U << 24) 571 #define CPUID_SSE (1U << 25) 572 #define CPUID_SSE2 (1U << 26) 573 #define CPUID_SS (1U << 27) 574 #define CPUID_HT (1U << 28) 575 #define CPUID_TM (1U << 29) 576 #define CPUID_IA64 (1U << 30) 577 #define CPUID_PBE (1U << 31) 578 579 #define CPUID_EXT_SSE3 (1U << 0) 580 #define CPUID_EXT_PCLMULQDQ (1U << 1) 581 #define CPUID_EXT_DTES64 (1U << 2) 582 #define CPUID_EXT_MONITOR (1U << 3) 583 #define CPUID_EXT_DSCPL (1U << 4) 584 #define CPUID_EXT_VMX (1U << 5) 585 #define CPUID_EXT_SMX (1U << 6) 586 #define CPUID_EXT_EST (1U << 7) 587 #define CPUID_EXT_TM2 (1U << 8) 588 #define CPUID_EXT_SSSE3 (1U << 9) 589 #define CPUID_EXT_CID (1U << 10) 590 #define CPUID_EXT_FMA (1U << 12) 591 #define CPUID_EXT_CX16 (1U << 13) 592 #define CPUID_EXT_XTPR (1U << 14) 593 #define CPUID_EXT_PDCM (1U << 15) 594 #define CPUID_EXT_PCID (1U << 17) 595 #define CPUID_EXT_DCA (1U << 18) 596 #define CPUID_EXT_SSE41 (1U << 19) 597 #define CPUID_EXT_SSE42 (1U << 20) 598 #define CPUID_EXT_X2APIC (1U << 21) 599 #define CPUID_EXT_MOVBE (1U << 22) 600 #define CPUID_EXT_POPCNT (1U << 23) 601 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 602 #define CPUID_EXT_AES (1U << 25) 603 #define CPUID_EXT_XSAVE (1U << 26) 604 #define CPUID_EXT_OSXSAVE (1U << 27) 605 #define CPUID_EXT_AVX (1U << 28) 606 #define CPUID_EXT_F16C (1U << 29) 607 #define CPUID_EXT_RDRAND (1U << 30) 608 #define CPUID_EXT_HYPERVISOR (1U << 31) 609 610 #define CPUID_EXT2_FPU (1U << 0) 611 #define CPUID_EXT2_VME (1U << 1) 612 #define CPUID_EXT2_DE (1U << 2) 613 #define CPUID_EXT2_PSE (1U << 3) 614 #define CPUID_EXT2_TSC (1U << 4) 615 #define CPUID_EXT2_MSR (1U << 5) 616 #define CPUID_EXT2_PAE (1U << 6) 617 #define CPUID_EXT2_MCE (1U << 7) 618 #define CPUID_EXT2_CX8 (1U << 8) 619 #define CPUID_EXT2_APIC (1U << 9) 620 #define CPUID_EXT2_SYSCALL (1U << 11) 621 #define CPUID_EXT2_MTRR (1U << 12) 622 #define CPUID_EXT2_PGE (1U << 13) 623 #define CPUID_EXT2_MCA (1U << 14) 624 #define CPUID_EXT2_CMOV (1U << 15) 625 #define CPUID_EXT2_PAT (1U << 16) 626 #define CPUID_EXT2_PSE36 (1U << 17) 627 #define CPUID_EXT2_MP (1U << 19) 628 #define CPUID_EXT2_NX (1U << 20) 629 #define CPUID_EXT2_MMXEXT (1U << 22) 630 #define CPUID_EXT2_MMX (1U << 23) 631 #define CPUID_EXT2_FXSR (1U << 24) 632 #define CPUID_EXT2_FFXSR (1U << 25) 633 #define CPUID_EXT2_PDPE1GB (1U << 26) 634 #define CPUID_EXT2_RDTSCP (1U << 27) 635 #define CPUID_EXT2_LM (1U << 29) 636 #define CPUID_EXT2_3DNOWEXT (1U << 30) 637 #define CPUID_EXT2_3DNOW (1U << 31) 638 639 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 640 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 641 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 642 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 643 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 644 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 645 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 646 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 647 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 648 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 649 650 #define CPUID_EXT3_LAHF_LM (1U << 0) 651 #define CPUID_EXT3_CMP_LEG (1U << 1) 652 #define CPUID_EXT3_SVM (1U << 2) 653 #define CPUID_EXT3_EXTAPIC (1U << 3) 654 #define CPUID_EXT3_CR8LEG (1U << 4) 655 #define CPUID_EXT3_ABM (1U << 5) 656 #define CPUID_EXT3_SSE4A (1U << 6) 657 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 658 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 659 #define CPUID_EXT3_OSVW (1U << 9) 660 #define CPUID_EXT3_IBS (1U << 10) 661 #define CPUID_EXT3_XOP (1U << 11) 662 #define CPUID_EXT3_SKINIT (1U << 12) 663 #define CPUID_EXT3_WDT (1U << 13) 664 #define CPUID_EXT3_LWP (1U << 15) 665 #define CPUID_EXT3_FMA4 (1U << 16) 666 #define CPUID_EXT3_TCE (1U << 17) 667 #define CPUID_EXT3_NODEID (1U << 19) 668 #define CPUID_EXT3_TBM (1U << 21) 669 #define CPUID_EXT3_TOPOEXT (1U << 22) 670 #define CPUID_EXT3_PERFCORE (1U << 23) 671 #define CPUID_EXT3_PERFNB (1U << 24) 672 673 #define CPUID_SVM_NPT (1U << 0) 674 #define CPUID_SVM_LBRV (1U << 1) 675 #define CPUID_SVM_SVMLOCK (1U << 2) 676 #define CPUID_SVM_NRIPSAVE (1U << 3) 677 #define CPUID_SVM_TSCSCALE (1U << 4) 678 #define CPUID_SVM_VMCBCLEAN (1U << 5) 679 #define CPUID_SVM_FLUSHASID (1U << 6) 680 #define CPUID_SVM_DECODEASSIST (1U << 7) 681 #define CPUID_SVM_PAUSEFILTER (1U << 10) 682 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 683 684 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 685 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 686 /* 1st Group of Advanced Bit Manipulation Extensions */ 687 #define CPUID_7_0_EBX_BMI1 (1U << 3) 688 /* Hardware Lock Elision */ 689 #define CPUID_7_0_EBX_HLE (1U << 4) 690 /* Intel Advanced Vector Extensions 2 */ 691 #define CPUID_7_0_EBX_AVX2 (1U << 5) 692 /* Supervisor-mode Execution Prevention */ 693 #define CPUID_7_0_EBX_SMEP (1U << 7) 694 /* 2nd Group of Advanced Bit Manipulation Extensions */ 695 #define CPUID_7_0_EBX_BMI2 (1U << 8) 696 /* Enhanced REP MOVSB/STOSB */ 697 #define CPUID_7_0_EBX_ERMS (1U << 9) 698 /* Invalidate Process-Context Identifier */ 699 #define CPUID_7_0_EBX_INVPCID (1U << 10) 700 /* Restricted Transactional Memory */ 701 #define CPUID_7_0_EBX_RTM (1U << 11) 702 /* Memory Protection Extension */ 703 #define CPUID_7_0_EBX_MPX (1U << 14) 704 /* AVX-512 Foundation */ 705 #define CPUID_7_0_EBX_AVX512F (1U << 16) 706 /* AVX-512 Doubleword & Quadword Instruction */ 707 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 708 /* Read Random SEED */ 709 #define CPUID_7_0_EBX_RDSEED (1U << 18) 710 /* ADCX and ADOX instructions */ 711 #define CPUID_7_0_EBX_ADX (1U << 19) 712 /* Supervisor Mode Access Prevention */ 713 #define CPUID_7_0_EBX_SMAP (1U << 20) 714 /* AVX-512 Integer Fused Multiply Add */ 715 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 716 /* Persistent Commit */ 717 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 718 /* Flush a Cache Line Optimized */ 719 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 720 /* Cache Line Write Back */ 721 #define CPUID_7_0_EBX_CLWB (1U << 24) 722 /* Intel Processor Trace */ 723 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 724 /* AVX-512 Prefetch */ 725 #define CPUID_7_0_EBX_AVX512PF (1U << 26) 726 /* AVX-512 Exponential and Reciprocal */ 727 #define CPUID_7_0_EBX_AVX512ER (1U << 27) 728 /* AVX-512 Conflict Detection */ 729 #define CPUID_7_0_EBX_AVX512CD (1U << 28) 730 /* SHA1/SHA256 Instruction Extensions */ 731 #define CPUID_7_0_EBX_SHA_NI (1U << 29) 732 /* AVX-512 Byte and Word Instructions */ 733 #define CPUID_7_0_EBX_AVX512BW (1U << 30) 734 /* AVX-512 Vector Length Extensions */ 735 #define CPUID_7_0_EBX_AVX512VL (1U << 31) 736 737 /* AVX-512 Vector Byte Manipulation Instruction */ 738 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 739 /* User-Mode Instruction Prevention */ 740 #define CPUID_7_0_ECX_UMIP (1U << 2) 741 /* Protection Keys for User-mode Pages */ 742 #define CPUID_7_0_ECX_PKU (1U << 3) 743 /* OS Enable Protection Keys */ 744 #define CPUID_7_0_ECX_OSPKE (1U << 4) 745 /* UMONITOR/UMWAIT/TPAUSE Instructions */ 746 #define CPUID_7_0_ECX_WAITPKG (1U << 5) 747 /* Additional AVX-512 Vector Byte Manipulation Instruction */ 748 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 749 /* Galois Field New Instructions */ 750 #define CPUID_7_0_ECX_GFNI (1U << 8) 751 /* Vector AES Instructions */ 752 #define CPUID_7_0_ECX_VAES (1U << 9) 753 /* Carry-Less Multiplication Quadword */ 754 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 755 /* Vector Neural Network Instructions */ 756 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 757 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 758 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 759 /* POPCNT for vectors of DW/QW */ 760 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 761 /* 5-level Page Tables */ 762 #define CPUID_7_0_ECX_LA57 (1U << 16) 763 /* Read Processor ID */ 764 #define CPUID_7_0_ECX_RDPID (1U << 22) 765 /* Cache Line Demote Instruction */ 766 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 767 /* Move Doubleword as Direct Store Instruction */ 768 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 769 /* Move 64 Bytes as Direct Store Instruction */ 770 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 771 772 /* AVX512 Neural Network Instructions */ 773 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 774 /* AVX512 Multiply Accumulation Single Precision */ 775 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 776 /* Fast Short Rep Mov */ 777 #define CPUID_7_0_EDX_FSRM (1U << 4) 778 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 779 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 780 /* SERIALIZE instruction */ 781 #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 782 /* TSX Suspend Load Address Tracking instruction */ 783 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 784 /* AVX512_FP16 instruction */ 785 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) 786 /* Speculation Control */ 787 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 788 /* Single Thread Indirect Branch Predictors */ 789 #define CPUID_7_0_EDX_STIBP (1U << 27) 790 /* Arch Capabilities */ 791 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 792 /* Core Capability */ 793 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 794 /* Speculative Store Bypass Disable */ 795 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 796 797 /* AVX512 BFloat16 Instruction */ 798 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 799 800 /* Packets which contain IP payload have LIP values */ 801 #define CPUID_14_0_ECX_LIP (1U << 31) 802 803 /* CLZERO instruction */ 804 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 805 /* Always save/restore FP error pointers */ 806 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 807 /* Write back and do not invalidate cache */ 808 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 809 /* Indirect Branch Prediction Barrier */ 810 #define CPUID_8000_0008_EBX_IBPB (1U << 12) 811 /* Single Thread Indirect Branch Predictors */ 812 #define CPUID_8000_0008_EBX_STIBP (1U << 15) 813 814 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 815 #define CPUID_XSAVE_XSAVEC (1U << 1) 816 #define CPUID_XSAVE_XGETBV1 (1U << 2) 817 #define CPUID_XSAVE_XSAVES (1U << 3) 818 819 #define CPUID_6_EAX_ARAT (1U << 2) 820 821 /* CPUID[0x80000007].EDX flags: */ 822 #define CPUID_APM_INVTSC (1U << 8) 823 824 #define CPUID_VENDOR_SZ 12 825 826 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 827 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 828 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 829 #define CPUID_VENDOR_INTEL "GenuineIntel" 830 831 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 832 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 833 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 834 #define CPUID_VENDOR_AMD "AuthenticAMD" 835 836 #define CPUID_VENDOR_VIA "CentaurHauls" 837 838 #define CPUID_VENDOR_HYGON "HygonGenuine" 839 840 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 841 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 842 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 843 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 844 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 845 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 846 847 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 848 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 849 850 /* CPUID[0xB].ECX level types */ 851 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 852 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 853 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 854 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 855 856 /* MSR Feature Bits */ 857 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 858 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 859 #define MSR_ARCH_CAP_RSBA (1U << 2) 860 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 861 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 862 #define MSR_ARCH_CAP_MDS_NO (1U << 5) 863 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 864 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 865 #define MSR_ARCH_CAP_TAA_NO (1U << 8) 866 867 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 868 869 /* VMX MSR features */ 870 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 871 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 872 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 873 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 874 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 875 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 876 877 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 878 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 879 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 880 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 881 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 882 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 883 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 884 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 885 886 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 887 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 888 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 889 #define MSR_VMX_EPT_UC (1ULL << 8) 890 #define MSR_VMX_EPT_WB (1ULL << 14) 891 #define MSR_VMX_EPT_2MB (1ULL << 16) 892 #define MSR_VMX_EPT_1GB (1ULL << 17) 893 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 894 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 895 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 896 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 897 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 898 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 899 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 900 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 901 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 902 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 903 904 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 905 906 907 /* VMX controls */ 908 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 909 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 910 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 911 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 912 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 913 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 914 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 915 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 916 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 917 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 918 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 919 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 920 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 921 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 922 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 923 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 924 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 925 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 926 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 927 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 928 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 929 930 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 931 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 932 #define VMX_SECONDARY_EXEC_DESC 0x00000004 933 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 934 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 935 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 936 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 937 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 938 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 939 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 940 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 941 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 942 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 943 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 944 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 945 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 946 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 947 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 948 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 949 950 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 951 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 952 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 953 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 954 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 955 956 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 957 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 958 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 959 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 960 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 961 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 962 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 963 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 964 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 965 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 966 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 967 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 968 969 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 970 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 971 #define VMX_VM_ENTRY_SMM 0x00000400 972 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 973 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 974 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 975 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 976 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 977 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 978 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 979 980 /* Supported Hyper-V Enlightenments */ 981 #define HYPERV_FEAT_RELAXED 0 982 #define HYPERV_FEAT_VAPIC 1 983 #define HYPERV_FEAT_TIME 2 984 #define HYPERV_FEAT_CRASH 3 985 #define HYPERV_FEAT_RESET 4 986 #define HYPERV_FEAT_VPINDEX 5 987 #define HYPERV_FEAT_RUNTIME 6 988 #define HYPERV_FEAT_SYNIC 7 989 #define HYPERV_FEAT_STIMER 8 990 #define HYPERV_FEAT_FREQUENCIES 9 991 #define HYPERV_FEAT_REENLIGHTENMENT 10 992 #define HYPERV_FEAT_TLBFLUSH 11 993 #define HYPERV_FEAT_EVMCS 12 994 #define HYPERV_FEAT_IPI 13 995 #define HYPERV_FEAT_STIMER_DIRECT 14 996 997 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY 998 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF 999 #endif 1000 1001 #define EXCP00_DIVZ 0 1002 #define EXCP01_DB 1 1003 #define EXCP02_NMI 2 1004 #define EXCP03_INT3 3 1005 #define EXCP04_INTO 4 1006 #define EXCP05_BOUND 5 1007 #define EXCP06_ILLOP 6 1008 #define EXCP07_PREX 7 1009 #define EXCP08_DBLE 8 1010 #define EXCP09_XERR 9 1011 #define EXCP0A_TSS 10 1012 #define EXCP0B_NOSEG 11 1013 #define EXCP0C_STACK 12 1014 #define EXCP0D_GPF 13 1015 #define EXCP0E_PAGE 14 1016 #define EXCP10_COPR 16 1017 #define EXCP11_ALGN 17 1018 #define EXCP12_MCHK 18 1019 1020 #define EXCP_VMEXIT 0x100 /* only for system emulation */ 1021 #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1022 #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1023 1024 /* i386-specific interrupt pending bits. */ 1025 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1026 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1027 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1028 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1029 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1030 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1031 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1032 1033 /* Use a clearer name for this. */ 1034 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1035 1036 /* Instead of computing the condition codes after each x86 instruction, 1037 * QEMU just stores one operand (called CC_SRC), the result 1038 * (called CC_DST) and the type of operation (called CC_OP). When the 1039 * condition codes are needed, the condition codes can be calculated 1040 * using this information. Condition codes are not generated if they 1041 * are only needed for conditional branches. 1042 */ 1043 typedef enum { 1044 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1045 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1046 1047 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1048 CC_OP_MULW, 1049 CC_OP_MULL, 1050 CC_OP_MULQ, 1051 1052 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1053 CC_OP_ADDW, 1054 CC_OP_ADDL, 1055 CC_OP_ADDQ, 1056 1057 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1058 CC_OP_ADCW, 1059 CC_OP_ADCL, 1060 CC_OP_ADCQ, 1061 1062 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1063 CC_OP_SUBW, 1064 CC_OP_SUBL, 1065 CC_OP_SUBQ, 1066 1067 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1068 CC_OP_SBBW, 1069 CC_OP_SBBL, 1070 CC_OP_SBBQ, 1071 1072 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1073 CC_OP_LOGICW, 1074 CC_OP_LOGICL, 1075 CC_OP_LOGICQ, 1076 1077 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1078 CC_OP_INCW, 1079 CC_OP_INCL, 1080 CC_OP_INCQ, 1081 1082 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1083 CC_OP_DECW, 1084 CC_OP_DECL, 1085 CC_OP_DECQ, 1086 1087 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1088 CC_OP_SHLW, 1089 CC_OP_SHLL, 1090 CC_OP_SHLQ, 1091 1092 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1093 CC_OP_SARW, 1094 CC_OP_SARL, 1095 CC_OP_SARQ, 1096 1097 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1098 CC_OP_BMILGW, 1099 CC_OP_BMILGL, 1100 CC_OP_BMILGQ, 1101 1102 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1103 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1104 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1105 1106 CC_OP_CLR, /* Z set, all other flags clear. */ 1107 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1108 1109 CC_OP_NB, 1110 } CCOp; 1111 1112 typedef struct SegmentCache { 1113 uint32_t selector; 1114 target_ulong base; 1115 uint32_t limit; 1116 uint32_t flags; 1117 } SegmentCache; 1118 1119 #define MMREG_UNION(n, bits) \ 1120 union n { \ 1121 uint8_t _b_##n[(bits)/8]; \ 1122 uint16_t _w_##n[(bits)/16]; \ 1123 uint32_t _l_##n[(bits)/32]; \ 1124 uint64_t _q_##n[(bits)/64]; \ 1125 float32 _s_##n[(bits)/32]; \ 1126 float64 _d_##n[(bits)/64]; \ 1127 } 1128 1129 typedef union { 1130 uint8_t _b[16]; 1131 uint16_t _w[8]; 1132 uint32_t _l[4]; 1133 uint64_t _q[2]; 1134 } XMMReg; 1135 1136 typedef union { 1137 uint8_t _b[32]; 1138 uint16_t _w[16]; 1139 uint32_t _l[8]; 1140 uint64_t _q[4]; 1141 } YMMReg; 1142 1143 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1144 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1145 1146 typedef struct BNDReg { 1147 uint64_t lb; 1148 uint64_t ub; 1149 } BNDReg; 1150 1151 typedef struct BNDCSReg { 1152 uint64_t cfgu; 1153 uint64_t sts; 1154 } BNDCSReg; 1155 1156 #define BNDCFG_ENABLE 1ULL 1157 #define BNDCFG_BNDPRESERVE 2ULL 1158 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1159 1160 #ifdef HOST_WORDS_BIGENDIAN 1161 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1162 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1163 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1164 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1165 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1166 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1167 1168 #define MMX_B(n) _b_MMXReg[7 - (n)] 1169 #define MMX_W(n) _w_MMXReg[3 - (n)] 1170 #define MMX_L(n) _l_MMXReg[1 - (n)] 1171 #define MMX_S(n) _s_MMXReg[1 - (n)] 1172 #else 1173 #define ZMM_B(n) _b_ZMMReg[n] 1174 #define ZMM_W(n) _w_ZMMReg[n] 1175 #define ZMM_L(n) _l_ZMMReg[n] 1176 #define ZMM_S(n) _s_ZMMReg[n] 1177 #define ZMM_Q(n) _q_ZMMReg[n] 1178 #define ZMM_D(n) _d_ZMMReg[n] 1179 1180 #define MMX_B(n) _b_MMXReg[n] 1181 #define MMX_W(n) _w_MMXReg[n] 1182 #define MMX_L(n) _l_MMXReg[n] 1183 #define MMX_S(n) _s_MMXReg[n] 1184 #endif 1185 #define MMX_Q(n) _q_MMXReg[n] 1186 1187 typedef union { 1188 floatx80 d __attribute__((aligned(16))); 1189 MMXReg mmx; 1190 } FPReg; 1191 1192 typedef struct { 1193 uint64_t base; 1194 uint64_t mask; 1195 } MTRRVar; 1196 1197 #define CPU_NB_REGS64 16 1198 #define CPU_NB_REGS32 8 1199 1200 #ifdef TARGET_X86_64 1201 #define CPU_NB_REGS CPU_NB_REGS64 1202 #else 1203 #define CPU_NB_REGS CPU_NB_REGS32 1204 #endif 1205 1206 #define MAX_FIXED_COUNTERS 3 1207 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1208 1209 #define TARGET_INSN_START_EXTRA_WORDS 1 1210 1211 #define NB_OPMASK_REGS 8 1212 1213 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1214 * that APIC ID hasn't been set yet 1215 */ 1216 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1217 1218 typedef union X86LegacyXSaveArea { 1219 struct { 1220 uint16_t fcw; 1221 uint16_t fsw; 1222 uint8_t ftw; 1223 uint8_t reserved; 1224 uint16_t fpop; 1225 uint64_t fpip; 1226 uint64_t fpdp; 1227 uint32_t mxcsr; 1228 uint32_t mxcsr_mask; 1229 FPReg fpregs[8]; 1230 uint8_t xmm_regs[16][16]; 1231 }; 1232 uint8_t data[512]; 1233 } X86LegacyXSaveArea; 1234 1235 typedef struct X86XSaveHeader { 1236 uint64_t xstate_bv; 1237 uint64_t xcomp_bv; 1238 uint64_t reserve0; 1239 uint8_t reserved[40]; 1240 } X86XSaveHeader; 1241 1242 /* Ext. save area 2: AVX State */ 1243 typedef struct XSaveAVX { 1244 uint8_t ymmh[16][16]; 1245 } XSaveAVX; 1246 1247 /* Ext. save area 3: BNDREG */ 1248 typedef struct XSaveBNDREG { 1249 BNDReg bnd_regs[4]; 1250 } XSaveBNDREG; 1251 1252 /* Ext. save area 4: BNDCSR */ 1253 typedef union XSaveBNDCSR { 1254 BNDCSReg bndcsr; 1255 uint8_t data[64]; 1256 } XSaveBNDCSR; 1257 1258 /* Ext. save area 5: Opmask */ 1259 typedef struct XSaveOpmask { 1260 uint64_t opmask_regs[NB_OPMASK_REGS]; 1261 } XSaveOpmask; 1262 1263 /* Ext. save area 6: ZMM_Hi256 */ 1264 typedef struct XSaveZMM_Hi256 { 1265 uint8_t zmm_hi256[16][32]; 1266 } XSaveZMM_Hi256; 1267 1268 /* Ext. save area 7: Hi16_ZMM */ 1269 typedef struct XSaveHi16_ZMM { 1270 uint8_t hi16_zmm[16][64]; 1271 } XSaveHi16_ZMM; 1272 1273 /* Ext. save area 9: PKRU state */ 1274 typedef struct XSavePKRU { 1275 uint32_t pkru; 1276 uint32_t padding; 1277 } XSavePKRU; 1278 1279 typedef struct X86XSaveArea { 1280 X86LegacyXSaveArea legacy; 1281 X86XSaveHeader header; 1282 1283 /* Extended save areas: */ 1284 1285 /* AVX State: */ 1286 XSaveAVX avx_state; 1287 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1288 /* MPX State: */ 1289 XSaveBNDREG bndreg_state; 1290 XSaveBNDCSR bndcsr_state; 1291 /* AVX-512 State: */ 1292 XSaveOpmask opmask_state; 1293 XSaveZMM_Hi256 zmm_hi256_state; 1294 XSaveHi16_ZMM hi16_zmm_state; 1295 /* PKRU State: */ 1296 XSavePKRU pkru_state; 1297 } X86XSaveArea; 1298 1299 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1300 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1301 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1302 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1303 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1304 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1305 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1306 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1307 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1308 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1309 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1310 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1311 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1312 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1313 1314 typedef enum TPRAccess { 1315 TPR_ACCESS_READ, 1316 TPR_ACCESS_WRITE, 1317 } TPRAccess; 1318 1319 /* Cache information data structures: */ 1320 1321 enum CacheType { 1322 DATA_CACHE, 1323 INSTRUCTION_CACHE, 1324 UNIFIED_CACHE 1325 }; 1326 1327 typedef struct CPUCacheInfo { 1328 enum CacheType type; 1329 uint8_t level; 1330 /* Size in bytes */ 1331 uint32_t size; 1332 /* Line size, in bytes */ 1333 uint16_t line_size; 1334 /* 1335 * Associativity. 1336 * Note: representation of fully-associative caches is not implemented 1337 */ 1338 uint8_t associativity; 1339 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1340 uint8_t partitions; 1341 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1342 uint32_t sets; 1343 /* 1344 * Lines per tag. 1345 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1346 * (Is this synonym to @partitions?) 1347 */ 1348 uint8_t lines_per_tag; 1349 1350 /* Self-initializing cache */ 1351 bool self_init; 1352 /* 1353 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1354 * non-originating threads sharing this cache. 1355 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1356 */ 1357 bool no_invd_sharing; 1358 /* 1359 * Cache is inclusive of lower cache levels. 1360 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1361 */ 1362 bool inclusive; 1363 /* 1364 * A complex function is used to index the cache, potentially using all 1365 * address bits. CPUID[4].EDX[bit 2]. 1366 */ 1367 bool complex_indexing; 1368 } CPUCacheInfo; 1369 1370 1371 typedef struct CPUCaches { 1372 CPUCacheInfo *l1d_cache; 1373 CPUCacheInfo *l1i_cache; 1374 CPUCacheInfo *l2_cache; 1375 CPUCacheInfo *l3_cache; 1376 } CPUCaches; 1377 1378 typedef struct HVFX86LazyFlags { 1379 target_ulong result; 1380 target_ulong auxbits; 1381 } HVFX86LazyFlags; 1382 1383 typedef struct CPUX86State { 1384 /* standard registers */ 1385 target_ulong regs[CPU_NB_REGS]; 1386 target_ulong eip; 1387 target_ulong eflags; /* eflags register. During CPU emulation, CC 1388 flags and DF are set to zero because they are 1389 stored elsewhere */ 1390 1391 /* emulator internal eflags handling */ 1392 target_ulong cc_dst; 1393 target_ulong cc_src; 1394 target_ulong cc_src2; 1395 uint32_t cc_op; 1396 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1397 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1398 are known at translation time. */ 1399 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1400 1401 /* segments */ 1402 SegmentCache segs[6]; /* selector values */ 1403 SegmentCache ldt; 1404 SegmentCache tr; 1405 SegmentCache gdt; /* only base and limit are used */ 1406 SegmentCache idt; /* only base and limit are used */ 1407 1408 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1409 int32_t a20_mask; 1410 1411 BNDReg bnd_regs[4]; 1412 BNDCSReg bndcs_regs; 1413 uint64_t msr_bndcfgs; 1414 uint64_t efer; 1415 1416 /* Beginning of state preserved by INIT (dummy marker). */ 1417 struct {} start_init_save; 1418 1419 /* FPU state */ 1420 unsigned int fpstt; /* top of stack index */ 1421 uint16_t fpus; 1422 uint16_t fpuc; 1423 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1424 FPReg fpregs[8]; 1425 /* KVM-only so far */ 1426 uint16_t fpop; 1427 uint64_t fpip; 1428 uint64_t fpdp; 1429 1430 /* emulator internal variables */ 1431 float_status fp_status; 1432 floatx80 ft0; 1433 1434 float_status mmx_status; /* for 3DNow! float ops */ 1435 float_status sse_status; 1436 uint32_t mxcsr; 1437 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1438 ZMMReg xmm_t0; 1439 MMXReg mmx_t0; 1440 1441 XMMReg ymmh_regs[CPU_NB_REGS]; 1442 1443 uint64_t opmask_regs[NB_OPMASK_REGS]; 1444 YMMReg zmmh_regs[CPU_NB_REGS]; 1445 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1446 1447 /* sysenter registers */ 1448 uint32_t sysenter_cs; 1449 target_ulong sysenter_esp; 1450 target_ulong sysenter_eip; 1451 uint64_t star; 1452 1453 uint64_t vm_hsave; 1454 1455 #ifdef TARGET_X86_64 1456 target_ulong lstar; 1457 target_ulong cstar; 1458 target_ulong fmask; 1459 target_ulong kernelgsbase; 1460 #endif 1461 1462 uint64_t tsc; 1463 uint64_t tsc_adjust; 1464 uint64_t tsc_deadline; 1465 uint64_t tsc_aux; 1466 1467 uint64_t xcr0; 1468 1469 uint64_t mcg_status; 1470 uint64_t msr_ia32_misc_enable; 1471 uint64_t msr_ia32_feature_control; 1472 1473 uint64_t msr_fixed_ctr_ctrl; 1474 uint64_t msr_global_ctrl; 1475 uint64_t msr_global_status; 1476 uint64_t msr_global_ovf_ctrl; 1477 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1478 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1479 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1480 1481 uint64_t pat; 1482 uint32_t smbase; 1483 uint64_t msr_smi_count; 1484 1485 uint32_t pkru; 1486 uint32_t tsx_ctrl; 1487 1488 uint64_t spec_ctrl; 1489 uint64_t virt_ssbd; 1490 1491 /* End of state preserved by INIT (dummy marker). */ 1492 struct {} end_init_save; 1493 1494 uint64_t system_time_msr; 1495 uint64_t wall_clock_msr; 1496 uint64_t steal_time_msr; 1497 uint64_t async_pf_en_msr; 1498 uint64_t async_pf_int_msr; 1499 uint64_t pv_eoi_en_msr; 1500 uint64_t poll_control_msr; 1501 1502 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1503 uint64_t msr_hv_hypercall; 1504 uint64_t msr_hv_guest_os_id; 1505 uint64_t msr_hv_tsc; 1506 1507 /* Per-VCPU HV MSRs */ 1508 uint64_t msr_hv_vapic; 1509 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1510 uint64_t msr_hv_runtime; 1511 uint64_t msr_hv_synic_control; 1512 uint64_t msr_hv_synic_evt_page; 1513 uint64_t msr_hv_synic_msg_page; 1514 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1515 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1516 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1517 uint64_t msr_hv_reenlightenment_control; 1518 uint64_t msr_hv_tsc_emulation_control; 1519 uint64_t msr_hv_tsc_emulation_status; 1520 1521 uint64_t msr_rtit_ctrl; 1522 uint64_t msr_rtit_status; 1523 uint64_t msr_rtit_output_base; 1524 uint64_t msr_rtit_output_mask; 1525 uint64_t msr_rtit_cr3_match; 1526 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1527 1528 /* exception/interrupt handling */ 1529 int error_code; 1530 int exception_is_int; 1531 target_ulong exception_next_eip; 1532 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1533 union { 1534 struct CPUBreakpoint *cpu_breakpoint[4]; 1535 struct CPUWatchpoint *cpu_watchpoint[4]; 1536 }; /* break/watchpoints for dr[0..3] */ 1537 int old_exception; /* exception in flight */ 1538 1539 uint64_t vm_vmcb; 1540 uint64_t tsc_offset; 1541 uint64_t intercept; 1542 uint16_t intercept_cr_read; 1543 uint16_t intercept_cr_write; 1544 uint16_t intercept_dr_read; 1545 uint16_t intercept_dr_write; 1546 uint32_t intercept_exceptions; 1547 uint64_t nested_cr3; 1548 uint32_t nested_pg_mode; 1549 uint8_t v_tpr; 1550 1551 /* KVM states, automatically cleared on reset */ 1552 uint8_t nmi_injected; 1553 uint8_t nmi_pending; 1554 1555 uintptr_t retaddr; 1556 1557 /* Fields up to this point are cleared by a CPU reset */ 1558 struct {} end_reset_fields; 1559 1560 /* Fields after this point are preserved across CPU reset. */ 1561 1562 /* processor features (e.g. for CPUID insn) */ 1563 /* Minimum cpuid leaf 7 value */ 1564 uint32_t cpuid_level_func7; 1565 /* Actual cpuid leaf 7 value */ 1566 uint32_t cpuid_min_level_func7; 1567 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1568 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1569 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1570 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1571 /* Actual level/xlevel/xlevel2 value: */ 1572 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1573 uint32_t cpuid_vendor1; 1574 uint32_t cpuid_vendor2; 1575 uint32_t cpuid_vendor3; 1576 uint32_t cpuid_version; 1577 FeatureWordArray features; 1578 /* Features that were explicitly enabled/disabled */ 1579 FeatureWordArray user_features; 1580 uint32_t cpuid_model[12]; 1581 /* Cache information for CPUID. When legacy-cache=on, the cache data 1582 * on each CPUID leaf will be different, because we keep compatibility 1583 * with old QEMU versions. 1584 */ 1585 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1586 1587 /* MTRRs */ 1588 uint64_t mtrr_fixed[11]; 1589 uint64_t mtrr_deftype; 1590 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1591 1592 /* For KVM */ 1593 uint32_t mp_state; 1594 int32_t exception_nr; 1595 int32_t interrupt_injected; 1596 uint8_t soft_interrupt; 1597 uint8_t exception_pending; 1598 uint8_t exception_injected; 1599 uint8_t has_error_code; 1600 uint8_t exception_has_payload; 1601 uint64_t exception_payload; 1602 uint32_t ins_len; 1603 uint32_t sipi_vector; 1604 bool tsc_valid; 1605 int64_t tsc_khz; 1606 int64_t user_tsc_khz; /* for sanity check only */ 1607 uint64_t apic_bus_freq; 1608 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1609 void *xsave_buf; 1610 #endif 1611 #if defined(CONFIG_KVM) 1612 struct kvm_nested_state *nested_state; 1613 #endif 1614 #if defined(CONFIG_HVF) 1615 HVFX86LazyFlags hvf_lflags; 1616 void *hvf_mmio_buf; 1617 #endif 1618 1619 uint64_t mcg_cap; 1620 uint64_t mcg_ctl; 1621 uint64_t mcg_ext_ctl; 1622 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1623 uint64_t xstate_bv; 1624 1625 /* vmstate */ 1626 uint16_t fpus_vmstate; 1627 uint16_t fptag_vmstate; 1628 uint16_t fpregs_format_vmstate; 1629 1630 uint64_t xss; 1631 uint32_t umwait; 1632 1633 TPRAccess tpr_access_type; 1634 1635 unsigned nr_dies; 1636 } CPUX86State; 1637 1638 struct kvm_msrs; 1639 1640 /** 1641 * X86CPU: 1642 * @env: #CPUX86State 1643 * @migratable: If set, only migratable flags will be accepted when "enforce" 1644 * mode is used, and only migratable flags will be included in the "host" 1645 * CPU model. 1646 * 1647 * An x86 CPU. 1648 */ 1649 struct X86CPU { 1650 /*< private >*/ 1651 CPUState parent_obj; 1652 /*< public >*/ 1653 1654 CPUNegativeOffsetState neg; 1655 CPUX86State env; 1656 VMChangeStateEntry *vmsentry; 1657 1658 uint64_t ucode_rev; 1659 1660 uint32_t hyperv_spinlock_attempts; 1661 char *hyperv_vendor; 1662 bool hyperv_synic_kvm_only; 1663 uint64_t hyperv_features; 1664 bool hyperv_passthrough; 1665 OnOffAuto hyperv_no_nonarch_cs; 1666 uint32_t hyperv_vendor_id[3]; 1667 uint32_t hyperv_interface_id[4]; 1668 uint32_t hyperv_version_id[4]; 1669 uint32_t hyperv_limits[3]; 1670 1671 bool check_cpuid; 1672 bool enforce_cpuid; 1673 /* 1674 * Force features to be enabled even if the host doesn't support them. 1675 * This is dangerous and should be done only for testing CPUID 1676 * compatibility. 1677 */ 1678 bool force_features; 1679 bool expose_kvm; 1680 bool expose_tcg; 1681 bool migratable; 1682 bool migrate_smi_count; 1683 bool max_features; /* Enable all supported features automatically */ 1684 uint32_t apic_id; 1685 1686 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1687 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1688 bool vmware_cpuid_freq; 1689 1690 /* if true the CPUID code directly forward host cache leaves to the guest */ 1691 bool cache_info_passthrough; 1692 1693 /* if true the CPUID code directly forwards 1694 * host monitor/mwait leaves to the guest */ 1695 struct { 1696 uint32_t eax; 1697 uint32_t ebx; 1698 uint32_t ecx; 1699 uint32_t edx; 1700 } mwait; 1701 1702 /* Features that were filtered out because of missing host capabilities */ 1703 FeatureWordArray filtered_features; 1704 1705 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1706 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1707 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1708 * capabilities) directly to the guest. 1709 */ 1710 bool enable_pmu; 1711 1712 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1713 * disabled by default to avoid breaking migration between QEMU with 1714 * different LMCE configurations. 1715 */ 1716 bool enable_lmce; 1717 1718 /* Compatibility bits for old machine types. 1719 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1720 * socket share an virtual l3 cache. 1721 */ 1722 bool enable_l3_cache; 1723 1724 /* Compatibility bits for old machine types. 1725 * If true present the old cache topology information 1726 */ 1727 bool legacy_cache; 1728 1729 /* Compatibility bits for old machine types: */ 1730 bool enable_cpuid_0xb; 1731 1732 /* Enable auto level-increase for all CPUID leaves */ 1733 bool full_cpuid_auto_level; 1734 1735 /* Enable auto level-increase for Intel Processor Trace leave */ 1736 bool intel_pt_auto_level; 1737 1738 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1739 bool fill_mtrr_mask; 1740 1741 /* if true override the phys_bits value with a value read from the host */ 1742 bool host_phys_bits; 1743 1744 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1745 uint8_t host_phys_bits_limit; 1746 1747 /* Stop SMI delivery for migration compatibility with old machines */ 1748 bool kvm_no_smi_migration; 1749 1750 /* Number of physical address bits supported */ 1751 uint32_t phys_bits; 1752 1753 /* in order to simplify APIC support, we leave this pointer to the 1754 user */ 1755 struct DeviceState *apic_state; 1756 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1757 Notifier machine_done; 1758 1759 struct kvm_msrs *kvm_msr_buf; 1760 1761 int32_t node_id; /* NUMA node this CPU belongs to */ 1762 int32_t socket_id; 1763 int32_t die_id; 1764 int32_t core_id; 1765 int32_t thread_id; 1766 1767 int32_t hv_max_vps; 1768 }; 1769 1770 1771 #ifndef CONFIG_USER_ONLY 1772 extern VMStateDescription vmstate_x86_cpu; 1773 #endif 1774 1775 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1776 1777 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1778 int cpuid, void *opaque); 1779 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1780 int cpuid, void *opaque); 1781 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1782 void *opaque); 1783 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1784 void *opaque); 1785 1786 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1787 Error **errp); 1788 1789 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1790 1791 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1792 MemTxAttrs *attrs); 1793 1794 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1795 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1796 1797 void x86_cpu_list(void); 1798 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1799 1800 int cpu_get_pic_interrupt(CPUX86State *s); 1801 /* MSDOS compatibility mode FPU exception support */ 1802 void x86_register_ferr_irq(qemu_irq irq); 1803 void cpu_set_ignne(void); 1804 /* mpx_helper.c */ 1805 void cpu_sync_bndcs_hflags(CPUX86State *env); 1806 1807 /* this function must always be used to load data in the segment 1808 cache: it synchronizes the hflags with the segment cache values */ 1809 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1810 int seg_reg, unsigned int selector, 1811 target_ulong base, 1812 unsigned int limit, 1813 unsigned int flags) 1814 { 1815 SegmentCache *sc; 1816 unsigned int new_hflags; 1817 1818 sc = &env->segs[seg_reg]; 1819 sc->selector = selector; 1820 sc->base = base; 1821 sc->limit = limit; 1822 sc->flags = flags; 1823 1824 /* update the hidden flags */ 1825 { 1826 if (seg_reg == R_CS) { 1827 #ifdef TARGET_X86_64 1828 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1829 /* long mode */ 1830 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1831 env->hflags &= ~(HF_ADDSEG_MASK); 1832 } else 1833 #endif 1834 { 1835 /* legacy / compatibility case */ 1836 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1837 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1838 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1839 new_hflags; 1840 } 1841 } 1842 if (seg_reg == R_SS) { 1843 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1844 #if HF_CPL_MASK != 3 1845 #error HF_CPL_MASK is hardcoded 1846 #endif 1847 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1848 /* Possibly switch between BNDCFGS and BNDCFGU */ 1849 cpu_sync_bndcs_hflags(env); 1850 } 1851 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1852 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1853 if (env->hflags & HF_CS64_MASK) { 1854 /* zero base assumed for DS, ES and SS in long mode */ 1855 } else if (!(env->cr[0] & CR0_PE_MASK) || 1856 (env->eflags & VM_MASK) || 1857 !(env->hflags & HF_CS32_MASK)) { 1858 /* XXX: try to avoid this test. The problem comes from the 1859 fact that is real mode or vm86 mode we only modify the 1860 'base' and 'selector' fields of the segment cache to go 1861 faster. A solution may be to force addseg to one in 1862 translate-i386.c. */ 1863 new_hflags |= HF_ADDSEG_MASK; 1864 } else { 1865 new_hflags |= ((env->segs[R_DS].base | 1866 env->segs[R_ES].base | 1867 env->segs[R_SS].base) != 0) << 1868 HF_ADDSEG_SHIFT; 1869 } 1870 env->hflags = (env->hflags & 1871 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1872 } 1873 } 1874 1875 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1876 uint8_t sipi_vector) 1877 { 1878 CPUState *cs = CPU(cpu); 1879 CPUX86State *env = &cpu->env; 1880 1881 env->eip = 0; 1882 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1883 sipi_vector << 12, 1884 env->segs[R_CS].limit, 1885 env->segs[R_CS].flags); 1886 cs->halted = 0; 1887 } 1888 1889 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1890 target_ulong *base, unsigned int *limit, 1891 unsigned int *flags); 1892 1893 /* op_helper.c */ 1894 /* used for debug or cpu save/restore */ 1895 1896 /* cpu-exec.c */ 1897 /* the following helpers are only usable in user mode simulation as 1898 they can trigger unexpected exceptions */ 1899 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1900 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1901 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1902 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1903 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1904 1905 /* you can call this signal handler from your SIGBUS and SIGSEGV 1906 signal handlers to inform the virtual CPU of exceptions. non zero 1907 is returned if the signal was handled by the virtual CPU. */ 1908 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1909 void *puc); 1910 1911 /* cpu.c */ 1912 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1913 uint32_t *eax, uint32_t *ebx, 1914 uint32_t *ecx, uint32_t *edx); 1915 void cpu_clear_apic_feature(CPUX86State *env); 1916 void host_cpuid(uint32_t function, uint32_t count, 1917 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1918 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1919 1920 /* helper.c */ 1921 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1922 1923 #ifndef CONFIG_USER_ONLY 1924 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1925 { 1926 return !!attrs.secure; 1927 } 1928 1929 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1930 { 1931 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1932 } 1933 1934 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1935 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1936 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1937 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1938 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1939 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1940 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1941 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1942 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1943 #endif 1944 1945 /* will be suppressed */ 1946 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1947 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1948 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1949 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1950 1951 /* hw/pc.c */ 1952 uint64_t cpu_get_tsc(CPUX86State *env); 1953 1954 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1955 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1956 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1957 1958 #ifdef TARGET_X86_64 1959 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1960 #else 1961 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1962 #endif 1963 1964 #define cpu_signal_handler cpu_x86_signal_handler 1965 #define cpu_list x86_cpu_list 1966 1967 /* MMU modes definitions */ 1968 #define MMU_KSMAP_IDX 0 1969 #define MMU_USER_IDX 1 1970 #define MMU_KNOSMAP_IDX 2 1971 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1972 { 1973 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1974 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1975 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1976 } 1977 1978 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1979 { 1980 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1981 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1982 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1983 } 1984 1985 #define CC_DST (env->cc_dst) 1986 #define CC_SRC (env->cc_src) 1987 #define CC_SRC2 (env->cc_src2) 1988 #define CC_OP (env->cc_op) 1989 1990 typedef CPUX86State CPUArchState; 1991 typedef X86CPU ArchCPU; 1992 1993 #include "exec/cpu-all.h" 1994 #include "svm.h" 1995 1996 #if !defined(CONFIG_USER_ONLY) 1997 #include "hw/i386/apic.h" 1998 #endif 1999 2000 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2001 target_ulong *cs_base, uint32_t *flags) 2002 { 2003 *cs_base = env->segs[R_CS].base; 2004 *pc = *cs_base + env->eip; 2005 *flags = env->hflags | 2006 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2007 } 2008 2009 void do_cpu_init(X86CPU *cpu); 2010 void do_cpu_sipi(X86CPU *cpu); 2011 2012 #define MCE_INJECT_BROADCAST 1 2013 #define MCE_INJECT_UNCOND_AO 2 2014 2015 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2016 uint64_t status, uint64_t mcg_status, uint64_t addr, 2017 uint64_t misc, int flags); 2018 2019 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2020 2021 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2022 { 2023 uint32_t eflags = env->eflags; 2024 if (tcg_enabled()) { 2025 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 2026 } 2027 return eflags; 2028 } 2029 2030 2031 /* load efer and update the corresponding hflags. XXX: do consistency 2032 checks with cpuid bits? */ 2033 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 2034 { 2035 env->efer = val; 2036 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 2037 if (env->efer & MSR_EFER_LMA) { 2038 env->hflags |= HF_LMA_MASK; 2039 } 2040 if (env->efer & MSR_EFER_SVME) { 2041 env->hflags |= HF_SVME_MASK; 2042 } 2043 } 2044 2045 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2046 { 2047 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2048 } 2049 2050 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2051 { 2052 if (env->hflags & HF_SMM_MASK) { 2053 return -1; 2054 } else { 2055 return env->a20_mask; 2056 } 2057 } 2058 2059 static inline bool cpu_has_vmx(CPUX86State *env) 2060 { 2061 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2062 } 2063 2064 static inline bool cpu_has_svm(CPUX86State *env) 2065 { 2066 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2067 } 2068 2069 /* 2070 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2071 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2072 * VMX operation. This is because CR4.VMXE is one of the bits set 2073 * in MSR_IA32_VMX_CR4_FIXED1. 2074 * 2075 * There is one exception to above statement when vCPU enters SMM mode. 2076 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2077 * may also reset CR4.VMXE during execution in SMM mode. 2078 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2079 * and CR4.VMXE is restored to it's original value of being set. 2080 * 2081 * Therefore, when vCPU is not in SMM mode, we can infer whether 2082 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2083 * know for certain. 2084 */ 2085 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2086 { 2087 return cpu_has_vmx(env) && 2088 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2089 } 2090 2091 /* fpu_helper.c */ 2092 void update_fp_status(CPUX86State *env); 2093 void update_mxcsr_status(CPUX86State *env); 2094 void update_mxcsr_from_sse_status(CPUX86State *env); 2095 2096 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2097 { 2098 env->mxcsr = mxcsr; 2099 if (tcg_enabled()) { 2100 update_mxcsr_status(env); 2101 } 2102 } 2103 2104 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2105 { 2106 env->fpuc = fpuc; 2107 if (tcg_enabled()) { 2108 update_fp_status(env); 2109 } 2110 } 2111 2112 /* mem_helper.c */ 2113 void helper_lock_init(void); 2114 2115 /* svm_helper.c */ 2116 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2117 uint64_t param, uintptr_t retaddr); 2118 /* apic.c */ 2119 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2120 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2121 TPRAccess access); 2122 2123 2124 /* Change the value of a KVM-specific default 2125 * 2126 * If value is NULL, no default will be set and the original 2127 * value from the CPU model table will be kept. 2128 * 2129 * It is valid to call this function only for properties that 2130 * are already present in the kvm_default_props table. 2131 */ 2132 void x86_cpu_change_kvm_default(const char *prop, const char *value); 2133 2134 /* Special values for X86CPUVersion: */ 2135 2136 /* Resolve to latest CPU version */ 2137 #define CPU_VERSION_LATEST -1 2138 2139 /* 2140 * Resolve to version defined by current machine type. 2141 * See x86_cpu_set_default_version() 2142 */ 2143 #define CPU_VERSION_AUTO -2 2144 2145 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2146 #define CPU_VERSION_LEGACY 0 2147 2148 typedef int X86CPUVersion; 2149 2150 /* 2151 * Set default CPU model version for CPU models having 2152 * version == CPU_VERSION_AUTO. 2153 */ 2154 void x86_cpu_set_default_version(X86CPUVersion version); 2155 2156 #define APIC_DEFAULT_ADDRESS 0xfee00000 2157 #define APIC_SPACE_SIZE 0x100000 2158 2159 /* cpu-dump.c */ 2160 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2161 2162 /* cpu.c */ 2163 bool cpu_is_bsp(X86CPU *cpu); 2164 2165 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 2166 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 2167 void x86_update_hflags(CPUX86State* env); 2168 2169 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2170 { 2171 return !!(cpu->hyperv_features & BIT(feat)); 2172 } 2173 2174 #if defined(TARGET_X86_64) && \ 2175 defined(CONFIG_USER_ONLY) && \ 2176 defined(CONFIG_LINUX) 2177 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2178 #endif 2179 2180 #endif /* I386_CPU_H */ 2181