1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef I386_CPU_H 21 #define I386_CPU_H 22 23 #include "sysemu/tcg.h" 24 #include "cpu-qom.h" 25 #include "kvm/hyperv-proto.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* The x86 has a strong memory model with some store-after-load re-ordering */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 31 32 #define KVM_HAVE_MCE_INJECTION 1 33 34 /* support for self modifying code even if the modified instruction is 35 close to the modifying instruction */ 36 #define TARGET_HAS_PRECISE_SMC 37 38 #ifdef TARGET_X86_64 39 #define I386_ELF_MACHINE EM_X86_64 40 #define ELF_MACHINE_UNAME "x86_64" 41 #else 42 #define I386_ELF_MACHINE EM_386 43 #define ELF_MACHINE_UNAME "i686" 44 #endif 45 46 enum { 47 R_EAX = 0, 48 R_ECX = 1, 49 R_EDX = 2, 50 R_EBX = 3, 51 R_ESP = 4, 52 R_EBP = 5, 53 R_ESI = 6, 54 R_EDI = 7, 55 R_R8 = 8, 56 R_R9 = 9, 57 R_R10 = 10, 58 R_R11 = 11, 59 R_R12 = 12, 60 R_R13 = 13, 61 R_R14 = 14, 62 R_R15 = 15, 63 64 R_AL = 0, 65 R_CL = 1, 66 R_DL = 2, 67 R_BL = 3, 68 R_AH = 4, 69 R_CH = 5, 70 R_DH = 6, 71 R_BH = 7, 72 }; 73 74 typedef enum X86Seg { 75 R_ES = 0, 76 R_CS = 1, 77 R_SS = 2, 78 R_DS = 3, 79 R_FS = 4, 80 R_GS = 5, 81 R_LDTR = 6, 82 R_TR = 7, 83 } X86Seg; 84 85 /* segment descriptor fields */ 86 #define DESC_G_SHIFT 23 87 #define DESC_G_MASK (1 << DESC_G_SHIFT) 88 #define DESC_B_SHIFT 22 89 #define DESC_B_MASK (1 << DESC_B_SHIFT) 90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91 #define DESC_L_MASK (1 << DESC_L_SHIFT) 92 #define DESC_AVL_SHIFT 20 93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94 #define DESC_P_SHIFT 15 95 #define DESC_P_MASK (1 << DESC_P_SHIFT) 96 #define DESC_DPL_SHIFT 13 97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98 #define DESC_S_SHIFT 12 99 #define DESC_S_MASK (1 << DESC_S_SHIFT) 100 #define DESC_TYPE_SHIFT 8 101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102 #define DESC_A_MASK (1 << 8) 103 104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105 #define DESC_C_MASK (1 << 10) /* code: conforming */ 106 #define DESC_R_MASK (1 << 9) /* code: readable */ 107 108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109 #define DESC_W_MASK (1 << 9) /* data: writable */ 110 111 #define DESC_TSS_BUSY_MASK (1 << 9) 112 113 /* eflags masks */ 114 #define CC_C 0x0001 115 #define CC_P 0x0004 116 #define CC_A 0x0010 117 #define CC_Z 0x0040 118 #define CC_S 0x0080 119 #define CC_O 0x0800 120 121 #define TF_SHIFT 8 122 #define IOPL_SHIFT 12 123 #define VM_SHIFT 17 124 125 #define TF_MASK 0x00000100 126 #define IF_MASK 0x00000200 127 #define DF_MASK 0x00000400 128 #define IOPL_MASK 0x00003000 129 #define NT_MASK 0x00004000 130 #define RF_MASK 0x00010000 131 #define VM_MASK 0x00020000 132 #define AC_MASK 0x00040000 133 #define VIF_MASK 0x00080000 134 #define VIP_MASK 0x00100000 135 #define ID_MASK 0x00200000 136 137 /* hidden flags - used internally by qemu to represent additional cpu 138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140 positions to ease oring with eflags. */ 141 /* current cpl */ 142 #define HF_CPL_SHIFT 0 143 /* true if hardware interrupts must be disabled for next instruction */ 144 #define HF_INHIBIT_IRQ_SHIFT 3 145 /* 16 or 32 segments */ 146 #define HF_CS32_SHIFT 4 147 #define HF_SS32_SHIFT 5 148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149 #define HF_ADDSEG_SHIFT 6 150 /* copy of CR0.PE (protected mode) */ 151 #define HF_PE_SHIFT 7 152 #define HF_TF_SHIFT 8 /* must be same as eflags */ 153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154 #define HF_EM_SHIFT 10 155 #define HF_TS_SHIFT 11 156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159 #define HF_RF_SHIFT 16 /* must be same as eflags */ 160 #define HF_VM_SHIFT 17 /* must be same as eflags */ 161 #define HF_AC_SHIFT 18 /* must be same as eflags */ 162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170 171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176 #define HF_PE_MASK (1 << HF_PE_SHIFT) 177 #define HF_TF_MASK (1 << HF_TF_SHIFT) 178 #define HF_MP_MASK (1 << HF_MP_SHIFT) 179 #define HF_EM_MASK (1 << HF_EM_SHIFT) 180 #define HF_TS_MASK (1 << HF_TS_SHIFT) 181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184 #define HF_RF_MASK (1 << HF_RF_SHIFT) 185 #define HF_VM_MASK (1 << HF_VM_SHIFT) 186 #define HF_AC_MASK (1 << HF_AC_SHIFT) 187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195 196 /* hflags2 */ 197 198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 206 207 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 208 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 209 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 210 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 211 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 212 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 213 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 214 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 215 216 #define CR0_PE_SHIFT 0 217 #define CR0_MP_SHIFT 1 218 219 #define CR0_PE_MASK (1U << 0) 220 #define CR0_MP_MASK (1U << 1) 221 #define CR0_EM_MASK (1U << 2) 222 #define CR0_TS_MASK (1U << 3) 223 #define CR0_ET_MASK (1U << 4) 224 #define CR0_NE_MASK (1U << 5) 225 #define CR0_WP_MASK (1U << 16) 226 #define CR0_AM_MASK (1U << 18) 227 #define CR0_PG_MASK (1U << 31) 228 229 #define CR4_VME_MASK (1U << 0) 230 #define CR4_PVI_MASK (1U << 1) 231 #define CR4_TSD_MASK (1U << 2) 232 #define CR4_DE_MASK (1U << 3) 233 #define CR4_PSE_MASK (1U << 4) 234 #define CR4_PAE_MASK (1U << 5) 235 #define CR4_MCE_MASK (1U << 6) 236 #define CR4_PGE_MASK (1U << 7) 237 #define CR4_PCE_MASK (1U << 8) 238 #define CR4_OSFXSR_SHIFT 9 239 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 240 #define CR4_OSXMMEXCPT_MASK (1U << 10) 241 #define CR4_LA57_MASK (1U << 12) 242 #define CR4_VMXE_MASK (1U << 13) 243 #define CR4_SMXE_MASK (1U << 14) 244 #define CR4_FSGSBASE_MASK (1U << 16) 245 #define CR4_PCIDE_MASK (1U << 17) 246 #define CR4_OSXSAVE_MASK (1U << 18) 247 #define CR4_SMEP_MASK (1U << 20) 248 #define CR4_SMAP_MASK (1U << 21) 249 #define CR4_PKE_MASK (1U << 22) 250 #define CR4_PKS_MASK (1U << 24) 251 252 #define DR6_BD (1 << 13) 253 #define DR6_BS (1 << 14) 254 #define DR6_BT (1 << 15) 255 #define DR6_FIXED_1 0xffff0ff0 256 257 #define DR7_GD (1 << 13) 258 #define DR7_TYPE_SHIFT 16 259 #define DR7_LEN_SHIFT 18 260 #define DR7_FIXED_1 0x00000400 261 #define DR7_GLOBAL_BP_MASK 0xaa 262 #define DR7_LOCAL_BP_MASK 0x55 263 #define DR7_MAX_BP 4 264 #define DR7_TYPE_BP_INST 0x0 265 #define DR7_TYPE_DATA_WR 0x1 266 #define DR7_TYPE_IO_RW 0x2 267 #define DR7_TYPE_DATA_RW 0x3 268 269 #define PG_PRESENT_BIT 0 270 #define PG_RW_BIT 1 271 #define PG_USER_BIT 2 272 #define PG_PWT_BIT 3 273 #define PG_PCD_BIT 4 274 #define PG_ACCESSED_BIT 5 275 #define PG_DIRTY_BIT 6 276 #define PG_PSE_BIT 7 277 #define PG_GLOBAL_BIT 8 278 #define PG_PSE_PAT_BIT 12 279 #define PG_PKRU_BIT 59 280 #define PG_NX_BIT 63 281 282 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 283 #define PG_RW_MASK (1 << PG_RW_BIT) 284 #define PG_USER_MASK (1 << PG_USER_BIT) 285 #define PG_PWT_MASK (1 << PG_PWT_BIT) 286 #define PG_PCD_MASK (1 << PG_PCD_BIT) 287 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 288 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 289 #define PG_PSE_MASK (1 << PG_PSE_BIT) 290 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 291 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 292 #define PG_ADDRESS_MASK 0x000ffffffffff000LL 293 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 294 #define PG_HI_USER_MASK 0x7ff0000000000000LL 295 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 296 #define PG_NX_MASK (1ULL << PG_NX_BIT) 297 298 #define PG_ERROR_W_BIT 1 299 300 #define PG_ERROR_P_MASK 0x01 301 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 302 #define PG_ERROR_U_MASK 0x04 303 #define PG_ERROR_RSVD_MASK 0x08 304 #define PG_ERROR_I_D_MASK 0x10 305 #define PG_ERROR_PK_MASK 0x20 306 307 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 308 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 309 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 310 311 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 312 #define MCE_BANKS_DEF 10 313 314 #define MCG_CAP_BANKS_MASK 0xff 315 316 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 317 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 318 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 319 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 320 321 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 322 323 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 324 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 325 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 326 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 327 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 328 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 329 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 330 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 331 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 332 333 /* MISC register defines */ 334 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 335 #define MCM_ADDR_LINEAR 1 /* linear address */ 336 #define MCM_ADDR_PHYS 2 /* physical address */ 337 #define MCM_ADDR_MEM 3 /* memory address */ 338 #define MCM_ADDR_GENERIC 7 /* generic */ 339 340 #define MSR_IA32_TSC 0x10 341 #define MSR_IA32_APICBASE 0x1b 342 #define MSR_IA32_APICBASE_BSP (1<<8) 343 #define MSR_IA32_APICBASE_ENABLE (1<<11) 344 #define MSR_IA32_APICBASE_EXTD (1 << 10) 345 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 346 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 347 #define MSR_TSC_ADJUST 0x0000003b 348 #define MSR_IA32_SPEC_CTRL 0x48 349 #define MSR_VIRT_SSBD 0xc001011f 350 #define MSR_IA32_PRED_CMD 0x49 351 #define MSR_IA32_UCODE_REV 0x8b 352 #define MSR_IA32_CORE_CAPABILITY 0xcf 353 354 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 355 #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 356 357 #define MSR_IA32_PERF_CAPABILITIES 0x345 358 359 #define MSR_IA32_TSX_CTRL 0x122 360 #define MSR_IA32_TSCDEADLINE 0x6e0 361 #define MSR_IA32_PKRS 0x6e1 362 363 #define FEATURE_CONTROL_LOCKED (1<<0) 364 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 365 #define FEATURE_CONTROL_LMCE (1<<20) 366 367 #define MSR_P6_PERFCTR0 0xc1 368 369 #define MSR_IA32_SMBASE 0x9e 370 #define MSR_SMI_COUNT 0x34 371 #define MSR_CORE_THREAD_COUNT 0x35 372 #define MSR_MTRRcap 0xfe 373 #define MSR_MTRRcap_VCNT 8 374 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 375 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 376 377 #define MSR_IA32_SYSENTER_CS 0x174 378 #define MSR_IA32_SYSENTER_ESP 0x175 379 #define MSR_IA32_SYSENTER_EIP 0x176 380 381 #define MSR_MCG_CAP 0x179 382 #define MSR_MCG_STATUS 0x17a 383 #define MSR_MCG_CTL 0x17b 384 #define MSR_MCG_EXT_CTL 0x4d0 385 386 #define MSR_P6_EVNTSEL0 0x186 387 388 #define MSR_IA32_PERF_STATUS 0x198 389 390 #define MSR_IA32_MISC_ENABLE 0x1a0 391 /* Indicates good rep/movs microcode on some processors: */ 392 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 393 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 394 395 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 396 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 397 398 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 399 400 #define MSR_MTRRfix64K_00000 0x250 401 #define MSR_MTRRfix16K_80000 0x258 402 #define MSR_MTRRfix16K_A0000 0x259 403 #define MSR_MTRRfix4K_C0000 0x268 404 #define MSR_MTRRfix4K_C8000 0x269 405 #define MSR_MTRRfix4K_D0000 0x26a 406 #define MSR_MTRRfix4K_D8000 0x26b 407 #define MSR_MTRRfix4K_E0000 0x26c 408 #define MSR_MTRRfix4K_E8000 0x26d 409 #define MSR_MTRRfix4K_F0000 0x26e 410 #define MSR_MTRRfix4K_F8000 0x26f 411 412 #define MSR_PAT 0x277 413 414 #define MSR_MTRRdefType 0x2ff 415 416 #define MSR_CORE_PERF_FIXED_CTR0 0x309 417 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 418 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 419 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 420 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 421 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 422 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 423 424 #define MSR_MC0_CTL 0x400 425 #define MSR_MC0_STATUS 0x401 426 #define MSR_MC0_ADDR 0x402 427 #define MSR_MC0_MISC 0x403 428 429 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 430 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 431 #define MSR_IA32_RTIT_CTL 0x570 432 #define MSR_IA32_RTIT_STATUS 0x571 433 #define MSR_IA32_RTIT_CR3_MATCH 0x572 434 #define MSR_IA32_RTIT_ADDR0_A 0x580 435 #define MSR_IA32_RTIT_ADDR0_B 0x581 436 #define MSR_IA32_RTIT_ADDR1_A 0x582 437 #define MSR_IA32_RTIT_ADDR1_B 0x583 438 #define MSR_IA32_RTIT_ADDR2_A 0x584 439 #define MSR_IA32_RTIT_ADDR2_B 0x585 440 #define MSR_IA32_RTIT_ADDR3_A 0x586 441 #define MSR_IA32_RTIT_ADDR3_B 0x587 442 #define MAX_RTIT_ADDRS 8 443 444 #define MSR_EFER 0xc0000080 445 446 #define MSR_EFER_SCE (1 << 0) 447 #define MSR_EFER_LME (1 << 8) 448 #define MSR_EFER_LMA (1 << 10) 449 #define MSR_EFER_NXE (1 << 11) 450 #define MSR_EFER_SVME (1 << 12) 451 #define MSR_EFER_FFXSR (1 << 14) 452 453 #define MSR_STAR 0xc0000081 454 #define MSR_LSTAR 0xc0000082 455 #define MSR_CSTAR 0xc0000083 456 #define MSR_FMASK 0xc0000084 457 #define MSR_FSBASE 0xc0000100 458 #define MSR_GSBASE 0xc0000101 459 #define MSR_KERNELGSBASE 0xc0000102 460 #define MSR_TSC_AUX 0xc0000103 461 462 #define MSR_VM_HSAVE_PA 0xc0010117 463 464 #define MSR_IA32_BNDCFGS 0x00000d90 465 #define MSR_IA32_XSS 0x00000da0 466 #define MSR_IA32_UMWAIT_CONTROL 0xe1 467 468 #define MSR_IA32_VMX_BASIC 0x00000480 469 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 470 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 471 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 472 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 473 #define MSR_IA32_VMX_MISC 0x00000485 474 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 475 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 476 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 477 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 478 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 479 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 480 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 481 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 482 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 483 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 484 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 485 #define MSR_IA32_VMX_VMFUNC 0x00000491 486 487 #define XSTATE_FP_BIT 0 488 #define XSTATE_SSE_BIT 1 489 #define XSTATE_YMM_BIT 2 490 #define XSTATE_BNDREGS_BIT 3 491 #define XSTATE_BNDCSR_BIT 4 492 #define XSTATE_OPMASK_BIT 5 493 #define XSTATE_ZMM_Hi256_BIT 6 494 #define XSTATE_Hi16_ZMM_BIT 7 495 #define XSTATE_PKRU_BIT 9 496 497 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 498 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 499 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 500 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 501 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 502 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 503 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 504 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 505 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 506 507 /* CPUID feature words */ 508 typedef enum FeatureWord { 509 FEAT_1_EDX, /* CPUID[1].EDX */ 510 FEAT_1_ECX, /* CPUID[1].ECX */ 511 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 512 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 513 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 514 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 515 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 516 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 517 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 518 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 519 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 520 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 521 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 522 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 523 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 524 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 525 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ 526 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ 527 FEAT_SVM, /* CPUID[8000_000A].EDX */ 528 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 529 FEAT_6_EAX, /* CPUID[6].EAX */ 530 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 531 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 532 FEAT_ARCH_CAPABILITIES, 533 FEAT_CORE_CAPABILITY, 534 FEAT_PERF_CAPABILITIES, 535 FEAT_VMX_PROCBASED_CTLS, 536 FEAT_VMX_SECONDARY_CTLS, 537 FEAT_VMX_PINBASED_CTLS, 538 FEAT_VMX_EXIT_CTLS, 539 FEAT_VMX_ENTRY_CTLS, 540 FEAT_VMX_MISC, 541 FEAT_VMX_EPT_VPID_CAPS, 542 FEAT_VMX_BASIC, 543 FEAT_VMX_VMFUNC, 544 FEAT_14_0_ECX, 545 FEATURE_WORDS, 546 } FeatureWord; 547 548 typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 549 550 /* cpuid_features bits */ 551 #define CPUID_FP87 (1U << 0) 552 #define CPUID_VME (1U << 1) 553 #define CPUID_DE (1U << 2) 554 #define CPUID_PSE (1U << 3) 555 #define CPUID_TSC (1U << 4) 556 #define CPUID_MSR (1U << 5) 557 #define CPUID_PAE (1U << 6) 558 #define CPUID_MCE (1U << 7) 559 #define CPUID_CX8 (1U << 8) 560 #define CPUID_APIC (1U << 9) 561 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 562 #define CPUID_MTRR (1U << 12) 563 #define CPUID_PGE (1U << 13) 564 #define CPUID_MCA (1U << 14) 565 #define CPUID_CMOV (1U << 15) 566 #define CPUID_PAT (1U << 16) 567 #define CPUID_PSE36 (1U << 17) 568 #define CPUID_PN (1U << 18) 569 #define CPUID_CLFLUSH (1U << 19) 570 #define CPUID_DTS (1U << 21) 571 #define CPUID_ACPI (1U << 22) 572 #define CPUID_MMX (1U << 23) 573 #define CPUID_FXSR (1U << 24) 574 #define CPUID_SSE (1U << 25) 575 #define CPUID_SSE2 (1U << 26) 576 #define CPUID_SS (1U << 27) 577 #define CPUID_HT (1U << 28) 578 #define CPUID_TM (1U << 29) 579 #define CPUID_IA64 (1U << 30) 580 #define CPUID_PBE (1U << 31) 581 582 #define CPUID_EXT_SSE3 (1U << 0) 583 #define CPUID_EXT_PCLMULQDQ (1U << 1) 584 #define CPUID_EXT_DTES64 (1U << 2) 585 #define CPUID_EXT_MONITOR (1U << 3) 586 #define CPUID_EXT_DSCPL (1U << 4) 587 #define CPUID_EXT_VMX (1U << 5) 588 #define CPUID_EXT_SMX (1U << 6) 589 #define CPUID_EXT_EST (1U << 7) 590 #define CPUID_EXT_TM2 (1U << 8) 591 #define CPUID_EXT_SSSE3 (1U << 9) 592 #define CPUID_EXT_CID (1U << 10) 593 #define CPUID_EXT_FMA (1U << 12) 594 #define CPUID_EXT_CX16 (1U << 13) 595 #define CPUID_EXT_XTPR (1U << 14) 596 #define CPUID_EXT_PDCM (1U << 15) 597 #define CPUID_EXT_PCID (1U << 17) 598 #define CPUID_EXT_DCA (1U << 18) 599 #define CPUID_EXT_SSE41 (1U << 19) 600 #define CPUID_EXT_SSE42 (1U << 20) 601 #define CPUID_EXT_X2APIC (1U << 21) 602 #define CPUID_EXT_MOVBE (1U << 22) 603 #define CPUID_EXT_POPCNT (1U << 23) 604 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 605 #define CPUID_EXT_AES (1U << 25) 606 #define CPUID_EXT_XSAVE (1U << 26) 607 #define CPUID_EXT_OSXSAVE (1U << 27) 608 #define CPUID_EXT_AVX (1U << 28) 609 #define CPUID_EXT_F16C (1U << 29) 610 #define CPUID_EXT_RDRAND (1U << 30) 611 #define CPUID_EXT_HYPERVISOR (1U << 31) 612 613 #define CPUID_EXT2_FPU (1U << 0) 614 #define CPUID_EXT2_VME (1U << 1) 615 #define CPUID_EXT2_DE (1U << 2) 616 #define CPUID_EXT2_PSE (1U << 3) 617 #define CPUID_EXT2_TSC (1U << 4) 618 #define CPUID_EXT2_MSR (1U << 5) 619 #define CPUID_EXT2_PAE (1U << 6) 620 #define CPUID_EXT2_MCE (1U << 7) 621 #define CPUID_EXT2_CX8 (1U << 8) 622 #define CPUID_EXT2_APIC (1U << 9) 623 #define CPUID_EXT2_SYSCALL (1U << 11) 624 #define CPUID_EXT2_MTRR (1U << 12) 625 #define CPUID_EXT2_PGE (1U << 13) 626 #define CPUID_EXT2_MCA (1U << 14) 627 #define CPUID_EXT2_CMOV (1U << 15) 628 #define CPUID_EXT2_PAT (1U << 16) 629 #define CPUID_EXT2_PSE36 (1U << 17) 630 #define CPUID_EXT2_MP (1U << 19) 631 #define CPUID_EXT2_NX (1U << 20) 632 #define CPUID_EXT2_MMXEXT (1U << 22) 633 #define CPUID_EXT2_MMX (1U << 23) 634 #define CPUID_EXT2_FXSR (1U << 24) 635 #define CPUID_EXT2_FFXSR (1U << 25) 636 #define CPUID_EXT2_PDPE1GB (1U << 26) 637 #define CPUID_EXT2_RDTSCP (1U << 27) 638 #define CPUID_EXT2_LM (1U << 29) 639 #define CPUID_EXT2_3DNOWEXT (1U << 30) 640 #define CPUID_EXT2_3DNOW (1U << 31) 641 642 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 643 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 644 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 645 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 646 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 647 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 648 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 649 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 650 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 651 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 652 653 #define CPUID_EXT3_LAHF_LM (1U << 0) 654 #define CPUID_EXT3_CMP_LEG (1U << 1) 655 #define CPUID_EXT3_SVM (1U << 2) 656 #define CPUID_EXT3_EXTAPIC (1U << 3) 657 #define CPUID_EXT3_CR8LEG (1U << 4) 658 #define CPUID_EXT3_ABM (1U << 5) 659 #define CPUID_EXT3_SSE4A (1U << 6) 660 #define CPUID_EXT3_MISALIGNSSE (1U << 7) 661 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 662 #define CPUID_EXT3_OSVW (1U << 9) 663 #define CPUID_EXT3_IBS (1U << 10) 664 #define CPUID_EXT3_XOP (1U << 11) 665 #define CPUID_EXT3_SKINIT (1U << 12) 666 #define CPUID_EXT3_WDT (1U << 13) 667 #define CPUID_EXT3_LWP (1U << 15) 668 #define CPUID_EXT3_FMA4 (1U << 16) 669 #define CPUID_EXT3_TCE (1U << 17) 670 #define CPUID_EXT3_NODEID (1U << 19) 671 #define CPUID_EXT3_TBM (1U << 21) 672 #define CPUID_EXT3_TOPOEXT (1U << 22) 673 #define CPUID_EXT3_PERFCORE (1U << 23) 674 #define CPUID_EXT3_PERFNB (1U << 24) 675 676 #define CPUID_SVM_NPT (1U << 0) 677 #define CPUID_SVM_LBRV (1U << 1) 678 #define CPUID_SVM_SVMLOCK (1U << 2) 679 #define CPUID_SVM_NRIPSAVE (1U << 3) 680 #define CPUID_SVM_TSCSCALE (1U << 4) 681 #define CPUID_SVM_VMCBCLEAN (1U << 5) 682 #define CPUID_SVM_FLUSHASID (1U << 6) 683 #define CPUID_SVM_DECODEASSIST (1U << 7) 684 #define CPUID_SVM_PAUSEFILTER (1U << 10) 685 #define CPUID_SVM_PFTHRESHOLD (1U << 12) 686 #define CPUID_SVM_AVIC (1U << 13) 687 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) 688 #define CPUID_SVM_VGIF (1U << 16) 689 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) 690 691 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 692 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 693 /* 1st Group of Advanced Bit Manipulation Extensions */ 694 #define CPUID_7_0_EBX_BMI1 (1U << 3) 695 /* Hardware Lock Elision */ 696 #define CPUID_7_0_EBX_HLE (1U << 4) 697 /* Intel Advanced Vector Extensions 2 */ 698 #define CPUID_7_0_EBX_AVX2 (1U << 5) 699 /* Supervisor-mode Execution Prevention */ 700 #define CPUID_7_0_EBX_SMEP (1U << 7) 701 /* 2nd Group of Advanced Bit Manipulation Extensions */ 702 #define CPUID_7_0_EBX_BMI2 (1U << 8) 703 /* Enhanced REP MOVSB/STOSB */ 704 #define CPUID_7_0_EBX_ERMS (1U << 9) 705 /* Invalidate Process-Context Identifier */ 706 #define CPUID_7_0_EBX_INVPCID (1U << 10) 707 /* Restricted Transactional Memory */ 708 #define CPUID_7_0_EBX_RTM (1U << 11) 709 /* Memory Protection Extension */ 710 #define CPUID_7_0_EBX_MPX (1U << 14) 711 /* AVX-512 Foundation */ 712 #define CPUID_7_0_EBX_AVX512F (1U << 16) 713 /* AVX-512 Doubleword & Quadword Instruction */ 714 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 715 /* Read Random SEED */ 716 #define CPUID_7_0_EBX_RDSEED (1U << 18) 717 /* ADCX and ADOX instructions */ 718 #define CPUID_7_0_EBX_ADX (1U << 19) 719 /* Supervisor Mode Access Prevention */ 720 #define CPUID_7_0_EBX_SMAP (1U << 20) 721 /* AVX-512 Integer Fused Multiply Add */ 722 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 723 /* Persistent Commit */ 724 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 725 /* Flush a Cache Line Optimized */ 726 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 727 /* Cache Line Write Back */ 728 #define CPUID_7_0_EBX_CLWB (1U << 24) 729 /* Intel Processor Trace */ 730 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 731 /* AVX-512 Prefetch */ 732 #define CPUID_7_0_EBX_AVX512PF (1U << 26) 733 /* AVX-512 Exponential and Reciprocal */ 734 #define CPUID_7_0_EBX_AVX512ER (1U << 27) 735 /* AVX-512 Conflict Detection */ 736 #define CPUID_7_0_EBX_AVX512CD (1U << 28) 737 /* SHA1/SHA256 Instruction Extensions */ 738 #define CPUID_7_0_EBX_SHA_NI (1U << 29) 739 /* AVX-512 Byte and Word Instructions */ 740 #define CPUID_7_0_EBX_AVX512BW (1U << 30) 741 /* AVX-512 Vector Length Extensions */ 742 #define CPUID_7_0_EBX_AVX512VL (1U << 31) 743 744 /* AVX-512 Vector Byte Manipulation Instruction */ 745 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 746 /* User-Mode Instruction Prevention */ 747 #define CPUID_7_0_ECX_UMIP (1U << 2) 748 /* Protection Keys for User-mode Pages */ 749 #define CPUID_7_0_ECX_PKU (1U << 3) 750 /* OS Enable Protection Keys */ 751 #define CPUID_7_0_ECX_OSPKE (1U << 4) 752 /* UMONITOR/UMWAIT/TPAUSE Instructions */ 753 #define CPUID_7_0_ECX_WAITPKG (1U << 5) 754 /* Additional AVX-512 Vector Byte Manipulation Instruction */ 755 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 756 /* Galois Field New Instructions */ 757 #define CPUID_7_0_ECX_GFNI (1U << 8) 758 /* Vector AES Instructions */ 759 #define CPUID_7_0_ECX_VAES (1U << 9) 760 /* Carry-Less Multiplication Quadword */ 761 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 762 /* Vector Neural Network Instructions */ 763 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 764 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 765 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 766 /* POPCNT for vectors of DW/QW */ 767 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 768 /* 5-level Page Tables */ 769 #define CPUID_7_0_ECX_LA57 (1U << 16) 770 /* Read Processor ID */ 771 #define CPUID_7_0_ECX_RDPID (1U << 22) 772 /* Cache Line Demote Instruction */ 773 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 774 /* Move Doubleword as Direct Store Instruction */ 775 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 776 /* Move 64 Bytes as Direct Store Instruction */ 777 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 778 /* Protection Keys for Supervisor-mode Pages */ 779 #define CPUID_7_0_ECX_PKS (1U << 31) 780 781 /* AVX512 Neural Network Instructions */ 782 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 783 /* AVX512 Multiply Accumulation Single Precision */ 784 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 785 /* Fast Short Rep Mov */ 786 #define CPUID_7_0_EDX_FSRM (1U << 4) 787 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 788 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 789 /* SERIALIZE instruction */ 790 #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 791 /* TSX Suspend Load Address Tracking instruction */ 792 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 793 /* AVX512_FP16 instruction */ 794 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) 795 /* Speculation Control */ 796 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 797 /* Single Thread Indirect Branch Predictors */ 798 #define CPUID_7_0_EDX_STIBP (1U << 27) 799 /* Arch Capabilities */ 800 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 801 /* Core Capability */ 802 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 803 /* Speculative Store Bypass Disable */ 804 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 805 806 /* AVX512 BFloat16 Instruction */ 807 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 808 809 /* Packets which contain IP payload have LIP values */ 810 #define CPUID_14_0_ECX_LIP (1U << 31) 811 812 /* CLZERO instruction */ 813 #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 814 /* Always save/restore FP error pointers */ 815 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 816 /* Write back and do not invalidate cache */ 817 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 818 /* Indirect Branch Prediction Barrier */ 819 #define CPUID_8000_0008_EBX_IBPB (1U << 12) 820 /* Indirect Branch Restricted Speculation */ 821 #define CPUID_8000_0008_EBX_IBRS (1U << 14) 822 /* Single Thread Indirect Branch Predictors */ 823 #define CPUID_8000_0008_EBX_STIBP (1U << 15) 824 /* Speculative Store Bypass Disable */ 825 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) 826 827 #define CPUID_XSAVE_XSAVEOPT (1U << 0) 828 #define CPUID_XSAVE_XSAVEC (1U << 1) 829 #define CPUID_XSAVE_XGETBV1 (1U << 2) 830 #define CPUID_XSAVE_XSAVES (1U << 3) 831 832 #define CPUID_6_EAX_ARAT (1U << 2) 833 834 /* CPUID[0x80000007].EDX flags: */ 835 #define CPUID_APM_INVTSC (1U << 8) 836 837 #define CPUID_VENDOR_SZ 12 838 839 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 840 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 841 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 842 #define CPUID_VENDOR_INTEL "GenuineIntel" 843 844 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 845 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 846 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 847 #define CPUID_VENDOR_AMD "AuthenticAMD" 848 849 #define CPUID_VENDOR_VIA "CentaurHauls" 850 851 #define CPUID_VENDOR_HYGON "HygonGenuine" 852 853 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 854 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 855 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 856 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 857 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 858 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 859 860 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 861 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 862 863 /* CPUID[0xB].ECX level types */ 864 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 865 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 866 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 867 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 868 869 /* MSR Feature Bits */ 870 #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 871 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 872 #define MSR_ARCH_CAP_RSBA (1U << 2) 873 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 874 #define MSR_ARCH_CAP_SSB_NO (1U << 4) 875 #define MSR_ARCH_CAP_MDS_NO (1U << 5) 876 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 877 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 878 #define MSR_ARCH_CAP_TAA_NO (1U << 8) 879 880 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 881 882 /* VMX MSR features */ 883 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 884 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 885 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 886 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 887 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 888 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 889 890 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 891 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 892 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 893 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 894 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 895 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 896 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 897 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 898 899 #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 900 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 901 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 902 #define MSR_VMX_EPT_UC (1ULL << 8) 903 #define MSR_VMX_EPT_WB (1ULL << 14) 904 #define MSR_VMX_EPT_2MB (1ULL << 16) 905 #define MSR_VMX_EPT_1GB (1ULL << 17) 906 #define MSR_VMX_EPT_INVEPT (1ULL << 20) 907 #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 908 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 909 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 910 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 911 #define MSR_VMX_EPT_INVVPID (1ULL << 32) 912 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 913 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 914 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 915 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 916 917 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 918 919 920 /* VMX controls */ 921 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 922 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 923 #define VMX_CPU_BASED_HLT_EXITING 0x00000080 924 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 925 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 926 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 927 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 928 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 929 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 930 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 931 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 932 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 933 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 934 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 935 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 936 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 937 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 938 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 939 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 940 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 941 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 942 943 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 944 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 945 #define VMX_SECONDARY_EXEC_DESC 0x00000004 946 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 947 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 948 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 949 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 950 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 951 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 952 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 953 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 954 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 955 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 956 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 957 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 958 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 959 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 960 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 961 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 962 963 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 964 #define VMX_PIN_BASED_NMI_EXITING 0x00000008 965 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 966 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 967 #define VMX_PIN_BASED_POSTED_INTR 0x00000080 968 969 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 970 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 971 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 972 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 973 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 974 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 975 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 976 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 977 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 978 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 979 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 980 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 981 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 982 983 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 984 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 985 #define VMX_VM_ENTRY_SMM 0x00000400 986 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 987 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 988 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 989 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 990 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 991 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 992 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 993 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 994 995 /* Supported Hyper-V Enlightenments */ 996 #define HYPERV_FEAT_RELAXED 0 997 #define HYPERV_FEAT_VAPIC 1 998 #define HYPERV_FEAT_TIME 2 999 #define HYPERV_FEAT_CRASH 3 1000 #define HYPERV_FEAT_RESET 4 1001 #define HYPERV_FEAT_VPINDEX 5 1002 #define HYPERV_FEAT_RUNTIME 6 1003 #define HYPERV_FEAT_SYNIC 7 1004 #define HYPERV_FEAT_STIMER 8 1005 #define HYPERV_FEAT_FREQUENCIES 9 1006 #define HYPERV_FEAT_REENLIGHTENMENT 10 1007 #define HYPERV_FEAT_TLBFLUSH 11 1008 #define HYPERV_FEAT_EVMCS 12 1009 #define HYPERV_FEAT_IPI 13 1010 #define HYPERV_FEAT_STIMER_DIRECT 14 1011 1012 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY 1013 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF 1014 #endif 1015 1016 #define EXCP00_DIVZ 0 1017 #define EXCP01_DB 1 1018 #define EXCP02_NMI 2 1019 #define EXCP03_INT3 3 1020 #define EXCP04_INTO 4 1021 #define EXCP05_BOUND 5 1022 #define EXCP06_ILLOP 6 1023 #define EXCP07_PREX 7 1024 #define EXCP08_DBLE 8 1025 #define EXCP09_XERR 9 1026 #define EXCP0A_TSS 10 1027 #define EXCP0B_NOSEG 11 1028 #define EXCP0C_STACK 12 1029 #define EXCP0D_GPF 13 1030 #define EXCP0E_PAGE 14 1031 #define EXCP10_COPR 16 1032 #define EXCP11_ALGN 17 1033 #define EXCP12_MCHK 18 1034 1035 #define EXCP_VMEXIT 0x100 /* only for system emulation */ 1036 #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1037 #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1038 1039 /* i386-specific interrupt pending bits. */ 1040 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1041 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1042 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1043 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1044 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1045 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1046 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1047 1048 /* Use a clearer name for this. */ 1049 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1050 1051 /* Instead of computing the condition codes after each x86 instruction, 1052 * QEMU just stores one operand (called CC_SRC), the result 1053 * (called CC_DST) and the type of operation (called CC_OP). When the 1054 * condition codes are needed, the condition codes can be calculated 1055 * using this information. Condition codes are not generated if they 1056 * are only needed for conditional branches. 1057 */ 1058 typedef enum { 1059 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1060 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1061 1062 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1063 CC_OP_MULW, 1064 CC_OP_MULL, 1065 CC_OP_MULQ, 1066 1067 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1068 CC_OP_ADDW, 1069 CC_OP_ADDL, 1070 CC_OP_ADDQ, 1071 1072 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1073 CC_OP_ADCW, 1074 CC_OP_ADCL, 1075 CC_OP_ADCQ, 1076 1077 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1078 CC_OP_SUBW, 1079 CC_OP_SUBL, 1080 CC_OP_SUBQ, 1081 1082 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1083 CC_OP_SBBW, 1084 CC_OP_SBBL, 1085 CC_OP_SBBQ, 1086 1087 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1088 CC_OP_LOGICW, 1089 CC_OP_LOGICL, 1090 CC_OP_LOGICQ, 1091 1092 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1093 CC_OP_INCW, 1094 CC_OP_INCL, 1095 CC_OP_INCQ, 1096 1097 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1098 CC_OP_DECW, 1099 CC_OP_DECL, 1100 CC_OP_DECQ, 1101 1102 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1103 CC_OP_SHLW, 1104 CC_OP_SHLL, 1105 CC_OP_SHLQ, 1106 1107 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1108 CC_OP_SARW, 1109 CC_OP_SARL, 1110 CC_OP_SARQ, 1111 1112 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1113 CC_OP_BMILGW, 1114 CC_OP_BMILGL, 1115 CC_OP_BMILGQ, 1116 1117 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1118 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1119 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1120 1121 CC_OP_CLR, /* Z set, all other flags clear. */ 1122 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1123 1124 CC_OP_NB, 1125 } CCOp; 1126 1127 typedef struct SegmentCache { 1128 uint32_t selector; 1129 target_ulong base; 1130 uint32_t limit; 1131 uint32_t flags; 1132 } SegmentCache; 1133 1134 #define MMREG_UNION(n, bits) \ 1135 union n { \ 1136 uint8_t _b_##n[(bits)/8]; \ 1137 uint16_t _w_##n[(bits)/16]; \ 1138 uint32_t _l_##n[(bits)/32]; \ 1139 uint64_t _q_##n[(bits)/64]; \ 1140 float32 _s_##n[(bits)/32]; \ 1141 float64 _d_##n[(bits)/64]; \ 1142 } 1143 1144 typedef union { 1145 uint8_t _b[16]; 1146 uint16_t _w[8]; 1147 uint32_t _l[4]; 1148 uint64_t _q[2]; 1149 } XMMReg; 1150 1151 typedef union { 1152 uint8_t _b[32]; 1153 uint16_t _w[16]; 1154 uint32_t _l[8]; 1155 uint64_t _q[4]; 1156 } YMMReg; 1157 1158 typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1159 typedef MMREG_UNION(MMXReg, 64) MMXReg; 1160 1161 typedef struct BNDReg { 1162 uint64_t lb; 1163 uint64_t ub; 1164 } BNDReg; 1165 1166 typedef struct BNDCSReg { 1167 uint64_t cfgu; 1168 uint64_t sts; 1169 } BNDCSReg; 1170 1171 #define BNDCFG_ENABLE 1ULL 1172 #define BNDCFG_BNDPRESERVE 2ULL 1173 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1174 1175 #ifdef HOST_WORDS_BIGENDIAN 1176 #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1177 #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1178 #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1179 #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1180 #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1181 #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1182 1183 #define MMX_B(n) _b_MMXReg[7 - (n)] 1184 #define MMX_W(n) _w_MMXReg[3 - (n)] 1185 #define MMX_L(n) _l_MMXReg[1 - (n)] 1186 #define MMX_S(n) _s_MMXReg[1 - (n)] 1187 #else 1188 #define ZMM_B(n) _b_ZMMReg[n] 1189 #define ZMM_W(n) _w_ZMMReg[n] 1190 #define ZMM_L(n) _l_ZMMReg[n] 1191 #define ZMM_S(n) _s_ZMMReg[n] 1192 #define ZMM_Q(n) _q_ZMMReg[n] 1193 #define ZMM_D(n) _d_ZMMReg[n] 1194 1195 #define MMX_B(n) _b_MMXReg[n] 1196 #define MMX_W(n) _w_MMXReg[n] 1197 #define MMX_L(n) _l_MMXReg[n] 1198 #define MMX_S(n) _s_MMXReg[n] 1199 #endif 1200 #define MMX_Q(n) _q_MMXReg[n] 1201 1202 typedef union { 1203 floatx80 d __attribute__((aligned(16))); 1204 MMXReg mmx; 1205 } FPReg; 1206 1207 typedef struct { 1208 uint64_t base; 1209 uint64_t mask; 1210 } MTRRVar; 1211 1212 #define CPU_NB_REGS64 16 1213 #define CPU_NB_REGS32 8 1214 1215 #ifdef TARGET_X86_64 1216 #define CPU_NB_REGS CPU_NB_REGS64 1217 #else 1218 #define CPU_NB_REGS CPU_NB_REGS32 1219 #endif 1220 1221 #define MAX_FIXED_COUNTERS 3 1222 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1223 1224 #define TARGET_INSN_START_EXTRA_WORDS 1 1225 1226 #define NB_OPMASK_REGS 8 1227 1228 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1229 * that APIC ID hasn't been set yet 1230 */ 1231 #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1232 1233 typedef union X86LegacyXSaveArea { 1234 struct { 1235 uint16_t fcw; 1236 uint16_t fsw; 1237 uint8_t ftw; 1238 uint8_t reserved; 1239 uint16_t fpop; 1240 uint64_t fpip; 1241 uint64_t fpdp; 1242 uint32_t mxcsr; 1243 uint32_t mxcsr_mask; 1244 FPReg fpregs[8]; 1245 uint8_t xmm_regs[16][16]; 1246 }; 1247 uint8_t data[512]; 1248 } X86LegacyXSaveArea; 1249 1250 typedef struct X86XSaveHeader { 1251 uint64_t xstate_bv; 1252 uint64_t xcomp_bv; 1253 uint64_t reserve0; 1254 uint8_t reserved[40]; 1255 } X86XSaveHeader; 1256 1257 /* Ext. save area 2: AVX State */ 1258 typedef struct XSaveAVX { 1259 uint8_t ymmh[16][16]; 1260 } XSaveAVX; 1261 1262 /* Ext. save area 3: BNDREG */ 1263 typedef struct XSaveBNDREG { 1264 BNDReg bnd_regs[4]; 1265 } XSaveBNDREG; 1266 1267 /* Ext. save area 4: BNDCSR */ 1268 typedef union XSaveBNDCSR { 1269 BNDCSReg bndcsr; 1270 uint8_t data[64]; 1271 } XSaveBNDCSR; 1272 1273 /* Ext. save area 5: Opmask */ 1274 typedef struct XSaveOpmask { 1275 uint64_t opmask_regs[NB_OPMASK_REGS]; 1276 } XSaveOpmask; 1277 1278 /* Ext. save area 6: ZMM_Hi256 */ 1279 typedef struct XSaveZMM_Hi256 { 1280 uint8_t zmm_hi256[16][32]; 1281 } XSaveZMM_Hi256; 1282 1283 /* Ext. save area 7: Hi16_ZMM */ 1284 typedef struct XSaveHi16_ZMM { 1285 uint8_t hi16_zmm[16][64]; 1286 } XSaveHi16_ZMM; 1287 1288 /* Ext. save area 9: PKRU state */ 1289 typedef struct XSavePKRU { 1290 uint32_t pkru; 1291 uint32_t padding; 1292 } XSavePKRU; 1293 1294 typedef struct X86XSaveArea { 1295 X86LegacyXSaveArea legacy; 1296 X86XSaveHeader header; 1297 1298 /* Extended save areas: */ 1299 1300 /* AVX State: */ 1301 XSaveAVX avx_state; 1302 uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 1303 /* MPX State: */ 1304 XSaveBNDREG bndreg_state; 1305 XSaveBNDCSR bndcsr_state; 1306 /* AVX-512 State: */ 1307 XSaveOpmask opmask_state; 1308 XSaveZMM_Hi256 zmm_hi256_state; 1309 XSaveHi16_ZMM hi16_zmm_state; 1310 /* PKRU State: */ 1311 XSavePKRU pkru_state; 1312 } X86XSaveArea; 1313 1314 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 1315 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1316 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 1317 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1318 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 1319 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1320 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 1321 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1322 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 1323 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1324 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 1325 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1326 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 1327 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1328 1329 typedef enum TPRAccess { 1330 TPR_ACCESS_READ, 1331 TPR_ACCESS_WRITE, 1332 } TPRAccess; 1333 1334 /* Cache information data structures: */ 1335 1336 enum CacheType { 1337 DATA_CACHE, 1338 INSTRUCTION_CACHE, 1339 UNIFIED_CACHE 1340 }; 1341 1342 typedef struct CPUCacheInfo { 1343 enum CacheType type; 1344 uint8_t level; 1345 /* Size in bytes */ 1346 uint32_t size; 1347 /* Line size, in bytes */ 1348 uint16_t line_size; 1349 /* 1350 * Associativity. 1351 * Note: representation of fully-associative caches is not implemented 1352 */ 1353 uint8_t associativity; 1354 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 1355 uint8_t partitions; 1356 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 1357 uint32_t sets; 1358 /* 1359 * Lines per tag. 1360 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 1361 * (Is this synonym to @partitions?) 1362 */ 1363 uint8_t lines_per_tag; 1364 1365 /* Self-initializing cache */ 1366 bool self_init; 1367 /* 1368 * WBINVD/INVD is not guaranteed to act upon lower level caches of 1369 * non-originating threads sharing this cache. 1370 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 1371 */ 1372 bool no_invd_sharing; 1373 /* 1374 * Cache is inclusive of lower cache levels. 1375 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 1376 */ 1377 bool inclusive; 1378 /* 1379 * A complex function is used to index the cache, potentially using all 1380 * address bits. CPUID[4].EDX[bit 2]. 1381 */ 1382 bool complex_indexing; 1383 } CPUCacheInfo; 1384 1385 1386 typedef struct CPUCaches { 1387 CPUCacheInfo *l1d_cache; 1388 CPUCacheInfo *l1i_cache; 1389 CPUCacheInfo *l2_cache; 1390 CPUCacheInfo *l3_cache; 1391 } CPUCaches; 1392 1393 typedef struct HVFX86LazyFlags { 1394 target_ulong result; 1395 target_ulong auxbits; 1396 } HVFX86LazyFlags; 1397 1398 typedef struct CPUX86State { 1399 /* standard registers */ 1400 target_ulong regs[CPU_NB_REGS]; 1401 target_ulong eip; 1402 target_ulong eflags; /* eflags register. During CPU emulation, CC 1403 flags and DF are set to zero because they are 1404 stored elsewhere */ 1405 1406 /* emulator internal eflags handling */ 1407 target_ulong cc_dst; 1408 target_ulong cc_src; 1409 target_ulong cc_src2; 1410 uint32_t cc_op; 1411 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1412 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1413 are known at translation time. */ 1414 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1415 1416 /* segments */ 1417 SegmentCache segs[6]; /* selector values */ 1418 SegmentCache ldt; 1419 SegmentCache tr; 1420 SegmentCache gdt; /* only base and limit are used */ 1421 SegmentCache idt; /* only base and limit are used */ 1422 1423 target_ulong cr[5]; /* NOTE: cr1 is unused */ 1424 int32_t a20_mask; 1425 1426 BNDReg bnd_regs[4]; 1427 BNDCSReg bndcs_regs; 1428 uint64_t msr_bndcfgs; 1429 uint64_t efer; 1430 1431 /* Beginning of state preserved by INIT (dummy marker). */ 1432 struct {} start_init_save; 1433 1434 /* FPU state */ 1435 unsigned int fpstt; /* top of stack index */ 1436 uint16_t fpus; 1437 uint16_t fpuc; 1438 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1439 FPReg fpregs[8]; 1440 /* KVM-only so far */ 1441 uint16_t fpop; 1442 uint64_t fpip; 1443 uint64_t fpdp; 1444 1445 /* emulator internal variables */ 1446 float_status fp_status; 1447 floatx80 ft0; 1448 1449 float_status mmx_status; /* for 3DNow! float ops */ 1450 float_status sse_status; 1451 uint32_t mxcsr; 1452 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1453 ZMMReg xmm_t0; 1454 MMXReg mmx_t0; 1455 1456 XMMReg ymmh_regs[CPU_NB_REGS]; 1457 1458 uint64_t opmask_regs[NB_OPMASK_REGS]; 1459 YMMReg zmmh_regs[CPU_NB_REGS]; 1460 ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1461 1462 /* sysenter registers */ 1463 uint32_t sysenter_cs; 1464 target_ulong sysenter_esp; 1465 target_ulong sysenter_eip; 1466 uint64_t star; 1467 1468 uint64_t vm_hsave; 1469 1470 #ifdef TARGET_X86_64 1471 target_ulong lstar; 1472 target_ulong cstar; 1473 target_ulong fmask; 1474 target_ulong kernelgsbase; 1475 #endif 1476 1477 uint64_t tsc; 1478 uint64_t tsc_adjust; 1479 uint64_t tsc_deadline; 1480 uint64_t tsc_aux; 1481 1482 uint64_t xcr0; 1483 1484 uint64_t mcg_status; 1485 uint64_t msr_ia32_misc_enable; 1486 uint64_t msr_ia32_feature_control; 1487 1488 uint64_t msr_fixed_ctr_ctrl; 1489 uint64_t msr_global_ctrl; 1490 uint64_t msr_global_status; 1491 uint64_t msr_global_ovf_ctrl; 1492 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1493 uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1494 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1495 1496 uint64_t pat; 1497 uint32_t smbase; 1498 uint64_t msr_smi_count; 1499 1500 uint32_t pkru; 1501 uint32_t pkrs; 1502 uint32_t tsx_ctrl; 1503 1504 uint64_t spec_ctrl; 1505 uint64_t virt_ssbd; 1506 1507 /* End of state preserved by INIT (dummy marker). */ 1508 struct {} end_init_save; 1509 1510 uint64_t system_time_msr; 1511 uint64_t wall_clock_msr; 1512 uint64_t steal_time_msr; 1513 uint64_t async_pf_en_msr; 1514 uint64_t async_pf_int_msr; 1515 uint64_t pv_eoi_en_msr; 1516 uint64_t poll_control_msr; 1517 1518 /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1519 uint64_t msr_hv_hypercall; 1520 uint64_t msr_hv_guest_os_id; 1521 uint64_t msr_hv_tsc; 1522 1523 /* Per-VCPU HV MSRs */ 1524 uint64_t msr_hv_vapic; 1525 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1526 uint64_t msr_hv_runtime; 1527 uint64_t msr_hv_synic_control; 1528 uint64_t msr_hv_synic_evt_page; 1529 uint64_t msr_hv_synic_msg_page; 1530 uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 1531 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 1532 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1533 uint64_t msr_hv_reenlightenment_control; 1534 uint64_t msr_hv_tsc_emulation_control; 1535 uint64_t msr_hv_tsc_emulation_status; 1536 1537 uint64_t msr_rtit_ctrl; 1538 uint64_t msr_rtit_status; 1539 uint64_t msr_rtit_output_base; 1540 uint64_t msr_rtit_output_mask; 1541 uint64_t msr_rtit_cr3_match; 1542 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1543 1544 /* exception/interrupt handling */ 1545 int error_code; 1546 int exception_is_int; 1547 target_ulong exception_next_eip; 1548 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1549 union { 1550 struct CPUBreakpoint *cpu_breakpoint[4]; 1551 struct CPUWatchpoint *cpu_watchpoint[4]; 1552 }; /* break/watchpoints for dr[0..3] */ 1553 int old_exception; /* exception in flight */ 1554 1555 uint64_t vm_vmcb; 1556 uint64_t tsc_offset; 1557 uint64_t intercept; 1558 uint16_t intercept_cr_read; 1559 uint16_t intercept_cr_write; 1560 uint16_t intercept_dr_read; 1561 uint16_t intercept_dr_write; 1562 uint32_t intercept_exceptions; 1563 uint64_t nested_cr3; 1564 uint32_t nested_pg_mode; 1565 uint8_t v_tpr; 1566 1567 /* KVM states, automatically cleared on reset */ 1568 uint8_t nmi_injected; 1569 uint8_t nmi_pending; 1570 1571 uintptr_t retaddr; 1572 1573 /* Fields up to this point are cleared by a CPU reset */ 1574 struct {} end_reset_fields; 1575 1576 /* Fields after this point are preserved across CPU reset. */ 1577 1578 /* processor features (e.g. for CPUID insn) */ 1579 /* Minimum cpuid leaf 7 value */ 1580 uint32_t cpuid_level_func7; 1581 /* Actual cpuid leaf 7 value */ 1582 uint32_t cpuid_min_level_func7; 1583 /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1584 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1585 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1586 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1587 /* Actual level/xlevel/xlevel2 value: */ 1588 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1589 uint32_t cpuid_vendor1; 1590 uint32_t cpuid_vendor2; 1591 uint32_t cpuid_vendor3; 1592 uint32_t cpuid_version; 1593 FeatureWordArray features; 1594 /* Features that were explicitly enabled/disabled */ 1595 FeatureWordArray user_features; 1596 uint32_t cpuid_model[12]; 1597 /* Cache information for CPUID. When legacy-cache=on, the cache data 1598 * on each CPUID leaf will be different, because we keep compatibility 1599 * with old QEMU versions. 1600 */ 1601 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1602 1603 /* MTRRs */ 1604 uint64_t mtrr_fixed[11]; 1605 uint64_t mtrr_deftype; 1606 MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1607 1608 /* For KVM */ 1609 uint32_t mp_state; 1610 int32_t exception_nr; 1611 int32_t interrupt_injected; 1612 uint8_t soft_interrupt; 1613 uint8_t exception_pending; 1614 uint8_t exception_injected; 1615 uint8_t has_error_code; 1616 uint8_t exception_has_payload; 1617 uint64_t exception_payload; 1618 uint32_t ins_len; 1619 uint32_t sipi_vector; 1620 bool tsc_valid; 1621 int64_t tsc_khz; 1622 int64_t user_tsc_khz; /* for sanity check only */ 1623 uint64_t apic_bus_freq; 1624 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 1625 void *xsave_buf; 1626 #endif 1627 #if defined(CONFIG_KVM) 1628 struct kvm_nested_state *nested_state; 1629 #endif 1630 #if defined(CONFIG_HVF) 1631 HVFX86LazyFlags hvf_lflags; 1632 void *hvf_mmio_buf; 1633 #endif 1634 1635 uint64_t mcg_cap; 1636 uint64_t mcg_ctl; 1637 uint64_t mcg_ext_ctl; 1638 uint64_t mce_banks[MCE_BANKS_DEF*4]; 1639 uint64_t xstate_bv; 1640 1641 /* vmstate */ 1642 uint16_t fpus_vmstate; 1643 uint16_t fptag_vmstate; 1644 uint16_t fpregs_format_vmstate; 1645 1646 uint64_t xss; 1647 uint32_t umwait; 1648 1649 TPRAccess tpr_access_type; 1650 1651 unsigned nr_dies; 1652 } CPUX86State; 1653 1654 struct kvm_msrs; 1655 1656 /** 1657 * X86CPU: 1658 * @env: #CPUX86State 1659 * @migratable: If set, only migratable flags will be accepted when "enforce" 1660 * mode is used, and only migratable flags will be included in the "host" 1661 * CPU model. 1662 * 1663 * An x86 CPU. 1664 */ 1665 struct X86CPU { 1666 /*< private >*/ 1667 CPUState parent_obj; 1668 /*< public >*/ 1669 1670 CPUNegativeOffsetState neg; 1671 CPUX86State env; 1672 VMChangeStateEntry *vmsentry; 1673 1674 uint64_t ucode_rev; 1675 1676 uint32_t hyperv_spinlock_attempts; 1677 char *hyperv_vendor; 1678 bool hyperv_synic_kvm_only; 1679 uint64_t hyperv_features; 1680 bool hyperv_passthrough; 1681 OnOffAuto hyperv_no_nonarch_cs; 1682 uint32_t hyperv_vendor_id[3]; 1683 uint32_t hyperv_interface_id[4]; 1684 uint32_t hyperv_version_id[4]; 1685 uint32_t hyperv_limits[3]; 1686 1687 bool check_cpuid; 1688 bool enforce_cpuid; 1689 /* 1690 * Force features to be enabled even if the host doesn't support them. 1691 * This is dangerous and should be done only for testing CPUID 1692 * compatibility. 1693 */ 1694 bool force_features; 1695 bool expose_kvm; 1696 bool expose_tcg; 1697 bool migratable; 1698 bool migrate_smi_count; 1699 bool max_features; /* Enable all supported features automatically */ 1700 uint32_t apic_id; 1701 1702 /* Enables publishing of TSC increment and Local APIC bus frequencies to 1703 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 1704 bool vmware_cpuid_freq; 1705 1706 /* if true the CPUID code directly forward host cache leaves to the guest */ 1707 bool cache_info_passthrough; 1708 1709 /* if true the CPUID code directly forwards 1710 * host monitor/mwait leaves to the guest */ 1711 struct { 1712 uint32_t eax; 1713 uint32_t ebx; 1714 uint32_t ecx; 1715 uint32_t edx; 1716 } mwait; 1717 1718 /* Features that were filtered out because of missing host capabilities */ 1719 FeatureWordArray filtered_features; 1720 1721 /* Enable PMU CPUID bits. This can't be enabled by default yet because 1722 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1723 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1724 * capabilities) directly to the guest. 1725 */ 1726 bool enable_pmu; 1727 1728 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1729 * disabled by default to avoid breaking migration between QEMU with 1730 * different LMCE configurations. 1731 */ 1732 bool enable_lmce; 1733 1734 /* Compatibility bits for old machine types. 1735 * If true present virtual l3 cache for VM, the vcpus in the same virtual 1736 * socket share an virtual l3 cache. 1737 */ 1738 bool enable_l3_cache; 1739 1740 /* Compatibility bits for old machine types. 1741 * If true present the old cache topology information 1742 */ 1743 bool legacy_cache; 1744 1745 /* Compatibility bits for old machine types: */ 1746 bool enable_cpuid_0xb; 1747 1748 /* Enable auto level-increase for all CPUID leaves */ 1749 bool full_cpuid_auto_level; 1750 1751 /* Enable auto level-increase for Intel Processor Trace leave */ 1752 bool intel_pt_auto_level; 1753 1754 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1755 bool fill_mtrr_mask; 1756 1757 /* if true override the phys_bits value with a value read from the host */ 1758 bool host_phys_bits; 1759 1760 /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1761 uint8_t host_phys_bits_limit; 1762 1763 /* Stop SMI delivery for migration compatibility with old machines */ 1764 bool kvm_no_smi_migration; 1765 1766 /* Number of physical address bits supported */ 1767 uint32_t phys_bits; 1768 1769 /* in order to simplify APIC support, we leave this pointer to the 1770 user */ 1771 struct DeviceState *apic_state; 1772 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1773 Notifier machine_done; 1774 1775 struct kvm_msrs *kvm_msr_buf; 1776 1777 int32_t node_id; /* NUMA node this CPU belongs to */ 1778 int32_t socket_id; 1779 int32_t die_id; 1780 int32_t core_id; 1781 int32_t thread_id; 1782 1783 int32_t hv_max_vps; 1784 }; 1785 1786 1787 #ifndef CONFIG_USER_ONLY 1788 extern VMStateDescription vmstate_x86_cpu; 1789 #endif 1790 1791 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1792 1793 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1794 int cpuid, void *opaque); 1795 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1796 int cpuid, void *opaque); 1797 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1798 void *opaque); 1799 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1800 void *opaque); 1801 1802 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1803 Error **errp); 1804 1805 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1806 1807 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1808 MemTxAttrs *attrs); 1809 1810 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1811 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1812 1813 void x86_cpu_list(void); 1814 int cpu_x86_support_mca_broadcast(CPUX86State *env); 1815 1816 int cpu_get_pic_interrupt(CPUX86State *s); 1817 /* MSDOS compatibility mode FPU exception support */ 1818 void x86_register_ferr_irq(qemu_irq irq); 1819 void cpu_set_ignne(void); 1820 /* mpx_helper.c */ 1821 void cpu_sync_bndcs_hflags(CPUX86State *env); 1822 1823 /* this function must always be used to load data in the segment 1824 cache: it synchronizes the hflags with the segment cache values */ 1825 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1826 X86Seg seg_reg, unsigned int selector, 1827 target_ulong base, 1828 unsigned int limit, 1829 unsigned int flags) 1830 { 1831 SegmentCache *sc; 1832 unsigned int new_hflags; 1833 1834 sc = &env->segs[seg_reg]; 1835 sc->selector = selector; 1836 sc->base = base; 1837 sc->limit = limit; 1838 sc->flags = flags; 1839 1840 /* update the hidden flags */ 1841 { 1842 if (seg_reg == R_CS) { 1843 #ifdef TARGET_X86_64 1844 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1845 /* long mode */ 1846 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1847 env->hflags &= ~(HF_ADDSEG_MASK); 1848 } else 1849 #endif 1850 { 1851 /* legacy / compatibility case */ 1852 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1853 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1854 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1855 new_hflags; 1856 } 1857 } 1858 if (seg_reg == R_SS) { 1859 int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1860 #if HF_CPL_MASK != 3 1861 #error HF_CPL_MASK is hardcoded 1862 #endif 1863 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1864 /* Possibly switch between BNDCFGS and BNDCFGU */ 1865 cpu_sync_bndcs_hflags(env); 1866 } 1867 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1868 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1869 if (env->hflags & HF_CS64_MASK) { 1870 /* zero base assumed for DS, ES and SS in long mode */ 1871 } else if (!(env->cr[0] & CR0_PE_MASK) || 1872 (env->eflags & VM_MASK) || 1873 !(env->hflags & HF_CS32_MASK)) { 1874 /* XXX: try to avoid this test. The problem comes from the 1875 fact that is real mode or vm86 mode we only modify the 1876 'base' and 'selector' fields of the segment cache to go 1877 faster. A solution may be to force addseg to one in 1878 translate-i386.c. */ 1879 new_hflags |= HF_ADDSEG_MASK; 1880 } else { 1881 new_hflags |= ((env->segs[R_DS].base | 1882 env->segs[R_ES].base | 1883 env->segs[R_SS].base) != 0) << 1884 HF_ADDSEG_SHIFT; 1885 } 1886 env->hflags = (env->hflags & 1887 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1888 } 1889 } 1890 1891 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1892 uint8_t sipi_vector) 1893 { 1894 CPUState *cs = CPU(cpu); 1895 CPUX86State *env = &cpu->env; 1896 1897 env->eip = 0; 1898 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1899 sipi_vector << 12, 1900 env->segs[R_CS].limit, 1901 env->segs[R_CS].flags); 1902 cs->halted = 0; 1903 } 1904 1905 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1906 target_ulong *base, unsigned int *limit, 1907 unsigned int *flags); 1908 1909 /* op_helper.c */ 1910 /* used for debug or cpu save/restore */ 1911 1912 /* cpu-exec.c */ 1913 /* the following helpers are only usable in user mode simulation as 1914 they can trigger unexpected exceptions */ 1915 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); 1916 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1917 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 1918 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 1919 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1920 1921 /* you can call this signal handler from your SIGBUS and SIGSEGV 1922 signal handlers to inform the virtual CPU of exceptions. non zero 1923 is returned if the signal was handled by the virtual CPU. */ 1924 int cpu_x86_signal_handler(int host_signum, void *pinfo, 1925 void *puc); 1926 1927 /* cpu.c */ 1928 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1929 uint32_t *eax, uint32_t *ebx, 1930 uint32_t *ecx, uint32_t *edx); 1931 void cpu_clear_apic_feature(CPUX86State *env); 1932 void host_cpuid(uint32_t function, uint32_t count, 1933 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1934 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1935 1936 /* helper.c */ 1937 void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1938 1939 #ifndef CONFIG_USER_ONLY 1940 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1941 { 1942 return !!attrs.secure; 1943 } 1944 1945 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1946 { 1947 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1948 } 1949 1950 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1951 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1952 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1953 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1954 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1955 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1956 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1957 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1958 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1959 #endif 1960 1961 /* will be suppressed */ 1962 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1963 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1964 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1965 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1966 1967 /* hw/pc.c */ 1968 uint64_t cpu_get_tsc(CPUX86State *env); 1969 1970 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1971 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1972 #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1973 1974 #ifdef TARGET_X86_64 1975 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1976 #else 1977 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1978 #endif 1979 1980 #define cpu_signal_handler cpu_x86_signal_handler 1981 #define cpu_list x86_cpu_list 1982 1983 /* MMU modes definitions */ 1984 #define MMU_KSMAP_IDX 0 1985 #define MMU_USER_IDX 1 1986 #define MMU_KNOSMAP_IDX 2 1987 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1988 { 1989 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1990 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1991 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1992 } 1993 1994 static inline int cpu_mmu_index_kernel(CPUX86State *env) 1995 { 1996 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1997 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1998 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1999 } 2000 2001 #define CC_DST (env->cc_dst) 2002 #define CC_SRC (env->cc_src) 2003 #define CC_SRC2 (env->cc_src2) 2004 #define CC_OP (env->cc_op) 2005 2006 typedef CPUX86State CPUArchState; 2007 typedef X86CPU ArchCPU; 2008 2009 #include "exec/cpu-all.h" 2010 #include "svm.h" 2011 2012 #if !defined(CONFIG_USER_ONLY) 2013 #include "hw/i386/apic.h" 2014 #endif 2015 2016 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2017 target_ulong *cs_base, uint32_t *flags) 2018 { 2019 *cs_base = env->segs[R_CS].base; 2020 *pc = *cs_base + env->eip; 2021 *flags = env->hflags | 2022 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2023 } 2024 2025 void do_cpu_init(X86CPU *cpu); 2026 void do_cpu_sipi(X86CPU *cpu); 2027 2028 #define MCE_INJECT_BROADCAST 1 2029 #define MCE_INJECT_UNCOND_AO 2 2030 2031 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2032 uint64_t status, uint64_t mcg_status, uint64_t addr, 2033 uint64_t misc, int flags); 2034 2035 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2036 2037 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2038 { 2039 uint32_t eflags = env->eflags; 2040 if (tcg_enabled()) { 2041 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 2042 } 2043 return eflags; 2044 } 2045 2046 2047 /* load efer and update the corresponding hflags. XXX: do consistency 2048 checks with cpuid bits? */ 2049 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 2050 { 2051 env->efer = val; 2052 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 2053 if (env->efer & MSR_EFER_LMA) { 2054 env->hflags |= HF_LMA_MASK; 2055 } 2056 if (env->efer & MSR_EFER_SVME) { 2057 env->hflags |= HF_SVME_MASK; 2058 } 2059 } 2060 2061 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2062 { 2063 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2064 } 2065 2066 static inline int32_t x86_get_a20_mask(CPUX86State *env) 2067 { 2068 if (env->hflags & HF_SMM_MASK) { 2069 return -1; 2070 } else { 2071 return env->a20_mask; 2072 } 2073 } 2074 2075 static inline bool cpu_has_vmx(CPUX86State *env) 2076 { 2077 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 2078 } 2079 2080 static inline bool cpu_has_svm(CPUX86State *env) 2081 { 2082 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2083 } 2084 2085 /* 2086 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 2087 * Since it was set, CR4.VMXE must remain set as long as vCPU is in 2088 * VMX operation. This is because CR4.VMXE is one of the bits set 2089 * in MSR_IA32_VMX_CR4_FIXED1. 2090 * 2091 * There is one exception to above statement when vCPU enters SMM mode. 2092 * When a vCPU enters SMM mode, it temporarily exit VMX operation and 2093 * may also reset CR4.VMXE during execution in SMM mode. 2094 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 2095 * and CR4.VMXE is restored to it's original value of being set. 2096 * 2097 * Therefore, when vCPU is not in SMM mode, we can infer whether 2098 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 2099 * know for certain. 2100 */ 2101 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 2102 { 2103 return cpu_has_vmx(env) && 2104 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 2105 } 2106 2107 /* fpu_helper.c */ 2108 void update_fp_status(CPUX86State *env); 2109 void update_mxcsr_status(CPUX86State *env); 2110 void update_mxcsr_from_sse_status(CPUX86State *env); 2111 2112 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 2113 { 2114 env->mxcsr = mxcsr; 2115 if (tcg_enabled()) { 2116 update_mxcsr_status(env); 2117 } 2118 } 2119 2120 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 2121 { 2122 env->fpuc = fpuc; 2123 if (tcg_enabled()) { 2124 update_fp_status(env); 2125 } 2126 } 2127 2128 /* mem_helper.c */ 2129 void helper_lock_init(void); 2130 2131 /* svm_helper.c */ 2132 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 2133 uint64_t param, uintptr_t retaddr); 2134 /* apic.c */ 2135 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2136 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2137 TPRAccess access); 2138 2139 2140 /* Change the value of a KVM-specific default 2141 * 2142 * If value is NULL, no default will be set and the original 2143 * value from the CPU model table will be kept. 2144 * 2145 * It is valid to call this function only for properties that 2146 * are already present in the kvm_default_props table. 2147 */ 2148 void x86_cpu_change_kvm_default(const char *prop, const char *value); 2149 2150 /* Special values for X86CPUVersion: */ 2151 2152 /* Resolve to latest CPU version */ 2153 #define CPU_VERSION_LATEST -1 2154 2155 /* 2156 * Resolve to version defined by current machine type. 2157 * See x86_cpu_set_default_version() 2158 */ 2159 #define CPU_VERSION_AUTO -2 2160 2161 /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2162 #define CPU_VERSION_LEGACY 0 2163 2164 typedef int X86CPUVersion; 2165 2166 /* 2167 * Set default CPU model version for CPU models having 2168 * version == CPU_VERSION_AUTO. 2169 */ 2170 void x86_cpu_set_default_version(X86CPUVersion version); 2171 2172 #define APIC_DEFAULT_ADDRESS 0xfee00000 2173 #define APIC_SPACE_SIZE 0x100000 2174 2175 /* cpu-dump.c */ 2176 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2177 2178 /* cpu.c */ 2179 bool cpu_is_bsp(X86CPU *cpu); 2180 2181 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 2182 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 2183 void x86_update_hflags(CPUX86State* env); 2184 2185 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 2186 { 2187 return !!(cpu->hyperv_features & BIT(feat)); 2188 } 2189 2190 #if defined(TARGET_X86_64) && \ 2191 defined(CONFIG_USER_ONLY) && \ 2192 defined(CONFIG_LINUX) 2193 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2194 #endif 2195 2196 #endif /* I386_CPU_H */ 2197