xref: /openbmc/qemu/target/i386/cpu.h (revision f7ff24a6e9259726db08e36cdc28645c0a3b1a70)
1  /*
2   * i386 virtual CPU header
3   *
4   *  Copyright (c) 2003 Fabrice Bellard
5   *
6   * This library is free software; you can redistribute it and/or
7   * modify it under the terms of the GNU Lesser General Public
8   * License as published by the Free Software Foundation; either
9   * version 2.1 of the License, or (at your option) any later version.
10   *
11   * This library is distributed in the hope that it will be useful,
12   * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14   * Lesser General Public License for more details.
15   *
16   * You should have received a copy of the GNU Lesser General Public
17   * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18   */
19  
20  #ifndef I386_CPU_H
21  #define I386_CPU_H
22  
23  #include "sysemu/tcg.h"
24  #include "cpu-qom.h"
25  #include "kvm/hyperv-proto.h"
26  #include "exec/cpu-defs.h"
27  #include "exec/memop.h"
28  #include "hw/i386/topology.h"
29  #include "qapi/qapi-types-common.h"
30  #include "qemu/cpu-float.h"
31  #include "qemu/timer.h"
32  
33  #define XEN_NR_VIRQS 24
34  
35  #define KVM_HAVE_MCE_INJECTION 1
36  
37  /* support for self modifying code even if the modified instruction is
38     close to the modifying instruction */
39  #define TARGET_HAS_PRECISE_SMC
40  
41  #ifdef TARGET_X86_64
42  #define I386_ELF_MACHINE  EM_X86_64
43  #define ELF_MACHINE_UNAME "x86_64"
44  #else
45  #define I386_ELF_MACHINE  EM_386
46  #define ELF_MACHINE_UNAME "i686"
47  #endif
48  
49  enum {
50      R_EAX = 0,
51      R_ECX = 1,
52      R_EDX = 2,
53      R_EBX = 3,
54      R_ESP = 4,
55      R_EBP = 5,
56      R_ESI = 6,
57      R_EDI = 7,
58      R_R8 = 8,
59      R_R9 = 9,
60      R_R10 = 10,
61      R_R11 = 11,
62      R_R12 = 12,
63      R_R13 = 13,
64      R_R14 = 14,
65      R_R15 = 15,
66  
67      R_AL = 0,
68      R_CL = 1,
69      R_DL = 2,
70      R_BL = 3,
71      R_AH = 4,
72      R_CH = 5,
73      R_DH = 6,
74      R_BH = 7,
75  };
76  
77  typedef enum X86Seg {
78      R_ES = 0,
79      R_CS = 1,
80      R_SS = 2,
81      R_DS = 3,
82      R_FS = 4,
83      R_GS = 5,
84      R_LDTR = 6,
85      R_TR = 7,
86  } X86Seg;
87  
88  /* segment descriptor fields */
89  #define DESC_G_SHIFT    23
90  #define DESC_G_MASK     (1 << DESC_G_SHIFT)
91  #define DESC_B_SHIFT    22
92  #define DESC_B_MASK     (1 << DESC_B_SHIFT)
93  #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
94  #define DESC_L_MASK     (1 << DESC_L_SHIFT)
95  #define DESC_AVL_SHIFT  20
96  #define DESC_AVL_MASK   (1 << DESC_AVL_SHIFT)
97  #define DESC_P_SHIFT    15
98  #define DESC_P_MASK     (1 << DESC_P_SHIFT)
99  #define DESC_DPL_SHIFT  13
100  #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
101  #define DESC_S_SHIFT    12
102  #define DESC_S_MASK     (1 << DESC_S_SHIFT)
103  #define DESC_TYPE_SHIFT 8
104  #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
105  #define DESC_A_MASK     (1 << 8)
106  
107  #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
108  #define DESC_C_MASK     (1 << 10) /* code: conforming */
109  #define DESC_R_MASK     (1 << 9)  /* code: readable */
110  
111  #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
112  #define DESC_W_MASK     (1 << 9)  /* data: writable */
113  
114  #define DESC_TSS_BUSY_MASK (1 << 9)
115  
116  /* eflags masks */
117  #define CC_C    0x0001
118  #define CC_P    0x0004
119  #define CC_A    0x0010
120  #define CC_Z    0x0040
121  #define CC_S    0x0080
122  #define CC_O    0x0800
123  
124  #define TF_SHIFT   8
125  #define IOPL_SHIFT 12
126  #define VM_SHIFT   17
127  
128  #define TF_MASK                 0x00000100
129  #define IF_MASK                 0x00000200
130  #define DF_MASK                 0x00000400
131  #define IOPL_MASK               0x00003000
132  #define NT_MASK                 0x00004000
133  #define RF_MASK                 0x00010000
134  #define VM_MASK                 0x00020000
135  #define AC_MASK                 0x00040000
136  #define VIF_MASK                0x00080000
137  #define VIP_MASK                0x00100000
138  #define ID_MASK                 0x00200000
139  
140  /* hidden flags - used internally by qemu to represent additional cpu
141     states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
142     avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
143     positions to ease oring with eflags. */
144  /* current cpl */
145  #define HF_CPL_SHIFT         0
146  /* true if hardware interrupts must be disabled for next instruction */
147  #define HF_INHIBIT_IRQ_SHIFT 3
148  /* 16 or 32 segments */
149  #define HF_CS32_SHIFT        4
150  #define HF_SS32_SHIFT        5
151  /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
152  #define HF_ADDSEG_SHIFT      6
153  /* copy of CR0.PE (protected mode) */
154  #define HF_PE_SHIFT          7
155  #define HF_TF_SHIFT          8 /* must be same as eflags */
156  #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
157  #define HF_EM_SHIFT         10
158  #define HF_TS_SHIFT         11
159  #define HF_IOPL_SHIFT       12 /* must be same as eflags */
160  #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
161  #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
162  #define HF_RF_SHIFT         16 /* must be same as eflags */
163  #define HF_VM_SHIFT         17 /* must be same as eflags */
164  #define HF_AC_SHIFT         18 /* must be same as eflags */
165  #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
166  #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
167  #define HF_GUEST_SHIFT      21 /* SVM intercepts are active */
168  #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
169  #define HF_SMAP_SHIFT       23 /* CR4.SMAP */
170  #define HF_IOBPT_SHIFT      24 /* an io breakpoint enabled */
171  #define HF_MPX_EN_SHIFT     25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
172  #define HF_MPX_IU_SHIFT     26 /* BND registers in-use */
173  #define HF_UMIP_SHIFT       27 /* CR4.UMIP */
174  #define HF_AVX_EN_SHIFT     28 /* AVX Enabled (CR4+XCR0) */
175  
176  #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
177  #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
178  #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
179  #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
180  #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
181  #define HF_PE_MASK           (1 << HF_PE_SHIFT)
182  #define HF_TF_MASK           (1 << HF_TF_SHIFT)
183  #define HF_MP_MASK           (1 << HF_MP_SHIFT)
184  #define HF_EM_MASK           (1 << HF_EM_SHIFT)
185  #define HF_TS_MASK           (1 << HF_TS_SHIFT)
186  #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
187  #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
188  #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
189  #define HF_RF_MASK           (1 << HF_RF_SHIFT)
190  #define HF_VM_MASK           (1 << HF_VM_SHIFT)
191  #define HF_AC_MASK           (1 << HF_AC_SHIFT)
192  #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
193  #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
194  #define HF_GUEST_MASK        (1 << HF_GUEST_SHIFT)
195  #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
196  #define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
197  #define HF_IOBPT_MASK        (1 << HF_IOBPT_SHIFT)
198  #define HF_MPX_EN_MASK       (1 << HF_MPX_EN_SHIFT)
199  #define HF_MPX_IU_MASK       (1 << HF_MPX_IU_SHIFT)
200  #define HF_UMIP_MASK         (1 << HF_UMIP_SHIFT)
201  #define HF_AVX_EN_MASK       (1 << HF_AVX_EN_SHIFT)
202  
203  /* hflags2 */
204  
205  #define HF2_GIF_SHIFT            0 /* if set CPU takes interrupts */
206  #define HF2_HIF_SHIFT            1 /* value of IF_MASK when entering SVM */
207  #define HF2_NMI_SHIFT            2 /* CPU serving NMI */
208  #define HF2_VINTR_SHIFT          3 /* value of V_INTR_MASKING bit */
209  #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
210  #define HF2_MPX_PR_SHIFT         5 /* BNDCFGx.BNDPRESERVE */
211  #define HF2_NPT_SHIFT            6 /* Nested Paging enabled */
212  #define HF2_IGNNE_SHIFT          7 /* Ignore CR0.NE=0 */
213  #define HF2_VGIF_SHIFT           8 /* Can take VIRQ*/
214  
215  #define HF2_GIF_MASK            (1 << HF2_GIF_SHIFT)
216  #define HF2_HIF_MASK            (1 << HF2_HIF_SHIFT)
217  #define HF2_NMI_MASK            (1 << HF2_NMI_SHIFT)
218  #define HF2_VINTR_MASK          (1 << HF2_VINTR_SHIFT)
219  #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
220  #define HF2_MPX_PR_MASK         (1 << HF2_MPX_PR_SHIFT)
221  #define HF2_NPT_MASK            (1 << HF2_NPT_SHIFT)
222  #define HF2_IGNNE_MASK          (1 << HF2_IGNNE_SHIFT)
223  #define HF2_VGIF_MASK           (1 << HF2_VGIF_SHIFT)
224  
225  #define CR0_PE_SHIFT 0
226  #define CR0_MP_SHIFT 1
227  
228  #define CR0_PE_MASK  (1U << 0)
229  #define CR0_MP_MASK  (1U << 1)
230  #define CR0_EM_MASK  (1U << 2)
231  #define CR0_TS_MASK  (1U << 3)
232  #define CR0_ET_MASK  (1U << 4)
233  #define CR0_NE_MASK  (1U << 5)
234  #define CR0_WP_MASK  (1U << 16)
235  #define CR0_AM_MASK  (1U << 18)
236  #define CR0_NW_MASK  (1U << 29)
237  #define CR0_CD_MASK  (1U << 30)
238  #define CR0_PG_MASK  (1U << 31)
239  
240  #define CR4_VME_MASK  (1U << 0)
241  #define CR4_PVI_MASK  (1U << 1)
242  #define CR4_TSD_MASK  (1U << 2)
243  #define CR4_DE_MASK   (1U << 3)
244  #define CR4_PSE_MASK  (1U << 4)
245  #define CR4_PAE_MASK  (1U << 5)
246  #define CR4_MCE_MASK  (1U << 6)
247  #define CR4_PGE_MASK  (1U << 7)
248  #define CR4_PCE_MASK  (1U << 8)
249  #define CR4_OSFXSR_SHIFT 9
250  #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
251  #define CR4_OSXMMEXCPT_MASK  (1U << 10)
252  #define CR4_UMIP_MASK   (1U << 11)
253  #define CR4_LA57_MASK   (1U << 12)
254  #define CR4_VMXE_MASK   (1U << 13)
255  #define CR4_SMXE_MASK   (1U << 14)
256  #define CR4_FSGSBASE_MASK (1U << 16)
257  #define CR4_PCIDE_MASK  (1U << 17)
258  #define CR4_OSXSAVE_MASK (1U << 18)
259  #define CR4_SMEP_MASK   (1U << 20)
260  #define CR4_SMAP_MASK   (1U << 21)
261  #define CR4_PKE_MASK   (1U << 22)
262  #define CR4_PKS_MASK   (1U << 24)
263  #define CR4_LAM_SUP_MASK (1U << 28)
264  
265  #ifdef TARGET_X86_64
266  #define CR4_FRED_MASK   (1ULL << 32)
267  #else
268  #define CR4_FRED_MASK   0
269  #endif
270  
271  #define CR4_RESERVED_MASK \
272  (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
273                  | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
274                  | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
275                  | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
276                  | CR4_LA57_MASK \
277                  | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
278                  | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \
279                  | CR4_LAM_SUP_MASK | CR4_FRED_MASK))
280  
281  #define DR6_BD          (1 << 13)
282  #define DR6_BS          (1 << 14)
283  #define DR6_BT          (1 << 15)
284  #define DR6_FIXED_1     0xffff0ff0
285  
286  #define DR7_GD          (1 << 13)
287  #define DR7_TYPE_SHIFT  16
288  #define DR7_LEN_SHIFT   18
289  #define DR7_FIXED_1     0x00000400
290  #define DR7_GLOBAL_BP_MASK   0xaa
291  #define DR7_LOCAL_BP_MASK    0x55
292  #define DR7_MAX_BP           4
293  #define DR7_TYPE_BP_INST     0x0
294  #define DR7_TYPE_DATA_WR     0x1
295  #define DR7_TYPE_IO_RW       0x2
296  #define DR7_TYPE_DATA_RW     0x3
297  
298  #define DR_RESERVED_MASK 0xffffffff00000000ULL
299  
300  #define PG_PRESENT_BIT  0
301  #define PG_RW_BIT       1
302  #define PG_USER_BIT     2
303  #define PG_PWT_BIT      3
304  #define PG_PCD_BIT      4
305  #define PG_ACCESSED_BIT 5
306  #define PG_DIRTY_BIT    6
307  #define PG_PSE_BIT      7
308  #define PG_GLOBAL_BIT   8
309  #define PG_PSE_PAT_BIT  12
310  #define PG_PKRU_BIT     59
311  #define PG_NX_BIT       63
312  
313  #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
314  #define PG_RW_MASK       (1 << PG_RW_BIT)
315  #define PG_USER_MASK     (1 << PG_USER_BIT)
316  #define PG_PWT_MASK      (1 << PG_PWT_BIT)
317  #define PG_PCD_MASK      (1 << PG_PCD_BIT)
318  #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
319  #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
320  #define PG_PSE_MASK      (1 << PG_PSE_BIT)
321  #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
322  #define PG_PSE_PAT_MASK  (1 << PG_PSE_PAT_BIT)
323  #define PG_ADDRESS_MASK  0x000ffffffffff000LL
324  #define PG_HI_USER_MASK  0x7ff0000000000000LL
325  #define PG_PKRU_MASK     (15ULL << PG_PKRU_BIT)
326  #define PG_NX_MASK       (1ULL << PG_NX_BIT)
327  
328  #define PG_ERROR_W_BIT     1
329  
330  #define PG_ERROR_P_MASK    0x01
331  #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
332  #define PG_ERROR_U_MASK    0x04
333  #define PG_ERROR_RSVD_MASK 0x08
334  #define PG_ERROR_I_D_MASK  0x10
335  #define PG_ERROR_PK_MASK   0x20
336  
337  #define PG_MODE_PAE      (1 << 0)
338  #define PG_MODE_LMA      (1 << 1)
339  #define PG_MODE_NXE      (1 << 2)
340  #define PG_MODE_PSE      (1 << 3)
341  #define PG_MODE_LA57     (1 << 4)
342  #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
343  
344  /* Bits of CR4 that do not affect the NPT page format.  */
345  #define PG_MODE_WP       (1 << 16)
346  #define PG_MODE_PKE      (1 << 17)
347  #define PG_MODE_PKS      (1 << 18)
348  #define PG_MODE_SMEP     (1 << 19)
349  #define PG_MODE_PG       (1 << 20)
350  
351  #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
352  #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
353  #define MCG_LMCE_P      (1ULL<<27) /* Local Machine Check Supported */
354  
355  #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
356  #define MCE_BANKS_DEF   10
357  
358  #define MCG_CAP_BANKS_MASK 0xff
359  
360  #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
361  #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
362  #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
363  #define MCG_STATUS_LMCE (1ULL<<3)   /* Local MCE signaled */
364  
365  #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
366  
367  #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
368  #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
369  #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
370  #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
371  #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
372  #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
373  #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
374  #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
375  #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
376  #define MCI_STATUS_DEFERRED    (1ULL<<44)  /* Deferred error */
377  #define MCI_STATUS_POISON      (1ULL<<43)  /* Poisoned data consumed */
378  
379  /* MISC register defines */
380  #define MCM_ADDR_SEGOFF  0      /* segment offset */
381  #define MCM_ADDR_LINEAR  1      /* linear address */
382  #define MCM_ADDR_PHYS    2      /* physical address */
383  #define MCM_ADDR_MEM     3      /* memory address */
384  #define MCM_ADDR_GENERIC 7      /* generic */
385  
386  #define MSR_IA32_TSC                    0x10
387  #define MSR_IA32_APICBASE               0x1b
388  #define MSR_IA32_APICBASE_BSP           (1<<8)
389  #define MSR_IA32_APICBASE_ENABLE        (1<<11)
390  #define MSR_IA32_APICBASE_EXTD          (1 << 10)
391  #define MSR_IA32_APICBASE_BASE          (0xfffffU<<12)
392  #define MSR_IA32_APICBASE_RESERVED \
393          (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
394                       | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE))
395  
396  #define MSR_IA32_FEATURE_CONTROL        0x0000003a
397  #define MSR_TSC_ADJUST                  0x0000003b
398  #define MSR_IA32_SPEC_CTRL              0x48
399  #define MSR_VIRT_SSBD                   0xc001011f
400  #define MSR_IA32_PRED_CMD               0x49
401  #define MSR_IA32_UCODE_REV              0x8b
402  #define MSR_IA32_CORE_CAPABILITY        0xcf
403  
404  #define MSR_IA32_ARCH_CAPABILITIES      0x10a
405  #define ARCH_CAP_TSX_CTRL_MSR		(1<<7)
406  
407  #define MSR_IA32_PERF_CAPABILITIES      0x345
408  #define PERF_CAP_LBR_FMT                0x3f
409  
410  #define MSR_IA32_TSX_CTRL		0x122
411  #define MSR_IA32_TSCDEADLINE            0x6e0
412  #define MSR_IA32_PKRS                   0x6e1
413  #define MSR_RAPL_POWER_UNIT             0x00000606
414  #define MSR_PKG_POWER_LIMIT             0x00000610
415  #define MSR_PKG_ENERGY_STATUS           0x00000611
416  #define MSR_PKG_POWER_INFO              0x00000614
417  #define MSR_ARCH_LBR_CTL                0x000014ce
418  #define MSR_ARCH_LBR_DEPTH              0x000014cf
419  #define MSR_ARCH_LBR_FROM_0             0x00001500
420  #define MSR_ARCH_LBR_TO_0               0x00001600
421  #define MSR_ARCH_LBR_INFO_0             0x00001200
422  
423  #define FEATURE_CONTROL_LOCKED                    (1<<0)
424  #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX  (1ULL << 1)
425  #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
426  #define FEATURE_CONTROL_SGX_LC                    (1ULL << 17)
427  #define FEATURE_CONTROL_SGX                       (1ULL << 18)
428  #define FEATURE_CONTROL_LMCE                      (1<<20)
429  
430  #define MSR_IA32_SGXLEPUBKEYHASH0       0x8c
431  #define MSR_IA32_SGXLEPUBKEYHASH1       0x8d
432  #define MSR_IA32_SGXLEPUBKEYHASH2       0x8e
433  #define MSR_IA32_SGXLEPUBKEYHASH3       0x8f
434  
435  #define MSR_P6_PERFCTR0                 0xc1
436  
437  #define MSR_IA32_SMBASE                 0x9e
438  #define MSR_SMI_COUNT                   0x34
439  #define MSR_CORE_THREAD_COUNT           0x35
440  #define MSR_MTRRcap                     0xfe
441  #define MSR_MTRRcap_VCNT                8
442  #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
443  #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
444  
445  #define MSR_IA32_SYSENTER_CS            0x174
446  #define MSR_IA32_SYSENTER_ESP           0x175
447  #define MSR_IA32_SYSENTER_EIP           0x176
448  
449  #define MSR_MCG_CAP                     0x179
450  #define MSR_MCG_STATUS                  0x17a
451  #define MSR_MCG_CTL                     0x17b
452  #define MSR_MCG_EXT_CTL                 0x4d0
453  
454  #define MSR_P6_EVNTSEL0                 0x186
455  
456  #define MSR_IA32_PERF_STATUS            0x198
457  
458  #define MSR_IA32_MISC_ENABLE            0x1a0
459  /* Indicates good rep/movs microcode on some processors: */
460  #define MSR_IA32_MISC_ENABLE_DEFAULT    1
461  #define MSR_IA32_MISC_ENABLE_MWAIT      (1ULL << 18)
462  
463  #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
464  #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
465  
466  #define MSR_MTRRphysIndex(addr)         ((((addr) & ~1u) - 0x200) / 2)
467  
468  #define MSR_MTRRfix64K_00000            0x250
469  #define MSR_MTRRfix16K_80000            0x258
470  #define MSR_MTRRfix16K_A0000            0x259
471  #define MSR_MTRRfix4K_C0000             0x268
472  #define MSR_MTRRfix4K_C8000             0x269
473  #define MSR_MTRRfix4K_D0000             0x26a
474  #define MSR_MTRRfix4K_D8000             0x26b
475  #define MSR_MTRRfix4K_E0000             0x26c
476  #define MSR_MTRRfix4K_E8000             0x26d
477  #define MSR_MTRRfix4K_F0000             0x26e
478  #define MSR_MTRRfix4K_F8000             0x26f
479  
480  #define MSR_PAT                         0x277
481  
482  #define MSR_MTRRdefType                 0x2ff
483  
484  #define MSR_CORE_PERF_FIXED_CTR0        0x309
485  #define MSR_CORE_PERF_FIXED_CTR1        0x30a
486  #define MSR_CORE_PERF_FIXED_CTR2        0x30b
487  #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
488  #define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
489  #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
490  #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
491  
492  #define MSR_MC0_CTL                     0x400
493  #define MSR_MC0_STATUS                  0x401
494  #define MSR_MC0_ADDR                    0x402
495  #define MSR_MC0_MISC                    0x403
496  
497  #define MSR_IA32_RTIT_OUTPUT_BASE       0x560
498  #define MSR_IA32_RTIT_OUTPUT_MASK       0x561
499  #define MSR_IA32_RTIT_CTL               0x570
500  #define MSR_IA32_RTIT_STATUS            0x571
501  #define MSR_IA32_RTIT_CR3_MATCH         0x572
502  #define MSR_IA32_RTIT_ADDR0_A           0x580
503  #define MSR_IA32_RTIT_ADDR0_B           0x581
504  #define MSR_IA32_RTIT_ADDR1_A           0x582
505  #define MSR_IA32_RTIT_ADDR1_B           0x583
506  #define MSR_IA32_RTIT_ADDR2_A           0x584
507  #define MSR_IA32_RTIT_ADDR2_B           0x585
508  #define MSR_IA32_RTIT_ADDR3_A           0x586
509  #define MSR_IA32_RTIT_ADDR3_B           0x587
510  #define MAX_RTIT_ADDRS                  8
511  
512  #define MSR_EFER                        0xc0000080
513  
514  #define MSR_EFER_SCE   (1 << 0)
515  #define MSR_EFER_LME   (1 << 8)
516  #define MSR_EFER_LMA   (1 << 10)
517  #define MSR_EFER_NXE   (1 << 11)
518  #define MSR_EFER_SVME  (1 << 12)
519  #define MSR_EFER_FFXSR (1 << 14)
520  
521  #define MSR_EFER_RESERVED\
522          (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
523              | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
524              | MSR_EFER_FFXSR))
525  
526  #define MSR_STAR                        0xc0000081
527  #define MSR_LSTAR                       0xc0000082
528  #define MSR_CSTAR                       0xc0000083
529  #define MSR_FMASK                       0xc0000084
530  #define MSR_FSBASE                      0xc0000100
531  #define MSR_GSBASE                      0xc0000101
532  #define MSR_KERNELGSBASE                0xc0000102
533  #define MSR_TSC_AUX                     0xc0000103
534  #define MSR_AMD64_TSC_RATIO             0xc0000104
535  
536  #define MSR_AMD64_TSC_RATIO_DEFAULT     0x100000000ULL
537  
538  #define MSR_K7_HWCR                     0xc0010015
539  
540  #define MSR_VM_HSAVE_PA                 0xc0010117
541  
542  #define MSR_IA32_XFD                    0x000001c4
543  #define MSR_IA32_XFD_ERR                0x000001c5
544  
545  /* FRED MSRs */
546  #define MSR_IA32_FRED_RSP0              0x000001cc       /* Stack level 0 regular stack pointer */
547  #define MSR_IA32_FRED_RSP1              0x000001cd       /* Stack level 1 regular stack pointer */
548  #define MSR_IA32_FRED_RSP2              0x000001ce       /* Stack level 2 regular stack pointer */
549  #define MSR_IA32_FRED_RSP3              0x000001cf       /* Stack level 3 regular stack pointer */
550  #define MSR_IA32_FRED_STKLVLS           0x000001d0       /* FRED exception stack levels */
551  #define MSR_IA32_FRED_SSP1              0x000001d1       /* Stack level 1 shadow stack pointer in ring 0 */
552  #define MSR_IA32_FRED_SSP2              0x000001d2       /* Stack level 2 shadow stack pointer in ring 0 */
553  #define MSR_IA32_FRED_SSP3              0x000001d3       /* Stack level 3 shadow stack pointer in ring 0 */
554  #define MSR_IA32_FRED_CONFIG            0x000001d4       /* FRED Entrypoint and interrupt stack level */
555  
556  #define MSR_IA32_BNDCFGS                0x00000d90
557  #define MSR_IA32_XSS                    0x00000da0
558  #define MSR_IA32_UMWAIT_CONTROL         0xe1
559  
560  #define MSR_IA32_VMX_BASIC              0x00000480
561  #define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
562  #define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
563  #define MSR_IA32_VMX_EXIT_CTLS          0x00000483
564  #define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
565  #define MSR_IA32_VMX_MISC               0x00000485
566  #define MSR_IA32_VMX_CR0_FIXED0         0x00000486
567  #define MSR_IA32_VMX_CR0_FIXED1         0x00000487
568  #define MSR_IA32_VMX_CR4_FIXED0         0x00000488
569  #define MSR_IA32_VMX_CR4_FIXED1         0x00000489
570  #define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
571  #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
572  #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
573  #define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
574  #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
575  #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
576  #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
577  #define MSR_IA32_VMX_VMFUNC             0x00000491
578  
579  #define MSR_APIC_START                  0x00000800
580  #define MSR_APIC_END                    0x000008ff
581  
582  #define XSTATE_FP_BIT                   0
583  #define XSTATE_SSE_BIT                  1
584  #define XSTATE_YMM_BIT                  2
585  #define XSTATE_BNDREGS_BIT              3
586  #define XSTATE_BNDCSR_BIT               4
587  #define XSTATE_OPMASK_BIT               5
588  #define XSTATE_ZMM_Hi256_BIT            6
589  #define XSTATE_Hi16_ZMM_BIT             7
590  #define XSTATE_PKRU_BIT                 9
591  #define XSTATE_ARCH_LBR_BIT             15
592  #define XSTATE_XTILE_CFG_BIT            17
593  #define XSTATE_XTILE_DATA_BIT           18
594  
595  #define XSTATE_FP_MASK                  (1ULL << XSTATE_FP_BIT)
596  #define XSTATE_SSE_MASK                 (1ULL << XSTATE_SSE_BIT)
597  #define XSTATE_YMM_MASK                 (1ULL << XSTATE_YMM_BIT)
598  #define XSTATE_BNDREGS_MASK             (1ULL << XSTATE_BNDREGS_BIT)
599  #define XSTATE_BNDCSR_MASK              (1ULL << XSTATE_BNDCSR_BIT)
600  #define XSTATE_OPMASK_MASK              (1ULL << XSTATE_OPMASK_BIT)
601  #define XSTATE_ZMM_Hi256_MASK           (1ULL << XSTATE_ZMM_Hi256_BIT)
602  #define XSTATE_Hi16_ZMM_MASK            (1ULL << XSTATE_Hi16_ZMM_BIT)
603  #define XSTATE_PKRU_MASK                (1ULL << XSTATE_PKRU_BIT)
604  #define XSTATE_ARCH_LBR_MASK            (1ULL << XSTATE_ARCH_LBR_BIT)
605  #define XSTATE_XTILE_CFG_MASK           (1ULL << XSTATE_XTILE_CFG_BIT)
606  #define XSTATE_XTILE_DATA_MASK          (1ULL << XSTATE_XTILE_DATA_BIT)
607  
608  #define XSTATE_DYNAMIC_MASK             (XSTATE_XTILE_DATA_MASK)
609  
610  #define ESA_FEATURE_ALIGN64_BIT         1
611  #define ESA_FEATURE_XFD_BIT             2
612  
613  #define ESA_FEATURE_ALIGN64_MASK        (1U << ESA_FEATURE_ALIGN64_BIT)
614  #define ESA_FEATURE_XFD_MASK            (1U << ESA_FEATURE_XFD_BIT)
615  
616  
617  /* CPUID feature bits available in XCR0 */
618  #define CPUID_XSTATE_XCR0_MASK  (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
619                                   XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
620                                   XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
621                                   XSTATE_ZMM_Hi256_MASK | \
622                                   XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
623                                   XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
624  
625  /* CPUID feature words */
626  typedef enum FeatureWord {
627      FEAT_1_EDX,         /* CPUID[1].EDX */
628      FEAT_1_ECX,         /* CPUID[1].ECX */
629      FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
630      FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */
631      FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */
632      FEAT_7_1_EAX,       /* CPUID[EAX=7,ECX=1].EAX */
633      FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
634      FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
635      FEAT_8000_0007_EBX, /* CPUID[8000_0007].EBX */
636      FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
637      FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
638      FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
639      FEAT_8000_0021_EBX, /* CPUID[8000_0021].EBX */
640      FEAT_8000_0022_EAX, /* CPUID[8000_0022].EAX */
641      FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
642      FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
643      FEAT_KVM_HINTS,     /* CPUID[4000_0001].EDX */
644      FEAT_SVM,           /* CPUID[8000_000A].EDX */
645      FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */
646      FEAT_6_EAX,         /* CPUID[6].EAX */
647      FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
648      FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
649      FEAT_ARCH_CAPABILITIES,
650      FEAT_CORE_CAPABILITY,
651      FEAT_PERF_CAPABILITIES,
652      FEAT_VMX_PROCBASED_CTLS,
653      FEAT_VMX_SECONDARY_CTLS,
654      FEAT_VMX_PINBASED_CTLS,
655      FEAT_VMX_EXIT_CTLS,
656      FEAT_VMX_ENTRY_CTLS,
657      FEAT_VMX_MISC,
658      FEAT_VMX_EPT_VPID_CAPS,
659      FEAT_VMX_BASIC,
660      FEAT_VMX_VMFUNC,
661      FEAT_14_0_ECX,
662      FEAT_SGX_12_0_EAX,  /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
663      FEAT_SGX_12_0_EBX,  /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
664      FEAT_SGX_12_1_EAX,  /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
665      FEAT_XSAVE_XSS_LO,     /* CPUID[EAX=0xd,ECX=1].ECX */
666      FEAT_XSAVE_XSS_HI,     /* CPUID[EAX=0xd,ECX=1].EDX */
667      FEAT_7_1_EDX,       /* CPUID[EAX=7,ECX=1].EDX */
668      FEAT_7_2_EDX,       /* CPUID[EAX=7,ECX=2].EDX */
669      FEAT_24_0_EBX,      /* CPUID[EAX=0x24,ECX=0].EBX */
670      FEATURE_WORDS,
671  } FeatureWord;
672  
673  typedef uint64_t FeatureWordArray[FEATURE_WORDS];
674  uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
675  
676  /* cpuid_features bits */
677  #define CPUID_FP87 (1U << 0)
678  #define CPUID_VME  (1U << 1)
679  #define CPUID_DE   (1U << 2)
680  #define CPUID_PSE  (1U << 3)
681  #define CPUID_TSC  (1U << 4)
682  #define CPUID_MSR  (1U << 5)
683  #define CPUID_PAE  (1U << 6)
684  #define CPUID_MCE  (1U << 7)
685  #define CPUID_CX8  (1U << 8)
686  #define CPUID_APIC (1U << 9)
687  #define CPUID_SEP  (1U << 11) /* sysenter/sysexit */
688  #define CPUID_MTRR (1U << 12)
689  #define CPUID_PGE  (1U << 13)
690  #define CPUID_MCA  (1U << 14)
691  #define CPUID_CMOV (1U << 15)
692  #define CPUID_PAT  (1U << 16)
693  #define CPUID_PSE36   (1U << 17)
694  #define CPUID_PN   (1U << 18)
695  #define CPUID_CLFLUSH (1U << 19)
696  #define CPUID_DTS (1U << 21)
697  #define CPUID_ACPI (1U << 22)
698  #define CPUID_MMX  (1U << 23)
699  #define CPUID_FXSR (1U << 24)
700  #define CPUID_SSE  (1U << 25)
701  #define CPUID_SSE2 (1U << 26)
702  #define CPUID_SS (1U << 27)
703  #define CPUID_HT (1U << 28)
704  #define CPUID_TM (1U << 29)
705  #define CPUID_IA64 (1U << 30)
706  #define CPUID_PBE (1U << 31)
707  
708  #define CPUID_EXT_SSE3     (1U << 0)
709  #define CPUID_EXT_PCLMULQDQ (1U << 1)
710  #define CPUID_EXT_DTES64   (1U << 2)
711  #define CPUID_EXT_MONITOR  (1U << 3)
712  #define CPUID_EXT_DSCPL    (1U << 4)
713  #define CPUID_EXT_VMX      (1U << 5)
714  #define CPUID_EXT_SMX      (1U << 6)
715  #define CPUID_EXT_EST      (1U << 7)
716  #define CPUID_EXT_TM2      (1U << 8)
717  #define CPUID_EXT_SSSE3    (1U << 9)
718  #define CPUID_EXT_CID      (1U << 10)
719  #define CPUID_EXT_FMA      (1U << 12)
720  #define CPUID_EXT_CX16     (1U << 13)
721  #define CPUID_EXT_XTPR     (1U << 14)
722  #define CPUID_EXT_PDCM     (1U << 15)
723  #define CPUID_EXT_PCID     (1U << 17)
724  #define CPUID_EXT_DCA      (1U << 18)
725  #define CPUID_EXT_SSE41    (1U << 19)
726  #define CPUID_EXT_SSE42    (1U << 20)
727  #define CPUID_EXT_X2APIC   (1U << 21)
728  #define CPUID_EXT_MOVBE    (1U << 22)
729  #define CPUID_EXT_POPCNT   (1U << 23)
730  #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
731  #define CPUID_EXT_AES      (1U << 25)
732  #define CPUID_EXT_XSAVE    (1U << 26)
733  #define CPUID_EXT_OSXSAVE  (1U << 27)
734  #define CPUID_EXT_AVX      (1U << 28)
735  #define CPUID_EXT_F16C     (1U << 29)
736  #define CPUID_EXT_RDRAND   (1U << 30)
737  #define CPUID_EXT_HYPERVISOR  (1U << 31)
738  
739  #define CPUID_EXT2_FPU     (1U << 0)
740  #define CPUID_EXT2_VME     (1U << 1)
741  #define CPUID_EXT2_DE      (1U << 2)
742  #define CPUID_EXT2_PSE     (1U << 3)
743  #define CPUID_EXT2_TSC     (1U << 4)
744  #define CPUID_EXT2_MSR     (1U << 5)
745  #define CPUID_EXT2_PAE     (1U << 6)
746  #define CPUID_EXT2_MCE     (1U << 7)
747  #define CPUID_EXT2_CX8     (1U << 8)
748  #define CPUID_EXT2_APIC    (1U << 9)
749  #define CPUID_EXT2_SYSCALL (1U << 11)
750  #define CPUID_EXT2_MTRR    (1U << 12)
751  #define CPUID_EXT2_PGE     (1U << 13)
752  #define CPUID_EXT2_MCA     (1U << 14)
753  #define CPUID_EXT2_CMOV    (1U << 15)
754  #define CPUID_EXT2_PAT     (1U << 16)
755  #define CPUID_EXT2_PSE36   (1U << 17)
756  #define CPUID_EXT2_MP      (1U << 19)
757  #define CPUID_EXT2_NX      (1U << 20)
758  #define CPUID_EXT2_MMXEXT  (1U << 22)
759  #define CPUID_EXT2_MMX     (1U << 23)
760  #define CPUID_EXT2_FXSR    (1U << 24)
761  #define CPUID_EXT2_FFXSR   (1U << 25)
762  #define CPUID_EXT2_PDPE1GB (1U << 26)
763  #define CPUID_EXT2_RDTSCP  (1U << 27)
764  #define CPUID_EXT2_LM      (1U << 29)
765  #define CPUID_EXT2_3DNOWEXT (1U << 30)
766  #define CPUID_EXT2_3DNOW   (1U << 31)
767  
768  /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */
769  #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
770                                  CPUID_EXT2_DE | CPUID_EXT2_PSE | \
771                                  CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
772                                  CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
773                                  CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
774                                  CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
775                                  CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
776                                  CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
777                                  CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
778  
779  #define CPUID_EXT3_LAHF_LM (1U << 0)
780  #define CPUID_EXT3_CMP_LEG (1U << 1)
781  #define CPUID_EXT3_SVM     (1U << 2)
782  #define CPUID_EXT3_EXTAPIC (1U << 3)
783  #define CPUID_EXT3_CR8LEG  (1U << 4)
784  #define CPUID_EXT3_ABM     (1U << 5)
785  #define CPUID_EXT3_SSE4A   (1U << 6)
786  #define CPUID_EXT3_MISALIGNSSE (1U << 7)
787  #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
788  #define CPUID_EXT3_OSVW    (1U << 9)
789  #define CPUID_EXT3_IBS     (1U << 10)
790  #define CPUID_EXT3_XOP     (1U << 11)
791  #define CPUID_EXT3_SKINIT  (1U << 12)
792  #define CPUID_EXT3_WDT     (1U << 13)
793  #define CPUID_EXT3_LWP     (1U << 15)
794  #define CPUID_EXT3_FMA4    (1U << 16)
795  #define CPUID_EXT3_TCE     (1U << 17)
796  #define CPUID_EXT3_NODEID  (1U << 19)
797  #define CPUID_EXT3_TBM     (1U << 21)
798  #define CPUID_EXT3_TOPOEXT (1U << 22)
799  #define CPUID_EXT3_PERFCORE (1U << 23)
800  #define CPUID_EXT3_PERFNB  (1U << 24)
801  
802  #define CPUID_SVM_NPT             (1U << 0)
803  #define CPUID_SVM_LBRV            (1U << 1)
804  #define CPUID_SVM_SVMLOCK         (1U << 2)
805  #define CPUID_SVM_NRIPSAVE        (1U << 3)
806  #define CPUID_SVM_TSCSCALE        (1U << 4)
807  #define CPUID_SVM_VMCBCLEAN       (1U << 5)
808  #define CPUID_SVM_FLUSHASID       (1U << 6)
809  #define CPUID_SVM_DECODEASSIST    (1U << 7)
810  #define CPUID_SVM_PAUSEFILTER     (1U << 10)
811  #define CPUID_SVM_PFTHRESHOLD     (1U << 12)
812  #define CPUID_SVM_AVIC            (1U << 13)
813  #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
814  #define CPUID_SVM_VGIF            (1U << 16)
815  #define CPUID_SVM_VNMI            (1U << 25)
816  #define CPUID_SVM_SVME_ADDR_CHK   (1U << 28)
817  
818  /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
819  #define CPUID_7_0_EBX_FSGSBASE          (1U << 0)
820  /* Support TSC adjust MSR */
821  #define CPUID_7_0_EBX_TSC_ADJUST        (1U << 1)
822  /* Support SGX */
823  #define CPUID_7_0_EBX_SGX               (1U << 2)
824  /* 1st Group of Advanced Bit Manipulation Extensions */
825  #define CPUID_7_0_EBX_BMI1              (1U << 3)
826  /* Hardware Lock Elision */
827  #define CPUID_7_0_EBX_HLE               (1U << 4)
828  /* Intel Advanced Vector Extensions 2 */
829  #define CPUID_7_0_EBX_AVX2              (1U << 5)
830  /* FPU data pointer updated only on x87 exceptions */
831  #define CPUID_7_0_EBX_FDP_EXCPTN_ONLY (1u << 6)
832  /* Supervisor-mode Execution Prevention */
833  #define CPUID_7_0_EBX_SMEP              (1U << 7)
834  /* 2nd Group of Advanced Bit Manipulation Extensions */
835  #define CPUID_7_0_EBX_BMI2              (1U << 8)
836  /* Enhanced REP MOVSB/STOSB */
837  #define CPUID_7_0_EBX_ERMS              (1U << 9)
838  /* Invalidate Process-Context Identifier */
839  #define CPUID_7_0_EBX_INVPCID           (1U << 10)
840  /* Restricted Transactional Memory */
841  #define CPUID_7_0_EBX_RTM               (1U << 11)
842  /* Zero out FPU CS and FPU DS */
843  #define CPUID_7_0_EBX_ZERO_FCS_FDS      (1U << 13)
844  /* Memory Protection Extension */
845  #define CPUID_7_0_EBX_MPX               (1U << 14)
846  /* AVX-512 Foundation */
847  #define CPUID_7_0_EBX_AVX512F           (1U << 16)
848  /* AVX-512 Doubleword & Quadword Instruction */
849  #define CPUID_7_0_EBX_AVX512DQ          (1U << 17)
850  /* Read Random SEED */
851  #define CPUID_7_0_EBX_RDSEED            (1U << 18)
852  /* ADCX and ADOX instructions */
853  #define CPUID_7_0_EBX_ADX               (1U << 19)
854  /* Supervisor Mode Access Prevention */
855  #define CPUID_7_0_EBX_SMAP              (1U << 20)
856  /* AVX-512 Integer Fused Multiply Add */
857  #define CPUID_7_0_EBX_AVX512IFMA        (1U << 21)
858  /* Flush a Cache Line Optimized */
859  #define CPUID_7_0_EBX_CLFLUSHOPT        (1U << 23)
860  /* Cache Line Write Back */
861  #define CPUID_7_0_EBX_CLWB              (1U << 24)
862  /* Intel Processor Trace */
863  #define CPUID_7_0_EBX_INTEL_PT          (1U << 25)
864  /* AVX-512 Prefetch */
865  #define CPUID_7_0_EBX_AVX512PF          (1U << 26)
866  /* AVX-512 Exponential and Reciprocal */
867  #define CPUID_7_0_EBX_AVX512ER          (1U << 27)
868  /* AVX-512 Conflict Detection */
869  #define CPUID_7_0_EBX_AVX512CD          (1U << 28)
870  /* SHA1/SHA256 Instruction Extensions */
871  #define CPUID_7_0_EBX_SHA_NI            (1U << 29)
872  /* AVX-512 Byte and Word Instructions */
873  #define CPUID_7_0_EBX_AVX512BW          (1U << 30)
874  /* AVX-512 Vector Length Extensions */
875  #define CPUID_7_0_EBX_AVX512VL          (1U << 31)
876  
877  /* AVX-512 Vector Byte Manipulation Instruction */
878  #define CPUID_7_0_ECX_AVX512_VBMI       (1U << 1)
879  /* User-Mode Instruction Prevention */
880  #define CPUID_7_0_ECX_UMIP              (1U << 2)
881  /* Protection Keys for User-mode Pages */
882  #define CPUID_7_0_ECX_PKU               (1U << 3)
883  /* OS Enable Protection Keys */
884  #define CPUID_7_0_ECX_OSPKE             (1U << 4)
885  /* UMONITOR/UMWAIT/TPAUSE Instructions */
886  #define CPUID_7_0_ECX_WAITPKG           (1U << 5)
887  /* Additional AVX-512 Vector Byte Manipulation Instruction */
888  #define CPUID_7_0_ECX_AVX512_VBMI2      (1U << 6)
889  /* Galois Field New Instructions */
890  #define CPUID_7_0_ECX_GFNI              (1U << 8)
891  /* Vector AES Instructions */
892  #define CPUID_7_0_ECX_VAES              (1U << 9)
893  /* Carry-Less Multiplication Quadword */
894  #define CPUID_7_0_ECX_VPCLMULQDQ        (1U << 10)
895  /* Vector Neural Network Instructions */
896  #define CPUID_7_0_ECX_AVX512VNNI        (1U << 11)
897  /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
898  #define CPUID_7_0_ECX_AVX512BITALG      (1U << 12)
899  /* POPCNT for vectors of DW/QW */
900  #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ  (1U << 14)
901  /* 5-level Page Tables */
902  #define CPUID_7_0_ECX_LA57              (1U << 16)
903  /* Read Processor ID */
904  #define CPUID_7_0_ECX_RDPID             (1U << 22)
905  /* Bus Lock Debug Exception */
906  #define CPUID_7_0_ECX_BUS_LOCK_DETECT   (1U << 24)
907  /* Cache Line Demote Instruction */
908  #define CPUID_7_0_ECX_CLDEMOTE          (1U << 25)
909  /* Move Doubleword as Direct Store Instruction */
910  #define CPUID_7_0_ECX_MOVDIRI           (1U << 27)
911  /* Move 64 Bytes as Direct Store Instruction */
912  #define CPUID_7_0_ECX_MOVDIR64B         (1U << 28)
913  /* Support SGX Launch Control */
914  #define CPUID_7_0_ECX_SGX_LC            (1U << 30)
915  /* Protection Keys for Supervisor-mode Pages */
916  #define CPUID_7_0_ECX_PKS               (1U << 31)
917  
918  /* AVX512 Neural Network Instructions */
919  #define CPUID_7_0_EDX_AVX512_4VNNIW     (1U << 2)
920  /* AVX512 Multiply Accumulation Single Precision */
921  #define CPUID_7_0_EDX_AVX512_4FMAPS     (1U << 3)
922  /* Fast Short Rep Mov */
923  #define CPUID_7_0_EDX_FSRM              (1U << 4)
924  /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
925  #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
926  /* SERIALIZE instruction */
927  #define CPUID_7_0_EDX_SERIALIZE         (1U << 14)
928  /* TSX Suspend Load Address Tracking instruction */
929  #define CPUID_7_0_EDX_TSX_LDTRK         (1U << 16)
930  /* Architectural LBRs */
931  #define CPUID_7_0_EDX_ARCH_LBR          (1U << 19)
932  /* AMX_BF16 instruction */
933  #define CPUID_7_0_EDX_AMX_BF16          (1U << 22)
934  /* AVX512_FP16 instruction */
935  #define CPUID_7_0_EDX_AVX512_FP16       (1U << 23)
936  /* AMX tile (two-dimensional register) */
937  #define CPUID_7_0_EDX_AMX_TILE          (1U << 24)
938  /* AMX_INT8 instruction */
939  #define CPUID_7_0_EDX_AMX_INT8          (1U << 25)
940  /* Speculation Control */
941  #define CPUID_7_0_EDX_SPEC_CTRL         (1U << 26)
942  /* Single Thread Indirect Branch Predictors */
943  #define CPUID_7_0_EDX_STIBP             (1U << 27)
944  /* Flush L1D cache */
945  #define CPUID_7_0_EDX_FLUSH_L1D         (1U << 28)
946  /* Arch Capabilities */
947  #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
948  /* Core Capability */
949  #define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)
950  /* Speculative Store Bypass Disable */
951  #define CPUID_7_0_EDX_SPEC_CTRL_SSBD    (1U << 31)
952  
953  /* AVX VNNI Instruction */
954  #define CPUID_7_1_EAX_AVX_VNNI          (1U << 4)
955  /* AVX512 BFloat16 Instruction */
956  #define CPUID_7_1_EAX_AVX512_BF16       (1U << 5)
957  /* CMPCCXADD Instructions */
958  #define CPUID_7_1_EAX_CMPCCXADD         (1U << 7)
959  /* Fast Zero REP MOVS */
960  #define CPUID_7_1_EAX_FZRM              (1U << 10)
961  /* Fast Short REP STOS */
962  #define CPUID_7_1_EAX_FSRS              (1U << 11)
963  /* Fast Short REP CMPS/SCAS */
964  #define CPUID_7_1_EAX_FSRC              (1U << 12)
965  /* Support Tile Computational Operations on FP16 Numbers */
966  #define CPUID_7_1_EAX_AMX_FP16          (1U << 21)
967  /* Support for VPMADD52[H,L]UQ */
968  #define CPUID_7_1_EAX_AVX_IFMA          (1U << 23)
969  /* Linear Address Masking */
970  #define CPUID_7_1_EAX_LAM               (1U << 26)
971  
972  /* Support for VPDPB[SU,UU,SS]D[,S] */
973  #define CPUID_7_1_EDX_AVX_VNNI_INT8     (1U << 4)
974  /* AVX NE CONVERT Instructions */
975  #define CPUID_7_1_EDX_AVX_NE_CONVERT    (1U << 5)
976  /* AMX COMPLEX Instructions */
977  #define CPUID_7_1_EDX_AMX_COMPLEX       (1U << 8)
978  /* PREFETCHIT0/1 Instructions */
979  #define CPUID_7_1_EDX_PREFETCHITI       (1U << 14)
980  /* Support for Advanced Vector Extensions 10 */
981  #define CPUID_7_1_EDX_AVX10             (1U << 19)
982  /* Flexible return and event delivery (FRED) */
983  #define CPUID_7_1_EAX_FRED              (1U << 17)
984  /* Load into IA32_KERNEL_GS_BASE (LKGS) */
985  #define CPUID_7_1_EAX_LKGS              (1U << 18)
986  /* Non-Serializing Write to Model Specific Register (WRMSRNS) */
987  #define CPUID_7_1_EAX_WRMSRNS           (1U << 19)
988  
989  /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
990  #define CPUID_7_2_EDX_MCDT_NO           (1U << 5)
991  
992  /* XFD Extend Feature Disabled */
993  #define CPUID_D_1_EAX_XFD               (1U << 4)
994  
995  /* Packets which contain IP payload have LIP values */
996  #define CPUID_14_0_ECX_LIP              (1U << 31)
997  
998  /* AVX10 128-bit vector support is present */
999  #define CPUID_24_0_EBX_AVX10_128        (1U << 16)
1000  /* AVX10 256-bit vector support is present */
1001  #define CPUID_24_0_EBX_AVX10_256        (1U << 17)
1002  /* AVX10 512-bit vector support is present */
1003  #define CPUID_24_0_EBX_AVX10_512        (1U << 18)
1004  /* AVX10 vector length support mask */
1005  #define CPUID_24_0_EBX_AVX10_VL_MASK    (CPUID_24_0_EBX_AVX10_128 | \
1006                                           CPUID_24_0_EBX_AVX10_256 | \
1007                                           CPUID_24_0_EBX_AVX10_512)
1008  
1009  /* RAS Features */
1010  #define CPUID_8000_0007_EBX_OVERFLOW_RECOV    (1U << 0)
1011  #define CPUID_8000_0007_EBX_SUCCOR      (1U << 1)
1012  
1013  /* CLZERO instruction */
1014  #define CPUID_8000_0008_EBX_CLZERO      (1U << 0)
1015  /* Always save/restore FP error pointers */
1016  #define CPUID_8000_0008_EBX_XSAVEERPTR  (1U << 2)
1017  /* Write back and do not invalidate cache */
1018  #define CPUID_8000_0008_EBX_WBNOINVD    (1U << 9)
1019  /* Indirect Branch Prediction Barrier */
1020  #define CPUID_8000_0008_EBX_IBPB        (1U << 12)
1021  /* Indirect Branch Restricted Speculation */
1022  #define CPUID_8000_0008_EBX_IBRS        (1U << 14)
1023  /* Single Thread Indirect Branch Predictors */
1024  #define CPUID_8000_0008_EBX_STIBP       (1U << 15)
1025  /* STIBP mode has enhanced performance and may be left always on */
1026  #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON    (1U << 17)
1027  /* Speculative Store Bypass Disable */
1028  #define CPUID_8000_0008_EBX_AMD_SSBD    (1U << 24)
1029  /* Paravirtualized Speculative Store Bypass Disable MSR */
1030  #define CPUID_8000_0008_EBX_VIRT_SSBD   (1U << 25)
1031  /* Predictive Store Forwarding Disable */
1032  #define CPUID_8000_0008_EBX_AMD_PSFD    (1U << 28)
1033  
1034  /* Processor ignores nested data breakpoints */
1035  #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP            (1U << 0)
1036  /* LFENCE is always serializing */
1037  #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING    (1U << 2)
1038  /* Null Selector Clears Base */
1039  #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE            (1U << 6)
1040  /* Automatic IBRS */
1041  #define CPUID_8000_0021_EAX_AUTO_IBRS                    (1U << 8)
1042  /* Enhanced Return Address Predictor Scurity */
1043  #define CPUID_8000_0021_EAX_ERAPS                        (1U << 24)
1044  /* Selective Branch Predictor Barrier */
1045  #define CPUID_8000_0021_EAX_SBPB                         (1U << 27)
1046  /* IBPB includes branch type prediction flushing */
1047  #define CPUID_8000_0021_EAX_IBPB_BRTYPE                  (1U << 28)
1048  /* Not vulnerable to Speculative Return Stack Overflow */
1049  #define CPUID_8000_0021_EAX_SRSO_NO                      (1U << 29)
1050  /* Not vulnerable to SRSO at the user-kernel boundary */
1051  #define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO          (1U << 30)
1052  
1053  /*
1054   * Return Address Predictor size. RapSize x 8 is the minimum number of
1055   * CALL instructions software needs to execute to flush the RAP.
1056   */
1057  #define CPUID_8000_0021_EBX_RAPSIZE    (8U << 16)
1058  
1059  /* Performance Monitoring Version 2 */
1060  #define CPUID_8000_0022_EAX_PERFMON_V2  (1U << 0)
1061  
1062  #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
1063  #define CPUID_XSAVE_XSAVEC     (1U << 1)
1064  #define CPUID_XSAVE_XGETBV1    (1U << 2)
1065  #define CPUID_XSAVE_XSAVES     (1U << 3)
1066  
1067  #define CPUID_6_EAX_ARAT       (1U << 2)
1068  
1069  /* CPUID[0x80000007].EDX flags: */
1070  #define CPUID_APM_INVTSC       (1U << 8)
1071  
1072  #define CPUID_VENDOR_SZ      12
1073  
1074  #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
1075  #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
1076  #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
1077  #define CPUID_VENDOR_INTEL "GenuineIntel"
1078  
1079  #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
1080  #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
1081  #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
1082  #define CPUID_VENDOR_AMD   "AuthenticAMD"
1083  
1084  #define CPUID_VENDOR_VIA   "CentaurHauls"
1085  
1086  #define CPUID_VENDOR_HYGON    "HygonGenuine"
1087  
1088  #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
1089                             (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
1090                             (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
1091  #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
1092                           (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
1093                           (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
1094  
1095  #define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
1096  #define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
1097  
1098  /* CPUID[0xB].ECX level types */
1099  #define CPUID_B_ECX_TOPO_LEVEL_INVALID  0
1100  #define CPUID_B_ECX_TOPO_LEVEL_SMT      1
1101  #define CPUID_B_ECX_TOPO_LEVEL_CORE     2
1102  
1103  /* COUID[0x1F].ECX level types */
1104  #define CPUID_1F_ECX_TOPO_LEVEL_INVALID  CPUID_B_ECX_TOPO_LEVEL_INVALID
1105  #define CPUID_1F_ECX_TOPO_LEVEL_SMT      CPUID_B_ECX_TOPO_LEVEL_SMT
1106  #define CPUID_1F_ECX_TOPO_LEVEL_CORE     CPUID_B_ECX_TOPO_LEVEL_CORE
1107  #define CPUID_1F_ECX_TOPO_LEVEL_MODULE   3
1108  #define CPUID_1F_ECX_TOPO_LEVEL_DIE      5
1109  
1110  /* MSR Feature Bits */
1111  #define MSR_ARCH_CAP_RDCL_NO            (1U << 0)
1112  #define MSR_ARCH_CAP_IBRS_ALL           (1U << 1)
1113  #define MSR_ARCH_CAP_RSBA               (1U << 2)
1114  #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1115  #define MSR_ARCH_CAP_SSB_NO             (1U << 4)
1116  #define MSR_ARCH_CAP_MDS_NO             (1U << 5)
1117  #define MSR_ARCH_CAP_PSCHANGE_MC_NO     (1U << 6)
1118  #define MSR_ARCH_CAP_TSX_CTRL_MSR       (1U << 7)
1119  #define MSR_ARCH_CAP_TAA_NO             (1U << 8)
1120  #define MSR_ARCH_CAP_SBDR_SSDP_NO       (1U << 13)
1121  #define MSR_ARCH_CAP_FBSDP_NO           (1U << 14)
1122  #define MSR_ARCH_CAP_PSDP_NO            (1U << 15)
1123  #define MSR_ARCH_CAP_FB_CLEAR           (1U << 17)
1124  #define MSR_ARCH_CAP_PBRSB_NO           (1U << 24)
1125  
1126  #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
1127  
1128  /* VMX MSR features */
1129  #define MSR_VMX_BASIC_VMCS_REVISION_MASK             0x7FFFFFFFull
1130  #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK         (0x00001FFFull << 32)
1131  #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK             (0x003C0000ull << 32)
1132  #define MSR_VMX_BASIC_DUAL_MONITOR                   (1ULL << 49)
1133  #define MSR_VMX_BASIC_INS_OUTS                       (1ULL << 54)
1134  #define MSR_VMX_BASIC_TRUE_CTLS                      (1ULL << 55)
1135  #define MSR_VMX_BASIC_ANY_ERRCODE                    (1ULL << 56)
1136  #define MSR_VMX_BASIC_NESTED_EXCEPTION               (1ULL << 58)
1137  
1138  #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK     0x1Full
1139  #define MSR_VMX_MISC_STORE_LMA                       (1ULL << 5)
1140  #define MSR_VMX_MISC_ACTIVITY_HLT                    (1ULL << 6)
1141  #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN               (1ULL << 7)
1142  #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI              (1ULL << 8)
1143  #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK          0x0E000000ull
1144  #define MSR_VMX_MISC_VMWRITE_VMEXIT                  (1ULL << 29)
1145  #define MSR_VMX_MISC_ZERO_LEN_INJECT                 (1ULL << 30)
1146  
1147  #define MSR_VMX_EPT_EXECONLY                         (1ULL << 0)
1148  #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4               (1ULL << 6)
1149  #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5               (1ULL << 7)
1150  #define MSR_VMX_EPT_UC                               (1ULL << 8)
1151  #define MSR_VMX_EPT_WB                               (1ULL << 14)
1152  #define MSR_VMX_EPT_2MB                              (1ULL << 16)
1153  #define MSR_VMX_EPT_1GB                              (1ULL << 17)
1154  #define MSR_VMX_EPT_INVEPT                           (1ULL << 20)
1155  #define MSR_VMX_EPT_AD_BITS                          (1ULL << 21)
1156  #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO             (1ULL << 22)
1157  #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT            (1ULL << 25)
1158  #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT               (1ULL << 26)
1159  #define MSR_VMX_EPT_INVVPID                          (1ULL << 32)
1160  #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR              (1ULL << 40)
1161  #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT           (1ULL << 41)
1162  #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT              (1ULL << 42)
1163  #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1164  
1165  #define MSR_VMX_VMFUNC_EPT_SWITCHING                 (1ULL << 0)
1166  
1167  
1168  /* VMX controls */
1169  #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
1170  #define VMX_CPU_BASED_USE_TSC_OFFSETING             0x00000008
1171  #define VMX_CPU_BASED_HLT_EXITING                   0x00000080
1172  #define VMX_CPU_BASED_INVLPG_EXITING                0x00000200
1173  #define VMX_CPU_BASED_MWAIT_EXITING                 0x00000400
1174  #define VMX_CPU_BASED_RDPMC_EXITING                 0x00000800
1175  #define VMX_CPU_BASED_RDTSC_EXITING                 0x00001000
1176  #define VMX_CPU_BASED_CR3_LOAD_EXITING              0x00008000
1177  #define VMX_CPU_BASED_CR3_STORE_EXITING             0x00010000
1178  #define VMX_CPU_BASED_CR8_LOAD_EXITING              0x00080000
1179  #define VMX_CPU_BASED_CR8_STORE_EXITING             0x00100000
1180  #define VMX_CPU_BASED_TPR_SHADOW                    0x00200000
1181  #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
1182  #define VMX_CPU_BASED_MOV_DR_EXITING                0x00800000
1183  #define VMX_CPU_BASED_UNCOND_IO_EXITING             0x01000000
1184  #define VMX_CPU_BASED_USE_IO_BITMAPS                0x02000000
1185  #define VMX_CPU_BASED_MONITOR_TRAP_FLAG             0x08000000
1186  #define VMX_CPU_BASED_USE_MSR_BITMAPS               0x10000000
1187  #define VMX_CPU_BASED_MONITOR_EXITING               0x20000000
1188  #define VMX_CPU_BASED_PAUSE_EXITING                 0x40000000
1189  #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
1190  
1191  #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1192  #define VMX_SECONDARY_EXEC_ENABLE_EPT               0x00000002
1193  #define VMX_SECONDARY_EXEC_DESC                     0x00000004
1194  #define VMX_SECONDARY_EXEC_RDTSCP                   0x00000008
1195  #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
1196  #define VMX_SECONDARY_EXEC_ENABLE_VPID              0x00000020
1197  #define VMX_SECONDARY_EXEC_WBINVD_EXITING           0x00000040
1198  #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
1199  #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
1200  #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
1201  #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
1202  #define VMX_SECONDARY_EXEC_RDRAND_EXITING           0x00000800
1203  #define VMX_SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
1204  #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC            0x00002000
1205  #define VMX_SECONDARY_EXEC_SHADOW_VMCS              0x00004000
1206  #define VMX_SECONDARY_EXEC_ENCLS_EXITING            0x00008000
1207  #define VMX_SECONDARY_EXEC_RDSEED_EXITING           0x00010000
1208  #define VMX_SECONDARY_EXEC_ENABLE_PML               0x00020000
1209  #define VMX_SECONDARY_EXEC_XSAVES                   0x00100000
1210  #define VMX_SECONDARY_EXEC_TSC_SCALING              0x02000000
1211  #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE   0x04000000
1212  
1213  #define VMX_PIN_BASED_EXT_INTR_MASK                 0x00000001
1214  #define VMX_PIN_BASED_NMI_EXITING                   0x00000008
1215  #define VMX_PIN_BASED_VIRTUAL_NMIS                  0x00000020
1216  #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
1217  #define VMX_PIN_BASED_POSTED_INTR                   0x00000080
1218  
1219  #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
1220  #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
1221  #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
1222  #define VMX_VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
1223  #define VMX_VM_EXIT_SAVE_IA32_PAT                   0x00040000
1224  #define VMX_VM_EXIT_LOAD_IA32_PAT                   0x00080000
1225  #define VMX_VM_EXIT_SAVE_IA32_EFER                  0x00100000
1226  #define VMX_VM_EXIT_LOAD_IA32_EFER                  0x00200000
1227  #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
1228  #define VMX_VM_EXIT_CLEAR_BNDCFGS                   0x00800000
1229  #define VMX_VM_EXIT_PT_CONCEAL_PIP                  0x01000000
1230  #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL             0x02000000
1231  #define VMX_VM_EXIT_LOAD_IA32_PKRS                  0x20000000
1232  #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS     0x80000000
1233  
1234  #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
1235  #define VMX_VM_ENTRY_IA32E_MODE                     0x00000200
1236  #define VMX_VM_ENTRY_SMM                            0x00000400
1237  #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
1238  #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
1239  #define VMX_VM_ENTRY_LOAD_IA32_PAT                  0x00004000
1240  #define VMX_VM_ENTRY_LOAD_IA32_EFER                 0x00008000
1241  #define VMX_VM_ENTRY_LOAD_BNDCFGS                   0x00010000
1242  #define VMX_VM_ENTRY_PT_CONCEAL_PIP                 0x00020000
1243  #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL             0x00040000
1244  #define VMX_VM_ENTRY_LOAD_IA32_PKRS                 0x00400000
1245  
1246  /* Supported Hyper-V Enlightenments */
1247  #define HYPERV_FEAT_RELAXED             0
1248  #define HYPERV_FEAT_VAPIC               1
1249  #define HYPERV_FEAT_TIME                2
1250  #define HYPERV_FEAT_CRASH               3
1251  #define HYPERV_FEAT_RESET               4
1252  #define HYPERV_FEAT_VPINDEX             5
1253  #define HYPERV_FEAT_RUNTIME             6
1254  #define HYPERV_FEAT_SYNIC               7
1255  #define HYPERV_FEAT_STIMER              8
1256  #define HYPERV_FEAT_FREQUENCIES         9
1257  #define HYPERV_FEAT_REENLIGHTENMENT     10
1258  #define HYPERV_FEAT_TLBFLUSH            11
1259  #define HYPERV_FEAT_EVMCS               12
1260  #define HYPERV_FEAT_IPI                 13
1261  #define HYPERV_FEAT_STIMER_DIRECT       14
1262  #define HYPERV_FEAT_AVIC                15
1263  #define HYPERV_FEAT_SYNDBG              16
1264  #define HYPERV_FEAT_MSR_BITMAP          17
1265  #define HYPERV_FEAT_XMM_INPUT           18
1266  #define HYPERV_FEAT_TLBFLUSH_EXT        19
1267  #define HYPERV_FEAT_TLBFLUSH_DIRECT     20
1268  
1269  #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1270  #define HYPERV_SPINLOCK_NEVER_NOTIFY             0xFFFFFFFF
1271  #endif
1272  
1273  #define EXCP00_DIVZ	0
1274  #define EXCP01_DB	1
1275  #define EXCP02_NMI	2
1276  #define EXCP03_INT3	3
1277  #define EXCP04_INTO	4
1278  #define EXCP05_BOUND	5
1279  #define EXCP06_ILLOP	6
1280  #define EXCP07_PREX	7
1281  #define EXCP08_DBLE	8
1282  #define EXCP09_XERR	9
1283  #define EXCP0A_TSS	10
1284  #define EXCP0B_NOSEG	11
1285  #define EXCP0C_STACK	12
1286  #define EXCP0D_GPF	13
1287  #define EXCP0E_PAGE	14
1288  #define EXCP10_COPR	16
1289  #define EXCP11_ALGN	17
1290  #define EXCP12_MCHK	18
1291  
1292  #define EXCP_VMEXIT     0x100 /* only for system emulation */
1293  #define EXCP_SYSCALL    0x101 /* only for user emulation */
1294  #define EXCP_VSYSCALL   0x102 /* only for user emulation */
1295  
1296  /* i386-specific interrupt pending bits.  */
1297  #define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
1298  #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
1299  #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
1300  #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
1301  #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
1302  #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_1
1303  #define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_2
1304  
1305  /* Use a clearer name for this.  */
1306  #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_RESET
1307  
1308  #define CC_OP_HAS_EFLAGS(op) ((op) >= CC_OP_EFLAGS && (op) <= CC_OP_ADCOX)
1309  
1310  /* Instead of computing the condition codes after each x86 instruction,
1311   * QEMU just stores one operand (called CC_SRC), the result
1312   * (called CC_DST) and the type of operation (called CC_OP). When the
1313   * condition codes are needed, the condition codes can be calculated
1314   * using this information. Condition codes are not generated if they
1315   * are only needed for conditional branches.
1316   */
1317  typedef enum {
1318      CC_OP_EFLAGS = 0,  /* all cc are explicitly computed, CC_SRC = flags */
1319      CC_OP_ADCX = 1,    /* CC_DST = C, CC_SRC = rest.  */
1320      CC_OP_ADOX = 2,    /* CC_SRC2 = O, CC_SRC = rest.  */
1321      CC_OP_ADCOX = 3,   /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */
1322  
1323      /* Low 2 bits = MemOp constant for the size */
1324  #define CC_OP_FIRST_BWLQ CC_OP_MULB
1325      CC_OP_MULB = 4, /* modify all flags, C, O = (CC_SRC != 0) */
1326      CC_OP_MULW,
1327      CC_OP_MULL,
1328      CC_OP_MULQ,
1329  
1330      CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1331      CC_OP_ADDW,
1332      CC_OP_ADDL,
1333      CC_OP_ADDQ,
1334  
1335      CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1336      CC_OP_ADCW,
1337      CC_OP_ADCL,
1338      CC_OP_ADCQ,
1339  
1340      CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1341      CC_OP_SUBW,
1342      CC_OP_SUBL,
1343      CC_OP_SUBQ,
1344  
1345      CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1346      CC_OP_SBBW,
1347      CC_OP_SBBL,
1348      CC_OP_SBBQ,
1349  
1350      CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1351      CC_OP_LOGICW,
1352      CC_OP_LOGICL,
1353      CC_OP_LOGICQ,
1354  
1355      CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1356      CC_OP_INCW,
1357      CC_OP_INCL,
1358      CC_OP_INCQ,
1359  
1360      CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
1361      CC_OP_DECW,
1362      CC_OP_DECL,
1363      CC_OP_DECQ,
1364  
1365      CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1366      CC_OP_SHLW,
1367      CC_OP_SHLL,
1368      CC_OP_SHLQ,
1369  
1370      CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1371      CC_OP_SARW,
1372      CC_OP_SARL,
1373      CC_OP_SARQ,
1374  
1375      CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1376      CC_OP_BMILGW,
1377      CC_OP_BMILGL,
1378      CC_OP_BMILGQ,
1379  
1380      CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */
1381      CC_OP_BLSIW,
1382      CC_OP_BLSIL,
1383      CC_OP_BLSIQ,
1384  
1385      /*
1386       * Note that only CC_OP_POPCNT (i.e. the one with MO_TL size)
1387       * is used or implemented, because the translation needs
1388       * to zero-extend CC_DST anyway.
1389       */
1390      CC_OP_POPCNTB__, /* Z via CC_DST, all other flags clear.  */
1391      CC_OP_POPCNTW__,
1392      CC_OP_POPCNTL__,
1393      CC_OP_POPCNTQ__,
1394      CC_OP_POPCNT = sizeof(target_ulong) == 8 ? CC_OP_POPCNTQ__ : CC_OP_POPCNTL__,
1395  #define CC_OP_LAST_BWLQ CC_OP_POPCNTQ__
1396  
1397      CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1398  } CCOp;
1399  
1400  /* See X86DecodedInsn.cc_op, using int8_t. */
1401  QEMU_BUILD_BUG_ON(CC_OP_DYNAMIC > INT8_MAX);
1402  
cc_op_size(CCOp op)1403  static inline MemOp cc_op_size(CCOp op)
1404  {
1405      MemOp size = op & 3;
1406  
1407      QEMU_BUILD_BUG_ON(CC_OP_FIRST_BWLQ & 3);
1408      assert(op >= CC_OP_FIRST_BWLQ && op <= CC_OP_LAST_BWLQ);
1409      assert(size <= MO_TL);
1410  
1411      return size;
1412  }
1413  
1414  typedef struct SegmentCache {
1415      uint32_t selector;
1416      target_ulong base;
1417      uint32_t limit;
1418      uint32_t flags;
1419  } SegmentCache;
1420  
1421  typedef union MMXReg {
1422      uint8_t  _b_MMXReg[64 / 8];
1423      uint16_t _w_MMXReg[64 / 16];
1424      uint32_t _l_MMXReg[64 / 32];
1425      uint64_t _q_MMXReg[64 / 64];
1426      float32  _s_MMXReg[64 / 32];
1427      float64  _d_MMXReg[64 / 64];
1428  } MMXReg;
1429  
1430  typedef union XMMReg {
1431      uint64_t _q_XMMReg[128 / 64];
1432  } XMMReg;
1433  
1434  typedef union YMMReg {
1435      uint64_t _q_YMMReg[256 / 64];
1436      XMMReg   _x_YMMReg[256 / 128];
1437  } YMMReg;
1438  
1439  typedef union ZMMReg {
1440      uint8_t  _b_ZMMReg[512 / 8];
1441      uint16_t _w_ZMMReg[512 / 16];
1442      uint32_t _l_ZMMReg[512 / 32];
1443      uint64_t _q_ZMMReg[512 / 64];
1444      float16  _h_ZMMReg[512 / 16];
1445      float32  _s_ZMMReg[512 / 32];
1446      float64  _d_ZMMReg[512 / 64];
1447      XMMReg   _x_ZMMReg[512 / 128];
1448      YMMReg   _y_ZMMReg[512 / 256];
1449  } ZMMReg;
1450  
1451  typedef struct BNDReg {
1452      uint64_t lb;
1453      uint64_t ub;
1454  } BNDReg;
1455  
1456  typedef struct BNDCSReg {
1457      uint64_t cfgu;
1458      uint64_t sts;
1459  } BNDCSReg;
1460  
1461  #define BNDCFG_ENABLE       1ULL
1462  #define BNDCFG_BNDPRESERVE  2ULL
1463  #define BNDCFG_BDIR_MASK    TARGET_PAGE_MASK
1464  
1465  #if HOST_BIG_ENDIAN
1466  #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1467  #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1468  #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1469  #define ZMM_H(n) _h_ZMMReg[31 - (n)]
1470  #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1471  #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1472  #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1473  #define ZMM_X(n) _x_ZMMReg[3 - (n)]
1474  #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1475  
1476  #define XMM_Q(n) _q_XMMReg[1 - (n)]
1477  
1478  #define YMM_Q(n) _q_YMMReg[3 - (n)]
1479  #define YMM_X(n) _x_YMMReg[1 - (n)]
1480  
1481  #define MMX_B(n) _b_MMXReg[7 - (n)]
1482  #define MMX_W(n) _w_MMXReg[3 - (n)]
1483  #define MMX_L(n) _l_MMXReg[1 - (n)]
1484  #define MMX_S(n) _s_MMXReg[1 - (n)]
1485  #else
1486  #define ZMM_B(n) _b_ZMMReg[n]
1487  #define ZMM_W(n) _w_ZMMReg[n]
1488  #define ZMM_L(n) _l_ZMMReg[n]
1489  #define ZMM_H(n) _h_ZMMReg[n]
1490  #define ZMM_S(n) _s_ZMMReg[n]
1491  #define ZMM_Q(n) _q_ZMMReg[n]
1492  #define ZMM_D(n) _d_ZMMReg[n]
1493  #define ZMM_X(n) _x_ZMMReg[n]
1494  #define ZMM_Y(n) _y_ZMMReg[n]
1495  
1496  #define XMM_Q(n) _q_XMMReg[n]
1497  
1498  #define YMM_Q(n) _q_YMMReg[n]
1499  #define YMM_X(n) _x_YMMReg[n]
1500  
1501  #define MMX_B(n) _b_MMXReg[n]
1502  #define MMX_W(n) _w_MMXReg[n]
1503  #define MMX_L(n) _l_MMXReg[n]
1504  #define MMX_S(n) _s_MMXReg[n]
1505  #endif
1506  #define MMX_Q(n) _q_MMXReg[n]
1507  
1508  typedef union {
1509      floatx80 d __attribute__((aligned(16)));
1510      MMXReg mmx;
1511  } FPReg;
1512  
1513  typedef struct {
1514      uint64_t base;
1515      uint64_t mask;
1516  } MTRRVar;
1517  
1518  #define CPU_NB_REGS64 16
1519  #define CPU_NB_REGS32 8
1520  
1521  #ifdef TARGET_X86_64
1522  #define CPU_NB_REGS CPU_NB_REGS64
1523  #else
1524  #define CPU_NB_REGS CPU_NB_REGS32
1525  #endif
1526  
1527  #define MAX_FIXED_COUNTERS 3
1528  #define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1529  
1530  #define TARGET_INSN_START_EXTRA_WORDS 1
1531  
1532  #define NB_OPMASK_REGS 8
1533  
1534  /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1535   * that APIC ID hasn't been set yet
1536   */
1537  #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1538  
1539  typedef struct X86LegacyXSaveArea {
1540      uint16_t fcw;
1541      uint16_t fsw;
1542      uint8_t ftw;
1543      uint8_t reserved;
1544      uint16_t fpop;
1545      union {
1546          struct {
1547              uint64_t fpip;
1548              uint64_t fpdp;
1549          };
1550          struct {
1551              uint32_t fip;
1552              uint32_t fcs;
1553              uint32_t foo;
1554              uint32_t fos;
1555          };
1556      };
1557      uint32_t mxcsr;
1558      uint32_t mxcsr_mask;
1559      FPReg fpregs[8];
1560      uint8_t xmm_regs[16][16];
1561      uint32_t hw_reserved[12];
1562      uint32_t sw_reserved[12];
1563  } X86LegacyXSaveArea;
1564  
1565  QEMU_BUILD_BUG_ON(sizeof(X86LegacyXSaveArea) != 512);
1566  
1567  typedef struct X86XSaveHeader {
1568      uint64_t xstate_bv;
1569      uint64_t xcomp_bv;
1570      uint64_t reserve0;
1571      uint8_t reserved[40];
1572  } X86XSaveHeader;
1573  
1574  /* Ext. save area 2: AVX State */
1575  typedef struct XSaveAVX {
1576      uint8_t ymmh[16][16];
1577  } XSaveAVX;
1578  
1579  /* Ext. save area 3: BNDREG */
1580  typedef struct XSaveBNDREG {
1581      BNDReg bnd_regs[4];
1582  } XSaveBNDREG;
1583  
1584  /* Ext. save area 4: BNDCSR */
1585  typedef union XSaveBNDCSR {
1586      BNDCSReg bndcsr;
1587      uint8_t data[64];
1588  } XSaveBNDCSR;
1589  
1590  /* Ext. save area 5: Opmask */
1591  typedef struct XSaveOpmask {
1592      uint64_t opmask_regs[NB_OPMASK_REGS];
1593  } XSaveOpmask;
1594  
1595  /* Ext. save area 6: ZMM_Hi256 */
1596  typedef struct XSaveZMM_Hi256 {
1597      uint8_t zmm_hi256[16][32];
1598  } XSaveZMM_Hi256;
1599  
1600  /* Ext. save area 7: Hi16_ZMM */
1601  typedef struct XSaveHi16_ZMM {
1602      uint8_t hi16_zmm[16][64];
1603  } XSaveHi16_ZMM;
1604  
1605  /* Ext. save area 9: PKRU state */
1606  typedef struct XSavePKRU {
1607      uint32_t pkru;
1608      uint32_t padding;
1609  } XSavePKRU;
1610  
1611  /* Ext. save area 17: AMX XTILECFG state */
1612  typedef struct XSaveXTILECFG {
1613      uint8_t xtilecfg[64];
1614  } XSaveXTILECFG;
1615  
1616  /* Ext. save area 18: AMX XTILEDATA state */
1617  typedef struct XSaveXTILEDATA {
1618      uint8_t xtiledata[8][1024];
1619  } XSaveXTILEDATA;
1620  
1621  typedef struct {
1622         uint64_t from;
1623         uint64_t to;
1624         uint64_t info;
1625  } LBREntry;
1626  
1627  #define ARCH_LBR_NR_ENTRIES            32
1628  
1629  /* Ext. save area 19: Supervisor mode Arch LBR state */
1630  typedef struct XSavesArchLBR {
1631      uint64_t lbr_ctl;
1632      uint64_t lbr_depth;
1633      uint64_t ler_from;
1634      uint64_t ler_to;
1635      uint64_t ler_info;
1636      LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1637  } XSavesArchLBR;
1638  
1639  QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1640  QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1641  QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1642  QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1643  QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1644  QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1645  QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1646  QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1647  QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1648  QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1649  
1650  typedef struct ExtSaveArea {
1651      uint32_t feature, bits;
1652      uint32_t offset, size;
1653      uint32_t ecx;
1654  } ExtSaveArea;
1655  
1656  #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1657  
1658  extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
1659  
1660  typedef enum TPRAccess {
1661      TPR_ACCESS_READ,
1662      TPR_ACCESS_WRITE,
1663  } TPRAccess;
1664  
1665  /* Cache information data structures: */
1666  
1667  enum CacheType {
1668      DATA_CACHE,
1669      INSTRUCTION_CACHE,
1670      UNIFIED_CACHE
1671  };
1672  
1673  typedef struct CPUCacheInfo {
1674      enum CacheType type;
1675      uint8_t level;
1676      /* Size in bytes */
1677      uint32_t size;
1678      /* Line size, in bytes */
1679      uint16_t line_size;
1680      /*
1681       * Associativity.
1682       * Note: representation of fully-associative caches is not implemented
1683       */
1684      uint8_t associativity;
1685      /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1686      uint8_t partitions;
1687      /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1688      uint32_t sets;
1689      /*
1690       * Lines per tag.
1691       * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1692       * (Is this synonym to @partitions?)
1693       */
1694      uint8_t lines_per_tag;
1695  
1696      /* Self-initializing cache */
1697      bool self_init;
1698      /*
1699       * WBINVD/INVD is not guaranteed to act upon lower level caches of
1700       * non-originating threads sharing this cache.
1701       * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1702       */
1703      bool no_invd_sharing;
1704      /*
1705       * Cache is inclusive of lower cache levels.
1706       * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1707       */
1708      bool inclusive;
1709      /*
1710       * A complex function is used to index the cache, potentially using all
1711       * address bits.  CPUID[4].EDX[bit 2].
1712       */
1713      bool complex_indexing;
1714  
1715      /*
1716       * Cache Topology. The level that cache is shared in.
1717       * Used to encode CPUID[4].EAX[bits 25:14] or
1718       * CPUID[0x8000001D].EAX[bits 25:14].
1719       */
1720      CpuTopologyLevel share_level;
1721  } CPUCacheInfo;
1722  
1723  
1724  typedef struct CPUCaches {
1725          CPUCacheInfo *l1d_cache;
1726          CPUCacheInfo *l1i_cache;
1727          CPUCacheInfo *l2_cache;
1728          CPUCacheInfo *l3_cache;
1729  } CPUCaches;
1730  
1731  typedef struct HVFX86LazyFlags {
1732      target_ulong result;
1733      target_ulong auxbits;
1734  } HVFX86LazyFlags;
1735  
1736  typedef struct CPUArchState {
1737      /* standard registers */
1738      target_ulong regs[CPU_NB_REGS];
1739      target_ulong eip;
1740      target_ulong eflags; /* eflags register. During CPU emulation, CC
1741                          flags and DF are set to zero because they are
1742                          stored elsewhere */
1743  
1744      /* emulator internal eflags handling */
1745      target_ulong cc_dst;
1746      target_ulong cc_src;
1747      target_ulong cc_src2;
1748      uint32_t cc_op;
1749      int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1750      uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1751                          are known at translation time. */
1752      uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1753  
1754      /* segments */
1755      SegmentCache segs[6]; /* selector values */
1756      SegmentCache ldt;
1757      SegmentCache tr;
1758      SegmentCache gdt; /* only base and limit are used */
1759      SegmentCache idt; /* only base and limit are used */
1760  
1761      target_ulong cr[5]; /* NOTE: cr1 is unused */
1762  
1763      bool pdptrs_valid;
1764      uint64_t pdptrs[4];
1765      int32_t a20_mask;
1766  
1767      BNDReg bnd_regs[4];
1768      BNDCSReg bndcs_regs;
1769      uint64_t msr_bndcfgs;
1770      uint64_t efer;
1771  
1772      /* Beginning of state preserved by INIT (dummy marker).  */
1773      struct {} start_init_save;
1774  
1775      /* FPU state */
1776      unsigned int fpstt; /* top of stack index */
1777      uint16_t fpus;
1778      uint16_t fpuc;
1779      uint8_t fptags[8];   /* 0 = valid, 1 = empty */
1780      FPReg fpregs[8];
1781      /* KVM-only so far */
1782      uint16_t fpop;
1783      uint16_t fpcs;
1784      uint16_t fpds;
1785      uint64_t fpip;
1786      uint64_t fpdp;
1787  
1788      /* emulator internal variables */
1789      float_status fp_status;
1790      floatx80 ft0;
1791  
1792      float_status mmx_status; /* for 3DNow! float ops */
1793      float_status sse_status;
1794      uint32_t mxcsr;
1795      ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
1796      ZMMReg xmm_t0 QEMU_ALIGNED(16);
1797      MMXReg mmx_t0;
1798  
1799      uint64_t opmask_regs[NB_OPMASK_REGS];
1800  #ifdef TARGET_X86_64
1801      uint8_t xtilecfg[64];
1802      uint8_t xtiledata[8192];
1803  #endif
1804  
1805      /* sysenter registers */
1806      uint32_t sysenter_cs;
1807      target_ulong sysenter_esp;
1808      target_ulong sysenter_eip;
1809      uint64_t star;
1810  
1811      uint64_t vm_hsave;
1812  
1813  #ifdef TARGET_X86_64
1814      target_ulong lstar;
1815      target_ulong cstar;
1816      target_ulong fmask;
1817      target_ulong kernelgsbase;
1818  
1819      /* FRED MSRs */
1820      uint64_t fred_rsp0;
1821      uint64_t fred_rsp1;
1822      uint64_t fred_rsp2;
1823      uint64_t fred_rsp3;
1824      uint64_t fred_stklvls;
1825      uint64_t fred_ssp1;
1826      uint64_t fred_ssp2;
1827      uint64_t fred_ssp3;
1828      uint64_t fred_config;
1829  #endif
1830  
1831      uint64_t tsc_adjust;
1832      uint64_t tsc_deadline;
1833      uint64_t tsc_aux;
1834  
1835      uint64_t xcr0;
1836  
1837      uint64_t mcg_status;
1838      uint64_t msr_ia32_misc_enable;
1839      uint64_t msr_ia32_feature_control;
1840      uint64_t msr_ia32_sgxlepubkeyhash[4];
1841  
1842      uint64_t msr_fixed_ctr_ctrl;
1843      uint64_t msr_global_ctrl;
1844      uint64_t msr_global_status;
1845      uint64_t msr_global_ovf_ctrl;
1846      uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1847      uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1848      uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1849  
1850      uint64_t pat;
1851      uint32_t smbase;
1852      uint64_t msr_smi_count;
1853  
1854      uint32_t pkru;
1855      uint32_t pkrs;
1856      uint32_t tsx_ctrl;
1857  
1858      uint64_t spec_ctrl;
1859      uint64_t amd_tsc_scale_msr;
1860      uint64_t virt_ssbd;
1861  
1862      /* End of state preserved by INIT (dummy marker).  */
1863      struct {} end_init_save;
1864  
1865      uint64_t system_time_msr;
1866      uint64_t wall_clock_msr;
1867      uint64_t steal_time_msr;
1868      uint64_t async_pf_en_msr;
1869      uint64_t async_pf_int_msr;
1870      uint64_t pv_eoi_en_msr;
1871      uint64_t poll_control_msr;
1872  
1873      /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1874      uint64_t msr_hv_hypercall;
1875      uint64_t msr_hv_guest_os_id;
1876      uint64_t msr_hv_tsc;
1877      uint64_t msr_hv_syndbg_control;
1878      uint64_t msr_hv_syndbg_status;
1879      uint64_t msr_hv_syndbg_send_page;
1880      uint64_t msr_hv_syndbg_recv_page;
1881      uint64_t msr_hv_syndbg_pending_page;
1882      uint64_t msr_hv_syndbg_options;
1883  
1884      /* Per-VCPU HV MSRs */
1885      uint64_t msr_hv_vapic;
1886      uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1887      uint64_t msr_hv_runtime;
1888      uint64_t msr_hv_synic_control;
1889      uint64_t msr_hv_synic_evt_page;
1890      uint64_t msr_hv_synic_msg_page;
1891      uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1892      uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1893      uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1894      uint64_t msr_hv_reenlightenment_control;
1895      uint64_t msr_hv_tsc_emulation_control;
1896      uint64_t msr_hv_tsc_emulation_status;
1897  
1898      uint64_t msr_rtit_ctrl;
1899      uint64_t msr_rtit_status;
1900      uint64_t msr_rtit_output_base;
1901      uint64_t msr_rtit_output_mask;
1902      uint64_t msr_rtit_cr3_match;
1903      uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1904  
1905      /* Per-VCPU XFD MSRs */
1906      uint64_t msr_xfd;
1907      uint64_t msr_xfd_err;
1908  
1909      /* Per-VCPU Arch LBR MSRs */
1910      uint64_t msr_lbr_ctl;
1911      uint64_t msr_lbr_depth;
1912      LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1913  
1914      /* AMD MSRC001_0015 Hardware Configuration */
1915      uint64_t msr_hwcr;
1916  
1917      /* exception/interrupt handling */
1918      int error_code;
1919      int exception_is_int;
1920      target_ulong exception_next_eip;
1921      target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1922      union {
1923          struct CPUBreakpoint *cpu_breakpoint[4];
1924          struct CPUWatchpoint *cpu_watchpoint[4];
1925      }; /* break/watchpoints for dr[0..3] */
1926      int old_exception;  /* exception in flight */
1927  
1928      uint64_t vm_vmcb;
1929      uint64_t tsc_offset;
1930      uint64_t intercept;
1931      uint16_t intercept_cr_read;
1932      uint16_t intercept_cr_write;
1933      uint16_t intercept_dr_read;
1934      uint16_t intercept_dr_write;
1935      uint32_t intercept_exceptions;
1936      uint64_t nested_cr3;
1937      uint32_t nested_pg_mode;
1938      uint8_t v_tpr;
1939      uint32_t int_ctl;
1940  
1941      /* KVM states, automatically cleared on reset */
1942      uint8_t nmi_injected;
1943      uint8_t nmi_pending;
1944  
1945      uintptr_t retaddr;
1946  
1947      /* RAPL MSR */
1948      uint64_t msr_rapl_power_unit;
1949      uint64_t msr_pkg_energy_status;
1950  
1951      /* Fields up to this point are cleared by a CPU reset */
1952      struct {} end_reset_fields;
1953  
1954      /* Fields after this point are preserved across CPU reset. */
1955  
1956      /* processor features (e.g. for CPUID insn) */
1957      /* Minimum cpuid leaf 7 value */
1958      uint32_t cpuid_level_func7;
1959      /* Actual cpuid leaf 7 value */
1960      uint32_t cpuid_min_level_func7;
1961      /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1962      uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1963      /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1964      uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1965      /* Actual level/xlevel/xlevel2 value: */
1966      uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1967      uint32_t cpuid_vendor1;
1968      uint32_t cpuid_vendor2;
1969      uint32_t cpuid_vendor3;
1970      uint32_t cpuid_version;
1971      FeatureWordArray features;
1972      /* AVX10 version */
1973      uint8_t avx10_version;
1974      /* Features that were explicitly enabled/disabled */
1975      FeatureWordArray user_features;
1976      uint32_t cpuid_model[12];
1977      /* Cache information for CPUID.  When legacy-cache=on, the cache data
1978       * on each CPUID leaf will be different, because we keep compatibility
1979       * with old QEMU versions.
1980       */
1981      CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1982  
1983      /* MTRRs */
1984      uint64_t mtrr_fixed[11];
1985      uint64_t mtrr_deftype;
1986      MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1987  
1988      /* For KVM */
1989      uint32_t mp_state;
1990      int32_t exception_nr;
1991      int32_t interrupt_injected;
1992      uint8_t soft_interrupt;
1993      uint8_t exception_pending;
1994      uint8_t exception_injected;
1995      uint8_t has_error_code;
1996      uint8_t exception_has_payload;
1997      uint64_t exception_payload;
1998      uint8_t triple_fault_pending;
1999      uint32_t ins_len;
2000      uint32_t sipi_vector;
2001      bool tsc_valid;
2002      int64_t tsc_khz;
2003      int64_t user_tsc_khz; /* for sanity check only */
2004      uint64_t apic_bus_freq;
2005      uint64_t tsc;
2006  #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
2007      void *xsave_buf;
2008      uint32_t xsave_buf_len;
2009  #endif
2010  #if defined(CONFIG_KVM)
2011      struct kvm_nested_state *nested_state;
2012      MemoryRegion *xen_vcpu_info_mr;
2013      void *xen_vcpu_info_hva;
2014      uint64_t xen_vcpu_info_gpa;
2015      uint64_t xen_vcpu_info_default_gpa;
2016      uint64_t xen_vcpu_time_info_gpa;
2017      uint64_t xen_vcpu_runstate_gpa;
2018      uint8_t xen_vcpu_callback_vector;
2019      bool xen_callback_asserted;
2020      uint16_t xen_virq[XEN_NR_VIRQS];
2021      uint64_t xen_singleshot_timer_ns;
2022      QEMUTimer *xen_singleshot_timer;
2023      uint64_t xen_periodic_timer_period;
2024      QEMUTimer *xen_periodic_timer;
2025      QemuMutex xen_timers_lock;
2026  #endif
2027  #if defined(CONFIG_HVF)
2028      HVFX86LazyFlags hvf_lflags;
2029      void *hvf_mmio_buf;
2030  #endif
2031  
2032      uint64_t mcg_cap;
2033      uint64_t mcg_ctl;
2034      uint64_t mcg_ext_ctl;
2035      uint64_t mce_banks[MCE_BANKS_DEF*4];
2036      uint64_t xstate_bv;
2037  
2038      /* vmstate */
2039      uint16_t fpus_vmstate;
2040      uint16_t fptag_vmstate;
2041      uint16_t fpregs_format_vmstate;
2042  
2043      uint64_t xss;
2044      uint32_t umwait;
2045  
2046      TPRAccess tpr_access_type;
2047  
2048      /* Number of dies within this CPU package. */
2049      unsigned nr_dies;
2050  
2051      /* Number of modules within one die. */
2052      unsigned nr_modules;
2053  
2054      /* Bitmap of available CPU topology levels for this CPU. */
2055      DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX);
2056  } CPUX86State;
2057  
2058  struct kvm_msrs;
2059  
2060  /**
2061   * X86CPU:
2062   * @env: #CPUX86State
2063   * @migratable: If set, only migratable flags will be accepted when "enforce"
2064   * mode is used, and only migratable flags will be included in the "host"
2065   * CPU model.
2066   *
2067   * An x86 CPU.
2068   */
2069  struct ArchCPU {
2070      CPUState parent_obj;
2071  
2072      CPUX86State env;
2073      VMChangeStateEntry *vmsentry;
2074  
2075      uint64_t ucode_rev;
2076  
2077      uint32_t hyperv_spinlock_attempts;
2078      char *hyperv_vendor;
2079      bool hyperv_synic_kvm_only;
2080      uint64_t hyperv_features;
2081      bool hyperv_passthrough;
2082      OnOffAuto hyperv_no_nonarch_cs;
2083      uint32_t hyperv_vendor_id[3];
2084      uint32_t hyperv_interface_id[4];
2085      uint32_t hyperv_limits[3];
2086      bool hyperv_enforce_cpuid;
2087      uint32_t hyperv_ver_id_build;
2088      uint16_t hyperv_ver_id_major;
2089      uint16_t hyperv_ver_id_minor;
2090      uint32_t hyperv_ver_id_sp;
2091      uint8_t hyperv_ver_id_sb;
2092      uint32_t hyperv_ver_id_sn;
2093  
2094      bool check_cpuid;
2095      bool enforce_cpuid;
2096      /*
2097       * Force features to be enabled even if the host doesn't support them.
2098       * This is dangerous and should be done only for testing CPUID
2099       * compatibility.
2100       */
2101      bool force_features;
2102      bool expose_kvm;
2103      bool expose_tcg;
2104      bool migratable;
2105      bool migrate_smi_count;
2106      bool max_features; /* Enable all supported features automatically */
2107      uint32_t apic_id;
2108  
2109      /* Enables publishing of TSC increment and Local APIC bus frequencies to
2110       * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
2111      bool vmware_cpuid_freq;
2112  
2113      /* if true the CPUID code directly forward host cache leaves to the guest */
2114      bool cache_info_passthrough;
2115  
2116      /* if true the CPUID code directly forwards
2117       * host monitor/mwait leaves to the guest */
2118      struct {
2119          uint32_t eax;
2120          uint32_t ebx;
2121          uint32_t ecx;
2122          uint32_t edx;
2123      } mwait;
2124  
2125      /* Features that were filtered out because of missing host capabilities */
2126      FeatureWordArray filtered_features;
2127  
2128      /* Enable PMU CPUID bits. This can't be enabled by default yet because
2129       * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
2130       * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
2131       * capabilities) directly to the guest.
2132       */
2133      bool enable_pmu;
2134  
2135      /*
2136       * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
2137       * This can't be initialized with a default because it doesn't have
2138       * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
2139       * returned by kvm_arch_get_supported_msr_feature()(which depends on both
2140       * host CPU and kernel capabilities) to the guest.
2141       */
2142      uint64_t lbr_fmt;
2143  
2144      /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
2145       * disabled by default to avoid breaking migration between QEMU with
2146       * different LMCE configurations.
2147       */
2148      bool enable_lmce;
2149  
2150      /* Compatibility bits for old machine types.
2151       * If true present virtual l3 cache for VM, the vcpus in the same virtual
2152       * socket share an virtual l3 cache.
2153       */
2154      bool enable_l3_cache;
2155  
2156      /* Compatibility bits for old machine types.
2157       * If true present L1 cache as per-thread, not per-core.
2158       */
2159      bool l1_cache_per_core;
2160  
2161      /* Compatibility bits for old machine types.
2162       * If true present the old cache topology information
2163       */
2164      bool legacy_cache;
2165  
2166      /* Compatibility bits for old machine types.
2167       * If true decode the CPUID Function 0x8000001E_ECX to support multiple
2168       * nodes per processor
2169       */
2170      bool legacy_multi_node;
2171  
2172      /* Compatibility bits for old machine types: */
2173      bool enable_cpuid_0xb;
2174  
2175      /* Enable auto level-increase for all CPUID leaves */
2176      bool full_cpuid_auto_level;
2177  
2178      /* Only advertise CPUID leaves defined by the vendor */
2179      bool vendor_cpuid_only;
2180  
2181      /* Only advertise TOPOEXT features that AMD defines */
2182      bool amd_topoext_features_only;
2183  
2184      /* Enable auto level-increase for Intel Processor Trace leave */
2185      bool intel_pt_auto_level;
2186  
2187      /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
2188      bool fill_mtrr_mask;
2189  
2190      /* if true override the phys_bits value with a value read from the host */
2191      bool host_phys_bits;
2192  
2193      /* if set, limit maximum value for phys_bits when host_phys_bits is true */
2194      uint8_t host_phys_bits_limit;
2195  
2196      /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
2197      bool kvm_pv_enforce_cpuid;
2198  
2199      /* Number of physical address bits supported */
2200      uint32_t phys_bits;
2201  
2202      /*
2203       * Number of guest physical address bits available. Usually this is
2204       * identical to host physical address bits. With NPT or EPT 4-level
2205       * paging, guest physical address space might be restricted to 48 bits
2206       * even if the host cpu supports more physical address bits.
2207       */
2208      uint32_t guest_phys_bits;
2209  
2210      /* in order to simplify APIC support, we leave this pointer to the
2211         user */
2212      struct DeviceState *apic_state;
2213      struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
2214      Notifier machine_done;
2215  
2216      struct kvm_msrs *kvm_msr_buf;
2217  
2218      int32_t node_id; /* NUMA node this CPU belongs to */
2219      int32_t socket_id;
2220      int32_t die_id;
2221      int32_t module_id;
2222      int32_t core_id;
2223      int32_t thread_id;
2224  
2225      int32_t hv_max_vps;
2226  
2227      bool xen_vapic;
2228  };
2229  
2230  typedef struct X86CPUModel X86CPUModel;
2231  
2232  /**
2233   * X86CPUClass:
2234   * @cpu_def: CPU model definition
2235   * @host_cpuid_required: Whether CPU model requires cpuid from host.
2236   * @ordering: Ordering on the "-cpu help" CPU model list.
2237   * @migration_safe: See CpuDefinitionInfo::migration_safe
2238   * @static_model: See CpuDefinitionInfo::static
2239   * @parent_realize: The parent class' realize handler.
2240   * @parent_phases: The parent class' reset phase handlers.
2241   *
2242   * An x86 CPU model or family.
2243   */
2244  struct X86CPUClass {
2245      CPUClass parent_class;
2246  
2247      /*
2248       * CPU definition, automatically loaded by instance_init if not NULL.
2249       * Should be eventually replaced by subclass-specific property defaults.
2250       */
2251      X86CPUModel *model;
2252  
2253      bool host_cpuid_required;
2254      int ordering;
2255      bool migration_safe;
2256      bool static_model;
2257  
2258      /*
2259       * Optional description of CPU model.
2260       * If unavailable, cpu_def->model_id is used.
2261       */
2262      const char *model_description;
2263  
2264      DeviceRealize parent_realize;
2265      DeviceUnrealize parent_unrealize;
2266      ResettablePhases parent_phases;
2267  };
2268  
2269  #ifndef CONFIG_USER_ONLY
2270  extern const VMStateDescription vmstate_x86_cpu;
2271  #endif
2272  
2273  int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
2274  
2275  int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
2276                               int cpuid, DumpState *s);
2277  int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
2278                               int cpuid, DumpState *s);
2279  int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2280                                   DumpState *s);
2281  int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2282                                   DumpState *s);
2283  
2284  bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
2285                                  Error **errp);
2286  
2287  void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
2288  
2289  int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
2290  int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
2291  void x86_cpu_gdb_init(CPUState *cs);
2292  
2293  void x86_cpu_list(void);
2294  int cpu_x86_support_mca_broadcast(CPUX86State *env);
2295  
2296  #ifndef CONFIG_USER_ONLY
2297  hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
2298                                           MemTxAttrs *attrs);
2299  int cpu_get_pic_interrupt(CPUX86State *s);
2300  
2301  /* MS-DOS compatibility mode FPU exception support */
2302  void x86_register_ferr_irq(qemu_irq irq);
2303  void fpu_check_raise_ferr_irq(CPUX86State *s);
2304  void cpu_set_ignne(void);
2305  void cpu_clear_ignne(void);
2306  #endif
2307  
2308  /* mpx_helper.c */
2309  void cpu_sync_bndcs_hflags(CPUX86State *env);
2310  
2311  /* this function must always be used to load data in the segment
2312     cache: it synchronizes the hflags with the segment cache values */
cpu_x86_load_seg_cache(CPUX86State * env,X86Seg seg_reg,unsigned int selector,target_ulong base,unsigned int limit,unsigned int flags)2313  static inline void cpu_x86_load_seg_cache(CPUX86State *env,
2314                                            X86Seg seg_reg, unsigned int selector,
2315                                            target_ulong base,
2316                                            unsigned int limit,
2317                                            unsigned int flags)
2318  {
2319      SegmentCache *sc;
2320      unsigned int new_hflags;
2321  
2322      sc = &env->segs[seg_reg];
2323      sc->selector = selector;
2324      sc->base = base;
2325      sc->limit = limit;
2326      sc->flags = flags;
2327  
2328      /* update the hidden flags */
2329      {
2330          if (seg_reg == R_CS) {
2331  #ifdef TARGET_X86_64
2332              if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
2333                  /* long mode */
2334                  env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2335                  env->hflags &= ~(HF_ADDSEG_MASK);
2336              } else
2337  #endif
2338              {
2339                  /* legacy / compatibility case */
2340                  new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
2341                      >> (DESC_B_SHIFT - HF_CS32_SHIFT);
2342                  env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
2343                      new_hflags;
2344              }
2345          }
2346          if (seg_reg == R_SS) {
2347              int cpl = (flags >> DESC_DPL_SHIFT) & 3;
2348  #if HF_CPL_MASK != 3
2349  #error HF_CPL_MASK is hardcoded
2350  #endif
2351              env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
2352              /* Possibly switch between BNDCFGS and BNDCFGU */
2353              cpu_sync_bndcs_hflags(env);
2354          }
2355          new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
2356              >> (DESC_B_SHIFT - HF_SS32_SHIFT);
2357          if (env->hflags & HF_CS64_MASK) {
2358              /* zero base assumed for DS, ES and SS in long mode */
2359          } else if (!(env->cr[0] & CR0_PE_MASK) ||
2360                     (env->eflags & VM_MASK) ||
2361                     !(env->hflags & HF_CS32_MASK)) {
2362              /* XXX: try to avoid this test. The problem comes from the
2363                 fact that is real mode or vm86 mode we only modify the
2364                 'base' and 'selector' fields of the segment cache to go
2365                 faster. A solution may be to force addseg to one in
2366                 translate-i386.c. */
2367              new_hflags |= HF_ADDSEG_MASK;
2368          } else {
2369              new_hflags |= ((env->segs[R_DS].base |
2370                              env->segs[R_ES].base |
2371                              env->segs[R_SS].base) != 0) <<
2372                  HF_ADDSEG_SHIFT;
2373          }
2374          env->hflags = (env->hflags &
2375                         ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
2376      }
2377  }
2378  
cpu_x86_load_seg_cache_sipi(X86CPU * cpu,uint8_t sipi_vector)2379  static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
2380                                                 uint8_t sipi_vector)
2381  {
2382      CPUState *cs = CPU(cpu);
2383      CPUX86State *env = &cpu->env;
2384  
2385      env->eip = 0;
2386      cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
2387                             sipi_vector << 12,
2388                             env->segs[R_CS].limit,
2389                             env->segs[R_CS].flags);
2390      cs->halted = 0;
2391  }
2392  
2393  int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
2394                              target_ulong *base, unsigned int *limit,
2395                              unsigned int *flags);
2396  
2397  /* op_helper.c */
2398  /* used for debug or cpu save/restore */
2399  
2400  /* cpu-exec.c */
2401  /*
2402   * The following helpers are only usable in user mode simulation.
2403   * The host pointers should come from lock_user().
2404   */
2405  void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
2406  void cpu_x86_fsave(CPUX86State *s, void *host, size_t len);
2407  void cpu_x86_frstor(CPUX86State *s, void *host, size_t len);
2408  void cpu_x86_fxsave(CPUX86State *s, void *host, size_t len);
2409  void cpu_x86_fxrstor(CPUX86State *s, void *host, size_t len);
2410  void cpu_x86_xsave(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2411  bool cpu_x86_xrstor(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2412  
2413  /* cpu.c */
2414  void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
2415                                uint32_t vendor2, uint32_t vendor3);
2416  typedef struct PropValue {
2417      const char *prop, *value;
2418  } PropValue;
2419  void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
2420  
2421  void x86_cpu_after_reset(X86CPU *cpu);
2422  
2423  uint32_t cpu_x86_virtual_addr_width(CPUX86State *env);
2424  
2425  /* cpu.c other functions (cpuid) */
2426  void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2427                     uint32_t *eax, uint32_t *ebx,
2428                     uint32_t *ecx, uint32_t *edx);
2429  void cpu_clear_apic_feature(CPUX86State *env);
2430  void cpu_set_apic_feature(CPUX86State *env);
2431  void host_cpuid(uint32_t function, uint32_t count,
2432                  uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
2433  bool cpu_has_x2apic_feature(CPUX86State *env);
2434  
2435  /* helper.c */
2436  void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
2437  void cpu_sync_avx_hflag(CPUX86State *env);
2438  
2439  #ifndef CONFIG_USER_ONLY
x86_asidx_from_attrs(CPUState * cs,MemTxAttrs attrs)2440  static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2441  {
2442      return !!attrs.secure;
2443  }
2444  
cpu_addressspace(CPUState * cs,MemTxAttrs attrs)2445  static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
2446  {
2447      return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
2448  }
2449  
2450  /*
2451   * load efer and update the corresponding hflags. XXX: do consistency
2452   * checks with cpuid bits?
2453   */
2454  void cpu_load_efer(CPUX86State *env, uint64_t val);
2455  uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
2456  uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
2457  uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
2458  uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
2459  void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
2460  void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
2461  void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
2462  void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
2463  void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
2464  #endif
2465  
2466  /* will be suppressed */
2467  void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
2468  void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
2469  void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
2470  void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
2471  
2472  /* hw/pc.c */
2473  uint64_t cpu_get_tsc(CPUX86State *env);
2474  
2475  #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2476  
2477  #ifdef TARGET_X86_64
2478  #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2479  #else
2480  #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2481  #endif
2482  
2483  #define cpu_list x86_cpu_list
2484  
2485  /* MMU modes definitions */
2486  #define MMU_KSMAP64_IDX    0
2487  #define MMU_KSMAP32_IDX    1
2488  #define MMU_USER64_IDX     2
2489  #define MMU_USER32_IDX     3
2490  #define MMU_KNOSMAP64_IDX  4
2491  #define MMU_KNOSMAP32_IDX  5
2492  #define MMU_PHYS_IDX       6
2493  #define MMU_NESTED_IDX     7
2494  
2495  #ifdef CONFIG_USER_ONLY
2496  #ifdef TARGET_X86_64
2497  #define MMU_USER_IDX MMU_USER64_IDX
2498  #else
2499  #define MMU_USER_IDX MMU_USER32_IDX
2500  #endif
2501  #endif
2502  
is_mmu_index_smap(int mmu_index)2503  static inline bool is_mmu_index_smap(int mmu_index)
2504  {
2505      return (mmu_index & ~1) == MMU_KSMAP64_IDX;
2506  }
2507  
is_mmu_index_user(int mmu_index)2508  static inline bool is_mmu_index_user(int mmu_index)
2509  {
2510      return (mmu_index & ~1) == MMU_USER64_IDX;
2511  }
2512  
is_mmu_index_32(int mmu_index)2513  static inline bool is_mmu_index_32(int mmu_index)
2514  {
2515      assert(mmu_index < MMU_PHYS_IDX);
2516      return mmu_index & 1;
2517  }
2518  
2519  int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
2520  int cpu_mmu_index_kernel(CPUX86State *env);
2521  
2522  #define CC_DST  (env->cc_dst)
2523  #define CC_SRC  (env->cc_src)
2524  #define CC_SRC2 (env->cc_src2)
2525  #define CC_OP   (env->cc_op)
2526  
2527  #include "exec/cpu-all.h"
2528  #include "svm.h"
2529  
2530  #if !defined(CONFIG_USER_ONLY)
2531  #include "hw/i386/apic.h"
2532  #endif
2533  
cpu_get_tb_cpu_state(CPUX86State * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)2534  static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
2535                                          uint64_t *cs_base, uint32_t *flags)
2536  {
2537      *flags = env->hflags |
2538          (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2539      if (env->hflags & HF_CS64_MASK) {
2540          *cs_base = 0;
2541          *pc = env->eip;
2542      } else {
2543          *cs_base = env->segs[R_CS].base;
2544          *pc = (uint32_t)(*cs_base + env->eip);
2545      }
2546  }
2547  
2548  void do_cpu_init(X86CPU *cpu);
2549  
2550  #define MCE_INJECT_BROADCAST    1
2551  #define MCE_INJECT_UNCOND_AO    2
2552  
2553  void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2554                          uint64_t status, uint64_t mcg_status, uint64_t addr,
2555                          uint64_t misc, int flags);
2556  
2557  uint32_t cpu_cc_compute_all(CPUX86State *env1);
2558  
cpu_compute_eflags(CPUX86State * env)2559  static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2560  {
2561      uint32_t eflags = env->eflags;
2562      if (tcg_enabled()) {
2563          eflags |= cpu_cc_compute_all(env) | (env->df & DF_MASK);
2564      }
2565      return eflags;
2566  }
2567  
cpu_get_mem_attrs(CPUX86State * env)2568  static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2569  {
2570      return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2571  }
2572  
x86_get_a20_mask(CPUX86State * env)2573  static inline int32_t x86_get_a20_mask(CPUX86State *env)
2574  {
2575      if (env->hflags & HF_SMM_MASK) {
2576          return -1;
2577      } else {
2578          return env->a20_mask;
2579      }
2580  }
2581  
cpu_has_vmx(CPUX86State * env)2582  static inline bool cpu_has_vmx(CPUX86State *env)
2583  {
2584      return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2585  }
2586  
cpu_has_svm(CPUX86State * env)2587  static inline bool cpu_has_svm(CPUX86State *env)
2588  {
2589      return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2590  }
2591  
2592  /*
2593   * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2594   * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2595   * VMX operation. This is because CR4.VMXE is one of the bits set
2596   * in MSR_IA32_VMX_CR4_FIXED1.
2597   *
2598   * There is one exception to above statement when vCPU enters SMM mode.
2599   * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2600   * may also reset CR4.VMXE during execution in SMM mode.
2601   * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2602   * and CR4.VMXE is restored to it's original value of being set.
2603   *
2604   * Therefore, when vCPU is not in SMM mode, we can infer whether
2605   * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2606   * know for certain.
2607   */
cpu_vmx_maybe_enabled(CPUX86State * env)2608  static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2609  {
2610      return cpu_has_vmx(env) &&
2611             ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2612  }
2613  
2614  /* excp_helper.c */
2615  int get_pg_mode(CPUX86State *env);
2616  
2617  /* fpu_helper.c */
2618  
2619  /* Set all non-runtime-variable float_status fields to x86 handling */
2620  void cpu_init_fp_statuses(CPUX86State *env);
2621  void update_fp_status(CPUX86State *env);
2622  void update_mxcsr_status(CPUX86State *env);
2623  void update_mxcsr_from_sse_status(CPUX86State *env);
2624  
cpu_set_mxcsr(CPUX86State * env,uint32_t mxcsr)2625  static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2626  {
2627      env->mxcsr = mxcsr;
2628      if (tcg_enabled()) {
2629          update_mxcsr_status(env);
2630      }
2631  }
2632  
cpu_set_fpuc(CPUX86State * env,uint16_t fpuc)2633  static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2634  {
2635       env->fpuc = fpuc;
2636       if (tcg_enabled()) {
2637          update_fp_status(env);
2638       }
2639  }
2640  
2641  /* svm_helper.c */
2642  #ifdef CONFIG_USER_ONLY
2643  static inline void
cpu_svm_check_intercept_param(CPUX86State * env1,uint32_t type,uint64_t param,uintptr_t retaddr)2644  cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2645                                uint64_t param, uintptr_t retaddr)
2646  { /* no-op */ }
2647  static inline bool
cpu_svm_has_intercept(CPUX86State * env,uint32_t type)2648  cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
2649  { return false; }
2650  #else
2651  void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2652                                     uint64_t param, uintptr_t retaddr);
2653  bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type);
2654  #endif
2655  
2656  /* apic.c */
2657  void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2658  void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2659                                     TPRAccess access);
2660  
2661  /* Special values for X86CPUVersion: */
2662  
2663  /* Resolve to latest CPU version */
2664  #define CPU_VERSION_LATEST -1
2665  
2666  /*
2667   * Resolve to version defined by current machine type.
2668   * See x86_cpu_set_default_version()
2669   */
2670  #define CPU_VERSION_AUTO   -2
2671  
2672  /* Don't resolve to any versioned CPU models, like old QEMU versions */
2673  #define CPU_VERSION_LEGACY  0
2674  
2675  typedef int X86CPUVersion;
2676  
2677  /*
2678   * Set default CPU model version for CPU models having
2679   * version == CPU_VERSION_AUTO.
2680   */
2681  void x86_cpu_set_default_version(X86CPUVersion version);
2682  
2683  #ifndef CONFIG_USER_ONLY
2684  
2685  void do_cpu_sipi(X86CPU *cpu);
2686  
2687  #define APIC_DEFAULT_ADDRESS 0xfee00000
2688  #define APIC_SPACE_SIZE      0x100000
2689  
2690  /* cpu-dump.c */
2691  void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2692  
2693  #endif
2694  
2695  /* cpu.c */
2696  bool cpu_is_bsp(X86CPU *cpu);
2697  
2698  void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen);
2699  void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen);
2700  uint32_t xsave_area_size(uint64_t mask, bool compacted);
2701  void x86_update_hflags(CPUX86State* env);
2702  
hyperv_feat_enabled(X86CPU * cpu,int feat)2703  static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2704  {
2705      return !!(cpu->hyperv_features & BIT(feat));
2706  }
2707  
cr4_reserved_bits(CPUX86State * env)2708  static inline uint64_t cr4_reserved_bits(CPUX86State *env)
2709  {
2710      uint64_t reserved_bits = CR4_RESERVED_MASK;
2711      if (!env->features[FEAT_XSAVE]) {
2712          reserved_bits |= CR4_OSXSAVE_MASK;
2713      }
2714      if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) {
2715          reserved_bits |= CR4_SMEP_MASK;
2716      }
2717      if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
2718          reserved_bits |= CR4_SMAP_MASK;
2719      }
2720      if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) {
2721          reserved_bits |= CR4_FSGSBASE_MASK;
2722      }
2723      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
2724          reserved_bits |= CR4_PKE_MASK;
2725      }
2726      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) {
2727          reserved_bits |= CR4_LA57_MASK;
2728      }
2729      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
2730          reserved_bits |= CR4_UMIP_MASK;
2731      }
2732      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
2733          reserved_bits |= CR4_PKS_MASK;
2734      }
2735      if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
2736          reserved_bits |= CR4_LAM_SUP_MASK;
2737      }
2738      if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) {
2739          reserved_bits |= CR4_FRED_MASK;
2740      }
2741      return reserved_bits;
2742  }
2743  
ctl_has_irq(CPUX86State * env)2744  static inline bool ctl_has_irq(CPUX86State *env)
2745  {
2746      uint32_t int_prio;
2747      uint32_t tpr;
2748  
2749      int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
2750      tpr = env->int_ctl & V_TPR_MASK;
2751  
2752      if (env->int_ctl & V_IGN_TPR_MASK) {
2753          return (env->int_ctl & V_IRQ_MASK);
2754      }
2755  
2756      return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
2757  }
2758  
2759  #if defined(TARGET_X86_64) && \
2760      defined(CONFIG_USER_ONLY) && \
2761      defined(CONFIG_LINUX)
2762  # define TARGET_VSYSCALL_PAGE  (UINT64_C(-10) << 20)
2763  #endif
2764  
2765  #endif /* I386_CPU_H */
2766