1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * i386 virtual CPU header 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003 Fabrice Bellard 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9d9ff33adSChetan Pant * version 2.1 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18fcf5ef2aSThomas Huth */ 19fcf5ef2aSThomas Huth 20fcf5ef2aSThomas Huth #ifndef I386_CPU_H 21fcf5ef2aSThomas Huth #define I386_CPU_H 22fcf5ef2aSThomas Huth 2314a48c1dSMarkus Armbruster #include "sysemu/tcg.h" 24fcf5ef2aSThomas Huth #include "cpu-qom.h" 25a9dc68d9SClaudio Fontana #include "kvm/hyperv-proto.h" 26c97d6d2cSSergio Andres Gomez Del Real #include "exec/cpu-defs.h" 2730d6ff66SVitaly Kuznetsov #include "qapi/qapi-types-common.h" 28c97d6d2cSSergio Andres Gomez Del Real 2972c1701fSAlex Bennée /* The x86 has a strong memory model with some store-after-load re-ordering */ 3072c1701fSAlex Bennée #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 3172c1701fSAlex Bennée 32e24fd076SDongjiu Geng #define KVM_HAVE_MCE_INJECTION 1 33e24fd076SDongjiu Geng 34fcf5ef2aSThomas Huth /* support for self modifying code even if the modified instruction is 35fcf5ef2aSThomas Huth close to the modifying instruction */ 36fcf5ef2aSThomas Huth #define TARGET_HAS_PRECISE_SMC 37fcf5ef2aSThomas Huth 38fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 39fcf5ef2aSThomas Huth #define I386_ELF_MACHINE EM_X86_64 40fcf5ef2aSThomas Huth #define ELF_MACHINE_UNAME "x86_64" 41fcf5ef2aSThomas Huth #else 42fcf5ef2aSThomas Huth #define I386_ELF_MACHINE EM_386 43fcf5ef2aSThomas Huth #define ELF_MACHINE_UNAME "i686" 44fcf5ef2aSThomas Huth #endif 45fcf5ef2aSThomas Huth 466701d81dSPaolo Bonzini enum { 476701d81dSPaolo Bonzini R_EAX = 0, 486701d81dSPaolo Bonzini R_ECX = 1, 496701d81dSPaolo Bonzini R_EDX = 2, 506701d81dSPaolo Bonzini R_EBX = 3, 516701d81dSPaolo Bonzini R_ESP = 4, 526701d81dSPaolo Bonzini R_EBP = 5, 536701d81dSPaolo Bonzini R_ESI = 6, 546701d81dSPaolo Bonzini R_EDI = 7, 556701d81dSPaolo Bonzini R_R8 = 8, 566701d81dSPaolo Bonzini R_R9 = 9, 576701d81dSPaolo Bonzini R_R10 = 10, 586701d81dSPaolo Bonzini R_R11 = 11, 596701d81dSPaolo Bonzini R_R12 = 12, 606701d81dSPaolo Bonzini R_R13 = 13, 616701d81dSPaolo Bonzini R_R14 = 14, 626701d81dSPaolo Bonzini R_R15 = 15, 63fcf5ef2aSThomas Huth 646701d81dSPaolo Bonzini R_AL = 0, 656701d81dSPaolo Bonzini R_CL = 1, 666701d81dSPaolo Bonzini R_DL = 2, 676701d81dSPaolo Bonzini R_BL = 3, 686701d81dSPaolo Bonzini R_AH = 4, 696701d81dSPaolo Bonzini R_CH = 5, 706701d81dSPaolo Bonzini R_DH = 6, 716701d81dSPaolo Bonzini R_BH = 7, 726701d81dSPaolo Bonzini }; 73fcf5ef2aSThomas Huth 746701d81dSPaolo Bonzini typedef enum X86Seg { 756701d81dSPaolo Bonzini R_ES = 0, 766701d81dSPaolo Bonzini R_CS = 1, 776701d81dSPaolo Bonzini R_SS = 2, 786701d81dSPaolo Bonzini R_DS = 3, 796701d81dSPaolo Bonzini R_FS = 4, 806701d81dSPaolo Bonzini R_GS = 5, 816701d81dSPaolo Bonzini R_LDTR = 6, 826701d81dSPaolo Bonzini R_TR = 7, 836701d81dSPaolo Bonzini } X86Seg; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth /* segment descriptor fields */ 86c97d6d2cSSergio Andres Gomez Del Real #define DESC_G_SHIFT 23 87c97d6d2cSSergio Andres Gomez Del Real #define DESC_G_MASK (1 << DESC_G_SHIFT) 88fcf5ef2aSThomas Huth #define DESC_B_SHIFT 22 89fcf5ef2aSThomas Huth #define DESC_B_MASK (1 << DESC_B_SHIFT) 90fcf5ef2aSThomas Huth #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 91fcf5ef2aSThomas Huth #define DESC_L_MASK (1 << DESC_L_SHIFT) 92c97d6d2cSSergio Andres Gomez Del Real #define DESC_AVL_SHIFT 20 93c97d6d2cSSergio Andres Gomez Del Real #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 94c97d6d2cSSergio Andres Gomez Del Real #define DESC_P_SHIFT 15 95c97d6d2cSSergio Andres Gomez Del Real #define DESC_P_MASK (1 << DESC_P_SHIFT) 96fcf5ef2aSThomas Huth #define DESC_DPL_SHIFT 13 97fcf5ef2aSThomas Huth #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 98c97d6d2cSSergio Andres Gomez Del Real #define DESC_S_SHIFT 12 99c97d6d2cSSergio Andres Gomez Del Real #define DESC_S_MASK (1 << DESC_S_SHIFT) 100fcf5ef2aSThomas Huth #define DESC_TYPE_SHIFT 8 101fcf5ef2aSThomas Huth #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 102fcf5ef2aSThomas Huth #define DESC_A_MASK (1 << 8) 103fcf5ef2aSThomas Huth 104fcf5ef2aSThomas Huth #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 105fcf5ef2aSThomas Huth #define DESC_C_MASK (1 << 10) /* code: conforming */ 106fcf5ef2aSThomas Huth #define DESC_R_MASK (1 << 9) /* code: readable */ 107fcf5ef2aSThomas Huth 108fcf5ef2aSThomas Huth #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 109fcf5ef2aSThomas Huth #define DESC_W_MASK (1 << 9) /* data: writable */ 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth #define DESC_TSS_BUSY_MASK (1 << 9) 112fcf5ef2aSThomas Huth 113fcf5ef2aSThomas Huth /* eflags masks */ 114fcf5ef2aSThomas Huth #define CC_C 0x0001 115fcf5ef2aSThomas Huth #define CC_P 0x0004 116fcf5ef2aSThomas Huth #define CC_A 0x0010 117fcf5ef2aSThomas Huth #define CC_Z 0x0040 118fcf5ef2aSThomas Huth #define CC_S 0x0080 119fcf5ef2aSThomas Huth #define CC_O 0x0800 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #define TF_SHIFT 8 122fcf5ef2aSThomas Huth #define IOPL_SHIFT 12 123fcf5ef2aSThomas Huth #define VM_SHIFT 17 124fcf5ef2aSThomas Huth 125fcf5ef2aSThomas Huth #define TF_MASK 0x00000100 126fcf5ef2aSThomas Huth #define IF_MASK 0x00000200 127fcf5ef2aSThomas Huth #define DF_MASK 0x00000400 128fcf5ef2aSThomas Huth #define IOPL_MASK 0x00003000 129fcf5ef2aSThomas Huth #define NT_MASK 0x00004000 130fcf5ef2aSThomas Huth #define RF_MASK 0x00010000 131fcf5ef2aSThomas Huth #define VM_MASK 0x00020000 132fcf5ef2aSThomas Huth #define AC_MASK 0x00040000 133fcf5ef2aSThomas Huth #define VIF_MASK 0x00080000 134fcf5ef2aSThomas Huth #define VIP_MASK 0x00100000 135fcf5ef2aSThomas Huth #define ID_MASK 0x00200000 136fcf5ef2aSThomas Huth 137fcf5ef2aSThomas Huth /* hidden flags - used internally by qemu to represent additional cpu 138fcf5ef2aSThomas Huth states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 139fcf5ef2aSThomas Huth avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 140fcf5ef2aSThomas Huth positions to ease oring with eflags. */ 141fcf5ef2aSThomas Huth /* current cpl */ 142fcf5ef2aSThomas Huth #define HF_CPL_SHIFT 0 143fcf5ef2aSThomas Huth /* true if hardware interrupts must be disabled for next instruction */ 144fcf5ef2aSThomas Huth #define HF_INHIBIT_IRQ_SHIFT 3 145fcf5ef2aSThomas Huth /* 16 or 32 segments */ 146fcf5ef2aSThomas Huth #define HF_CS32_SHIFT 4 147fcf5ef2aSThomas Huth #define HF_SS32_SHIFT 5 148fcf5ef2aSThomas Huth /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 149fcf5ef2aSThomas Huth #define HF_ADDSEG_SHIFT 6 150fcf5ef2aSThomas Huth /* copy of CR0.PE (protected mode) */ 151fcf5ef2aSThomas Huth #define HF_PE_SHIFT 7 152fcf5ef2aSThomas Huth #define HF_TF_SHIFT 8 /* must be same as eflags */ 153fcf5ef2aSThomas Huth #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 154fcf5ef2aSThomas Huth #define HF_EM_SHIFT 10 155fcf5ef2aSThomas Huth #define HF_TS_SHIFT 11 156fcf5ef2aSThomas Huth #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 157fcf5ef2aSThomas Huth #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 158fcf5ef2aSThomas Huth #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 159fcf5ef2aSThomas Huth #define HF_RF_SHIFT 16 /* must be same as eflags */ 160fcf5ef2aSThomas Huth #define HF_VM_SHIFT 17 /* must be same as eflags */ 161fcf5ef2aSThomas Huth #define HF_AC_SHIFT 18 /* must be same as eflags */ 162fcf5ef2aSThomas Huth #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 163fcf5ef2aSThomas Huth #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 164f8dc4c64SPaolo Bonzini #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 165fcf5ef2aSThomas Huth #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 166fcf5ef2aSThomas Huth #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 167fcf5ef2aSThomas Huth #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 168fcf5ef2aSThomas Huth #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 169fcf5ef2aSThomas Huth #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 170fcf5ef2aSThomas Huth 171fcf5ef2aSThomas Huth #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 172fcf5ef2aSThomas Huth #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 173fcf5ef2aSThomas Huth #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 174fcf5ef2aSThomas Huth #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 175fcf5ef2aSThomas Huth #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 176fcf5ef2aSThomas Huth #define HF_PE_MASK (1 << HF_PE_SHIFT) 177fcf5ef2aSThomas Huth #define HF_TF_MASK (1 << HF_TF_SHIFT) 178fcf5ef2aSThomas Huth #define HF_MP_MASK (1 << HF_MP_SHIFT) 179fcf5ef2aSThomas Huth #define HF_EM_MASK (1 << HF_EM_SHIFT) 180fcf5ef2aSThomas Huth #define HF_TS_MASK (1 << HF_TS_SHIFT) 181fcf5ef2aSThomas Huth #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 182fcf5ef2aSThomas Huth #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 183fcf5ef2aSThomas Huth #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 184fcf5ef2aSThomas Huth #define HF_RF_MASK (1 << HF_RF_SHIFT) 185fcf5ef2aSThomas Huth #define HF_VM_MASK (1 << HF_VM_SHIFT) 186fcf5ef2aSThomas Huth #define HF_AC_MASK (1 << HF_AC_SHIFT) 187fcf5ef2aSThomas Huth #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 188fcf5ef2aSThomas Huth #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 189f8dc4c64SPaolo Bonzini #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 190fcf5ef2aSThomas Huth #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 191fcf5ef2aSThomas Huth #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 192fcf5ef2aSThomas Huth #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 193fcf5ef2aSThomas Huth #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 194fcf5ef2aSThomas Huth #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 195fcf5ef2aSThomas Huth 196fcf5ef2aSThomas Huth /* hflags2 */ 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 199fcf5ef2aSThomas Huth #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 200fcf5ef2aSThomas Huth #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 201fcf5ef2aSThomas Huth #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 202fcf5ef2aSThomas Huth #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 203fcf5ef2aSThomas Huth #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 204fe441054SJan Kiszka #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 205bf13bfabSPaolo Bonzini #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 206b67e2796SLara Lazier #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/ 207fcf5ef2aSThomas Huth 208fcf5ef2aSThomas Huth #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 209fcf5ef2aSThomas Huth #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 210fcf5ef2aSThomas Huth #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 211fcf5ef2aSThomas Huth #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 212fcf5ef2aSThomas Huth #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 213fcf5ef2aSThomas Huth #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 214fe441054SJan Kiszka #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 215bf13bfabSPaolo Bonzini #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 216b67e2796SLara Lazier #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT) 217fcf5ef2aSThomas Huth 218fcf5ef2aSThomas Huth #define CR0_PE_SHIFT 0 219fcf5ef2aSThomas Huth #define CR0_MP_SHIFT 1 220fcf5ef2aSThomas Huth 221fcf5ef2aSThomas Huth #define CR0_PE_MASK (1U << 0) 222fcf5ef2aSThomas Huth #define CR0_MP_MASK (1U << 1) 223fcf5ef2aSThomas Huth #define CR0_EM_MASK (1U << 2) 224fcf5ef2aSThomas Huth #define CR0_TS_MASK (1U << 3) 225fcf5ef2aSThomas Huth #define CR0_ET_MASK (1U << 4) 226fcf5ef2aSThomas Huth #define CR0_NE_MASK (1U << 5) 227fcf5ef2aSThomas Huth #define CR0_WP_MASK (1U << 16) 228fcf5ef2aSThomas Huth #define CR0_AM_MASK (1U << 18) 229498df2a7SLara Lazier #define CR0_NW_MASK (1U << 29) 230498df2a7SLara Lazier #define CR0_CD_MASK (1U << 30) 231fcf5ef2aSThomas Huth #define CR0_PG_MASK (1U << 31) 232fcf5ef2aSThomas Huth 233fcf5ef2aSThomas Huth #define CR4_VME_MASK (1U << 0) 234fcf5ef2aSThomas Huth #define CR4_PVI_MASK (1U << 1) 235fcf5ef2aSThomas Huth #define CR4_TSD_MASK (1U << 2) 236fcf5ef2aSThomas Huth #define CR4_DE_MASK (1U << 3) 237fcf5ef2aSThomas Huth #define CR4_PSE_MASK (1U << 4) 238fcf5ef2aSThomas Huth #define CR4_PAE_MASK (1U << 5) 239fcf5ef2aSThomas Huth #define CR4_MCE_MASK (1U << 6) 240fcf5ef2aSThomas Huth #define CR4_PGE_MASK (1U << 7) 241fcf5ef2aSThomas Huth #define CR4_PCE_MASK (1U << 8) 242fcf5ef2aSThomas Huth #define CR4_OSFXSR_SHIFT 9 243fcf5ef2aSThomas Huth #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 244fcf5ef2aSThomas Huth #define CR4_OSXMMEXCPT_MASK (1U << 10) 245213ff024SLara Lazier #define CR4_UMIP_MASK (1U << 11) 2466c7c3c21SKirill A. Shutemov #define CR4_LA57_MASK (1U << 12) 247fcf5ef2aSThomas Huth #define CR4_VMXE_MASK (1U << 13) 248fcf5ef2aSThomas Huth #define CR4_SMXE_MASK (1U << 14) 249fcf5ef2aSThomas Huth #define CR4_FSGSBASE_MASK (1U << 16) 250fcf5ef2aSThomas Huth #define CR4_PCIDE_MASK (1U << 17) 251fcf5ef2aSThomas Huth #define CR4_OSXSAVE_MASK (1U << 18) 252fcf5ef2aSThomas Huth #define CR4_SMEP_MASK (1U << 20) 253fcf5ef2aSThomas Huth #define CR4_SMAP_MASK (1U << 21) 254fcf5ef2aSThomas Huth #define CR4_PKE_MASK (1U << 22) 255e7e7bdabSPaolo Bonzini #define CR4_PKS_MASK (1U << 24) 256fcf5ef2aSThomas Huth 257213ff024SLara Lazier #define CR4_RESERVED_MASK \ 258213ff024SLara Lazier (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ 259213ff024SLara Lazier | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ 260213ff024SLara Lazier | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ 261213ff024SLara Lazier | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK |CR4_UMIP_MASK \ 26269e3895fSDaniel P. Berrangé | CR4_LA57_MASK \ 263213ff024SLara Lazier | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ 264213ff024SLara Lazier | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) 265213ff024SLara Lazier 266fcf5ef2aSThomas Huth #define DR6_BD (1 << 13) 267fcf5ef2aSThomas Huth #define DR6_BS (1 << 14) 268fcf5ef2aSThomas Huth #define DR6_BT (1 << 15) 269fcf5ef2aSThomas Huth #define DR6_FIXED_1 0xffff0ff0 270fcf5ef2aSThomas Huth 271fcf5ef2aSThomas Huth #define DR7_GD (1 << 13) 272fcf5ef2aSThomas Huth #define DR7_TYPE_SHIFT 16 273fcf5ef2aSThomas Huth #define DR7_LEN_SHIFT 18 274fcf5ef2aSThomas Huth #define DR7_FIXED_1 0x00000400 275fcf5ef2aSThomas Huth #define DR7_GLOBAL_BP_MASK 0xaa 276fcf5ef2aSThomas Huth #define DR7_LOCAL_BP_MASK 0x55 277fcf5ef2aSThomas Huth #define DR7_MAX_BP 4 278fcf5ef2aSThomas Huth #define DR7_TYPE_BP_INST 0x0 279fcf5ef2aSThomas Huth #define DR7_TYPE_DATA_WR 0x1 280fcf5ef2aSThomas Huth #define DR7_TYPE_IO_RW 0x2 281fcf5ef2aSThomas Huth #define DR7_TYPE_DATA_RW 0x3 282fcf5ef2aSThomas Huth 283533883fdSPaolo Bonzini #define DR_RESERVED_MASK 0xffffffff00000000ULL 284533883fdSPaolo Bonzini 285fcf5ef2aSThomas Huth #define PG_PRESENT_BIT 0 286fcf5ef2aSThomas Huth #define PG_RW_BIT 1 287fcf5ef2aSThomas Huth #define PG_USER_BIT 2 288fcf5ef2aSThomas Huth #define PG_PWT_BIT 3 289fcf5ef2aSThomas Huth #define PG_PCD_BIT 4 290fcf5ef2aSThomas Huth #define PG_ACCESSED_BIT 5 291fcf5ef2aSThomas Huth #define PG_DIRTY_BIT 6 292fcf5ef2aSThomas Huth #define PG_PSE_BIT 7 293fcf5ef2aSThomas Huth #define PG_GLOBAL_BIT 8 294fcf5ef2aSThomas Huth #define PG_PSE_PAT_BIT 12 295fcf5ef2aSThomas Huth #define PG_PKRU_BIT 59 296fcf5ef2aSThomas Huth #define PG_NX_BIT 63 297fcf5ef2aSThomas Huth 298fcf5ef2aSThomas Huth #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 299fcf5ef2aSThomas Huth #define PG_RW_MASK (1 << PG_RW_BIT) 300fcf5ef2aSThomas Huth #define PG_USER_MASK (1 << PG_USER_BIT) 301fcf5ef2aSThomas Huth #define PG_PWT_MASK (1 << PG_PWT_BIT) 302fcf5ef2aSThomas Huth #define PG_PCD_MASK (1 << PG_PCD_BIT) 303fcf5ef2aSThomas Huth #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 304fcf5ef2aSThomas Huth #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 305fcf5ef2aSThomas Huth #define PG_PSE_MASK (1 << PG_PSE_BIT) 306fcf5ef2aSThomas Huth #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 307fcf5ef2aSThomas Huth #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 308fcf5ef2aSThomas Huth #define PG_ADDRESS_MASK 0x000ffffffffff000LL 309fcf5ef2aSThomas Huth #define PG_HI_USER_MASK 0x7ff0000000000000LL 310fcf5ef2aSThomas Huth #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 311fcf5ef2aSThomas Huth #define PG_NX_MASK (1ULL << PG_NX_BIT) 312fcf5ef2aSThomas Huth 313fcf5ef2aSThomas Huth #define PG_ERROR_W_BIT 1 314fcf5ef2aSThomas Huth 315fcf5ef2aSThomas Huth #define PG_ERROR_P_MASK 0x01 316fcf5ef2aSThomas Huth #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 317fcf5ef2aSThomas Huth #define PG_ERROR_U_MASK 0x04 318fcf5ef2aSThomas Huth #define PG_ERROR_RSVD_MASK 0x08 319fcf5ef2aSThomas Huth #define PG_ERROR_I_D_MASK 0x10 320fcf5ef2aSThomas Huth #define PG_ERROR_PK_MASK 0x20 321fcf5ef2aSThomas Huth 322616a89eaSPaolo Bonzini #define PG_MODE_PAE (1 << 0) 323616a89eaSPaolo Bonzini #define PG_MODE_LMA (1 << 1) 324616a89eaSPaolo Bonzini #define PG_MODE_NXE (1 << 2) 325616a89eaSPaolo Bonzini #define PG_MODE_PSE (1 << 3) 32631dd35ebSPaolo Bonzini #define PG_MODE_LA57 (1 << 4) 32731dd35ebSPaolo Bonzini #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) 32831dd35ebSPaolo Bonzini 32931dd35ebSPaolo Bonzini /* Bits of CR4 that do not affect the NPT page format. */ 33031dd35ebSPaolo Bonzini #define PG_MODE_WP (1 << 16) 33131dd35ebSPaolo Bonzini #define PG_MODE_PKE (1 << 17) 33231dd35ebSPaolo Bonzini #define PG_MODE_PKS (1 << 18) 33331dd35ebSPaolo Bonzini #define PG_MODE_SMEP (1 << 19) 334616a89eaSPaolo Bonzini 335fcf5ef2aSThomas Huth #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 336fcf5ef2aSThomas Huth #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 337fcf5ef2aSThomas Huth #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 338fcf5ef2aSThomas Huth 339fcf5ef2aSThomas Huth #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 340fcf5ef2aSThomas Huth #define MCE_BANKS_DEF 10 341fcf5ef2aSThomas Huth 342fcf5ef2aSThomas Huth #define MCG_CAP_BANKS_MASK 0xff 343fcf5ef2aSThomas Huth 344fcf5ef2aSThomas Huth #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 345fcf5ef2aSThomas Huth #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 346fcf5ef2aSThomas Huth #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 347fcf5ef2aSThomas Huth #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 348fcf5ef2aSThomas Huth 349fcf5ef2aSThomas Huth #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 352fcf5ef2aSThomas Huth #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 353fcf5ef2aSThomas Huth #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 354fcf5ef2aSThomas Huth #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 355fcf5ef2aSThomas Huth #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 356fcf5ef2aSThomas Huth #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 357fcf5ef2aSThomas Huth #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 358fcf5ef2aSThomas Huth #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 359fcf5ef2aSThomas Huth #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 360fcf5ef2aSThomas Huth 361fcf5ef2aSThomas Huth /* MISC register defines */ 362fcf5ef2aSThomas Huth #define MCM_ADDR_SEGOFF 0 /* segment offset */ 363fcf5ef2aSThomas Huth #define MCM_ADDR_LINEAR 1 /* linear address */ 364fcf5ef2aSThomas Huth #define MCM_ADDR_PHYS 2 /* physical address */ 365fcf5ef2aSThomas Huth #define MCM_ADDR_MEM 3 /* memory address */ 366fcf5ef2aSThomas Huth #define MCM_ADDR_GENERIC 7 /* generic */ 367fcf5ef2aSThomas Huth 368fcf5ef2aSThomas Huth #define MSR_IA32_TSC 0x10 369fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE 0x1b 370fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_BSP (1<<8) 371fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_ENABLE (1<<11) 372fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_EXTD (1 << 10) 373fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 374fcf5ef2aSThomas Huth #define MSR_IA32_FEATURE_CONTROL 0x0000003a 375fcf5ef2aSThomas Huth #define MSR_TSC_ADJUST 0x0000003b 376a33a2cfeSPaolo Bonzini #define MSR_IA32_SPEC_CTRL 0x48 377cfeea0c0SKonrad Rzeszutek Wilk #define MSR_VIRT_SSBD 0xc001011f 3788c80c99fSRobert Hoo #define MSR_IA32_PRED_CMD 0x49 3794e45aff3SPaolo Bonzini #define MSR_IA32_UCODE_REV 0x8b 380597360c0SXiaoyao Li #define MSR_IA32_CORE_CAPABILITY 0xcf 3812a9758c5SPaolo Bonzini 3828c80c99fSRobert Hoo #define MSR_IA32_ARCH_CAPABILITIES 0x10a 3832a9758c5SPaolo Bonzini #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 3842a9758c5SPaolo Bonzini 385ea39f9b6SLike Xu #define MSR_IA32_PERF_CAPABILITIES 0x345 386ea39f9b6SLike Xu 3872a9758c5SPaolo Bonzini #define MSR_IA32_TSX_CTRL 0x122 388fcf5ef2aSThomas Huth #define MSR_IA32_TSCDEADLINE 0x6e0 389e7e7bdabSPaolo Bonzini #define MSR_IA32_PKRS 0x6e1 390fcf5ef2aSThomas Huth 391fcf5ef2aSThomas Huth #define FEATURE_CONTROL_LOCKED (1<<0) 3925c76b651SSean Christopherson #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1) 393fcf5ef2aSThomas Huth #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 3945c76b651SSean Christopherson #define FEATURE_CONTROL_SGX_LC (1ULL << 17) 3955c76b651SSean Christopherson #define FEATURE_CONTROL_SGX (1ULL << 18) 396fcf5ef2aSThomas Huth #define FEATURE_CONTROL_LMCE (1<<20) 397fcf5ef2aSThomas Huth 3985c76b651SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c 3995c76b651SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d 4005c76b651SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e 4015c76b651SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f 4025c76b651SSean Christopherson 403fcf5ef2aSThomas Huth #define MSR_P6_PERFCTR0 0xc1 404fcf5ef2aSThomas Huth 405fcf5ef2aSThomas Huth #define MSR_IA32_SMBASE 0x9e 406e13713dbSLiran Alon #define MSR_SMI_COUNT 0x34 407027ac0cbSVladislav Yaroshchuk #define MSR_CORE_THREAD_COUNT 0x35 408fcf5ef2aSThomas Huth #define MSR_MTRRcap 0xfe 409fcf5ef2aSThomas Huth #define MSR_MTRRcap_VCNT 8 410fcf5ef2aSThomas Huth #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 411fcf5ef2aSThomas Huth #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 412fcf5ef2aSThomas Huth 413fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_CS 0x174 414fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_ESP 0x175 415fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_EIP 0x176 416fcf5ef2aSThomas Huth 417fcf5ef2aSThomas Huth #define MSR_MCG_CAP 0x179 418fcf5ef2aSThomas Huth #define MSR_MCG_STATUS 0x17a 419fcf5ef2aSThomas Huth #define MSR_MCG_CTL 0x17b 420fcf5ef2aSThomas Huth #define MSR_MCG_EXT_CTL 0x4d0 421fcf5ef2aSThomas Huth 422fcf5ef2aSThomas Huth #define MSR_P6_EVNTSEL0 0x186 423fcf5ef2aSThomas Huth 424fcf5ef2aSThomas Huth #define MSR_IA32_PERF_STATUS 0x198 425fcf5ef2aSThomas Huth 426fcf5ef2aSThomas Huth #define MSR_IA32_MISC_ENABLE 0x1a0 427fcf5ef2aSThomas Huth /* Indicates good rep/movs microcode on some processors: */ 428fcf5ef2aSThomas Huth #define MSR_IA32_MISC_ENABLE_DEFAULT 1 4294cfd7babSWanpeng Li #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 430fcf5ef2aSThomas Huth 431fcf5ef2aSThomas Huth #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 432fcf5ef2aSThomas Huth #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 433fcf5ef2aSThomas Huth 434fcf5ef2aSThomas Huth #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 435fcf5ef2aSThomas Huth 436fcf5ef2aSThomas Huth #define MSR_MTRRfix64K_00000 0x250 437fcf5ef2aSThomas Huth #define MSR_MTRRfix16K_80000 0x258 438fcf5ef2aSThomas Huth #define MSR_MTRRfix16K_A0000 0x259 439fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_C0000 0x268 440fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_C8000 0x269 441fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_D0000 0x26a 442fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_D8000 0x26b 443fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_E0000 0x26c 444fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_E8000 0x26d 445fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_F0000 0x26e 446fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_F8000 0x26f 447fcf5ef2aSThomas Huth 448fcf5ef2aSThomas Huth #define MSR_PAT 0x277 449fcf5ef2aSThomas Huth 450fcf5ef2aSThomas Huth #define MSR_MTRRdefType 0x2ff 451fcf5ef2aSThomas Huth 452fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR0 0x309 453fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR1 0x30a 454fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR2 0x30b 455fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 456fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 457fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 458fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 459fcf5ef2aSThomas Huth 460fcf5ef2aSThomas Huth #define MSR_MC0_CTL 0x400 461fcf5ef2aSThomas Huth #define MSR_MC0_STATUS 0x401 462fcf5ef2aSThomas Huth #define MSR_MC0_ADDR 0x402 463fcf5ef2aSThomas Huth #define MSR_MC0_MISC 0x403 464fcf5ef2aSThomas Huth 465b77146e9SChao Peng #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 466b77146e9SChao Peng #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 467b77146e9SChao Peng #define MSR_IA32_RTIT_CTL 0x570 468b77146e9SChao Peng #define MSR_IA32_RTIT_STATUS 0x571 469b77146e9SChao Peng #define MSR_IA32_RTIT_CR3_MATCH 0x572 470b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR0_A 0x580 471b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR0_B 0x581 472b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR1_A 0x582 473b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR1_B 0x583 474b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR2_A 0x584 475b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR2_B 0x585 476b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR3_A 0x586 477b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR3_B 0x587 478b77146e9SChao Peng #define MAX_RTIT_ADDRS 8 479b77146e9SChao Peng 480fcf5ef2aSThomas Huth #define MSR_EFER 0xc0000080 481fcf5ef2aSThomas Huth 482fcf5ef2aSThomas Huth #define MSR_EFER_SCE (1 << 0) 483fcf5ef2aSThomas Huth #define MSR_EFER_LME (1 << 8) 484fcf5ef2aSThomas Huth #define MSR_EFER_LMA (1 << 10) 485fcf5ef2aSThomas Huth #define MSR_EFER_NXE (1 << 11) 486fcf5ef2aSThomas Huth #define MSR_EFER_SVME (1 << 12) 487fcf5ef2aSThomas Huth #define MSR_EFER_FFXSR (1 << 14) 488fcf5ef2aSThomas Huth 489d499f196SLara Lazier #define MSR_EFER_RESERVED\ 490d499f196SLara Lazier (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\ 491d499f196SLara Lazier | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\ 492d499f196SLara Lazier | MSR_EFER_FFXSR)) 493d499f196SLara Lazier 494fcf5ef2aSThomas Huth #define MSR_STAR 0xc0000081 495fcf5ef2aSThomas Huth #define MSR_LSTAR 0xc0000082 496fcf5ef2aSThomas Huth #define MSR_CSTAR 0xc0000083 497fcf5ef2aSThomas Huth #define MSR_FMASK 0xc0000084 498fcf5ef2aSThomas Huth #define MSR_FSBASE 0xc0000100 499fcf5ef2aSThomas Huth #define MSR_GSBASE 0xc0000101 500fcf5ef2aSThomas Huth #define MSR_KERNELGSBASE 0xc0000102 501fcf5ef2aSThomas Huth #define MSR_TSC_AUX 0xc0000103 502fcf5ef2aSThomas Huth 503fcf5ef2aSThomas Huth #define MSR_VM_HSAVE_PA 0xc0010117 504fcf5ef2aSThomas Huth 505fcf5ef2aSThomas Huth #define MSR_IA32_BNDCFGS 0x00000d90 506fcf5ef2aSThomas Huth #define MSR_IA32_XSS 0x00000da0 50765087997STao Xu #define MSR_IA32_UMWAIT_CONTROL 0xe1 508fcf5ef2aSThomas Huth 509704798adSPaolo Bonzini #define MSR_IA32_VMX_BASIC 0x00000480 510704798adSPaolo Bonzini #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 511704798adSPaolo Bonzini #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 512704798adSPaolo Bonzini #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 513704798adSPaolo Bonzini #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 514704798adSPaolo Bonzini #define MSR_IA32_VMX_MISC 0x00000485 515704798adSPaolo Bonzini #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 516704798adSPaolo Bonzini #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 517704798adSPaolo Bonzini #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 518704798adSPaolo Bonzini #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 519704798adSPaolo Bonzini #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 520704798adSPaolo Bonzini #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 521704798adSPaolo Bonzini #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 522704798adSPaolo Bonzini #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 523704798adSPaolo Bonzini #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 524704798adSPaolo Bonzini #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 525704798adSPaolo Bonzini #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 526704798adSPaolo Bonzini #define MSR_IA32_VMX_VMFUNC 0x00000491 527704798adSPaolo Bonzini 528fcf5ef2aSThomas Huth #define XSTATE_FP_BIT 0 529fcf5ef2aSThomas Huth #define XSTATE_SSE_BIT 1 530fcf5ef2aSThomas Huth #define XSTATE_YMM_BIT 2 531fcf5ef2aSThomas Huth #define XSTATE_BNDREGS_BIT 3 532fcf5ef2aSThomas Huth #define XSTATE_BNDCSR_BIT 4 533fcf5ef2aSThomas Huth #define XSTATE_OPMASK_BIT 5 534fcf5ef2aSThomas Huth #define XSTATE_ZMM_Hi256_BIT 6 535fcf5ef2aSThomas Huth #define XSTATE_Hi16_ZMM_BIT 7 536fcf5ef2aSThomas Huth #define XSTATE_PKRU_BIT 9 537fcf5ef2aSThomas Huth 538fcf5ef2aSThomas Huth #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 539fcf5ef2aSThomas Huth #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 540fcf5ef2aSThomas Huth #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 541fcf5ef2aSThomas Huth #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 542fcf5ef2aSThomas Huth #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 543fcf5ef2aSThomas Huth #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 544fcf5ef2aSThomas Huth #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 545fcf5ef2aSThomas Huth #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 546fcf5ef2aSThomas Huth #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 547fcf5ef2aSThomas Huth 548fcf5ef2aSThomas Huth /* CPUID feature words */ 549fcf5ef2aSThomas Huth typedef enum FeatureWord { 550fcf5ef2aSThomas Huth FEAT_1_EDX, /* CPUID[1].EDX */ 551fcf5ef2aSThomas Huth FEAT_1_ECX, /* CPUID[1].ECX */ 552fcf5ef2aSThomas Huth FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 553fcf5ef2aSThomas Huth FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 554fcf5ef2aSThomas Huth FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 55580db491dSJing Liu FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 556fcf5ef2aSThomas Huth FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 557fcf5ef2aSThomas Huth FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 558fcf5ef2aSThomas Huth FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 5591b3420e1SEduardo Habkost FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 560fcf5ef2aSThomas Huth FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 561fcf5ef2aSThomas Huth FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 562be777326SWanpeng Li FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 563fcf5ef2aSThomas Huth FEAT_SVM, /* CPUID[8000_000A].EDX */ 564fcf5ef2aSThomas Huth FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 565fcf5ef2aSThomas Huth FEAT_6_EAX, /* CPUID[6].EAX */ 566fcf5ef2aSThomas Huth FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 567fcf5ef2aSThomas Huth FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 568d86f9636SRobert Hoo FEAT_ARCH_CAPABILITIES, 569597360c0SXiaoyao Li FEAT_CORE_CAPABILITY, 570ea39f9b6SLike Xu FEAT_PERF_CAPABILITIES, 57120a78b02SPaolo Bonzini FEAT_VMX_PROCBASED_CTLS, 57220a78b02SPaolo Bonzini FEAT_VMX_SECONDARY_CTLS, 57320a78b02SPaolo Bonzini FEAT_VMX_PINBASED_CTLS, 57420a78b02SPaolo Bonzini FEAT_VMX_EXIT_CTLS, 57520a78b02SPaolo Bonzini FEAT_VMX_ENTRY_CTLS, 57620a78b02SPaolo Bonzini FEAT_VMX_MISC, 57720a78b02SPaolo Bonzini FEAT_VMX_EPT_VPID_CAPS, 57820a78b02SPaolo Bonzini FEAT_VMX_BASIC, 57920a78b02SPaolo Bonzini FEAT_VMX_VMFUNC, 580d1615ea5SLuwei Kang FEAT_14_0_ECX, 5814b841a79SSean Christopherson FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */ 582120ca112SSean Christopherson FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */ 583165981a5SSean Christopherson FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ 584fcf5ef2aSThomas Huth FEATURE_WORDS, 585fcf5ef2aSThomas Huth } FeatureWord; 586fcf5ef2aSThomas Huth 587ede146c2SPaolo Bonzini typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 588fcf5ef2aSThomas Huth 589fcf5ef2aSThomas Huth /* cpuid_features bits */ 590fcf5ef2aSThomas Huth #define CPUID_FP87 (1U << 0) 591fcf5ef2aSThomas Huth #define CPUID_VME (1U << 1) 592fcf5ef2aSThomas Huth #define CPUID_DE (1U << 2) 593fcf5ef2aSThomas Huth #define CPUID_PSE (1U << 3) 594fcf5ef2aSThomas Huth #define CPUID_TSC (1U << 4) 595fcf5ef2aSThomas Huth #define CPUID_MSR (1U << 5) 596fcf5ef2aSThomas Huth #define CPUID_PAE (1U << 6) 597fcf5ef2aSThomas Huth #define CPUID_MCE (1U << 7) 598fcf5ef2aSThomas Huth #define CPUID_CX8 (1U << 8) 599fcf5ef2aSThomas Huth #define CPUID_APIC (1U << 9) 600fcf5ef2aSThomas Huth #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 601fcf5ef2aSThomas Huth #define CPUID_MTRR (1U << 12) 602fcf5ef2aSThomas Huth #define CPUID_PGE (1U << 13) 603fcf5ef2aSThomas Huth #define CPUID_MCA (1U << 14) 604fcf5ef2aSThomas Huth #define CPUID_CMOV (1U << 15) 605fcf5ef2aSThomas Huth #define CPUID_PAT (1U << 16) 606fcf5ef2aSThomas Huth #define CPUID_PSE36 (1U << 17) 607fcf5ef2aSThomas Huth #define CPUID_PN (1U << 18) 608fcf5ef2aSThomas Huth #define CPUID_CLFLUSH (1U << 19) 609fcf5ef2aSThomas Huth #define CPUID_DTS (1U << 21) 610fcf5ef2aSThomas Huth #define CPUID_ACPI (1U << 22) 611fcf5ef2aSThomas Huth #define CPUID_MMX (1U << 23) 612fcf5ef2aSThomas Huth #define CPUID_FXSR (1U << 24) 613fcf5ef2aSThomas Huth #define CPUID_SSE (1U << 25) 614fcf5ef2aSThomas Huth #define CPUID_SSE2 (1U << 26) 615fcf5ef2aSThomas Huth #define CPUID_SS (1U << 27) 616fcf5ef2aSThomas Huth #define CPUID_HT (1U << 28) 617fcf5ef2aSThomas Huth #define CPUID_TM (1U << 29) 618fcf5ef2aSThomas Huth #define CPUID_IA64 (1U << 30) 619fcf5ef2aSThomas Huth #define CPUID_PBE (1U << 31) 620fcf5ef2aSThomas Huth 621fcf5ef2aSThomas Huth #define CPUID_EXT_SSE3 (1U << 0) 622fcf5ef2aSThomas Huth #define CPUID_EXT_PCLMULQDQ (1U << 1) 623fcf5ef2aSThomas Huth #define CPUID_EXT_DTES64 (1U << 2) 624fcf5ef2aSThomas Huth #define CPUID_EXT_MONITOR (1U << 3) 625fcf5ef2aSThomas Huth #define CPUID_EXT_DSCPL (1U << 4) 626fcf5ef2aSThomas Huth #define CPUID_EXT_VMX (1U << 5) 627fcf5ef2aSThomas Huth #define CPUID_EXT_SMX (1U << 6) 628fcf5ef2aSThomas Huth #define CPUID_EXT_EST (1U << 7) 629fcf5ef2aSThomas Huth #define CPUID_EXT_TM2 (1U << 8) 630fcf5ef2aSThomas Huth #define CPUID_EXT_SSSE3 (1U << 9) 631fcf5ef2aSThomas Huth #define CPUID_EXT_CID (1U << 10) 632fcf5ef2aSThomas Huth #define CPUID_EXT_FMA (1U << 12) 633fcf5ef2aSThomas Huth #define CPUID_EXT_CX16 (1U << 13) 634fcf5ef2aSThomas Huth #define CPUID_EXT_XTPR (1U << 14) 635fcf5ef2aSThomas Huth #define CPUID_EXT_PDCM (1U << 15) 636fcf5ef2aSThomas Huth #define CPUID_EXT_PCID (1U << 17) 637fcf5ef2aSThomas Huth #define CPUID_EXT_DCA (1U << 18) 638fcf5ef2aSThomas Huth #define CPUID_EXT_SSE41 (1U << 19) 639fcf5ef2aSThomas Huth #define CPUID_EXT_SSE42 (1U << 20) 640fcf5ef2aSThomas Huth #define CPUID_EXT_X2APIC (1U << 21) 641fcf5ef2aSThomas Huth #define CPUID_EXT_MOVBE (1U << 22) 642fcf5ef2aSThomas Huth #define CPUID_EXT_POPCNT (1U << 23) 643fcf5ef2aSThomas Huth #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 644fcf5ef2aSThomas Huth #define CPUID_EXT_AES (1U << 25) 645fcf5ef2aSThomas Huth #define CPUID_EXT_XSAVE (1U << 26) 646fcf5ef2aSThomas Huth #define CPUID_EXT_OSXSAVE (1U << 27) 647fcf5ef2aSThomas Huth #define CPUID_EXT_AVX (1U << 28) 648fcf5ef2aSThomas Huth #define CPUID_EXT_F16C (1U << 29) 649fcf5ef2aSThomas Huth #define CPUID_EXT_RDRAND (1U << 30) 650fcf5ef2aSThomas Huth #define CPUID_EXT_HYPERVISOR (1U << 31) 651fcf5ef2aSThomas Huth 652fcf5ef2aSThomas Huth #define CPUID_EXT2_FPU (1U << 0) 653fcf5ef2aSThomas Huth #define CPUID_EXT2_VME (1U << 1) 654fcf5ef2aSThomas Huth #define CPUID_EXT2_DE (1U << 2) 655fcf5ef2aSThomas Huth #define CPUID_EXT2_PSE (1U << 3) 656fcf5ef2aSThomas Huth #define CPUID_EXT2_TSC (1U << 4) 657fcf5ef2aSThomas Huth #define CPUID_EXT2_MSR (1U << 5) 658fcf5ef2aSThomas Huth #define CPUID_EXT2_PAE (1U << 6) 659fcf5ef2aSThomas Huth #define CPUID_EXT2_MCE (1U << 7) 660fcf5ef2aSThomas Huth #define CPUID_EXT2_CX8 (1U << 8) 661fcf5ef2aSThomas Huth #define CPUID_EXT2_APIC (1U << 9) 662fcf5ef2aSThomas Huth #define CPUID_EXT2_SYSCALL (1U << 11) 663fcf5ef2aSThomas Huth #define CPUID_EXT2_MTRR (1U << 12) 664fcf5ef2aSThomas Huth #define CPUID_EXT2_PGE (1U << 13) 665fcf5ef2aSThomas Huth #define CPUID_EXT2_MCA (1U << 14) 666fcf5ef2aSThomas Huth #define CPUID_EXT2_CMOV (1U << 15) 667fcf5ef2aSThomas Huth #define CPUID_EXT2_PAT (1U << 16) 668fcf5ef2aSThomas Huth #define CPUID_EXT2_PSE36 (1U << 17) 669fcf5ef2aSThomas Huth #define CPUID_EXT2_MP (1U << 19) 670fcf5ef2aSThomas Huth #define CPUID_EXT2_NX (1U << 20) 671fcf5ef2aSThomas Huth #define CPUID_EXT2_MMXEXT (1U << 22) 672fcf5ef2aSThomas Huth #define CPUID_EXT2_MMX (1U << 23) 673fcf5ef2aSThomas Huth #define CPUID_EXT2_FXSR (1U << 24) 674fcf5ef2aSThomas Huth #define CPUID_EXT2_FFXSR (1U << 25) 675fcf5ef2aSThomas Huth #define CPUID_EXT2_PDPE1GB (1U << 26) 676fcf5ef2aSThomas Huth #define CPUID_EXT2_RDTSCP (1U << 27) 677fcf5ef2aSThomas Huth #define CPUID_EXT2_LM (1U << 29) 678fcf5ef2aSThomas Huth #define CPUID_EXT2_3DNOWEXT (1U << 30) 679fcf5ef2aSThomas Huth #define CPUID_EXT2_3DNOW (1U << 31) 680fcf5ef2aSThomas Huth 681fcf5ef2aSThomas Huth /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 682fcf5ef2aSThomas Huth #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 683fcf5ef2aSThomas Huth CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 684fcf5ef2aSThomas Huth CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 685fcf5ef2aSThomas Huth CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 686fcf5ef2aSThomas Huth CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 687fcf5ef2aSThomas Huth CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 688fcf5ef2aSThomas Huth CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 689fcf5ef2aSThomas Huth CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 690fcf5ef2aSThomas Huth CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 691fcf5ef2aSThomas Huth 692fcf5ef2aSThomas Huth #define CPUID_EXT3_LAHF_LM (1U << 0) 693fcf5ef2aSThomas Huth #define CPUID_EXT3_CMP_LEG (1U << 1) 694fcf5ef2aSThomas Huth #define CPUID_EXT3_SVM (1U << 2) 695fcf5ef2aSThomas Huth #define CPUID_EXT3_EXTAPIC (1U << 3) 696fcf5ef2aSThomas Huth #define CPUID_EXT3_CR8LEG (1U << 4) 697fcf5ef2aSThomas Huth #define CPUID_EXT3_ABM (1U << 5) 698fcf5ef2aSThomas Huth #define CPUID_EXT3_SSE4A (1U << 6) 699fcf5ef2aSThomas Huth #define CPUID_EXT3_MISALIGNSSE (1U << 7) 700fcf5ef2aSThomas Huth #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 701fcf5ef2aSThomas Huth #define CPUID_EXT3_OSVW (1U << 9) 702fcf5ef2aSThomas Huth #define CPUID_EXT3_IBS (1U << 10) 703fcf5ef2aSThomas Huth #define CPUID_EXT3_XOP (1U << 11) 704fcf5ef2aSThomas Huth #define CPUID_EXT3_SKINIT (1U << 12) 705fcf5ef2aSThomas Huth #define CPUID_EXT3_WDT (1U << 13) 706fcf5ef2aSThomas Huth #define CPUID_EXT3_LWP (1U << 15) 707fcf5ef2aSThomas Huth #define CPUID_EXT3_FMA4 (1U << 16) 708fcf5ef2aSThomas Huth #define CPUID_EXT3_TCE (1U << 17) 709fcf5ef2aSThomas Huth #define CPUID_EXT3_NODEID (1U << 19) 710fcf5ef2aSThomas Huth #define CPUID_EXT3_TBM (1U << 21) 711fcf5ef2aSThomas Huth #define CPUID_EXT3_TOPOEXT (1U << 22) 712fcf5ef2aSThomas Huth #define CPUID_EXT3_PERFCORE (1U << 23) 713fcf5ef2aSThomas Huth #define CPUID_EXT3_PERFNB (1U << 24) 714fcf5ef2aSThomas Huth 715fcf5ef2aSThomas Huth #define CPUID_SVM_NPT (1U << 0) 716fcf5ef2aSThomas Huth #define CPUID_SVM_LBRV (1U << 1) 717fcf5ef2aSThomas Huth #define CPUID_SVM_SVMLOCK (1U << 2) 718fcf5ef2aSThomas Huth #define CPUID_SVM_NRIPSAVE (1U << 3) 719fcf5ef2aSThomas Huth #define CPUID_SVM_TSCSCALE (1U << 4) 720fcf5ef2aSThomas Huth #define CPUID_SVM_VMCBCLEAN (1U << 5) 721fcf5ef2aSThomas Huth #define CPUID_SVM_FLUSHASID (1U << 6) 722fcf5ef2aSThomas Huth #define CPUID_SVM_DECODEASSIST (1U << 7) 723fcf5ef2aSThomas Huth #define CPUID_SVM_PAUSEFILTER (1U << 10) 724fcf5ef2aSThomas Huth #define CPUID_SVM_PFTHRESHOLD (1U << 12) 7255447089cSWei Huang #define CPUID_SVM_AVIC (1U << 13) 7265447089cSWei Huang #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) 7275447089cSWei Huang #define CPUID_SVM_VGIF (1U << 16) 7285447089cSWei Huang #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) 729fcf5ef2aSThomas Huth 730f2be0bebSTao Xu /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 731fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 7325c76b651SSean Christopherson /* Support SGX */ 7335c76b651SSean Christopherson #define CPUID_7_0_EBX_SGX (1U << 2) 734f2be0bebSTao Xu /* 1st Group of Advanced Bit Manipulation Extensions */ 735fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_BMI1 (1U << 3) 736f2be0bebSTao Xu /* Hardware Lock Elision */ 737fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_HLE (1U << 4) 738f2be0bebSTao Xu /* Intel Advanced Vector Extensions 2 */ 739fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX2 (1U << 5) 740f2be0bebSTao Xu /* Supervisor-mode Execution Prevention */ 741fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_SMEP (1U << 7) 742f2be0bebSTao Xu /* 2nd Group of Advanced Bit Manipulation Extensions */ 743fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_BMI2 (1U << 8) 744f2be0bebSTao Xu /* Enhanced REP MOVSB/STOSB */ 745fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_ERMS (1U << 9) 746f2be0bebSTao Xu /* Invalidate Process-Context Identifier */ 747fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_INVPCID (1U << 10) 748f2be0bebSTao Xu /* Restricted Transactional Memory */ 749fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_RTM (1U << 11) 750f2be0bebSTao Xu /* Memory Protection Extension */ 751fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_MPX (1U << 14) 752f2be0bebSTao Xu /* AVX-512 Foundation */ 753f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512F (1U << 16) 754f2be0bebSTao Xu /* AVX-512 Doubleword & Quadword Instruction */ 755f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 756f2be0bebSTao Xu /* Read Random SEED */ 757fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_RDSEED (1U << 18) 758f2be0bebSTao Xu /* ADCX and ADOX instructions */ 759fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_ADX (1U << 19) 760f2be0bebSTao Xu /* Supervisor Mode Access Prevention */ 761fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_SMAP (1U << 20) 762f2be0bebSTao Xu /* AVX-512 Integer Fused Multiply Add */ 763f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 764f2be0bebSTao Xu /* Persistent Commit */ 765f2be0bebSTao Xu #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 766f2be0bebSTao Xu /* Flush a Cache Line Optimized */ 767f2be0bebSTao Xu #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 768f2be0bebSTao Xu /* Cache Line Write Back */ 769f2be0bebSTao Xu #define CPUID_7_0_EBX_CLWB (1U << 24) 770f2be0bebSTao Xu /* Intel Processor Trace */ 771f2be0bebSTao Xu #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 772f2be0bebSTao Xu /* AVX-512 Prefetch */ 773f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512PF (1U << 26) 774f2be0bebSTao Xu /* AVX-512 Exponential and Reciprocal */ 775f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512ER (1U << 27) 776f2be0bebSTao Xu /* AVX-512 Conflict Detection */ 777f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512CD (1U << 28) 778f2be0bebSTao Xu /* SHA1/SHA256 Instruction Extensions */ 779f2be0bebSTao Xu #define CPUID_7_0_EBX_SHA_NI (1U << 29) 780f2be0bebSTao Xu /* AVX-512 Byte and Word Instructions */ 781f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512BW (1U << 30) 782f2be0bebSTao Xu /* AVX-512 Vector Length Extensions */ 783f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512VL (1U << 31) 784fcf5ef2aSThomas Huth 785f2be0bebSTao Xu /* AVX-512 Vector Byte Manipulation Instruction */ 786e7694a5eSTao Xu #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 787f2be0bebSTao Xu /* User-Mode Instruction Prevention */ 788fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_UMIP (1U << 2) 789f2be0bebSTao Xu /* Protection Keys for User-mode Pages */ 790fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_PKU (1U << 3) 791f2be0bebSTao Xu /* OS Enable Protection Keys */ 792fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_OSPKE (1U << 4) 79367192a29STao Xu /* UMONITOR/UMWAIT/TPAUSE Instructions */ 79467192a29STao Xu #define CPUID_7_0_ECX_WAITPKG (1U << 5) 795f2be0bebSTao Xu /* Additional AVX-512 Vector Byte Manipulation Instruction */ 796e7694a5eSTao Xu #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 797f2be0bebSTao Xu /* Galois Field New Instructions */ 798aff9e6e4SYang Zhong #define CPUID_7_0_ECX_GFNI (1U << 8) 799f2be0bebSTao Xu /* Vector AES Instructions */ 800aff9e6e4SYang Zhong #define CPUID_7_0_ECX_VAES (1U << 9) 801f2be0bebSTao Xu /* Carry-Less Multiplication Quadword */ 802aff9e6e4SYang Zhong #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 803f2be0bebSTao Xu /* Vector Neural Network Instructions */ 804aff9e6e4SYang Zhong #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 805f2be0bebSTao Xu /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 806aff9e6e4SYang Zhong #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 807f2be0bebSTao Xu /* POPCNT for vectors of DW/QW */ 808f2be0bebSTao Xu #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 809f2be0bebSTao Xu /* 5-level Page Tables */ 8106c7c3c21SKirill A. Shutemov #define CPUID_7_0_ECX_LA57 (1U << 16) 811f2be0bebSTao Xu /* Read Processor ID */ 812fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_RDPID (1U << 22) 81306e878b4SChenyi Qiang /* Bus Lock Debug Exception */ 81406e878b4SChenyi Qiang #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) 815f2be0bebSTao Xu /* Cache Line Demote Instruction */ 816f2be0bebSTao Xu #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 817f2be0bebSTao Xu /* Move Doubleword as Direct Store Instruction */ 818f2be0bebSTao Xu #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 819f2be0bebSTao Xu /* Move 64 Bytes as Direct Store Instruction */ 820f2be0bebSTao Xu #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 8215c76b651SSean Christopherson /* Support SGX Launch Control */ 8225c76b651SSean Christopherson #define CPUID_7_0_ECX_SGX_LC (1U << 30) 823e7e7bdabSPaolo Bonzini /* Protection Keys for Supervisor-mode Pages */ 824e7e7bdabSPaolo Bonzini #define CPUID_7_0_ECX_PKS (1U << 31) 825fcf5ef2aSThomas Huth 826f2be0bebSTao Xu /* AVX512 Neural Network Instructions */ 827f2be0bebSTao Xu #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 828f2be0bebSTao Xu /* AVX512 Multiply Accumulation Single Precision */ 829f2be0bebSTao Xu #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 8305cb287d2SChenyi Qiang /* Fast Short Rep Mov */ 8315cb287d2SChenyi Qiang #define CPUID_7_0_EDX_FSRM (1U << 4) 832353f98c9SCathy Zhang /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 833353f98c9SCathy Zhang #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 8345dd13f2aSCathy Zhang /* SERIALIZE instruction */ 8355dd13f2aSCathy Zhang #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 836b3c7344eSCathy Zhang /* TSX Suspend Load Address Tracking instruction */ 837b3c7344eSCathy Zhang #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 83840399ecbSCathy Zhang /* AVX512_FP16 instruction */ 83940399ecbSCathy Zhang #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) 840f2be0bebSTao Xu /* Speculation Control */ 841f2be0bebSTao Xu #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 8425af514d0SCathy Zhang /* Single Thread Indirect Branch Predictors */ 8435af514d0SCathy Zhang #define CPUID_7_0_EDX_STIBP (1U << 27) 844f2be0bebSTao Xu /* Arch Capabilities */ 845f2be0bebSTao Xu #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 846f2be0bebSTao Xu /* Core Capability */ 847f2be0bebSTao Xu #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 848f2be0bebSTao Xu /* Speculative Store Bypass Disable */ 849f2be0bebSTao Xu #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 850fcf5ef2aSThomas Huth 851c1826ea6SYang Zhong /* AVX VNNI Instruction */ 852c1826ea6SYang Zhong #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) 853f2be0bebSTao Xu /* AVX512 BFloat16 Instruction */ 854f2be0bebSTao Xu #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 85580db491dSJing Liu 856d1615ea5SLuwei Kang /* Packets which contain IP payload have LIP values */ 857d1615ea5SLuwei Kang #define CPUID_14_0_ECX_LIP (1U << 31) 858d1615ea5SLuwei Kang 859f2be0bebSTao Xu /* CLZERO instruction */ 860f2be0bebSTao Xu #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 861f2be0bebSTao Xu /* Always save/restore FP error pointers */ 862f2be0bebSTao Xu #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 863f2be0bebSTao Xu /* Write back and do not invalidate cache */ 864f2be0bebSTao Xu #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 865f2be0bebSTao Xu /* Indirect Branch Prediction Barrier */ 866f2be0bebSTao Xu #define CPUID_8000_0008_EBX_IBPB (1U << 12) 867623972ceSBabu Moger /* Indirect Branch Restricted Speculation */ 868623972ceSBabu Moger #define CPUID_8000_0008_EBX_IBRS (1U << 14) 869143c30d4SMoger, Babu /* Single Thread Indirect Branch Predictors */ 870143c30d4SMoger, Babu #define CPUID_8000_0008_EBX_STIBP (1U << 15) 871623972ceSBabu Moger /* Speculative Store Bypass Disable */ 872623972ceSBabu Moger #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) 8731b3420e1SEduardo Habkost 874fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVEOPT (1U << 0) 875fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVEC (1U << 1) 876fcf5ef2aSThomas Huth #define CPUID_XSAVE_XGETBV1 (1U << 2) 877fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVES (1U << 3) 878fcf5ef2aSThomas Huth 879fcf5ef2aSThomas Huth #define CPUID_6_EAX_ARAT (1U << 2) 880fcf5ef2aSThomas Huth 881fcf5ef2aSThomas Huth /* CPUID[0x80000007].EDX flags: */ 882fcf5ef2aSThomas Huth #define CPUID_APM_INVTSC (1U << 8) 883fcf5ef2aSThomas Huth 884fcf5ef2aSThomas Huth #define CPUID_VENDOR_SZ 12 885fcf5ef2aSThomas Huth 886fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 887fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 888fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 889fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL "GenuineIntel" 890fcf5ef2aSThomas Huth 891fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 892fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 893fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 894fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD "AuthenticAMD" 895fcf5ef2aSThomas Huth 896fcf5ef2aSThomas Huth #define CPUID_VENDOR_VIA "CentaurHauls" 897fcf5ef2aSThomas Huth 8988d031cecSPu Wen #define CPUID_VENDOR_HYGON "HygonGenuine" 8998d031cecSPu Wen 90018ab37baSLiran Alon #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 90118ab37baSLiran Alon (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 90218ab37baSLiran Alon (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 90318ab37baSLiran Alon #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 90418ab37baSLiran Alon (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 90518ab37baSLiran Alon (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 90618ab37baSLiran Alon 907fcf5ef2aSThomas Huth #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 908fcf5ef2aSThomas Huth #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 909fcf5ef2aSThomas Huth 910fcf5ef2aSThomas Huth /* CPUID[0xB].ECX level types */ 911fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 912fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 913fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 914a94e1428SLike Xu #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 915fcf5ef2aSThomas Huth 916d86f9636SRobert Hoo /* MSR Feature Bits */ 917d86f9636SRobert Hoo #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 918d86f9636SRobert Hoo #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 919d86f9636SRobert Hoo #define MSR_ARCH_CAP_RSBA (1U << 2) 920d86f9636SRobert Hoo #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 921d86f9636SRobert Hoo #define MSR_ARCH_CAP_SSB_NO (1U << 4) 92277b168d2SCathy Zhang #define MSR_ARCH_CAP_MDS_NO (1U << 5) 9236c997b4aSXiaoyao Li #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 9246c997b4aSXiaoyao Li #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 9256c997b4aSXiaoyao Li #define MSR_ARCH_CAP_TAA_NO (1U << 8) 926d86f9636SRobert Hoo 927597360c0SXiaoyao Li #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 928597360c0SXiaoyao Li 929704798adSPaolo Bonzini /* VMX MSR features */ 930704798adSPaolo Bonzini #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 931704798adSPaolo Bonzini #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 932704798adSPaolo Bonzini #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 933704798adSPaolo Bonzini #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 934704798adSPaolo Bonzini #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 935704798adSPaolo Bonzini #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 936704798adSPaolo Bonzini 937704798adSPaolo Bonzini #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 938704798adSPaolo Bonzini #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 939704798adSPaolo Bonzini #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 940704798adSPaolo Bonzini #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 941704798adSPaolo Bonzini #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 942704798adSPaolo Bonzini #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 943704798adSPaolo Bonzini #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 944704798adSPaolo Bonzini #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 945704798adSPaolo Bonzini 946704798adSPaolo Bonzini #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 947704798adSPaolo Bonzini #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 948704798adSPaolo Bonzini #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 949704798adSPaolo Bonzini #define MSR_VMX_EPT_UC (1ULL << 8) 950704798adSPaolo Bonzini #define MSR_VMX_EPT_WB (1ULL << 14) 951704798adSPaolo Bonzini #define MSR_VMX_EPT_2MB (1ULL << 16) 952704798adSPaolo Bonzini #define MSR_VMX_EPT_1GB (1ULL << 17) 953704798adSPaolo Bonzini #define MSR_VMX_EPT_INVEPT (1ULL << 20) 954704798adSPaolo Bonzini #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 955704798adSPaolo Bonzini #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 956704798adSPaolo Bonzini #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 957704798adSPaolo Bonzini #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 958704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID (1ULL << 32) 959704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 960704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 961704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 962704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 963704798adSPaolo Bonzini 964704798adSPaolo Bonzini #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 965704798adSPaolo Bonzini 966704798adSPaolo Bonzini 967704798adSPaolo Bonzini /* VMX controls */ 968704798adSPaolo Bonzini #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 969704798adSPaolo Bonzini #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 970704798adSPaolo Bonzini #define VMX_CPU_BASED_HLT_EXITING 0x00000080 971704798adSPaolo Bonzini #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 972704798adSPaolo Bonzini #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 973704798adSPaolo Bonzini #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 974704798adSPaolo Bonzini #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 975704798adSPaolo Bonzini #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 976704798adSPaolo Bonzini #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 977704798adSPaolo Bonzini #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 978704798adSPaolo Bonzini #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 979704798adSPaolo Bonzini #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 980704798adSPaolo Bonzini #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 981704798adSPaolo Bonzini #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 982704798adSPaolo Bonzini #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 983704798adSPaolo Bonzini #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 984704798adSPaolo Bonzini #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 985704798adSPaolo Bonzini #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 986704798adSPaolo Bonzini #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 987704798adSPaolo Bonzini #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 988704798adSPaolo Bonzini #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 989704798adSPaolo Bonzini 990704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 991704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 992704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_DESC 0x00000004 993704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 994704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 995704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 996704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 997704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 998704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 999704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 1000704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 1001704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 1002704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 1003704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 1004704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 1005704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 1006704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 1007704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 1008704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 10099ce8af4dSPaolo Bonzini #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000 1010704798adSPaolo Bonzini 1011704798adSPaolo Bonzini #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 1012704798adSPaolo Bonzini #define VMX_PIN_BASED_NMI_EXITING 0x00000008 1013704798adSPaolo Bonzini #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 1014704798adSPaolo Bonzini #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 1015704798adSPaolo Bonzini #define VMX_PIN_BASED_POSTED_INTR 0x00000080 1016704798adSPaolo Bonzini 1017704798adSPaolo Bonzini #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 1018704798adSPaolo Bonzini #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 1019704798adSPaolo Bonzini #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 1020704798adSPaolo Bonzini #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 1021704798adSPaolo Bonzini #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 1022704798adSPaolo Bonzini #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 1023704798adSPaolo Bonzini #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 1024704798adSPaolo Bonzini #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 1025704798adSPaolo Bonzini #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 1026704798adSPaolo Bonzini #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 1027704798adSPaolo Bonzini #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 1028704798adSPaolo Bonzini #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 102952a44ad2SChenyi Qiang #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 1030704798adSPaolo Bonzini 1031704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 1032704798adSPaolo Bonzini #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 1033704798adSPaolo Bonzini #define VMX_VM_ENTRY_SMM 0x00000400 1034704798adSPaolo Bonzini #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 1035704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 1036704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 1037704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 1038704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 1039704798adSPaolo Bonzini #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 1040704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 104152a44ad2SChenyi Qiang #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 1042704798adSPaolo Bonzini 10432d384d7cSVitaly Kuznetsov /* Supported Hyper-V Enlightenments */ 10442d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_RELAXED 0 10452d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_VAPIC 1 10462d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_TIME 2 10472d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_CRASH 3 10482d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_RESET 4 10492d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_VPINDEX 5 10502d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_RUNTIME 6 10512d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_SYNIC 7 10522d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_STIMER 8 10532d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_FREQUENCIES 9 10542d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_REENLIGHTENMENT 10 10552d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_TLBFLUSH 11 10562d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_EVMCS 12 10572d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_IPI 13 1058128531d9SVitaly Kuznetsov #define HYPERV_FEAT_STIMER_DIRECT 14 1059*e1f9a8e8SVitaly Kuznetsov #define HYPERV_FEAT_AVIC 15 10602d384d7cSVitaly Kuznetsov 1061f701c082SVitaly Kuznetsov #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY 1062f701c082SVitaly Kuznetsov #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF 1063fcf5ef2aSThomas Huth #endif 1064fcf5ef2aSThomas Huth 1065fcf5ef2aSThomas Huth #define EXCP00_DIVZ 0 1066fcf5ef2aSThomas Huth #define EXCP01_DB 1 1067fcf5ef2aSThomas Huth #define EXCP02_NMI 2 1068fcf5ef2aSThomas Huth #define EXCP03_INT3 3 1069fcf5ef2aSThomas Huth #define EXCP04_INTO 4 1070fcf5ef2aSThomas Huth #define EXCP05_BOUND 5 1071fcf5ef2aSThomas Huth #define EXCP06_ILLOP 6 1072fcf5ef2aSThomas Huth #define EXCP07_PREX 7 1073fcf5ef2aSThomas Huth #define EXCP08_DBLE 8 1074fcf5ef2aSThomas Huth #define EXCP09_XERR 9 1075fcf5ef2aSThomas Huth #define EXCP0A_TSS 10 1076fcf5ef2aSThomas Huth #define EXCP0B_NOSEG 11 1077fcf5ef2aSThomas Huth #define EXCP0C_STACK 12 1078fcf5ef2aSThomas Huth #define EXCP0D_GPF 13 1079fcf5ef2aSThomas Huth #define EXCP0E_PAGE 14 1080fcf5ef2aSThomas Huth #define EXCP10_COPR 16 1081fcf5ef2aSThomas Huth #define EXCP11_ALGN 17 1082fcf5ef2aSThomas Huth #define EXCP12_MCHK 18 1083fcf5ef2aSThomas Huth 108462846089SRichard Henderson #define EXCP_VMEXIT 0x100 /* only for system emulation */ 108562846089SRichard Henderson #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1086b26491b4SRichard Henderson #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1087fcf5ef2aSThomas Huth 1088fcf5ef2aSThomas Huth /* i386-specific interrupt pending bits. */ 1089fcf5ef2aSThomas Huth #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1090fcf5ef2aSThomas Huth #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1091fcf5ef2aSThomas Huth #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1092fcf5ef2aSThomas Huth #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1093fcf5ef2aSThomas Huth #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1094fcf5ef2aSThomas Huth #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1095fcf5ef2aSThomas Huth #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1096fcf5ef2aSThomas Huth 1097fcf5ef2aSThomas Huth /* Use a clearer name for this. */ 1098fcf5ef2aSThomas Huth #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1099fcf5ef2aSThomas Huth 1100fcf5ef2aSThomas Huth /* Instead of computing the condition codes after each x86 instruction, 1101fcf5ef2aSThomas Huth * QEMU just stores one operand (called CC_SRC), the result 1102fcf5ef2aSThomas Huth * (called CC_DST) and the type of operation (called CC_OP). When the 1103fcf5ef2aSThomas Huth * condition codes are needed, the condition codes can be calculated 1104fcf5ef2aSThomas Huth * using this information. Condition codes are not generated if they 1105fcf5ef2aSThomas Huth * are only needed for conditional branches. 1106fcf5ef2aSThomas Huth */ 1107fcf5ef2aSThomas Huth typedef enum { 1108fcf5ef2aSThomas Huth CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1109fcf5ef2aSThomas Huth CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1110fcf5ef2aSThomas Huth 1111fcf5ef2aSThomas Huth CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1112fcf5ef2aSThomas Huth CC_OP_MULW, 1113fcf5ef2aSThomas Huth CC_OP_MULL, 1114fcf5ef2aSThomas Huth CC_OP_MULQ, 1115fcf5ef2aSThomas Huth 1116fcf5ef2aSThomas Huth CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1117fcf5ef2aSThomas Huth CC_OP_ADDW, 1118fcf5ef2aSThomas Huth CC_OP_ADDL, 1119fcf5ef2aSThomas Huth CC_OP_ADDQ, 1120fcf5ef2aSThomas Huth 1121fcf5ef2aSThomas Huth CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1122fcf5ef2aSThomas Huth CC_OP_ADCW, 1123fcf5ef2aSThomas Huth CC_OP_ADCL, 1124fcf5ef2aSThomas Huth CC_OP_ADCQ, 1125fcf5ef2aSThomas Huth 1126fcf5ef2aSThomas Huth CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1127fcf5ef2aSThomas Huth CC_OP_SUBW, 1128fcf5ef2aSThomas Huth CC_OP_SUBL, 1129fcf5ef2aSThomas Huth CC_OP_SUBQ, 1130fcf5ef2aSThomas Huth 1131fcf5ef2aSThomas Huth CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1132fcf5ef2aSThomas Huth CC_OP_SBBW, 1133fcf5ef2aSThomas Huth CC_OP_SBBL, 1134fcf5ef2aSThomas Huth CC_OP_SBBQ, 1135fcf5ef2aSThomas Huth 1136fcf5ef2aSThomas Huth CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1137fcf5ef2aSThomas Huth CC_OP_LOGICW, 1138fcf5ef2aSThomas Huth CC_OP_LOGICL, 1139fcf5ef2aSThomas Huth CC_OP_LOGICQ, 1140fcf5ef2aSThomas Huth 1141fcf5ef2aSThomas Huth CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1142fcf5ef2aSThomas Huth CC_OP_INCW, 1143fcf5ef2aSThomas Huth CC_OP_INCL, 1144fcf5ef2aSThomas Huth CC_OP_INCQ, 1145fcf5ef2aSThomas Huth 1146fcf5ef2aSThomas Huth CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1147fcf5ef2aSThomas Huth CC_OP_DECW, 1148fcf5ef2aSThomas Huth CC_OP_DECL, 1149fcf5ef2aSThomas Huth CC_OP_DECQ, 1150fcf5ef2aSThomas Huth 1151fcf5ef2aSThomas Huth CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1152fcf5ef2aSThomas Huth CC_OP_SHLW, 1153fcf5ef2aSThomas Huth CC_OP_SHLL, 1154fcf5ef2aSThomas Huth CC_OP_SHLQ, 1155fcf5ef2aSThomas Huth 1156fcf5ef2aSThomas Huth CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1157fcf5ef2aSThomas Huth CC_OP_SARW, 1158fcf5ef2aSThomas Huth CC_OP_SARL, 1159fcf5ef2aSThomas Huth CC_OP_SARQ, 1160fcf5ef2aSThomas Huth 1161fcf5ef2aSThomas Huth CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1162fcf5ef2aSThomas Huth CC_OP_BMILGW, 1163fcf5ef2aSThomas Huth CC_OP_BMILGL, 1164fcf5ef2aSThomas Huth CC_OP_BMILGQ, 1165fcf5ef2aSThomas Huth 1166fcf5ef2aSThomas Huth CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1167fcf5ef2aSThomas Huth CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1168fcf5ef2aSThomas Huth CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1169fcf5ef2aSThomas Huth 1170fcf5ef2aSThomas Huth CC_OP_CLR, /* Z set, all other flags clear. */ 11714885c3c4SRichard Henderson CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1172fcf5ef2aSThomas Huth 1173fcf5ef2aSThomas Huth CC_OP_NB, 1174fcf5ef2aSThomas Huth } CCOp; 1175fcf5ef2aSThomas Huth 1176fcf5ef2aSThomas Huth typedef struct SegmentCache { 1177fcf5ef2aSThomas Huth uint32_t selector; 1178fcf5ef2aSThomas Huth target_ulong base; 1179fcf5ef2aSThomas Huth uint32_t limit; 1180fcf5ef2aSThomas Huth uint32_t flags; 1181fcf5ef2aSThomas Huth } SegmentCache; 1182fcf5ef2aSThomas Huth 1183fcf5ef2aSThomas Huth #define MMREG_UNION(n, bits) \ 1184fcf5ef2aSThomas Huth union n { \ 1185fcf5ef2aSThomas Huth uint8_t _b_##n[(bits)/8]; \ 1186fcf5ef2aSThomas Huth uint16_t _w_##n[(bits)/16]; \ 1187fcf5ef2aSThomas Huth uint32_t _l_##n[(bits)/32]; \ 1188fcf5ef2aSThomas Huth uint64_t _q_##n[(bits)/64]; \ 1189fcf5ef2aSThomas Huth float32 _s_##n[(bits)/32]; \ 1190fcf5ef2aSThomas Huth float64 _d_##n[(bits)/64]; \ 1191fcf5ef2aSThomas Huth } 1192fcf5ef2aSThomas Huth 1193c97d6d2cSSergio Andres Gomez Del Real typedef union { 1194c97d6d2cSSergio Andres Gomez Del Real uint8_t _b[16]; 1195c97d6d2cSSergio Andres Gomez Del Real uint16_t _w[8]; 1196c97d6d2cSSergio Andres Gomez Del Real uint32_t _l[4]; 1197c97d6d2cSSergio Andres Gomez Del Real uint64_t _q[2]; 1198c97d6d2cSSergio Andres Gomez Del Real } XMMReg; 1199c97d6d2cSSergio Andres Gomez Del Real 1200c97d6d2cSSergio Andres Gomez Del Real typedef union { 1201c97d6d2cSSergio Andres Gomez Del Real uint8_t _b[32]; 1202c97d6d2cSSergio Andres Gomez Del Real uint16_t _w[16]; 1203c97d6d2cSSergio Andres Gomez Del Real uint32_t _l[8]; 1204c97d6d2cSSergio Andres Gomez Del Real uint64_t _q[4]; 1205c97d6d2cSSergio Andres Gomez Del Real } YMMReg; 1206c97d6d2cSSergio Andres Gomez Del Real 1207fcf5ef2aSThomas Huth typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 1208fcf5ef2aSThomas Huth typedef MMREG_UNION(MMXReg, 64) MMXReg; 1209fcf5ef2aSThomas Huth 1210fcf5ef2aSThomas Huth typedef struct BNDReg { 1211fcf5ef2aSThomas Huth uint64_t lb; 1212fcf5ef2aSThomas Huth uint64_t ub; 1213fcf5ef2aSThomas Huth } BNDReg; 1214fcf5ef2aSThomas Huth 1215fcf5ef2aSThomas Huth typedef struct BNDCSReg { 1216fcf5ef2aSThomas Huth uint64_t cfgu; 1217fcf5ef2aSThomas Huth uint64_t sts; 1218fcf5ef2aSThomas Huth } BNDCSReg; 1219fcf5ef2aSThomas Huth 1220fcf5ef2aSThomas Huth #define BNDCFG_ENABLE 1ULL 1221fcf5ef2aSThomas Huth #define BNDCFG_BNDPRESERVE 2ULL 1222fcf5ef2aSThomas Huth #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1223fcf5ef2aSThomas Huth 1224fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 1225fcf5ef2aSThomas Huth #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1226fcf5ef2aSThomas Huth #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1227fcf5ef2aSThomas Huth #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1228fcf5ef2aSThomas Huth #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1229fcf5ef2aSThomas Huth #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1230fcf5ef2aSThomas Huth #define ZMM_D(n) _d_ZMMReg[7 - (n)] 1231fcf5ef2aSThomas Huth 1232fcf5ef2aSThomas Huth #define MMX_B(n) _b_MMXReg[7 - (n)] 1233fcf5ef2aSThomas Huth #define MMX_W(n) _w_MMXReg[3 - (n)] 1234fcf5ef2aSThomas Huth #define MMX_L(n) _l_MMXReg[1 - (n)] 1235fcf5ef2aSThomas Huth #define MMX_S(n) _s_MMXReg[1 - (n)] 1236fcf5ef2aSThomas Huth #else 1237fcf5ef2aSThomas Huth #define ZMM_B(n) _b_ZMMReg[n] 1238fcf5ef2aSThomas Huth #define ZMM_W(n) _w_ZMMReg[n] 1239fcf5ef2aSThomas Huth #define ZMM_L(n) _l_ZMMReg[n] 1240fcf5ef2aSThomas Huth #define ZMM_S(n) _s_ZMMReg[n] 1241fcf5ef2aSThomas Huth #define ZMM_Q(n) _q_ZMMReg[n] 1242fcf5ef2aSThomas Huth #define ZMM_D(n) _d_ZMMReg[n] 1243fcf5ef2aSThomas Huth 1244fcf5ef2aSThomas Huth #define MMX_B(n) _b_MMXReg[n] 1245fcf5ef2aSThomas Huth #define MMX_W(n) _w_MMXReg[n] 1246fcf5ef2aSThomas Huth #define MMX_L(n) _l_MMXReg[n] 1247fcf5ef2aSThomas Huth #define MMX_S(n) _s_MMXReg[n] 1248fcf5ef2aSThomas Huth #endif 1249fcf5ef2aSThomas Huth #define MMX_Q(n) _q_MMXReg[n] 1250fcf5ef2aSThomas Huth 1251fcf5ef2aSThomas Huth typedef union { 1252fcf5ef2aSThomas Huth floatx80 d __attribute__((aligned(16))); 1253fcf5ef2aSThomas Huth MMXReg mmx; 1254fcf5ef2aSThomas Huth } FPReg; 1255fcf5ef2aSThomas Huth 1256fcf5ef2aSThomas Huth typedef struct { 1257fcf5ef2aSThomas Huth uint64_t base; 1258fcf5ef2aSThomas Huth uint64_t mask; 1259fcf5ef2aSThomas Huth } MTRRVar; 1260fcf5ef2aSThomas Huth 1261fcf5ef2aSThomas Huth #define CPU_NB_REGS64 16 1262fcf5ef2aSThomas Huth #define CPU_NB_REGS32 8 1263fcf5ef2aSThomas Huth 1264fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 1265fcf5ef2aSThomas Huth #define CPU_NB_REGS CPU_NB_REGS64 1266fcf5ef2aSThomas Huth #else 1267fcf5ef2aSThomas Huth #define CPU_NB_REGS CPU_NB_REGS32 1268fcf5ef2aSThomas Huth #endif 1269fcf5ef2aSThomas Huth 1270fcf5ef2aSThomas Huth #define MAX_FIXED_COUNTERS 3 1271fcf5ef2aSThomas Huth #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1272fcf5ef2aSThomas Huth 1273fcf5ef2aSThomas Huth #define TARGET_INSN_START_EXTRA_WORDS 1 1274fcf5ef2aSThomas Huth 1275fcf5ef2aSThomas Huth #define NB_OPMASK_REGS 8 1276fcf5ef2aSThomas Huth 1277fcf5ef2aSThomas Huth /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1278fcf5ef2aSThomas Huth * that APIC ID hasn't been set yet 1279fcf5ef2aSThomas Huth */ 1280fcf5ef2aSThomas Huth #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1281fcf5ef2aSThomas Huth 1282fcf5ef2aSThomas Huth typedef union X86LegacyXSaveArea { 1283fcf5ef2aSThomas Huth struct { 1284fcf5ef2aSThomas Huth uint16_t fcw; 1285fcf5ef2aSThomas Huth uint16_t fsw; 1286fcf5ef2aSThomas Huth uint8_t ftw; 1287fcf5ef2aSThomas Huth uint8_t reserved; 1288fcf5ef2aSThomas Huth uint16_t fpop; 1289fcf5ef2aSThomas Huth uint64_t fpip; 1290fcf5ef2aSThomas Huth uint64_t fpdp; 1291fcf5ef2aSThomas Huth uint32_t mxcsr; 1292fcf5ef2aSThomas Huth uint32_t mxcsr_mask; 1293fcf5ef2aSThomas Huth FPReg fpregs[8]; 1294fcf5ef2aSThomas Huth uint8_t xmm_regs[16][16]; 1295fcf5ef2aSThomas Huth }; 1296fcf5ef2aSThomas Huth uint8_t data[512]; 1297fcf5ef2aSThomas Huth } X86LegacyXSaveArea; 1298fcf5ef2aSThomas Huth 1299fcf5ef2aSThomas Huth typedef struct X86XSaveHeader { 1300fcf5ef2aSThomas Huth uint64_t xstate_bv; 1301fcf5ef2aSThomas Huth uint64_t xcomp_bv; 1302fcf5ef2aSThomas Huth uint64_t reserve0; 1303fcf5ef2aSThomas Huth uint8_t reserved[40]; 1304fcf5ef2aSThomas Huth } X86XSaveHeader; 1305fcf5ef2aSThomas Huth 1306fcf5ef2aSThomas Huth /* Ext. save area 2: AVX State */ 1307fcf5ef2aSThomas Huth typedef struct XSaveAVX { 1308fcf5ef2aSThomas Huth uint8_t ymmh[16][16]; 1309fcf5ef2aSThomas Huth } XSaveAVX; 1310fcf5ef2aSThomas Huth 1311fcf5ef2aSThomas Huth /* Ext. save area 3: BNDREG */ 1312fcf5ef2aSThomas Huth typedef struct XSaveBNDREG { 1313fcf5ef2aSThomas Huth BNDReg bnd_regs[4]; 1314fcf5ef2aSThomas Huth } XSaveBNDREG; 1315fcf5ef2aSThomas Huth 1316fcf5ef2aSThomas Huth /* Ext. save area 4: BNDCSR */ 1317fcf5ef2aSThomas Huth typedef union XSaveBNDCSR { 1318fcf5ef2aSThomas Huth BNDCSReg bndcsr; 1319fcf5ef2aSThomas Huth uint8_t data[64]; 1320fcf5ef2aSThomas Huth } XSaveBNDCSR; 1321fcf5ef2aSThomas Huth 1322fcf5ef2aSThomas Huth /* Ext. save area 5: Opmask */ 1323fcf5ef2aSThomas Huth typedef struct XSaveOpmask { 1324fcf5ef2aSThomas Huth uint64_t opmask_regs[NB_OPMASK_REGS]; 1325fcf5ef2aSThomas Huth } XSaveOpmask; 1326fcf5ef2aSThomas Huth 1327fcf5ef2aSThomas Huth /* Ext. save area 6: ZMM_Hi256 */ 1328fcf5ef2aSThomas Huth typedef struct XSaveZMM_Hi256 { 1329fcf5ef2aSThomas Huth uint8_t zmm_hi256[16][32]; 1330fcf5ef2aSThomas Huth } XSaveZMM_Hi256; 1331fcf5ef2aSThomas Huth 1332fcf5ef2aSThomas Huth /* Ext. save area 7: Hi16_ZMM */ 1333fcf5ef2aSThomas Huth typedef struct XSaveHi16_ZMM { 1334fcf5ef2aSThomas Huth uint8_t hi16_zmm[16][64]; 1335fcf5ef2aSThomas Huth } XSaveHi16_ZMM; 1336fcf5ef2aSThomas Huth 1337fcf5ef2aSThomas Huth /* Ext. save area 9: PKRU state */ 1338fcf5ef2aSThomas Huth typedef struct XSavePKRU { 1339fcf5ef2aSThomas Huth uint32_t pkru; 1340fcf5ef2aSThomas Huth uint32_t padding; 1341fcf5ef2aSThomas Huth } XSavePKRU; 1342fcf5ef2aSThomas Huth 1343fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1344fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1345fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1346fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1347fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1348fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1349fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 1350fcf5ef2aSThomas Huth 13515aa10ab1SDavid Edmondson typedef struct ExtSaveArea { 13525aa10ab1SDavid Edmondson uint32_t feature, bits; 13535aa10ab1SDavid Edmondson uint32_t offset, size; 13545aa10ab1SDavid Edmondson } ExtSaveArea; 13555aa10ab1SDavid Edmondson 13565aa10ab1SDavid Edmondson #define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) 13575aa10ab1SDavid Edmondson 1358fea45008SDavid Edmondson extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; 13595aa10ab1SDavid Edmondson 1360fcf5ef2aSThomas Huth typedef enum TPRAccess { 1361fcf5ef2aSThomas Huth TPR_ACCESS_READ, 1362fcf5ef2aSThomas Huth TPR_ACCESS_WRITE, 1363fcf5ef2aSThomas Huth } TPRAccess; 1364fcf5ef2aSThomas Huth 13657e3482f8SEduardo Habkost /* Cache information data structures: */ 13667e3482f8SEduardo Habkost 13677e3482f8SEduardo Habkost enum CacheType { 13685f00335aSEduardo Habkost DATA_CACHE, 13695f00335aSEduardo Habkost INSTRUCTION_CACHE, 13707e3482f8SEduardo Habkost UNIFIED_CACHE 13717e3482f8SEduardo Habkost }; 13727e3482f8SEduardo Habkost 13737e3482f8SEduardo Habkost typedef struct CPUCacheInfo { 13747e3482f8SEduardo Habkost enum CacheType type; 13757e3482f8SEduardo Habkost uint8_t level; 13767e3482f8SEduardo Habkost /* Size in bytes */ 13777e3482f8SEduardo Habkost uint32_t size; 13787e3482f8SEduardo Habkost /* Line size, in bytes */ 13797e3482f8SEduardo Habkost uint16_t line_size; 13807e3482f8SEduardo Habkost /* 13817e3482f8SEduardo Habkost * Associativity. 13827e3482f8SEduardo Habkost * Note: representation of fully-associative caches is not implemented 13837e3482f8SEduardo Habkost */ 13847e3482f8SEduardo Habkost uint8_t associativity; 13857e3482f8SEduardo Habkost /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 13867e3482f8SEduardo Habkost uint8_t partitions; 13877e3482f8SEduardo Habkost /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 13887e3482f8SEduardo Habkost uint32_t sets; 13897e3482f8SEduardo Habkost /* 13907e3482f8SEduardo Habkost * Lines per tag. 13917e3482f8SEduardo Habkost * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 13927e3482f8SEduardo Habkost * (Is this synonym to @partitions?) 13937e3482f8SEduardo Habkost */ 13947e3482f8SEduardo Habkost uint8_t lines_per_tag; 13957e3482f8SEduardo Habkost 13967e3482f8SEduardo Habkost /* Self-initializing cache */ 13977e3482f8SEduardo Habkost bool self_init; 13987e3482f8SEduardo Habkost /* 13997e3482f8SEduardo Habkost * WBINVD/INVD is not guaranteed to act upon lower level caches of 14007e3482f8SEduardo Habkost * non-originating threads sharing this cache. 14017e3482f8SEduardo Habkost * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 14027e3482f8SEduardo Habkost */ 14037e3482f8SEduardo Habkost bool no_invd_sharing; 14047e3482f8SEduardo Habkost /* 14057e3482f8SEduardo Habkost * Cache is inclusive of lower cache levels. 14067e3482f8SEduardo Habkost * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 14077e3482f8SEduardo Habkost */ 14087e3482f8SEduardo Habkost bool inclusive; 14097e3482f8SEduardo Habkost /* 14107e3482f8SEduardo Habkost * A complex function is used to index the cache, potentially using all 14117e3482f8SEduardo Habkost * address bits. CPUID[4].EDX[bit 2]. 14127e3482f8SEduardo Habkost */ 14137e3482f8SEduardo Habkost bool complex_indexing; 14147e3482f8SEduardo Habkost } CPUCacheInfo; 14157e3482f8SEduardo Habkost 14167e3482f8SEduardo Habkost 14176aaeb054SBabu Moger typedef struct CPUCaches { 1418a9f27ea9SEduardo Habkost CPUCacheInfo *l1d_cache; 1419a9f27ea9SEduardo Habkost CPUCacheInfo *l1i_cache; 1420a9f27ea9SEduardo Habkost CPUCacheInfo *l2_cache; 1421a9f27ea9SEduardo Habkost CPUCacheInfo *l3_cache; 14226aaeb054SBabu Moger } CPUCaches; 14237e3482f8SEduardo Habkost 1424577f02b8SRoman Bolshakov typedef struct HVFX86LazyFlags { 1425577f02b8SRoman Bolshakov target_ulong result; 1426577f02b8SRoman Bolshakov target_ulong auxbits; 1427577f02b8SRoman Bolshakov } HVFX86LazyFlags; 1428577f02b8SRoman Bolshakov 1429fcf5ef2aSThomas Huth typedef struct CPUX86State { 1430fcf5ef2aSThomas Huth /* standard registers */ 1431fcf5ef2aSThomas Huth target_ulong regs[CPU_NB_REGS]; 1432fcf5ef2aSThomas Huth target_ulong eip; 1433fcf5ef2aSThomas Huth target_ulong eflags; /* eflags register. During CPU emulation, CC 1434fcf5ef2aSThomas Huth flags and DF are set to zero because they are 1435fcf5ef2aSThomas Huth stored elsewhere */ 1436fcf5ef2aSThomas Huth 1437fcf5ef2aSThomas Huth /* emulator internal eflags handling */ 1438fcf5ef2aSThomas Huth target_ulong cc_dst; 1439fcf5ef2aSThomas Huth target_ulong cc_src; 1440fcf5ef2aSThomas Huth target_ulong cc_src2; 1441fcf5ef2aSThomas Huth uint32_t cc_op; 1442fcf5ef2aSThomas Huth int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1443fcf5ef2aSThomas Huth uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1444fcf5ef2aSThomas Huth are known at translation time. */ 1445fcf5ef2aSThomas Huth uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1446fcf5ef2aSThomas Huth 1447fcf5ef2aSThomas Huth /* segments */ 1448fcf5ef2aSThomas Huth SegmentCache segs[6]; /* selector values */ 1449fcf5ef2aSThomas Huth SegmentCache ldt; 1450fcf5ef2aSThomas Huth SegmentCache tr; 1451fcf5ef2aSThomas Huth SegmentCache gdt; /* only base and limit are used */ 1452fcf5ef2aSThomas Huth SegmentCache idt; /* only base and limit are used */ 1453fcf5ef2aSThomas Huth 1454fcf5ef2aSThomas Huth target_ulong cr[5]; /* NOTE: cr1 is unused */ 1455fcf5ef2aSThomas Huth int32_t a20_mask; 1456fcf5ef2aSThomas Huth 1457fcf5ef2aSThomas Huth BNDReg bnd_regs[4]; 1458fcf5ef2aSThomas Huth BNDCSReg bndcs_regs; 1459fcf5ef2aSThomas Huth uint64_t msr_bndcfgs; 1460fcf5ef2aSThomas Huth uint64_t efer; 1461fcf5ef2aSThomas Huth 1462fcf5ef2aSThomas Huth /* Beginning of state preserved by INIT (dummy marker). */ 1463fcf5ef2aSThomas Huth struct {} start_init_save; 1464fcf5ef2aSThomas Huth 1465fcf5ef2aSThomas Huth /* FPU state */ 1466fcf5ef2aSThomas Huth unsigned int fpstt; /* top of stack index */ 1467fcf5ef2aSThomas Huth uint16_t fpus; 1468fcf5ef2aSThomas Huth uint16_t fpuc; 1469fcf5ef2aSThomas Huth uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1470fcf5ef2aSThomas Huth FPReg fpregs[8]; 1471fcf5ef2aSThomas Huth /* KVM-only so far */ 1472fcf5ef2aSThomas Huth uint16_t fpop; 147384abdd7dSZiqiao Kong uint16_t fpcs; 147484abdd7dSZiqiao Kong uint16_t fpds; 1475fcf5ef2aSThomas Huth uint64_t fpip; 1476fcf5ef2aSThomas Huth uint64_t fpdp; 1477fcf5ef2aSThomas Huth 1478fcf5ef2aSThomas Huth /* emulator internal variables */ 1479fcf5ef2aSThomas Huth float_status fp_status; 1480fcf5ef2aSThomas Huth floatx80 ft0; 1481fcf5ef2aSThomas Huth 1482fcf5ef2aSThomas Huth float_status mmx_status; /* for 3DNow! float ops */ 1483fcf5ef2aSThomas Huth float_status sse_status; 1484fcf5ef2aSThomas Huth uint32_t mxcsr; 1485fcf5ef2aSThomas Huth ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1486fcf5ef2aSThomas Huth ZMMReg xmm_t0; 1487fcf5ef2aSThomas Huth MMXReg mmx_t0; 1488fcf5ef2aSThomas Huth 1489c97d6d2cSSergio Andres Gomez Del Real XMMReg ymmh_regs[CPU_NB_REGS]; 1490c97d6d2cSSergio Andres Gomez Del Real 1491fcf5ef2aSThomas Huth uint64_t opmask_regs[NB_OPMASK_REGS]; 1492c97d6d2cSSergio Andres Gomez Del Real YMMReg zmmh_regs[CPU_NB_REGS]; 1493c97d6d2cSSergio Andres Gomez Del Real ZMMReg hi16_zmm_regs[CPU_NB_REGS]; 1494fcf5ef2aSThomas Huth 1495fcf5ef2aSThomas Huth /* sysenter registers */ 1496fcf5ef2aSThomas Huth uint32_t sysenter_cs; 1497fcf5ef2aSThomas Huth target_ulong sysenter_esp; 1498fcf5ef2aSThomas Huth target_ulong sysenter_eip; 1499fcf5ef2aSThomas Huth uint64_t star; 1500fcf5ef2aSThomas Huth 1501fcf5ef2aSThomas Huth uint64_t vm_hsave; 1502fcf5ef2aSThomas Huth 1503fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 1504fcf5ef2aSThomas Huth target_ulong lstar; 1505fcf5ef2aSThomas Huth target_ulong cstar; 1506fcf5ef2aSThomas Huth target_ulong fmask; 1507fcf5ef2aSThomas Huth target_ulong kernelgsbase; 1508fcf5ef2aSThomas Huth #endif 1509fcf5ef2aSThomas Huth 1510fcf5ef2aSThomas Huth uint64_t tsc; 1511fcf5ef2aSThomas Huth uint64_t tsc_adjust; 1512fcf5ef2aSThomas Huth uint64_t tsc_deadline; 1513fcf5ef2aSThomas Huth uint64_t tsc_aux; 1514fcf5ef2aSThomas Huth 1515fcf5ef2aSThomas Huth uint64_t xcr0; 1516fcf5ef2aSThomas Huth 1517fcf5ef2aSThomas Huth uint64_t mcg_status; 1518fcf5ef2aSThomas Huth uint64_t msr_ia32_misc_enable; 1519fcf5ef2aSThomas Huth uint64_t msr_ia32_feature_control; 1520db888065SSean Christopherson uint64_t msr_ia32_sgxlepubkeyhash[4]; 1521fcf5ef2aSThomas Huth 1522fcf5ef2aSThomas Huth uint64_t msr_fixed_ctr_ctrl; 1523fcf5ef2aSThomas Huth uint64_t msr_global_ctrl; 1524fcf5ef2aSThomas Huth uint64_t msr_global_status; 1525fcf5ef2aSThomas Huth uint64_t msr_global_ovf_ctrl; 1526fcf5ef2aSThomas Huth uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1527fcf5ef2aSThomas Huth uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1528fcf5ef2aSThomas Huth uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1529fcf5ef2aSThomas Huth 1530fcf5ef2aSThomas Huth uint64_t pat; 1531fcf5ef2aSThomas Huth uint32_t smbase; 1532e13713dbSLiran Alon uint64_t msr_smi_count; 1533fcf5ef2aSThomas Huth 1534fcf5ef2aSThomas Huth uint32_t pkru; 1535e7e7bdabSPaolo Bonzini uint32_t pkrs; 15362a9758c5SPaolo Bonzini uint32_t tsx_ctrl; 1537fcf5ef2aSThomas Huth 1538a33a2cfeSPaolo Bonzini uint64_t spec_ctrl; 1539cfeea0c0SKonrad Rzeszutek Wilk uint64_t virt_ssbd; 1540a33a2cfeSPaolo Bonzini 1541fcf5ef2aSThomas Huth /* End of state preserved by INIT (dummy marker). */ 1542fcf5ef2aSThomas Huth struct {} end_init_save; 1543fcf5ef2aSThomas Huth 1544fcf5ef2aSThomas Huth uint64_t system_time_msr; 1545fcf5ef2aSThomas Huth uint64_t wall_clock_msr; 1546fcf5ef2aSThomas Huth uint64_t steal_time_msr; 1547fcf5ef2aSThomas Huth uint64_t async_pf_en_msr; 1548db5daafaSVitaly Kuznetsov uint64_t async_pf_int_msr; 1549fcf5ef2aSThomas Huth uint64_t pv_eoi_en_msr; 1550d645e132SMarcelo Tosatti uint64_t poll_control_msr; 1551fcf5ef2aSThomas Huth 1552da1cc323SEvgeny Yakovlev /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1553fcf5ef2aSThomas Huth uint64_t msr_hv_hypercall; 1554fcf5ef2aSThomas Huth uint64_t msr_hv_guest_os_id; 1555fcf5ef2aSThomas Huth uint64_t msr_hv_tsc; 1556da1cc323SEvgeny Yakovlev 1557da1cc323SEvgeny Yakovlev /* Per-VCPU HV MSRs */ 1558da1cc323SEvgeny Yakovlev uint64_t msr_hv_vapic; 15595e953812SRoman Kagan uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1560fcf5ef2aSThomas Huth uint64_t msr_hv_runtime; 1561fcf5ef2aSThomas Huth uint64_t msr_hv_synic_control; 1562fcf5ef2aSThomas Huth uint64_t msr_hv_synic_evt_page; 1563fcf5ef2aSThomas Huth uint64_t msr_hv_synic_msg_page; 15645e953812SRoman Kagan uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 15655e953812SRoman Kagan uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 15665e953812SRoman Kagan uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1567ba6a4fd9SVitaly Kuznetsov uint64_t msr_hv_reenlightenment_control; 1568ba6a4fd9SVitaly Kuznetsov uint64_t msr_hv_tsc_emulation_control; 1569ba6a4fd9SVitaly Kuznetsov uint64_t msr_hv_tsc_emulation_status; 1570fcf5ef2aSThomas Huth 1571b77146e9SChao Peng uint64_t msr_rtit_ctrl; 1572b77146e9SChao Peng uint64_t msr_rtit_status; 1573b77146e9SChao Peng uint64_t msr_rtit_output_base; 1574b77146e9SChao Peng uint64_t msr_rtit_output_mask; 1575b77146e9SChao Peng uint64_t msr_rtit_cr3_match; 1576b77146e9SChao Peng uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1577b77146e9SChao Peng 1578fcf5ef2aSThomas Huth /* exception/interrupt handling */ 1579fcf5ef2aSThomas Huth int error_code; 1580fcf5ef2aSThomas Huth int exception_is_int; 1581fcf5ef2aSThomas Huth target_ulong exception_next_eip; 1582fcf5ef2aSThomas Huth target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1583fcf5ef2aSThomas Huth union { 1584fcf5ef2aSThomas Huth struct CPUBreakpoint *cpu_breakpoint[4]; 1585fcf5ef2aSThomas Huth struct CPUWatchpoint *cpu_watchpoint[4]; 1586fcf5ef2aSThomas Huth }; /* break/watchpoints for dr[0..3] */ 1587fcf5ef2aSThomas Huth int old_exception; /* exception in flight */ 1588fcf5ef2aSThomas Huth 1589fcf5ef2aSThomas Huth uint64_t vm_vmcb; 1590fcf5ef2aSThomas Huth uint64_t tsc_offset; 1591fcf5ef2aSThomas Huth uint64_t intercept; 1592fcf5ef2aSThomas Huth uint16_t intercept_cr_read; 1593fcf5ef2aSThomas Huth uint16_t intercept_cr_write; 1594fcf5ef2aSThomas Huth uint16_t intercept_dr_read; 1595fcf5ef2aSThomas Huth uint16_t intercept_dr_write; 1596fcf5ef2aSThomas Huth uint32_t intercept_exceptions; 1597fe441054SJan Kiszka uint64_t nested_cr3; 1598fe441054SJan Kiszka uint32_t nested_pg_mode; 1599fcf5ef2aSThomas Huth uint8_t v_tpr; 1600e3126a5cSLara Lazier uint32_t int_ctl; 1601fcf5ef2aSThomas Huth 1602fcf5ef2aSThomas Huth /* KVM states, automatically cleared on reset */ 1603fcf5ef2aSThomas Huth uint8_t nmi_injected; 1604fcf5ef2aSThomas Huth uint8_t nmi_pending; 1605fcf5ef2aSThomas Huth 1606fe441054SJan Kiszka uintptr_t retaddr; 1607fe441054SJan Kiszka 16081f5c00cfSAlex Bennée /* Fields up to this point are cleared by a CPU reset */ 16091f5c00cfSAlex Bennée struct {} end_reset_fields; 16101f5c00cfSAlex Bennée 1611e8b5fae5SRichard Henderson /* Fields after this point are preserved across CPU reset. */ 1612fcf5ef2aSThomas Huth 1613fcf5ef2aSThomas Huth /* processor features (e.g. for CPUID insn) */ 161480db491dSJing Liu /* Minimum cpuid leaf 7 value */ 161580db491dSJing Liu uint32_t cpuid_level_func7; 161680db491dSJing Liu /* Actual cpuid leaf 7 value */ 161780db491dSJing Liu uint32_t cpuid_min_level_func7; 1618fcf5ef2aSThomas Huth /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1619fcf5ef2aSThomas Huth uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1620fcf5ef2aSThomas Huth /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1621fcf5ef2aSThomas Huth uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1622fcf5ef2aSThomas Huth /* Actual level/xlevel/xlevel2 value: */ 1623fcf5ef2aSThomas Huth uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1624fcf5ef2aSThomas Huth uint32_t cpuid_vendor1; 1625fcf5ef2aSThomas Huth uint32_t cpuid_vendor2; 1626fcf5ef2aSThomas Huth uint32_t cpuid_vendor3; 1627fcf5ef2aSThomas Huth uint32_t cpuid_version; 1628fcf5ef2aSThomas Huth FeatureWordArray features; 1629d4a606b3SEduardo Habkost /* Features that were explicitly enabled/disabled */ 1630d4a606b3SEduardo Habkost FeatureWordArray user_features; 1631fcf5ef2aSThomas Huth uint32_t cpuid_model[12]; 1632a9f27ea9SEduardo Habkost /* Cache information for CPUID. When legacy-cache=on, the cache data 1633a9f27ea9SEduardo Habkost * on each CPUID leaf will be different, because we keep compatibility 1634a9f27ea9SEduardo Habkost * with old QEMU versions. 1635a9f27ea9SEduardo Habkost */ 1636a9f27ea9SEduardo Habkost CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1637fcf5ef2aSThomas Huth 1638fcf5ef2aSThomas Huth /* MTRRs */ 1639fcf5ef2aSThomas Huth uint64_t mtrr_fixed[11]; 1640fcf5ef2aSThomas Huth uint64_t mtrr_deftype; 1641fcf5ef2aSThomas Huth MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1642fcf5ef2aSThomas Huth 1643fcf5ef2aSThomas Huth /* For KVM */ 1644fcf5ef2aSThomas Huth uint32_t mp_state; 1645fd13f23bSLiran Alon int32_t exception_nr; 1646fcf5ef2aSThomas Huth int32_t interrupt_injected; 1647fcf5ef2aSThomas Huth uint8_t soft_interrupt; 1648fd13f23bSLiran Alon uint8_t exception_pending; 1649fd13f23bSLiran Alon uint8_t exception_injected; 1650fcf5ef2aSThomas Huth uint8_t has_error_code; 1651fd13f23bSLiran Alon uint8_t exception_has_payload; 1652fd13f23bSLiran Alon uint64_t exception_payload; 1653c97d6d2cSSergio Andres Gomez Del Real uint32_t ins_len; 1654fcf5ef2aSThomas Huth uint32_t sipi_vector; 1655fcf5ef2aSThomas Huth bool tsc_valid; 1656fcf5ef2aSThomas Huth int64_t tsc_khz; 1657fcf5ef2aSThomas Huth int64_t user_tsc_khz; /* for sanity check only */ 165873b994f6SLiran Alon uint64_t apic_bus_freq; 16595b8063c4SLiran Alon #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 16605b8063c4SLiran Alon void *xsave_buf; 1661c0198c5fSDavid Edmondson uint32_t xsave_buf_len; 16625b8063c4SLiran Alon #endif 1663ebbfef2fSLiran Alon #if defined(CONFIG_KVM) 1664ebbfef2fSLiran Alon struct kvm_nested_state *nested_state; 1665ebbfef2fSLiran Alon #endif 1666c97d6d2cSSergio Andres Gomez Del Real #if defined(CONFIG_HVF) 1667577f02b8SRoman Bolshakov HVFX86LazyFlags hvf_lflags; 1668fe76b09cSRoman Bolshakov void *hvf_mmio_buf; 1669c97d6d2cSSergio Andres Gomez Del Real #endif 1670fcf5ef2aSThomas Huth 1671fcf5ef2aSThomas Huth uint64_t mcg_cap; 1672fcf5ef2aSThomas Huth uint64_t mcg_ctl; 1673fcf5ef2aSThomas Huth uint64_t mcg_ext_ctl; 1674fcf5ef2aSThomas Huth uint64_t mce_banks[MCE_BANKS_DEF*4]; 1675fcf5ef2aSThomas Huth uint64_t xstate_bv; 1676fcf5ef2aSThomas Huth 1677fcf5ef2aSThomas Huth /* vmstate */ 1678fcf5ef2aSThomas Huth uint16_t fpus_vmstate; 1679fcf5ef2aSThomas Huth uint16_t fptag_vmstate; 1680fcf5ef2aSThomas Huth uint16_t fpregs_format_vmstate; 1681fcf5ef2aSThomas Huth 1682fcf5ef2aSThomas Huth uint64_t xss; 168365087997STao Xu uint32_t umwait; 1684fcf5ef2aSThomas Huth 1685fcf5ef2aSThomas Huth TPRAccess tpr_access_type; 1686c26ae610SLike Xu 1687c26ae610SLike Xu unsigned nr_dies; 1688fcf5ef2aSThomas Huth } CPUX86State; 1689fcf5ef2aSThomas Huth 1690fcf5ef2aSThomas Huth struct kvm_msrs; 1691fcf5ef2aSThomas Huth 1692fcf5ef2aSThomas Huth /** 1693fcf5ef2aSThomas Huth * X86CPU: 1694fcf5ef2aSThomas Huth * @env: #CPUX86State 1695fcf5ef2aSThomas Huth * @migratable: If set, only migratable flags will be accepted when "enforce" 1696fcf5ef2aSThomas Huth * mode is used, and only migratable flags will be included in the "host" 1697fcf5ef2aSThomas Huth * CPU model. 1698fcf5ef2aSThomas Huth * 1699fcf5ef2aSThomas Huth * An x86 CPU. 1700fcf5ef2aSThomas Huth */ 1701fcf5ef2aSThomas Huth struct X86CPU { 1702fcf5ef2aSThomas Huth /*< private >*/ 1703fcf5ef2aSThomas Huth CPUState parent_obj; 1704fcf5ef2aSThomas Huth /*< public >*/ 1705fcf5ef2aSThomas Huth 17065b146dc7SRichard Henderson CPUNegativeOffsetState neg; 1707fcf5ef2aSThomas Huth CPUX86State env; 17082a693142SPan Nengyuan VMChangeStateEntry *vmsentry; 1709fcf5ef2aSThomas Huth 17104e45aff3SPaolo Bonzini uint64_t ucode_rev; 17114e45aff3SPaolo Bonzini 17124f2beda4SEduardo Habkost uint32_t hyperv_spinlock_attempts; 171308856771SVitaly Kuznetsov char *hyperv_vendor; 17149b4cf107SRoman Kagan bool hyperv_synic_kvm_only; 17152d384d7cSVitaly Kuznetsov uint64_t hyperv_features; 1716e48ddcc6SVitaly Kuznetsov bool hyperv_passthrough; 171730d6ff66SVitaly Kuznetsov OnOffAuto hyperv_no_nonarch_cs; 171808856771SVitaly Kuznetsov uint32_t hyperv_vendor_id[3]; 1719735db465SVitaly Kuznetsov uint32_t hyperv_interface_id[4]; 1720fb7e31aaSVitaly Kuznetsov uint32_t hyperv_version_id[4]; 172123eb5d03SVitaly Kuznetsov uint32_t hyperv_limits[3]; 1722c830015eSVitaly Kuznetsov uint32_t hyperv_nested[4]; 172370367f09SVitaly Kuznetsov bool hyperv_enforce_cpuid; 17242d384d7cSVitaly Kuznetsov 1725fcf5ef2aSThomas Huth bool check_cpuid; 1726fcf5ef2aSThomas Huth bool enforce_cpuid; 1727dac1deaeSEduardo Habkost /* 1728dac1deaeSEduardo Habkost * Force features to be enabled even if the host doesn't support them. 1729dac1deaeSEduardo Habkost * This is dangerous and should be done only for testing CPUID 1730dac1deaeSEduardo Habkost * compatibility. 1731dac1deaeSEduardo Habkost */ 1732dac1deaeSEduardo Habkost bool force_features; 1733fcf5ef2aSThomas Huth bool expose_kvm; 17341ce36bfeSDaniel P. Berrange bool expose_tcg; 1735fcf5ef2aSThomas Huth bool migratable; 1736990e0be2SPaolo Bonzini bool migrate_smi_count; 173744bd8e53SEduardo Habkost bool max_features; /* Enable all supported features automatically */ 1738fcf5ef2aSThomas Huth uint32_t apic_id; 1739fcf5ef2aSThomas Huth 17409954a158SPhil Dennis-Jordan /* Enables publishing of TSC increment and Local APIC bus frequencies to 17419954a158SPhil Dennis-Jordan * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 17429954a158SPhil Dennis-Jordan bool vmware_cpuid_freq; 17439954a158SPhil Dennis-Jordan 1744fcf5ef2aSThomas Huth /* if true the CPUID code directly forward host cache leaves to the guest */ 1745fcf5ef2aSThomas Huth bool cache_info_passthrough; 1746fcf5ef2aSThomas Huth 17472266d443SMichael S. Tsirkin /* if true the CPUID code directly forwards 17482266d443SMichael S. Tsirkin * host monitor/mwait leaves to the guest */ 17492266d443SMichael S. Tsirkin struct { 17502266d443SMichael S. Tsirkin uint32_t eax; 17512266d443SMichael S. Tsirkin uint32_t ebx; 17522266d443SMichael S. Tsirkin uint32_t ecx; 17532266d443SMichael S. Tsirkin uint32_t edx; 17542266d443SMichael S. Tsirkin } mwait; 17552266d443SMichael S. Tsirkin 1756fcf5ef2aSThomas Huth /* Features that were filtered out because of missing host capabilities */ 1757f69ecddbSWei Yang FeatureWordArray filtered_features; 1758fcf5ef2aSThomas Huth 1759fcf5ef2aSThomas Huth /* Enable PMU CPUID bits. This can't be enabled by default yet because 1760fcf5ef2aSThomas Huth * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1761fcf5ef2aSThomas Huth * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1762fcf5ef2aSThomas Huth * capabilities) directly to the guest. 1763fcf5ef2aSThomas Huth */ 1764fcf5ef2aSThomas Huth bool enable_pmu; 1765fcf5ef2aSThomas Huth 1766fcf5ef2aSThomas Huth /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1767fcf5ef2aSThomas Huth * disabled by default to avoid breaking migration between QEMU with 1768fcf5ef2aSThomas Huth * different LMCE configurations. 1769fcf5ef2aSThomas Huth */ 1770fcf5ef2aSThomas Huth bool enable_lmce; 1771fcf5ef2aSThomas Huth 1772fcf5ef2aSThomas Huth /* Compatibility bits for old machine types. 1773fcf5ef2aSThomas Huth * If true present virtual l3 cache for VM, the vcpus in the same virtual 1774fcf5ef2aSThomas Huth * socket share an virtual l3 cache. 1775fcf5ef2aSThomas Huth */ 1776fcf5ef2aSThomas Huth bool enable_l3_cache; 1777fcf5ef2aSThomas Huth 1778ab8f992eSBabu Moger /* Compatibility bits for old machine types. 1779ab8f992eSBabu Moger * If true present the old cache topology information 1780ab8f992eSBabu Moger */ 1781ab8f992eSBabu Moger bool legacy_cache; 1782ab8f992eSBabu Moger 1783fcf5ef2aSThomas Huth /* Compatibility bits for old machine types: */ 1784fcf5ef2aSThomas Huth bool enable_cpuid_0xb; 1785fcf5ef2aSThomas Huth 1786fcf5ef2aSThomas Huth /* Enable auto level-increase for all CPUID leaves */ 1787fcf5ef2aSThomas Huth bool full_cpuid_auto_level; 1788fcf5ef2aSThomas Huth 1789a7a0da84SMichael Roth /* Only advertise CPUID leaves defined by the vendor */ 1790a7a0da84SMichael Roth bool vendor_cpuid_only; 1791a7a0da84SMichael Roth 1792f24c3a79SLuwei Kang /* Enable auto level-increase for Intel Processor Trace leave */ 1793f24c3a79SLuwei Kang bool intel_pt_auto_level; 1794f24c3a79SLuwei Kang 1795fcf5ef2aSThomas Huth /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1796fcf5ef2aSThomas Huth bool fill_mtrr_mask; 1797fcf5ef2aSThomas Huth 1798fcf5ef2aSThomas Huth /* if true override the phys_bits value with a value read from the host */ 1799fcf5ef2aSThomas Huth bool host_phys_bits; 1800fcf5ef2aSThomas Huth 1801258fe08bSEduardo Habkost /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 1802258fe08bSEduardo Habkost uint8_t host_phys_bits_limit; 1803258fe08bSEduardo Habkost 1804fc3a1fd7SDr. David Alan Gilbert /* Stop SMI delivery for migration compatibility with old machines */ 1805fc3a1fd7SDr. David Alan Gilbert bool kvm_no_smi_migration; 1806fc3a1fd7SDr. David Alan Gilbert 1807988f7b8bSVitaly Kuznetsov /* Forcefully disable KVM PV features not exposed in guest CPUIDs */ 1808988f7b8bSVitaly Kuznetsov bool kvm_pv_enforce_cpuid; 1809988f7b8bSVitaly Kuznetsov 1810fcf5ef2aSThomas Huth /* Number of physical address bits supported */ 1811fcf5ef2aSThomas Huth uint32_t phys_bits; 1812fcf5ef2aSThomas Huth 1813fcf5ef2aSThomas Huth /* in order to simplify APIC support, we leave this pointer to the 1814fcf5ef2aSThomas Huth user */ 1815fcf5ef2aSThomas Huth struct DeviceState *apic_state; 1816fcf5ef2aSThomas Huth struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1817fcf5ef2aSThomas Huth Notifier machine_done; 1818fcf5ef2aSThomas Huth 1819fcf5ef2aSThomas Huth struct kvm_msrs *kvm_msr_buf; 1820fcf5ef2aSThomas Huth 182115f8b142SIgor Mammedov int32_t node_id; /* NUMA node this CPU belongs to */ 1822fcf5ef2aSThomas Huth int32_t socket_id; 1823176d2cdaSLike Xu int32_t die_id; 1824fcf5ef2aSThomas Huth int32_t core_id; 1825fcf5ef2aSThomas Huth int32_t thread_id; 18266c69dfb6SGonglei 18276c69dfb6SGonglei int32_t hv_max_vps; 1828fcf5ef2aSThomas Huth }; 1829fcf5ef2aSThomas Huth 1830fcf5ef2aSThomas Huth 1831fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 1832ac701a4fSKeqian Zhu extern const VMStateDescription vmstate_x86_cpu; 1833fcf5ef2aSThomas Huth #endif 1834fcf5ef2aSThomas Huth 183592d5f1a4SPaolo Bonzini int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 1836fcf5ef2aSThomas Huth 1837fcf5ef2aSThomas Huth int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1838fcf5ef2aSThomas Huth int cpuid, void *opaque); 1839fcf5ef2aSThomas Huth int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1840fcf5ef2aSThomas Huth int cpuid, void *opaque); 1841fcf5ef2aSThomas Huth int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1842fcf5ef2aSThomas Huth void *opaque); 1843fcf5ef2aSThomas Huth int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1844fcf5ef2aSThomas Huth void *opaque); 1845fcf5ef2aSThomas Huth 1846fcf5ef2aSThomas Huth void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1847fcf5ef2aSThomas Huth Error **errp); 1848fcf5ef2aSThomas Huth 184990c84c56SMarkus Armbruster void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 1850fcf5ef2aSThomas Huth 185156f99750SDmitry Poletaev hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 185256f99750SDmitry Poletaev MemTxAttrs *attrs); 1853fcf5ef2aSThomas Huth 1854a010bdbeSAlex Bennée int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1855fcf5ef2aSThomas Huth int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1856fcf5ef2aSThomas Huth 18570442428aSMarkus Armbruster void x86_cpu_list(void); 1858fcf5ef2aSThomas Huth int cpu_x86_support_mca_broadcast(CPUX86State *env); 1859fcf5ef2aSThomas Huth 186076d0042bSPhilippe Mathieu-Daudé #ifndef CONFIG_USER_ONLY 1861fcf5ef2aSThomas Huth int cpu_get_pic_interrupt(CPUX86State *s); 18627ce08865SPhilippe Mathieu-Daudé 1863fcf5ef2aSThomas Huth /* MSDOS compatibility mode FPU exception support */ 18646f529b75SPaolo Bonzini void x86_register_ferr_irq(qemu_irq irq); 186583a3d9c7SClaudio Fontana void fpu_check_raise_ferr_irq(CPUX86State *s); 1866bf13bfabSPaolo Bonzini void cpu_set_ignne(void); 186783a3d9c7SClaudio Fontana void cpu_clear_ignne(void); 18687ce08865SPhilippe Mathieu-Daudé #endif 186983a3d9c7SClaudio Fontana 18705e76d84eSPaolo Bonzini /* mpx_helper.c */ 18715e76d84eSPaolo Bonzini void cpu_sync_bndcs_hflags(CPUX86State *env); 1872fcf5ef2aSThomas Huth 1873fcf5ef2aSThomas Huth /* this function must always be used to load data in the segment 1874fcf5ef2aSThomas Huth cache: it synchronizes the hflags with the segment cache values */ 1875fcf5ef2aSThomas Huth static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1876c117e5b1SPhilippe Mathieu-Daudé X86Seg seg_reg, unsigned int selector, 1877fcf5ef2aSThomas Huth target_ulong base, 1878fcf5ef2aSThomas Huth unsigned int limit, 1879fcf5ef2aSThomas Huth unsigned int flags) 1880fcf5ef2aSThomas Huth { 1881fcf5ef2aSThomas Huth SegmentCache *sc; 1882fcf5ef2aSThomas Huth unsigned int new_hflags; 1883fcf5ef2aSThomas Huth 1884fcf5ef2aSThomas Huth sc = &env->segs[seg_reg]; 1885fcf5ef2aSThomas Huth sc->selector = selector; 1886fcf5ef2aSThomas Huth sc->base = base; 1887fcf5ef2aSThomas Huth sc->limit = limit; 1888fcf5ef2aSThomas Huth sc->flags = flags; 1889fcf5ef2aSThomas Huth 1890fcf5ef2aSThomas Huth /* update the hidden flags */ 1891fcf5ef2aSThomas Huth { 1892fcf5ef2aSThomas Huth if (seg_reg == R_CS) { 1893fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 1894fcf5ef2aSThomas Huth if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1895fcf5ef2aSThomas Huth /* long mode */ 1896fcf5ef2aSThomas Huth env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1897fcf5ef2aSThomas Huth env->hflags &= ~(HF_ADDSEG_MASK); 1898fcf5ef2aSThomas Huth } else 1899fcf5ef2aSThomas Huth #endif 1900fcf5ef2aSThomas Huth { 1901fcf5ef2aSThomas Huth /* legacy / compatibility case */ 1902fcf5ef2aSThomas Huth new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1903fcf5ef2aSThomas Huth >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1904fcf5ef2aSThomas Huth env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1905fcf5ef2aSThomas Huth new_hflags; 1906fcf5ef2aSThomas Huth } 1907fcf5ef2aSThomas Huth } 1908fcf5ef2aSThomas Huth if (seg_reg == R_SS) { 1909fcf5ef2aSThomas Huth int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1910fcf5ef2aSThomas Huth #if HF_CPL_MASK != 3 1911fcf5ef2aSThomas Huth #error HF_CPL_MASK is hardcoded 1912fcf5ef2aSThomas Huth #endif 1913fcf5ef2aSThomas Huth env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 19145e76d84eSPaolo Bonzini /* Possibly switch between BNDCFGS and BNDCFGU */ 19155e76d84eSPaolo Bonzini cpu_sync_bndcs_hflags(env); 1916fcf5ef2aSThomas Huth } 1917fcf5ef2aSThomas Huth new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1918fcf5ef2aSThomas Huth >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1919fcf5ef2aSThomas Huth if (env->hflags & HF_CS64_MASK) { 1920fcf5ef2aSThomas Huth /* zero base assumed for DS, ES and SS in long mode */ 1921fcf5ef2aSThomas Huth } else if (!(env->cr[0] & CR0_PE_MASK) || 1922fcf5ef2aSThomas Huth (env->eflags & VM_MASK) || 1923fcf5ef2aSThomas Huth !(env->hflags & HF_CS32_MASK)) { 1924fcf5ef2aSThomas Huth /* XXX: try to avoid this test. The problem comes from the 1925fcf5ef2aSThomas Huth fact that is real mode or vm86 mode we only modify the 1926fcf5ef2aSThomas Huth 'base' and 'selector' fields of the segment cache to go 1927fcf5ef2aSThomas Huth faster. A solution may be to force addseg to one in 1928fcf5ef2aSThomas Huth translate-i386.c. */ 1929fcf5ef2aSThomas Huth new_hflags |= HF_ADDSEG_MASK; 1930fcf5ef2aSThomas Huth } else { 1931fcf5ef2aSThomas Huth new_hflags |= ((env->segs[R_DS].base | 1932fcf5ef2aSThomas Huth env->segs[R_ES].base | 1933fcf5ef2aSThomas Huth env->segs[R_SS].base) != 0) << 1934fcf5ef2aSThomas Huth HF_ADDSEG_SHIFT; 1935fcf5ef2aSThomas Huth } 1936fcf5ef2aSThomas Huth env->hflags = (env->hflags & 1937fcf5ef2aSThomas Huth ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1938fcf5ef2aSThomas Huth } 1939fcf5ef2aSThomas Huth } 1940fcf5ef2aSThomas Huth 1941fcf5ef2aSThomas Huth static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1942fcf5ef2aSThomas Huth uint8_t sipi_vector) 1943fcf5ef2aSThomas Huth { 1944fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 1945fcf5ef2aSThomas Huth CPUX86State *env = &cpu->env; 1946fcf5ef2aSThomas Huth 1947fcf5ef2aSThomas Huth env->eip = 0; 1948fcf5ef2aSThomas Huth cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1949fcf5ef2aSThomas Huth sipi_vector << 12, 1950fcf5ef2aSThomas Huth env->segs[R_CS].limit, 1951fcf5ef2aSThomas Huth env->segs[R_CS].flags); 1952fcf5ef2aSThomas Huth cs->halted = 0; 1953fcf5ef2aSThomas Huth } 1954fcf5ef2aSThomas Huth 1955fcf5ef2aSThomas Huth int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1956fcf5ef2aSThomas Huth target_ulong *base, unsigned int *limit, 1957fcf5ef2aSThomas Huth unsigned int *flags); 1958fcf5ef2aSThomas Huth 1959fcf5ef2aSThomas Huth /* op_helper.c */ 1960fcf5ef2aSThomas Huth /* used for debug or cpu save/restore */ 1961fcf5ef2aSThomas Huth 1962fcf5ef2aSThomas Huth /* cpu-exec.c */ 1963fcf5ef2aSThomas Huth /* the following helpers are only usable in user mode simulation as 1964fcf5ef2aSThomas Huth they can trigger unexpected exceptions */ 1965c117e5b1SPhilippe Mathieu-Daudé void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); 1966fcf5ef2aSThomas Huth void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1967fcf5ef2aSThomas Huth void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 19681c1df019SPranith Kumar void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 19691c1df019SPranith Kumar void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1970fcf5ef2aSThomas Huth 1971fcf5ef2aSThomas Huth /* cpu.c */ 1972f5cc5a5cSClaudio Fontana void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 1973f5cc5a5cSClaudio Fontana uint32_t vendor2, uint32_t vendor3); 1974f5cc5a5cSClaudio Fontana typedef struct PropValue { 1975f5cc5a5cSClaudio Fontana const char *prop, *value; 1976f5cc5a5cSClaudio Fontana } PropValue; 1977f5cc5a5cSClaudio Fontana void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); 1978f5cc5a5cSClaudio Fontana 197997afb47eSLara Lazier uint32_t cpu_x86_virtual_addr_width(CPUX86State *env); 198097afb47eSLara Lazier 1981f5cc5a5cSClaudio Fontana /* cpu.c other functions (cpuid) */ 1982fcf5ef2aSThomas Huth void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1983fcf5ef2aSThomas Huth uint32_t *eax, uint32_t *ebx, 1984fcf5ef2aSThomas Huth uint32_t *ecx, uint32_t *edx); 1985fcf5ef2aSThomas Huth void cpu_clear_apic_feature(CPUX86State *env); 1986fcf5ef2aSThomas Huth void host_cpuid(uint32_t function, uint32_t count, 1987fcf5ef2aSThomas Huth uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 1988fcf5ef2aSThomas Huth 1989fcf5ef2aSThomas Huth /* helper.c */ 1990fcf5ef2aSThomas Huth void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1991fcf5ef2aSThomas Huth 1992fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 1993f8c45c65SPaolo Bonzini static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1994f8c45c65SPaolo Bonzini { 1995f8c45c65SPaolo Bonzini return !!attrs.secure; 1996f8c45c65SPaolo Bonzini } 1997f8c45c65SPaolo Bonzini 1998f8c45c65SPaolo Bonzini static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1999f8c45c65SPaolo Bonzini { 2000f8c45c65SPaolo Bonzini return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 2001f8c45c65SPaolo Bonzini } 2002f8c45c65SPaolo Bonzini 200363087289SClaudio Fontana /* 200463087289SClaudio Fontana * load efer and update the corresponding hflags. XXX: do consistency 200563087289SClaudio Fontana * checks with cpuid bits? 200663087289SClaudio Fontana */ 200763087289SClaudio Fontana void cpu_load_efer(CPUX86State *env, uint64_t val); 2008fcf5ef2aSThomas Huth uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 2009fcf5ef2aSThomas Huth uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 2010fcf5ef2aSThomas Huth uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 2011fcf5ef2aSThomas Huth uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 2012fcf5ef2aSThomas Huth void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 2013fcf5ef2aSThomas Huth void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 2014fcf5ef2aSThomas Huth void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 2015fcf5ef2aSThomas Huth void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 2016fcf5ef2aSThomas Huth void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 2017fcf5ef2aSThomas Huth #endif 2018fcf5ef2aSThomas Huth 2019fcf5ef2aSThomas Huth /* will be suppressed */ 2020fcf5ef2aSThomas Huth void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 2021fcf5ef2aSThomas Huth void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 2022fcf5ef2aSThomas Huth void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 2023fcf5ef2aSThomas Huth void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 2024fcf5ef2aSThomas Huth 2025fcf5ef2aSThomas Huth /* hw/pc.c */ 2026fcf5ef2aSThomas Huth uint64_t cpu_get_tsc(CPUX86State *env); 2027fcf5ef2aSThomas Huth 2028311ca98dSIgor Mammedov #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 2029311ca98dSIgor Mammedov #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 20300dacec87SIgor Mammedov #define CPU_RESOLVING_TYPE TYPE_X86_CPU 2031311ca98dSIgor Mammedov 2032311ca98dSIgor Mammedov #ifdef TARGET_X86_64 2033311ca98dSIgor Mammedov #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 2034311ca98dSIgor Mammedov #else 2035311ca98dSIgor Mammedov #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 2036311ca98dSIgor Mammedov #endif 2037311ca98dSIgor Mammedov 2038fcf5ef2aSThomas Huth #define cpu_list x86_cpu_list 2039fcf5ef2aSThomas Huth 2040fcf5ef2aSThomas Huth /* MMU modes definitions */ 2041fcf5ef2aSThomas Huth #define MMU_KSMAP_IDX 0 2042fcf5ef2aSThomas Huth #define MMU_USER_IDX 1 2043fcf5ef2aSThomas Huth #define MMU_KNOSMAP_IDX 2 2044fcf5ef2aSThomas Huth static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 2045fcf5ef2aSThomas Huth { 2046fcf5ef2aSThomas Huth return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 2047fcf5ef2aSThomas Huth (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 2048fcf5ef2aSThomas Huth ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2049fcf5ef2aSThomas Huth } 2050fcf5ef2aSThomas Huth 2051fcf5ef2aSThomas Huth static inline int cpu_mmu_index_kernel(CPUX86State *env) 2052fcf5ef2aSThomas Huth { 2053fcf5ef2aSThomas Huth return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 2054fcf5ef2aSThomas Huth ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 2055fcf5ef2aSThomas Huth ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2056fcf5ef2aSThomas Huth } 2057fcf5ef2aSThomas Huth 2058fcf5ef2aSThomas Huth #define CC_DST (env->cc_dst) 2059fcf5ef2aSThomas Huth #define CC_SRC (env->cc_src) 2060fcf5ef2aSThomas Huth #define CC_SRC2 (env->cc_src2) 2061fcf5ef2aSThomas Huth #define CC_OP (env->cc_op) 2062fcf5ef2aSThomas Huth 20634f7c64b3SRichard Henderson typedef CPUX86State CPUArchState; 20642161a612SRichard Henderson typedef X86CPU ArchCPU; 20654f7c64b3SRichard Henderson 2066fcf5ef2aSThomas Huth #include "exec/cpu-all.h" 2067fcf5ef2aSThomas Huth #include "svm.h" 2068fcf5ef2aSThomas Huth 2069fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2070fcf5ef2aSThomas Huth #include "hw/i386/apic.h" 2071fcf5ef2aSThomas Huth #endif 2072fcf5ef2aSThomas Huth 2073fcf5ef2aSThomas Huth static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 2074fcf5ef2aSThomas Huth target_ulong *cs_base, uint32_t *flags) 2075fcf5ef2aSThomas Huth { 2076fcf5ef2aSThomas Huth *cs_base = env->segs[R_CS].base; 2077fcf5ef2aSThomas Huth *pc = *cs_base + env->eip; 2078fcf5ef2aSThomas Huth *flags = env->hflags | 2079fcf5ef2aSThomas Huth (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2080fcf5ef2aSThomas Huth } 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth void do_cpu_init(X86CPU *cpu); 2083fcf5ef2aSThomas Huth void do_cpu_sipi(X86CPU *cpu); 2084fcf5ef2aSThomas Huth 2085fcf5ef2aSThomas Huth #define MCE_INJECT_BROADCAST 1 2086fcf5ef2aSThomas Huth #define MCE_INJECT_UNCOND_AO 2 2087fcf5ef2aSThomas Huth 2088fcf5ef2aSThomas Huth void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2089fcf5ef2aSThomas Huth uint64_t status, uint64_t mcg_status, uint64_t addr, 2090fcf5ef2aSThomas Huth uint64_t misc, int flags); 2091fcf5ef2aSThomas Huth 2092fcf5ef2aSThomas Huth uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2093fcf5ef2aSThomas Huth 2094fcf5ef2aSThomas Huth static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2095fcf5ef2aSThomas Huth { 209679c664f6SYang Zhong uint32_t eflags = env->eflags; 209779c664f6SYang Zhong if (tcg_enabled()) { 209879c664f6SYang Zhong eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 209979c664f6SYang Zhong } 210079c664f6SYang Zhong return eflags; 2101fcf5ef2aSThomas Huth } 2102fcf5ef2aSThomas Huth 2103fcf5ef2aSThomas Huth static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2104fcf5ef2aSThomas Huth { 2105fcf5ef2aSThomas Huth return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2106fcf5ef2aSThomas Huth } 2107fcf5ef2aSThomas Huth 2108c8bc83a4SPaolo Bonzini static inline int32_t x86_get_a20_mask(CPUX86State *env) 2109c8bc83a4SPaolo Bonzini { 2110c8bc83a4SPaolo Bonzini if (env->hflags & HF_SMM_MASK) { 2111c8bc83a4SPaolo Bonzini return -1; 2112c8bc83a4SPaolo Bonzini } else { 2113c8bc83a4SPaolo Bonzini return env->a20_mask; 2114c8bc83a4SPaolo Bonzini } 2115c8bc83a4SPaolo Bonzini } 2116c8bc83a4SPaolo Bonzini 211718ab37baSLiran Alon static inline bool cpu_has_vmx(CPUX86State *env) 211818ab37baSLiran Alon { 211918ab37baSLiran Alon return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 212018ab37baSLiran Alon } 212118ab37baSLiran Alon 2122b16c0e20SPaolo Bonzini static inline bool cpu_has_svm(CPUX86State *env) 2123b16c0e20SPaolo Bonzini { 2124b16c0e20SPaolo Bonzini return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2125b16c0e20SPaolo Bonzini } 2126b16c0e20SPaolo Bonzini 212779a197abSLiran Alon /* 212879a197abSLiran Alon * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 212979a197abSLiran Alon * Since it was set, CR4.VMXE must remain set as long as vCPU is in 213079a197abSLiran Alon * VMX operation. This is because CR4.VMXE is one of the bits set 213179a197abSLiran Alon * in MSR_IA32_VMX_CR4_FIXED1. 213279a197abSLiran Alon * 213379a197abSLiran Alon * There is one exception to above statement when vCPU enters SMM mode. 213479a197abSLiran Alon * When a vCPU enters SMM mode, it temporarily exit VMX operation and 213579a197abSLiran Alon * may also reset CR4.VMXE during execution in SMM mode. 213679a197abSLiran Alon * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 213779a197abSLiran Alon * and CR4.VMXE is restored to it's original value of being set. 213879a197abSLiran Alon * 213979a197abSLiran Alon * Therefore, when vCPU is not in SMM mode, we can infer whether 214079a197abSLiran Alon * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 214179a197abSLiran Alon * know for certain. 214279a197abSLiran Alon */ 214379a197abSLiran Alon static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 214479a197abSLiran Alon { 214579a197abSLiran Alon return cpu_has_vmx(env) && 214679a197abSLiran Alon ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 214779a197abSLiran Alon } 214879a197abSLiran Alon 2149616a89eaSPaolo Bonzini /* excp_helper.c */ 2150616a89eaSPaolo Bonzini int get_pg_mode(CPUX86State *env); 2151616a89eaSPaolo Bonzini 2152fcf5ef2aSThomas Huth /* fpu_helper.c */ 21531d8ad165SYang Zhong void update_fp_status(CPUX86State *env); 21541d8ad165SYang Zhong void update_mxcsr_status(CPUX86State *env); 2155418b0f93SJoseph Myers void update_mxcsr_from_sse_status(CPUX86State *env); 21561d8ad165SYang Zhong 21571d8ad165SYang Zhong static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 21581d8ad165SYang Zhong { 21591d8ad165SYang Zhong env->mxcsr = mxcsr; 21601d8ad165SYang Zhong if (tcg_enabled()) { 21611d8ad165SYang Zhong update_mxcsr_status(env); 21621d8ad165SYang Zhong } 21631d8ad165SYang Zhong } 21641d8ad165SYang Zhong 21651d8ad165SYang Zhong static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 21661d8ad165SYang Zhong { 21671d8ad165SYang Zhong env->fpuc = fpuc; 21681d8ad165SYang Zhong if (tcg_enabled()) { 21691d8ad165SYang Zhong update_fp_status(env); 21701d8ad165SYang Zhong } 21711d8ad165SYang Zhong } 2172fcf5ef2aSThomas Huth 2173fcf5ef2aSThomas Huth /* mem_helper.c */ 2174fcf5ef2aSThomas Huth void helper_lock_init(void); 2175fcf5ef2aSThomas Huth 2176fcf5ef2aSThomas Huth /* svm_helper.c */ 217727bd3216SRichard Henderson #ifdef CONFIG_USER_ONLY 217827bd3216SRichard Henderson static inline void 217927bd3216SRichard Henderson cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 218027bd3216SRichard Henderson uint64_t param, uintptr_t retaddr) 218127bd3216SRichard Henderson { /* no-op */ } 2182813c6459SLara Lazier static inline bool 2183813c6459SLara Lazier cpu_svm_has_intercept(CPUX86State *env, uint32_t type) 2184813c6459SLara Lazier { return false; } 218527bd3216SRichard Henderson #else 2186fcf5ef2aSThomas Huth void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 218765c9d60aSPaolo Bonzini uint64_t param, uintptr_t retaddr); 2188813c6459SLara Lazier bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); 218927bd3216SRichard Henderson #endif 219027bd3216SRichard Henderson 2191fcf5ef2aSThomas Huth /* apic.c */ 2192fcf5ef2aSThomas Huth void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2193fcf5ef2aSThomas Huth void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2194fcf5ef2aSThomas Huth TPRAccess access); 2195fcf5ef2aSThomas Huth 2196dcafd1efSEduardo Habkost /* Special values for X86CPUVersion: */ 2197dcafd1efSEduardo Habkost 2198dcafd1efSEduardo Habkost /* Resolve to latest CPU version */ 2199dcafd1efSEduardo Habkost #define CPU_VERSION_LATEST -1 2200dcafd1efSEduardo Habkost 22010788a56bSEduardo Habkost /* 22020788a56bSEduardo Habkost * Resolve to version defined by current machine type. 22030788a56bSEduardo Habkost * See x86_cpu_set_default_version() 22040788a56bSEduardo Habkost */ 22050788a56bSEduardo Habkost #define CPU_VERSION_AUTO -2 22060788a56bSEduardo Habkost 2207dcafd1efSEduardo Habkost /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2208dcafd1efSEduardo Habkost #define CPU_VERSION_LEGACY 0 2209dcafd1efSEduardo Habkost 2210dcafd1efSEduardo Habkost typedef int X86CPUVersion; 2211dcafd1efSEduardo Habkost 22120788a56bSEduardo Habkost /* 22130788a56bSEduardo Habkost * Set default CPU model version for CPU models having 22140788a56bSEduardo Habkost * version == CPU_VERSION_AUTO. 22150788a56bSEduardo Habkost */ 22160788a56bSEduardo Habkost void x86_cpu_set_default_version(X86CPUVersion version); 22170788a56bSEduardo Habkost 2218fcf5ef2aSThomas Huth #define APIC_DEFAULT_ADDRESS 0xfee00000 2219fcf5ef2aSThomas Huth #define APIC_SPACE_SIZE 0x100000 2220fcf5ef2aSThomas Huth 22210c36af8cSClaudio Fontana /* cpu-dump.c */ 2222d3fd9e4bSMarkus Armbruster void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2223fcf5ef2aSThomas Huth 2224fcf5ef2aSThomas Huth /* cpu.c */ 2225fcf5ef2aSThomas Huth bool cpu_is_bsp(X86CPU *cpu); 2226fcf5ef2aSThomas Huth 2227c0198c5fSDavid Edmondson void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen); 2228c0198c5fSDavid Edmondson void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); 222935b1b927STao Wu void x86_update_hflags(CPUX86State* env); 223035b1b927STao Wu 22312d384d7cSVitaly Kuznetsov static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 22322d384d7cSVitaly Kuznetsov { 22332d384d7cSVitaly Kuznetsov return !!(cpu->hyperv_features & BIT(feat)); 22342d384d7cSVitaly Kuznetsov } 22352d384d7cSVitaly Kuznetsov 2236213ff024SLara Lazier static inline uint64_t cr4_reserved_bits(CPUX86State *env) 2237213ff024SLara Lazier { 2238213ff024SLara Lazier uint64_t reserved_bits = CR4_RESERVED_MASK; 2239213ff024SLara Lazier if (!env->features[FEAT_XSAVE]) { 2240213ff024SLara Lazier reserved_bits |= CR4_OSXSAVE_MASK; 2241213ff024SLara Lazier } 2242213ff024SLara Lazier if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) { 2243213ff024SLara Lazier reserved_bits |= CR4_SMEP_MASK; 2244213ff024SLara Lazier } 2245213ff024SLara Lazier if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { 2246213ff024SLara Lazier reserved_bits |= CR4_SMAP_MASK; 2247213ff024SLara Lazier } 2248213ff024SLara Lazier if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) { 2249213ff024SLara Lazier reserved_bits |= CR4_FSGSBASE_MASK; 2250213ff024SLara Lazier } 2251213ff024SLara Lazier if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { 2252213ff024SLara Lazier reserved_bits |= CR4_PKE_MASK; 2253213ff024SLara Lazier } 2254213ff024SLara Lazier if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) { 2255213ff024SLara Lazier reserved_bits |= CR4_LA57_MASK; 2256213ff024SLara Lazier } 2257213ff024SLara Lazier if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { 2258213ff024SLara Lazier reserved_bits |= CR4_UMIP_MASK; 2259213ff024SLara Lazier } 2260213ff024SLara Lazier if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { 2261213ff024SLara Lazier reserved_bits |= CR4_PKS_MASK; 2262213ff024SLara Lazier } 2263213ff024SLara Lazier return reserved_bits; 2264213ff024SLara Lazier } 2265213ff024SLara Lazier 22667760bb06SLara Lazier static inline bool ctl_has_irq(CPUX86State *env) 22677760bb06SLara Lazier { 22687760bb06SLara Lazier uint32_t int_prio; 22697760bb06SLara Lazier uint32_t tpr; 22707760bb06SLara Lazier 22717760bb06SLara Lazier int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; 22727760bb06SLara Lazier tpr = env->int_ctl & V_TPR_MASK; 22737760bb06SLara Lazier 22747760bb06SLara Lazier if (env->int_ctl & V_IGN_TPR_MASK) { 22757760bb06SLara Lazier return (env->int_ctl & V_IRQ_MASK); 22767760bb06SLara Lazier } 22777760bb06SLara Lazier 22787760bb06SLara Lazier return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr); 22797760bb06SLara Lazier } 22807760bb06SLara Lazier 228152fb8ad3SLara Lazier hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, 228252fb8ad3SLara Lazier int *prot); 2283b26491b4SRichard Henderson #if defined(TARGET_X86_64) && \ 2284b26491b4SRichard Henderson defined(CONFIG_USER_ONLY) && \ 2285b26491b4SRichard Henderson defined(CONFIG_LINUX) 2286b26491b4SRichard Henderson # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2287b26491b4SRichard Henderson #endif 2288b26491b4SRichard Henderson 2289fcf5ef2aSThomas Huth #endif /* I386_CPU_H */ 2290