1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * i386 virtual CPU header 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003 Fabrice Bellard 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9d9ff33adSChetan Pant * version 2.1 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18fcf5ef2aSThomas Huth */ 19fcf5ef2aSThomas Huth 20fcf5ef2aSThomas Huth #ifndef I386_CPU_H 21fcf5ef2aSThomas Huth #define I386_CPU_H 22fcf5ef2aSThomas Huth 2314a48c1dSMarkus Armbruster #include "sysemu/tcg.h" 24fcf5ef2aSThomas Huth #include "cpu-qom.h" 25a9dc68d9SClaudio Fontana #include "kvm/hyperv-proto.h" 26c97d6d2cSSergio Andres Gomez Del Real #include "exec/cpu-defs.h" 2730d6ff66SVitaly Kuznetsov #include "qapi/qapi-types-common.h" 2869242e7eSMarc-André Lureau #include "qemu/cpu-float.h" 29b746a779SJoao Martins #include "qemu/timer.h" 30c97d6d2cSSergio Andres Gomez Del Real 31c723d4c1SDavid Woodhouse #define XEN_NR_VIRQS 24 32c723d4c1SDavid Woodhouse 3372c1701fSAlex Bennée /* The x86 has a strong memory model with some store-after-load re-ordering */ 3472c1701fSAlex Bennée #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 3572c1701fSAlex Bennée 36e24fd076SDongjiu Geng #define KVM_HAVE_MCE_INJECTION 1 37e24fd076SDongjiu Geng 38fcf5ef2aSThomas Huth /* support for self modifying code even if the modified instruction is 39fcf5ef2aSThomas Huth close to the modifying instruction */ 40fcf5ef2aSThomas Huth #define TARGET_HAS_PRECISE_SMC 41fcf5ef2aSThomas Huth 42fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 43fcf5ef2aSThomas Huth #define I386_ELF_MACHINE EM_X86_64 44fcf5ef2aSThomas Huth #define ELF_MACHINE_UNAME "x86_64" 45fcf5ef2aSThomas Huth #else 46fcf5ef2aSThomas Huth #define I386_ELF_MACHINE EM_386 47fcf5ef2aSThomas Huth #define ELF_MACHINE_UNAME "i686" 48fcf5ef2aSThomas Huth #endif 49fcf5ef2aSThomas Huth 506701d81dSPaolo Bonzini enum { 516701d81dSPaolo Bonzini R_EAX = 0, 526701d81dSPaolo Bonzini R_ECX = 1, 536701d81dSPaolo Bonzini R_EDX = 2, 546701d81dSPaolo Bonzini R_EBX = 3, 556701d81dSPaolo Bonzini R_ESP = 4, 566701d81dSPaolo Bonzini R_EBP = 5, 576701d81dSPaolo Bonzini R_ESI = 6, 586701d81dSPaolo Bonzini R_EDI = 7, 596701d81dSPaolo Bonzini R_R8 = 8, 606701d81dSPaolo Bonzini R_R9 = 9, 616701d81dSPaolo Bonzini R_R10 = 10, 626701d81dSPaolo Bonzini R_R11 = 11, 636701d81dSPaolo Bonzini R_R12 = 12, 646701d81dSPaolo Bonzini R_R13 = 13, 656701d81dSPaolo Bonzini R_R14 = 14, 666701d81dSPaolo Bonzini R_R15 = 15, 67fcf5ef2aSThomas Huth 686701d81dSPaolo Bonzini R_AL = 0, 696701d81dSPaolo Bonzini R_CL = 1, 706701d81dSPaolo Bonzini R_DL = 2, 716701d81dSPaolo Bonzini R_BL = 3, 726701d81dSPaolo Bonzini R_AH = 4, 736701d81dSPaolo Bonzini R_CH = 5, 746701d81dSPaolo Bonzini R_DH = 6, 756701d81dSPaolo Bonzini R_BH = 7, 766701d81dSPaolo Bonzini }; 77fcf5ef2aSThomas Huth 786701d81dSPaolo Bonzini typedef enum X86Seg { 796701d81dSPaolo Bonzini R_ES = 0, 806701d81dSPaolo Bonzini R_CS = 1, 816701d81dSPaolo Bonzini R_SS = 2, 826701d81dSPaolo Bonzini R_DS = 3, 836701d81dSPaolo Bonzini R_FS = 4, 846701d81dSPaolo Bonzini R_GS = 5, 856701d81dSPaolo Bonzini R_LDTR = 6, 866701d81dSPaolo Bonzini R_TR = 7, 876701d81dSPaolo Bonzini } X86Seg; 88fcf5ef2aSThomas Huth 89fcf5ef2aSThomas Huth /* segment descriptor fields */ 90c97d6d2cSSergio Andres Gomez Del Real #define DESC_G_SHIFT 23 91c97d6d2cSSergio Andres Gomez Del Real #define DESC_G_MASK (1 << DESC_G_SHIFT) 92fcf5ef2aSThomas Huth #define DESC_B_SHIFT 22 93fcf5ef2aSThomas Huth #define DESC_B_MASK (1 << DESC_B_SHIFT) 94fcf5ef2aSThomas Huth #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 95fcf5ef2aSThomas Huth #define DESC_L_MASK (1 << DESC_L_SHIFT) 96c97d6d2cSSergio Andres Gomez Del Real #define DESC_AVL_SHIFT 20 97c97d6d2cSSergio Andres Gomez Del Real #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) 98c97d6d2cSSergio Andres Gomez Del Real #define DESC_P_SHIFT 15 99c97d6d2cSSergio Andres Gomez Del Real #define DESC_P_MASK (1 << DESC_P_SHIFT) 100fcf5ef2aSThomas Huth #define DESC_DPL_SHIFT 13 101fcf5ef2aSThomas Huth #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 102c97d6d2cSSergio Andres Gomez Del Real #define DESC_S_SHIFT 12 103c97d6d2cSSergio Andres Gomez Del Real #define DESC_S_MASK (1 << DESC_S_SHIFT) 104fcf5ef2aSThomas Huth #define DESC_TYPE_SHIFT 8 105fcf5ef2aSThomas Huth #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 106fcf5ef2aSThomas Huth #define DESC_A_MASK (1 << 8) 107fcf5ef2aSThomas Huth 108fcf5ef2aSThomas Huth #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 109fcf5ef2aSThomas Huth #define DESC_C_MASK (1 << 10) /* code: conforming */ 110fcf5ef2aSThomas Huth #define DESC_R_MASK (1 << 9) /* code: readable */ 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 113fcf5ef2aSThomas Huth #define DESC_W_MASK (1 << 9) /* data: writable */ 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth #define DESC_TSS_BUSY_MASK (1 << 9) 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth /* eflags masks */ 118fcf5ef2aSThomas Huth #define CC_C 0x0001 119fcf5ef2aSThomas Huth #define CC_P 0x0004 120fcf5ef2aSThomas Huth #define CC_A 0x0010 121fcf5ef2aSThomas Huth #define CC_Z 0x0040 122fcf5ef2aSThomas Huth #define CC_S 0x0080 123fcf5ef2aSThomas Huth #define CC_O 0x0800 124fcf5ef2aSThomas Huth 125fcf5ef2aSThomas Huth #define TF_SHIFT 8 126fcf5ef2aSThomas Huth #define IOPL_SHIFT 12 127fcf5ef2aSThomas Huth #define VM_SHIFT 17 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth #define TF_MASK 0x00000100 130fcf5ef2aSThomas Huth #define IF_MASK 0x00000200 131fcf5ef2aSThomas Huth #define DF_MASK 0x00000400 132fcf5ef2aSThomas Huth #define IOPL_MASK 0x00003000 133fcf5ef2aSThomas Huth #define NT_MASK 0x00004000 134fcf5ef2aSThomas Huth #define RF_MASK 0x00010000 135fcf5ef2aSThomas Huth #define VM_MASK 0x00020000 136fcf5ef2aSThomas Huth #define AC_MASK 0x00040000 137fcf5ef2aSThomas Huth #define VIF_MASK 0x00080000 138fcf5ef2aSThomas Huth #define VIP_MASK 0x00100000 139fcf5ef2aSThomas Huth #define ID_MASK 0x00200000 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth /* hidden flags - used internally by qemu to represent additional cpu 142fcf5ef2aSThomas Huth states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 143fcf5ef2aSThomas Huth avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 144fcf5ef2aSThomas Huth positions to ease oring with eflags. */ 145fcf5ef2aSThomas Huth /* current cpl */ 146fcf5ef2aSThomas Huth #define HF_CPL_SHIFT 0 147fcf5ef2aSThomas Huth /* true if hardware interrupts must be disabled for next instruction */ 148fcf5ef2aSThomas Huth #define HF_INHIBIT_IRQ_SHIFT 3 149fcf5ef2aSThomas Huth /* 16 or 32 segments */ 150fcf5ef2aSThomas Huth #define HF_CS32_SHIFT 4 151fcf5ef2aSThomas Huth #define HF_SS32_SHIFT 5 152fcf5ef2aSThomas Huth /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 153fcf5ef2aSThomas Huth #define HF_ADDSEG_SHIFT 6 154fcf5ef2aSThomas Huth /* copy of CR0.PE (protected mode) */ 155fcf5ef2aSThomas Huth #define HF_PE_SHIFT 7 156fcf5ef2aSThomas Huth #define HF_TF_SHIFT 8 /* must be same as eflags */ 157fcf5ef2aSThomas Huth #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 158fcf5ef2aSThomas Huth #define HF_EM_SHIFT 10 159fcf5ef2aSThomas Huth #define HF_TS_SHIFT 11 160fcf5ef2aSThomas Huth #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 161fcf5ef2aSThomas Huth #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 162fcf5ef2aSThomas Huth #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 163fcf5ef2aSThomas Huth #define HF_RF_SHIFT 16 /* must be same as eflags */ 164fcf5ef2aSThomas Huth #define HF_VM_SHIFT 17 /* must be same as eflags */ 165fcf5ef2aSThomas Huth #define HF_AC_SHIFT 18 /* must be same as eflags */ 166fcf5ef2aSThomas Huth #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 167fcf5ef2aSThomas Huth #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 168f8dc4c64SPaolo Bonzini #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ 169fcf5ef2aSThomas Huth #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 170fcf5ef2aSThomas Huth #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 171fcf5ef2aSThomas Huth #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 172fcf5ef2aSThomas Huth #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 173fcf5ef2aSThomas Huth #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 174637f1ee3SGareth Webb #define HF_UMIP_SHIFT 27 /* CR4.UMIP */ 175608db8dbSPaul Brook #define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */ 176fcf5ef2aSThomas Huth 177fcf5ef2aSThomas Huth #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 178fcf5ef2aSThomas Huth #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 179fcf5ef2aSThomas Huth #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 180fcf5ef2aSThomas Huth #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 181fcf5ef2aSThomas Huth #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 182fcf5ef2aSThomas Huth #define HF_PE_MASK (1 << HF_PE_SHIFT) 183fcf5ef2aSThomas Huth #define HF_TF_MASK (1 << HF_TF_SHIFT) 184fcf5ef2aSThomas Huth #define HF_MP_MASK (1 << HF_MP_SHIFT) 185fcf5ef2aSThomas Huth #define HF_EM_MASK (1 << HF_EM_SHIFT) 186fcf5ef2aSThomas Huth #define HF_TS_MASK (1 << HF_TS_SHIFT) 187fcf5ef2aSThomas Huth #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 188fcf5ef2aSThomas Huth #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 189fcf5ef2aSThomas Huth #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 190fcf5ef2aSThomas Huth #define HF_RF_MASK (1 << HF_RF_SHIFT) 191fcf5ef2aSThomas Huth #define HF_VM_MASK (1 << HF_VM_SHIFT) 192fcf5ef2aSThomas Huth #define HF_AC_MASK (1 << HF_AC_SHIFT) 193fcf5ef2aSThomas Huth #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 194fcf5ef2aSThomas Huth #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 195f8dc4c64SPaolo Bonzini #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) 196fcf5ef2aSThomas Huth #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 197fcf5ef2aSThomas Huth #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 198fcf5ef2aSThomas Huth #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 199fcf5ef2aSThomas Huth #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 200fcf5ef2aSThomas Huth #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 201637f1ee3SGareth Webb #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT) 202608db8dbSPaul Brook #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT) 203fcf5ef2aSThomas Huth 204fcf5ef2aSThomas Huth /* hflags2 */ 205fcf5ef2aSThomas Huth 206fcf5ef2aSThomas Huth #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 207fcf5ef2aSThomas Huth #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 208fcf5ef2aSThomas Huth #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 209fcf5ef2aSThomas Huth #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 210fcf5ef2aSThomas Huth #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 211fcf5ef2aSThomas Huth #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 212fe441054SJan Kiszka #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ 213bf13bfabSPaolo Bonzini #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ 214b67e2796SLara Lazier #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/ 215fcf5ef2aSThomas Huth 216fcf5ef2aSThomas Huth #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 217fcf5ef2aSThomas Huth #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 218fcf5ef2aSThomas Huth #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 219fcf5ef2aSThomas Huth #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 220fcf5ef2aSThomas Huth #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 221fcf5ef2aSThomas Huth #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 222fe441054SJan Kiszka #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) 223bf13bfabSPaolo Bonzini #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) 224b67e2796SLara Lazier #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT) 225fcf5ef2aSThomas Huth 226fcf5ef2aSThomas Huth #define CR0_PE_SHIFT 0 227fcf5ef2aSThomas Huth #define CR0_MP_SHIFT 1 228fcf5ef2aSThomas Huth 229fcf5ef2aSThomas Huth #define CR0_PE_MASK (1U << 0) 230fcf5ef2aSThomas Huth #define CR0_MP_MASK (1U << 1) 231fcf5ef2aSThomas Huth #define CR0_EM_MASK (1U << 2) 232fcf5ef2aSThomas Huth #define CR0_TS_MASK (1U << 3) 233fcf5ef2aSThomas Huth #define CR0_ET_MASK (1U << 4) 234fcf5ef2aSThomas Huth #define CR0_NE_MASK (1U << 5) 235fcf5ef2aSThomas Huth #define CR0_WP_MASK (1U << 16) 236fcf5ef2aSThomas Huth #define CR0_AM_MASK (1U << 18) 237498df2a7SLara Lazier #define CR0_NW_MASK (1U << 29) 238498df2a7SLara Lazier #define CR0_CD_MASK (1U << 30) 239fcf5ef2aSThomas Huth #define CR0_PG_MASK (1U << 31) 240fcf5ef2aSThomas Huth 241fcf5ef2aSThomas Huth #define CR4_VME_MASK (1U << 0) 242fcf5ef2aSThomas Huth #define CR4_PVI_MASK (1U << 1) 243fcf5ef2aSThomas Huth #define CR4_TSD_MASK (1U << 2) 244fcf5ef2aSThomas Huth #define CR4_DE_MASK (1U << 3) 245fcf5ef2aSThomas Huth #define CR4_PSE_MASK (1U << 4) 246fcf5ef2aSThomas Huth #define CR4_PAE_MASK (1U << 5) 247fcf5ef2aSThomas Huth #define CR4_MCE_MASK (1U << 6) 248fcf5ef2aSThomas Huth #define CR4_PGE_MASK (1U << 7) 249fcf5ef2aSThomas Huth #define CR4_PCE_MASK (1U << 8) 250fcf5ef2aSThomas Huth #define CR4_OSFXSR_SHIFT 9 251fcf5ef2aSThomas Huth #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 252fcf5ef2aSThomas Huth #define CR4_OSXMMEXCPT_MASK (1U << 10) 253213ff024SLara Lazier #define CR4_UMIP_MASK (1U << 11) 2546c7c3c21SKirill A. Shutemov #define CR4_LA57_MASK (1U << 12) 255fcf5ef2aSThomas Huth #define CR4_VMXE_MASK (1U << 13) 256fcf5ef2aSThomas Huth #define CR4_SMXE_MASK (1U << 14) 257fcf5ef2aSThomas Huth #define CR4_FSGSBASE_MASK (1U << 16) 258fcf5ef2aSThomas Huth #define CR4_PCIDE_MASK (1U << 17) 259fcf5ef2aSThomas Huth #define CR4_OSXSAVE_MASK (1U << 18) 260fcf5ef2aSThomas Huth #define CR4_SMEP_MASK (1U << 20) 261fcf5ef2aSThomas Huth #define CR4_SMAP_MASK (1U << 21) 262fcf5ef2aSThomas Huth #define CR4_PKE_MASK (1U << 22) 263e7e7bdabSPaolo Bonzini #define CR4_PKS_MASK (1U << 24) 264fcf5ef2aSThomas Huth 265213ff024SLara Lazier #define CR4_RESERVED_MASK \ 266213ff024SLara Lazier (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ 267213ff024SLara Lazier | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ 268213ff024SLara Lazier | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ 269213ff024SLara Lazier | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ 27069e3895fSDaniel P. Berrangé | CR4_LA57_MASK \ 271213ff024SLara Lazier | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ 272213ff024SLara Lazier | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) 273213ff024SLara Lazier 274fcf5ef2aSThomas Huth #define DR6_BD (1 << 13) 275fcf5ef2aSThomas Huth #define DR6_BS (1 << 14) 276fcf5ef2aSThomas Huth #define DR6_BT (1 << 15) 277fcf5ef2aSThomas Huth #define DR6_FIXED_1 0xffff0ff0 278fcf5ef2aSThomas Huth 279fcf5ef2aSThomas Huth #define DR7_GD (1 << 13) 280fcf5ef2aSThomas Huth #define DR7_TYPE_SHIFT 16 281fcf5ef2aSThomas Huth #define DR7_LEN_SHIFT 18 282fcf5ef2aSThomas Huth #define DR7_FIXED_1 0x00000400 283fcf5ef2aSThomas Huth #define DR7_GLOBAL_BP_MASK 0xaa 284fcf5ef2aSThomas Huth #define DR7_LOCAL_BP_MASK 0x55 285fcf5ef2aSThomas Huth #define DR7_MAX_BP 4 286fcf5ef2aSThomas Huth #define DR7_TYPE_BP_INST 0x0 287fcf5ef2aSThomas Huth #define DR7_TYPE_DATA_WR 0x1 288fcf5ef2aSThomas Huth #define DR7_TYPE_IO_RW 0x2 289fcf5ef2aSThomas Huth #define DR7_TYPE_DATA_RW 0x3 290fcf5ef2aSThomas Huth 291533883fdSPaolo Bonzini #define DR_RESERVED_MASK 0xffffffff00000000ULL 292533883fdSPaolo Bonzini 293fcf5ef2aSThomas Huth #define PG_PRESENT_BIT 0 294fcf5ef2aSThomas Huth #define PG_RW_BIT 1 295fcf5ef2aSThomas Huth #define PG_USER_BIT 2 296fcf5ef2aSThomas Huth #define PG_PWT_BIT 3 297fcf5ef2aSThomas Huth #define PG_PCD_BIT 4 298fcf5ef2aSThomas Huth #define PG_ACCESSED_BIT 5 299fcf5ef2aSThomas Huth #define PG_DIRTY_BIT 6 300fcf5ef2aSThomas Huth #define PG_PSE_BIT 7 301fcf5ef2aSThomas Huth #define PG_GLOBAL_BIT 8 302fcf5ef2aSThomas Huth #define PG_PSE_PAT_BIT 12 303fcf5ef2aSThomas Huth #define PG_PKRU_BIT 59 304fcf5ef2aSThomas Huth #define PG_NX_BIT 63 305fcf5ef2aSThomas Huth 306fcf5ef2aSThomas Huth #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 307fcf5ef2aSThomas Huth #define PG_RW_MASK (1 << PG_RW_BIT) 308fcf5ef2aSThomas Huth #define PG_USER_MASK (1 << PG_USER_BIT) 309fcf5ef2aSThomas Huth #define PG_PWT_MASK (1 << PG_PWT_BIT) 310fcf5ef2aSThomas Huth #define PG_PCD_MASK (1 << PG_PCD_BIT) 311fcf5ef2aSThomas Huth #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 312fcf5ef2aSThomas Huth #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 313fcf5ef2aSThomas Huth #define PG_PSE_MASK (1 << PG_PSE_BIT) 314fcf5ef2aSThomas Huth #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 315fcf5ef2aSThomas Huth #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 316fcf5ef2aSThomas Huth #define PG_ADDRESS_MASK 0x000ffffffffff000LL 317fcf5ef2aSThomas Huth #define PG_HI_USER_MASK 0x7ff0000000000000LL 318fcf5ef2aSThomas Huth #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 319fcf5ef2aSThomas Huth #define PG_NX_MASK (1ULL << PG_NX_BIT) 320fcf5ef2aSThomas Huth 321fcf5ef2aSThomas Huth #define PG_ERROR_W_BIT 1 322fcf5ef2aSThomas Huth 323fcf5ef2aSThomas Huth #define PG_ERROR_P_MASK 0x01 324fcf5ef2aSThomas Huth #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 325fcf5ef2aSThomas Huth #define PG_ERROR_U_MASK 0x04 326fcf5ef2aSThomas Huth #define PG_ERROR_RSVD_MASK 0x08 327fcf5ef2aSThomas Huth #define PG_ERROR_I_D_MASK 0x10 328fcf5ef2aSThomas Huth #define PG_ERROR_PK_MASK 0x20 329fcf5ef2aSThomas Huth 330616a89eaSPaolo Bonzini #define PG_MODE_PAE (1 << 0) 331616a89eaSPaolo Bonzini #define PG_MODE_LMA (1 << 1) 332616a89eaSPaolo Bonzini #define PG_MODE_NXE (1 << 2) 333616a89eaSPaolo Bonzini #define PG_MODE_PSE (1 << 3) 33431dd35ebSPaolo Bonzini #define PG_MODE_LA57 (1 << 4) 33531dd35ebSPaolo Bonzini #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) 33631dd35ebSPaolo Bonzini 33731dd35ebSPaolo Bonzini /* Bits of CR4 that do not affect the NPT page format. */ 33831dd35ebSPaolo Bonzini #define PG_MODE_WP (1 << 16) 33931dd35ebSPaolo Bonzini #define PG_MODE_PKE (1 << 17) 34031dd35ebSPaolo Bonzini #define PG_MODE_PKS (1 << 18) 34131dd35ebSPaolo Bonzini #define PG_MODE_SMEP (1 << 19) 342616a89eaSPaolo Bonzini 343fcf5ef2aSThomas Huth #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 344fcf5ef2aSThomas Huth #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 345fcf5ef2aSThomas Huth #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 346fcf5ef2aSThomas Huth 347fcf5ef2aSThomas Huth #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 348fcf5ef2aSThomas Huth #define MCE_BANKS_DEF 10 349fcf5ef2aSThomas Huth 350fcf5ef2aSThomas Huth #define MCG_CAP_BANKS_MASK 0xff 351fcf5ef2aSThomas Huth 352fcf5ef2aSThomas Huth #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 353fcf5ef2aSThomas Huth #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 354fcf5ef2aSThomas Huth #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 355fcf5ef2aSThomas Huth #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 356fcf5ef2aSThomas Huth 357fcf5ef2aSThomas Huth #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 358fcf5ef2aSThomas Huth 359fcf5ef2aSThomas Huth #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 360fcf5ef2aSThomas Huth #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 361fcf5ef2aSThomas Huth #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 362fcf5ef2aSThomas Huth #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 363fcf5ef2aSThomas Huth #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 364fcf5ef2aSThomas Huth #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 365fcf5ef2aSThomas Huth #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 366fcf5ef2aSThomas Huth #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 367fcf5ef2aSThomas Huth #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 368fcf5ef2aSThomas Huth 369fcf5ef2aSThomas Huth /* MISC register defines */ 370fcf5ef2aSThomas Huth #define MCM_ADDR_SEGOFF 0 /* segment offset */ 371fcf5ef2aSThomas Huth #define MCM_ADDR_LINEAR 1 /* linear address */ 372fcf5ef2aSThomas Huth #define MCM_ADDR_PHYS 2 /* physical address */ 373fcf5ef2aSThomas Huth #define MCM_ADDR_MEM 3 /* memory address */ 374fcf5ef2aSThomas Huth #define MCM_ADDR_GENERIC 7 /* generic */ 375fcf5ef2aSThomas Huth 376fcf5ef2aSThomas Huth #define MSR_IA32_TSC 0x10 377fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE 0x1b 378fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_BSP (1<<8) 379fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_ENABLE (1<<11) 380fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_EXTD (1 << 10) 381fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 382fcf5ef2aSThomas Huth #define MSR_IA32_FEATURE_CONTROL 0x0000003a 383fcf5ef2aSThomas Huth #define MSR_TSC_ADJUST 0x0000003b 384a33a2cfeSPaolo Bonzini #define MSR_IA32_SPEC_CTRL 0x48 385cfeea0c0SKonrad Rzeszutek Wilk #define MSR_VIRT_SSBD 0xc001011f 3868c80c99fSRobert Hoo #define MSR_IA32_PRED_CMD 0x49 3874e45aff3SPaolo Bonzini #define MSR_IA32_UCODE_REV 0x8b 388597360c0SXiaoyao Li #define MSR_IA32_CORE_CAPABILITY 0xcf 3892a9758c5SPaolo Bonzini 3908c80c99fSRobert Hoo #define MSR_IA32_ARCH_CAPABILITIES 0x10a 3912a9758c5SPaolo Bonzini #define ARCH_CAP_TSX_CTRL_MSR (1<<7) 3922a9758c5SPaolo Bonzini 393ea39f9b6SLike Xu #define MSR_IA32_PERF_CAPABILITIES 0x345 394f06d8a18SYang Weijiang #define PERF_CAP_LBR_FMT 0x3f 395ea39f9b6SLike Xu 3962a9758c5SPaolo Bonzini #define MSR_IA32_TSX_CTRL 0x122 397fcf5ef2aSThomas Huth #define MSR_IA32_TSCDEADLINE 0x6e0 398e7e7bdabSPaolo Bonzini #define MSR_IA32_PKRS 0x6e1 39912703d4eSYang Weijiang #define MSR_ARCH_LBR_CTL 0x000014ce 40012703d4eSYang Weijiang #define MSR_ARCH_LBR_DEPTH 0x000014cf 40112703d4eSYang Weijiang #define MSR_ARCH_LBR_FROM_0 0x00001500 40212703d4eSYang Weijiang #define MSR_ARCH_LBR_TO_0 0x00001600 40312703d4eSYang Weijiang #define MSR_ARCH_LBR_INFO_0 0x00001200 404fcf5ef2aSThomas Huth 405fcf5ef2aSThomas Huth #define FEATURE_CONTROL_LOCKED (1<<0) 4065c76b651SSean Christopherson #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1) 407fcf5ef2aSThomas Huth #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 4085c76b651SSean Christopherson #define FEATURE_CONTROL_SGX_LC (1ULL << 17) 4095c76b651SSean Christopherson #define FEATURE_CONTROL_SGX (1ULL << 18) 410fcf5ef2aSThomas Huth #define FEATURE_CONTROL_LMCE (1<<20) 411fcf5ef2aSThomas Huth 4125c76b651SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c 4135c76b651SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d 4145c76b651SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e 4155c76b651SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f 4165c76b651SSean Christopherson 417fcf5ef2aSThomas Huth #define MSR_P6_PERFCTR0 0xc1 418fcf5ef2aSThomas Huth 419fcf5ef2aSThomas Huth #define MSR_IA32_SMBASE 0x9e 420e13713dbSLiran Alon #define MSR_SMI_COUNT 0x34 421027ac0cbSVladislav Yaroshchuk #define MSR_CORE_THREAD_COUNT 0x35 422fcf5ef2aSThomas Huth #define MSR_MTRRcap 0xfe 423fcf5ef2aSThomas Huth #define MSR_MTRRcap_VCNT 8 424fcf5ef2aSThomas Huth #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 425fcf5ef2aSThomas Huth #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 426fcf5ef2aSThomas Huth 427fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_CS 0x174 428fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_ESP 0x175 429fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_EIP 0x176 430fcf5ef2aSThomas Huth 431fcf5ef2aSThomas Huth #define MSR_MCG_CAP 0x179 432fcf5ef2aSThomas Huth #define MSR_MCG_STATUS 0x17a 433fcf5ef2aSThomas Huth #define MSR_MCG_CTL 0x17b 434fcf5ef2aSThomas Huth #define MSR_MCG_EXT_CTL 0x4d0 435fcf5ef2aSThomas Huth 436fcf5ef2aSThomas Huth #define MSR_P6_EVNTSEL0 0x186 437fcf5ef2aSThomas Huth 438fcf5ef2aSThomas Huth #define MSR_IA32_PERF_STATUS 0x198 439fcf5ef2aSThomas Huth 440fcf5ef2aSThomas Huth #define MSR_IA32_MISC_ENABLE 0x1a0 441fcf5ef2aSThomas Huth /* Indicates good rep/movs microcode on some processors: */ 442fcf5ef2aSThomas Huth #define MSR_IA32_MISC_ENABLE_DEFAULT 1 4434cfd7babSWanpeng Li #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 444fcf5ef2aSThomas Huth 445fcf5ef2aSThomas Huth #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 446fcf5ef2aSThomas Huth #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 447fcf5ef2aSThomas Huth 448fcf5ef2aSThomas Huth #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 449fcf5ef2aSThomas Huth 450fcf5ef2aSThomas Huth #define MSR_MTRRfix64K_00000 0x250 451fcf5ef2aSThomas Huth #define MSR_MTRRfix16K_80000 0x258 452fcf5ef2aSThomas Huth #define MSR_MTRRfix16K_A0000 0x259 453fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_C0000 0x268 454fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_C8000 0x269 455fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_D0000 0x26a 456fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_D8000 0x26b 457fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_E0000 0x26c 458fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_E8000 0x26d 459fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_F0000 0x26e 460fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_F8000 0x26f 461fcf5ef2aSThomas Huth 462fcf5ef2aSThomas Huth #define MSR_PAT 0x277 463fcf5ef2aSThomas Huth 464fcf5ef2aSThomas Huth #define MSR_MTRRdefType 0x2ff 465fcf5ef2aSThomas Huth 466fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR0 0x309 467fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR1 0x30a 468fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR2 0x30b 469fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 470fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 471fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 472fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 473fcf5ef2aSThomas Huth 474fcf5ef2aSThomas Huth #define MSR_MC0_CTL 0x400 475fcf5ef2aSThomas Huth #define MSR_MC0_STATUS 0x401 476fcf5ef2aSThomas Huth #define MSR_MC0_ADDR 0x402 477fcf5ef2aSThomas Huth #define MSR_MC0_MISC 0x403 478fcf5ef2aSThomas Huth 479b77146e9SChao Peng #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 480b77146e9SChao Peng #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 481b77146e9SChao Peng #define MSR_IA32_RTIT_CTL 0x570 482b77146e9SChao Peng #define MSR_IA32_RTIT_STATUS 0x571 483b77146e9SChao Peng #define MSR_IA32_RTIT_CR3_MATCH 0x572 484b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR0_A 0x580 485b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR0_B 0x581 486b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR1_A 0x582 487b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR1_B 0x583 488b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR2_A 0x584 489b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR2_B 0x585 490b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR3_A 0x586 491b77146e9SChao Peng #define MSR_IA32_RTIT_ADDR3_B 0x587 492b77146e9SChao Peng #define MAX_RTIT_ADDRS 8 493b77146e9SChao Peng 494fcf5ef2aSThomas Huth #define MSR_EFER 0xc0000080 495fcf5ef2aSThomas Huth 496fcf5ef2aSThomas Huth #define MSR_EFER_SCE (1 << 0) 497fcf5ef2aSThomas Huth #define MSR_EFER_LME (1 << 8) 498fcf5ef2aSThomas Huth #define MSR_EFER_LMA (1 << 10) 499fcf5ef2aSThomas Huth #define MSR_EFER_NXE (1 << 11) 500fcf5ef2aSThomas Huth #define MSR_EFER_SVME (1 << 12) 501fcf5ef2aSThomas Huth #define MSR_EFER_FFXSR (1 << 14) 502fcf5ef2aSThomas Huth 503d499f196SLara Lazier #define MSR_EFER_RESERVED\ 504d499f196SLara Lazier (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\ 505d499f196SLara Lazier | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\ 506d499f196SLara Lazier | MSR_EFER_FFXSR)) 507d499f196SLara Lazier 508fcf5ef2aSThomas Huth #define MSR_STAR 0xc0000081 509fcf5ef2aSThomas Huth #define MSR_LSTAR 0xc0000082 510fcf5ef2aSThomas Huth #define MSR_CSTAR 0xc0000083 511fcf5ef2aSThomas Huth #define MSR_FMASK 0xc0000084 512fcf5ef2aSThomas Huth #define MSR_FSBASE 0xc0000100 513fcf5ef2aSThomas Huth #define MSR_GSBASE 0xc0000101 514fcf5ef2aSThomas Huth #define MSR_KERNELGSBASE 0xc0000102 515fcf5ef2aSThomas Huth #define MSR_TSC_AUX 0xc0000103 516cabf9862SMaxim Levitsky #define MSR_AMD64_TSC_RATIO 0xc0000104 517cabf9862SMaxim Levitsky 518cabf9862SMaxim Levitsky #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL 519fcf5ef2aSThomas Huth 520fcf5ef2aSThomas Huth #define MSR_VM_HSAVE_PA 0xc0010117 521fcf5ef2aSThomas Huth 522cdec2b75SZeng Guang #define MSR_IA32_XFD 0x000001c4 523cdec2b75SZeng Guang #define MSR_IA32_XFD_ERR 0x000001c5 524cdec2b75SZeng Guang 525fcf5ef2aSThomas Huth #define MSR_IA32_BNDCFGS 0x00000d90 526fcf5ef2aSThomas Huth #define MSR_IA32_XSS 0x00000da0 52765087997STao Xu #define MSR_IA32_UMWAIT_CONTROL 0xe1 528fcf5ef2aSThomas Huth 529704798adSPaolo Bonzini #define MSR_IA32_VMX_BASIC 0x00000480 530704798adSPaolo Bonzini #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 531704798adSPaolo Bonzini #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 532704798adSPaolo Bonzini #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 533704798adSPaolo Bonzini #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 534704798adSPaolo Bonzini #define MSR_IA32_VMX_MISC 0x00000485 535704798adSPaolo Bonzini #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 536704798adSPaolo Bonzini #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 537704798adSPaolo Bonzini #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 538704798adSPaolo Bonzini #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 539704798adSPaolo Bonzini #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 540704798adSPaolo Bonzini #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 541704798adSPaolo Bonzini #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 542704798adSPaolo Bonzini #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 543704798adSPaolo Bonzini #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 544704798adSPaolo Bonzini #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 545704798adSPaolo Bonzini #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 546704798adSPaolo Bonzini #define MSR_IA32_VMX_VMFUNC 0x00000491 547704798adSPaolo Bonzini 548fcf5ef2aSThomas Huth #define XSTATE_FP_BIT 0 549fcf5ef2aSThomas Huth #define XSTATE_SSE_BIT 1 550fcf5ef2aSThomas Huth #define XSTATE_YMM_BIT 2 551fcf5ef2aSThomas Huth #define XSTATE_BNDREGS_BIT 3 552fcf5ef2aSThomas Huth #define XSTATE_BNDCSR_BIT 4 553fcf5ef2aSThomas Huth #define XSTATE_OPMASK_BIT 5 554fcf5ef2aSThomas Huth #define XSTATE_ZMM_Hi256_BIT 6 555fcf5ef2aSThomas Huth #define XSTATE_Hi16_ZMM_BIT 7 556fcf5ef2aSThomas Huth #define XSTATE_PKRU_BIT 9 55710f0abcbSYang Weijiang #define XSTATE_ARCH_LBR_BIT 15 5581f16764fSJing Liu #define XSTATE_XTILE_CFG_BIT 17 5591f16764fSJing Liu #define XSTATE_XTILE_DATA_BIT 18 560fcf5ef2aSThomas Huth 561fcf5ef2aSThomas Huth #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 562fcf5ef2aSThomas Huth #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 563fcf5ef2aSThomas Huth #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 564fcf5ef2aSThomas Huth #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 565fcf5ef2aSThomas Huth #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 566fcf5ef2aSThomas Huth #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 567fcf5ef2aSThomas Huth #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 568fcf5ef2aSThomas Huth #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 569fcf5ef2aSThomas Huth #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 57010f0abcbSYang Weijiang #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT) 57119db68caSYang Zhong #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) 57219db68caSYang Zhong #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) 57319db68caSYang Zhong 57419db68caSYang Zhong #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) 575fcf5ef2aSThomas Huth 576131266b7SJing Liu #define ESA_FEATURE_ALIGN64_BIT 1 5770f17f6b3SJing Liu #define ESA_FEATURE_XFD_BIT 2 578131266b7SJing Liu 579131266b7SJing Liu #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) 5800f17f6b3SJing Liu #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT) 581131266b7SJing Liu 582131266b7SJing Liu 583301e9067SYang Weijiang /* CPUID feature bits available in XCR0 */ 584301e9067SYang Weijiang #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ 585301e9067SYang Weijiang XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ 586301e9067SYang Weijiang XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \ 587301e9067SYang Weijiang XSTATE_ZMM_Hi256_MASK | \ 588301e9067SYang Weijiang XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \ 589301e9067SYang Weijiang XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK) 590301e9067SYang Weijiang 591fcf5ef2aSThomas Huth /* CPUID feature words */ 592fcf5ef2aSThomas Huth typedef enum FeatureWord { 593fcf5ef2aSThomas Huth FEAT_1_EDX, /* CPUID[1].EDX */ 594fcf5ef2aSThomas Huth FEAT_1_ECX, /* CPUID[1].ECX */ 595fcf5ef2aSThomas Huth FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 596fcf5ef2aSThomas Huth FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 597fcf5ef2aSThomas Huth FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 59880db491dSJing Liu FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ 599fcf5ef2aSThomas Huth FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 600fcf5ef2aSThomas Huth FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 601fcf5ef2aSThomas Huth FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 6021b3420e1SEduardo Habkost FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ 603b70eec31SBabu Moger FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ 604fcf5ef2aSThomas Huth FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 605fcf5ef2aSThomas Huth FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 606be777326SWanpeng Li FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ 607fcf5ef2aSThomas Huth FEAT_SVM, /* CPUID[8000_000A].EDX */ 608fcf5ef2aSThomas Huth FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 609fcf5ef2aSThomas Huth FEAT_6_EAX, /* CPUID[6].EAX */ 610301e9067SYang Weijiang FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 611301e9067SYang Weijiang FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 612d86f9636SRobert Hoo FEAT_ARCH_CAPABILITIES, 613597360c0SXiaoyao Li FEAT_CORE_CAPABILITY, 614ea39f9b6SLike Xu FEAT_PERF_CAPABILITIES, 61520a78b02SPaolo Bonzini FEAT_VMX_PROCBASED_CTLS, 61620a78b02SPaolo Bonzini FEAT_VMX_SECONDARY_CTLS, 61720a78b02SPaolo Bonzini FEAT_VMX_PINBASED_CTLS, 61820a78b02SPaolo Bonzini FEAT_VMX_EXIT_CTLS, 61920a78b02SPaolo Bonzini FEAT_VMX_ENTRY_CTLS, 62020a78b02SPaolo Bonzini FEAT_VMX_MISC, 62120a78b02SPaolo Bonzini FEAT_VMX_EPT_VPID_CAPS, 62220a78b02SPaolo Bonzini FEAT_VMX_BASIC, 62320a78b02SPaolo Bonzini FEAT_VMX_VMFUNC, 624d1615ea5SLuwei Kang FEAT_14_0_ECX, 6254b841a79SSean Christopherson FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */ 626120ca112SSean Christopherson FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */ 627165981a5SSean Christopherson FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ 628301e9067SYang Weijiang FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */ 629301e9067SYang Weijiang FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ 630eaaa197dSJiaxi Chen FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ 6319dd8b710STao Su FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ 632fcf5ef2aSThomas Huth FEATURE_WORDS, 633fcf5ef2aSThomas Huth } FeatureWord; 634fcf5ef2aSThomas Huth 635ede146c2SPaolo Bonzini typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 63658f7db26SPaolo Bonzini uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 63758f7db26SPaolo Bonzini bool migratable_only); 638fcf5ef2aSThomas Huth 639fcf5ef2aSThomas Huth /* cpuid_features bits */ 640fcf5ef2aSThomas Huth #define CPUID_FP87 (1U << 0) 641fcf5ef2aSThomas Huth #define CPUID_VME (1U << 1) 642fcf5ef2aSThomas Huth #define CPUID_DE (1U << 2) 643fcf5ef2aSThomas Huth #define CPUID_PSE (1U << 3) 644fcf5ef2aSThomas Huth #define CPUID_TSC (1U << 4) 645fcf5ef2aSThomas Huth #define CPUID_MSR (1U << 5) 646fcf5ef2aSThomas Huth #define CPUID_PAE (1U << 6) 647fcf5ef2aSThomas Huth #define CPUID_MCE (1U << 7) 648fcf5ef2aSThomas Huth #define CPUID_CX8 (1U << 8) 649fcf5ef2aSThomas Huth #define CPUID_APIC (1U << 9) 650fcf5ef2aSThomas Huth #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 651fcf5ef2aSThomas Huth #define CPUID_MTRR (1U << 12) 652fcf5ef2aSThomas Huth #define CPUID_PGE (1U << 13) 653fcf5ef2aSThomas Huth #define CPUID_MCA (1U << 14) 654fcf5ef2aSThomas Huth #define CPUID_CMOV (1U << 15) 655fcf5ef2aSThomas Huth #define CPUID_PAT (1U << 16) 656fcf5ef2aSThomas Huth #define CPUID_PSE36 (1U << 17) 657fcf5ef2aSThomas Huth #define CPUID_PN (1U << 18) 658fcf5ef2aSThomas Huth #define CPUID_CLFLUSH (1U << 19) 659fcf5ef2aSThomas Huth #define CPUID_DTS (1U << 21) 660fcf5ef2aSThomas Huth #define CPUID_ACPI (1U << 22) 661fcf5ef2aSThomas Huth #define CPUID_MMX (1U << 23) 662fcf5ef2aSThomas Huth #define CPUID_FXSR (1U << 24) 663fcf5ef2aSThomas Huth #define CPUID_SSE (1U << 25) 664fcf5ef2aSThomas Huth #define CPUID_SSE2 (1U << 26) 665fcf5ef2aSThomas Huth #define CPUID_SS (1U << 27) 666fcf5ef2aSThomas Huth #define CPUID_HT (1U << 28) 667fcf5ef2aSThomas Huth #define CPUID_TM (1U << 29) 668fcf5ef2aSThomas Huth #define CPUID_IA64 (1U << 30) 669fcf5ef2aSThomas Huth #define CPUID_PBE (1U << 31) 670fcf5ef2aSThomas Huth 671fcf5ef2aSThomas Huth #define CPUID_EXT_SSE3 (1U << 0) 672fcf5ef2aSThomas Huth #define CPUID_EXT_PCLMULQDQ (1U << 1) 673fcf5ef2aSThomas Huth #define CPUID_EXT_DTES64 (1U << 2) 674fcf5ef2aSThomas Huth #define CPUID_EXT_MONITOR (1U << 3) 675fcf5ef2aSThomas Huth #define CPUID_EXT_DSCPL (1U << 4) 676fcf5ef2aSThomas Huth #define CPUID_EXT_VMX (1U << 5) 677fcf5ef2aSThomas Huth #define CPUID_EXT_SMX (1U << 6) 678fcf5ef2aSThomas Huth #define CPUID_EXT_EST (1U << 7) 679fcf5ef2aSThomas Huth #define CPUID_EXT_TM2 (1U << 8) 680fcf5ef2aSThomas Huth #define CPUID_EXT_SSSE3 (1U << 9) 681fcf5ef2aSThomas Huth #define CPUID_EXT_CID (1U << 10) 682fcf5ef2aSThomas Huth #define CPUID_EXT_FMA (1U << 12) 683fcf5ef2aSThomas Huth #define CPUID_EXT_CX16 (1U << 13) 684fcf5ef2aSThomas Huth #define CPUID_EXT_XTPR (1U << 14) 685fcf5ef2aSThomas Huth #define CPUID_EXT_PDCM (1U << 15) 686fcf5ef2aSThomas Huth #define CPUID_EXT_PCID (1U << 17) 687fcf5ef2aSThomas Huth #define CPUID_EXT_DCA (1U << 18) 688fcf5ef2aSThomas Huth #define CPUID_EXT_SSE41 (1U << 19) 689fcf5ef2aSThomas Huth #define CPUID_EXT_SSE42 (1U << 20) 690fcf5ef2aSThomas Huth #define CPUID_EXT_X2APIC (1U << 21) 691fcf5ef2aSThomas Huth #define CPUID_EXT_MOVBE (1U << 22) 692fcf5ef2aSThomas Huth #define CPUID_EXT_POPCNT (1U << 23) 693fcf5ef2aSThomas Huth #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 694fcf5ef2aSThomas Huth #define CPUID_EXT_AES (1U << 25) 695fcf5ef2aSThomas Huth #define CPUID_EXT_XSAVE (1U << 26) 696fcf5ef2aSThomas Huth #define CPUID_EXT_OSXSAVE (1U << 27) 697fcf5ef2aSThomas Huth #define CPUID_EXT_AVX (1U << 28) 698fcf5ef2aSThomas Huth #define CPUID_EXT_F16C (1U << 29) 699fcf5ef2aSThomas Huth #define CPUID_EXT_RDRAND (1U << 30) 700fcf5ef2aSThomas Huth #define CPUID_EXT_HYPERVISOR (1U << 31) 701fcf5ef2aSThomas Huth 702fcf5ef2aSThomas Huth #define CPUID_EXT2_FPU (1U << 0) 703fcf5ef2aSThomas Huth #define CPUID_EXT2_VME (1U << 1) 704fcf5ef2aSThomas Huth #define CPUID_EXT2_DE (1U << 2) 705fcf5ef2aSThomas Huth #define CPUID_EXT2_PSE (1U << 3) 706fcf5ef2aSThomas Huth #define CPUID_EXT2_TSC (1U << 4) 707fcf5ef2aSThomas Huth #define CPUID_EXT2_MSR (1U << 5) 708fcf5ef2aSThomas Huth #define CPUID_EXT2_PAE (1U << 6) 709fcf5ef2aSThomas Huth #define CPUID_EXT2_MCE (1U << 7) 710fcf5ef2aSThomas Huth #define CPUID_EXT2_CX8 (1U << 8) 711fcf5ef2aSThomas Huth #define CPUID_EXT2_APIC (1U << 9) 712fcf5ef2aSThomas Huth #define CPUID_EXT2_SYSCALL (1U << 11) 713fcf5ef2aSThomas Huth #define CPUID_EXT2_MTRR (1U << 12) 714fcf5ef2aSThomas Huth #define CPUID_EXT2_PGE (1U << 13) 715fcf5ef2aSThomas Huth #define CPUID_EXT2_MCA (1U << 14) 716fcf5ef2aSThomas Huth #define CPUID_EXT2_CMOV (1U << 15) 717fcf5ef2aSThomas Huth #define CPUID_EXT2_PAT (1U << 16) 718fcf5ef2aSThomas Huth #define CPUID_EXT2_PSE36 (1U << 17) 719fcf5ef2aSThomas Huth #define CPUID_EXT2_MP (1U << 19) 720fcf5ef2aSThomas Huth #define CPUID_EXT2_NX (1U << 20) 721fcf5ef2aSThomas Huth #define CPUID_EXT2_MMXEXT (1U << 22) 722fcf5ef2aSThomas Huth #define CPUID_EXT2_MMX (1U << 23) 723fcf5ef2aSThomas Huth #define CPUID_EXT2_FXSR (1U << 24) 724fcf5ef2aSThomas Huth #define CPUID_EXT2_FFXSR (1U << 25) 725fcf5ef2aSThomas Huth #define CPUID_EXT2_PDPE1GB (1U << 26) 726fcf5ef2aSThomas Huth #define CPUID_EXT2_RDTSCP (1U << 27) 727fcf5ef2aSThomas Huth #define CPUID_EXT2_LM (1U << 29) 728fcf5ef2aSThomas Huth #define CPUID_EXT2_3DNOWEXT (1U << 30) 729fcf5ef2aSThomas Huth #define CPUID_EXT2_3DNOW (1U << 31) 730fcf5ef2aSThomas Huth 731bad5cfcdSMichael Tokarev /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */ 732fcf5ef2aSThomas Huth #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 733fcf5ef2aSThomas Huth CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 734fcf5ef2aSThomas Huth CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 735fcf5ef2aSThomas Huth CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 736fcf5ef2aSThomas Huth CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 737fcf5ef2aSThomas Huth CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 738fcf5ef2aSThomas Huth CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 739fcf5ef2aSThomas Huth CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 740fcf5ef2aSThomas Huth CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 741fcf5ef2aSThomas Huth 742fcf5ef2aSThomas Huth #define CPUID_EXT3_LAHF_LM (1U << 0) 743fcf5ef2aSThomas Huth #define CPUID_EXT3_CMP_LEG (1U << 1) 744fcf5ef2aSThomas Huth #define CPUID_EXT3_SVM (1U << 2) 745fcf5ef2aSThomas Huth #define CPUID_EXT3_EXTAPIC (1U << 3) 746fcf5ef2aSThomas Huth #define CPUID_EXT3_CR8LEG (1U << 4) 747fcf5ef2aSThomas Huth #define CPUID_EXT3_ABM (1U << 5) 748fcf5ef2aSThomas Huth #define CPUID_EXT3_SSE4A (1U << 6) 749fcf5ef2aSThomas Huth #define CPUID_EXT3_MISALIGNSSE (1U << 7) 750fcf5ef2aSThomas Huth #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 751fcf5ef2aSThomas Huth #define CPUID_EXT3_OSVW (1U << 9) 752fcf5ef2aSThomas Huth #define CPUID_EXT3_IBS (1U << 10) 753fcf5ef2aSThomas Huth #define CPUID_EXT3_XOP (1U << 11) 754fcf5ef2aSThomas Huth #define CPUID_EXT3_SKINIT (1U << 12) 755fcf5ef2aSThomas Huth #define CPUID_EXT3_WDT (1U << 13) 756fcf5ef2aSThomas Huth #define CPUID_EXT3_LWP (1U << 15) 757fcf5ef2aSThomas Huth #define CPUID_EXT3_FMA4 (1U << 16) 758fcf5ef2aSThomas Huth #define CPUID_EXT3_TCE (1U << 17) 759fcf5ef2aSThomas Huth #define CPUID_EXT3_NODEID (1U << 19) 760fcf5ef2aSThomas Huth #define CPUID_EXT3_TBM (1U << 21) 761fcf5ef2aSThomas Huth #define CPUID_EXT3_TOPOEXT (1U << 22) 762fcf5ef2aSThomas Huth #define CPUID_EXT3_PERFCORE (1U << 23) 763fcf5ef2aSThomas Huth #define CPUID_EXT3_PERFNB (1U << 24) 764fcf5ef2aSThomas Huth 765fcf5ef2aSThomas Huth #define CPUID_SVM_NPT (1U << 0) 766fcf5ef2aSThomas Huth #define CPUID_SVM_LBRV (1U << 1) 767fcf5ef2aSThomas Huth #define CPUID_SVM_SVMLOCK (1U << 2) 768fcf5ef2aSThomas Huth #define CPUID_SVM_NRIPSAVE (1U << 3) 769fcf5ef2aSThomas Huth #define CPUID_SVM_TSCSCALE (1U << 4) 770fcf5ef2aSThomas Huth #define CPUID_SVM_VMCBCLEAN (1U << 5) 771fcf5ef2aSThomas Huth #define CPUID_SVM_FLUSHASID (1U << 6) 772fcf5ef2aSThomas Huth #define CPUID_SVM_DECODEASSIST (1U << 7) 773fcf5ef2aSThomas Huth #define CPUID_SVM_PAUSEFILTER (1U << 10) 774fcf5ef2aSThomas Huth #define CPUID_SVM_PFTHRESHOLD (1U << 12) 7755447089cSWei Huang #define CPUID_SVM_AVIC (1U << 13) 7765447089cSWei Huang #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) 7775447089cSWei Huang #define CPUID_SVM_VGIF (1U << 16) 77862a798d4SBabu Moger #define CPUID_SVM_VNMI (1U << 25) 7795447089cSWei Huang #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) 780fcf5ef2aSThomas Huth 781f2be0bebSTao Xu /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 782fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 7835c76b651SSean Christopherson /* Support SGX */ 7845c76b651SSean Christopherson #define CPUID_7_0_EBX_SGX (1U << 2) 785f2be0bebSTao Xu /* 1st Group of Advanced Bit Manipulation Extensions */ 786fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_BMI1 (1U << 3) 787f2be0bebSTao Xu /* Hardware Lock Elision */ 788fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_HLE (1U << 4) 789f2be0bebSTao Xu /* Intel Advanced Vector Extensions 2 */ 790fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX2 (1U << 5) 791f2be0bebSTao Xu /* Supervisor-mode Execution Prevention */ 792fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_SMEP (1U << 7) 793f2be0bebSTao Xu /* 2nd Group of Advanced Bit Manipulation Extensions */ 794fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_BMI2 (1U << 8) 795f2be0bebSTao Xu /* Enhanced REP MOVSB/STOSB */ 796fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_ERMS (1U << 9) 797f2be0bebSTao Xu /* Invalidate Process-Context Identifier */ 798fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_INVPCID (1U << 10) 799f2be0bebSTao Xu /* Restricted Transactional Memory */ 800fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_RTM (1U << 11) 801f2be0bebSTao Xu /* Memory Protection Extension */ 802fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_MPX (1U << 14) 803f2be0bebSTao Xu /* AVX-512 Foundation */ 804f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512F (1U << 16) 805f2be0bebSTao Xu /* AVX-512 Doubleword & Quadword Instruction */ 806f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512DQ (1U << 17) 807f2be0bebSTao Xu /* Read Random SEED */ 808fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_RDSEED (1U << 18) 809f2be0bebSTao Xu /* ADCX and ADOX instructions */ 810fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_ADX (1U << 19) 811f2be0bebSTao Xu /* Supervisor Mode Access Prevention */ 812fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_SMAP (1U << 20) 813f2be0bebSTao Xu /* AVX-512 Integer Fused Multiply Add */ 814f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) 815f2be0bebSTao Xu /* Persistent Commit */ 816f2be0bebSTao Xu #define CPUID_7_0_EBX_PCOMMIT (1U << 22) 817f2be0bebSTao Xu /* Flush a Cache Line Optimized */ 818f2be0bebSTao Xu #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) 819f2be0bebSTao Xu /* Cache Line Write Back */ 820f2be0bebSTao Xu #define CPUID_7_0_EBX_CLWB (1U << 24) 821f2be0bebSTao Xu /* Intel Processor Trace */ 822f2be0bebSTao Xu #define CPUID_7_0_EBX_INTEL_PT (1U << 25) 823f2be0bebSTao Xu /* AVX-512 Prefetch */ 824f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512PF (1U << 26) 825f2be0bebSTao Xu /* AVX-512 Exponential and Reciprocal */ 826f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512ER (1U << 27) 827f2be0bebSTao Xu /* AVX-512 Conflict Detection */ 828f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512CD (1U << 28) 829f2be0bebSTao Xu /* SHA1/SHA256 Instruction Extensions */ 830f2be0bebSTao Xu #define CPUID_7_0_EBX_SHA_NI (1U << 29) 831f2be0bebSTao Xu /* AVX-512 Byte and Word Instructions */ 832f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512BW (1U << 30) 833f2be0bebSTao Xu /* AVX-512 Vector Length Extensions */ 834f2be0bebSTao Xu #define CPUID_7_0_EBX_AVX512VL (1U << 31) 835fcf5ef2aSThomas Huth 836f2be0bebSTao Xu /* AVX-512 Vector Byte Manipulation Instruction */ 837e7694a5eSTao Xu #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) 838f2be0bebSTao Xu /* User-Mode Instruction Prevention */ 839fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_UMIP (1U << 2) 840f2be0bebSTao Xu /* Protection Keys for User-mode Pages */ 841fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_PKU (1U << 3) 842f2be0bebSTao Xu /* OS Enable Protection Keys */ 843fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_OSPKE (1U << 4) 84467192a29STao Xu /* UMONITOR/UMWAIT/TPAUSE Instructions */ 84567192a29STao Xu #define CPUID_7_0_ECX_WAITPKG (1U << 5) 846f2be0bebSTao Xu /* Additional AVX-512 Vector Byte Manipulation Instruction */ 847e7694a5eSTao Xu #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) 848f2be0bebSTao Xu /* Galois Field New Instructions */ 849aff9e6e4SYang Zhong #define CPUID_7_0_ECX_GFNI (1U << 8) 850f2be0bebSTao Xu /* Vector AES Instructions */ 851aff9e6e4SYang Zhong #define CPUID_7_0_ECX_VAES (1U << 9) 852f2be0bebSTao Xu /* Carry-Less Multiplication Quadword */ 853aff9e6e4SYang Zhong #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) 854f2be0bebSTao Xu /* Vector Neural Network Instructions */ 855aff9e6e4SYang Zhong #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) 856f2be0bebSTao Xu /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 857aff9e6e4SYang Zhong #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) 858f2be0bebSTao Xu /* POPCNT for vectors of DW/QW */ 859f2be0bebSTao Xu #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) 860f2be0bebSTao Xu /* 5-level Page Tables */ 8616c7c3c21SKirill A. Shutemov #define CPUID_7_0_ECX_LA57 (1U << 16) 862f2be0bebSTao Xu /* Read Processor ID */ 863fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_RDPID (1U << 22) 86406e878b4SChenyi Qiang /* Bus Lock Debug Exception */ 86506e878b4SChenyi Qiang #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) 866f2be0bebSTao Xu /* Cache Line Demote Instruction */ 867f2be0bebSTao Xu #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) 868f2be0bebSTao Xu /* Move Doubleword as Direct Store Instruction */ 869f2be0bebSTao Xu #define CPUID_7_0_ECX_MOVDIRI (1U << 27) 870f2be0bebSTao Xu /* Move 64 Bytes as Direct Store Instruction */ 871f2be0bebSTao Xu #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) 8725c76b651SSean Christopherson /* Support SGX Launch Control */ 8735c76b651SSean Christopherson #define CPUID_7_0_ECX_SGX_LC (1U << 30) 874e7e7bdabSPaolo Bonzini /* Protection Keys for Supervisor-mode Pages */ 875e7e7bdabSPaolo Bonzini #define CPUID_7_0_ECX_PKS (1U << 31) 876fcf5ef2aSThomas Huth 877f2be0bebSTao Xu /* AVX512 Neural Network Instructions */ 878f2be0bebSTao Xu #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) 879f2be0bebSTao Xu /* AVX512 Multiply Accumulation Single Precision */ 880f2be0bebSTao Xu #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) 8815cb287d2SChenyi Qiang /* Fast Short Rep Mov */ 8825cb287d2SChenyi Qiang #define CPUID_7_0_EDX_FSRM (1U << 4) 883353f98c9SCathy Zhang /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ 884353f98c9SCathy Zhang #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 8855dd13f2aSCathy Zhang /* SERIALIZE instruction */ 8865dd13f2aSCathy Zhang #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 887b3c7344eSCathy Zhang /* TSX Suspend Load Address Tracking instruction */ 888b3c7344eSCathy Zhang #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 88910f0abcbSYang Weijiang /* Architectural LBRs */ 89010f0abcbSYang Weijiang #define CPUID_7_0_EDX_ARCH_LBR (1U << 19) 8917eb061b0SWang, Lei /* AMX_BF16 instruction */ 8927eb061b0SWang, Lei #define CPUID_7_0_EDX_AMX_BF16 (1U << 22) 89340399ecbSCathy Zhang /* AVX512_FP16 instruction */ 89440399ecbSCathy Zhang #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) 8951f16764fSJing Liu /* AMX tile (two-dimensional register) */ 8961f16764fSJing Liu #define CPUID_7_0_EDX_AMX_TILE (1U << 24) 8977eb061b0SWang, Lei /* AMX_INT8 instruction */ 8987eb061b0SWang, Lei #define CPUID_7_0_EDX_AMX_INT8 (1U << 25) 899f2be0bebSTao Xu /* Speculation Control */ 900f2be0bebSTao Xu #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 9015af514d0SCathy Zhang /* Single Thread Indirect Branch Predictors */ 9025af514d0SCathy Zhang #define CPUID_7_0_EDX_STIBP (1U << 27) 9030e7e3bf1SEmanuele Giuseppe Esposito /* Flush L1D cache */ 9040e7e3bf1SEmanuele Giuseppe Esposito #define CPUID_7_0_EDX_FLUSH_L1D (1U << 28) 905f2be0bebSTao Xu /* Arch Capabilities */ 906f2be0bebSTao Xu #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) 907f2be0bebSTao Xu /* Core Capability */ 908f2be0bebSTao Xu #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) 909f2be0bebSTao Xu /* Speculative Store Bypass Disable */ 910f2be0bebSTao Xu #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) 911fcf5ef2aSThomas Huth 912c1826ea6SYang Zhong /* AVX VNNI Instruction */ 913c1826ea6SYang Zhong #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) 914f2be0bebSTao Xu /* AVX512 BFloat16 Instruction */ 915f2be0bebSTao Xu #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) 916a9ce107fSJiaxi Chen /* CMPCCXADD Instructions */ 917a9ce107fSJiaxi Chen #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) 91858794f64SPaolo Bonzini /* Fast Zero REP MOVS */ 91958794f64SPaolo Bonzini #define CPUID_7_1_EAX_FZRM (1U << 10) 92058794f64SPaolo Bonzini /* Fast Short REP STOS */ 92158794f64SPaolo Bonzini #define CPUID_7_1_EAX_FSRS (1U << 11) 92258794f64SPaolo Bonzini /* Fast Short REP CMPS/SCAS */ 92358794f64SPaolo Bonzini #define CPUID_7_1_EAX_FSRC (1U << 12) 92499ed8445SJiaxi Chen /* Support Tile Computational Operations on FP16 Numbers */ 92599ed8445SJiaxi Chen #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) 926a957a884SJiaxi Chen /* Support for VPMADD52[H,L]UQ */ 927a957a884SJiaxi Chen #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) 92858794f64SPaolo Bonzini 929eaaa197dSJiaxi Chen /* Support for VPDPB[SU,UU,SS]D[,S] */ 930eaaa197dSJiaxi Chen #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) 931ecd2e6caSJiaxi Chen /* AVX NE CONVERT Instructions */ 932ecd2e6caSJiaxi Chen #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) 9333e76bafbSTao Su /* AMX COMPLEX Instructions */ 9343e76bafbSTao Su #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8) 935d1a11115SJiaxi Chen /* PREFETCHIT0/1 Instructions */ 936d1a11115SJiaxi Chen #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) 937eaaa197dSJiaxi Chen 9389dd8b710STao Su /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ 9399dd8b710STao Su #define CPUID_7_2_EDX_MCDT_NO (1U << 5) 9409dd8b710STao Su 941cdec2b75SZeng Guang /* XFD Extend Feature Disabled */ 942cdec2b75SZeng Guang #define CPUID_D_1_EAX_XFD (1U << 4) 94380db491dSJing Liu 944d1615ea5SLuwei Kang /* Packets which contain IP payload have LIP values */ 945d1615ea5SLuwei Kang #define CPUID_14_0_ECX_LIP (1U << 31) 946d1615ea5SLuwei Kang 947f2be0bebSTao Xu /* CLZERO instruction */ 948f2be0bebSTao Xu #define CPUID_8000_0008_EBX_CLZERO (1U << 0) 949f2be0bebSTao Xu /* Always save/restore FP error pointers */ 950f2be0bebSTao Xu #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) 951f2be0bebSTao Xu /* Write back and do not invalidate cache */ 952f2be0bebSTao Xu #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) 953f2be0bebSTao Xu /* Indirect Branch Prediction Barrier */ 954f2be0bebSTao Xu #define CPUID_8000_0008_EBX_IBPB (1U << 12) 955623972ceSBabu Moger /* Indirect Branch Restricted Speculation */ 956623972ceSBabu Moger #define CPUID_8000_0008_EBX_IBRS (1U << 14) 957143c30d4SMoger, Babu /* Single Thread Indirect Branch Predictors */ 958143c30d4SMoger, Babu #define CPUID_8000_0008_EBX_STIBP (1U << 15) 959bb039a23SBabu Moger /* STIBP mode has enhanced performance and may be left always on */ 960bb039a23SBabu Moger #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17) 961623972ceSBabu Moger /* Speculative Store Bypass Disable */ 962623972ceSBabu Moger #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) 963bb039a23SBabu Moger /* Predictive Store Forwarding Disable */ 964bb039a23SBabu Moger #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) 9651b3420e1SEduardo Habkost 966b70eec31SBabu Moger /* Processor ignores nested data breakpoints */ 967b70eec31SBabu Moger #define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0) 968b70eec31SBabu Moger /* LFENCE is always serializing */ 969b70eec31SBabu Moger #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) 970b70eec31SBabu Moger /* Null Selector Clears Base */ 971b70eec31SBabu Moger #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) 97262a798d4SBabu Moger /* Automatic IBRS */ 97362a798d4SBabu Moger #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) 974b70eec31SBabu Moger 975fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVEOPT (1U << 0) 976fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVEC (1U << 1) 977fcf5ef2aSThomas Huth #define CPUID_XSAVE_XGETBV1 (1U << 2) 978fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVES (1U << 3) 979fcf5ef2aSThomas Huth 980fcf5ef2aSThomas Huth #define CPUID_6_EAX_ARAT (1U << 2) 981fcf5ef2aSThomas Huth 982fcf5ef2aSThomas Huth /* CPUID[0x80000007].EDX flags: */ 983fcf5ef2aSThomas Huth #define CPUID_APM_INVTSC (1U << 8) 984fcf5ef2aSThomas Huth 985fcf5ef2aSThomas Huth #define CPUID_VENDOR_SZ 12 986fcf5ef2aSThomas Huth 987fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 988fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 989fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 990fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL "GenuineIntel" 991fcf5ef2aSThomas Huth 992fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 993fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 994fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 995fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD "AuthenticAMD" 996fcf5ef2aSThomas Huth 997fcf5ef2aSThomas Huth #define CPUID_VENDOR_VIA "CentaurHauls" 998fcf5ef2aSThomas Huth 9998d031cecSPu Wen #define CPUID_VENDOR_HYGON "HygonGenuine" 10008d031cecSPu Wen 100118ab37baSLiran Alon #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ 100218ab37baSLiran Alon (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ 100318ab37baSLiran Alon (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) 100418ab37baSLiran Alon #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ 100518ab37baSLiran Alon (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ 100618ab37baSLiran Alon (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) 100718ab37baSLiran Alon 1008fcf5ef2aSThomas Huth #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 1009fcf5ef2aSThomas Huth #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 1010fcf5ef2aSThomas Huth 1011fcf5ef2aSThomas Huth /* CPUID[0xB].ECX level types */ 1012fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 1013fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 1014fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 1015a94e1428SLike Xu #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) 1016fcf5ef2aSThomas Huth 1017d86f9636SRobert Hoo /* MSR Feature Bits */ 1018d86f9636SRobert Hoo #define MSR_ARCH_CAP_RDCL_NO (1U << 0) 1019d86f9636SRobert Hoo #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) 1020d86f9636SRobert Hoo #define MSR_ARCH_CAP_RSBA (1U << 2) 1021d86f9636SRobert Hoo #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) 1022d86f9636SRobert Hoo #define MSR_ARCH_CAP_SSB_NO (1U << 4) 102377b168d2SCathy Zhang #define MSR_ARCH_CAP_MDS_NO (1U << 5) 10246c997b4aSXiaoyao Li #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) 10256c997b4aSXiaoyao Li #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) 10266c997b4aSXiaoyao Li #define MSR_ARCH_CAP_TAA_NO (1U << 8) 10276c43ec3bSTao Su #define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13) 10286c43ec3bSTao Su #define MSR_ARCH_CAP_FBSDP_NO (1U << 14) 10296c43ec3bSTao Su #define MSR_ARCH_CAP_PSDP_NO (1U << 15) 103022e1094cSEmanuele Giuseppe Esposito #define MSR_ARCH_CAP_FB_CLEAR (1U << 17) 10316c43ec3bSTao Su #define MSR_ARCH_CAP_PBRSB_NO (1U << 24) 1032d86f9636SRobert Hoo 1033597360c0SXiaoyao Li #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) 1034597360c0SXiaoyao Li 1035704798adSPaolo Bonzini /* VMX MSR features */ 1036704798adSPaolo Bonzini #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull 1037704798adSPaolo Bonzini #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) 1038704798adSPaolo Bonzini #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) 1039704798adSPaolo Bonzini #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) 1040704798adSPaolo Bonzini #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) 1041704798adSPaolo Bonzini #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) 10420c49c918SPaolo Bonzini #define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56) 1043704798adSPaolo Bonzini 1044704798adSPaolo Bonzini #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full 1045704798adSPaolo Bonzini #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) 1046704798adSPaolo Bonzini #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) 1047704798adSPaolo Bonzini #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) 1048704798adSPaolo Bonzini #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 1049704798adSPaolo Bonzini #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull 1050704798adSPaolo Bonzini #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) 1051704798adSPaolo Bonzini #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) 1052704798adSPaolo Bonzini 1053704798adSPaolo Bonzini #define MSR_VMX_EPT_EXECONLY (1ULL << 0) 1054704798adSPaolo Bonzini #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) 1055704798adSPaolo Bonzini #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) 1056704798adSPaolo Bonzini #define MSR_VMX_EPT_UC (1ULL << 8) 1057704798adSPaolo Bonzini #define MSR_VMX_EPT_WB (1ULL << 14) 1058704798adSPaolo Bonzini #define MSR_VMX_EPT_2MB (1ULL << 16) 1059704798adSPaolo Bonzini #define MSR_VMX_EPT_1GB (1ULL << 17) 1060704798adSPaolo Bonzini #define MSR_VMX_EPT_INVEPT (1ULL << 20) 1061704798adSPaolo Bonzini #define MSR_VMX_EPT_AD_BITS (1ULL << 21) 1062704798adSPaolo Bonzini #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) 1063704798adSPaolo Bonzini #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) 1064704798adSPaolo Bonzini #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) 1065704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID (1ULL << 32) 1066704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) 1067704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) 1068704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) 1069704798adSPaolo Bonzini #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) 1070704798adSPaolo Bonzini 1071704798adSPaolo Bonzini #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) 1072704798adSPaolo Bonzini 1073704798adSPaolo Bonzini 1074704798adSPaolo Bonzini /* VMX controls */ 1075704798adSPaolo Bonzini #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 1076704798adSPaolo Bonzini #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 1077704798adSPaolo Bonzini #define VMX_CPU_BASED_HLT_EXITING 0x00000080 1078704798adSPaolo Bonzini #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 1079704798adSPaolo Bonzini #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 1080704798adSPaolo Bonzini #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 1081704798adSPaolo Bonzini #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 1082704798adSPaolo Bonzini #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 1083704798adSPaolo Bonzini #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 1084704798adSPaolo Bonzini #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 1085704798adSPaolo Bonzini #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 1086704798adSPaolo Bonzini #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 1087704798adSPaolo Bonzini #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 1088704798adSPaolo Bonzini #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 1089704798adSPaolo Bonzini #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 1090704798adSPaolo Bonzini #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 1091704798adSPaolo Bonzini #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 1092704798adSPaolo Bonzini #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 1093704798adSPaolo Bonzini #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 1094704798adSPaolo Bonzini #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 1095704798adSPaolo Bonzini #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 1096704798adSPaolo Bonzini 1097704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 1098704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 1099704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_DESC 0x00000004 1100704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 1101704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 1102704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 1103704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 1104704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 1105704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 1106704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 1107704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 1108704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 1109704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 1110704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 1111704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 1112704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 1113704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 1114704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 1115704798adSPaolo Bonzini #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 11169ce8af4dSPaolo Bonzini #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000 111733cc8826SAke Koomsin #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000 1118704798adSPaolo Bonzini 1119704798adSPaolo Bonzini #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 1120704798adSPaolo Bonzini #define VMX_PIN_BASED_NMI_EXITING 0x00000008 1121704798adSPaolo Bonzini #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 1122704798adSPaolo Bonzini #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 1123704798adSPaolo Bonzini #define VMX_PIN_BASED_POSTED_INTR 0x00000080 1124704798adSPaolo Bonzini 1125704798adSPaolo Bonzini #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 1126704798adSPaolo Bonzini #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 1127704798adSPaolo Bonzini #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 1128704798adSPaolo Bonzini #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 1129704798adSPaolo Bonzini #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 1130704798adSPaolo Bonzini #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 1131704798adSPaolo Bonzini #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 1132704798adSPaolo Bonzini #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 1133704798adSPaolo Bonzini #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 1134704798adSPaolo Bonzini #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 1135704798adSPaolo Bonzini #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 1136704798adSPaolo Bonzini #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 113752a44ad2SChenyi Qiang #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 1138704798adSPaolo Bonzini 1139704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 1140704798adSPaolo Bonzini #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 1141704798adSPaolo Bonzini #define VMX_VM_ENTRY_SMM 0x00000400 1142704798adSPaolo Bonzini #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 1143704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 1144704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 1145704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 1146704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 1147704798adSPaolo Bonzini #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 1148704798adSPaolo Bonzini #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 114952a44ad2SChenyi Qiang #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 1150704798adSPaolo Bonzini 11512d384d7cSVitaly Kuznetsov /* Supported Hyper-V Enlightenments */ 11522d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_RELAXED 0 11532d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_VAPIC 1 11542d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_TIME 2 11552d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_CRASH 3 11562d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_RESET 4 11572d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_VPINDEX 5 11582d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_RUNTIME 6 11592d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_SYNIC 7 11602d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_STIMER 8 11612d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_FREQUENCIES 9 11622d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_REENLIGHTENMENT 10 11632d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_TLBFLUSH 11 11642d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_EVMCS 12 11652d384d7cSVitaly Kuznetsov #define HYPERV_FEAT_IPI 13 1166128531d9SVitaly Kuznetsov #define HYPERV_FEAT_STIMER_DIRECT 14 1167e1f9a8e8SVitaly Kuznetsov #define HYPERV_FEAT_AVIC 15 116873d24074SJon Doron #define HYPERV_FEAT_SYNDBG 16 1169869840d2SVitaly Kuznetsov #define HYPERV_FEAT_MSR_BITMAP 17 11709411e8b6SVitaly Kuznetsov #define HYPERV_FEAT_XMM_INPUT 18 1171aa6bb5faSVitaly Kuznetsov #define HYPERV_FEAT_TLBFLUSH_EXT 19 11723aae0854SVitaly Kuznetsov #define HYPERV_FEAT_TLBFLUSH_DIRECT 20 11732d384d7cSVitaly Kuznetsov 1174f701c082SVitaly Kuznetsov #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY 1175f701c082SVitaly Kuznetsov #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF 1176fcf5ef2aSThomas Huth #endif 1177fcf5ef2aSThomas Huth 1178fcf5ef2aSThomas Huth #define EXCP00_DIVZ 0 1179fcf5ef2aSThomas Huth #define EXCP01_DB 1 1180fcf5ef2aSThomas Huth #define EXCP02_NMI 2 1181fcf5ef2aSThomas Huth #define EXCP03_INT3 3 1182fcf5ef2aSThomas Huth #define EXCP04_INTO 4 1183fcf5ef2aSThomas Huth #define EXCP05_BOUND 5 1184fcf5ef2aSThomas Huth #define EXCP06_ILLOP 6 1185fcf5ef2aSThomas Huth #define EXCP07_PREX 7 1186fcf5ef2aSThomas Huth #define EXCP08_DBLE 8 1187fcf5ef2aSThomas Huth #define EXCP09_XERR 9 1188fcf5ef2aSThomas Huth #define EXCP0A_TSS 10 1189fcf5ef2aSThomas Huth #define EXCP0B_NOSEG 11 1190fcf5ef2aSThomas Huth #define EXCP0C_STACK 12 1191fcf5ef2aSThomas Huth #define EXCP0D_GPF 13 1192fcf5ef2aSThomas Huth #define EXCP0E_PAGE 14 1193fcf5ef2aSThomas Huth #define EXCP10_COPR 16 1194fcf5ef2aSThomas Huth #define EXCP11_ALGN 17 1195fcf5ef2aSThomas Huth #define EXCP12_MCHK 18 1196fcf5ef2aSThomas Huth 119762846089SRichard Henderson #define EXCP_VMEXIT 0x100 /* only for system emulation */ 119862846089SRichard Henderson #define EXCP_SYSCALL 0x101 /* only for user emulation */ 1199b26491b4SRichard Henderson #define EXCP_VSYSCALL 0x102 /* only for user emulation */ 1200fcf5ef2aSThomas Huth 1201fcf5ef2aSThomas Huth /* i386-specific interrupt pending bits. */ 1202fcf5ef2aSThomas Huth #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 1203fcf5ef2aSThomas Huth #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 1204fcf5ef2aSThomas Huth #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 1205fcf5ef2aSThomas Huth #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 1206fcf5ef2aSThomas Huth #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 1207fcf5ef2aSThomas Huth #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 1208fcf5ef2aSThomas Huth #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 1209fcf5ef2aSThomas Huth 1210fcf5ef2aSThomas Huth /* Use a clearer name for this. */ 1211fcf5ef2aSThomas Huth #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 1212fcf5ef2aSThomas Huth 1213fcf5ef2aSThomas Huth /* Instead of computing the condition codes after each x86 instruction, 1214fcf5ef2aSThomas Huth * QEMU just stores one operand (called CC_SRC), the result 1215fcf5ef2aSThomas Huth * (called CC_DST) and the type of operation (called CC_OP). When the 1216fcf5ef2aSThomas Huth * condition codes are needed, the condition codes can be calculated 1217fcf5ef2aSThomas Huth * using this information. Condition codes are not generated if they 1218fcf5ef2aSThomas Huth * are only needed for conditional branches. 1219fcf5ef2aSThomas Huth */ 1220fcf5ef2aSThomas Huth typedef enum { 1221fcf5ef2aSThomas Huth CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 1222fcf5ef2aSThomas Huth CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 1223fcf5ef2aSThomas Huth 1224fcf5ef2aSThomas Huth CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 1225fcf5ef2aSThomas Huth CC_OP_MULW, 1226fcf5ef2aSThomas Huth CC_OP_MULL, 1227fcf5ef2aSThomas Huth CC_OP_MULQ, 1228fcf5ef2aSThomas Huth 1229fcf5ef2aSThomas Huth CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1230fcf5ef2aSThomas Huth CC_OP_ADDW, 1231fcf5ef2aSThomas Huth CC_OP_ADDL, 1232fcf5ef2aSThomas Huth CC_OP_ADDQ, 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1235fcf5ef2aSThomas Huth CC_OP_ADCW, 1236fcf5ef2aSThomas Huth CC_OP_ADCL, 1237fcf5ef2aSThomas Huth CC_OP_ADCQ, 1238fcf5ef2aSThomas Huth 1239fcf5ef2aSThomas Huth CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1240fcf5ef2aSThomas Huth CC_OP_SUBW, 1241fcf5ef2aSThomas Huth CC_OP_SUBL, 1242fcf5ef2aSThomas Huth CC_OP_SUBQ, 1243fcf5ef2aSThomas Huth 1244fcf5ef2aSThomas Huth CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 1245fcf5ef2aSThomas Huth CC_OP_SBBW, 1246fcf5ef2aSThomas Huth CC_OP_SBBL, 1247fcf5ef2aSThomas Huth CC_OP_SBBQ, 1248fcf5ef2aSThomas Huth 1249fcf5ef2aSThomas Huth CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 1250fcf5ef2aSThomas Huth CC_OP_LOGICW, 1251fcf5ef2aSThomas Huth CC_OP_LOGICL, 1252fcf5ef2aSThomas Huth CC_OP_LOGICQ, 1253fcf5ef2aSThomas Huth 1254fcf5ef2aSThomas Huth CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1255fcf5ef2aSThomas Huth CC_OP_INCW, 1256fcf5ef2aSThomas Huth CC_OP_INCL, 1257fcf5ef2aSThomas Huth CC_OP_INCQ, 1258fcf5ef2aSThomas Huth 1259fcf5ef2aSThomas Huth CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 1260fcf5ef2aSThomas Huth CC_OP_DECW, 1261fcf5ef2aSThomas Huth CC_OP_DECL, 1262fcf5ef2aSThomas Huth CC_OP_DECQ, 1263fcf5ef2aSThomas Huth 1264fcf5ef2aSThomas Huth CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 1265fcf5ef2aSThomas Huth CC_OP_SHLW, 1266fcf5ef2aSThomas Huth CC_OP_SHLL, 1267fcf5ef2aSThomas Huth CC_OP_SHLQ, 1268fcf5ef2aSThomas Huth 1269fcf5ef2aSThomas Huth CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 1270fcf5ef2aSThomas Huth CC_OP_SARW, 1271fcf5ef2aSThomas Huth CC_OP_SARL, 1272fcf5ef2aSThomas Huth CC_OP_SARQ, 1273fcf5ef2aSThomas Huth 1274fcf5ef2aSThomas Huth CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 1275fcf5ef2aSThomas Huth CC_OP_BMILGW, 1276fcf5ef2aSThomas Huth CC_OP_BMILGL, 1277fcf5ef2aSThomas Huth CC_OP_BMILGQ, 1278fcf5ef2aSThomas Huth 1279fcf5ef2aSThomas Huth CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 1280fcf5ef2aSThomas Huth CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 1281fcf5ef2aSThomas Huth CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 1282fcf5ef2aSThomas Huth 1283fcf5ef2aSThomas Huth CC_OP_CLR, /* Z set, all other flags clear. */ 12844885c3c4SRichard Henderson CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 1285fcf5ef2aSThomas Huth 1286fcf5ef2aSThomas Huth CC_OP_NB, 1287fcf5ef2aSThomas Huth } CCOp; 1288fcf5ef2aSThomas Huth 1289fcf5ef2aSThomas Huth typedef struct SegmentCache { 1290fcf5ef2aSThomas Huth uint32_t selector; 1291fcf5ef2aSThomas Huth target_ulong base; 1292fcf5ef2aSThomas Huth uint32_t limit; 1293fcf5ef2aSThomas Huth uint32_t flags; 1294fcf5ef2aSThomas Huth } SegmentCache; 1295fcf5ef2aSThomas Huth 129675f107a8SRichard Henderson typedef union MMXReg { 129775f107a8SRichard Henderson uint8_t _b_MMXReg[64 / 8]; 129875f107a8SRichard Henderson uint16_t _w_MMXReg[64 / 16]; 129975f107a8SRichard Henderson uint32_t _l_MMXReg[64 / 32]; 130075f107a8SRichard Henderson uint64_t _q_MMXReg[64 / 64]; 130175f107a8SRichard Henderson float32 _s_MMXReg[64 / 32]; 130275f107a8SRichard Henderson float64 _d_MMXReg[64 / 64]; 130375f107a8SRichard Henderson } MMXReg; 1304fcf5ef2aSThomas Huth 130575f107a8SRichard Henderson typedef union XMMReg { 130675f107a8SRichard Henderson uint64_t _q_XMMReg[128 / 64]; 130775f107a8SRichard Henderson } XMMReg; 130875f107a8SRichard Henderson 130975f107a8SRichard Henderson typedef union YMMReg { 131075f107a8SRichard Henderson uint64_t _q_YMMReg[256 / 64]; 131175f107a8SRichard Henderson XMMReg _x_YMMReg[256 / 128]; 131275f107a8SRichard Henderson } YMMReg; 131375f107a8SRichard Henderson 131475f107a8SRichard Henderson typedef union ZMMReg { 131575f107a8SRichard Henderson uint8_t _b_ZMMReg[512 / 8]; 131675f107a8SRichard Henderson uint16_t _w_ZMMReg[512 / 16]; 131775f107a8SRichard Henderson uint32_t _l_ZMMReg[512 / 32]; 131875f107a8SRichard Henderson uint64_t _q_ZMMReg[512 / 64]; 1319cf5ec664SPaolo Bonzini float16 _h_ZMMReg[512 / 16]; 132075f107a8SRichard Henderson float32 _s_ZMMReg[512 / 32]; 132175f107a8SRichard Henderson float64 _d_ZMMReg[512 / 64]; 132275f107a8SRichard Henderson XMMReg _x_ZMMReg[512 / 128]; 132375f107a8SRichard Henderson YMMReg _y_ZMMReg[512 / 256]; 132475f107a8SRichard Henderson } ZMMReg; 1325fcf5ef2aSThomas Huth 1326fcf5ef2aSThomas Huth typedef struct BNDReg { 1327fcf5ef2aSThomas Huth uint64_t lb; 1328fcf5ef2aSThomas Huth uint64_t ub; 1329fcf5ef2aSThomas Huth } BNDReg; 1330fcf5ef2aSThomas Huth 1331fcf5ef2aSThomas Huth typedef struct BNDCSReg { 1332fcf5ef2aSThomas Huth uint64_t cfgu; 1333fcf5ef2aSThomas Huth uint64_t sts; 1334fcf5ef2aSThomas Huth } BNDCSReg; 1335fcf5ef2aSThomas Huth 1336fcf5ef2aSThomas Huth #define BNDCFG_ENABLE 1ULL 1337fcf5ef2aSThomas Huth #define BNDCFG_BNDPRESERVE 2ULL 1338fcf5ef2aSThomas Huth #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 1339fcf5ef2aSThomas Huth 1340e03b5686SMarc-André Lureau #if HOST_BIG_ENDIAN 1341fcf5ef2aSThomas Huth #define ZMM_B(n) _b_ZMMReg[63 - (n)] 1342fcf5ef2aSThomas Huth #define ZMM_W(n) _w_ZMMReg[31 - (n)] 1343fcf5ef2aSThomas Huth #define ZMM_L(n) _l_ZMMReg[15 - (n)] 1344cf5ec664SPaolo Bonzini #define ZMM_H(n) _h_ZMMReg[31 - (n)] 1345fcf5ef2aSThomas Huth #define ZMM_S(n) _s_ZMMReg[15 - (n)] 1346fcf5ef2aSThomas Huth #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 1347fcf5ef2aSThomas Huth #define ZMM_D(n) _d_ZMMReg[7 - (n)] 134875f107a8SRichard Henderson #define ZMM_X(n) _x_ZMMReg[3 - (n)] 134975f107a8SRichard Henderson #define ZMM_Y(n) _y_ZMMReg[1 - (n)] 135075f107a8SRichard Henderson 135175f107a8SRichard Henderson #define XMM_Q(n) _q_XMMReg[1 - (n)] 135275f107a8SRichard Henderson 135375f107a8SRichard Henderson #define YMM_Q(n) _q_YMMReg[3 - (n)] 135475f107a8SRichard Henderson #define YMM_X(n) _x_YMMReg[1 - (n)] 1355fcf5ef2aSThomas Huth 1356fcf5ef2aSThomas Huth #define MMX_B(n) _b_MMXReg[7 - (n)] 1357fcf5ef2aSThomas Huth #define MMX_W(n) _w_MMXReg[3 - (n)] 1358fcf5ef2aSThomas Huth #define MMX_L(n) _l_MMXReg[1 - (n)] 1359fcf5ef2aSThomas Huth #define MMX_S(n) _s_MMXReg[1 - (n)] 1360fcf5ef2aSThomas Huth #else 1361fcf5ef2aSThomas Huth #define ZMM_B(n) _b_ZMMReg[n] 1362fcf5ef2aSThomas Huth #define ZMM_W(n) _w_ZMMReg[n] 1363fcf5ef2aSThomas Huth #define ZMM_L(n) _l_ZMMReg[n] 1364cf5ec664SPaolo Bonzini #define ZMM_H(n) _h_ZMMReg[n] 1365fcf5ef2aSThomas Huth #define ZMM_S(n) _s_ZMMReg[n] 1366fcf5ef2aSThomas Huth #define ZMM_Q(n) _q_ZMMReg[n] 1367fcf5ef2aSThomas Huth #define ZMM_D(n) _d_ZMMReg[n] 136875f107a8SRichard Henderson #define ZMM_X(n) _x_ZMMReg[n] 136975f107a8SRichard Henderson #define ZMM_Y(n) _y_ZMMReg[n] 137075f107a8SRichard Henderson 137175f107a8SRichard Henderson #define XMM_Q(n) _q_XMMReg[n] 137275f107a8SRichard Henderson 137375f107a8SRichard Henderson #define YMM_Q(n) _q_YMMReg[n] 137475f107a8SRichard Henderson #define YMM_X(n) _x_YMMReg[n] 1375fcf5ef2aSThomas Huth 1376fcf5ef2aSThomas Huth #define MMX_B(n) _b_MMXReg[n] 1377fcf5ef2aSThomas Huth #define MMX_W(n) _w_MMXReg[n] 1378fcf5ef2aSThomas Huth #define MMX_L(n) _l_MMXReg[n] 1379fcf5ef2aSThomas Huth #define MMX_S(n) _s_MMXReg[n] 1380fcf5ef2aSThomas Huth #endif 1381fcf5ef2aSThomas Huth #define MMX_Q(n) _q_MMXReg[n] 1382fcf5ef2aSThomas Huth 1383fcf5ef2aSThomas Huth typedef union { 1384fcf5ef2aSThomas Huth floatx80 d __attribute__((aligned(16))); 1385fcf5ef2aSThomas Huth MMXReg mmx; 1386fcf5ef2aSThomas Huth } FPReg; 1387fcf5ef2aSThomas Huth 1388fcf5ef2aSThomas Huth typedef struct { 1389fcf5ef2aSThomas Huth uint64_t base; 1390fcf5ef2aSThomas Huth uint64_t mask; 1391fcf5ef2aSThomas Huth } MTRRVar; 1392fcf5ef2aSThomas Huth 1393fcf5ef2aSThomas Huth #define CPU_NB_REGS64 16 1394fcf5ef2aSThomas Huth #define CPU_NB_REGS32 8 1395fcf5ef2aSThomas Huth 1396fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 1397fcf5ef2aSThomas Huth #define CPU_NB_REGS CPU_NB_REGS64 1398fcf5ef2aSThomas Huth #else 1399fcf5ef2aSThomas Huth #define CPU_NB_REGS CPU_NB_REGS32 1400fcf5ef2aSThomas Huth #endif 1401fcf5ef2aSThomas Huth 1402fcf5ef2aSThomas Huth #define MAX_FIXED_COUNTERS 3 1403fcf5ef2aSThomas Huth #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 1404fcf5ef2aSThomas Huth 1405fcf5ef2aSThomas Huth #define TARGET_INSN_START_EXTRA_WORDS 1 1406fcf5ef2aSThomas Huth 1407fcf5ef2aSThomas Huth #define NB_OPMASK_REGS 8 1408fcf5ef2aSThomas Huth 1409fcf5ef2aSThomas Huth /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 1410fcf5ef2aSThomas Huth * that APIC ID hasn't been set yet 1411fcf5ef2aSThomas Huth */ 1412fcf5ef2aSThomas Huth #define UNASSIGNED_APIC_ID 0xFFFFFFFF 1413fcf5ef2aSThomas Huth 1414fcf5ef2aSThomas Huth typedef union X86LegacyXSaveArea { 1415fcf5ef2aSThomas Huth struct { 1416fcf5ef2aSThomas Huth uint16_t fcw; 1417fcf5ef2aSThomas Huth uint16_t fsw; 1418fcf5ef2aSThomas Huth uint8_t ftw; 1419fcf5ef2aSThomas Huth uint8_t reserved; 1420fcf5ef2aSThomas Huth uint16_t fpop; 1421fcf5ef2aSThomas Huth uint64_t fpip; 1422fcf5ef2aSThomas Huth uint64_t fpdp; 1423fcf5ef2aSThomas Huth uint32_t mxcsr; 1424fcf5ef2aSThomas Huth uint32_t mxcsr_mask; 1425fcf5ef2aSThomas Huth FPReg fpregs[8]; 1426fcf5ef2aSThomas Huth uint8_t xmm_regs[16][16]; 1427fcf5ef2aSThomas Huth }; 1428fcf5ef2aSThomas Huth uint8_t data[512]; 1429fcf5ef2aSThomas Huth } X86LegacyXSaveArea; 1430fcf5ef2aSThomas Huth 1431fcf5ef2aSThomas Huth typedef struct X86XSaveHeader { 1432fcf5ef2aSThomas Huth uint64_t xstate_bv; 1433fcf5ef2aSThomas Huth uint64_t xcomp_bv; 1434fcf5ef2aSThomas Huth uint64_t reserve0; 1435fcf5ef2aSThomas Huth uint8_t reserved[40]; 1436fcf5ef2aSThomas Huth } X86XSaveHeader; 1437fcf5ef2aSThomas Huth 1438fcf5ef2aSThomas Huth /* Ext. save area 2: AVX State */ 1439fcf5ef2aSThomas Huth typedef struct XSaveAVX { 1440fcf5ef2aSThomas Huth uint8_t ymmh[16][16]; 1441fcf5ef2aSThomas Huth } XSaveAVX; 1442fcf5ef2aSThomas Huth 1443fcf5ef2aSThomas Huth /* Ext. save area 3: BNDREG */ 1444fcf5ef2aSThomas Huth typedef struct XSaveBNDREG { 1445fcf5ef2aSThomas Huth BNDReg bnd_regs[4]; 1446fcf5ef2aSThomas Huth } XSaveBNDREG; 1447fcf5ef2aSThomas Huth 1448fcf5ef2aSThomas Huth /* Ext. save area 4: BNDCSR */ 1449fcf5ef2aSThomas Huth typedef union XSaveBNDCSR { 1450fcf5ef2aSThomas Huth BNDCSReg bndcsr; 1451fcf5ef2aSThomas Huth uint8_t data[64]; 1452fcf5ef2aSThomas Huth } XSaveBNDCSR; 1453fcf5ef2aSThomas Huth 1454fcf5ef2aSThomas Huth /* Ext. save area 5: Opmask */ 1455fcf5ef2aSThomas Huth typedef struct XSaveOpmask { 1456fcf5ef2aSThomas Huth uint64_t opmask_regs[NB_OPMASK_REGS]; 1457fcf5ef2aSThomas Huth } XSaveOpmask; 1458fcf5ef2aSThomas Huth 1459fcf5ef2aSThomas Huth /* Ext. save area 6: ZMM_Hi256 */ 1460fcf5ef2aSThomas Huth typedef struct XSaveZMM_Hi256 { 1461fcf5ef2aSThomas Huth uint8_t zmm_hi256[16][32]; 1462fcf5ef2aSThomas Huth } XSaveZMM_Hi256; 1463fcf5ef2aSThomas Huth 1464fcf5ef2aSThomas Huth /* Ext. save area 7: Hi16_ZMM */ 1465fcf5ef2aSThomas Huth typedef struct XSaveHi16_ZMM { 1466fcf5ef2aSThomas Huth uint8_t hi16_zmm[16][64]; 1467fcf5ef2aSThomas Huth } XSaveHi16_ZMM; 1468fcf5ef2aSThomas Huth 1469fcf5ef2aSThomas Huth /* Ext. save area 9: PKRU state */ 1470fcf5ef2aSThomas Huth typedef struct XSavePKRU { 1471fcf5ef2aSThomas Huth uint32_t pkru; 1472fcf5ef2aSThomas Huth uint32_t padding; 1473fcf5ef2aSThomas Huth } XSavePKRU; 1474fcf5ef2aSThomas Huth 14751f16764fSJing Liu /* Ext. save area 17: AMX XTILECFG state */ 14761f16764fSJing Liu typedef struct XSaveXTILECFG { 14771f16764fSJing Liu uint8_t xtilecfg[64]; 14781f16764fSJing Liu } XSaveXTILECFG; 14791f16764fSJing Liu 14801f16764fSJing Liu /* Ext. save area 18: AMX XTILEDATA state */ 14811f16764fSJing Liu typedef struct XSaveXTILEDATA { 14821f16764fSJing Liu uint8_t xtiledata[8][1024]; 14831f16764fSJing Liu } XSaveXTILEDATA; 14841f16764fSJing Liu 148510f0abcbSYang Weijiang typedef struct { 148610f0abcbSYang Weijiang uint64_t from; 148710f0abcbSYang Weijiang uint64_t to; 148810f0abcbSYang Weijiang uint64_t info; 148910f0abcbSYang Weijiang } LBREntry; 149010f0abcbSYang Weijiang 149110f0abcbSYang Weijiang #define ARCH_LBR_NR_ENTRIES 32 149210f0abcbSYang Weijiang 149310f0abcbSYang Weijiang /* Ext. save area 19: Supervisor mode Arch LBR state */ 149410f0abcbSYang Weijiang typedef struct XSavesArchLBR { 149510f0abcbSYang Weijiang uint64_t lbr_ctl; 149610f0abcbSYang Weijiang uint64_t lbr_depth; 149710f0abcbSYang Weijiang uint64_t ler_from; 149810f0abcbSYang Weijiang uint64_t ler_to; 149910f0abcbSYang Weijiang uint64_t ler_info; 150010f0abcbSYang Weijiang LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; 150110f0abcbSYang Weijiang } XSavesArchLBR; 150210f0abcbSYang Weijiang 1503fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 1504fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 1505fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 1506fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 1507fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 1508fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 1509fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 15101f16764fSJing Liu QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40); 15111f16764fSJing Liu QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000); 151210f0abcbSYang Weijiang QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328); 1513fcf5ef2aSThomas Huth 15145aa10ab1SDavid Edmondson typedef struct ExtSaveArea { 15155aa10ab1SDavid Edmondson uint32_t feature, bits; 15165aa10ab1SDavid Edmondson uint32_t offset, size; 1517131266b7SJing Liu uint32_t ecx; 15185aa10ab1SDavid Edmondson } ExtSaveArea; 15195aa10ab1SDavid Edmondson 15201f16764fSJing Liu #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) 15215aa10ab1SDavid Edmondson 1522fea45008SDavid Edmondson extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; 15235aa10ab1SDavid Edmondson 1524fcf5ef2aSThomas Huth typedef enum TPRAccess { 1525fcf5ef2aSThomas Huth TPR_ACCESS_READ, 1526fcf5ef2aSThomas Huth TPR_ACCESS_WRITE, 1527fcf5ef2aSThomas Huth } TPRAccess; 1528fcf5ef2aSThomas Huth 15297e3482f8SEduardo Habkost /* Cache information data structures: */ 15307e3482f8SEduardo Habkost 15317e3482f8SEduardo Habkost enum CacheType { 15325f00335aSEduardo Habkost DATA_CACHE, 15335f00335aSEduardo Habkost INSTRUCTION_CACHE, 15347e3482f8SEduardo Habkost UNIFIED_CACHE 15357e3482f8SEduardo Habkost }; 15367e3482f8SEduardo Habkost 15377e3482f8SEduardo Habkost typedef struct CPUCacheInfo { 15387e3482f8SEduardo Habkost enum CacheType type; 15397e3482f8SEduardo Habkost uint8_t level; 15407e3482f8SEduardo Habkost /* Size in bytes */ 15417e3482f8SEduardo Habkost uint32_t size; 15427e3482f8SEduardo Habkost /* Line size, in bytes */ 15437e3482f8SEduardo Habkost uint16_t line_size; 15447e3482f8SEduardo Habkost /* 15457e3482f8SEduardo Habkost * Associativity. 15467e3482f8SEduardo Habkost * Note: representation of fully-associative caches is not implemented 15477e3482f8SEduardo Habkost */ 15487e3482f8SEduardo Habkost uint8_t associativity; 15497e3482f8SEduardo Habkost /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ 15507e3482f8SEduardo Habkost uint8_t partitions; 15517e3482f8SEduardo Habkost /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ 15527e3482f8SEduardo Habkost uint32_t sets; 15537e3482f8SEduardo Habkost /* 15547e3482f8SEduardo Habkost * Lines per tag. 15557e3482f8SEduardo Habkost * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. 15567e3482f8SEduardo Habkost * (Is this synonym to @partitions?) 15577e3482f8SEduardo Habkost */ 15587e3482f8SEduardo Habkost uint8_t lines_per_tag; 15597e3482f8SEduardo Habkost 15607e3482f8SEduardo Habkost /* Self-initializing cache */ 15617e3482f8SEduardo Habkost bool self_init; 15627e3482f8SEduardo Habkost /* 15637e3482f8SEduardo Habkost * WBINVD/INVD is not guaranteed to act upon lower level caches of 15647e3482f8SEduardo Habkost * non-originating threads sharing this cache. 15657e3482f8SEduardo Habkost * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] 15667e3482f8SEduardo Habkost */ 15677e3482f8SEduardo Habkost bool no_invd_sharing; 15687e3482f8SEduardo Habkost /* 15697e3482f8SEduardo Habkost * Cache is inclusive of lower cache levels. 15707e3482f8SEduardo Habkost * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. 15717e3482f8SEduardo Habkost */ 15727e3482f8SEduardo Habkost bool inclusive; 15737e3482f8SEduardo Habkost /* 15747e3482f8SEduardo Habkost * A complex function is used to index the cache, potentially using all 15757e3482f8SEduardo Habkost * address bits. CPUID[4].EDX[bit 2]. 15767e3482f8SEduardo Habkost */ 15777e3482f8SEduardo Habkost bool complex_indexing; 15787e3482f8SEduardo Habkost } CPUCacheInfo; 15797e3482f8SEduardo Habkost 15807e3482f8SEduardo Habkost 15816aaeb054SBabu Moger typedef struct CPUCaches { 1582a9f27ea9SEduardo Habkost CPUCacheInfo *l1d_cache; 1583a9f27ea9SEduardo Habkost CPUCacheInfo *l1i_cache; 1584a9f27ea9SEduardo Habkost CPUCacheInfo *l2_cache; 1585a9f27ea9SEduardo Habkost CPUCacheInfo *l3_cache; 15866aaeb054SBabu Moger } CPUCaches; 15877e3482f8SEduardo Habkost 1588577f02b8SRoman Bolshakov typedef struct HVFX86LazyFlags { 1589577f02b8SRoman Bolshakov target_ulong result; 1590577f02b8SRoman Bolshakov target_ulong auxbits; 1591577f02b8SRoman Bolshakov } HVFX86LazyFlags; 1592577f02b8SRoman Bolshakov 15931ea4a06aSPhilippe Mathieu-Daudé typedef struct CPUArchState { 1594fcf5ef2aSThomas Huth /* standard registers */ 1595fcf5ef2aSThomas Huth target_ulong regs[CPU_NB_REGS]; 1596fcf5ef2aSThomas Huth target_ulong eip; 1597fcf5ef2aSThomas Huth target_ulong eflags; /* eflags register. During CPU emulation, CC 1598fcf5ef2aSThomas Huth flags and DF are set to zero because they are 1599fcf5ef2aSThomas Huth stored elsewhere */ 1600fcf5ef2aSThomas Huth 1601fcf5ef2aSThomas Huth /* emulator internal eflags handling */ 1602fcf5ef2aSThomas Huth target_ulong cc_dst; 1603fcf5ef2aSThomas Huth target_ulong cc_src; 1604fcf5ef2aSThomas Huth target_ulong cc_src2; 1605fcf5ef2aSThomas Huth uint32_t cc_op; 1606fcf5ef2aSThomas Huth int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1607fcf5ef2aSThomas Huth uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1608fcf5ef2aSThomas Huth are known at translation time. */ 1609fcf5ef2aSThomas Huth uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1610fcf5ef2aSThomas Huth 1611fcf5ef2aSThomas Huth /* segments */ 1612fcf5ef2aSThomas Huth SegmentCache segs[6]; /* selector values */ 1613fcf5ef2aSThomas Huth SegmentCache ldt; 1614fcf5ef2aSThomas Huth SegmentCache tr; 1615fcf5ef2aSThomas Huth SegmentCache gdt; /* only base and limit are used */ 1616fcf5ef2aSThomas Huth SegmentCache idt; /* only base and limit are used */ 1617fcf5ef2aSThomas Huth 1618fcf5ef2aSThomas Huth target_ulong cr[5]; /* NOTE: cr1 is unused */ 16198f515d38SMaxim Levitsky 16208f515d38SMaxim Levitsky bool pdptrs_valid; 16218f515d38SMaxim Levitsky uint64_t pdptrs[4]; 1622fcf5ef2aSThomas Huth int32_t a20_mask; 1623fcf5ef2aSThomas Huth 1624fcf5ef2aSThomas Huth BNDReg bnd_regs[4]; 1625fcf5ef2aSThomas Huth BNDCSReg bndcs_regs; 1626fcf5ef2aSThomas Huth uint64_t msr_bndcfgs; 1627fcf5ef2aSThomas Huth uint64_t efer; 1628fcf5ef2aSThomas Huth 1629fcf5ef2aSThomas Huth /* Beginning of state preserved by INIT (dummy marker). */ 1630fcf5ef2aSThomas Huth struct {} start_init_save; 1631fcf5ef2aSThomas Huth 1632fcf5ef2aSThomas Huth /* FPU state */ 1633fcf5ef2aSThomas Huth unsigned int fpstt; /* top of stack index */ 1634fcf5ef2aSThomas Huth uint16_t fpus; 1635fcf5ef2aSThomas Huth uint16_t fpuc; 1636fcf5ef2aSThomas Huth uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1637fcf5ef2aSThomas Huth FPReg fpregs[8]; 1638fcf5ef2aSThomas Huth /* KVM-only so far */ 1639fcf5ef2aSThomas Huth uint16_t fpop; 164084abdd7dSZiqiao Kong uint16_t fpcs; 164184abdd7dSZiqiao Kong uint16_t fpds; 1642fcf5ef2aSThomas Huth uint64_t fpip; 1643fcf5ef2aSThomas Huth uint64_t fpdp; 1644fcf5ef2aSThomas Huth 1645fcf5ef2aSThomas Huth /* emulator internal variables */ 1646fcf5ef2aSThomas Huth float_status fp_status; 1647fcf5ef2aSThomas Huth floatx80 ft0; 1648fcf5ef2aSThomas Huth 1649fcf5ef2aSThomas Huth float_status mmx_status; /* for 3DNow! float ops */ 1650fcf5ef2aSThomas Huth float_status sse_status; 1651fcf5ef2aSThomas Huth uint32_t mxcsr; 165275f107a8SRichard Henderson ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16); 165375f107a8SRichard Henderson ZMMReg xmm_t0 QEMU_ALIGNED(16); 1654fcf5ef2aSThomas Huth MMXReg mmx_t0; 1655fcf5ef2aSThomas Huth 1656fcf5ef2aSThomas Huth uint64_t opmask_regs[NB_OPMASK_REGS]; 1657e56dd3c7SJing Liu #ifdef TARGET_X86_64 1658e56dd3c7SJing Liu uint8_t xtilecfg[64]; 1659e56dd3c7SJing Liu uint8_t xtiledata[8192]; 1660e56dd3c7SJing Liu #endif 1661fcf5ef2aSThomas Huth 1662fcf5ef2aSThomas Huth /* sysenter registers */ 1663fcf5ef2aSThomas Huth uint32_t sysenter_cs; 1664fcf5ef2aSThomas Huth target_ulong sysenter_esp; 1665fcf5ef2aSThomas Huth target_ulong sysenter_eip; 1666fcf5ef2aSThomas Huth uint64_t star; 1667fcf5ef2aSThomas Huth 1668fcf5ef2aSThomas Huth uint64_t vm_hsave; 1669fcf5ef2aSThomas Huth 1670fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 1671fcf5ef2aSThomas Huth target_ulong lstar; 1672fcf5ef2aSThomas Huth target_ulong cstar; 1673fcf5ef2aSThomas Huth target_ulong fmask; 1674fcf5ef2aSThomas Huth target_ulong kernelgsbase; 1675fcf5ef2aSThomas Huth #endif 1676fcf5ef2aSThomas Huth 1677fcf5ef2aSThomas Huth uint64_t tsc_adjust; 1678fcf5ef2aSThomas Huth uint64_t tsc_deadline; 1679fcf5ef2aSThomas Huth uint64_t tsc_aux; 1680fcf5ef2aSThomas Huth 1681fcf5ef2aSThomas Huth uint64_t xcr0; 1682fcf5ef2aSThomas Huth 1683fcf5ef2aSThomas Huth uint64_t mcg_status; 1684fcf5ef2aSThomas Huth uint64_t msr_ia32_misc_enable; 1685fcf5ef2aSThomas Huth uint64_t msr_ia32_feature_control; 1686db888065SSean Christopherson uint64_t msr_ia32_sgxlepubkeyhash[4]; 1687fcf5ef2aSThomas Huth 1688fcf5ef2aSThomas Huth uint64_t msr_fixed_ctr_ctrl; 1689fcf5ef2aSThomas Huth uint64_t msr_global_ctrl; 1690fcf5ef2aSThomas Huth uint64_t msr_global_status; 1691fcf5ef2aSThomas Huth uint64_t msr_global_ovf_ctrl; 1692fcf5ef2aSThomas Huth uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1693fcf5ef2aSThomas Huth uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1694fcf5ef2aSThomas Huth uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1695fcf5ef2aSThomas Huth 1696fcf5ef2aSThomas Huth uint64_t pat; 1697fcf5ef2aSThomas Huth uint32_t smbase; 1698e13713dbSLiran Alon uint64_t msr_smi_count; 1699fcf5ef2aSThomas Huth 1700fcf5ef2aSThomas Huth uint32_t pkru; 1701e7e7bdabSPaolo Bonzini uint32_t pkrs; 17022a9758c5SPaolo Bonzini uint32_t tsx_ctrl; 1703fcf5ef2aSThomas Huth 1704a33a2cfeSPaolo Bonzini uint64_t spec_ctrl; 1705cabf9862SMaxim Levitsky uint64_t amd_tsc_scale_msr; 1706cfeea0c0SKonrad Rzeszutek Wilk uint64_t virt_ssbd; 1707a33a2cfeSPaolo Bonzini 1708fcf5ef2aSThomas Huth /* End of state preserved by INIT (dummy marker). */ 1709fcf5ef2aSThomas Huth struct {} end_init_save; 1710fcf5ef2aSThomas Huth 1711fcf5ef2aSThomas Huth uint64_t system_time_msr; 1712fcf5ef2aSThomas Huth uint64_t wall_clock_msr; 1713fcf5ef2aSThomas Huth uint64_t steal_time_msr; 1714fcf5ef2aSThomas Huth uint64_t async_pf_en_msr; 1715db5daafaSVitaly Kuznetsov uint64_t async_pf_int_msr; 1716fcf5ef2aSThomas Huth uint64_t pv_eoi_en_msr; 1717d645e132SMarcelo Tosatti uint64_t poll_control_msr; 1718fcf5ef2aSThomas Huth 1719da1cc323SEvgeny Yakovlev /* Partition-wide HV MSRs, will be updated only on the first vcpu */ 1720fcf5ef2aSThomas Huth uint64_t msr_hv_hypercall; 1721fcf5ef2aSThomas Huth uint64_t msr_hv_guest_os_id; 1722fcf5ef2aSThomas Huth uint64_t msr_hv_tsc; 172373d24074SJon Doron uint64_t msr_hv_syndbg_control; 172473d24074SJon Doron uint64_t msr_hv_syndbg_status; 172573d24074SJon Doron uint64_t msr_hv_syndbg_send_page; 172673d24074SJon Doron uint64_t msr_hv_syndbg_recv_page; 172773d24074SJon Doron uint64_t msr_hv_syndbg_pending_page; 172873d24074SJon Doron uint64_t msr_hv_syndbg_options; 1729da1cc323SEvgeny Yakovlev 1730da1cc323SEvgeny Yakovlev /* Per-VCPU HV MSRs */ 1731da1cc323SEvgeny Yakovlev uint64_t msr_hv_vapic; 17325e953812SRoman Kagan uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; 1733fcf5ef2aSThomas Huth uint64_t msr_hv_runtime; 1734fcf5ef2aSThomas Huth uint64_t msr_hv_synic_control; 1735fcf5ef2aSThomas Huth uint64_t msr_hv_synic_evt_page; 1736fcf5ef2aSThomas Huth uint64_t msr_hv_synic_msg_page; 17375e953812SRoman Kagan uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; 17385e953812SRoman Kagan uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; 17395e953812SRoman Kagan uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; 1740ba6a4fd9SVitaly Kuznetsov uint64_t msr_hv_reenlightenment_control; 1741ba6a4fd9SVitaly Kuznetsov uint64_t msr_hv_tsc_emulation_control; 1742ba6a4fd9SVitaly Kuznetsov uint64_t msr_hv_tsc_emulation_status; 1743fcf5ef2aSThomas Huth 1744b77146e9SChao Peng uint64_t msr_rtit_ctrl; 1745b77146e9SChao Peng uint64_t msr_rtit_status; 1746b77146e9SChao Peng uint64_t msr_rtit_output_base; 1747b77146e9SChao Peng uint64_t msr_rtit_output_mask; 1748b77146e9SChao Peng uint64_t msr_rtit_cr3_match; 1749b77146e9SChao Peng uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; 1750b77146e9SChao Peng 1751cdec2b75SZeng Guang /* Per-VCPU XFD MSRs */ 1752cdec2b75SZeng Guang uint64_t msr_xfd; 1753cdec2b75SZeng Guang uint64_t msr_xfd_err; 1754cdec2b75SZeng Guang 175512703d4eSYang Weijiang /* Per-VCPU Arch LBR MSRs */ 175612703d4eSYang Weijiang uint64_t msr_lbr_ctl; 175712703d4eSYang Weijiang uint64_t msr_lbr_depth; 175812703d4eSYang Weijiang LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; 175912703d4eSYang Weijiang 1760fcf5ef2aSThomas Huth /* exception/interrupt handling */ 1761fcf5ef2aSThomas Huth int error_code; 1762fcf5ef2aSThomas Huth int exception_is_int; 1763fcf5ef2aSThomas Huth target_ulong exception_next_eip; 1764fcf5ef2aSThomas Huth target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1765fcf5ef2aSThomas Huth union { 1766fcf5ef2aSThomas Huth struct CPUBreakpoint *cpu_breakpoint[4]; 1767fcf5ef2aSThomas Huth struct CPUWatchpoint *cpu_watchpoint[4]; 1768fcf5ef2aSThomas Huth }; /* break/watchpoints for dr[0..3] */ 1769fcf5ef2aSThomas Huth int old_exception; /* exception in flight */ 1770fcf5ef2aSThomas Huth 1771fcf5ef2aSThomas Huth uint64_t vm_vmcb; 1772fcf5ef2aSThomas Huth uint64_t tsc_offset; 1773fcf5ef2aSThomas Huth uint64_t intercept; 1774fcf5ef2aSThomas Huth uint16_t intercept_cr_read; 1775fcf5ef2aSThomas Huth uint16_t intercept_cr_write; 1776fcf5ef2aSThomas Huth uint16_t intercept_dr_read; 1777fcf5ef2aSThomas Huth uint16_t intercept_dr_write; 1778fcf5ef2aSThomas Huth uint32_t intercept_exceptions; 1779fe441054SJan Kiszka uint64_t nested_cr3; 1780fe441054SJan Kiszka uint32_t nested_pg_mode; 1781fcf5ef2aSThomas Huth uint8_t v_tpr; 1782e3126a5cSLara Lazier uint32_t int_ctl; 1783fcf5ef2aSThomas Huth 1784fcf5ef2aSThomas Huth /* KVM states, automatically cleared on reset */ 1785fcf5ef2aSThomas Huth uint8_t nmi_injected; 1786fcf5ef2aSThomas Huth uint8_t nmi_pending; 1787fcf5ef2aSThomas Huth 1788fe441054SJan Kiszka uintptr_t retaddr; 1789fe441054SJan Kiszka 17901f5c00cfSAlex Bennée /* Fields up to this point are cleared by a CPU reset */ 17911f5c00cfSAlex Bennée struct {} end_reset_fields; 17921f5c00cfSAlex Bennée 1793e8b5fae5SRichard Henderson /* Fields after this point are preserved across CPU reset. */ 1794fcf5ef2aSThomas Huth 1795fcf5ef2aSThomas Huth /* processor features (e.g. for CPUID insn) */ 179680db491dSJing Liu /* Minimum cpuid leaf 7 value */ 179780db491dSJing Liu uint32_t cpuid_level_func7; 179880db491dSJing Liu /* Actual cpuid leaf 7 value */ 179980db491dSJing Liu uint32_t cpuid_min_level_func7; 1800fcf5ef2aSThomas Huth /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1801fcf5ef2aSThomas Huth uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1802fcf5ef2aSThomas Huth /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1803fcf5ef2aSThomas Huth uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1804fcf5ef2aSThomas Huth /* Actual level/xlevel/xlevel2 value: */ 1805fcf5ef2aSThomas Huth uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1806fcf5ef2aSThomas Huth uint32_t cpuid_vendor1; 1807fcf5ef2aSThomas Huth uint32_t cpuid_vendor2; 1808fcf5ef2aSThomas Huth uint32_t cpuid_vendor3; 1809fcf5ef2aSThomas Huth uint32_t cpuid_version; 1810fcf5ef2aSThomas Huth FeatureWordArray features; 1811d4a606b3SEduardo Habkost /* Features that were explicitly enabled/disabled */ 1812d4a606b3SEduardo Habkost FeatureWordArray user_features; 1813fcf5ef2aSThomas Huth uint32_t cpuid_model[12]; 1814a9f27ea9SEduardo Habkost /* Cache information for CPUID. When legacy-cache=on, the cache data 1815a9f27ea9SEduardo Habkost * on each CPUID leaf will be different, because we keep compatibility 1816a9f27ea9SEduardo Habkost * with old QEMU versions. 1817a9f27ea9SEduardo Habkost */ 1818a9f27ea9SEduardo Habkost CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; 1819fcf5ef2aSThomas Huth 1820fcf5ef2aSThomas Huth /* MTRRs */ 1821fcf5ef2aSThomas Huth uint64_t mtrr_fixed[11]; 1822fcf5ef2aSThomas Huth uint64_t mtrr_deftype; 1823fcf5ef2aSThomas Huth MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1824fcf5ef2aSThomas Huth 1825fcf5ef2aSThomas Huth /* For KVM */ 1826fcf5ef2aSThomas Huth uint32_t mp_state; 1827fd13f23bSLiran Alon int32_t exception_nr; 1828fcf5ef2aSThomas Huth int32_t interrupt_injected; 1829fcf5ef2aSThomas Huth uint8_t soft_interrupt; 1830fd13f23bSLiran Alon uint8_t exception_pending; 1831fd13f23bSLiran Alon uint8_t exception_injected; 1832fcf5ef2aSThomas Huth uint8_t has_error_code; 1833fd13f23bSLiran Alon uint8_t exception_has_payload; 1834fd13f23bSLiran Alon uint64_t exception_payload; 183512f89a39SChenyi Qiang uint8_t triple_fault_pending; 1836c97d6d2cSSergio Andres Gomez Del Real uint32_t ins_len; 1837fcf5ef2aSThomas Huth uint32_t sipi_vector; 1838fcf5ef2aSThomas Huth bool tsc_valid; 1839fcf5ef2aSThomas Huth int64_t tsc_khz; 1840fcf5ef2aSThomas Huth int64_t user_tsc_khz; /* for sanity check only */ 184173b994f6SLiran Alon uint64_t apic_bus_freq; 18425286c366SPaolo Bonzini uint64_t tsc; 18435b8063c4SLiran Alon #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 18445b8063c4SLiran Alon void *xsave_buf; 1845c0198c5fSDavid Edmondson uint32_t xsave_buf_len; 18465b8063c4SLiran Alon #endif 1847ebbfef2fSLiran Alon #if defined(CONFIG_KVM) 1848ebbfef2fSLiran Alon struct kvm_nested_state *nested_state; 184927d4075dSDavid Woodhouse MemoryRegion *xen_vcpu_info_mr; 185027d4075dSDavid Woodhouse void *xen_vcpu_info_hva; 1851c345104cSJoao Martins uint64_t xen_vcpu_info_gpa; 1852c345104cSJoao Martins uint64_t xen_vcpu_info_default_gpa; 1853f0689302SJoao Martins uint64_t xen_vcpu_time_info_gpa; 18545092db87SJoao Martins uint64_t xen_vcpu_runstate_gpa; 1855105b47fdSAnkur Arora uint8_t xen_vcpu_callback_vector; 1856ddf0fd9aSDavid Woodhouse bool xen_callback_asserted; 1857c723d4c1SDavid Woodhouse uint16_t xen_virq[XEN_NR_VIRQS]; 1858c723d4c1SDavid Woodhouse uint64_t xen_singleshot_timer_ns; 1859b746a779SJoao Martins QEMUTimer *xen_singleshot_timer; 1860b746a779SJoao Martins uint64_t xen_periodic_timer_period; 1861b746a779SJoao Martins QEMUTimer *xen_periodic_timer; 1862b746a779SJoao Martins QemuMutex xen_timers_lock; 1863ebbfef2fSLiran Alon #endif 1864c97d6d2cSSergio Andres Gomez Del Real #if defined(CONFIG_HVF) 1865577f02b8SRoman Bolshakov HVFX86LazyFlags hvf_lflags; 1866fe76b09cSRoman Bolshakov void *hvf_mmio_buf; 1867c97d6d2cSSergio Andres Gomez Del Real #endif 1868fcf5ef2aSThomas Huth 1869fcf5ef2aSThomas Huth uint64_t mcg_cap; 1870fcf5ef2aSThomas Huth uint64_t mcg_ctl; 1871fcf5ef2aSThomas Huth uint64_t mcg_ext_ctl; 1872fcf5ef2aSThomas Huth uint64_t mce_banks[MCE_BANKS_DEF*4]; 1873fcf5ef2aSThomas Huth uint64_t xstate_bv; 1874fcf5ef2aSThomas Huth 1875fcf5ef2aSThomas Huth /* vmstate */ 1876fcf5ef2aSThomas Huth uint16_t fpus_vmstate; 1877fcf5ef2aSThomas Huth uint16_t fptag_vmstate; 1878fcf5ef2aSThomas Huth uint16_t fpregs_format_vmstate; 1879fcf5ef2aSThomas Huth 1880fcf5ef2aSThomas Huth uint64_t xss; 188165087997STao Xu uint32_t umwait; 1882fcf5ef2aSThomas Huth 1883fcf5ef2aSThomas Huth TPRAccess tpr_access_type; 1884c26ae610SLike Xu 1885*aa1878fbSZhao Liu /* Number of dies within this CPU package. */ 1886c26ae610SLike Xu unsigned nr_dies; 1887fcf5ef2aSThomas Huth } CPUX86State; 1888fcf5ef2aSThomas Huth 1889fcf5ef2aSThomas Huth struct kvm_msrs; 1890fcf5ef2aSThomas Huth 1891fcf5ef2aSThomas Huth /** 1892fcf5ef2aSThomas Huth * X86CPU: 1893fcf5ef2aSThomas Huth * @env: #CPUX86State 1894fcf5ef2aSThomas Huth * @migratable: If set, only migratable flags will be accepted when "enforce" 1895fcf5ef2aSThomas Huth * mode is used, and only migratable flags will be included in the "host" 1896fcf5ef2aSThomas Huth * CPU model. 1897fcf5ef2aSThomas Huth * 1898fcf5ef2aSThomas Huth * An x86 CPU. 1899fcf5ef2aSThomas Huth */ 1900b36e239eSPhilippe Mathieu-Daudé struct ArchCPU { 1901fcf5ef2aSThomas Huth CPUState parent_obj; 1902fcf5ef2aSThomas Huth 1903fcf5ef2aSThomas Huth CPUX86State env; 19042a693142SPan Nengyuan VMChangeStateEntry *vmsentry; 1905fcf5ef2aSThomas Huth 19064e45aff3SPaolo Bonzini uint64_t ucode_rev; 19074e45aff3SPaolo Bonzini 19084f2beda4SEduardo Habkost uint32_t hyperv_spinlock_attempts; 190908856771SVitaly Kuznetsov char *hyperv_vendor; 19109b4cf107SRoman Kagan bool hyperv_synic_kvm_only; 19112d384d7cSVitaly Kuznetsov uint64_t hyperv_features; 1912e48ddcc6SVitaly Kuznetsov bool hyperv_passthrough; 191330d6ff66SVitaly Kuznetsov OnOffAuto hyperv_no_nonarch_cs; 191408856771SVitaly Kuznetsov uint32_t hyperv_vendor_id[3]; 1915735db465SVitaly Kuznetsov uint32_t hyperv_interface_id[4]; 191623eb5d03SVitaly Kuznetsov uint32_t hyperv_limits[3]; 191770367f09SVitaly Kuznetsov bool hyperv_enforce_cpuid; 1918af7228b8SVitaly Kuznetsov uint32_t hyperv_ver_id_build; 1919af7228b8SVitaly Kuznetsov uint16_t hyperv_ver_id_major; 1920af7228b8SVitaly Kuznetsov uint16_t hyperv_ver_id_minor; 1921af7228b8SVitaly Kuznetsov uint32_t hyperv_ver_id_sp; 1922af7228b8SVitaly Kuznetsov uint8_t hyperv_ver_id_sb; 1923af7228b8SVitaly Kuznetsov uint32_t hyperv_ver_id_sn; 19242d384d7cSVitaly Kuznetsov 1925fcf5ef2aSThomas Huth bool check_cpuid; 1926fcf5ef2aSThomas Huth bool enforce_cpuid; 1927dac1deaeSEduardo Habkost /* 1928dac1deaeSEduardo Habkost * Force features to be enabled even if the host doesn't support them. 1929dac1deaeSEduardo Habkost * This is dangerous and should be done only for testing CPUID 1930dac1deaeSEduardo Habkost * compatibility. 1931dac1deaeSEduardo Habkost */ 1932dac1deaeSEduardo Habkost bool force_features; 1933fcf5ef2aSThomas Huth bool expose_kvm; 19341ce36bfeSDaniel P. Berrange bool expose_tcg; 1935fcf5ef2aSThomas Huth bool migratable; 1936990e0be2SPaolo Bonzini bool migrate_smi_count; 193744bd8e53SEduardo Habkost bool max_features; /* Enable all supported features automatically */ 1938fcf5ef2aSThomas Huth uint32_t apic_id; 1939fcf5ef2aSThomas Huth 19409954a158SPhil Dennis-Jordan /* Enables publishing of TSC increment and Local APIC bus frequencies to 19419954a158SPhil Dennis-Jordan * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 19429954a158SPhil Dennis-Jordan bool vmware_cpuid_freq; 19439954a158SPhil Dennis-Jordan 1944fcf5ef2aSThomas Huth /* if true the CPUID code directly forward host cache leaves to the guest */ 1945fcf5ef2aSThomas Huth bool cache_info_passthrough; 1946fcf5ef2aSThomas Huth 19472266d443SMichael S. Tsirkin /* if true the CPUID code directly forwards 19482266d443SMichael S. Tsirkin * host monitor/mwait leaves to the guest */ 19492266d443SMichael S. Tsirkin struct { 19502266d443SMichael S. Tsirkin uint32_t eax; 19512266d443SMichael S. Tsirkin uint32_t ebx; 19522266d443SMichael S. Tsirkin uint32_t ecx; 19532266d443SMichael S. Tsirkin uint32_t edx; 19542266d443SMichael S. Tsirkin } mwait; 19552266d443SMichael S. Tsirkin 1956fcf5ef2aSThomas Huth /* Features that were filtered out because of missing host capabilities */ 1957f69ecddbSWei Yang FeatureWordArray filtered_features; 1958fcf5ef2aSThomas Huth 1959fcf5ef2aSThomas Huth /* Enable PMU CPUID bits. This can't be enabled by default yet because 1960fcf5ef2aSThomas Huth * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1961fcf5ef2aSThomas Huth * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1962fcf5ef2aSThomas Huth * capabilities) directly to the guest. 1963fcf5ef2aSThomas Huth */ 1964fcf5ef2aSThomas Huth bool enable_pmu; 1965fcf5ef2aSThomas Huth 1966f06d8a18SYang Weijiang /* 1967f06d8a18SYang Weijiang * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR. 1968f06d8a18SYang Weijiang * This can't be initialized with a default because it doesn't have 1969f06d8a18SYang Weijiang * stable ABI support yet. It is only allowed to pass all LBR_FMT bits 1970f06d8a18SYang Weijiang * returned by kvm_arch_get_supported_msr_feature()(which depends on both 1971f06d8a18SYang Weijiang * host CPU and kernel capabilities) to the guest. 1972f06d8a18SYang Weijiang */ 1973f06d8a18SYang Weijiang uint64_t lbr_fmt; 1974f06d8a18SYang Weijiang 1975fcf5ef2aSThomas Huth /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1976fcf5ef2aSThomas Huth * disabled by default to avoid breaking migration between QEMU with 1977fcf5ef2aSThomas Huth * different LMCE configurations. 1978fcf5ef2aSThomas Huth */ 1979fcf5ef2aSThomas Huth bool enable_lmce; 1980fcf5ef2aSThomas Huth 1981fcf5ef2aSThomas Huth /* Compatibility bits for old machine types. 1982fcf5ef2aSThomas Huth * If true present virtual l3 cache for VM, the vcpus in the same virtual 1983fcf5ef2aSThomas Huth * socket share an virtual l3 cache. 1984fcf5ef2aSThomas Huth */ 1985fcf5ef2aSThomas Huth bool enable_l3_cache; 1986fcf5ef2aSThomas Huth 1987ab8f992eSBabu Moger /* Compatibility bits for old machine types. 1988ab8f992eSBabu Moger * If true present the old cache topology information 1989ab8f992eSBabu Moger */ 1990ab8f992eSBabu Moger bool legacy_cache; 1991ab8f992eSBabu Moger 1992fcf5ef2aSThomas Huth /* Compatibility bits for old machine types: */ 1993fcf5ef2aSThomas Huth bool enable_cpuid_0xb; 1994fcf5ef2aSThomas Huth 1995fcf5ef2aSThomas Huth /* Enable auto level-increase for all CPUID leaves */ 1996fcf5ef2aSThomas Huth bool full_cpuid_auto_level; 1997fcf5ef2aSThomas Huth 1998a7a0da84SMichael Roth /* Only advertise CPUID leaves defined by the vendor */ 1999a7a0da84SMichael Roth bool vendor_cpuid_only; 2000a7a0da84SMichael Roth 2001f24c3a79SLuwei Kang /* Enable auto level-increase for Intel Processor Trace leave */ 2002f24c3a79SLuwei Kang bool intel_pt_auto_level; 2003f24c3a79SLuwei Kang 2004fcf5ef2aSThomas Huth /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 2005fcf5ef2aSThomas Huth bool fill_mtrr_mask; 2006fcf5ef2aSThomas Huth 2007fcf5ef2aSThomas Huth /* if true override the phys_bits value with a value read from the host */ 2008fcf5ef2aSThomas Huth bool host_phys_bits; 2009fcf5ef2aSThomas Huth 2010258fe08bSEduardo Habkost /* if set, limit maximum value for phys_bits when host_phys_bits is true */ 2011258fe08bSEduardo Habkost uint8_t host_phys_bits_limit; 2012258fe08bSEduardo Habkost 2013fc3a1fd7SDr. David Alan Gilbert /* Stop SMI delivery for migration compatibility with old machines */ 2014fc3a1fd7SDr. David Alan Gilbert bool kvm_no_smi_migration; 2015fc3a1fd7SDr. David Alan Gilbert 2016988f7b8bSVitaly Kuznetsov /* Forcefully disable KVM PV features not exposed in guest CPUIDs */ 2017988f7b8bSVitaly Kuznetsov bool kvm_pv_enforce_cpuid; 2018988f7b8bSVitaly Kuznetsov 2019fcf5ef2aSThomas Huth /* Number of physical address bits supported */ 2020fcf5ef2aSThomas Huth uint32_t phys_bits; 2021fcf5ef2aSThomas Huth 2022fcf5ef2aSThomas Huth /* in order to simplify APIC support, we leave this pointer to the 2023fcf5ef2aSThomas Huth user */ 2024fcf5ef2aSThomas Huth struct DeviceState *apic_state; 2025fcf5ef2aSThomas Huth struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 2026fcf5ef2aSThomas Huth Notifier machine_done; 2027fcf5ef2aSThomas Huth 2028fcf5ef2aSThomas Huth struct kvm_msrs *kvm_msr_buf; 2029fcf5ef2aSThomas Huth 203015f8b142SIgor Mammedov int32_t node_id; /* NUMA node this CPU belongs to */ 2031fcf5ef2aSThomas Huth int32_t socket_id; 2032176d2cdaSLike Xu int32_t die_id; 2033fcf5ef2aSThomas Huth int32_t core_id; 2034fcf5ef2aSThomas Huth int32_t thread_id; 20356c69dfb6SGonglei 20366c69dfb6SGonglei int32_t hv_max_vps; 2037f66b8a83SJoao Martins 2038f66b8a83SJoao Martins bool xen_vapic; 2039fcf5ef2aSThomas Huth }; 2040fcf5ef2aSThomas Huth 20419348028eSPhilippe Mathieu-Daudé typedef struct X86CPUModel X86CPUModel; 20429348028eSPhilippe Mathieu-Daudé 20439348028eSPhilippe Mathieu-Daudé /** 20449348028eSPhilippe Mathieu-Daudé * X86CPUClass: 20459348028eSPhilippe Mathieu-Daudé * @cpu_def: CPU model definition 20469348028eSPhilippe Mathieu-Daudé * @host_cpuid_required: Whether CPU model requires cpuid from host. 20479348028eSPhilippe Mathieu-Daudé * @ordering: Ordering on the "-cpu help" CPU model list. 20489348028eSPhilippe Mathieu-Daudé * @migration_safe: See CpuDefinitionInfo::migration_safe 20499348028eSPhilippe Mathieu-Daudé * @static_model: See CpuDefinitionInfo::static 20509348028eSPhilippe Mathieu-Daudé * @parent_realize: The parent class' realize handler. 20519348028eSPhilippe Mathieu-Daudé * @parent_phases: The parent class' reset phase handlers. 20529348028eSPhilippe Mathieu-Daudé * 20539348028eSPhilippe Mathieu-Daudé * An x86 CPU model or family. 20549348028eSPhilippe Mathieu-Daudé */ 20559348028eSPhilippe Mathieu-Daudé struct X86CPUClass { 20569348028eSPhilippe Mathieu-Daudé CPUClass parent_class; 20579348028eSPhilippe Mathieu-Daudé 20589348028eSPhilippe Mathieu-Daudé /* 20599348028eSPhilippe Mathieu-Daudé * CPU definition, automatically loaded by instance_init if not NULL. 20609348028eSPhilippe Mathieu-Daudé * Should be eventually replaced by subclass-specific property defaults. 20619348028eSPhilippe Mathieu-Daudé */ 20629348028eSPhilippe Mathieu-Daudé X86CPUModel *model; 20639348028eSPhilippe Mathieu-Daudé 20649348028eSPhilippe Mathieu-Daudé bool host_cpuid_required; 20659348028eSPhilippe Mathieu-Daudé int ordering; 20669348028eSPhilippe Mathieu-Daudé bool migration_safe; 20679348028eSPhilippe Mathieu-Daudé bool static_model; 20689348028eSPhilippe Mathieu-Daudé 20699348028eSPhilippe Mathieu-Daudé /* 20709348028eSPhilippe Mathieu-Daudé * Optional description of CPU model. 20719348028eSPhilippe Mathieu-Daudé * If unavailable, cpu_def->model_id is used. 20729348028eSPhilippe Mathieu-Daudé */ 20739348028eSPhilippe Mathieu-Daudé const char *model_description; 20749348028eSPhilippe Mathieu-Daudé 20759348028eSPhilippe Mathieu-Daudé DeviceRealize parent_realize; 20769348028eSPhilippe Mathieu-Daudé DeviceUnrealize parent_unrealize; 20779348028eSPhilippe Mathieu-Daudé ResettablePhases parent_phases; 20789348028eSPhilippe Mathieu-Daudé }; 2079fcf5ef2aSThomas Huth 2080fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 2081ac701a4fSKeqian Zhu extern const VMStateDescription vmstate_x86_cpu; 2082fcf5ef2aSThomas Huth #endif 2083fcf5ef2aSThomas Huth 208492d5f1a4SPaolo Bonzini int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); 2085fcf5ef2aSThomas Huth 2086fcf5ef2aSThomas Huth int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 20871af0006aSJanosch Frank int cpuid, DumpState *s); 2088fcf5ef2aSThomas Huth int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 20891af0006aSJanosch Frank int cpuid, DumpState *s); 2090fcf5ef2aSThomas Huth int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 20911af0006aSJanosch Frank DumpState *s); 2092fcf5ef2aSThomas Huth int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 20931af0006aSJanosch Frank DumpState *s); 2094fcf5ef2aSThomas Huth 20958a5b974bSMarc-André Lureau bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 2096fcf5ef2aSThomas Huth Error **errp); 2097fcf5ef2aSThomas Huth 209890c84c56SMarkus Armbruster void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); 2099fcf5ef2aSThomas Huth 2100a010bdbeSAlex Bennée int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 2101fcf5ef2aSThomas Huth int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 2102fcf5ef2aSThomas Huth 21030442428aSMarkus Armbruster void x86_cpu_list(void); 2104fcf5ef2aSThomas Huth int cpu_x86_support_mca_broadcast(CPUX86State *env); 2105fcf5ef2aSThomas Huth 210676d0042bSPhilippe Mathieu-Daudé #ifndef CONFIG_USER_ONLY 21076d2d454aSPhilippe Mathieu-Daudé hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 21086d2d454aSPhilippe Mathieu-Daudé MemTxAttrs *attrs); 2109fcf5ef2aSThomas Huth int cpu_get_pic_interrupt(CPUX86State *s); 21107ce08865SPhilippe Mathieu-Daudé 2111bad5cfcdSMichael Tokarev /* MS-DOS compatibility mode FPU exception support */ 21126f529b75SPaolo Bonzini void x86_register_ferr_irq(qemu_irq irq); 211383a3d9c7SClaudio Fontana void fpu_check_raise_ferr_irq(CPUX86State *s); 2114bf13bfabSPaolo Bonzini void cpu_set_ignne(void); 211583a3d9c7SClaudio Fontana void cpu_clear_ignne(void); 21167ce08865SPhilippe Mathieu-Daudé #endif 211783a3d9c7SClaudio Fontana 21185e76d84eSPaolo Bonzini /* mpx_helper.c */ 21195e76d84eSPaolo Bonzini void cpu_sync_bndcs_hflags(CPUX86State *env); 2120fcf5ef2aSThomas Huth 2121fcf5ef2aSThomas Huth /* this function must always be used to load data in the segment 2122fcf5ef2aSThomas Huth cache: it synchronizes the hflags with the segment cache values */ 2123fcf5ef2aSThomas Huth static inline void cpu_x86_load_seg_cache(CPUX86State *env, 2124c117e5b1SPhilippe Mathieu-Daudé X86Seg seg_reg, unsigned int selector, 2125fcf5ef2aSThomas Huth target_ulong base, 2126fcf5ef2aSThomas Huth unsigned int limit, 2127fcf5ef2aSThomas Huth unsigned int flags) 2128fcf5ef2aSThomas Huth { 2129fcf5ef2aSThomas Huth SegmentCache *sc; 2130fcf5ef2aSThomas Huth unsigned int new_hflags; 2131fcf5ef2aSThomas Huth 2132fcf5ef2aSThomas Huth sc = &env->segs[seg_reg]; 2133fcf5ef2aSThomas Huth sc->selector = selector; 2134fcf5ef2aSThomas Huth sc->base = base; 2135fcf5ef2aSThomas Huth sc->limit = limit; 2136fcf5ef2aSThomas Huth sc->flags = flags; 2137fcf5ef2aSThomas Huth 2138fcf5ef2aSThomas Huth /* update the hidden flags */ 2139fcf5ef2aSThomas Huth { 2140fcf5ef2aSThomas Huth if (seg_reg == R_CS) { 2141fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 2142fcf5ef2aSThomas Huth if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 2143fcf5ef2aSThomas Huth /* long mode */ 2144fcf5ef2aSThomas Huth env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 2145fcf5ef2aSThomas Huth env->hflags &= ~(HF_ADDSEG_MASK); 2146fcf5ef2aSThomas Huth } else 2147fcf5ef2aSThomas Huth #endif 2148fcf5ef2aSThomas Huth { 2149fcf5ef2aSThomas Huth /* legacy / compatibility case */ 2150fcf5ef2aSThomas Huth new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 2151fcf5ef2aSThomas Huth >> (DESC_B_SHIFT - HF_CS32_SHIFT); 2152fcf5ef2aSThomas Huth env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 2153fcf5ef2aSThomas Huth new_hflags; 2154fcf5ef2aSThomas Huth } 2155fcf5ef2aSThomas Huth } 2156fcf5ef2aSThomas Huth if (seg_reg == R_SS) { 2157fcf5ef2aSThomas Huth int cpl = (flags >> DESC_DPL_SHIFT) & 3; 2158fcf5ef2aSThomas Huth #if HF_CPL_MASK != 3 2159fcf5ef2aSThomas Huth #error HF_CPL_MASK is hardcoded 2160fcf5ef2aSThomas Huth #endif 2161fcf5ef2aSThomas Huth env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 21625e76d84eSPaolo Bonzini /* Possibly switch between BNDCFGS and BNDCFGU */ 21635e76d84eSPaolo Bonzini cpu_sync_bndcs_hflags(env); 2164fcf5ef2aSThomas Huth } 2165fcf5ef2aSThomas Huth new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 2166fcf5ef2aSThomas Huth >> (DESC_B_SHIFT - HF_SS32_SHIFT); 2167fcf5ef2aSThomas Huth if (env->hflags & HF_CS64_MASK) { 2168fcf5ef2aSThomas Huth /* zero base assumed for DS, ES and SS in long mode */ 2169fcf5ef2aSThomas Huth } else if (!(env->cr[0] & CR0_PE_MASK) || 2170fcf5ef2aSThomas Huth (env->eflags & VM_MASK) || 2171fcf5ef2aSThomas Huth !(env->hflags & HF_CS32_MASK)) { 2172fcf5ef2aSThomas Huth /* XXX: try to avoid this test. The problem comes from the 2173fcf5ef2aSThomas Huth fact that is real mode or vm86 mode we only modify the 2174fcf5ef2aSThomas Huth 'base' and 'selector' fields of the segment cache to go 2175fcf5ef2aSThomas Huth faster. A solution may be to force addseg to one in 2176fcf5ef2aSThomas Huth translate-i386.c. */ 2177fcf5ef2aSThomas Huth new_hflags |= HF_ADDSEG_MASK; 2178fcf5ef2aSThomas Huth } else { 2179fcf5ef2aSThomas Huth new_hflags |= ((env->segs[R_DS].base | 2180fcf5ef2aSThomas Huth env->segs[R_ES].base | 2181fcf5ef2aSThomas Huth env->segs[R_SS].base) != 0) << 2182fcf5ef2aSThomas Huth HF_ADDSEG_SHIFT; 2183fcf5ef2aSThomas Huth } 2184fcf5ef2aSThomas Huth env->hflags = (env->hflags & 2185fcf5ef2aSThomas Huth ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 2186fcf5ef2aSThomas Huth } 2187fcf5ef2aSThomas Huth } 2188fcf5ef2aSThomas Huth 2189fcf5ef2aSThomas Huth static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 2190fcf5ef2aSThomas Huth uint8_t sipi_vector) 2191fcf5ef2aSThomas Huth { 2192fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 2193fcf5ef2aSThomas Huth CPUX86State *env = &cpu->env; 2194fcf5ef2aSThomas Huth 2195fcf5ef2aSThomas Huth env->eip = 0; 2196fcf5ef2aSThomas Huth cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 2197fcf5ef2aSThomas Huth sipi_vector << 12, 2198fcf5ef2aSThomas Huth env->segs[R_CS].limit, 2199fcf5ef2aSThomas Huth env->segs[R_CS].flags); 2200fcf5ef2aSThomas Huth cs->halted = 0; 2201fcf5ef2aSThomas Huth } 2202fcf5ef2aSThomas Huth 2203fcf5ef2aSThomas Huth int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 2204fcf5ef2aSThomas Huth target_ulong *base, unsigned int *limit, 2205fcf5ef2aSThomas Huth unsigned int *flags); 2206fcf5ef2aSThomas Huth 2207fcf5ef2aSThomas Huth /* op_helper.c */ 2208fcf5ef2aSThomas Huth /* used for debug or cpu save/restore */ 2209fcf5ef2aSThomas Huth 2210fcf5ef2aSThomas Huth /* cpu-exec.c */ 2211fcf5ef2aSThomas Huth /* the following helpers are only usable in user mode simulation as 2212fcf5ef2aSThomas Huth they can trigger unexpected exceptions */ 2213c117e5b1SPhilippe Mathieu-Daudé void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); 2214fcf5ef2aSThomas Huth void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 2215fcf5ef2aSThomas Huth void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 22161c1df019SPranith Kumar void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 22171c1df019SPranith Kumar void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 22185d245678SPaolo Bonzini void cpu_x86_xsave(CPUX86State *s, target_ulong ptr); 22195d245678SPaolo Bonzini void cpu_x86_xrstor(CPUX86State *s, target_ulong ptr); 2220fcf5ef2aSThomas Huth 2221fcf5ef2aSThomas Huth /* cpu.c */ 2222f5cc5a5cSClaudio Fontana void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 2223f5cc5a5cSClaudio Fontana uint32_t vendor2, uint32_t vendor3); 2224f5cc5a5cSClaudio Fontana typedef struct PropValue { 2225f5cc5a5cSClaudio Fontana const char *prop, *value; 2226f5cc5a5cSClaudio Fontana } PropValue; 2227f5cc5a5cSClaudio Fontana void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); 2228f5cc5a5cSClaudio Fontana 2229ec19444aSMaciej S. Szmigiero void x86_cpu_after_reset(X86CPU *cpu); 2230ec19444aSMaciej S. Szmigiero 223197afb47eSLara Lazier uint32_t cpu_x86_virtual_addr_width(CPUX86State *env); 223297afb47eSLara Lazier 2233f5cc5a5cSClaudio Fontana /* cpu.c other functions (cpuid) */ 2234fcf5ef2aSThomas Huth void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 2235fcf5ef2aSThomas Huth uint32_t *eax, uint32_t *ebx, 2236fcf5ef2aSThomas Huth uint32_t *ecx, uint32_t *edx); 2237fcf5ef2aSThomas Huth void cpu_clear_apic_feature(CPUX86State *env); 2238fcf5ef2aSThomas Huth void host_cpuid(uint32_t function, uint32_t count, 2239fcf5ef2aSThomas Huth uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 2240fcf5ef2aSThomas Huth 2241fcf5ef2aSThomas Huth /* helper.c */ 2242fcf5ef2aSThomas Huth void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 2243608db8dbSPaul Brook void cpu_sync_avx_hflag(CPUX86State *env); 2244fcf5ef2aSThomas Huth 2245fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 2246f8c45c65SPaolo Bonzini static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2247f8c45c65SPaolo Bonzini { 2248f8c45c65SPaolo Bonzini return !!attrs.secure; 2249f8c45c65SPaolo Bonzini } 2250f8c45c65SPaolo Bonzini 2251f8c45c65SPaolo Bonzini static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 2252f8c45c65SPaolo Bonzini { 2253f8c45c65SPaolo Bonzini return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 2254f8c45c65SPaolo Bonzini } 2255f8c45c65SPaolo Bonzini 225663087289SClaudio Fontana /* 225763087289SClaudio Fontana * load efer and update the corresponding hflags. XXX: do consistency 225863087289SClaudio Fontana * checks with cpuid bits? 225963087289SClaudio Fontana */ 226063087289SClaudio Fontana void cpu_load_efer(CPUX86State *env, uint64_t val); 2261fcf5ef2aSThomas Huth uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 2262fcf5ef2aSThomas Huth uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 2263fcf5ef2aSThomas Huth uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 2264fcf5ef2aSThomas Huth uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 2265fcf5ef2aSThomas Huth void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 2266fcf5ef2aSThomas Huth void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 2267fcf5ef2aSThomas Huth void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 2268fcf5ef2aSThomas Huth void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 2269fcf5ef2aSThomas Huth void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 2270fcf5ef2aSThomas Huth #endif 2271fcf5ef2aSThomas Huth 2272fcf5ef2aSThomas Huth /* will be suppressed */ 2273fcf5ef2aSThomas Huth void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 2274fcf5ef2aSThomas Huth void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 2275fcf5ef2aSThomas Huth void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 2276fcf5ef2aSThomas Huth void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 2277fcf5ef2aSThomas Huth 2278fcf5ef2aSThomas Huth /* hw/pc.c */ 2279fcf5ef2aSThomas Huth uint64_t cpu_get_tsc(CPUX86State *env); 2280fcf5ef2aSThomas Huth 22810dacec87SIgor Mammedov #define CPU_RESOLVING_TYPE TYPE_X86_CPU 2282311ca98dSIgor Mammedov 2283311ca98dSIgor Mammedov #ifdef TARGET_X86_64 2284311ca98dSIgor Mammedov #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 2285311ca98dSIgor Mammedov #else 2286311ca98dSIgor Mammedov #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 2287311ca98dSIgor Mammedov #endif 2288311ca98dSIgor Mammedov 2289fcf5ef2aSThomas Huth #define cpu_list x86_cpu_list 2290fcf5ef2aSThomas Huth 2291fcf5ef2aSThomas Huth /* MMU modes definitions */ 2292fcf5ef2aSThomas Huth #define MMU_KSMAP_IDX 0 2293fcf5ef2aSThomas Huth #define MMU_USER_IDX 1 2294fcf5ef2aSThomas Huth #define MMU_KNOSMAP_IDX 2 229598281984SRichard Henderson #define MMU_NESTED_IDX 3 229698281984SRichard Henderson #define MMU_PHYS_IDX 4 229798281984SRichard Henderson 2298fcf5ef2aSThomas Huth static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 2299fcf5ef2aSThomas Huth { 2300fcf5ef2aSThomas Huth return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 2301fcf5ef2aSThomas Huth (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 2302fcf5ef2aSThomas Huth ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2303fcf5ef2aSThomas Huth } 2304fcf5ef2aSThomas Huth 2305fcf5ef2aSThomas Huth static inline int cpu_mmu_index_kernel(CPUX86State *env) 2306fcf5ef2aSThomas Huth { 2307fcf5ef2aSThomas Huth return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 2308fcf5ef2aSThomas Huth ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 2309fcf5ef2aSThomas Huth ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 2310fcf5ef2aSThomas Huth } 2311fcf5ef2aSThomas Huth 2312fcf5ef2aSThomas Huth #define CC_DST (env->cc_dst) 2313fcf5ef2aSThomas Huth #define CC_SRC (env->cc_src) 2314fcf5ef2aSThomas Huth #define CC_SRC2 (env->cc_src2) 2315fcf5ef2aSThomas Huth #define CC_OP (env->cc_op) 2316fcf5ef2aSThomas Huth 2317fcf5ef2aSThomas Huth #include "exec/cpu-all.h" 2318fcf5ef2aSThomas Huth #include "svm.h" 2319fcf5ef2aSThomas Huth 2320fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2321fcf5ef2aSThomas Huth #include "hw/i386/apic.h" 2322fcf5ef2aSThomas Huth #endif 2323fcf5ef2aSThomas Huth 2324bb5de525SAnton Johansson static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, 2325bb5de525SAnton Johansson uint64_t *cs_base, uint32_t *flags) 2326fcf5ef2aSThomas Huth { 2327fcf5ef2aSThomas Huth *cs_base = env->segs[R_CS].base; 2328fcf5ef2aSThomas Huth *pc = *cs_base + env->eip; 2329fcf5ef2aSThomas Huth *flags = env->hflags | 2330fcf5ef2aSThomas Huth (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 2331fcf5ef2aSThomas Huth } 2332fcf5ef2aSThomas Huth 2333fcf5ef2aSThomas Huth void do_cpu_init(X86CPU *cpu); 2334fcf5ef2aSThomas Huth 2335fcf5ef2aSThomas Huth #define MCE_INJECT_BROADCAST 1 2336fcf5ef2aSThomas Huth #define MCE_INJECT_UNCOND_AO 2 2337fcf5ef2aSThomas Huth 2338fcf5ef2aSThomas Huth void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 2339fcf5ef2aSThomas Huth uint64_t status, uint64_t mcg_status, uint64_t addr, 2340fcf5ef2aSThomas Huth uint64_t misc, int flags); 2341fcf5ef2aSThomas Huth 2342fcf5ef2aSThomas Huth uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 2343fcf5ef2aSThomas Huth 2344fcf5ef2aSThomas Huth static inline uint32_t cpu_compute_eflags(CPUX86State *env) 2345fcf5ef2aSThomas Huth { 234679c664f6SYang Zhong uint32_t eflags = env->eflags; 234779c664f6SYang Zhong if (tcg_enabled()) { 234879c664f6SYang Zhong eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 234979c664f6SYang Zhong } 235079c664f6SYang Zhong return eflags; 2351fcf5ef2aSThomas Huth } 2352fcf5ef2aSThomas Huth 2353fcf5ef2aSThomas Huth static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 2354fcf5ef2aSThomas Huth { 2355fcf5ef2aSThomas Huth return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 2356fcf5ef2aSThomas Huth } 2357fcf5ef2aSThomas Huth 2358c8bc83a4SPaolo Bonzini static inline int32_t x86_get_a20_mask(CPUX86State *env) 2359c8bc83a4SPaolo Bonzini { 2360c8bc83a4SPaolo Bonzini if (env->hflags & HF_SMM_MASK) { 2361c8bc83a4SPaolo Bonzini return -1; 2362c8bc83a4SPaolo Bonzini } else { 2363c8bc83a4SPaolo Bonzini return env->a20_mask; 2364c8bc83a4SPaolo Bonzini } 2365c8bc83a4SPaolo Bonzini } 2366c8bc83a4SPaolo Bonzini 236718ab37baSLiran Alon static inline bool cpu_has_vmx(CPUX86State *env) 236818ab37baSLiran Alon { 236918ab37baSLiran Alon return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; 237018ab37baSLiran Alon } 237118ab37baSLiran Alon 2372b16c0e20SPaolo Bonzini static inline bool cpu_has_svm(CPUX86State *env) 2373b16c0e20SPaolo Bonzini { 2374b16c0e20SPaolo Bonzini return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; 2375b16c0e20SPaolo Bonzini } 2376b16c0e20SPaolo Bonzini 237779a197abSLiran Alon /* 237879a197abSLiran Alon * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. 237979a197abSLiran Alon * Since it was set, CR4.VMXE must remain set as long as vCPU is in 238079a197abSLiran Alon * VMX operation. This is because CR4.VMXE is one of the bits set 238179a197abSLiran Alon * in MSR_IA32_VMX_CR4_FIXED1. 238279a197abSLiran Alon * 238379a197abSLiran Alon * There is one exception to above statement when vCPU enters SMM mode. 238479a197abSLiran Alon * When a vCPU enters SMM mode, it temporarily exit VMX operation and 238579a197abSLiran Alon * may also reset CR4.VMXE during execution in SMM mode. 238679a197abSLiran Alon * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation 238779a197abSLiran Alon * and CR4.VMXE is restored to it's original value of being set. 238879a197abSLiran Alon * 238979a197abSLiran Alon * Therefore, when vCPU is not in SMM mode, we can infer whether 239079a197abSLiran Alon * VMX is being used by examining CR4.VMXE. Otherwise, we cannot 239179a197abSLiran Alon * know for certain. 239279a197abSLiran Alon */ 239379a197abSLiran Alon static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) 239479a197abSLiran Alon { 239579a197abSLiran Alon return cpu_has_vmx(env) && 239679a197abSLiran Alon ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); 239779a197abSLiran Alon } 239879a197abSLiran Alon 2399616a89eaSPaolo Bonzini /* excp_helper.c */ 2400616a89eaSPaolo Bonzini int get_pg_mode(CPUX86State *env); 2401616a89eaSPaolo Bonzini 2402fcf5ef2aSThomas Huth /* fpu_helper.c */ 24031d8ad165SYang Zhong void update_fp_status(CPUX86State *env); 24041d8ad165SYang Zhong void update_mxcsr_status(CPUX86State *env); 2405418b0f93SJoseph Myers void update_mxcsr_from_sse_status(CPUX86State *env); 24061d8ad165SYang Zhong 24071d8ad165SYang Zhong static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 24081d8ad165SYang Zhong { 24091d8ad165SYang Zhong env->mxcsr = mxcsr; 24101d8ad165SYang Zhong if (tcg_enabled()) { 24111d8ad165SYang Zhong update_mxcsr_status(env); 24121d8ad165SYang Zhong } 24131d8ad165SYang Zhong } 24141d8ad165SYang Zhong 24151d8ad165SYang Zhong static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 24161d8ad165SYang Zhong { 24171d8ad165SYang Zhong env->fpuc = fpuc; 24181d8ad165SYang Zhong if (tcg_enabled()) { 24191d8ad165SYang Zhong update_fp_status(env); 24201d8ad165SYang Zhong } 24211d8ad165SYang Zhong } 2422fcf5ef2aSThomas Huth 2423fcf5ef2aSThomas Huth /* svm_helper.c */ 242427bd3216SRichard Henderson #ifdef CONFIG_USER_ONLY 242527bd3216SRichard Henderson static inline void 242627bd3216SRichard Henderson cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 242727bd3216SRichard Henderson uint64_t param, uintptr_t retaddr) 242827bd3216SRichard Henderson { /* no-op */ } 2429813c6459SLara Lazier static inline bool 2430813c6459SLara Lazier cpu_svm_has_intercept(CPUX86State *env, uint32_t type) 2431813c6459SLara Lazier { return false; } 243227bd3216SRichard Henderson #else 2433fcf5ef2aSThomas Huth void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 243465c9d60aSPaolo Bonzini uint64_t param, uintptr_t retaddr); 2435813c6459SLara Lazier bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); 243627bd3216SRichard Henderson #endif 243727bd3216SRichard Henderson 2438fcf5ef2aSThomas Huth /* apic.c */ 2439fcf5ef2aSThomas Huth void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 2440fcf5ef2aSThomas Huth void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 2441fcf5ef2aSThomas Huth TPRAccess access); 2442fcf5ef2aSThomas Huth 2443dcafd1efSEduardo Habkost /* Special values for X86CPUVersion: */ 2444dcafd1efSEduardo Habkost 2445dcafd1efSEduardo Habkost /* Resolve to latest CPU version */ 2446dcafd1efSEduardo Habkost #define CPU_VERSION_LATEST -1 2447dcafd1efSEduardo Habkost 24480788a56bSEduardo Habkost /* 24490788a56bSEduardo Habkost * Resolve to version defined by current machine type. 24500788a56bSEduardo Habkost * See x86_cpu_set_default_version() 24510788a56bSEduardo Habkost */ 24520788a56bSEduardo Habkost #define CPU_VERSION_AUTO -2 24530788a56bSEduardo Habkost 2454dcafd1efSEduardo Habkost /* Don't resolve to any versioned CPU models, like old QEMU versions */ 2455dcafd1efSEduardo Habkost #define CPU_VERSION_LEGACY 0 2456dcafd1efSEduardo Habkost 2457dcafd1efSEduardo Habkost typedef int X86CPUVersion; 2458dcafd1efSEduardo Habkost 24590788a56bSEduardo Habkost /* 24600788a56bSEduardo Habkost * Set default CPU model version for CPU models having 24610788a56bSEduardo Habkost * version == CPU_VERSION_AUTO. 24620788a56bSEduardo Habkost */ 24630788a56bSEduardo Habkost void x86_cpu_set_default_version(X86CPUVersion version); 24640788a56bSEduardo Habkost 2465b5c6a3c1SPhilippe Mathieu-Daudé #ifndef CONFIG_USER_ONLY 2466b5c6a3c1SPhilippe Mathieu-Daudé 24673b8484c5SPhilippe Mathieu-Daudé void do_cpu_sipi(X86CPU *cpu); 24683b8484c5SPhilippe Mathieu-Daudé 2469fcf5ef2aSThomas Huth #define APIC_DEFAULT_ADDRESS 0xfee00000 2470fcf5ef2aSThomas Huth #define APIC_SPACE_SIZE 0x100000 2471fcf5ef2aSThomas Huth 24720c36af8cSClaudio Fontana /* cpu-dump.c */ 2473d3fd9e4bSMarkus Armbruster void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); 2474fcf5ef2aSThomas Huth 2475b5c6a3c1SPhilippe Mathieu-Daudé #endif 2476b5c6a3c1SPhilippe Mathieu-Daudé 2477fcf5ef2aSThomas Huth /* cpu.c */ 2478fcf5ef2aSThomas Huth bool cpu_is_bsp(X86CPU *cpu); 2479fcf5ef2aSThomas Huth 2480c0198c5fSDavid Edmondson void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen); 2481c0198c5fSDavid Edmondson void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); 24825d245678SPaolo Bonzini uint32_t xsave_area_size(uint64_t mask, bool compacted); 248335b1b927STao Wu void x86_update_hflags(CPUX86State* env); 248435b1b927STao Wu 24852d384d7cSVitaly Kuznetsov static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) 24862d384d7cSVitaly Kuznetsov { 24872d384d7cSVitaly Kuznetsov return !!(cpu->hyperv_features & BIT(feat)); 24882d384d7cSVitaly Kuznetsov } 24892d384d7cSVitaly Kuznetsov 2490213ff024SLara Lazier static inline uint64_t cr4_reserved_bits(CPUX86State *env) 2491213ff024SLara Lazier { 2492213ff024SLara Lazier uint64_t reserved_bits = CR4_RESERVED_MASK; 2493213ff024SLara Lazier if (!env->features[FEAT_XSAVE]) { 2494213ff024SLara Lazier reserved_bits |= CR4_OSXSAVE_MASK; 2495213ff024SLara Lazier } 2496213ff024SLara Lazier if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) { 2497213ff024SLara Lazier reserved_bits |= CR4_SMEP_MASK; 2498213ff024SLara Lazier } 2499213ff024SLara Lazier if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { 2500213ff024SLara Lazier reserved_bits |= CR4_SMAP_MASK; 2501213ff024SLara Lazier } 2502213ff024SLara Lazier if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) { 2503213ff024SLara Lazier reserved_bits |= CR4_FSGSBASE_MASK; 2504213ff024SLara Lazier } 2505213ff024SLara Lazier if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { 2506213ff024SLara Lazier reserved_bits |= CR4_PKE_MASK; 2507213ff024SLara Lazier } 2508213ff024SLara Lazier if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) { 2509213ff024SLara Lazier reserved_bits |= CR4_LA57_MASK; 2510213ff024SLara Lazier } 2511213ff024SLara Lazier if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { 2512213ff024SLara Lazier reserved_bits |= CR4_UMIP_MASK; 2513213ff024SLara Lazier } 2514213ff024SLara Lazier if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { 2515213ff024SLara Lazier reserved_bits |= CR4_PKS_MASK; 2516213ff024SLara Lazier } 2517213ff024SLara Lazier return reserved_bits; 2518213ff024SLara Lazier } 2519213ff024SLara Lazier 25207760bb06SLara Lazier static inline bool ctl_has_irq(CPUX86State *env) 25217760bb06SLara Lazier { 25227760bb06SLara Lazier uint32_t int_prio; 25237760bb06SLara Lazier uint32_t tpr; 25247760bb06SLara Lazier 25257760bb06SLara Lazier int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; 25267760bb06SLara Lazier tpr = env->int_ctl & V_TPR_MASK; 25277760bb06SLara Lazier 25287760bb06SLara Lazier if (env->int_ctl & V_IGN_TPR_MASK) { 25297760bb06SLara Lazier return (env->int_ctl & V_IRQ_MASK); 25307760bb06SLara Lazier } 25317760bb06SLara Lazier 25327760bb06SLara Lazier return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr); 25337760bb06SLara Lazier } 25347760bb06SLara Lazier 2535b26491b4SRichard Henderson #if defined(TARGET_X86_64) && \ 2536b26491b4SRichard Henderson defined(CONFIG_USER_ONLY) && \ 2537b26491b4SRichard Henderson defined(CONFIG_LINUX) 2538b26491b4SRichard Henderson # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) 2539b26491b4SRichard Henderson #endif 2540b26491b4SRichard Henderson 2541fcf5ef2aSThomas Huth #endif /* I386_CPU_H */ 2542