1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * i386 virtual CPU header 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003 Fabrice Bellard 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18fcf5ef2aSThomas Huth */ 19fcf5ef2aSThomas Huth 20fcf5ef2aSThomas Huth #ifndef I386_CPU_H 21fcf5ef2aSThomas Huth #define I386_CPU_H 22fcf5ef2aSThomas Huth 23fcf5ef2aSThomas Huth #include "qemu-common.h" 24fcf5ef2aSThomas Huth #include "cpu-qom.h" 25fcf5ef2aSThomas Huth #include "standard-headers/asm-x86/hyperv.h" 26fcf5ef2aSThomas Huth 27fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 28fcf5ef2aSThomas Huth #define TARGET_LONG_BITS 64 29fcf5ef2aSThomas Huth #else 30fcf5ef2aSThomas Huth #define TARGET_LONG_BITS 32 31fcf5ef2aSThomas Huth #endif 32fcf5ef2aSThomas Huth 3372c1701fSAlex Bennée /* The x86 has a strong memory model with some store-after-load re-ordering */ 3472c1701fSAlex Bennée #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 3572c1701fSAlex Bennée 36fcf5ef2aSThomas Huth /* Maximum instruction code size */ 37fcf5ef2aSThomas Huth #define TARGET_MAX_INSN_SIZE 16 38fcf5ef2aSThomas Huth 39fcf5ef2aSThomas Huth /* support for self modifying code even if the modified instruction is 40fcf5ef2aSThomas Huth close to the modifying instruction */ 41fcf5ef2aSThomas Huth #define TARGET_HAS_PRECISE_SMC 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 44fcf5ef2aSThomas Huth #define I386_ELF_MACHINE EM_X86_64 45fcf5ef2aSThomas Huth #define ELF_MACHINE_UNAME "x86_64" 46fcf5ef2aSThomas Huth #else 47fcf5ef2aSThomas Huth #define I386_ELF_MACHINE EM_386 48fcf5ef2aSThomas Huth #define ELF_MACHINE_UNAME "i686" 49fcf5ef2aSThomas Huth #endif 50fcf5ef2aSThomas Huth 51fcf5ef2aSThomas Huth #define CPUArchState struct CPUX86State 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth #include "exec/cpu-defs.h" 54fcf5ef2aSThomas Huth 5579c664f6SYang Zhong #ifdef CONFIG_TCG 56fcf5ef2aSThomas Huth #include "fpu/softfloat.h" 5779c664f6SYang Zhong #endif 58fcf5ef2aSThomas Huth 59fcf5ef2aSThomas Huth #define R_EAX 0 60fcf5ef2aSThomas Huth #define R_ECX 1 61fcf5ef2aSThomas Huth #define R_EDX 2 62fcf5ef2aSThomas Huth #define R_EBX 3 63fcf5ef2aSThomas Huth #define R_ESP 4 64fcf5ef2aSThomas Huth #define R_EBP 5 65fcf5ef2aSThomas Huth #define R_ESI 6 66fcf5ef2aSThomas Huth #define R_EDI 7 67fcf5ef2aSThomas Huth 68fcf5ef2aSThomas Huth #define R_AL 0 69fcf5ef2aSThomas Huth #define R_CL 1 70fcf5ef2aSThomas Huth #define R_DL 2 71fcf5ef2aSThomas Huth #define R_BL 3 72fcf5ef2aSThomas Huth #define R_AH 4 73fcf5ef2aSThomas Huth #define R_CH 5 74fcf5ef2aSThomas Huth #define R_DH 6 75fcf5ef2aSThomas Huth #define R_BH 7 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #define R_ES 0 78fcf5ef2aSThomas Huth #define R_CS 1 79fcf5ef2aSThomas Huth #define R_SS 2 80fcf5ef2aSThomas Huth #define R_DS 3 81fcf5ef2aSThomas Huth #define R_FS 4 82fcf5ef2aSThomas Huth #define R_GS 5 83fcf5ef2aSThomas Huth 84fcf5ef2aSThomas Huth /* segment descriptor fields */ 85fcf5ef2aSThomas Huth #define DESC_G_MASK (1 << 23) 86fcf5ef2aSThomas Huth #define DESC_B_SHIFT 22 87fcf5ef2aSThomas Huth #define DESC_B_MASK (1 << DESC_B_SHIFT) 88fcf5ef2aSThomas Huth #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 89fcf5ef2aSThomas Huth #define DESC_L_MASK (1 << DESC_L_SHIFT) 90fcf5ef2aSThomas Huth #define DESC_AVL_MASK (1 << 20) 91fcf5ef2aSThomas Huth #define DESC_P_MASK (1 << 15) 92fcf5ef2aSThomas Huth #define DESC_DPL_SHIFT 13 93fcf5ef2aSThomas Huth #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 94fcf5ef2aSThomas Huth #define DESC_S_MASK (1 << 12) 95fcf5ef2aSThomas Huth #define DESC_TYPE_SHIFT 8 96fcf5ef2aSThomas Huth #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 97fcf5ef2aSThomas Huth #define DESC_A_MASK (1 << 8) 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 100fcf5ef2aSThomas Huth #define DESC_C_MASK (1 << 10) /* code: conforming */ 101fcf5ef2aSThomas Huth #define DESC_R_MASK (1 << 9) /* code: readable */ 102fcf5ef2aSThomas Huth 103fcf5ef2aSThomas Huth #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 104fcf5ef2aSThomas Huth #define DESC_W_MASK (1 << 9) /* data: writable */ 105fcf5ef2aSThomas Huth 106fcf5ef2aSThomas Huth #define DESC_TSS_BUSY_MASK (1 << 9) 107fcf5ef2aSThomas Huth 108fcf5ef2aSThomas Huth /* eflags masks */ 109fcf5ef2aSThomas Huth #define CC_C 0x0001 110fcf5ef2aSThomas Huth #define CC_P 0x0004 111fcf5ef2aSThomas Huth #define CC_A 0x0010 112fcf5ef2aSThomas Huth #define CC_Z 0x0040 113fcf5ef2aSThomas Huth #define CC_S 0x0080 114fcf5ef2aSThomas Huth #define CC_O 0x0800 115fcf5ef2aSThomas Huth 116fcf5ef2aSThomas Huth #define TF_SHIFT 8 117fcf5ef2aSThomas Huth #define IOPL_SHIFT 12 118fcf5ef2aSThomas Huth #define VM_SHIFT 17 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth #define TF_MASK 0x00000100 121fcf5ef2aSThomas Huth #define IF_MASK 0x00000200 122fcf5ef2aSThomas Huth #define DF_MASK 0x00000400 123fcf5ef2aSThomas Huth #define IOPL_MASK 0x00003000 124fcf5ef2aSThomas Huth #define NT_MASK 0x00004000 125fcf5ef2aSThomas Huth #define RF_MASK 0x00010000 126fcf5ef2aSThomas Huth #define VM_MASK 0x00020000 127fcf5ef2aSThomas Huth #define AC_MASK 0x00040000 128fcf5ef2aSThomas Huth #define VIF_MASK 0x00080000 129fcf5ef2aSThomas Huth #define VIP_MASK 0x00100000 130fcf5ef2aSThomas Huth #define ID_MASK 0x00200000 131fcf5ef2aSThomas Huth 132fcf5ef2aSThomas Huth /* hidden flags - used internally by qemu to represent additional cpu 133fcf5ef2aSThomas Huth states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We 134fcf5ef2aSThomas Huth avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit 135fcf5ef2aSThomas Huth positions to ease oring with eflags. */ 136fcf5ef2aSThomas Huth /* current cpl */ 137fcf5ef2aSThomas Huth #define HF_CPL_SHIFT 0 138fcf5ef2aSThomas Huth /* true if hardware interrupts must be disabled for next instruction */ 139fcf5ef2aSThomas Huth #define HF_INHIBIT_IRQ_SHIFT 3 140fcf5ef2aSThomas Huth /* 16 or 32 segments */ 141fcf5ef2aSThomas Huth #define HF_CS32_SHIFT 4 142fcf5ef2aSThomas Huth #define HF_SS32_SHIFT 5 143fcf5ef2aSThomas Huth /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 144fcf5ef2aSThomas Huth #define HF_ADDSEG_SHIFT 6 145fcf5ef2aSThomas Huth /* copy of CR0.PE (protected mode) */ 146fcf5ef2aSThomas Huth #define HF_PE_SHIFT 7 147fcf5ef2aSThomas Huth #define HF_TF_SHIFT 8 /* must be same as eflags */ 148fcf5ef2aSThomas Huth #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 149fcf5ef2aSThomas Huth #define HF_EM_SHIFT 10 150fcf5ef2aSThomas Huth #define HF_TS_SHIFT 11 151fcf5ef2aSThomas Huth #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 152fcf5ef2aSThomas Huth #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 153fcf5ef2aSThomas Huth #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 154fcf5ef2aSThomas Huth #define HF_RF_SHIFT 16 /* must be same as eflags */ 155fcf5ef2aSThomas Huth #define HF_VM_SHIFT 17 /* must be same as eflags */ 156fcf5ef2aSThomas Huth #define HF_AC_SHIFT 18 /* must be same as eflags */ 157fcf5ef2aSThomas Huth #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 158fcf5ef2aSThomas Huth #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 159fcf5ef2aSThomas Huth #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 160fcf5ef2aSThomas Huth #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 161fcf5ef2aSThomas Huth #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 162fcf5ef2aSThomas Huth #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ 163fcf5ef2aSThomas Huth #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ 164fcf5ef2aSThomas Huth #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ 165fcf5ef2aSThomas Huth 166fcf5ef2aSThomas Huth #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 167fcf5ef2aSThomas Huth #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 168fcf5ef2aSThomas Huth #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 169fcf5ef2aSThomas Huth #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 170fcf5ef2aSThomas Huth #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 171fcf5ef2aSThomas Huth #define HF_PE_MASK (1 << HF_PE_SHIFT) 172fcf5ef2aSThomas Huth #define HF_TF_MASK (1 << HF_TF_SHIFT) 173fcf5ef2aSThomas Huth #define HF_MP_MASK (1 << HF_MP_SHIFT) 174fcf5ef2aSThomas Huth #define HF_EM_MASK (1 << HF_EM_SHIFT) 175fcf5ef2aSThomas Huth #define HF_TS_MASK (1 << HF_TS_SHIFT) 176fcf5ef2aSThomas Huth #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 177fcf5ef2aSThomas Huth #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 178fcf5ef2aSThomas Huth #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 179fcf5ef2aSThomas Huth #define HF_RF_MASK (1 << HF_RF_SHIFT) 180fcf5ef2aSThomas Huth #define HF_VM_MASK (1 << HF_VM_SHIFT) 181fcf5ef2aSThomas Huth #define HF_AC_MASK (1 << HF_AC_SHIFT) 182fcf5ef2aSThomas Huth #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 183fcf5ef2aSThomas Huth #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 184fcf5ef2aSThomas Huth #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 185fcf5ef2aSThomas Huth #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 186fcf5ef2aSThomas Huth #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 187fcf5ef2aSThomas Huth #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) 188fcf5ef2aSThomas Huth #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) 189fcf5ef2aSThomas Huth #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) 190fcf5ef2aSThomas Huth 191fcf5ef2aSThomas Huth /* hflags2 */ 192fcf5ef2aSThomas Huth 193fcf5ef2aSThomas Huth #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 194fcf5ef2aSThomas Huth #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 195fcf5ef2aSThomas Huth #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 196fcf5ef2aSThomas Huth #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 197fcf5ef2aSThomas Huth #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ 198fcf5ef2aSThomas Huth #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ 199fcf5ef2aSThomas Huth 200fcf5ef2aSThomas Huth #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 201fcf5ef2aSThomas Huth #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 202fcf5ef2aSThomas Huth #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 203fcf5ef2aSThomas Huth #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 204fcf5ef2aSThomas Huth #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) 205fcf5ef2aSThomas Huth #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) 206fcf5ef2aSThomas Huth 207fcf5ef2aSThomas Huth #define CR0_PE_SHIFT 0 208fcf5ef2aSThomas Huth #define CR0_MP_SHIFT 1 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth #define CR0_PE_MASK (1U << 0) 211fcf5ef2aSThomas Huth #define CR0_MP_MASK (1U << 1) 212fcf5ef2aSThomas Huth #define CR0_EM_MASK (1U << 2) 213fcf5ef2aSThomas Huth #define CR0_TS_MASK (1U << 3) 214fcf5ef2aSThomas Huth #define CR0_ET_MASK (1U << 4) 215fcf5ef2aSThomas Huth #define CR0_NE_MASK (1U << 5) 216fcf5ef2aSThomas Huth #define CR0_WP_MASK (1U << 16) 217fcf5ef2aSThomas Huth #define CR0_AM_MASK (1U << 18) 218fcf5ef2aSThomas Huth #define CR0_PG_MASK (1U << 31) 219fcf5ef2aSThomas Huth 220fcf5ef2aSThomas Huth #define CR4_VME_MASK (1U << 0) 221fcf5ef2aSThomas Huth #define CR4_PVI_MASK (1U << 1) 222fcf5ef2aSThomas Huth #define CR4_TSD_MASK (1U << 2) 223fcf5ef2aSThomas Huth #define CR4_DE_MASK (1U << 3) 224fcf5ef2aSThomas Huth #define CR4_PSE_MASK (1U << 4) 225fcf5ef2aSThomas Huth #define CR4_PAE_MASK (1U << 5) 226fcf5ef2aSThomas Huth #define CR4_MCE_MASK (1U << 6) 227fcf5ef2aSThomas Huth #define CR4_PGE_MASK (1U << 7) 228fcf5ef2aSThomas Huth #define CR4_PCE_MASK (1U << 8) 229fcf5ef2aSThomas Huth #define CR4_OSFXSR_SHIFT 9 230fcf5ef2aSThomas Huth #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) 231fcf5ef2aSThomas Huth #define CR4_OSXMMEXCPT_MASK (1U << 10) 2326c7c3c21SKirill A. Shutemov #define CR4_LA57_MASK (1U << 12) 233fcf5ef2aSThomas Huth #define CR4_VMXE_MASK (1U << 13) 234fcf5ef2aSThomas Huth #define CR4_SMXE_MASK (1U << 14) 235fcf5ef2aSThomas Huth #define CR4_FSGSBASE_MASK (1U << 16) 236fcf5ef2aSThomas Huth #define CR4_PCIDE_MASK (1U << 17) 237fcf5ef2aSThomas Huth #define CR4_OSXSAVE_MASK (1U << 18) 238fcf5ef2aSThomas Huth #define CR4_SMEP_MASK (1U << 20) 239fcf5ef2aSThomas Huth #define CR4_SMAP_MASK (1U << 21) 240fcf5ef2aSThomas Huth #define CR4_PKE_MASK (1U << 22) 241fcf5ef2aSThomas Huth 242fcf5ef2aSThomas Huth #define DR6_BD (1 << 13) 243fcf5ef2aSThomas Huth #define DR6_BS (1 << 14) 244fcf5ef2aSThomas Huth #define DR6_BT (1 << 15) 245fcf5ef2aSThomas Huth #define DR6_FIXED_1 0xffff0ff0 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth #define DR7_GD (1 << 13) 248fcf5ef2aSThomas Huth #define DR7_TYPE_SHIFT 16 249fcf5ef2aSThomas Huth #define DR7_LEN_SHIFT 18 250fcf5ef2aSThomas Huth #define DR7_FIXED_1 0x00000400 251fcf5ef2aSThomas Huth #define DR7_GLOBAL_BP_MASK 0xaa 252fcf5ef2aSThomas Huth #define DR7_LOCAL_BP_MASK 0x55 253fcf5ef2aSThomas Huth #define DR7_MAX_BP 4 254fcf5ef2aSThomas Huth #define DR7_TYPE_BP_INST 0x0 255fcf5ef2aSThomas Huth #define DR7_TYPE_DATA_WR 0x1 256fcf5ef2aSThomas Huth #define DR7_TYPE_IO_RW 0x2 257fcf5ef2aSThomas Huth #define DR7_TYPE_DATA_RW 0x3 258fcf5ef2aSThomas Huth 259fcf5ef2aSThomas Huth #define PG_PRESENT_BIT 0 260fcf5ef2aSThomas Huth #define PG_RW_BIT 1 261fcf5ef2aSThomas Huth #define PG_USER_BIT 2 262fcf5ef2aSThomas Huth #define PG_PWT_BIT 3 263fcf5ef2aSThomas Huth #define PG_PCD_BIT 4 264fcf5ef2aSThomas Huth #define PG_ACCESSED_BIT 5 265fcf5ef2aSThomas Huth #define PG_DIRTY_BIT 6 266fcf5ef2aSThomas Huth #define PG_PSE_BIT 7 267fcf5ef2aSThomas Huth #define PG_GLOBAL_BIT 8 268fcf5ef2aSThomas Huth #define PG_PSE_PAT_BIT 12 269fcf5ef2aSThomas Huth #define PG_PKRU_BIT 59 270fcf5ef2aSThomas Huth #define PG_NX_BIT 63 271fcf5ef2aSThomas Huth 272fcf5ef2aSThomas Huth #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 273fcf5ef2aSThomas Huth #define PG_RW_MASK (1 << PG_RW_BIT) 274fcf5ef2aSThomas Huth #define PG_USER_MASK (1 << PG_USER_BIT) 275fcf5ef2aSThomas Huth #define PG_PWT_MASK (1 << PG_PWT_BIT) 276fcf5ef2aSThomas Huth #define PG_PCD_MASK (1 << PG_PCD_BIT) 277fcf5ef2aSThomas Huth #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 278fcf5ef2aSThomas Huth #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 279fcf5ef2aSThomas Huth #define PG_PSE_MASK (1 << PG_PSE_BIT) 280fcf5ef2aSThomas Huth #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 281fcf5ef2aSThomas Huth #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) 282fcf5ef2aSThomas Huth #define PG_ADDRESS_MASK 0x000ffffffffff000LL 283fcf5ef2aSThomas Huth #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) 284fcf5ef2aSThomas Huth #define PG_HI_USER_MASK 0x7ff0000000000000LL 285fcf5ef2aSThomas Huth #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) 286fcf5ef2aSThomas Huth #define PG_NX_MASK (1ULL << PG_NX_BIT) 287fcf5ef2aSThomas Huth 288fcf5ef2aSThomas Huth #define PG_ERROR_W_BIT 1 289fcf5ef2aSThomas Huth 290fcf5ef2aSThomas Huth #define PG_ERROR_P_MASK 0x01 291fcf5ef2aSThomas Huth #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 292fcf5ef2aSThomas Huth #define PG_ERROR_U_MASK 0x04 293fcf5ef2aSThomas Huth #define PG_ERROR_RSVD_MASK 0x08 294fcf5ef2aSThomas Huth #define PG_ERROR_I_D_MASK 0x10 295fcf5ef2aSThomas Huth #define PG_ERROR_PK_MASK 0x20 296fcf5ef2aSThomas Huth 297fcf5ef2aSThomas Huth #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 298fcf5ef2aSThomas Huth #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 299fcf5ef2aSThomas Huth #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ 300fcf5ef2aSThomas Huth 301fcf5ef2aSThomas Huth #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) 302fcf5ef2aSThomas Huth #define MCE_BANKS_DEF 10 303fcf5ef2aSThomas Huth 304fcf5ef2aSThomas Huth #define MCG_CAP_BANKS_MASK 0xff 305fcf5ef2aSThomas Huth 306fcf5ef2aSThomas Huth #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 307fcf5ef2aSThomas Huth #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 308fcf5ef2aSThomas Huth #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 309fcf5ef2aSThomas Huth #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ 310fcf5ef2aSThomas Huth 311fcf5ef2aSThomas Huth #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ 312fcf5ef2aSThomas Huth 313fcf5ef2aSThomas Huth #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 314fcf5ef2aSThomas Huth #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 315fcf5ef2aSThomas Huth #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 316fcf5ef2aSThomas Huth #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 317fcf5ef2aSThomas Huth #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 318fcf5ef2aSThomas Huth #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 319fcf5ef2aSThomas Huth #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 320fcf5ef2aSThomas Huth #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 321fcf5ef2aSThomas Huth #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 322fcf5ef2aSThomas Huth 323fcf5ef2aSThomas Huth /* MISC register defines */ 324fcf5ef2aSThomas Huth #define MCM_ADDR_SEGOFF 0 /* segment offset */ 325fcf5ef2aSThomas Huth #define MCM_ADDR_LINEAR 1 /* linear address */ 326fcf5ef2aSThomas Huth #define MCM_ADDR_PHYS 2 /* physical address */ 327fcf5ef2aSThomas Huth #define MCM_ADDR_MEM 3 /* memory address */ 328fcf5ef2aSThomas Huth #define MCM_ADDR_GENERIC 7 /* generic */ 329fcf5ef2aSThomas Huth 330fcf5ef2aSThomas Huth #define MSR_IA32_TSC 0x10 331fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE 0x1b 332fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_BSP (1<<8) 333fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_ENABLE (1<<11) 334fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_EXTD (1 << 10) 335fcf5ef2aSThomas Huth #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) 336fcf5ef2aSThomas Huth #define MSR_IA32_FEATURE_CONTROL 0x0000003a 337fcf5ef2aSThomas Huth #define MSR_TSC_ADJUST 0x0000003b 338fcf5ef2aSThomas Huth #define MSR_IA32_TSCDEADLINE 0x6e0 339fcf5ef2aSThomas Huth 340fcf5ef2aSThomas Huth #define FEATURE_CONTROL_LOCKED (1<<0) 341fcf5ef2aSThomas Huth #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 342fcf5ef2aSThomas Huth #define FEATURE_CONTROL_LMCE (1<<20) 343fcf5ef2aSThomas Huth 344fcf5ef2aSThomas Huth #define MSR_P6_PERFCTR0 0xc1 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth #define MSR_IA32_SMBASE 0x9e 347fcf5ef2aSThomas Huth #define MSR_MTRRcap 0xfe 348fcf5ef2aSThomas Huth #define MSR_MTRRcap_VCNT 8 349fcf5ef2aSThomas Huth #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 350fcf5ef2aSThomas Huth #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 351fcf5ef2aSThomas Huth 352fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_CS 0x174 353fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_ESP 0x175 354fcf5ef2aSThomas Huth #define MSR_IA32_SYSENTER_EIP 0x176 355fcf5ef2aSThomas Huth 356fcf5ef2aSThomas Huth #define MSR_MCG_CAP 0x179 357fcf5ef2aSThomas Huth #define MSR_MCG_STATUS 0x17a 358fcf5ef2aSThomas Huth #define MSR_MCG_CTL 0x17b 359fcf5ef2aSThomas Huth #define MSR_MCG_EXT_CTL 0x4d0 360fcf5ef2aSThomas Huth 361fcf5ef2aSThomas Huth #define MSR_P6_EVNTSEL0 0x186 362fcf5ef2aSThomas Huth 363fcf5ef2aSThomas Huth #define MSR_IA32_PERF_STATUS 0x198 364fcf5ef2aSThomas Huth 365fcf5ef2aSThomas Huth #define MSR_IA32_MISC_ENABLE 0x1a0 366fcf5ef2aSThomas Huth /* Indicates good rep/movs microcode on some processors: */ 367fcf5ef2aSThomas Huth #define MSR_IA32_MISC_ENABLE_DEFAULT 1 368fcf5ef2aSThomas Huth 369fcf5ef2aSThomas Huth #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 370fcf5ef2aSThomas Huth #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 371fcf5ef2aSThomas Huth 372fcf5ef2aSThomas Huth #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) 373fcf5ef2aSThomas Huth 374fcf5ef2aSThomas Huth #define MSR_MTRRfix64K_00000 0x250 375fcf5ef2aSThomas Huth #define MSR_MTRRfix16K_80000 0x258 376fcf5ef2aSThomas Huth #define MSR_MTRRfix16K_A0000 0x259 377fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_C0000 0x268 378fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_C8000 0x269 379fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_D0000 0x26a 380fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_D8000 0x26b 381fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_E0000 0x26c 382fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_E8000 0x26d 383fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_F0000 0x26e 384fcf5ef2aSThomas Huth #define MSR_MTRRfix4K_F8000 0x26f 385fcf5ef2aSThomas Huth 386fcf5ef2aSThomas Huth #define MSR_PAT 0x277 387fcf5ef2aSThomas Huth 388fcf5ef2aSThomas Huth #define MSR_MTRRdefType 0x2ff 389fcf5ef2aSThomas Huth 390fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR0 0x309 391fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR1 0x30a 392fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR2 0x30b 393fcf5ef2aSThomas Huth #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 394fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 395fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 396fcf5ef2aSThomas Huth #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 397fcf5ef2aSThomas Huth 398fcf5ef2aSThomas Huth #define MSR_MC0_CTL 0x400 399fcf5ef2aSThomas Huth #define MSR_MC0_STATUS 0x401 400fcf5ef2aSThomas Huth #define MSR_MC0_ADDR 0x402 401fcf5ef2aSThomas Huth #define MSR_MC0_MISC 0x403 402fcf5ef2aSThomas Huth 403fcf5ef2aSThomas Huth #define MSR_EFER 0xc0000080 404fcf5ef2aSThomas Huth 405fcf5ef2aSThomas Huth #define MSR_EFER_SCE (1 << 0) 406fcf5ef2aSThomas Huth #define MSR_EFER_LME (1 << 8) 407fcf5ef2aSThomas Huth #define MSR_EFER_LMA (1 << 10) 408fcf5ef2aSThomas Huth #define MSR_EFER_NXE (1 << 11) 409fcf5ef2aSThomas Huth #define MSR_EFER_SVME (1 << 12) 410fcf5ef2aSThomas Huth #define MSR_EFER_FFXSR (1 << 14) 411fcf5ef2aSThomas Huth 412fcf5ef2aSThomas Huth #define MSR_STAR 0xc0000081 413fcf5ef2aSThomas Huth #define MSR_LSTAR 0xc0000082 414fcf5ef2aSThomas Huth #define MSR_CSTAR 0xc0000083 415fcf5ef2aSThomas Huth #define MSR_FMASK 0xc0000084 416fcf5ef2aSThomas Huth #define MSR_FSBASE 0xc0000100 417fcf5ef2aSThomas Huth #define MSR_GSBASE 0xc0000101 418fcf5ef2aSThomas Huth #define MSR_KERNELGSBASE 0xc0000102 419fcf5ef2aSThomas Huth #define MSR_TSC_AUX 0xc0000103 420fcf5ef2aSThomas Huth 421fcf5ef2aSThomas Huth #define MSR_VM_HSAVE_PA 0xc0010117 422fcf5ef2aSThomas Huth 423fcf5ef2aSThomas Huth #define MSR_IA32_BNDCFGS 0x00000d90 424fcf5ef2aSThomas Huth #define MSR_IA32_XSS 0x00000da0 425fcf5ef2aSThomas Huth 426fcf5ef2aSThomas Huth #define XSTATE_FP_BIT 0 427fcf5ef2aSThomas Huth #define XSTATE_SSE_BIT 1 428fcf5ef2aSThomas Huth #define XSTATE_YMM_BIT 2 429fcf5ef2aSThomas Huth #define XSTATE_BNDREGS_BIT 3 430fcf5ef2aSThomas Huth #define XSTATE_BNDCSR_BIT 4 431fcf5ef2aSThomas Huth #define XSTATE_OPMASK_BIT 5 432fcf5ef2aSThomas Huth #define XSTATE_ZMM_Hi256_BIT 6 433fcf5ef2aSThomas Huth #define XSTATE_Hi16_ZMM_BIT 7 434fcf5ef2aSThomas Huth #define XSTATE_PKRU_BIT 9 435fcf5ef2aSThomas Huth 436fcf5ef2aSThomas Huth #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) 437fcf5ef2aSThomas Huth #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) 438fcf5ef2aSThomas Huth #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) 439fcf5ef2aSThomas Huth #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) 440fcf5ef2aSThomas Huth #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) 441fcf5ef2aSThomas Huth #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) 442fcf5ef2aSThomas Huth #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) 443fcf5ef2aSThomas Huth #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) 444fcf5ef2aSThomas Huth #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) 445fcf5ef2aSThomas Huth 446fcf5ef2aSThomas Huth /* CPUID feature words */ 447fcf5ef2aSThomas Huth typedef enum FeatureWord { 448fcf5ef2aSThomas Huth FEAT_1_EDX, /* CPUID[1].EDX */ 449fcf5ef2aSThomas Huth FEAT_1_ECX, /* CPUID[1].ECX */ 450fcf5ef2aSThomas Huth FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 451fcf5ef2aSThomas Huth FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ 452fcf5ef2aSThomas Huth FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ 453fcf5ef2aSThomas Huth FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 454fcf5ef2aSThomas Huth FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 455fcf5ef2aSThomas Huth FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ 456fcf5ef2aSThomas Huth FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 457fcf5ef2aSThomas Huth FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 458fcf5ef2aSThomas Huth FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ 459fcf5ef2aSThomas Huth FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ 460fcf5ef2aSThomas Huth FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ 461fcf5ef2aSThomas Huth FEAT_SVM, /* CPUID[8000_000A].EDX */ 462fcf5ef2aSThomas Huth FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ 463fcf5ef2aSThomas Huth FEAT_6_EAX, /* CPUID[6].EAX */ 464fcf5ef2aSThomas Huth FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ 465fcf5ef2aSThomas Huth FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ 466fcf5ef2aSThomas Huth FEATURE_WORDS, 467fcf5ef2aSThomas Huth } FeatureWord; 468fcf5ef2aSThomas Huth 469fcf5ef2aSThomas Huth typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 470fcf5ef2aSThomas Huth 471fcf5ef2aSThomas Huth /* cpuid_features bits */ 472fcf5ef2aSThomas Huth #define CPUID_FP87 (1U << 0) 473fcf5ef2aSThomas Huth #define CPUID_VME (1U << 1) 474fcf5ef2aSThomas Huth #define CPUID_DE (1U << 2) 475fcf5ef2aSThomas Huth #define CPUID_PSE (1U << 3) 476fcf5ef2aSThomas Huth #define CPUID_TSC (1U << 4) 477fcf5ef2aSThomas Huth #define CPUID_MSR (1U << 5) 478fcf5ef2aSThomas Huth #define CPUID_PAE (1U << 6) 479fcf5ef2aSThomas Huth #define CPUID_MCE (1U << 7) 480fcf5ef2aSThomas Huth #define CPUID_CX8 (1U << 8) 481fcf5ef2aSThomas Huth #define CPUID_APIC (1U << 9) 482fcf5ef2aSThomas Huth #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ 483fcf5ef2aSThomas Huth #define CPUID_MTRR (1U << 12) 484fcf5ef2aSThomas Huth #define CPUID_PGE (1U << 13) 485fcf5ef2aSThomas Huth #define CPUID_MCA (1U << 14) 486fcf5ef2aSThomas Huth #define CPUID_CMOV (1U << 15) 487fcf5ef2aSThomas Huth #define CPUID_PAT (1U << 16) 488fcf5ef2aSThomas Huth #define CPUID_PSE36 (1U << 17) 489fcf5ef2aSThomas Huth #define CPUID_PN (1U << 18) 490fcf5ef2aSThomas Huth #define CPUID_CLFLUSH (1U << 19) 491fcf5ef2aSThomas Huth #define CPUID_DTS (1U << 21) 492fcf5ef2aSThomas Huth #define CPUID_ACPI (1U << 22) 493fcf5ef2aSThomas Huth #define CPUID_MMX (1U << 23) 494fcf5ef2aSThomas Huth #define CPUID_FXSR (1U << 24) 495fcf5ef2aSThomas Huth #define CPUID_SSE (1U << 25) 496fcf5ef2aSThomas Huth #define CPUID_SSE2 (1U << 26) 497fcf5ef2aSThomas Huth #define CPUID_SS (1U << 27) 498fcf5ef2aSThomas Huth #define CPUID_HT (1U << 28) 499fcf5ef2aSThomas Huth #define CPUID_TM (1U << 29) 500fcf5ef2aSThomas Huth #define CPUID_IA64 (1U << 30) 501fcf5ef2aSThomas Huth #define CPUID_PBE (1U << 31) 502fcf5ef2aSThomas Huth 503fcf5ef2aSThomas Huth #define CPUID_EXT_SSE3 (1U << 0) 504fcf5ef2aSThomas Huth #define CPUID_EXT_PCLMULQDQ (1U << 1) 505fcf5ef2aSThomas Huth #define CPUID_EXT_DTES64 (1U << 2) 506fcf5ef2aSThomas Huth #define CPUID_EXT_MONITOR (1U << 3) 507fcf5ef2aSThomas Huth #define CPUID_EXT_DSCPL (1U << 4) 508fcf5ef2aSThomas Huth #define CPUID_EXT_VMX (1U << 5) 509fcf5ef2aSThomas Huth #define CPUID_EXT_SMX (1U << 6) 510fcf5ef2aSThomas Huth #define CPUID_EXT_EST (1U << 7) 511fcf5ef2aSThomas Huth #define CPUID_EXT_TM2 (1U << 8) 512fcf5ef2aSThomas Huth #define CPUID_EXT_SSSE3 (1U << 9) 513fcf5ef2aSThomas Huth #define CPUID_EXT_CID (1U << 10) 514fcf5ef2aSThomas Huth #define CPUID_EXT_FMA (1U << 12) 515fcf5ef2aSThomas Huth #define CPUID_EXT_CX16 (1U << 13) 516fcf5ef2aSThomas Huth #define CPUID_EXT_XTPR (1U << 14) 517fcf5ef2aSThomas Huth #define CPUID_EXT_PDCM (1U << 15) 518fcf5ef2aSThomas Huth #define CPUID_EXT_PCID (1U << 17) 519fcf5ef2aSThomas Huth #define CPUID_EXT_DCA (1U << 18) 520fcf5ef2aSThomas Huth #define CPUID_EXT_SSE41 (1U << 19) 521fcf5ef2aSThomas Huth #define CPUID_EXT_SSE42 (1U << 20) 522fcf5ef2aSThomas Huth #define CPUID_EXT_X2APIC (1U << 21) 523fcf5ef2aSThomas Huth #define CPUID_EXT_MOVBE (1U << 22) 524fcf5ef2aSThomas Huth #define CPUID_EXT_POPCNT (1U << 23) 525fcf5ef2aSThomas Huth #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) 526fcf5ef2aSThomas Huth #define CPUID_EXT_AES (1U << 25) 527fcf5ef2aSThomas Huth #define CPUID_EXT_XSAVE (1U << 26) 528fcf5ef2aSThomas Huth #define CPUID_EXT_OSXSAVE (1U << 27) 529fcf5ef2aSThomas Huth #define CPUID_EXT_AVX (1U << 28) 530fcf5ef2aSThomas Huth #define CPUID_EXT_F16C (1U << 29) 531fcf5ef2aSThomas Huth #define CPUID_EXT_RDRAND (1U << 30) 532fcf5ef2aSThomas Huth #define CPUID_EXT_HYPERVISOR (1U << 31) 533fcf5ef2aSThomas Huth 534fcf5ef2aSThomas Huth #define CPUID_EXT2_FPU (1U << 0) 535fcf5ef2aSThomas Huth #define CPUID_EXT2_VME (1U << 1) 536fcf5ef2aSThomas Huth #define CPUID_EXT2_DE (1U << 2) 537fcf5ef2aSThomas Huth #define CPUID_EXT2_PSE (1U << 3) 538fcf5ef2aSThomas Huth #define CPUID_EXT2_TSC (1U << 4) 539fcf5ef2aSThomas Huth #define CPUID_EXT2_MSR (1U << 5) 540fcf5ef2aSThomas Huth #define CPUID_EXT2_PAE (1U << 6) 541fcf5ef2aSThomas Huth #define CPUID_EXT2_MCE (1U << 7) 542fcf5ef2aSThomas Huth #define CPUID_EXT2_CX8 (1U << 8) 543fcf5ef2aSThomas Huth #define CPUID_EXT2_APIC (1U << 9) 544fcf5ef2aSThomas Huth #define CPUID_EXT2_SYSCALL (1U << 11) 545fcf5ef2aSThomas Huth #define CPUID_EXT2_MTRR (1U << 12) 546fcf5ef2aSThomas Huth #define CPUID_EXT2_PGE (1U << 13) 547fcf5ef2aSThomas Huth #define CPUID_EXT2_MCA (1U << 14) 548fcf5ef2aSThomas Huth #define CPUID_EXT2_CMOV (1U << 15) 549fcf5ef2aSThomas Huth #define CPUID_EXT2_PAT (1U << 16) 550fcf5ef2aSThomas Huth #define CPUID_EXT2_PSE36 (1U << 17) 551fcf5ef2aSThomas Huth #define CPUID_EXT2_MP (1U << 19) 552fcf5ef2aSThomas Huth #define CPUID_EXT2_NX (1U << 20) 553fcf5ef2aSThomas Huth #define CPUID_EXT2_MMXEXT (1U << 22) 554fcf5ef2aSThomas Huth #define CPUID_EXT2_MMX (1U << 23) 555fcf5ef2aSThomas Huth #define CPUID_EXT2_FXSR (1U << 24) 556fcf5ef2aSThomas Huth #define CPUID_EXT2_FFXSR (1U << 25) 557fcf5ef2aSThomas Huth #define CPUID_EXT2_PDPE1GB (1U << 26) 558fcf5ef2aSThomas Huth #define CPUID_EXT2_RDTSCP (1U << 27) 559fcf5ef2aSThomas Huth #define CPUID_EXT2_LM (1U << 29) 560fcf5ef2aSThomas Huth #define CPUID_EXT2_3DNOWEXT (1U << 30) 561fcf5ef2aSThomas Huth #define CPUID_EXT2_3DNOW (1U << 31) 562fcf5ef2aSThomas Huth 563fcf5ef2aSThomas Huth /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 564fcf5ef2aSThomas Huth #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 565fcf5ef2aSThomas Huth CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 566fcf5ef2aSThomas Huth CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 567fcf5ef2aSThomas Huth CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 568fcf5ef2aSThomas Huth CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 569fcf5ef2aSThomas Huth CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 570fcf5ef2aSThomas Huth CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 571fcf5ef2aSThomas Huth CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 572fcf5ef2aSThomas Huth CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 573fcf5ef2aSThomas Huth 574fcf5ef2aSThomas Huth #define CPUID_EXT3_LAHF_LM (1U << 0) 575fcf5ef2aSThomas Huth #define CPUID_EXT3_CMP_LEG (1U << 1) 576fcf5ef2aSThomas Huth #define CPUID_EXT3_SVM (1U << 2) 577fcf5ef2aSThomas Huth #define CPUID_EXT3_EXTAPIC (1U << 3) 578fcf5ef2aSThomas Huth #define CPUID_EXT3_CR8LEG (1U << 4) 579fcf5ef2aSThomas Huth #define CPUID_EXT3_ABM (1U << 5) 580fcf5ef2aSThomas Huth #define CPUID_EXT3_SSE4A (1U << 6) 581fcf5ef2aSThomas Huth #define CPUID_EXT3_MISALIGNSSE (1U << 7) 582fcf5ef2aSThomas Huth #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) 583fcf5ef2aSThomas Huth #define CPUID_EXT3_OSVW (1U << 9) 584fcf5ef2aSThomas Huth #define CPUID_EXT3_IBS (1U << 10) 585fcf5ef2aSThomas Huth #define CPUID_EXT3_XOP (1U << 11) 586fcf5ef2aSThomas Huth #define CPUID_EXT3_SKINIT (1U << 12) 587fcf5ef2aSThomas Huth #define CPUID_EXT3_WDT (1U << 13) 588fcf5ef2aSThomas Huth #define CPUID_EXT3_LWP (1U << 15) 589fcf5ef2aSThomas Huth #define CPUID_EXT3_FMA4 (1U << 16) 590fcf5ef2aSThomas Huth #define CPUID_EXT3_TCE (1U << 17) 591fcf5ef2aSThomas Huth #define CPUID_EXT3_NODEID (1U << 19) 592fcf5ef2aSThomas Huth #define CPUID_EXT3_TBM (1U << 21) 593fcf5ef2aSThomas Huth #define CPUID_EXT3_TOPOEXT (1U << 22) 594fcf5ef2aSThomas Huth #define CPUID_EXT3_PERFCORE (1U << 23) 595fcf5ef2aSThomas Huth #define CPUID_EXT3_PERFNB (1U << 24) 596fcf5ef2aSThomas Huth 597fcf5ef2aSThomas Huth #define CPUID_SVM_NPT (1U << 0) 598fcf5ef2aSThomas Huth #define CPUID_SVM_LBRV (1U << 1) 599fcf5ef2aSThomas Huth #define CPUID_SVM_SVMLOCK (1U << 2) 600fcf5ef2aSThomas Huth #define CPUID_SVM_NRIPSAVE (1U << 3) 601fcf5ef2aSThomas Huth #define CPUID_SVM_TSCSCALE (1U << 4) 602fcf5ef2aSThomas Huth #define CPUID_SVM_VMCBCLEAN (1U << 5) 603fcf5ef2aSThomas Huth #define CPUID_SVM_FLUSHASID (1U << 6) 604fcf5ef2aSThomas Huth #define CPUID_SVM_DECODEASSIST (1U << 7) 605fcf5ef2aSThomas Huth #define CPUID_SVM_PAUSEFILTER (1U << 10) 606fcf5ef2aSThomas Huth #define CPUID_SVM_PFTHRESHOLD (1U << 12) 607fcf5ef2aSThomas Huth 608fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_FSGSBASE (1U << 0) 609fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_BMI1 (1U << 3) 610fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_HLE (1U << 4) 611fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX2 (1U << 5) 612fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_SMEP (1U << 7) 613fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_BMI2 (1U << 8) 614fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_ERMS (1U << 9) 615fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_INVPCID (1U << 10) 616fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_RTM (1U << 11) 617fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_MPX (1U << 14) 618fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ 619fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ 620fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_RDSEED (1U << 18) 621fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_ADX (1U << 19) 622fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_SMAP (1U << 20) 623fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ 624fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ 625fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ 626fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ 627fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ 628fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ 629fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ 630638cbd45SYi Sun #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ 631fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ 632fcf5ef2aSThomas Huth #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ 633fcf5ef2aSThomas Huth 634fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ 635fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_UMIP (1U << 2) 636fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_PKU (1U << 3) 637fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_OSPKE (1U << 4) 638f7754377SHe Chen #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ 6396c7c3c21SKirill A. Shutemov #define CPUID_7_0_ECX_LA57 (1U << 16) 640fcf5ef2aSThomas Huth #define CPUID_7_0_ECX_RDPID (1U << 22) 641fcf5ef2aSThomas Huth 642fcf5ef2aSThomas Huth #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ 643fcf5ef2aSThomas Huth #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ 644fcf5ef2aSThomas Huth 645fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVEOPT (1U << 0) 646fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVEC (1U << 1) 647fcf5ef2aSThomas Huth #define CPUID_XSAVE_XGETBV1 (1U << 2) 648fcf5ef2aSThomas Huth #define CPUID_XSAVE_XSAVES (1U << 3) 649fcf5ef2aSThomas Huth 650fcf5ef2aSThomas Huth #define CPUID_6_EAX_ARAT (1U << 2) 651fcf5ef2aSThomas Huth 652fcf5ef2aSThomas Huth /* CPUID[0x80000007].EDX flags: */ 653fcf5ef2aSThomas Huth #define CPUID_APM_INVTSC (1U << 8) 654fcf5ef2aSThomas Huth 655fcf5ef2aSThomas Huth #define CPUID_VENDOR_SZ 12 656fcf5ef2aSThomas Huth 657fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 658fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 659fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 660fcf5ef2aSThomas Huth #define CPUID_VENDOR_INTEL "GenuineIntel" 661fcf5ef2aSThomas Huth 662fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 663fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 664fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 665fcf5ef2aSThomas Huth #define CPUID_VENDOR_AMD "AuthenticAMD" 666fcf5ef2aSThomas Huth 667fcf5ef2aSThomas Huth #define CPUID_VENDOR_VIA "CentaurHauls" 668fcf5ef2aSThomas Huth 669fcf5ef2aSThomas Huth #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ 670fcf5ef2aSThomas Huth #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ 671fcf5ef2aSThomas Huth 672fcf5ef2aSThomas Huth /* CPUID[0xB].ECX level types */ 673fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) 674fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) 675fcf5ef2aSThomas Huth #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) 676fcf5ef2aSThomas Huth 677fcf5ef2aSThomas Huth #ifndef HYPERV_SPINLOCK_NEVER_RETRY 678fcf5ef2aSThomas Huth #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 679fcf5ef2aSThomas Huth #endif 680fcf5ef2aSThomas Huth 681fcf5ef2aSThomas Huth #define EXCP00_DIVZ 0 682fcf5ef2aSThomas Huth #define EXCP01_DB 1 683fcf5ef2aSThomas Huth #define EXCP02_NMI 2 684fcf5ef2aSThomas Huth #define EXCP03_INT3 3 685fcf5ef2aSThomas Huth #define EXCP04_INTO 4 686fcf5ef2aSThomas Huth #define EXCP05_BOUND 5 687fcf5ef2aSThomas Huth #define EXCP06_ILLOP 6 688fcf5ef2aSThomas Huth #define EXCP07_PREX 7 689fcf5ef2aSThomas Huth #define EXCP08_DBLE 8 690fcf5ef2aSThomas Huth #define EXCP09_XERR 9 691fcf5ef2aSThomas Huth #define EXCP0A_TSS 10 692fcf5ef2aSThomas Huth #define EXCP0B_NOSEG 11 693fcf5ef2aSThomas Huth #define EXCP0C_STACK 12 694fcf5ef2aSThomas Huth #define EXCP0D_GPF 13 695fcf5ef2aSThomas Huth #define EXCP0E_PAGE 14 696fcf5ef2aSThomas Huth #define EXCP10_COPR 16 697fcf5ef2aSThomas Huth #define EXCP11_ALGN 17 698fcf5ef2aSThomas Huth #define EXCP12_MCHK 18 699fcf5ef2aSThomas Huth 700fcf5ef2aSThomas Huth #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 701fcf5ef2aSThomas Huth for syscall instruction */ 70210cde894SPaolo Bonzini #define EXCP_VMEXIT 0x100 703fcf5ef2aSThomas Huth 704fcf5ef2aSThomas Huth /* i386-specific interrupt pending bits. */ 705fcf5ef2aSThomas Huth #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 706fcf5ef2aSThomas Huth #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 707fcf5ef2aSThomas Huth #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 708fcf5ef2aSThomas Huth #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 709fcf5ef2aSThomas Huth #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 710fcf5ef2aSThomas Huth #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 711fcf5ef2aSThomas Huth #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 712fcf5ef2aSThomas Huth 713fcf5ef2aSThomas Huth /* Use a clearer name for this. */ 714fcf5ef2aSThomas Huth #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET 715fcf5ef2aSThomas Huth 716fcf5ef2aSThomas Huth /* Instead of computing the condition codes after each x86 instruction, 717fcf5ef2aSThomas Huth * QEMU just stores one operand (called CC_SRC), the result 718fcf5ef2aSThomas Huth * (called CC_DST) and the type of operation (called CC_OP). When the 719fcf5ef2aSThomas Huth * condition codes are needed, the condition codes can be calculated 720fcf5ef2aSThomas Huth * using this information. Condition codes are not generated if they 721fcf5ef2aSThomas Huth * are only needed for conditional branches. 722fcf5ef2aSThomas Huth */ 723fcf5ef2aSThomas Huth typedef enum { 724fcf5ef2aSThomas Huth CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 725fcf5ef2aSThomas Huth CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 726fcf5ef2aSThomas Huth 727fcf5ef2aSThomas Huth CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 728fcf5ef2aSThomas Huth CC_OP_MULW, 729fcf5ef2aSThomas Huth CC_OP_MULL, 730fcf5ef2aSThomas Huth CC_OP_MULQ, 731fcf5ef2aSThomas Huth 732fcf5ef2aSThomas Huth CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 733fcf5ef2aSThomas Huth CC_OP_ADDW, 734fcf5ef2aSThomas Huth CC_OP_ADDL, 735fcf5ef2aSThomas Huth CC_OP_ADDQ, 736fcf5ef2aSThomas Huth 737fcf5ef2aSThomas Huth CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 738fcf5ef2aSThomas Huth CC_OP_ADCW, 739fcf5ef2aSThomas Huth CC_OP_ADCL, 740fcf5ef2aSThomas Huth CC_OP_ADCQ, 741fcf5ef2aSThomas Huth 742fcf5ef2aSThomas Huth CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 743fcf5ef2aSThomas Huth CC_OP_SUBW, 744fcf5ef2aSThomas Huth CC_OP_SUBL, 745fcf5ef2aSThomas Huth CC_OP_SUBQ, 746fcf5ef2aSThomas Huth 747fcf5ef2aSThomas Huth CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 748fcf5ef2aSThomas Huth CC_OP_SBBW, 749fcf5ef2aSThomas Huth CC_OP_SBBL, 750fcf5ef2aSThomas Huth CC_OP_SBBQ, 751fcf5ef2aSThomas Huth 752fcf5ef2aSThomas Huth CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 753fcf5ef2aSThomas Huth CC_OP_LOGICW, 754fcf5ef2aSThomas Huth CC_OP_LOGICL, 755fcf5ef2aSThomas Huth CC_OP_LOGICQ, 756fcf5ef2aSThomas Huth 757fcf5ef2aSThomas Huth CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 758fcf5ef2aSThomas Huth CC_OP_INCW, 759fcf5ef2aSThomas Huth CC_OP_INCL, 760fcf5ef2aSThomas Huth CC_OP_INCQ, 761fcf5ef2aSThomas Huth 762fcf5ef2aSThomas Huth CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 763fcf5ef2aSThomas Huth CC_OP_DECW, 764fcf5ef2aSThomas Huth CC_OP_DECL, 765fcf5ef2aSThomas Huth CC_OP_DECQ, 766fcf5ef2aSThomas Huth 767fcf5ef2aSThomas Huth CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 768fcf5ef2aSThomas Huth CC_OP_SHLW, 769fcf5ef2aSThomas Huth CC_OP_SHLL, 770fcf5ef2aSThomas Huth CC_OP_SHLQ, 771fcf5ef2aSThomas Huth 772fcf5ef2aSThomas Huth CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 773fcf5ef2aSThomas Huth CC_OP_SARW, 774fcf5ef2aSThomas Huth CC_OP_SARL, 775fcf5ef2aSThomas Huth CC_OP_SARQ, 776fcf5ef2aSThomas Huth 777fcf5ef2aSThomas Huth CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ 778fcf5ef2aSThomas Huth CC_OP_BMILGW, 779fcf5ef2aSThomas Huth CC_OP_BMILGL, 780fcf5ef2aSThomas Huth CC_OP_BMILGQ, 781fcf5ef2aSThomas Huth 782fcf5ef2aSThomas Huth CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ 783fcf5ef2aSThomas Huth CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ 784fcf5ef2aSThomas Huth CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ 785fcf5ef2aSThomas Huth 786fcf5ef2aSThomas Huth CC_OP_CLR, /* Z set, all other flags clear. */ 7874885c3c4SRichard Henderson CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ 788fcf5ef2aSThomas Huth 789fcf5ef2aSThomas Huth CC_OP_NB, 790fcf5ef2aSThomas Huth } CCOp; 791fcf5ef2aSThomas Huth 792fcf5ef2aSThomas Huth typedef struct SegmentCache { 793fcf5ef2aSThomas Huth uint32_t selector; 794fcf5ef2aSThomas Huth target_ulong base; 795fcf5ef2aSThomas Huth uint32_t limit; 796fcf5ef2aSThomas Huth uint32_t flags; 797fcf5ef2aSThomas Huth } SegmentCache; 798fcf5ef2aSThomas Huth 799fcf5ef2aSThomas Huth #define MMREG_UNION(n, bits) \ 800fcf5ef2aSThomas Huth union n { \ 801fcf5ef2aSThomas Huth uint8_t _b_##n[(bits)/8]; \ 802fcf5ef2aSThomas Huth uint16_t _w_##n[(bits)/16]; \ 803fcf5ef2aSThomas Huth uint32_t _l_##n[(bits)/32]; \ 804fcf5ef2aSThomas Huth uint64_t _q_##n[(bits)/64]; \ 805fcf5ef2aSThomas Huth float32 _s_##n[(bits)/32]; \ 806fcf5ef2aSThomas Huth float64 _d_##n[(bits)/64]; \ 807fcf5ef2aSThomas Huth } 808fcf5ef2aSThomas Huth 809fcf5ef2aSThomas Huth typedef MMREG_UNION(ZMMReg, 512) ZMMReg; 810fcf5ef2aSThomas Huth typedef MMREG_UNION(MMXReg, 64) MMXReg; 811fcf5ef2aSThomas Huth 812fcf5ef2aSThomas Huth typedef struct BNDReg { 813fcf5ef2aSThomas Huth uint64_t lb; 814fcf5ef2aSThomas Huth uint64_t ub; 815fcf5ef2aSThomas Huth } BNDReg; 816fcf5ef2aSThomas Huth 817fcf5ef2aSThomas Huth typedef struct BNDCSReg { 818fcf5ef2aSThomas Huth uint64_t cfgu; 819fcf5ef2aSThomas Huth uint64_t sts; 820fcf5ef2aSThomas Huth } BNDCSReg; 821fcf5ef2aSThomas Huth 822fcf5ef2aSThomas Huth #define BNDCFG_ENABLE 1ULL 823fcf5ef2aSThomas Huth #define BNDCFG_BNDPRESERVE 2ULL 824fcf5ef2aSThomas Huth #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK 825fcf5ef2aSThomas Huth 826fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 827fcf5ef2aSThomas Huth #define ZMM_B(n) _b_ZMMReg[63 - (n)] 828fcf5ef2aSThomas Huth #define ZMM_W(n) _w_ZMMReg[31 - (n)] 829fcf5ef2aSThomas Huth #define ZMM_L(n) _l_ZMMReg[15 - (n)] 830fcf5ef2aSThomas Huth #define ZMM_S(n) _s_ZMMReg[15 - (n)] 831fcf5ef2aSThomas Huth #define ZMM_Q(n) _q_ZMMReg[7 - (n)] 832fcf5ef2aSThomas Huth #define ZMM_D(n) _d_ZMMReg[7 - (n)] 833fcf5ef2aSThomas Huth 834fcf5ef2aSThomas Huth #define MMX_B(n) _b_MMXReg[7 - (n)] 835fcf5ef2aSThomas Huth #define MMX_W(n) _w_MMXReg[3 - (n)] 836fcf5ef2aSThomas Huth #define MMX_L(n) _l_MMXReg[1 - (n)] 837fcf5ef2aSThomas Huth #define MMX_S(n) _s_MMXReg[1 - (n)] 838fcf5ef2aSThomas Huth #else 839fcf5ef2aSThomas Huth #define ZMM_B(n) _b_ZMMReg[n] 840fcf5ef2aSThomas Huth #define ZMM_W(n) _w_ZMMReg[n] 841fcf5ef2aSThomas Huth #define ZMM_L(n) _l_ZMMReg[n] 842fcf5ef2aSThomas Huth #define ZMM_S(n) _s_ZMMReg[n] 843fcf5ef2aSThomas Huth #define ZMM_Q(n) _q_ZMMReg[n] 844fcf5ef2aSThomas Huth #define ZMM_D(n) _d_ZMMReg[n] 845fcf5ef2aSThomas Huth 846fcf5ef2aSThomas Huth #define MMX_B(n) _b_MMXReg[n] 847fcf5ef2aSThomas Huth #define MMX_W(n) _w_MMXReg[n] 848fcf5ef2aSThomas Huth #define MMX_L(n) _l_MMXReg[n] 849fcf5ef2aSThomas Huth #define MMX_S(n) _s_MMXReg[n] 850fcf5ef2aSThomas Huth #endif 851fcf5ef2aSThomas Huth #define MMX_Q(n) _q_MMXReg[n] 852fcf5ef2aSThomas Huth 853fcf5ef2aSThomas Huth typedef union { 854fcf5ef2aSThomas Huth floatx80 d __attribute__((aligned(16))); 855fcf5ef2aSThomas Huth MMXReg mmx; 856fcf5ef2aSThomas Huth } FPReg; 857fcf5ef2aSThomas Huth 858fcf5ef2aSThomas Huth typedef struct { 859fcf5ef2aSThomas Huth uint64_t base; 860fcf5ef2aSThomas Huth uint64_t mask; 861fcf5ef2aSThomas Huth } MTRRVar; 862fcf5ef2aSThomas Huth 863fcf5ef2aSThomas Huth #define CPU_NB_REGS64 16 864fcf5ef2aSThomas Huth #define CPU_NB_REGS32 8 865fcf5ef2aSThomas Huth 866fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 867fcf5ef2aSThomas Huth #define CPU_NB_REGS CPU_NB_REGS64 868fcf5ef2aSThomas Huth #else 869fcf5ef2aSThomas Huth #define CPU_NB_REGS CPU_NB_REGS32 870fcf5ef2aSThomas Huth #endif 871fcf5ef2aSThomas Huth 872fcf5ef2aSThomas Huth #define MAX_FIXED_COUNTERS 3 873fcf5ef2aSThomas Huth #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) 874fcf5ef2aSThomas Huth 875fcf5ef2aSThomas Huth #define NB_MMU_MODES 3 876fcf5ef2aSThomas Huth #define TARGET_INSN_START_EXTRA_WORDS 1 877fcf5ef2aSThomas Huth 878fcf5ef2aSThomas Huth #define NB_OPMASK_REGS 8 879fcf5ef2aSThomas Huth 880fcf5ef2aSThomas Huth /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish 881fcf5ef2aSThomas Huth * that APIC ID hasn't been set yet 882fcf5ef2aSThomas Huth */ 883fcf5ef2aSThomas Huth #define UNASSIGNED_APIC_ID 0xFFFFFFFF 884fcf5ef2aSThomas Huth 885fcf5ef2aSThomas Huth typedef union X86LegacyXSaveArea { 886fcf5ef2aSThomas Huth struct { 887fcf5ef2aSThomas Huth uint16_t fcw; 888fcf5ef2aSThomas Huth uint16_t fsw; 889fcf5ef2aSThomas Huth uint8_t ftw; 890fcf5ef2aSThomas Huth uint8_t reserved; 891fcf5ef2aSThomas Huth uint16_t fpop; 892fcf5ef2aSThomas Huth uint64_t fpip; 893fcf5ef2aSThomas Huth uint64_t fpdp; 894fcf5ef2aSThomas Huth uint32_t mxcsr; 895fcf5ef2aSThomas Huth uint32_t mxcsr_mask; 896fcf5ef2aSThomas Huth FPReg fpregs[8]; 897fcf5ef2aSThomas Huth uint8_t xmm_regs[16][16]; 898fcf5ef2aSThomas Huth }; 899fcf5ef2aSThomas Huth uint8_t data[512]; 900fcf5ef2aSThomas Huth } X86LegacyXSaveArea; 901fcf5ef2aSThomas Huth 902fcf5ef2aSThomas Huth typedef struct X86XSaveHeader { 903fcf5ef2aSThomas Huth uint64_t xstate_bv; 904fcf5ef2aSThomas Huth uint64_t xcomp_bv; 905fcf5ef2aSThomas Huth uint64_t reserve0; 906fcf5ef2aSThomas Huth uint8_t reserved[40]; 907fcf5ef2aSThomas Huth } X86XSaveHeader; 908fcf5ef2aSThomas Huth 909fcf5ef2aSThomas Huth /* Ext. save area 2: AVX State */ 910fcf5ef2aSThomas Huth typedef struct XSaveAVX { 911fcf5ef2aSThomas Huth uint8_t ymmh[16][16]; 912fcf5ef2aSThomas Huth } XSaveAVX; 913fcf5ef2aSThomas Huth 914fcf5ef2aSThomas Huth /* Ext. save area 3: BNDREG */ 915fcf5ef2aSThomas Huth typedef struct XSaveBNDREG { 916fcf5ef2aSThomas Huth BNDReg bnd_regs[4]; 917fcf5ef2aSThomas Huth } XSaveBNDREG; 918fcf5ef2aSThomas Huth 919fcf5ef2aSThomas Huth /* Ext. save area 4: BNDCSR */ 920fcf5ef2aSThomas Huth typedef union XSaveBNDCSR { 921fcf5ef2aSThomas Huth BNDCSReg bndcsr; 922fcf5ef2aSThomas Huth uint8_t data[64]; 923fcf5ef2aSThomas Huth } XSaveBNDCSR; 924fcf5ef2aSThomas Huth 925fcf5ef2aSThomas Huth /* Ext. save area 5: Opmask */ 926fcf5ef2aSThomas Huth typedef struct XSaveOpmask { 927fcf5ef2aSThomas Huth uint64_t opmask_regs[NB_OPMASK_REGS]; 928fcf5ef2aSThomas Huth } XSaveOpmask; 929fcf5ef2aSThomas Huth 930fcf5ef2aSThomas Huth /* Ext. save area 6: ZMM_Hi256 */ 931fcf5ef2aSThomas Huth typedef struct XSaveZMM_Hi256 { 932fcf5ef2aSThomas Huth uint8_t zmm_hi256[16][32]; 933fcf5ef2aSThomas Huth } XSaveZMM_Hi256; 934fcf5ef2aSThomas Huth 935fcf5ef2aSThomas Huth /* Ext. save area 7: Hi16_ZMM */ 936fcf5ef2aSThomas Huth typedef struct XSaveHi16_ZMM { 937fcf5ef2aSThomas Huth uint8_t hi16_zmm[16][64]; 938fcf5ef2aSThomas Huth } XSaveHi16_ZMM; 939fcf5ef2aSThomas Huth 940fcf5ef2aSThomas Huth /* Ext. save area 9: PKRU state */ 941fcf5ef2aSThomas Huth typedef struct XSavePKRU { 942fcf5ef2aSThomas Huth uint32_t pkru; 943fcf5ef2aSThomas Huth uint32_t padding; 944fcf5ef2aSThomas Huth } XSavePKRU; 945fcf5ef2aSThomas Huth 946fcf5ef2aSThomas Huth typedef struct X86XSaveArea { 947fcf5ef2aSThomas Huth X86LegacyXSaveArea legacy; 948fcf5ef2aSThomas Huth X86XSaveHeader header; 949fcf5ef2aSThomas Huth 950fcf5ef2aSThomas Huth /* Extended save areas: */ 951fcf5ef2aSThomas Huth 952fcf5ef2aSThomas Huth /* AVX State: */ 953fcf5ef2aSThomas Huth XSaveAVX avx_state; 954fcf5ef2aSThomas Huth uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; 955fcf5ef2aSThomas Huth /* MPX State: */ 956fcf5ef2aSThomas Huth XSaveBNDREG bndreg_state; 957fcf5ef2aSThomas Huth XSaveBNDCSR bndcsr_state; 958fcf5ef2aSThomas Huth /* AVX-512 State: */ 959fcf5ef2aSThomas Huth XSaveOpmask opmask_state; 960fcf5ef2aSThomas Huth XSaveZMM_Hi256 zmm_hi256_state; 961fcf5ef2aSThomas Huth XSaveHi16_ZMM hi16_zmm_state; 962fcf5ef2aSThomas Huth /* PKRU State: */ 963fcf5ef2aSThomas Huth XSavePKRU pkru_state; 964fcf5ef2aSThomas Huth } X86XSaveArea; 965fcf5ef2aSThomas Huth 966fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); 967fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); 968fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); 969fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); 970fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); 971fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); 972fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); 973fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); 974fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); 975fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); 976fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); 977fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); 978fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); 979fcf5ef2aSThomas Huth QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); 980fcf5ef2aSThomas Huth 981fcf5ef2aSThomas Huth typedef enum TPRAccess { 982fcf5ef2aSThomas Huth TPR_ACCESS_READ, 983fcf5ef2aSThomas Huth TPR_ACCESS_WRITE, 984fcf5ef2aSThomas Huth } TPRAccess; 985fcf5ef2aSThomas Huth 986fcf5ef2aSThomas Huth typedef struct CPUX86State { 987fcf5ef2aSThomas Huth /* standard registers */ 988fcf5ef2aSThomas Huth target_ulong regs[CPU_NB_REGS]; 989fcf5ef2aSThomas Huth target_ulong eip; 990fcf5ef2aSThomas Huth target_ulong eflags; /* eflags register. During CPU emulation, CC 991fcf5ef2aSThomas Huth flags and DF are set to zero because they are 992fcf5ef2aSThomas Huth stored elsewhere */ 993fcf5ef2aSThomas Huth 994fcf5ef2aSThomas Huth /* emulator internal eflags handling */ 995fcf5ef2aSThomas Huth target_ulong cc_dst; 996fcf5ef2aSThomas Huth target_ulong cc_src; 997fcf5ef2aSThomas Huth target_ulong cc_src2; 998fcf5ef2aSThomas Huth uint32_t cc_op; 999fcf5ef2aSThomas Huth int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 1000fcf5ef2aSThomas Huth uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 1001fcf5ef2aSThomas Huth are known at translation time. */ 1002fcf5ef2aSThomas Huth uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 1003fcf5ef2aSThomas Huth 1004fcf5ef2aSThomas Huth /* segments */ 1005fcf5ef2aSThomas Huth SegmentCache segs[6]; /* selector values */ 1006fcf5ef2aSThomas Huth SegmentCache ldt; 1007fcf5ef2aSThomas Huth SegmentCache tr; 1008fcf5ef2aSThomas Huth SegmentCache gdt; /* only base and limit are used */ 1009fcf5ef2aSThomas Huth SegmentCache idt; /* only base and limit are used */ 1010fcf5ef2aSThomas Huth 1011fcf5ef2aSThomas Huth target_ulong cr[5]; /* NOTE: cr1 is unused */ 1012fcf5ef2aSThomas Huth int32_t a20_mask; 1013fcf5ef2aSThomas Huth 1014fcf5ef2aSThomas Huth BNDReg bnd_regs[4]; 1015fcf5ef2aSThomas Huth BNDCSReg bndcs_regs; 1016fcf5ef2aSThomas Huth uint64_t msr_bndcfgs; 1017fcf5ef2aSThomas Huth uint64_t efer; 1018fcf5ef2aSThomas Huth 1019fcf5ef2aSThomas Huth /* Beginning of state preserved by INIT (dummy marker). */ 1020fcf5ef2aSThomas Huth struct {} start_init_save; 1021fcf5ef2aSThomas Huth 1022fcf5ef2aSThomas Huth /* FPU state */ 1023fcf5ef2aSThomas Huth unsigned int fpstt; /* top of stack index */ 1024fcf5ef2aSThomas Huth uint16_t fpus; 1025fcf5ef2aSThomas Huth uint16_t fpuc; 1026fcf5ef2aSThomas Huth uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 1027fcf5ef2aSThomas Huth FPReg fpregs[8]; 1028fcf5ef2aSThomas Huth /* KVM-only so far */ 1029fcf5ef2aSThomas Huth uint16_t fpop; 1030fcf5ef2aSThomas Huth uint64_t fpip; 1031fcf5ef2aSThomas Huth uint64_t fpdp; 1032fcf5ef2aSThomas Huth 1033fcf5ef2aSThomas Huth /* emulator internal variables */ 1034fcf5ef2aSThomas Huth float_status fp_status; 1035fcf5ef2aSThomas Huth floatx80 ft0; 1036fcf5ef2aSThomas Huth 1037fcf5ef2aSThomas Huth float_status mmx_status; /* for 3DNow! float ops */ 1038fcf5ef2aSThomas Huth float_status sse_status; 1039fcf5ef2aSThomas Huth uint32_t mxcsr; 1040fcf5ef2aSThomas Huth ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; 1041fcf5ef2aSThomas Huth ZMMReg xmm_t0; 1042fcf5ef2aSThomas Huth MMXReg mmx_t0; 1043fcf5ef2aSThomas Huth 1044fcf5ef2aSThomas Huth uint64_t opmask_regs[NB_OPMASK_REGS]; 1045fcf5ef2aSThomas Huth 1046fcf5ef2aSThomas Huth /* sysenter registers */ 1047fcf5ef2aSThomas Huth uint32_t sysenter_cs; 1048fcf5ef2aSThomas Huth target_ulong sysenter_esp; 1049fcf5ef2aSThomas Huth target_ulong sysenter_eip; 1050fcf5ef2aSThomas Huth uint64_t star; 1051fcf5ef2aSThomas Huth 1052fcf5ef2aSThomas Huth uint64_t vm_hsave; 1053fcf5ef2aSThomas Huth 1054fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 1055fcf5ef2aSThomas Huth target_ulong lstar; 1056fcf5ef2aSThomas Huth target_ulong cstar; 1057fcf5ef2aSThomas Huth target_ulong fmask; 1058fcf5ef2aSThomas Huth target_ulong kernelgsbase; 1059fcf5ef2aSThomas Huth #endif 1060fcf5ef2aSThomas Huth 1061fcf5ef2aSThomas Huth uint64_t tsc; 1062fcf5ef2aSThomas Huth uint64_t tsc_adjust; 1063fcf5ef2aSThomas Huth uint64_t tsc_deadline; 1064fcf5ef2aSThomas Huth uint64_t tsc_aux; 1065fcf5ef2aSThomas Huth 1066fcf5ef2aSThomas Huth uint64_t xcr0; 1067fcf5ef2aSThomas Huth 1068fcf5ef2aSThomas Huth uint64_t mcg_status; 1069fcf5ef2aSThomas Huth uint64_t msr_ia32_misc_enable; 1070fcf5ef2aSThomas Huth uint64_t msr_ia32_feature_control; 1071fcf5ef2aSThomas Huth 1072fcf5ef2aSThomas Huth uint64_t msr_fixed_ctr_ctrl; 1073fcf5ef2aSThomas Huth uint64_t msr_global_ctrl; 1074fcf5ef2aSThomas Huth uint64_t msr_global_status; 1075fcf5ef2aSThomas Huth uint64_t msr_global_ovf_ctrl; 1076fcf5ef2aSThomas Huth uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; 1077fcf5ef2aSThomas Huth uint64_t msr_gp_counters[MAX_GP_COUNTERS]; 1078fcf5ef2aSThomas Huth uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; 1079fcf5ef2aSThomas Huth 1080fcf5ef2aSThomas Huth uint64_t pat; 1081fcf5ef2aSThomas Huth uint32_t smbase; 1082fcf5ef2aSThomas Huth 1083fcf5ef2aSThomas Huth uint32_t pkru; 1084fcf5ef2aSThomas Huth 1085fcf5ef2aSThomas Huth /* End of state preserved by INIT (dummy marker). */ 1086fcf5ef2aSThomas Huth struct {} end_init_save; 1087fcf5ef2aSThomas Huth 1088fcf5ef2aSThomas Huth uint64_t system_time_msr; 1089fcf5ef2aSThomas Huth uint64_t wall_clock_msr; 1090fcf5ef2aSThomas Huth uint64_t steal_time_msr; 1091fcf5ef2aSThomas Huth uint64_t async_pf_en_msr; 1092fcf5ef2aSThomas Huth uint64_t pv_eoi_en_msr; 1093fcf5ef2aSThomas Huth 1094fcf5ef2aSThomas Huth uint64_t msr_hv_hypercall; 1095fcf5ef2aSThomas Huth uint64_t msr_hv_guest_os_id; 1096fcf5ef2aSThomas Huth uint64_t msr_hv_vapic; 1097fcf5ef2aSThomas Huth uint64_t msr_hv_tsc; 1098fcf5ef2aSThomas Huth uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS]; 1099fcf5ef2aSThomas Huth uint64_t msr_hv_runtime; 1100fcf5ef2aSThomas Huth uint64_t msr_hv_synic_control; 1101fcf5ef2aSThomas Huth uint64_t msr_hv_synic_version; 1102fcf5ef2aSThomas Huth uint64_t msr_hv_synic_evt_page; 1103fcf5ef2aSThomas Huth uint64_t msr_hv_synic_msg_page; 1104fcf5ef2aSThomas Huth uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT]; 1105fcf5ef2aSThomas Huth uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT]; 1106fcf5ef2aSThomas Huth uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT]; 1107fcf5ef2aSThomas Huth 1108fcf5ef2aSThomas Huth /* exception/interrupt handling */ 1109fcf5ef2aSThomas Huth int error_code; 1110fcf5ef2aSThomas Huth int exception_is_int; 1111fcf5ef2aSThomas Huth target_ulong exception_next_eip; 1112fcf5ef2aSThomas Huth target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ 1113fcf5ef2aSThomas Huth union { 1114fcf5ef2aSThomas Huth struct CPUBreakpoint *cpu_breakpoint[4]; 1115fcf5ef2aSThomas Huth struct CPUWatchpoint *cpu_watchpoint[4]; 1116fcf5ef2aSThomas Huth }; /* break/watchpoints for dr[0..3] */ 1117fcf5ef2aSThomas Huth int old_exception; /* exception in flight */ 1118fcf5ef2aSThomas Huth 1119fcf5ef2aSThomas Huth uint64_t vm_vmcb; 1120fcf5ef2aSThomas Huth uint64_t tsc_offset; 1121fcf5ef2aSThomas Huth uint64_t intercept; 1122fcf5ef2aSThomas Huth uint16_t intercept_cr_read; 1123fcf5ef2aSThomas Huth uint16_t intercept_cr_write; 1124fcf5ef2aSThomas Huth uint16_t intercept_dr_read; 1125fcf5ef2aSThomas Huth uint16_t intercept_dr_write; 1126fcf5ef2aSThomas Huth uint32_t intercept_exceptions; 1127fcf5ef2aSThomas Huth uint8_t v_tpr; 1128fcf5ef2aSThomas Huth 1129fcf5ef2aSThomas Huth /* KVM states, automatically cleared on reset */ 1130fcf5ef2aSThomas Huth uint8_t nmi_injected; 1131fcf5ef2aSThomas Huth uint8_t nmi_pending; 1132fcf5ef2aSThomas Huth 11331f5c00cfSAlex Bennée /* Fields up to this point are cleared by a CPU reset */ 11341f5c00cfSAlex Bennée struct {} end_reset_fields; 11351f5c00cfSAlex Bennée 1136fcf5ef2aSThomas Huth CPU_COMMON 1137fcf5ef2aSThomas Huth 11381f5c00cfSAlex Bennée /* Fields after CPU_COMMON are preserved across CPU reset. */ 1139fcf5ef2aSThomas Huth 1140fcf5ef2aSThomas Huth /* processor features (e.g. for CPUID insn) */ 1141fcf5ef2aSThomas Huth /* Minimum level/xlevel/xlevel2, based on CPU model + features */ 1142fcf5ef2aSThomas Huth uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; 1143fcf5ef2aSThomas Huth /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ 1144fcf5ef2aSThomas Huth uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; 1145fcf5ef2aSThomas Huth /* Actual level/xlevel/xlevel2 value: */ 1146fcf5ef2aSThomas Huth uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; 1147fcf5ef2aSThomas Huth uint32_t cpuid_vendor1; 1148fcf5ef2aSThomas Huth uint32_t cpuid_vendor2; 1149fcf5ef2aSThomas Huth uint32_t cpuid_vendor3; 1150fcf5ef2aSThomas Huth uint32_t cpuid_version; 1151fcf5ef2aSThomas Huth FeatureWordArray features; 1152d4a606b3SEduardo Habkost /* Features that were explicitly enabled/disabled */ 1153d4a606b3SEduardo Habkost FeatureWordArray user_features; 1154fcf5ef2aSThomas Huth uint32_t cpuid_model[12]; 1155fcf5ef2aSThomas Huth 1156fcf5ef2aSThomas Huth /* MTRRs */ 1157fcf5ef2aSThomas Huth uint64_t mtrr_fixed[11]; 1158fcf5ef2aSThomas Huth uint64_t mtrr_deftype; 1159fcf5ef2aSThomas Huth MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; 1160fcf5ef2aSThomas Huth 1161fcf5ef2aSThomas Huth /* For KVM */ 1162fcf5ef2aSThomas Huth uint32_t mp_state; 1163fcf5ef2aSThomas Huth int32_t exception_injected; 1164fcf5ef2aSThomas Huth int32_t interrupt_injected; 1165fcf5ef2aSThomas Huth uint8_t soft_interrupt; 1166fcf5ef2aSThomas Huth uint8_t has_error_code; 1167fcf5ef2aSThomas Huth uint32_t sipi_vector; 1168fcf5ef2aSThomas Huth bool tsc_valid; 1169fcf5ef2aSThomas Huth int64_t tsc_khz; 1170fcf5ef2aSThomas Huth int64_t user_tsc_khz; /* for sanity check only */ 1171fcf5ef2aSThomas Huth void *kvm_xsave_buf; 1172fcf5ef2aSThomas Huth 1173fcf5ef2aSThomas Huth uint64_t mcg_cap; 1174fcf5ef2aSThomas Huth uint64_t mcg_ctl; 1175fcf5ef2aSThomas Huth uint64_t mcg_ext_ctl; 1176fcf5ef2aSThomas Huth uint64_t mce_banks[MCE_BANKS_DEF*4]; 1177fcf5ef2aSThomas Huth uint64_t xstate_bv; 1178fcf5ef2aSThomas Huth 1179fcf5ef2aSThomas Huth /* vmstate */ 1180fcf5ef2aSThomas Huth uint16_t fpus_vmstate; 1181fcf5ef2aSThomas Huth uint16_t fptag_vmstate; 1182fcf5ef2aSThomas Huth uint16_t fpregs_format_vmstate; 1183fcf5ef2aSThomas Huth 1184fcf5ef2aSThomas Huth uint64_t xss; 1185fcf5ef2aSThomas Huth 1186fcf5ef2aSThomas Huth TPRAccess tpr_access_type; 1187fcf5ef2aSThomas Huth } CPUX86State; 1188fcf5ef2aSThomas Huth 1189fcf5ef2aSThomas Huth struct kvm_msrs; 1190fcf5ef2aSThomas Huth 1191fcf5ef2aSThomas Huth /** 1192fcf5ef2aSThomas Huth * X86CPU: 1193fcf5ef2aSThomas Huth * @env: #CPUX86State 1194fcf5ef2aSThomas Huth * @migratable: If set, only migratable flags will be accepted when "enforce" 1195fcf5ef2aSThomas Huth * mode is used, and only migratable flags will be included in the "host" 1196fcf5ef2aSThomas Huth * CPU model. 1197fcf5ef2aSThomas Huth * 1198fcf5ef2aSThomas Huth * An x86 CPU. 1199fcf5ef2aSThomas Huth */ 1200fcf5ef2aSThomas Huth struct X86CPU { 1201fcf5ef2aSThomas Huth /*< private >*/ 1202fcf5ef2aSThomas Huth CPUState parent_obj; 1203fcf5ef2aSThomas Huth /*< public >*/ 1204fcf5ef2aSThomas Huth 1205fcf5ef2aSThomas Huth CPUX86State env; 1206fcf5ef2aSThomas Huth 1207fcf5ef2aSThomas Huth bool hyperv_vapic; 1208fcf5ef2aSThomas Huth bool hyperv_relaxed_timing; 1209fcf5ef2aSThomas Huth int hyperv_spinlock_attempts; 1210fcf5ef2aSThomas Huth char *hyperv_vendor_id; 1211fcf5ef2aSThomas Huth bool hyperv_time; 1212fcf5ef2aSThomas Huth bool hyperv_crash; 1213fcf5ef2aSThomas Huth bool hyperv_reset; 1214fcf5ef2aSThomas Huth bool hyperv_vpindex; 1215fcf5ef2aSThomas Huth bool hyperv_runtime; 1216fcf5ef2aSThomas Huth bool hyperv_synic; 1217fcf5ef2aSThomas Huth bool hyperv_stimer; 1218fcf5ef2aSThomas Huth bool check_cpuid; 1219fcf5ef2aSThomas Huth bool enforce_cpuid; 1220fcf5ef2aSThomas Huth bool expose_kvm; 1221*1ce36bfeSDaniel P. Berrange bool expose_tcg; 1222fcf5ef2aSThomas Huth bool migratable; 122344bd8e53SEduardo Habkost bool max_features; /* Enable all supported features automatically */ 1224fcf5ef2aSThomas Huth uint32_t apic_id; 1225fcf5ef2aSThomas Huth 12269954a158SPhil Dennis-Jordan /* Enables publishing of TSC increment and Local APIC bus frequencies to 12279954a158SPhil Dennis-Jordan * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ 12289954a158SPhil Dennis-Jordan bool vmware_cpuid_freq; 12299954a158SPhil Dennis-Jordan 1230fcf5ef2aSThomas Huth /* if true the CPUID code directly forward host cache leaves to the guest */ 1231fcf5ef2aSThomas Huth bool cache_info_passthrough; 1232fcf5ef2aSThomas Huth 1233fcf5ef2aSThomas Huth /* Features that were filtered out because of missing host capabilities */ 1234fcf5ef2aSThomas Huth uint32_t filtered_features[FEATURE_WORDS]; 1235fcf5ef2aSThomas Huth 1236fcf5ef2aSThomas Huth /* Enable PMU CPUID bits. This can't be enabled by default yet because 1237fcf5ef2aSThomas Huth * it doesn't have ABI stability guarantees, as it passes all PMU CPUID 1238fcf5ef2aSThomas Huth * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel 1239fcf5ef2aSThomas Huth * capabilities) directly to the guest. 1240fcf5ef2aSThomas Huth */ 1241fcf5ef2aSThomas Huth bool enable_pmu; 1242fcf5ef2aSThomas Huth 1243fcf5ef2aSThomas Huth /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is 1244fcf5ef2aSThomas Huth * disabled by default to avoid breaking migration between QEMU with 1245fcf5ef2aSThomas Huth * different LMCE configurations. 1246fcf5ef2aSThomas Huth */ 1247fcf5ef2aSThomas Huth bool enable_lmce; 1248fcf5ef2aSThomas Huth 1249fcf5ef2aSThomas Huth /* Compatibility bits for old machine types. 1250fcf5ef2aSThomas Huth * If true present virtual l3 cache for VM, the vcpus in the same virtual 1251fcf5ef2aSThomas Huth * socket share an virtual l3 cache. 1252fcf5ef2aSThomas Huth */ 1253fcf5ef2aSThomas Huth bool enable_l3_cache; 1254fcf5ef2aSThomas Huth 1255fcf5ef2aSThomas Huth /* Compatibility bits for old machine types: */ 1256fcf5ef2aSThomas Huth bool enable_cpuid_0xb; 1257fcf5ef2aSThomas Huth 1258fcf5ef2aSThomas Huth /* Enable auto level-increase for all CPUID leaves */ 1259fcf5ef2aSThomas Huth bool full_cpuid_auto_level; 1260fcf5ef2aSThomas Huth 1261fcf5ef2aSThomas Huth /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ 1262fcf5ef2aSThomas Huth bool fill_mtrr_mask; 1263fcf5ef2aSThomas Huth 1264fcf5ef2aSThomas Huth /* if true override the phys_bits value with a value read from the host */ 1265fcf5ef2aSThomas Huth bool host_phys_bits; 1266fcf5ef2aSThomas Huth 1267fc3a1fd7SDr. David Alan Gilbert /* Stop SMI delivery for migration compatibility with old machines */ 1268fc3a1fd7SDr. David Alan Gilbert bool kvm_no_smi_migration; 1269fc3a1fd7SDr. David Alan Gilbert 1270fcf5ef2aSThomas Huth /* Number of physical address bits supported */ 1271fcf5ef2aSThomas Huth uint32_t phys_bits; 1272fcf5ef2aSThomas Huth 1273fcf5ef2aSThomas Huth /* in order to simplify APIC support, we leave this pointer to the 1274fcf5ef2aSThomas Huth user */ 1275fcf5ef2aSThomas Huth struct DeviceState *apic_state; 1276fcf5ef2aSThomas Huth struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; 1277fcf5ef2aSThomas Huth Notifier machine_done; 1278fcf5ef2aSThomas Huth 1279fcf5ef2aSThomas Huth struct kvm_msrs *kvm_msr_buf; 1280fcf5ef2aSThomas Huth 128115f8b142SIgor Mammedov int32_t node_id; /* NUMA node this CPU belongs to */ 1282fcf5ef2aSThomas Huth int32_t socket_id; 1283fcf5ef2aSThomas Huth int32_t core_id; 1284fcf5ef2aSThomas Huth int32_t thread_id; 1285fcf5ef2aSThomas Huth }; 1286fcf5ef2aSThomas Huth 1287fcf5ef2aSThomas Huth static inline X86CPU *x86_env_get_cpu(CPUX86State *env) 1288fcf5ef2aSThomas Huth { 1289fcf5ef2aSThomas Huth return container_of(env, X86CPU, env); 1290fcf5ef2aSThomas Huth } 1291fcf5ef2aSThomas Huth 1292fcf5ef2aSThomas Huth #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) 1293fcf5ef2aSThomas Huth 1294fcf5ef2aSThomas Huth #define ENV_OFFSET offsetof(X86CPU, env) 1295fcf5ef2aSThomas Huth 1296fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 1297fcf5ef2aSThomas Huth extern struct VMStateDescription vmstate_x86_cpu; 1298fcf5ef2aSThomas Huth #endif 1299fcf5ef2aSThomas Huth 1300fcf5ef2aSThomas Huth /** 1301fcf5ef2aSThomas Huth * x86_cpu_do_interrupt: 1302fcf5ef2aSThomas Huth * @cpu: vCPU the interrupt is to be handled by. 1303fcf5ef2aSThomas Huth */ 1304fcf5ef2aSThomas Huth void x86_cpu_do_interrupt(CPUState *cpu); 1305fcf5ef2aSThomas Huth bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); 1306fcf5ef2aSThomas Huth 1307fcf5ef2aSThomas Huth int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 1308fcf5ef2aSThomas Huth int cpuid, void *opaque); 1309fcf5ef2aSThomas Huth int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 1310fcf5ef2aSThomas Huth int cpuid, void *opaque); 1311fcf5ef2aSThomas Huth int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1312fcf5ef2aSThomas Huth void *opaque); 1313fcf5ef2aSThomas Huth int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 1314fcf5ef2aSThomas Huth void *opaque); 1315fcf5ef2aSThomas Huth 1316fcf5ef2aSThomas Huth void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 1317fcf5ef2aSThomas Huth Error **errp); 1318fcf5ef2aSThomas Huth 1319fcf5ef2aSThomas Huth void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 1320fcf5ef2aSThomas Huth int flags); 1321fcf5ef2aSThomas Huth 1322fcf5ef2aSThomas Huth hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1323fcf5ef2aSThomas Huth 1324fcf5ef2aSThomas Huth int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1325fcf5ef2aSThomas Huth int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1326fcf5ef2aSThomas Huth 1327fcf5ef2aSThomas Huth void x86_cpu_exec_enter(CPUState *cpu); 1328fcf5ef2aSThomas Huth void x86_cpu_exec_exit(CPUState *cpu); 1329fcf5ef2aSThomas Huth 1330fcf5ef2aSThomas Huth X86CPU *cpu_x86_init(const char *cpu_model); 1331fcf5ef2aSThomas Huth void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1332fcf5ef2aSThomas Huth int cpu_x86_support_mca_broadcast(CPUX86State *env); 1333fcf5ef2aSThomas Huth 1334fcf5ef2aSThomas Huth int cpu_get_pic_interrupt(CPUX86State *s); 1335fcf5ef2aSThomas Huth /* MSDOS compatibility mode FPU exception support */ 1336fcf5ef2aSThomas Huth void cpu_set_ferr(CPUX86State *s); 1337fcf5ef2aSThomas Huth 1338fcf5ef2aSThomas Huth /* this function must always be used to load data in the segment 1339fcf5ef2aSThomas Huth cache: it synchronizes the hflags with the segment cache values */ 1340fcf5ef2aSThomas Huth static inline void cpu_x86_load_seg_cache(CPUX86State *env, 1341fcf5ef2aSThomas Huth int seg_reg, unsigned int selector, 1342fcf5ef2aSThomas Huth target_ulong base, 1343fcf5ef2aSThomas Huth unsigned int limit, 1344fcf5ef2aSThomas Huth unsigned int flags) 1345fcf5ef2aSThomas Huth { 1346fcf5ef2aSThomas Huth SegmentCache *sc; 1347fcf5ef2aSThomas Huth unsigned int new_hflags; 1348fcf5ef2aSThomas Huth 1349fcf5ef2aSThomas Huth sc = &env->segs[seg_reg]; 1350fcf5ef2aSThomas Huth sc->selector = selector; 1351fcf5ef2aSThomas Huth sc->base = base; 1352fcf5ef2aSThomas Huth sc->limit = limit; 1353fcf5ef2aSThomas Huth sc->flags = flags; 1354fcf5ef2aSThomas Huth 1355fcf5ef2aSThomas Huth /* update the hidden flags */ 1356fcf5ef2aSThomas Huth { 1357fcf5ef2aSThomas Huth if (seg_reg == R_CS) { 1358fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 1359fcf5ef2aSThomas Huth if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 1360fcf5ef2aSThomas Huth /* long mode */ 1361fcf5ef2aSThomas Huth env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 1362fcf5ef2aSThomas Huth env->hflags &= ~(HF_ADDSEG_MASK); 1363fcf5ef2aSThomas Huth } else 1364fcf5ef2aSThomas Huth #endif 1365fcf5ef2aSThomas Huth { 1366fcf5ef2aSThomas Huth /* legacy / compatibility case */ 1367fcf5ef2aSThomas Huth new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 1368fcf5ef2aSThomas Huth >> (DESC_B_SHIFT - HF_CS32_SHIFT); 1369fcf5ef2aSThomas Huth env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 1370fcf5ef2aSThomas Huth new_hflags; 1371fcf5ef2aSThomas Huth } 1372fcf5ef2aSThomas Huth } 1373fcf5ef2aSThomas Huth if (seg_reg == R_SS) { 1374fcf5ef2aSThomas Huth int cpl = (flags >> DESC_DPL_SHIFT) & 3; 1375fcf5ef2aSThomas Huth #if HF_CPL_MASK != 3 1376fcf5ef2aSThomas Huth #error HF_CPL_MASK is hardcoded 1377fcf5ef2aSThomas Huth #endif 1378fcf5ef2aSThomas Huth env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; 1379fcf5ef2aSThomas Huth } 1380fcf5ef2aSThomas Huth new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 1381fcf5ef2aSThomas Huth >> (DESC_B_SHIFT - HF_SS32_SHIFT); 1382fcf5ef2aSThomas Huth if (env->hflags & HF_CS64_MASK) { 1383fcf5ef2aSThomas Huth /* zero base assumed for DS, ES and SS in long mode */ 1384fcf5ef2aSThomas Huth } else if (!(env->cr[0] & CR0_PE_MASK) || 1385fcf5ef2aSThomas Huth (env->eflags & VM_MASK) || 1386fcf5ef2aSThomas Huth !(env->hflags & HF_CS32_MASK)) { 1387fcf5ef2aSThomas Huth /* XXX: try to avoid this test. The problem comes from the 1388fcf5ef2aSThomas Huth fact that is real mode or vm86 mode we only modify the 1389fcf5ef2aSThomas Huth 'base' and 'selector' fields of the segment cache to go 1390fcf5ef2aSThomas Huth faster. A solution may be to force addseg to one in 1391fcf5ef2aSThomas Huth translate-i386.c. */ 1392fcf5ef2aSThomas Huth new_hflags |= HF_ADDSEG_MASK; 1393fcf5ef2aSThomas Huth } else { 1394fcf5ef2aSThomas Huth new_hflags |= ((env->segs[R_DS].base | 1395fcf5ef2aSThomas Huth env->segs[R_ES].base | 1396fcf5ef2aSThomas Huth env->segs[R_SS].base) != 0) << 1397fcf5ef2aSThomas Huth HF_ADDSEG_SHIFT; 1398fcf5ef2aSThomas Huth } 1399fcf5ef2aSThomas Huth env->hflags = (env->hflags & 1400fcf5ef2aSThomas Huth ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 1401fcf5ef2aSThomas Huth } 1402fcf5ef2aSThomas Huth } 1403fcf5ef2aSThomas Huth 1404fcf5ef2aSThomas Huth static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, 1405fcf5ef2aSThomas Huth uint8_t sipi_vector) 1406fcf5ef2aSThomas Huth { 1407fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 1408fcf5ef2aSThomas Huth CPUX86State *env = &cpu->env; 1409fcf5ef2aSThomas Huth 1410fcf5ef2aSThomas Huth env->eip = 0; 1411fcf5ef2aSThomas Huth cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, 1412fcf5ef2aSThomas Huth sipi_vector << 12, 1413fcf5ef2aSThomas Huth env->segs[R_CS].limit, 1414fcf5ef2aSThomas Huth env->segs[R_CS].flags); 1415fcf5ef2aSThomas Huth cs->halted = 0; 1416fcf5ef2aSThomas Huth } 1417fcf5ef2aSThomas Huth 1418fcf5ef2aSThomas Huth int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, 1419fcf5ef2aSThomas Huth target_ulong *base, unsigned int *limit, 1420fcf5ef2aSThomas Huth unsigned int *flags); 1421fcf5ef2aSThomas Huth 1422fcf5ef2aSThomas Huth /* op_helper.c */ 1423fcf5ef2aSThomas Huth /* used for debug or cpu save/restore */ 1424fcf5ef2aSThomas Huth 1425fcf5ef2aSThomas Huth /* cpu-exec.c */ 1426fcf5ef2aSThomas Huth /* the following helpers are only usable in user mode simulation as 1427fcf5ef2aSThomas Huth they can trigger unexpected exceptions */ 1428fcf5ef2aSThomas Huth void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 1429fcf5ef2aSThomas Huth void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 1430fcf5ef2aSThomas Huth void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 14311c1df019SPranith Kumar void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); 14321c1df019SPranith Kumar void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); 1433fcf5ef2aSThomas Huth 1434fcf5ef2aSThomas Huth /* you can call this signal handler from your SIGBUS and SIGSEGV 1435fcf5ef2aSThomas Huth signal handlers to inform the virtual CPU of exceptions. non zero 1436fcf5ef2aSThomas Huth is returned if the signal was handled by the virtual CPU. */ 1437fcf5ef2aSThomas Huth int cpu_x86_signal_handler(int host_signum, void *pinfo, 1438fcf5ef2aSThomas Huth void *puc); 1439fcf5ef2aSThomas Huth 1440fcf5ef2aSThomas Huth /* cpu.c */ 1441fcf5ef2aSThomas Huth void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 1442fcf5ef2aSThomas Huth uint32_t *eax, uint32_t *ebx, 1443fcf5ef2aSThomas Huth uint32_t *ecx, uint32_t *edx); 1444fcf5ef2aSThomas Huth void cpu_clear_apic_feature(CPUX86State *env); 1445fcf5ef2aSThomas Huth void host_cpuid(uint32_t function, uint32_t count, 1446fcf5ef2aSThomas Huth uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); 144720271d48SEduardo Habkost void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); 1448fcf5ef2aSThomas Huth 1449fcf5ef2aSThomas Huth /* helper.c */ 1450fcf5ef2aSThomas Huth int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, 1451fcf5ef2aSThomas Huth int is_write, int mmu_idx); 1452fcf5ef2aSThomas Huth void x86_cpu_set_a20(X86CPU *cpu, int a20_state); 1453fcf5ef2aSThomas Huth 1454fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 1455f8c45c65SPaolo Bonzini static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 1456f8c45c65SPaolo Bonzini { 1457f8c45c65SPaolo Bonzini return !!attrs.secure; 1458f8c45c65SPaolo Bonzini } 1459f8c45c65SPaolo Bonzini 1460f8c45c65SPaolo Bonzini static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) 1461f8c45c65SPaolo Bonzini { 1462f8c45c65SPaolo Bonzini return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); 1463f8c45c65SPaolo Bonzini } 1464f8c45c65SPaolo Bonzini 1465fcf5ef2aSThomas Huth uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); 1466fcf5ef2aSThomas Huth uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); 1467fcf5ef2aSThomas Huth uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); 1468fcf5ef2aSThomas Huth uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); 1469fcf5ef2aSThomas Huth void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); 1470fcf5ef2aSThomas Huth void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); 1471fcf5ef2aSThomas Huth void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); 1472fcf5ef2aSThomas Huth void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 1473fcf5ef2aSThomas Huth void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); 1474fcf5ef2aSThomas Huth #endif 1475fcf5ef2aSThomas Huth 1476fcf5ef2aSThomas Huth void breakpoint_handler(CPUState *cs); 1477fcf5ef2aSThomas Huth 1478fcf5ef2aSThomas Huth /* will be suppressed */ 1479fcf5ef2aSThomas Huth void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 1480fcf5ef2aSThomas Huth void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 1481fcf5ef2aSThomas Huth void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 1482fcf5ef2aSThomas Huth void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); 1483fcf5ef2aSThomas Huth 1484fcf5ef2aSThomas Huth /* hw/pc.c */ 1485fcf5ef2aSThomas Huth uint64_t cpu_get_tsc(CPUX86State *env); 1486fcf5ef2aSThomas Huth 1487fcf5ef2aSThomas Huth #define TARGET_PAGE_BITS 12 1488fcf5ef2aSThomas Huth 1489fcf5ef2aSThomas Huth #ifdef TARGET_X86_64 1490fcf5ef2aSThomas Huth #define TARGET_PHYS_ADDR_SPACE_BITS 52 1491fcf5ef2aSThomas Huth /* ??? This is really 48 bits, sign-extended, but the only thing 1492fcf5ef2aSThomas Huth accessible to userland with bit 48 set is the VSYSCALL, and that 1493fcf5ef2aSThomas Huth is handled via other mechanisms. */ 1494fcf5ef2aSThomas Huth #define TARGET_VIRT_ADDR_SPACE_BITS 47 1495fcf5ef2aSThomas Huth #else 1496fcf5ef2aSThomas Huth #define TARGET_PHYS_ADDR_SPACE_BITS 36 1497fcf5ef2aSThomas Huth #define TARGET_VIRT_ADDR_SPACE_BITS 32 1498fcf5ef2aSThomas Huth #endif 1499fcf5ef2aSThomas Huth 1500fcf5ef2aSThomas Huth /* XXX: This value should match the one returned by CPUID 1501fcf5ef2aSThomas Huth * and in exec.c */ 1502fcf5ef2aSThomas Huth # if defined(TARGET_X86_64) 1503fcf5ef2aSThomas Huth # define TCG_PHYS_ADDR_BITS 40 1504fcf5ef2aSThomas Huth # else 1505fcf5ef2aSThomas Huth # define TCG_PHYS_ADDR_BITS 36 1506fcf5ef2aSThomas Huth # endif 1507fcf5ef2aSThomas Huth 1508fcf5ef2aSThomas Huth #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1509fcf5ef2aSThomas Huth 1510fcf5ef2aSThomas Huth #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model)) 1511fcf5ef2aSThomas Huth 1512fcf5ef2aSThomas Huth #define cpu_signal_handler cpu_x86_signal_handler 1513fcf5ef2aSThomas Huth #define cpu_list x86_cpu_list 1514fcf5ef2aSThomas Huth 1515fcf5ef2aSThomas Huth /* MMU modes definitions */ 1516fcf5ef2aSThomas Huth #define MMU_MODE0_SUFFIX _ksmap 1517fcf5ef2aSThomas Huth #define MMU_MODE1_SUFFIX _user 1518fcf5ef2aSThomas Huth #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ 1519fcf5ef2aSThomas Huth #define MMU_KSMAP_IDX 0 1520fcf5ef2aSThomas Huth #define MMU_USER_IDX 1 1521fcf5ef2aSThomas Huth #define MMU_KNOSMAP_IDX 2 1522fcf5ef2aSThomas Huth static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) 1523fcf5ef2aSThomas Huth { 1524fcf5ef2aSThomas Huth return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : 1525fcf5ef2aSThomas Huth (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) 1526fcf5ef2aSThomas Huth ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1527fcf5ef2aSThomas Huth } 1528fcf5ef2aSThomas Huth 1529fcf5ef2aSThomas Huth static inline int cpu_mmu_index_kernel(CPUX86State *env) 1530fcf5ef2aSThomas Huth { 1531fcf5ef2aSThomas Huth return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : 1532fcf5ef2aSThomas Huth ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) 1533fcf5ef2aSThomas Huth ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; 1534fcf5ef2aSThomas Huth } 1535fcf5ef2aSThomas Huth 1536fcf5ef2aSThomas Huth #define CC_DST (env->cc_dst) 1537fcf5ef2aSThomas Huth #define CC_SRC (env->cc_src) 1538fcf5ef2aSThomas Huth #define CC_SRC2 (env->cc_src2) 1539fcf5ef2aSThomas Huth #define CC_OP (env->cc_op) 1540fcf5ef2aSThomas Huth 1541fcf5ef2aSThomas Huth /* n must be a constant to be efficient */ 1542fcf5ef2aSThomas Huth static inline target_long lshift(target_long x, int n) 1543fcf5ef2aSThomas Huth { 1544fcf5ef2aSThomas Huth if (n >= 0) { 1545fcf5ef2aSThomas Huth return x << n; 1546fcf5ef2aSThomas Huth } else { 1547fcf5ef2aSThomas Huth return x >> (-n); 1548fcf5ef2aSThomas Huth } 1549fcf5ef2aSThomas Huth } 1550fcf5ef2aSThomas Huth 1551fcf5ef2aSThomas Huth /* float macros */ 1552fcf5ef2aSThomas Huth #define FT0 (env->ft0) 1553fcf5ef2aSThomas Huth #define ST0 (env->fpregs[env->fpstt].d) 1554fcf5ef2aSThomas Huth #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1555fcf5ef2aSThomas Huth #define ST1 ST(1) 1556fcf5ef2aSThomas Huth 1557fcf5ef2aSThomas Huth /* translate.c */ 1558fcf5ef2aSThomas Huth void tcg_x86_init(void); 1559fcf5ef2aSThomas Huth 1560fcf5ef2aSThomas Huth #include "exec/cpu-all.h" 1561fcf5ef2aSThomas Huth #include "svm.h" 1562fcf5ef2aSThomas Huth 1563fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1564fcf5ef2aSThomas Huth #include "hw/i386/apic.h" 1565fcf5ef2aSThomas Huth #endif 1566fcf5ef2aSThomas Huth 1567fcf5ef2aSThomas Huth static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1568fcf5ef2aSThomas Huth target_ulong *cs_base, uint32_t *flags) 1569fcf5ef2aSThomas Huth { 1570fcf5ef2aSThomas Huth *cs_base = env->segs[R_CS].base; 1571fcf5ef2aSThomas Huth *pc = *cs_base + env->eip; 1572fcf5ef2aSThomas Huth *flags = env->hflags | 1573fcf5ef2aSThomas Huth (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); 1574fcf5ef2aSThomas Huth } 1575fcf5ef2aSThomas Huth 1576fcf5ef2aSThomas Huth void do_cpu_init(X86CPU *cpu); 1577fcf5ef2aSThomas Huth void do_cpu_sipi(X86CPU *cpu); 1578fcf5ef2aSThomas Huth 1579fcf5ef2aSThomas Huth #define MCE_INJECT_BROADCAST 1 1580fcf5ef2aSThomas Huth #define MCE_INJECT_UNCOND_AO 2 1581fcf5ef2aSThomas Huth 1582fcf5ef2aSThomas Huth void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, 1583fcf5ef2aSThomas Huth uint64_t status, uint64_t mcg_status, uint64_t addr, 1584fcf5ef2aSThomas Huth uint64_t misc, int flags); 1585fcf5ef2aSThomas Huth 1586fcf5ef2aSThomas Huth /* excp_helper.c */ 1587fcf5ef2aSThomas Huth void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); 1588fcf5ef2aSThomas Huth void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, 1589fcf5ef2aSThomas Huth uintptr_t retaddr); 1590fcf5ef2aSThomas Huth void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, 1591fcf5ef2aSThomas Huth int error_code); 1592fcf5ef2aSThomas Huth void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, 1593fcf5ef2aSThomas Huth int error_code, uintptr_t retaddr); 1594fcf5ef2aSThomas Huth void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, 1595fcf5ef2aSThomas Huth int error_code, int next_eip_addend); 1596fcf5ef2aSThomas Huth 1597fcf5ef2aSThomas Huth /* cc_helper.c */ 1598fcf5ef2aSThomas Huth extern const uint8_t parity_table[256]; 1599fcf5ef2aSThomas Huth uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); 1600fcf5ef2aSThomas Huth 1601fcf5ef2aSThomas Huth static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1602fcf5ef2aSThomas Huth { 160379c664f6SYang Zhong uint32_t eflags = env->eflags; 160479c664f6SYang Zhong if (tcg_enabled()) { 160579c664f6SYang Zhong eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); 160679c664f6SYang Zhong } 160779c664f6SYang Zhong return eflags; 1608fcf5ef2aSThomas Huth } 1609fcf5ef2aSThomas Huth 1610fcf5ef2aSThomas Huth /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS 1611fcf5ef2aSThomas Huth * after generating a call to a helper that uses this. 1612fcf5ef2aSThomas Huth */ 1613fcf5ef2aSThomas Huth static inline void cpu_load_eflags(CPUX86State *env, int eflags, 1614fcf5ef2aSThomas Huth int update_mask) 1615fcf5ef2aSThomas Huth { 1616fcf5ef2aSThomas Huth CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1617fcf5ef2aSThomas Huth CC_OP = CC_OP_EFLAGS; 1618fcf5ef2aSThomas Huth env->df = 1 - (2 * ((eflags >> 10) & 1)); 1619fcf5ef2aSThomas Huth env->eflags = (env->eflags & ~update_mask) | 1620fcf5ef2aSThomas Huth (eflags & update_mask) | 0x2; 1621fcf5ef2aSThomas Huth } 1622fcf5ef2aSThomas Huth 1623fcf5ef2aSThomas Huth /* load efer and update the corresponding hflags. XXX: do consistency 1624fcf5ef2aSThomas Huth checks with cpuid bits? */ 1625fcf5ef2aSThomas Huth static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1626fcf5ef2aSThomas Huth { 1627fcf5ef2aSThomas Huth env->efer = val; 1628fcf5ef2aSThomas Huth env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1629fcf5ef2aSThomas Huth if (env->efer & MSR_EFER_LMA) { 1630fcf5ef2aSThomas Huth env->hflags |= HF_LMA_MASK; 1631fcf5ef2aSThomas Huth } 1632fcf5ef2aSThomas Huth if (env->efer & MSR_EFER_SVME) { 1633fcf5ef2aSThomas Huth env->hflags |= HF_SVME_MASK; 1634fcf5ef2aSThomas Huth } 1635fcf5ef2aSThomas Huth } 1636fcf5ef2aSThomas Huth 1637fcf5ef2aSThomas Huth static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) 1638fcf5ef2aSThomas Huth { 1639fcf5ef2aSThomas Huth return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); 1640fcf5ef2aSThomas Huth } 1641fcf5ef2aSThomas Huth 1642c8bc83a4SPaolo Bonzini static inline int32_t x86_get_a20_mask(CPUX86State *env) 1643c8bc83a4SPaolo Bonzini { 1644c8bc83a4SPaolo Bonzini if (env->hflags & HF_SMM_MASK) { 1645c8bc83a4SPaolo Bonzini return -1; 1646c8bc83a4SPaolo Bonzini } else { 1647c8bc83a4SPaolo Bonzini return env->a20_mask; 1648c8bc83a4SPaolo Bonzini } 1649c8bc83a4SPaolo Bonzini } 1650c8bc83a4SPaolo Bonzini 1651fcf5ef2aSThomas Huth /* fpu_helper.c */ 16521d8ad165SYang Zhong void update_fp_status(CPUX86State *env); 16531d8ad165SYang Zhong void update_mxcsr_status(CPUX86State *env); 16541d8ad165SYang Zhong 16551d8ad165SYang Zhong static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) 16561d8ad165SYang Zhong { 16571d8ad165SYang Zhong env->mxcsr = mxcsr; 16581d8ad165SYang Zhong if (tcg_enabled()) { 16591d8ad165SYang Zhong update_mxcsr_status(env); 16601d8ad165SYang Zhong } 16611d8ad165SYang Zhong } 16621d8ad165SYang Zhong 16631d8ad165SYang Zhong static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) 16641d8ad165SYang Zhong { 16651d8ad165SYang Zhong env->fpuc = fpuc; 16661d8ad165SYang Zhong if (tcg_enabled()) { 16671d8ad165SYang Zhong update_fp_status(env); 16681d8ad165SYang Zhong } 16691d8ad165SYang Zhong } 1670fcf5ef2aSThomas Huth 1671fcf5ef2aSThomas Huth /* mem_helper.c */ 1672fcf5ef2aSThomas Huth void helper_lock_init(void); 1673fcf5ef2aSThomas Huth 1674fcf5ef2aSThomas Huth /* svm_helper.c */ 1675fcf5ef2aSThomas Huth void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, 167665c9d60aSPaolo Bonzini uint64_t param, uintptr_t retaddr); 167765c9d60aSPaolo Bonzini void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, 167865c9d60aSPaolo Bonzini uintptr_t retaddr); 167910cde894SPaolo Bonzini void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); 1680fcf5ef2aSThomas Huth 1681fcf5ef2aSThomas Huth /* seg_helper.c */ 1682fcf5ef2aSThomas Huth void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); 1683fcf5ef2aSThomas Huth 1684fcf5ef2aSThomas Huth /* smm_helper.c */ 1685fcf5ef2aSThomas Huth void do_smm_enter(X86CPU *cpu); 1686fcf5ef2aSThomas Huth 1687fcf5ef2aSThomas Huth /* apic.c */ 1688fcf5ef2aSThomas Huth void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); 1689fcf5ef2aSThomas Huth void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 1690fcf5ef2aSThomas Huth TPRAccess access); 1691fcf5ef2aSThomas Huth 1692fcf5ef2aSThomas Huth 1693fcf5ef2aSThomas Huth /* Change the value of a KVM-specific default 1694fcf5ef2aSThomas Huth * 1695fcf5ef2aSThomas Huth * If value is NULL, no default will be set and the original 1696fcf5ef2aSThomas Huth * value from the CPU model table will be kept. 1697fcf5ef2aSThomas Huth * 1698fcf5ef2aSThomas Huth * It is valid to call this function only for properties that 1699fcf5ef2aSThomas Huth * are already present in the kvm_default_props table. 1700fcf5ef2aSThomas Huth */ 1701fcf5ef2aSThomas Huth void x86_cpu_change_kvm_default(const char *prop, const char *value); 1702fcf5ef2aSThomas Huth 1703fcf5ef2aSThomas Huth /* mpx_helper.c */ 1704fcf5ef2aSThomas Huth void cpu_sync_bndcs_hflags(CPUX86State *env); 1705fcf5ef2aSThomas Huth 1706fcf5ef2aSThomas Huth /* Return name of 32-bit register, from a R_* constant */ 1707fcf5ef2aSThomas Huth const char *get_register_name_32(unsigned int reg); 1708fcf5ef2aSThomas Huth 1709fcf5ef2aSThomas Huth void enable_compat_apic_id_mode(void); 1710fcf5ef2aSThomas Huth 1711fcf5ef2aSThomas Huth #define APIC_DEFAULT_ADDRESS 0xfee00000 1712fcf5ef2aSThomas Huth #define APIC_SPACE_SIZE 0x100000 1713fcf5ef2aSThomas Huth 1714fcf5ef2aSThomas Huth void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, 1715fcf5ef2aSThomas Huth fprintf_function cpu_fprintf, int flags); 1716fcf5ef2aSThomas Huth 1717fcf5ef2aSThomas Huth /* cpu.c */ 1718fcf5ef2aSThomas Huth bool cpu_is_bsp(X86CPU *cpu); 1719fcf5ef2aSThomas Huth 172086a57621SSergio Andres Gomez Del Real void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); 172186a57621SSergio Andres Gomez Del Real void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); 1722fcf5ef2aSThomas Huth #endif /* I386_CPU_H */ 1723