1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "sysemu/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 51 /* Helpers for building CPUID[2] descriptors: */ 52 53 struct CPUID2CacheDescriptorInfo { 54 enum CacheType type; 55 int level; 56 int size; 57 int line_size; 58 int associativity; 59 }; 60 61 /* 62 * Known CPUID 2 cache descriptors. 63 * From Intel SDM Volume 2A, CPUID instruction 64 */ 65 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 67 .associativity = 4, .line_size = 32, }, 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 73 .associativity = 2, .line_size = 32, }, 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 79 .associativity = 6, .line_size = 64, }, 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 81 .associativity = 2, .line_size = 64, }, 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 83 .associativity = 8, .line_size = 64, }, 84 /* lines per sector is not supported cpuid2_cache_descriptor(), 85 * so descriptors 0x22, 0x23 are not included 86 */ 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 88 .associativity = 16, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x25, 0x20 are not included 91 */ 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 93 .associativity = 8, .line_size = 64, }, 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 107 .associativity = 4, .line_size = 64, }, 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 122 .associativity = 24, .line_size = 64, }, 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 8, .line_size = 64, }, 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 132 .associativity = 4, .line_size = 64, }, 133 /* lines per sector is not supported cpuid2_cache_descriptor(), 134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 135 */ 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 2, .line_size = 64, }, 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 64, }, 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 }; 185 186 /* 187 * "CPUID leaf 2 does not report cache descriptor information, 188 * use CPUID leaf 4 to query cache parameters" 189 */ 190 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 191 192 /* 193 * Return a CPUID 2 cache descriptor for a given cache. 194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 195 */ 196 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 197 { 198 int i; 199 200 assert(cache->size > 0); 201 assert(cache->level > 0); 202 assert(cache->line_size > 0); 203 assert(cache->associativity > 0); 204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 206 if (d->level == cache->level && d->type == cache->type && 207 d->size == cache->size && d->line_size == cache->line_size && 208 d->associativity == cache->associativity) { 209 return i; 210 } 211 } 212 213 return CACHE_DESCRIPTOR_UNAVAILABLE; 214 } 215 216 /* CPUID Leaf 4 constants: */ 217 218 /* EAX: */ 219 #define CACHE_TYPE_D 1 220 #define CACHE_TYPE_I 2 221 #define CACHE_TYPE_UNIFIED 3 222 223 #define CACHE_LEVEL(l) (l << 5) 224 225 #define CACHE_SELF_INIT_LEVEL (1 << 8) 226 227 /* EDX: */ 228 #define CACHE_NO_INVD_SHARING (1 << 0) 229 #define CACHE_INCLUSIVE (1 << 1) 230 #define CACHE_COMPLEX_IDX (1 << 2) 231 232 /* Encode CacheType for CPUID[4].EAX */ 233 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 236 0 /* Invalid value */) 237 238 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 239 enum CPUTopoLevel share_level) 240 { 241 uint32_t num_ids = 0; 242 243 switch (share_level) { 244 case CPU_TOPO_LEVEL_CORE: 245 num_ids = 1 << apicid_core_offset(topo_info); 246 break; 247 case CPU_TOPO_LEVEL_DIE: 248 num_ids = 1 << apicid_die_offset(topo_info); 249 break; 250 case CPU_TOPO_LEVEL_PACKAGE: 251 num_ids = 1 << apicid_pkg_offset(topo_info); 252 break; 253 default: 254 /* 255 * Currently there is no use case for SMT and MODULE, so use 256 * assert directly to facilitate debugging. 257 */ 258 g_assert_not_reached(); 259 } 260 261 return num_ids - 1; 262 } 263 264 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 265 { 266 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 267 apicid_core_offset(topo_info)); 268 return num_cores - 1; 269 } 270 271 /* Encode cache info for CPUID[4] */ 272 static void encode_cache_cpuid4(CPUCacheInfo *cache, 273 X86CPUTopoInfo *topo_info, 274 uint32_t *eax, uint32_t *ebx, 275 uint32_t *ecx, uint32_t *edx) 276 { 277 assert(cache->size == cache->line_size * cache->associativity * 278 cache->partitions * cache->sets); 279 280 *eax = CACHE_TYPE(cache->type) | 281 CACHE_LEVEL(cache->level) | 282 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 283 (max_core_ids_in_package(topo_info) << 26) | 284 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 285 286 assert(cache->line_size > 0); 287 assert(cache->partitions > 0); 288 assert(cache->associativity > 0); 289 /* We don't implement fully-associative caches */ 290 assert(cache->associativity < cache->sets); 291 *ebx = (cache->line_size - 1) | 292 ((cache->partitions - 1) << 12) | 293 ((cache->associativity - 1) << 22); 294 295 assert(cache->sets > 0); 296 *ecx = cache->sets - 1; 297 298 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 299 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 300 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 301 } 302 303 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 304 enum CPUTopoLevel topo_level) 305 { 306 switch (topo_level) { 307 case CPU_TOPO_LEVEL_SMT: 308 return 1; 309 case CPU_TOPO_LEVEL_CORE: 310 return topo_info->threads_per_core; 311 case CPU_TOPO_LEVEL_MODULE: 312 return topo_info->threads_per_core * topo_info->cores_per_module; 313 case CPU_TOPO_LEVEL_DIE: 314 return topo_info->threads_per_core * topo_info->cores_per_module * 315 topo_info->modules_per_die; 316 case CPU_TOPO_LEVEL_PACKAGE: 317 return topo_info->threads_per_core * topo_info->cores_per_module * 318 topo_info->modules_per_die * topo_info->dies_per_pkg; 319 default: 320 g_assert_not_reached(); 321 } 322 return 0; 323 } 324 325 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 326 enum CPUTopoLevel topo_level) 327 { 328 switch (topo_level) { 329 case CPU_TOPO_LEVEL_SMT: 330 return 0; 331 case CPU_TOPO_LEVEL_CORE: 332 return apicid_core_offset(topo_info); 333 case CPU_TOPO_LEVEL_MODULE: 334 return apicid_module_offset(topo_info); 335 case CPU_TOPO_LEVEL_DIE: 336 return apicid_die_offset(topo_info); 337 case CPU_TOPO_LEVEL_PACKAGE: 338 return apicid_pkg_offset(topo_info); 339 default: 340 g_assert_not_reached(); 341 } 342 return 0; 343 } 344 345 static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) 346 { 347 switch (topo_level) { 348 case CPU_TOPO_LEVEL_INVALID: 349 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 350 case CPU_TOPO_LEVEL_SMT: 351 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 352 case CPU_TOPO_LEVEL_CORE: 353 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 354 case CPU_TOPO_LEVEL_MODULE: 355 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 356 case CPU_TOPO_LEVEL_DIE: 357 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 358 default: 359 /* Other types are not supported in QEMU. */ 360 g_assert_not_reached(); 361 } 362 return 0; 363 } 364 365 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 366 X86CPUTopoInfo *topo_info, 367 uint32_t *eax, uint32_t *ebx, 368 uint32_t *ecx, uint32_t *edx) 369 { 370 X86CPU *cpu = env_archcpu(env); 371 unsigned long level, next_level; 372 uint32_t num_threads_next_level, offset_next_level; 373 374 assert(count + 1 < CPU_TOPO_LEVEL_MAX); 375 376 /* 377 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 378 * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). 379 */ 380 level = CPU_TOPO_LEVEL_INVALID; 381 for (int i = 0; i <= count; i++) { 382 level = find_next_bit(env->avail_cpu_topo, 383 CPU_TOPO_LEVEL_PACKAGE, 384 level + 1); 385 386 /* 387 * CPUID[0x1f] doesn't explicitly encode the package level, 388 * and it just encodes the invalid level (all fields are 0) 389 * into the last subleaf of 0x1f. 390 */ 391 if (level == CPU_TOPO_LEVEL_PACKAGE) { 392 level = CPU_TOPO_LEVEL_INVALID; 393 break; 394 } 395 } 396 397 if (level == CPU_TOPO_LEVEL_INVALID) { 398 num_threads_next_level = 0; 399 offset_next_level = 0; 400 } else { 401 next_level = find_next_bit(env->avail_cpu_topo, 402 CPU_TOPO_LEVEL_PACKAGE, 403 level + 1); 404 num_threads_next_level = num_threads_by_topo_level(topo_info, 405 next_level); 406 offset_next_level = apicid_offset_by_topo_level(topo_info, 407 next_level); 408 } 409 410 *eax = offset_next_level; 411 /* The count (bits 15-00) doesn't need to be reliable. */ 412 *ebx = num_threads_next_level & 0xffff; 413 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 414 *edx = cpu->apic_id; 415 416 assert(!(*eax & ~0x1f)); 417 } 418 419 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 420 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 421 { 422 assert(cache->size % 1024 == 0); 423 assert(cache->lines_per_tag > 0); 424 assert(cache->associativity > 0); 425 assert(cache->line_size > 0); 426 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 427 (cache->lines_per_tag << 8) | (cache->line_size); 428 } 429 430 #define ASSOC_FULL 0xFF 431 432 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 433 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 434 a == 2 ? 0x2 : \ 435 a == 4 ? 0x4 : \ 436 a == 8 ? 0x6 : \ 437 a == 16 ? 0x8 : \ 438 a == 32 ? 0xA : \ 439 a == 48 ? 0xB : \ 440 a == 64 ? 0xC : \ 441 a == 96 ? 0xD : \ 442 a == 128 ? 0xE : \ 443 a == ASSOC_FULL ? 0xF : \ 444 0 /* invalid value */) 445 446 /* 447 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 448 * @l3 can be NULL. 449 */ 450 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 451 CPUCacheInfo *l3, 452 uint32_t *ecx, uint32_t *edx) 453 { 454 assert(l2->size % 1024 == 0); 455 assert(l2->associativity > 0); 456 assert(l2->lines_per_tag > 0); 457 assert(l2->line_size > 0); 458 *ecx = ((l2->size / 1024) << 16) | 459 (AMD_ENC_ASSOC(l2->associativity) << 12) | 460 (l2->lines_per_tag << 8) | (l2->line_size); 461 462 if (l3) { 463 assert(l3->size % (512 * 1024) == 0); 464 assert(l3->associativity > 0); 465 assert(l3->lines_per_tag > 0); 466 assert(l3->line_size > 0); 467 *edx = ((l3->size / (512 * 1024)) << 18) | 468 (AMD_ENC_ASSOC(l3->associativity) << 12) | 469 (l3->lines_per_tag << 8) | (l3->line_size); 470 } else { 471 *edx = 0; 472 } 473 } 474 475 /* Encode cache info for CPUID[8000001D] */ 476 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 477 X86CPUTopoInfo *topo_info, 478 uint32_t *eax, uint32_t *ebx, 479 uint32_t *ecx, uint32_t *edx) 480 { 481 assert(cache->size == cache->line_size * cache->associativity * 482 cache->partitions * cache->sets); 483 484 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 485 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 486 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 487 488 assert(cache->line_size > 0); 489 assert(cache->partitions > 0); 490 assert(cache->associativity > 0); 491 /* We don't implement fully-associative caches */ 492 assert(cache->associativity < cache->sets); 493 *ebx = (cache->line_size - 1) | 494 ((cache->partitions - 1) << 12) | 495 ((cache->associativity - 1) << 22); 496 497 assert(cache->sets > 0); 498 *ecx = cache->sets - 1; 499 500 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 501 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 502 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 503 } 504 505 /* Encode cache info for CPUID[8000001E] */ 506 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 507 uint32_t *eax, uint32_t *ebx, 508 uint32_t *ecx, uint32_t *edx) 509 { 510 X86CPUTopoIDs topo_ids; 511 512 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 513 514 *eax = cpu->apic_id; 515 516 /* 517 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 518 * Read-only. Reset: 0000_XXXXh. 519 * See Core::X86::Cpuid::ExtApicId. 520 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 521 * Bits Description 522 * 31:16 Reserved. 523 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 524 * The number of threads per core is ThreadsPerCore+1. 525 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 526 * 527 * NOTE: CoreId is already part of apic_id. Just use it. We can 528 * use all the 8 bits to represent the core_id here. 529 */ 530 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 531 532 /* 533 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 534 * Read-only. Reset: 0000_0XXXh. 535 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 536 * Bits Description 537 * 31:11 Reserved. 538 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 539 * ValidValues: 540 * Value Description 541 * 0h 1 node per processor. 542 * 7h-1h Reserved. 543 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 544 * 545 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 546 * But users can create more nodes than the actual hardware can 547 * support. To genaralize we can use all the upper 8 bits for nodes. 548 * NodeId is combination of node and socket_id which is already decoded 549 * in apic_id. Just use it by shifting. 550 */ 551 if (cpu->legacy_multi_node) { 552 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 553 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 554 } else { 555 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 556 } 557 558 *edx = 0; 559 } 560 561 /* 562 * Definitions of the hardcoded cache entries we expose: 563 * These are legacy cache values. If there is a need to change any 564 * of these values please use builtin_x86_defs 565 */ 566 567 /* L1 data cache: */ 568 static CPUCacheInfo legacy_l1d_cache = { 569 .type = DATA_CACHE, 570 .level = 1, 571 .size = 32 * KiB, 572 .self_init = 1, 573 .line_size = 64, 574 .associativity = 8, 575 .sets = 64, 576 .partitions = 1, 577 .no_invd_sharing = true, 578 .share_level = CPU_TOPO_LEVEL_CORE, 579 }; 580 581 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 582 static CPUCacheInfo legacy_l1d_cache_amd = { 583 .type = DATA_CACHE, 584 .level = 1, 585 .size = 64 * KiB, 586 .self_init = 1, 587 .line_size = 64, 588 .associativity = 2, 589 .sets = 512, 590 .partitions = 1, 591 .lines_per_tag = 1, 592 .no_invd_sharing = true, 593 .share_level = CPU_TOPO_LEVEL_CORE, 594 }; 595 596 /* L1 instruction cache: */ 597 static CPUCacheInfo legacy_l1i_cache = { 598 .type = INSTRUCTION_CACHE, 599 .level = 1, 600 .size = 32 * KiB, 601 .self_init = 1, 602 .line_size = 64, 603 .associativity = 8, 604 .sets = 64, 605 .partitions = 1, 606 .no_invd_sharing = true, 607 .share_level = CPU_TOPO_LEVEL_CORE, 608 }; 609 610 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 611 static CPUCacheInfo legacy_l1i_cache_amd = { 612 .type = INSTRUCTION_CACHE, 613 .level = 1, 614 .size = 64 * KiB, 615 .self_init = 1, 616 .line_size = 64, 617 .associativity = 2, 618 .sets = 512, 619 .partitions = 1, 620 .lines_per_tag = 1, 621 .no_invd_sharing = true, 622 .share_level = CPU_TOPO_LEVEL_CORE, 623 }; 624 625 /* Level 2 unified cache: */ 626 static CPUCacheInfo legacy_l2_cache = { 627 .type = UNIFIED_CACHE, 628 .level = 2, 629 .size = 4 * MiB, 630 .self_init = 1, 631 .line_size = 64, 632 .associativity = 16, 633 .sets = 4096, 634 .partitions = 1, 635 .no_invd_sharing = true, 636 .share_level = CPU_TOPO_LEVEL_CORE, 637 }; 638 639 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 640 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 641 .type = UNIFIED_CACHE, 642 .level = 2, 643 .size = 2 * MiB, 644 .line_size = 64, 645 .associativity = 8, 646 .share_level = CPU_TOPO_LEVEL_INVALID, 647 }; 648 649 650 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 651 static CPUCacheInfo legacy_l2_cache_amd = { 652 .type = UNIFIED_CACHE, 653 .level = 2, 654 .size = 512 * KiB, 655 .line_size = 64, 656 .lines_per_tag = 1, 657 .associativity = 16, 658 .sets = 512, 659 .partitions = 1, 660 .share_level = CPU_TOPO_LEVEL_CORE, 661 }; 662 663 /* Level 3 unified cache: */ 664 static CPUCacheInfo legacy_l3_cache = { 665 .type = UNIFIED_CACHE, 666 .level = 3, 667 .size = 16 * MiB, 668 .line_size = 64, 669 .associativity = 16, 670 .sets = 16384, 671 .partitions = 1, 672 .lines_per_tag = 1, 673 .self_init = true, 674 .inclusive = true, 675 .complex_indexing = true, 676 .share_level = CPU_TOPO_LEVEL_DIE, 677 }; 678 679 /* TLB definitions: */ 680 681 #define L1_DTLB_2M_ASSOC 1 682 #define L1_DTLB_2M_ENTRIES 255 683 #define L1_DTLB_4K_ASSOC 1 684 #define L1_DTLB_4K_ENTRIES 255 685 686 #define L1_ITLB_2M_ASSOC 1 687 #define L1_ITLB_2M_ENTRIES 255 688 #define L1_ITLB_4K_ASSOC 1 689 #define L1_ITLB_4K_ENTRIES 255 690 691 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 692 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 693 #define L2_DTLB_4K_ASSOC 4 694 #define L2_DTLB_4K_ENTRIES 512 695 696 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 697 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 698 #define L2_ITLB_4K_ASSOC 4 699 #define L2_ITLB_4K_ENTRIES 512 700 701 /* CPUID Leaf 0x14 constants: */ 702 #define INTEL_PT_MAX_SUBLEAF 0x1 703 /* 704 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 705 * MSR can be accessed; 706 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 707 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 708 * of Intel PT MSRs across warm reset; 709 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 710 */ 711 #define INTEL_PT_MINIMAL_EBX 0xf 712 /* 713 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 714 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 715 * accessed; 716 * bit[01]: ToPA tables can hold any number of output entries, up to the 717 * maximum allowed by the MaskOrTableOffset field of 718 * IA32_RTIT_OUTPUT_MASK_PTRS; 719 * bit[02]: Support Single-Range Output scheme; 720 */ 721 #define INTEL_PT_MINIMAL_ECX 0x7 722 /* generated packets which contain IP payloads have LIP values */ 723 #define INTEL_PT_IP_LIP (1 << 31) 724 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 725 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 726 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 727 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 728 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 729 730 /* CPUID Leaf 0x1D constants: */ 731 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 732 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 733 #define INTEL_AMX_BYTES_PER_TILE 0x400 734 #define INTEL_AMX_BYTES_PER_ROW 0x40 735 #define INTEL_AMX_TILE_MAX_NAMES 0x8 736 #define INTEL_AMX_TILE_MAX_ROWS 0x10 737 738 /* CPUID Leaf 0x1E constants: */ 739 #define INTEL_AMX_TMUL_MAX_K 0x10 740 #define INTEL_AMX_TMUL_MAX_N 0x40 741 742 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 743 uint32_t vendor2, uint32_t vendor3) 744 { 745 int i; 746 for (i = 0; i < 4; i++) { 747 dst[i] = vendor1 >> (8 * i); 748 dst[i + 4] = vendor2 >> (8 * i); 749 dst[i + 8] = vendor3 >> (8 * i); 750 } 751 dst[CPUID_VENDOR_SZ] = '\0'; 752 } 753 754 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 755 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 756 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 757 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 758 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 759 CPUID_PSE36 | CPUID_FXSR) 760 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 761 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 762 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 763 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 764 CPUID_PAE | CPUID_SEP | CPUID_APIC) 765 766 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 767 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 768 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 769 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 770 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 771 /* partly implemented: 772 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 773 /* missing: 774 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 775 776 /* 777 * Kernel-only features that can be shown to usermode programs even if 778 * they aren't actually supported by TCG, because qemu-user only runs 779 * in CPL=3; remove them if they are ever implemented for system emulation. 780 */ 781 #if defined CONFIG_USER_ONLY 782 #define CPUID_EXT_KERNEL_FEATURES \ 783 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 784 #else 785 #define CPUID_EXT_KERNEL_FEATURES 0 786 #endif 787 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 788 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 789 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 790 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 791 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 792 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 793 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 794 /* missing: 795 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 796 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 797 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 798 CPUID_EXT_TSC_DEADLINE_TIMER 799 */ 800 801 #ifdef TARGET_X86_64 802 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 803 #else 804 #define TCG_EXT2_X86_64_FEATURES 0 805 #endif 806 807 /* 808 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 809 * in usermode or by 32-bit programs. Those are added to supported 810 * TCG features unconditionally in user-mode emulation mode. This may 811 * indeed seem strange or incorrect, but it works because code running 812 * under usermode emulation cannot access them. 813 * 814 * Even for long mode, qemu-i386 is not running "a userspace program on a 815 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 816 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 817 * but again the difference is only visible in kernel mode. 818 */ 819 #if defined CONFIG_LINUX_USER 820 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 821 #elif defined CONFIG_USER_ONLY 822 /* FIXME: Long mode not yet supported for i386 bsd-user */ 823 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 824 #else 825 #define CPUID_EXT2_KERNEL_FEATURES 0 826 #endif 827 828 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 829 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 830 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 831 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 832 CPUID_EXT2_KERNEL_FEATURES) 833 834 #if defined CONFIG_USER_ONLY 835 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 836 #else 837 #define CPUID_EXT3_KERNEL_FEATURES 0 838 #endif 839 840 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 841 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 842 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 843 844 #define TCG_EXT4_FEATURES 0 845 846 #if defined CONFIG_USER_ONLY 847 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 848 #else 849 #define CPUID_SVM_KERNEL_FEATURES 0 850 #endif 851 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 852 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 853 854 #define TCG_KVM_FEATURES 0 855 856 #if defined CONFIG_USER_ONLY 857 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 858 #else 859 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 860 #endif 861 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 862 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 863 CPUID_7_0_EBX_CLFLUSHOPT | \ 864 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 865 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 866 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 867 /* missing: 868 CPUID_7_0_EBX_HLE 869 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 870 871 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 872 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 873 #else 874 #define TCG_7_0_ECX_RDPID 0 875 #endif 876 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 877 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 878 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 879 TCG_7_0_ECX_RDPID) 880 881 #if defined CONFIG_USER_ONLY 882 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 883 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 884 #else 885 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 886 #endif 887 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 888 889 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 890 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 891 #define TCG_7_1_EDX_FEATURES 0 892 #define TCG_7_2_EDX_FEATURES 0 893 #define TCG_APM_FEATURES 0 894 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 895 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 896 /* missing: 897 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 898 #define TCG_14_0_ECX_FEATURES 0 899 #define TCG_SGX_12_0_EAX_FEATURES 0 900 #define TCG_SGX_12_0_EBX_FEATURES 0 901 #define TCG_SGX_12_1_EAX_FEATURES 0 902 903 #if defined CONFIG_USER_ONLY 904 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 905 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 906 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 907 CPUID_8000_0008_EBX_AMD_PSFD) 908 #else 909 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 910 #endif 911 912 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 913 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 914 915 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 916 [FEAT_1_EDX] = { 917 .type = CPUID_FEATURE_WORD, 918 .feat_names = { 919 "fpu", "vme", "de", "pse", 920 "tsc", "msr", "pae", "mce", 921 "cx8", "apic", NULL, "sep", 922 "mtrr", "pge", "mca", "cmov", 923 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 924 NULL, "ds" /* Intel dts */, "acpi", "mmx", 925 "fxsr", "sse", "sse2", "ss", 926 "ht" /* Intel htt */, "tm", "ia64", "pbe", 927 }, 928 .cpuid = {.eax = 1, .reg = R_EDX, }, 929 .tcg_features = TCG_FEATURES, 930 .no_autoenable_flags = CPUID_HT, 931 }, 932 [FEAT_1_ECX] = { 933 .type = CPUID_FEATURE_WORD, 934 .feat_names = { 935 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 936 "ds-cpl", "vmx", "smx", "est", 937 "tm2", "ssse3", "cid", NULL, 938 "fma", "cx16", "xtpr", "pdcm", 939 NULL, "pcid", "dca", "sse4.1", 940 "sse4.2", "x2apic", "movbe", "popcnt", 941 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 942 "avx", "f16c", "rdrand", "hypervisor", 943 }, 944 .cpuid = { .eax = 1, .reg = R_ECX, }, 945 .tcg_features = TCG_EXT_FEATURES, 946 }, 947 /* Feature names that are already defined on feature_name[] but 948 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 949 * names on feat_names below. They are copied automatically 950 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 951 */ 952 [FEAT_8000_0001_EDX] = { 953 .type = CPUID_FEATURE_WORD, 954 .feat_names = { 955 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 956 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 957 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 958 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 959 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 960 "nx", NULL, "mmxext", NULL /* mmx */, 961 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 962 NULL, "lm", "3dnowext", "3dnow", 963 }, 964 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 965 .tcg_features = TCG_EXT2_FEATURES, 966 }, 967 [FEAT_8000_0001_ECX] = { 968 .type = CPUID_FEATURE_WORD, 969 .feat_names = { 970 "lahf-lm", "cmp-legacy", "svm", "extapic", 971 "cr8legacy", "abm", "sse4a", "misalignsse", 972 "3dnowprefetch", "osvw", "ibs", "xop", 973 "skinit", "wdt", NULL, "lwp", 974 "fma4", "tce", NULL, "nodeid-msr", 975 NULL, "tbm", "topoext", "perfctr-core", 976 "perfctr-nb", NULL, NULL, NULL, 977 NULL, NULL, NULL, NULL, 978 }, 979 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 980 .tcg_features = TCG_EXT3_FEATURES, 981 /* 982 * TOPOEXT is always allowed but can't be enabled blindly by 983 * "-cpu host", as it requires consistent cache topology info 984 * to be provided so it doesn't confuse guests. 985 */ 986 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 987 }, 988 [FEAT_C000_0001_EDX] = { 989 .type = CPUID_FEATURE_WORD, 990 .feat_names = { 991 NULL, NULL, "xstore", "xstore-en", 992 NULL, NULL, "xcrypt", "xcrypt-en", 993 "ace2", "ace2-en", "phe", "phe-en", 994 "pmm", "pmm-en", NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 }, 1000 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1001 .tcg_features = TCG_EXT4_FEATURES, 1002 }, 1003 [FEAT_KVM] = { 1004 .type = CPUID_FEATURE_WORD, 1005 .feat_names = { 1006 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1007 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1008 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1009 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1010 NULL, NULL, NULL, NULL, 1011 NULL, NULL, NULL, NULL, 1012 "kvmclock-stable-bit", NULL, NULL, NULL, 1013 NULL, NULL, NULL, NULL, 1014 }, 1015 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1016 .tcg_features = TCG_KVM_FEATURES, 1017 }, 1018 [FEAT_KVM_HINTS] = { 1019 .type = CPUID_FEATURE_WORD, 1020 .feat_names = { 1021 "kvm-hint-dedicated", NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 }, 1030 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1031 .tcg_features = TCG_KVM_FEATURES, 1032 /* 1033 * KVM hints aren't auto-enabled by -cpu host, they need to be 1034 * explicitly enabled in the command-line. 1035 */ 1036 .no_autoenable_flags = ~0U, 1037 }, 1038 [FEAT_SVM] = { 1039 .type = CPUID_FEATURE_WORD, 1040 .feat_names = { 1041 "npt", "lbrv", "svm-lock", "nrip-save", 1042 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1043 NULL, NULL, "pause-filter", NULL, 1044 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1045 "vgif", NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, "vnmi", NULL, NULL, 1048 "svme-addr-chk", NULL, NULL, NULL, 1049 }, 1050 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1051 .tcg_features = TCG_SVM_FEATURES, 1052 }, 1053 [FEAT_7_0_EBX] = { 1054 .type = CPUID_FEATURE_WORD, 1055 .feat_names = { 1056 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1057 "hle", "avx2", NULL, "smep", 1058 "bmi2", "erms", "invpcid", "rtm", 1059 NULL, NULL, "mpx", NULL, 1060 "avx512f", "avx512dq", "rdseed", "adx", 1061 "smap", "avx512ifma", "pcommit", "clflushopt", 1062 "clwb", "intel-pt", "avx512pf", "avx512er", 1063 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1064 }, 1065 .cpuid = { 1066 .eax = 7, 1067 .needs_ecx = true, .ecx = 0, 1068 .reg = R_EBX, 1069 }, 1070 .tcg_features = TCG_7_0_EBX_FEATURES, 1071 }, 1072 [FEAT_7_0_ECX] = { 1073 .type = CPUID_FEATURE_WORD, 1074 .feat_names = { 1075 NULL, "avx512vbmi", "umip", "pku", 1076 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1077 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1078 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1079 "la57", NULL, NULL, NULL, 1080 NULL, NULL, "rdpid", NULL, 1081 "bus-lock-detect", "cldemote", NULL, "movdiri", 1082 "movdir64b", NULL, "sgxlc", "pks", 1083 }, 1084 .cpuid = { 1085 .eax = 7, 1086 .needs_ecx = true, .ecx = 0, 1087 .reg = R_ECX, 1088 }, 1089 .tcg_features = TCG_7_0_ECX_FEATURES, 1090 }, 1091 [FEAT_7_0_EDX] = { 1092 .type = CPUID_FEATURE_WORD, 1093 .feat_names = { 1094 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1095 "fsrm", NULL, NULL, NULL, 1096 "avx512-vp2intersect", NULL, "md-clear", NULL, 1097 NULL, NULL, "serialize", NULL, 1098 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1099 NULL, NULL, "amx-bf16", "avx512-fp16", 1100 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1101 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1102 }, 1103 .cpuid = { 1104 .eax = 7, 1105 .needs_ecx = true, .ecx = 0, 1106 .reg = R_EDX, 1107 }, 1108 .tcg_features = TCG_7_0_EDX_FEATURES, 1109 }, 1110 [FEAT_7_1_EAX] = { 1111 .type = CPUID_FEATURE_WORD, 1112 .feat_names = { 1113 NULL, NULL, NULL, NULL, 1114 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1115 NULL, NULL, "fzrm", "fsrs", 1116 "fsrc", NULL, NULL, NULL, 1117 NULL, "fred", "lkgs", "wrmsrns", 1118 NULL, "amx-fp16", NULL, "avx-ifma", 1119 NULL, NULL, "lam", NULL, 1120 NULL, NULL, NULL, NULL, 1121 }, 1122 .cpuid = { 1123 .eax = 7, 1124 .needs_ecx = true, .ecx = 1, 1125 .reg = R_EAX, 1126 }, 1127 .tcg_features = TCG_7_1_EAX_FEATURES, 1128 }, 1129 [FEAT_7_1_EDX] = { 1130 .type = CPUID_FEATURE_WORD, 1131 .feat_names = { 1132 NULL, NULL, NULL, NULL, 1133 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1134 "amx-complex", NULL, NULL, NULL, 1135 NULL, NULL, "prefetchiti", NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .cpuid = { 1142 .eax = 7, 1143 .needs_ecx = true, .ecx = 1, 1144 .reg = R_EDX, 1145 }, 1146 .tcg_features = TCG_7_1_EDX_FEATURES, 1147 }, 1148 [FEAT_7_2_EDX] = { 1149 .type = CPUID_FEATURE_WORD, 1150 .feat_names = { 1151 NULL, NULL, NULL, NULL, 1152 NULL, "mcdt-no", NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 NULL, NULL, NULL, NULL, 1159 }, 1160 .cpuid = { 1161 .eax = 7, 1162 .needs_ecx = true, .ecx = 2, 1163 .reg = R_EDX, 1164 }, 1165 .tcg_features = TCG_7_2_EDX_FEATURES, 1166 }, 1167 [FEAT_8000_0007_EDX] = { 1168 .type = CPUID_FEATURE_WORD, 1169 .feat_names = { 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 "invtsc", NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 }, 1179 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1180 .tcg_features = TCG_APM_FEATURES, 1181 .unmigratable_flags = CPUID_APM_INVTSC, 1182 }, 1183 [FEAT_8000_0008_EBX] = { 1184 .type = CPUID_FEATURE_WORD, 1185 .feat_names = { 1186 "clzero", NULL, "xsaveerptr", NULL, 1187 NULL, NULL, NULL, NULL, 1188 NULL, "wbnoinvd", NULL, NULL, 1189 "ibpb", NULL, "ibrs", "amd-stibp", 1190 NULL, "stibp-always-on", NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1193 "amd-psfd", NULL, NULL, NULL, 1194 }, 1195 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1196 .tcg_features = TCG_8000_0008_EBX, 1197 .unmigratable_flags = 0, 1198 }, 1199 [FEAT_8000_0021_EAX] = { 1200 .type = CPUID_FEATURE_WORD, 1201 .feat_names = { 1202 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1203 NULL, NULL, "null-sel-clr-base", NULL, 1204 "auto-ibrs", NULL, NULL, NULL, 1205 NULL, NULL, NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 NULL, NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 }, 1211 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1212 .tcg_features = 0, 1213 .unmigratable_flags = 0, 1214 }, 1215 [FEAT_XSAVE] = { 1216 .type = CPUID_FEATURE_WORD, 1217 .feat_names = { 1218 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1219 "xfd", NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 }, 1227 .cpuid = { 1228 .eax = 0xd, 1229 .needs_ecx = true, .ecx = 1, 1230 .reg = R_EAX, 1231 }, 1232 .tcg_features = TCG_XSAVE_FEATURES, 1233 }, 1234 [FEAT_XSAVE_XSS_LO] = { 1235 .type = CPUID_FEATURE_WORD, 1236 .feat_names = { 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 }, 1246 .cpuid = { 1247 .eax = 0xD, 1248 .needs_ecx = true, 1249 .ecx = 1, 1250 .reg = R_ECX, 1251 }, 1252 }, 1253 [FEAT_XSAVE_XSS_HI] = { 1254 .type = CPUID_FEATURE_WORD, 1255 .cpuid = { 1256 .eax = 0xD, 1257 .needs_ecx = true, 1258 .ecx = 1, 1259 .reg = R_EDX 1260 }, 1261 }, 1262 [FEAT_6_EAX] = { 1263 .type = CPUID_FEATURE_WORD, 1264 .feat_names = { 1265 NULL, NULL, "arat", NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 NULL, NULL, NULL, NULL, 1270 NULL, NULL, NULL, NULL, 1271 NULL, NULL, NULL, NULL, 1272 NULL, NULL, NULL, NULL, 1273 }, 1274 .cpuid = { .eax = 6, .reg = R_EAX, }, 1275 .tcg_features = TCG_6_EAX_FEATURES, 1276 }, 1277 [FEAT_XSAVE_XCR0_LO] = { 1278 .type = CPUID_FEATURE_WORD, 1279 .cpuid = { 1280 .eax = 0xD, 1281 .needs_ecx = true, .ecx = 0, 1282 .reg = R_EAX, 1283 }, 1284 .tcg_features = ~0U, 1285 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1286 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1287 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1288 XSTATE_PKRU_MASK, 1289 }, 1290 [FEAT_XSAVE_XCR0_HI] = { 1291 .type = CPUID_FEATURE_WORD, 1292 .cpuid = { 1293 .eax = 0xD, 1294 .needs_ecx = true, .ecx = 0, 1295 .reg = R_EDX, 1296 }, 1297 .tcg_features = ~0U, 1298 }, 1299 /*Below are MSR exposed features*/ 1300 [FEAT_ARCH_CAPABILITIES] = { 1301 .type = MSR_FEATURE_WORD, 1302 .feat_names = { 1303 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1304 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1305 "taa-no", NULL, NULL, NULL, 1306 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1307 NULL, "fb-clear", NULL, NULL, 1308 NULL, NULL, NULL, NULL, 1309 "pbrsb-no", NULL, "gds-no", "rfds-no", 1310 "rfds-clear", NULL, NULL, NULL, 1311 }, 1312 .msr = { 1313 .index = MSR_IA32_ARCH_CAPABILITIES, 1314 }, 1315 /* 1316 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1317 * cannot be read from user mode. Therefore, it has no impact 1318 > on any user-mode operation, and warnings about unsupported 1319 * features do not matter. 1320 */ 1321 .tcg_features = ~0U, 1322 }, 1323 [FEAT_CORE_CAPABILITY] = { 1324 .type = MSR_FEATURE_WORD, 1325 .feat_names = { 1326 NULL, NULL, NULL, NULL, 1327 NULL, "split-lock-detect", NULL, NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 NULL, NULL, NULL, NULL, 1334 }, 1335 .msr = { 1336 .index = MSR_IA32_CORE_CAPABILITY, 1337 }, 1338 }, 1339 [FEAT_PERF_CAPABILITIES] = { 1340 .type = MSR_FEATURE_WORD, 1341 .feat_names = { 1342 NULL, NULL, NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, "full-width-write", NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 NULL, NULL, NULL, NULL, 1350 }, 1351 .msr = { 1352 .index = MSR_IA32_PERF_CAPABILITIES, 1353 }, 1354 }, 1355 1356 [FEAT_VMX_PROCBASED_CTLS] = { 1357 .type = MSR_FEATURE_WORD, 1358 .feat_names = { 1359 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1360 NULL, NULL, NULL, "vmx-hlt-exit", 1361 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1362 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1363 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1364 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1365 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1366 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1367 }, 1368 .msr = { 1369 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1370 } 1371 }, 1372 1373 [FEAT_VMX_SECONDARY_CTLS] = { 1374 .type = MSR_FEATURE_WORD, 1375 .feat_names = { 1376 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1377 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1378 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1379 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1380 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1381 "vmx-xsaves", NULL, NULL, NULL, 1382 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1383 NULL, NULL, NULL, NULL, 1384 }, 1385 .msr = { 1386 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1387 } 1388 }, 1389 1390 [FEAT_VMX_PINBASED_CTLS] = { 1391 .type = MSR_FEATURE_WORD, 1392 .feat_names = { 1393 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1394 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1395 NULL, NULL, NULL, NULL, 1396 NULL, NULL, NULL, NULL, 1397 NULL, NULL, NULL, NULL, 1398 NULL, NULL, NULL, NULL, 1399 NULL, NULL, NULL, NULL, 1400 NULL, NULL, NULL, NULL, 1401 }, 1402 .msr = { 1403 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1404 } 1405 }, 1406 1407 [FEAT_VMX_EXIT_CTLS] = { 1408 .type = MSR_FEATURE_WORD, 1409 /* 1410 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1411 * the LM CPUID bit. 1412 */ 1413 .feat_names = { 1414 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1417 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1418 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1419 "vmx-exit-save-efer", "vmx-exit-load-efer", 1420 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1421 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1422 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1423 }, 1424 .msr = { 1425 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1426 } 1427 }, 1428 1429 [FEAT_VMX_ENTRY_CTLS] = { 1430 .type = MSR_FEATURE_WORD, 1431 .feat_names = { 1432 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1435 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1436 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1437 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1438 NULL, NULL, NULL, NULL, 1439 NULL, NULL, NULL, NULL, 1440 }, 1441 .msr = { 1442 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1443 } 1444 }, 1445 1446 [FEAT_VMX_MISC] = { 1447 .type = MSR_FEATURE_WORD, 1448 .feat_names = { 1449 NULL, NULL, NULL, NULL, 1450 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1451 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1452 NULL, NULL, NULL, NULL, 1453 NULL, NULL, NULL, NULL, 1454 NULL, NULL, NULL, NULL, 1455 NULL, NULL, NULL, NULL, 1456 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1457 }, 1458 .msr = { 1459 .index = MSR_IA32_VMX_MISC, 1460 } 1461 }, 1462 1463 [FEAT_VMX_EPT_VPID_CAPS] = { 1464 .type = MSR_FEATURE_WORD, 1465 .feat_names = { 1466 "vmx-ept-execonly", NULL, NULL, NULL, 1467 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1468 NULL, NULL, NULL, NULL, 1469 NULL, NULL, NULL, NULL, 1470 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1471 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1472 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1473 NULL, NULL, NULL, NULL, 1474 "vmx-invvpid", NULL, NULL, NULL, 1475 NULL, NULL, NULL, NULL, 1476 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1477 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1478 NULL, NULL, NULL, NULL, 1479 NULL, NULL, NULL, NULL, 1480 NULL, NULL, NULL, NULL, 1481 NULL, NULL, NULL, NULL, 1482 NULL, NULL, NULL, NULL, 1483 }, 1484 .msr = { 1485 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1486 } 1487 }, 1488 1489 [FEAT_VMX_BASIC] = { 1490 .type = MSR_FEATURE_WORD, 1491 .feat_names = { 1492 [54] = "vmx-ins-outs", 1493 [55] = "vmx-true-ctls", 1494 [56] = "vmx-any-errcode", 1495 [58] = "vmx-nested-exception", 1496 }, 1497 .msr = { 1498 .index = MSR_IA32_VMX_BASIC, 1499 }, 1500 /* Just to be safe - we don't support setting the MSEG version field. */ 1501 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1502 }, 1503 1504 [FEAT_VMX_VMFUNC] = { 1505 .type = MSR_FEATURE_WORD, 1506 .feat_names = { 1507 [0] = "vmx-eptp-switching", 1508 }, 1509 .msr = { 1510 .index = MSR_IA32_VMX_VMFUNC, 1511 } 1512 }, 1513 1514 [FEAT_14_0_ECX] = { 1515 .type = CPUID_FEATURE_WORD, 1516 .feat_names = { 1517 NULL, NULL, NULL, NULL, 1518 NULL, NULL, NULL, NULL, 1519 NULL, NULL, NULL, NULL, 1520 NULL, NULL, NULL, NULL, 1521 NULL, NULL, NULL, NULL, 1522 NULL, NULL, NULL, NULL, 1523 NULL, NULL, NULL, NULL, 1524 NULL, NULL, NULL, "intel-pt-lip", 1525 }, 1526 .cpuid = { 1527 .eax = 0x14, 1528 .needs_ecx = true, .ecx = 0, 1529 .reg = R_ECX, 1530 }, 1531 .tcg_features = TCG_14_0_ECX_FEATURES, 1532 }, 1533 1534 [FEAT_SGX_12_0_EAX] = { 1535 .type = CPUID_FEATURE_WORD, 1536 .feat_names = { 1537 "sgx1", "sgx2", NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, "sgx-edeccssa", 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 NULL, NULL, NULL, NULL, 1543 NULL, NULL, NULL, NULL, 1544 NULL, NULL, NULL, NULL, 1545 }, 1546 .cpuid = { 1547 .eax = 0x12, 1548 .needs_ecx = true, .ecx = 0, 1549 .reg = R_EAX, 1550 }, 1551 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1552 }, 1553 1554 [FEAT_SGX_12_0_EBX] = { 1555 .type = CPUID_FEATURE_WORD, 1556 .feat_names = { 1557 "sgx-exinfo" , NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 NULL, NULL, NULL, NULL, 1562 NULL, NULL, NULL, NULL, 1563 NULL, NULL, NULL, NULL, 1564 NULL, NULL, NULL, NULL, 1565 }, 1566 .cpuid = { 1567 .eax = 0x12, 1568 .needs_ecx = true, .ecx = 0, 1569 .reg = R_EBX, 1570 }, 1571 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1572 }, 1573 1574 [FEAT_SGX_12_1_EAX] = { 1575 .type = CPUID_FEATURE_WORD, 1576 .feat_names = { 1577 NULL, "sgx-debug", "sgx-mode64", NULL, 1578 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1579 NULL, NULL, "sgx-aex-notify", NULL, 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, NULL, 1584 NULL, NULL, NULL, NULL, 1585 }, 1586 .cpuid = { 1587 .eax = 0x12, 1588 .needs_ecx = true, .ecx = 1, 1589 .reg = R_EAX, 1590 }, 1591 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1592 }, 1593 }; 1594 1595 typedef struct FeatureMask { 1596 FeatureWord index; 1597 uint64_t mask; 1598 } FeatureMask; 1599 1600 typedef struct FeatureDep { 1601 FeatureMask from, to; 1602 } FeatureDep; 1603 1604 static FeatureDep feature_dependencies[] = { 1605 { 1606 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1607 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1608 }, 1609 { 1610 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1611 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1612 }, 1613 { 1614 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1615 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1616 }, 1617 { 1618 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1619 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1620 }, 1621 { 1622 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1623 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1624 }, 1625 { 1626 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1627 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1628 }, 1629 { 1630 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1631 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1632 }, 1633 { 1634 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1635 .to = { FEAT_VMX_MISC, ~0ull }, 1636 }, 1637 { 1638 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1639 .to = { FEAT_VMX_BASIC, ~0ull }, 1640 }, 1641 { 1642 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1643 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1644 }, 1645 { 1646 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1647 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1648 }, 1649 { 1650 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1651 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1652 }, 1653 { 1654 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1655 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1656 }, 1657 { 1658 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1659 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1660 }, 1661 { 1662 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1663 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1664 }, 1665 { 1666 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1667 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1668 }, 1669 { 1670 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1671 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1672 }, 1673 { 1674 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1675 .to = { FEAT_14_0_ECX, ~0ull }, 1676 }, 1677 { 1678 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1679 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1680 }, 1681 { 1682 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1683 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1684 }, 1685 { 1686 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1687 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1688 }, 1689 { 1690 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1691 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1692 }, 1693 { 1694 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1695 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1696 }, 1697 { 1698 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1699 .to = { FEAT_SVM, ~0ull }, 1700 }, 1701 { 1702 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1703 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1704 }, 1705 { 1706 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1707 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1708 }, 1709 { 1710 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1711 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1712 }, 1713 { 1714 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1715 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1716 }, 1717 }; 1718 1719 typedef struct X86RegisterInfo32 { 1720 /* Name of register */ 1721 const char *name; 1722 /* QAPI enum value register */ 1723 X86CPURegister32 qapi_enum; 1724 } X86RegisterInfo32; 1725 1726 #define REGISTER(reg) \ 1727 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1728 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1729 REGISTER(EAX), 1730 REGISTER(ECX), 1731 REGISTER(EDX), 1732 REGISTER(EBX), 1733 REGISTER(ESP), 1734 REGISTER(EBP), 1735 REGISTER(ESI), 1736 REGISTER(EDI), 1737 }; 1738 #undef REGISTER 1739 1740 /* CPUID feature bits available in XSS */ 1741 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1742 1743 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1744 [XSTATE_FP_BIT] = { 1745 /* x87 FP state component is always enabled if XSAVE is supported */ 1746 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1747 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1748 }, 1749 [XSTATE_SSE_BIT] = { 1750 /* SSE state component is always enabled if XSAVE is supported */ 1751 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1752 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1753 }, 1754 [XSTATE_YMM_BIT] = 1755 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1756 .size = sizeof(XSaveAVX) }, 1757 [XSTATE_BNDREGS_BIT] = 1758 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1759 .size = sizeof(XSaveBNDREG) }, 1760 [XSTATE_BNDCSR_BIT] = 1761 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1762 .size = sizeof(XSaveBNDCSR) }, 1763 [XSTATE_OPMASK_BIT] = 1764 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1765 .size = sizeof(XSaveOpmask) }, 1766 [XSTATE_ZMM_Hi256_BIT] = 1767 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1768 .size = sizeof(XSaveZMM_Hi256) }, 1769 [XSTATE_Hi16_ZMM_BIT] = 1770 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1771 .size = sizeof(XSaveHi16_ZMM) }, 1772 [XSTATE_PKRU_BIT] = 1773 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1774 .size = sizeof(XSavePKRU) }, 1775 [XSTATE_ARCH_LBR_BIT] = { 1776 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1777 .offset = 0 /*supervisor mode component, offset = 0 */, 1778 .size = sizeof(XSavesArchLBR) }, 1779 [XSTATE_XTILE_CFG_BIT] = { 1780 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1781 .size = sizeof(XSaveXTILECFG), 1782 }, 1783 [XSTATE_XTILE_DATA_BIT] = { 1784 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1785 .size = sizeof(XSaveXTILEDATA) 1786 }, 1787 }; 1788 1789 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1790 { 1791 uint64_t ret = x86_ext_save_areas[0].size; 1792 const ExtSaveArea *esa; 1793 uint32_t offset = 0; 1794 int i; 1795 1796 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1797 esa = &x86_ext_save_areas[i]; 1798 if ((mask >> i) & 1) { 1799 offset = compacted ? ret : esa->offset; 1800 ret = MAX(ret, offset + esa->size); 1801 } 1802 } 1803 return ret; 1804 } 1805 1806 static inline bool accel_uses_host_cpuid(void) 1807 { 1808 return kvm_enabled() || hvf_enabled(); 1809 } 1810 1811 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1812 { 1813 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1814 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1815 } 1816 1817 /* Return name of 32-bit register, from a R_* constant */ 1818 static const char *get_register_name_32(unsigned int reg) 1819 { 1820 if (reg >= CPU_NB_REGS32) { 1821 return NULL; 1822 } 1823 return x86_reg_info_32[reg].name; 1824 } 1825 1826 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1827 { 1828 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1829 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1830 } 1831 1832 /* 1833 * Returns the set of feature flags that are supported and migratable by 1834 * QEMU, for a given FeatureWord. 1835 */ 1836 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1837 { 1838 FeatureWordInfo *wi = &feature_word_info[w]; 1839 uint64_t r = 0; 1840 int i; 1841 1842 for (i = 0; i < 64; i++) { 1843 uint64_t f = 1ULL << i; 1844 1845 /* If the feature name is known, it is implicitly considered migratable, 1846 * unless it is explicitly set in unmigratable_flags */ 1847 if ((wi->migratable_flags & f) || 1848 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1849 r |= f; 1850 } 1851 } 1852 return r; 1853 } 1854 1855 void host_cpuid(uint32_t function, uint32_t count, 1856 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1857 { 1858 uint32_t vec[4]; 1859 1860 #ifdef __x86_64__ 1861 asm volatile("cpuid" 1862 : "=a"(vec[0]), "=b"(vec[1]), 1863 "=c"(vec[2]), "=d"(vec[3]) 1864 : "0"(function), "c"(count) : "cc"); 1865 #elif defined(__i386__) 1866 asm volatile("pusha \n\t" 1867 "cpuid \n\t" 1868 "mov %%eax, 0(%2) \n\t" 1869 "mov %%ebx, 4(%2) \n\t" 1870 "mov %%ecx, 8(%2) \n\t" 1871 "mov %%edx, 12(%2) \n\t" 1872 "popa" 1873 : : "a"(function), "c"(count), "S"(vec) 1874 : "memory", "cc"); 1875 #else 1876 abort(); 1877 #endif 1878 1879 if (eax) 1880 *eax = vec[0]; 1881 if (ebx) 1882 *ebx = vec[1]; 1883 if (ecx) 1884 *ecx = vec[2]; 1885 if (edx) 1886 *edx = vec[3]; 1887 } 1888 1889 /* CPU class name definitions: */ 1890 1891 /* Return type name for a given CPU model name 1892 * Caller is responsible for freeing the returned string. 1893 */ 1894 static char *x86_cpu_type_name(const char *model_name) 1895 { 1896 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1897 } 1898 1899 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1900 { 1901 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1902 return object_class_by_name(typename); 1903 } 1904 1905 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1906 { 1907 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1908 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1909 return cpu_model_from_type(class_name); 1910 } 1911 1912 typedef struct X86CPUVersionDefinition { 1913 X86CPUVersion version; 1914 const char *alias; 1915 const char *note; 1916 PropValue *props; 1917 const CPUCaches *const cache_info; 1918 } X86CPUVersionDefinition; 1919 1920 /* Base definition for a CPU model */ 1921 typedef struct X86CPUDefinition { 1922 const char *name; 1923 uint32_t level; 1924 uint32_t xlevel; 1925 /* vendor is zero-terminated, 12 character ASCII string */ 1926 char vendor[CPUID_VENDOR_SZ + 1]; 1927 int family; 1928 int model; 1929 int stepping; 1930 FeatureWordArray features; 1931 const char *model_id; 1932 const CPUCaches *const cache_info; 1933 /* 1934 * Definitions for alternative versions of CPU model. 1935 * List is terminated by item with version == 0. 1936 * If NULL, version 1 will be registered automatically. 1937 */ 1938 const X86CPUVersionDefinition *versions; 1939 const char *deprecation_note; 1940 } X86CPUDefinition; 1941 1942 /* Reference to a specific CPU model version */ 1943 struct X86CPUModel { 1944 /* Base CPU definition */ 1945 const X86CPUDefinition *cpudef; 1946 /* CPU model version */ 1947 X86CPUVersion version; 1948 const char *note; 1949 /* 1950 * If true, this is an alias CPU model. 1951 * This matters only for "-cpu help" and query-cpu-definitions 1952 */ 1953 bool is_alias; 1954 }; 1955 1956 /* Get full model name for CPU version */ 1957 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1958 X86CPUVersion version) 1959 { 1960 assert(version > 0); 1961 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1962 } 1963 1964 static const X86CPUVersionDefinition * 1965 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1966 { 1967 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1968 static const X86CPUVersionDefinition default_version_list[] = { 1969 { 1 }, 1970 { /* end of list */ } 1971 }; 1972 1973 return def->versions ?: default_version_list; 1974 } 1975 1976 static const CPUCaches epyc_cache_info = { 1977 .l1d_cache = &(CPUCacheInfo) { 1978 .type = DATA_CACHE, 1979 .level = 1, 1980 .size = 32 * KiB, 1981 .line_size = 64, 1982 .associativity = 8, 1983 .partitions = 1, 1984 .sets = 64, 1985 .lines_per_tag = 1, 1986 .self_init = 1, 1987 .no_invd_sharing = true, 1988 .share_level = CPU_TOPO_LEVEL_CORE, 1989 }, 1990 .l1i_cache = &(CPUCacheInfo) { 1991 .type = INSTRUCTION_CACHE, 1992 .level = 1, 1993 .size = 64 * KiB, 1994 .line_size = 64, 1995 .associativity = 4, 1996 .partitions = 1, 1997 .sets = 256, 1998 .lines_per_tag = 1, 1999 .self_init = 1, 2000 .no_invd_sharing = true, 2001 .share_level = CPU_TOPO_LEVEL_CORE, 2002 }, 2003 .l2_cache = &(CPUCacheInfo) { 2004 .type = UNIFIED_CACHE, 2005 .level = 2, 2006 .size = 512 * KiB, 2007 .line_size = 64, 2008 .associativity = 8, 2009 .partitions = 1, 2010 .sets = 1024, 2011 .lines_per_tag = 1, 2012 .share_level = CPU_TOPO_LEVEL_CORE, 2013 }, 2014 .l3_cache = &(CPUCacheInfo) { 2015 .type = UNIFIED_CACHE, 2016 .level = 3, 2017 .size = 8 * MiB, 2018 .line_size = 64, 2019 .associativity = 16, 2020 .partitions = 1, 2021 .sets = 8192, 2022 .lines_per_tag = 1, 2023 .self_init = true, 2024 .inclusive = true, 2025 .complex_indexing = true, 2026 .share_level = CPU_TOPO_LEVEL_DIE, 2027 }, 2028 }; 2029 2030 static CPUCaches epyc_v4_cache_info = { 2031 .l1d_cache = &(CPUCacheInfo) { 2032 .type = DATA_CACHE, 2033 .level = 1, 2034 .size = 32 * KiB, 2035 .line_size = 64, 2036 .associativity = 8, 2037 .partitions = 1, 2038 .sets = 64, 2039 .lines_per_tag = 1, 2040 .self_init = 1, 2041 .no_invd_sharing = true, 2042 .share_level = CPU_TOPO_LEVEL_CORE, 2043 }, 2044 .l1i_cache = &(CPUCacheInfo) { 2045 .type = INSTRUCTION_CACHE, 2046 .level = 1, 2047 .size = 64 * KiB, 2048 .line_size = 64, 2049 .associativity = 4, 2050 .partitions = 1, 2051 .sets = 256, 2052 .lines_per_tag = 1, 2053 .self_init = 1, 2054 .no_invd_sharing = true, 2055 .share_level = CPU_TOPO_LEVEL_CORE, 2056 }, 2057 .l2_cache = &(CPUCacheInfo) { 2058 .type = UNIFIED_CACHE, 2059 .level = 2, 2060 .size = 512 * KiB, 2061 .line_size = 64, 2062 .associativity = 8, 2063 .partitions = 1, 2064 .sets = 1024, 2065 .lines_per_tag = 1, 2066 .share_level = CPU_TOPO_LEVEL_CORE, 2067 }, 2068 .l3_cache = &(CPUCacheInfo) { 2069 .type = UNIFIED_CACHE, 2070 .level = 3, 2071 .size = 8 * MiB, 2072 .line_size = 64, 2073 .associativity = 16, 2074 .partitions = 1, 2075 .sets = 8192, 2076 .lines_per_tag = 1, 2077 .self_init = true, 2078 .inclusive = true, 2079 .complex_indexing = false, 2080 .share_level = CPU_TOPO_LEVEL_DIE, 2081 }, 2082 }; 2083 2084 static const CPUCaches epyc_rome_cache_info = { 2085 .l1d_cache = &(CPUCacheInfo) { 2086 .type = DATA_CACHE, 2087 .level = 1, 2088 .size = 32 * KiB, 2089 .line_size = 64, 2090 .associativity = 8, 2091 .partitions = 1, 2092 .sets = 64, 2093 .lines_per_tag = 1, 2094 .self_init = 1, 2095 .no_invd_sharing = true, 2096 .share_level = CPU_TOPO_LEVEL_CORE, 2097 }, 2098 .l1i_cache = &(CPUCacheInfo) { 2099 .type = INSTRUCTION_CACHE, 2100 .level = 1, 2101 .size = 32 * KiB, 2102 .line_size = 64, 2103 .associativity = 8, 2104 .partitions = 1, 2105 .sets = 64, 2106 .lines_per_tag = 1, 2107 .self_init = 1, 2108 .no_invd_sharing = true, 2109 .share_level = CPU_TOPO_LEVEL_CORE, 2110 }, 2111 .l2_cache = &(CPUCacheInfo) { 2112 .type = UNIFIED_CACHE, 2113 .level = 2, 2114 .size = 512 * KiB, 2115 .line_size = 64, 2116 .associativity = 8, 2117 .partitions = 1, 2118 .sets = 1024, 2119 .lines_per_tag = 1, 2120 .share_level = CPU_TOPO_LEVEL_CORE, 2121 }, 2122 .l3_cache = &(CPUCacheInfo) { 2123 .type = UNIFIED_CACHE, 2124 .level = 3, 2125 .size = 16 * MiB, 2126 .line_size = 64, 2127 .associativity = 16, 2128 .partitions = 1, 2129 .sets = 16384, 2130 .lines_per_tag = 1, 2131 .self_init = true, 2132 .inclusive = true, 2133 .complex_indexing = true, 2134 .share_level = CPU_TOPO_LEVEL_DIE, 2135 }, 2136 }; 2137 2138 static const CPUCaches epyc_rome_v3_cache_info = { 2139 .l1d_cache = &(CPUCacheInfo) { 2140 .type = DATA_CACHE, 2141 .level = 1, 2142 .size = 32 * KiB, 2143 .line_size = 64, 2144 .associativity = 8, 2145 .partitions = 1, 2146 .sets = 64, 2147 .lines_per_tag = 1, 2148 .self_init = 1, 2149 .no_invd_sharing = true, 2150 .share_level = CPU_TOPO_LEVEL_CORE, 2151 }, 2152 .l1i_cache = &(CPUCacheInfo) { 2153 .type = INSTRUCTION_CACHE, 2154 .level = 1, 2155 .size = 32 * KiB, 2156 .line_size = 64, 2157 .associativity = 8, 2158 .partitions = 1, 2159 .sets = 64, 2160 .lines_per_tag = 1, 2161 .self_init = 1, 2162 .no_invd_sharing = true, 2163 .share_level = CPU_TOPO_LEVEL_CORE, 2164 }, 2165 .l2_cache = &(CPUCacheInfo) { 2166 .type = UNIFIED_CACHE, 2167 .level = 2, 2168 .size = 512 * KiB, 2169 .line_size = 64, 2170 .associativity = 8, 2171 .partitions = 1, 2172 .sets = 1024, 2173 .lines_per_tag = 1, 2174 .share_level = CPU_TOPO_LEVEL_CORE, 2175 }, 2176 .l3_cache = &(CPUCacheInfo) { 2177 .type = UNIFIED_CACHE, 2178 .level = 3, 2179 .size = 16 * MiB, 2180 .line_size = 64, 2181 .associativity = 16, 2182 .partitions = 1, 2183 .sets = 16384, 2184 .lines_per_tag = 1, 2185 .self_init = true, 2186 .inclusive = true, 2187 .complex_indexing = false, 2188 .share_level = CPU_TOPO_LEVEL_DIE, 2189 }, 2190 }; 2191 2192 static const CPUCaches epyc_milan_cache_info = { 2193 .l1d_cache = &(CPUCacheInfo) { 2194 .type = DATA_CACHE, 2195 .level = 1, 2196 .size = 32 * KiB, 2197 .line_size = 64, 2198 .associativity = 8, 2199 .partitions = 1, 2200 .sets = 64, 2201 .lines_per_tag = 1, 2202 .self_init = 1, 2203 .no_invd_sharing = true, 2204 .share_level = CPU_TOPO_LEVEL_CORE, 2205 }, 2206 .l1i_cache = &(CPUCacheInfo) { 2207 .type = INSTRUCTION_CACHE, 2208 .level = 1, 2209 .size = 32 * KiB, 2210 .line_size = 64, 2211 .associativity = 8, 2212 .partitions = 1, 2213 .sets = 64, 2214 .lines_per_tag = 1, 2215 .self_init = 1, 2216 .no_invd_sharing = true, 2217 .share_level = CPU_TOPO_LEVEL_CORE, 2218 }, 2219 .l2_cache = &(CPUCacheInfo) { 2220 .type = UNIFIED_CACHE, 2221 .level = 2, 2222 .size = 512 * KiB, 2223 .line_size = 64, 2224 .associativity = 8, 2225 .partitions = 1, 2226 .sets = 1024, 2227 .lines_per_tag = 1, 2228 .share_level = CPU_TOPO_LEVEL_CORE, 2229 }, 2230 .l3_cache = &(CPUCacheInfo) { 2231 .type = UNIFIED_CACHE, 2232 .level = 3, 2233 .size = 32 * MiB, 2234 .line_size = 64, 2235 .associativity = 16, 2236 .partitions = 1, 2237 .sets = 32768, 2238 .lines_per_tag = 1, 2239 .self_init = true, 2240 .inclusive = true, 2241 .complex_indexing = true, 2242 .share_level = CPU_TOPO_LEVEL_DIE, 2243 }, 2244 }; 2245 2246 static const CPUCaches epyc_milan_v2_cache_info = { 2247 .l1d_cache = &(CPUCacheInfo) { 2248 .type = DATA_CACHE, 2249 .level = 1, 2250 .size = 32 * KiB, 2251 .line_size = 64, 2252 .associativity = 8, 2253 .partitions = 1, 2254 .sets = 64, 2255 .lines_per_tag = 1, 2256 .self_init = 1, 2257 .no_invd_sharing = true, 2258 .share_level = CPU_TOPO_LEVEL_CORE, 2259 }, 2260 .l1i_cache = &(CPUCacheInfo) { 2261 .type = INSTRUCTION_CACHE, 2262 .level = 1, 2263 .size = 32 * KiB, 2264 .line_size = 64, 2265 .associativity = 8, 2266 .partitions = 1, 2267 .sets = 64, 2268 .lines_per_tag = 1, 2269 .self_init = 1, 2270 .no_invd_sharing = true, 2271 .share_level = CPU_TOPO_LEVEL_CORE, 2272 }, 2273 .l2_cache = &(CPUCacheInfo) { 2274 .type = UNIFIED_CACHE, 2275 .level = 2, 2276 .size = 512 * KiB, 2277 .line_size = 64, 2278 .associativity = 8, 2279 .partitions = 1, 2280 .sets = 1024, 2281 .lines_per_tag = 1, 2282 .share_level = CPU_TOPO_LEVEL_CORE, 2283 }, 2284 .l3_cache = &(CPUCacheInfo) { 2285 .type = UNIFIED_CACHE, 2286 .level = 3, 2287 .size = 32 * MiB, 2288 .line_size = 64, 2289 .associativity = 16, 2290 .partitions = 1, 2291 .sets = 32768, 2292 .lines_per_tag = 1, 2293 .self_init = true, 2294 .inclusive = true, 2295 .complex_indexing = false, 2296 .share_level = CPU_TOPO_LEVEL_DIE, 2297 }, 2298 }; 2299 2300 static const CPUCaches epyc_genoa_cache_info = { 2301 .l1d_cache = &(CPUCacheInfo) { 2302 .type = DATA_CACHE, 2303 .level = 1, 2304 .size = 32 * KiB, 2305 .line_size = 64, 2306 .associativity = 8, 2307 .partitions = 1, 2308 .sets = 64, 2309 .lines_per_tag = 1, 2310 .self_init = 1, 2311 .no_invd_sharing = true, 2312 .share_level = CPU_TOPO_LEVEL_CORE, 2313 }, 2314 .l1i_cache = &(CPUCacheInfo) { 2315 .type = INSTRUCTION_CACHE, 2316 .level = 1, 2317 .size = 32 * KiB, 2318 .line_size = 64, 2319 .associativity = 8, 2320 .partitions = 1, 2321 .sets = 64, 2322 .lines_per_tag = 1, 2323 .self_init = 1, 2324 .no_invd_sharing = true, 2325 .share_level = CPU_TOPO_LEVEL_CORE, 2326 }, 2327 .l2_cache = &(CPUCacheInfo) { 2328 .type = UNIFIED_CACHE, 2329 .level = 2, 2330 .size = 1 * MiB, 2331 .line_size = 64, 2332 .associativity = 8, 2333 .partitions = 1, 2334 .sets = 2048, 2335 .lines_per_tag = 1, 2336 .share_level = CPU_TOPO_LEVEL_CORE, 2337 }, 2338 .l3_cache = &(CPUCacheInfo) { 2339 .type = UNIFIED_CACHE, 2340 .level = 3, 2341 .size = 32 * MiB, 2342 .line_size = 64, 2343 .associativity = 16, 2344 .partitions = 1, 2345 .sets = 32768, 2346 .lines_per_tag = 1, 2347 .self_init = true, 2348 .inclusive = true, 2349 .complex_indexing = false, 2350 .share_level = CPU_TOPO_LEVEL_DIE, 2351 }, 2352 }; 2353 2354 /* The following VMX features are not supported by KVM and are left out in the 2355 * CPU definitions: 2356 * 2357 * Dual-monitor support (all processors) 2358 * Entry to SMM 2359 * Deactivate dual-monitor treatment 2360 * Number of CR3-target values 2361 * Shutdown activity state 2362 * Wait-for-SIPI activity state 2363 * PAUSE-loop exiting (Westmere and newer) 2364 * EPT-violation #VE (Broadwell and newer) 2365 * Inject event with insn length=0 (Skylake and newer) 2366 * Conceal non-root operation from PT 2367 * Conceal VM exits from PT 2368 * Conceal VM entries from PT 2369 * Enable ENCLS exiting 2370 * Mode-based execute control (XS/XU) 2371 * TSC scaling (Skylake Server and newer) 2372 * GPA translation for PT (IceLake and newer) 2373 * User wait and pause 2374 * ENCLV exiting 2375 * Load IA32_RTIT_CTL 2376 * Clear IA32_RTIT_CTL 2377 * Advanced VM-exit information for EPT violations 2378 * Sub-page write permissions 2379 * PT in VMX operation 2380 */ 2381 2382 static const X86CPUDefinition builtin_x86_defs[] = { 2383 { 2384 .name = "qemu64", 2385 .level = 0xd, 2386 .vendor = CPUID_VENDOR_AMD, 2387 .family = 15, 2388 .model = 107, 2389 .stepping = 1, 2390 .features[FEAT_1_EDX] = 2391 PPRO_FEATURES | 2392 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2393 CPUID_PSE36, 2394 .features[FEAT_1_ECX] = 2395 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2396 .features[FEAT_8000_0001_EDX] = 2397 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2398 .features[FEAT_8000_0001_ECX] = 2399 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2400 .xlevel = 0x8000000A, 2401 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2402 }, 2403 { 2404 .name = "phenom", 2405 .level = 5, 2406 .vendor = CPUID_VENDOR_AMD, 2407 .family = 16, 2408 .model = 2, 2409 .stepping = 3, 2410 /* Missing: CPUID_HT */ 2411 .features[FEAT_1_EDX] = 2412 PPRO_FEATURES | 2413 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2414 CPUID_PSE36 | CPUID_VME, 2415 .features[FEAT_1_ECX] = 2416 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2417 CPUID_EXT_POPCNT, 2418 .features[FEAT_8000_0001_EDX] = 2419 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2420 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2421 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2422 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2423 CPUID_EXT3_CR8LEG, 2424 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2425 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2426 .features[FEAT_8000_0001_ECX] = 2427 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2428 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2429 /* Missing: CPUID_SVM_LBRV */ 2430 .features[FEAT_SVM] = 2431 CPUID_SVM_NPT, 2432 .xlevel = 0x8000001A, 2433 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2434 }, 2435 { 2436 .name = "core2duo", 2437 .level = 10, 2438 .vendor = CPUID_VENDOR_INTEL, 2439 .family = 6, 2440 .model = 15, 2441 .stepping = 11, 2442 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2443 .features[FEAT_1_EDX] = 2444 PPRO_FEATURES | 2445 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2446 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2447 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2448 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2449 .features[FEAT_1_ECX] = 2450 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2451 CPUID_EXT_CX16, 2452 .features[FEAT_8000_0001_EDX] = 2453 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2454 .features[FEAT_8000_0001_ECX] = 2455 CPUID_EXT3_LAHF_LM, 2456 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2457 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2458 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2459 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2460 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2461 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2462 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2463 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2464 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2465 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2466 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2467 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2468 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2469 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2470 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2471 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2472 .features[FEAT_VMX_SECONDARY_CTLS] = 2473 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2474 .xlevel = 0x80000008, 2475 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2476 }, 2477 { 2478 .name = "kvm64", 2479 .level = 0xd, 2480 .vendor = CPUID_VENDOR_INTEL, 2481 .family = 15, 2482 .model = 6, 2483 .stepping = 1, 2484 /* Missing: CPUID_HT */ 2485 .features[FEAT_1_EDX] = 2486 PPRO_FEATURES | CPUID_VME | 2487 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2488 CPUID_PSE36, 2489 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2490 .features[FEAT_1_ECX] = 2491 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2492 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2493 .features[FEAT_8000_0001_EDX] = 2494 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2495 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2496 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2497 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2498 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2499 .features[FEAT_8000_0001_ECX] = 2500 0, 2501 /* VMX features from Cedar Mill/Prescott */ 2502 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2503 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2504 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2505 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2506 VMX_PIN_BASED_NMI_EXITING, 2507 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2508 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2509 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2510 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2511 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2512 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2513 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2514 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2515 .xlevel = 0x80000008, 2516 .model_id = "Common KVM processor" 2517 }, 2518 { 2519 .name = "qemu32", 2520 .level = 4, 2521 .vendor = CPUID_VENDOR_INTEL, 2522 .family = 6, 2523 .model = 6, 2524 .stepping = 3, 2525 .features[FEAT_1_EDX] = 2526 PPRO_FEATURES, 2527 .features[FEAT_1_ECX] = 2528 CPUID_EXT_SSE3, 2529 .xlevel = 0x80000004, 2530 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2531 }, 2532 { 2533 .name = "kvm32", 2534 .level = 5, 2535 .vendor = CPUID_VENDOR_INTEL, 2536 .family = 15, 2537 .model = 6, 2538 .stepping = 1, 2539 .features[FEAT_1_EDX] = 2540 PPRO_FEATURES | CPUID_VME | 2541 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2542 .features[FEAT_1_ECX] = 2543 CPUID_EXT_SSE3, 2544 .features[FEAT_8000_0001_ECX] = 2545 0, 2546 /* VMX features from Yonah */ 2547 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2548 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2549 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2550 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2551 VMX_PIN_BASED_NMI_EXITING, 2552 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2553 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2554 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2555 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2556 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2557 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2558 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2559 .xlevel = 0x80000008, 2560 .model_id = "Common 32-bit KVM processor" 2561 }, 2562 { 2563 .name = "coreduo", 2564 .level = 10, 2565 .vendor = CPUID_VENDOR_INTEL, 2566 .family = 6, 2567 .model = 14, 2568 .stepping = 8, 2569 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2570 .features[FEAT_1_EDX] = 2571 PPRO_FEATURES | CPUID_VME | 2572 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2573 CPUID_SS, 2574 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2575 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2576 .features[FEAT_1_ECX] = 2577 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2578 .features[FEAT_8000_0001_EDX] = 2579 CPUID_EXT2_NX, 2580 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2581 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2582 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2583 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2584 VMX_PIN_BASED_NMI_EXITING, 2585 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2586 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2587 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2588 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2589 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2590 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2591 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2592 .xlevel = 0x80000008, 2593 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2594 }, 2595 { 2596 .name = "486", 2597 .level = 1, 2598 .vendor = CPUID_VENDOR_INTEL, 2599 .family = 4, 2600 .model = 8, 2601 .stepping = 0, 2602 .features[FEAT_1_EDX] = 2603 I486_FEATURES, 2604 .xlevel = 0, 2605 .model_id = "", 2606 }, 2607 { 2608 .name = "pentium", 2609 .level = 1, 2610 .vendor = CPUID_VENDOR_INTEL, 2611 .family = 5, 2612 .model = 4, 2613 .stepping = 3, 2614 .features[FEAT_1_EDX] = 2615 PENTIUM_FEATURES, 2616 .xlevel = 0, 2617 .model_id = "", 2618 }, 2619 { 2620 .name = "pentium2", 2621 .level = 2, 2622 .vendor = CPUID_VENDOR_INTEL, 2623 .family = 6, 2624 .model = 5, 2625 .stepping = 2, 2626 .features[FEAT_1_EDX] = 2627 PENTIUM2_FEATURES, 2628 .xlevel = 0, 2629 .model_id = "", 2630 }, 2631 { 2632 .name = "pentium3", 2633 .level = 3, 2634 .vendor = CPUID_VENDOR_INTEL, 2635 .family = 6, 2636 .model = 7, 2637 .stepping = 3, 2638 .features[FEAT_1_EDX] = 2639 PENTIUM3_FEATURES, 2640 .xlevel = 0, 2641 .model_id = "", 2642 }, 2643 { 2644 .name = "athlon", 2645 .level = 2, 2646 .vendor = CPUID_VENDOR_AMD, 2647 .family = 6, 2648 .model = 2, 2649 .stepping = 3, 2650 .features[FEAT_1_EDX] = 2651 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2652 CPUID_MCA, 2653 .features[FEAT_8000_0001_EDX] = 2654 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2655 .xlevel = 0x80000008, 2656 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2657 }, 2658 { 2659 .name = "n270", 2660 .level = 10, 2661 .vendor = CPUID_VENDOR_INTEL, 2662 .family = 6, 2663 .model = 28, 2664 .stepping = 2, 2665 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2666 .features[FEAT_1_EDX] = 2667 PPRO_FEATURES | 2668 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2669 CPUID_ACPI | CPUID_SS, 2670 /* Some CPUs got no CPUID_SEP */ 2671 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2672 * CPUID_EXT_XTPR */ 2673 .features[FEAT_1_ECX] = 2674 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2675 CPUID_EXT_MOVBE, 2676 .features[FEAT_8000_0001_EDX] = 2677 CPUID_EXT2_NX, 2678 .features[FEAT_8000_0001_ECX] = 2679 CPUID_EXT3_LAHF_LM, 2680 .xlevel = 0x80000008, 2681 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2682 }, 2683 { 2684 .name = "Conroe", 2685 .level = 10, 2686 .vendor = CPUID_VENDOR_INTEL, 2687 .family = 6, 2688 .model = 15, 2689 .stepping = 3, 2690 .features[FEAT_1_EDX] = 2691 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2692 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2693 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2694 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2695 CPUID_DE | CPUID_FP87, 2696 .features[FEAT_1_ECX] = 2697 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2698 .features[FEAT_8000_0001_EDX] = 2699 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2700 .features[FEAT_8000_0001_ECX] = 2701 CPUID_EXT3_LAHF_LM, 2702 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2703 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2704 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2705 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2706 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2707 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2708 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2709 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2710 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2711 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2712 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2713 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2714 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2715 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2716 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2717 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2718 .features[FEAT_VMX_SECONDARY_CTLS] = 2719 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2720 .xlevel = 0x80000008, 2721 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2722 }, 2723 { 2724 .name = "Penryn", 2725 .level = 10, 2726 .vendor = CPUID_VENDOR_INTEL, 2727 .family = 6, 2728 .model = 23, 2729 .stepping = 3, 2730 .features[FEAT_1_EDX] = 2731 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2732 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2733 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2734 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2735 CPUID_DE | CPUID_FP87, 2736 .features[FEAT_1_ECX] = 2737 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2738 CPUID_EXT_SSE3, 2739 .features[FEAT_8000_0001_EDX] = 2740 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2741 .features[FEAT_8000_0001_ECX] = 2742 CPUID_EXT3_LAHF_LM, 2743 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2744 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2745 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2746 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2747 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2748 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2749 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2750 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2751 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2752 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2753 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2754 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2755 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2756 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2757 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2758 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2759 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2760 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2761 .features[FEAT_VMX_SECONDARY_CTLS] = 2762 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2763 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2764 .xlevel = 0x80000008, 2765 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2766 }, 2767 { 2768 .name = "Nehalem", 2769 .level = 11, 2770 .vendor = CPUID_VENDOR_INTEL, 2771 .family = 6, 2772 .model = 26, 2773 .stepping = 3, 2774 .features[FEAT_1_EDX] = 2775 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2776 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2777 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2778 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2779 CPUID_DE | CPUID_FP87, 2780 .features[FEAT_1_ECX] = 2781 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2782 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2783 .features[FEAT_8000_0001_EDX] = 2784 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2785 .features[FEAT_8000_0001_ECX] = 2786 CPUID_EXT3_LAHF_LM, 2787 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2788 MSR_VMX_BASIC_TRUE_CTLS, 2789 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2790 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2791 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2792 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2793 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2794 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2795 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2796 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2797 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2798 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2799 .features[FEAT_VMX_EXIT_CTLS] = 2800 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2801 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2802 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2803 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2804 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2805 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2806 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2807 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2808 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2809 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2810 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2811 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2812 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2813 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2814 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2815 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2816 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2817 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2818 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2819 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2820 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2821 .features[FEAT_VMX_SECONDARY_CTLS] = 2822 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2823 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2824 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2825 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2826 VMX_SECONDARY_EXEC_ENABLE_VPID, 2827 .xlevel = 0x80000008, 2828 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2829 .versions = (X86CPUVersionDefinition[]) { 2830 { .version = 1 }, 2831 { 2832 .version = 2, 2833 .alias = "Nehalem-IBRS", 2834 .props = (PropValue[]) { 2835 { "spec-ctrl", "on" }, 2836 { "model-id", 2837 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2838 { /* end of list */ } 2839 } 2840 }, 2841 { /* end of list */ } 2842 } 2843 }, 2844 { 2845 .name = "Westmere", 2846 .level = 11, 2847 .vendor = CPUID_VENDOR_INTEL, 2848 .family = 6, 2849 .model = 44, 2850 .stepping = 1, 2851 .features[FEAT_1_EDX] = 2852 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2853 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2854 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2855 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2856 CPUID_DE | CPUID_FP87, 2857 .features[FEAT_1_ECX] = 2858 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2859 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2860 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2861 .features[FEAT_8000_0001_EDX] = 2862 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2863 .features[FEAT_8000_0001_ECX] = 2864 CPUID_EXT3_LAHF_LM, 2865 .features[FEAT_6_EAX] = 2866 CPUID_6_EAX_ARAT, 2867 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2868 MSR_VMX_BASIC_TRUE_CTLS, 2869 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2870 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2871 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2872 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2873 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2874 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2875 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2876 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2877 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2878 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2879 .features[FEAT_VMX_EXIT_CTLS] = 2880 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2881 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2882 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2883 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2884 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2885 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2886 MSR_VMX_MISC_STORE_LMA, 2887 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2888 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2889 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2890 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2891 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2892 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2893 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2894 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2895 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2896 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2897 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2898 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2899 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2900 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2901 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2902 .features[FEAT_VMX_SECONDARY_CTLS] = 2903 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2904 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2905 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2906 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2907 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2908 .xlevel = 0x80000008, 2909 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2910 .versions = (X86CPUVersionDefinition[]) { 2911 { .version = 1 }, 2912 { 2913 .version = 2, 2914 .alias = "Westmere-IBRS", 2915 .props = (PropValue[]) { 2916 { "spec-ctrl", "on" }, 2917 { "model-id", 2918 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2919 { /* end of list */ } 2920 } 2921 }, 2922 { /* end of list */ } 2923 } 2924 }, 2925 { 2926 .name = "SandyBridge", 2927 .level = 0xd, 2928 .vendor = CPUID_VENDOR_INTEL, 2929 .family = 6, 2930 .model = 42, 2931 .stepping = 1, 2932 .features[FEAT_1_EDX] = 2933 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2934 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2935 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2936 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2937 CPUID_DE | CPUID_FP87, 2938 .features[FEAT_1_ECX] = 2939 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2940 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2941 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2942 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2943 CPUID_EXT_SSE3, 2944 .features[FEAT_8000_0001_EDX] = 2945 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2946 CPUID_EXT2_SYSCALL, 2947 .features[FEAT_8000_0001_ECX] = 2948 CPUID_EXT3_LAHF_LM, 2949 .features[FEAT_XSAVE] = 2950 CPUID_XSAVE_XSAVEOPT, 2951 .features[FEAT_6_EAX] = 2952 CPUID_6_EAX_ARAT, 2953 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2954 MSR_VMX_BASIC_TRUE_CTLS, 2955 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2956 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2957 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2958 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2959 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2960 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2961 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2962 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2963 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2964 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2965 .features[FEAT_VMX_EXIT_CTLS] = 2966 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2967 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2968 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2969 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2970 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2971 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2972 MSR_VMX_MISC_STORE_LMA, 2973 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2974 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2975 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2976 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2977 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2978 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2979 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2980 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2981 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2982 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2983 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2984 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2985 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2986 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2987 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2988 .features[FEAT_VMX_SECONDARY_CTLS] = 2989 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2990 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2991 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2992 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2993 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2994 .xlevel = 0x80000008, 2995 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2996 .versions = (X86CPUVersionDefinition[]) { 2997 { .version = 1 }, 2998 { 2999 .version = 2, 3000 .alias = "SandyBridge-IBRS", 3001 .props = (PropValue[]) { 3002 { "spec-ctrl", "on" }, 3003 { "model-id", 3004 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3005 { /* end of list */ } 3006 } 3007 }, 3008 { /* end of list */ } 3009 } 3010 }, 3011 { 3012 .name = "IvyBridge", 3013 .level = 0xd, 3014 .vendor = CPUID_VENDOR_INTEL, 3015 .family = 6, 3016 .model = 58, 3017 .stepping = 9, 3018 .features[FEAT_1_EDX] = 3019 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3020 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3021 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3022 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3023 CPUID_DE | CPUID_FP87, 3024 .features[FEAT_1_ECX] = 3025 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3026 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3027 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3028 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3029 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3030 .features[FEAT_7_0_EBX] = 3031 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3032 CPUID_7_0_EBX_ERMS, 3033 .features[FEAT_8000_0001_EDX] = 3034 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3035 CPUID_EXT2_SYSCALL, 3036 .features[FEAT_8000_0001_ECX] = 3037 CPUID_EXT3_LAHF_LM, 3038 .features[FEAT_XSAVE] = 3039 CPUID_XSAVE_XSAVEOPT, 3040 .features[FEAT_6_EAX] = 3041 CPUID_6_EAX_ARAT, 3042 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3043 MSR_VMX_BASIC_TRUE_CTLS, 3044 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3045 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3046 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3047 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3048 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3049 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3050 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3051 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3052 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3053 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3054 .features[FEAT_VMX_EXIT_CTLS] = 3055 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3056 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3057 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3058 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3059 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3060 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3061 MSR_VMX_MISC_STORE_LMA, 3062 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3063 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3064 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3065 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3066 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3067 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3068 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3069 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3070 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3071 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3072 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3073 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3074 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3075 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3076 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3077 .features[FEAT_VMX_SECONDARY_CTLS] = 3078 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3079 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3080 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3081 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3082 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3083 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3084 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3085 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3086 .xlevel = 0x80000008, 3087 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3088 .versions = (X86CPUVersionDefinition[]) { 3089 { .version = 1 }, 3090 { 3091 .version = 2, 3092 .alias = "IvyBridge-IBRS", 3093 .props = (PropValue[]) { 3094 { "spec-ctrl", "on" }, 3095 { "model-id", 3096 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3097 { /* end of list */ } 3098 } 3099 }, 3100 { /* end of list */ } 3101 } 3102 }, 3103 { 3104 .name = "Haswell", 3105 .level = 0xd, 3106 .vendor = CPUID_VENDOR_INTEL, 3107 .family = 6, 3108 .model = 60, 3109 .stepping = 4, 3110 .features[FEAT_1_EDX] = 3111 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3112 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3113 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3114 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3115 CPUID_DE | CPUID_FP87, 3116 .features[FEAT_1_ECX] = 3117 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3118 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3119 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3120 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3121 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3122 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3123 .features[FEAT_8000_0001_EDX] = 3124 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3125 CPUID_EXT2_SYSCALL, 3126 .features[FEAT_8000_0001_ECX] = 3127 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3128 .features[FEAT_7_0_EBX] = 3129 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3130 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3131 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3132 CPUID_7_0_EBX_RTM, 3133 .features[FEAT_XSAVE] = 3134 CPUID_XSAVE_XSAVEOPT, 3135 .features[FEAT_6_EAX] = 3136 CPUID_6_EAX_ARAT, 3137 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3138 MSR_VMX_BASIC_TRUE_CTLS, 3139 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3140 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3141 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3142 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3143 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3144 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3145 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3146 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3147 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3148 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3149 .features[FEAT_VMX_EXIT_CTLS] = 3150 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3151 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3152 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3153 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3154 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3155 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3156 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3157 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3158 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3159 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3160 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3161 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3162 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3163 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3164 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3165 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3166 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3167 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3168 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3169 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3170 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3171 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3172 .features[FEAT_VMX_SECONDARY_CTLS] = 3173 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3174 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3175 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3176 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3177 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3178 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3179 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3180 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3181 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3182 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3183 .xlevel = 0x80000008, 3184 .model_id = "Intel Core Processor (Haswell)", 3185 .versions = (X86CPUVersionDefinition[]) { 3186 { .version = 1 }, 3187 { 3188 .version = 2, 3189 .alias = "Haswell-noTSX", 3190 .props = (PropValue[]) { 3191 { "hle", "off" }, 3192 { "rtm", "off" }, 3193 { "stepping", "1" }, 3194 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3195 { /* end of list */ } 3196 }, 3197 }, 3198 { 3199 .version = 3, 3200 .alias = "Haswell-IBRS", 3201 .props = (PropValue[]) { 3202 /* Restore TSX features removed by -v2 above */ 3203 { "hle", "on" }, 3204 { "rtm", "on" }, 3205 /* 3206 * Haswell and Haswell-IBRS had stepping=4 in 3207 * QEMU 4.0 and older 3208 */ 3209 { "stepping", "4" }, 3210 { "spec-ctrl", "on" }, 3211 { "model-id", 3212 "Intel Core Processor (Haswell, IBRS)" }, 3213 { /* end of list */ } 3214 } 3215 }, 3216 { 3217 .version = 4, 3218 .alias = "Haswell-noTSX-IBRS", 3219 .props = (PropValue[]) { 3220 { "hle", "off" }, 3221 { "rtm", "off" }, 3222 /* spec-ctrl was already enabled by -v3 above */ 3223 { "stepping", "1" }, 3224 { "model-id", 3225 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3226 { /* end of list */ } 3227 } 3228 }, 3229 { /* end of list */ } 3230 } 3231 }, 3232 { 3233 .name = "Broadwell", 3234 .level = 0xd, 3235 .vendor = CPUID_VENDOR_INTEL, 3236 .family = 6, 3237 .model = 61, 3238 .stepping = 2, 3239 .features[FEAT_1_EDX] = 3240 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3241 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3242 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3243 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3244 CPUID_DE | CPUID_FP87, 3245 .features[FEAT_1_ECX] = 3246 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3247 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3248 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3249 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3250 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3251 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3252 .features[FEAT_8000_0001_EDX] = 3253 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3254 CPUID_EXT2_SYSCALL, 3255 .features[FEAT_8000_0001_ECX] = 3256 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3257 .features[FEAT_7_0_EBX] = 3258 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3259 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3260 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3261 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3262 CPUID_7_0_EBX_SMAP, 3263 .features[FEAT_XSAVE] = 3264 CPUID_XSAVE_XSAVEOPT, 3265 .features[FEAT_6_EAX] = 3266 CPUID_6_EAX_ARAT, 3267 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3268 MSR_VMX_BASIC_TRUE_CTLS, 3269 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3270 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3271 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3272 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3273 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3274 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3275 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3276 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3277 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3278 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3279 .features[FEAT_VMX_EXIT_CTLS] = 3280 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3281 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3282 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3283 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3284 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3285 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3286 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3287 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3288 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3289 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3290 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3291 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3292 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3293 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3294 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3295 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3296 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3297 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3298 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3299 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3300 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3301 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3302 .features[FEAT_VMX_SECONDARY_CTLS] = 3303 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3304 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3305 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3306 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3307 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3308 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3309 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3310 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3311 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3312 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3313 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3314 .xlevel = 0x80000008, 3315 .model_id = "Intel Core Processor (Broadwell)", 3316 .versions = (X86CPUVersionDefinition[]) { 3317 { .version = 1 }, 3318 { 3319 .version = 2, 3320 .alias = "Broadwell-noTSX", 3321 .props = (PropValue[]) { 3322 { "hle", "off" }, 3323 { "rtm", "off" }, 3324 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3325 { /* end of list */ } 3326 }, 3327 }, 3328 { 3329 .version = 3, 3330 .alias = "Broadwell-IBRS", 3331 .props = (PropValue[]) { 3332 /* Restore TSX features removed by -v2 above */ 3333 { "hle", "on" }, 3334 { "rtm", "on" }, 3335 { "spec-ctrl", "on" }, 3336 { "model-id", 3337 "Intel Core Processor (Broadwell, IBRS)" }, 3338 { /* end of list */ } 3339 } 3340 }, 3341 { 3342 .version = 4, 3343 .alias = "Broadwell-noTSX-IBRS", 3344 .props = (PropValue[]) { 3345 { "hle", "off" }, 3346 { "rtm", "off" }, 3347 /* spec-ctrl was already enabled by -v3 above */ 3348 { "model-id", 3349 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3350 { /* end of list */ } 3351 } 3352 }, 3353 { /* end of list */ } 3354 } 3355 }, 3356 { 3357 .name = "Skylake-Client", 3358 .level = 0xd, 3359 .vendor = CPUID_VENDOR_INTEL, 3360 .family = 6, 3361 .model = 94, 3362 .stepping = 3, 3363 .features[FEAT_1_EDX] = 3364 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3365 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3366 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3367 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3368 CPUID_DE | CPUID_FP87, 3369 .features[FEAT_1_ECX] = 3370 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3371 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3372 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3373 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3374 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3375 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3376 .features[FEAT_8000_0001_EDX] = 3377 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3378 CPUID_EXT2_SYSCALL, 3379 .features[FEAT_8000_0001_ECX] = 3380 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3381 .features[FEAT_7_0_EBX] = 3382 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3383 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3384 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3385 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3386 CPUID_7_0_EBX_SMAP, 3387 /* XSAVES is added in version 4 */ 3388 .features[FEAT_XSAVE] = 3389 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3390 CPUID_XSAVE_XGETBV1, 3391 .features[FEAT_6_EAX] = 3392 CPUID_6_EAX_ARAT, 3393 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3394 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3395 MSR_VMX_BASIC_TRUE_CTLS, 3396 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3397 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3398 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3399 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3400 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3401 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3402 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3403 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3404 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3405 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3406 .features[FEAT_VMX_EXIT_CTLS] = 3407 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3408 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3409 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3410 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3411 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3412 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3413 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3414 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3415 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3416 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3417 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3418 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3419 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3420 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3421 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3422 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3423 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3424 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3425 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3426 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3427 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3428 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3429 .features[FEAT_VMX_SECONDARY_CTLS] = 3430 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3431 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3432 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3433 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3434 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3435 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3436 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3437 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3438 .xlevel = 0x80000008, 3439 .model_id = "Intel Core Processor (Skylake)", 3440 .versions = (X86CPUVersionDefinition[]) { 3441 { .version = 1 }, 3442 { 3443 .version = 2, 3444 .alias = "Skylake-Client-IBRS", 3445 .props = (PropValue[]) { 3446 { "spec-ctrl", "on" }, 3447 { "model-id", 3448 "Intel Core Processor (Skylake, IBRS)" }, 3449 { /* end of list */ } 3450 } 3451 }, 3452 { 3453 .version = 3, 3454 .alias = "Skylake-Client-noTSX-IBRS", 3455 .props = (PropValue[]) { 3456 { "hle", "off" }, 3457 { "rtm", "off" }, 3458 { "model-id", 3459 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3460 { /* end of list */ } 3461 } 3462 }, 3463 { 3464 .version = 4, 3465 .note = "IBRS, XSAVES, no TSX", 3466 .props = (PropValue[]) { 3467 { "xsaves", "on" }, 3468 { "vmx-xsaves", "on" }, 3469 { /* end of list */ } 3470 } 3471 }, 3472 { /* end of list */ } 3473 } 3474 }, 3475 { 3476 .name = "Skylake-Server", 3477 .level = 0xd, 3478 .vendor = CPUID_VENDOR_INTEL, 3479 .family = 6, 3480 .model = 85, 3481 .stepping = 4, 3482 .features[FEAT_1_EDX] = 3483 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3484 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3485 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3486 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3487 CPUID_DE | CPUID_FP87, 3488 .features[FEAT_1_ECX] = 3489 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3490 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3491 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3492 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3493 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3494 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3495 .features[FEAT_8000_0001_EDX] = 3496 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3497 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3498 .features[FEAT_8000_0001_ECX] = 3499 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3500 .features[FEAT_7_0_EBX] = 3501 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3502 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3503 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3504 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3505 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3506 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3507 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3508 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3509 .features[FEAT_7_0_ECX] = 3510 CPUID_7_0_ECX_PKU, 3511 /* XSAVES is added in version 5 */ 3512 .features[FEAT_XSAVE] = 3513 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3514 CPUID_XSAVE_XGETBV1, 3515 .features[FEAT_6_EAX] = 3516 CPUID_6_EAX_ARAT, 3517 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3518 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3519 MSR_VMX_BASIC_TRUE_CTLS, 3520 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3521 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3522 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3523 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3524 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3525 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3526 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3527 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3528 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3529 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3530 .features[FEAT_VMX_EXIT_CTLS] = 3531 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3532 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3533 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3534 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3535 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3536 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3537 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3538 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3539 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3540 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3541 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3542 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3543 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3544 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3545 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3546 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3547 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3548 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3549 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3550 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3551 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3552 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3553 .features[FEAT_VMX_SECONDARY_CTLS] = 3554 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3555 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3556 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3557 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3558 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3559 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3560 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3561 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3562 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3563 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3564 .xlevel = 0x80000008, 3565 .model_id = "Intel Xeon Processor (Skylake)", 3566 .versions = (X86CPUVersionDefinition[]) { 3567 { .version = 1 }, 3568 { 3569 .version = 2, 3570 .alias = "Skylake-Server-IBRS", 3571 .props = (PropValue[]) { 3572 /* clflushopt was not added to Skylake-Server-IBRS */ 3573 /* TODO: add -v3 including clflushopt */ 3574 { "clflushopt", "off" }, 3575 { "spec-ctrl", "on" }, 3576 { "model-id", 3577 "Intel Xeon Processor (Skylake, IBRS)" }, 3578 { /* end of list */ } 3579 } 3580 }, 3581 { 3582 .version = 3, 3583 .alias = "Skylake-Server-noTSX-IBRS", 3584 .props = (PropValue[]) { 3585 { "hle", "off" }, 3586 { "rtm", "off" }, 3587 { "model-id", 3588 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3589 { /* end of list */ } 3590 } 3591 }, 3592 { 3593 .version = 4, 3594 .props = (PropValue[]) { 3595 { "vmx-eptp-switching", "on" }, 3596 { /* end of list */ } 3597 } 3598 }, 3599 { 3600 .version = 5, 3601 .note = "IBRS, XSAVES, EPT switching, no TSX", 3602 .props = (PropValue[]) { 3603 { "xsaves", "on" }, 3604 { "vmx-xsaves", "on" }, 3605 { /* end of list */ } 3606 } 3607 }, 3608 { /* end of list */ } 3609 } 3610 }, 3611 { 3612 .name = "Cascadelake-Server", 3613 .level = 0xd, 3614 .vendor = CPUID_VENDOR_INTEL, 3615 .family = 6, 3616 .model = 85, 3617 .stepping = 6, 3618 .features[FEAT_1_EDX] = 3619 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3620 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3621 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3622 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3623 CPUID_DE | CPUID_FP87, 3624 .features[FEAT_1_ECX] = 3625 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3626 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3627 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3628 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3629 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3630 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3631 .features[FEAT_8000_0001_EDX] = 3632 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3633 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3634 .features[FEAT_8000_0001_ECX] = 3635 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3636 .features[FEAT_7_0_EBX] = 3637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3638 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3639 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3640 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3641 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3642 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3643 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3644 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3645 .features[FEAT_7_0_ECX] = 3646 CPUID_7_0_ECX_PKU | 3647 CPUID_7_0_ECX_AVX512VNNI, 3648 .features[FEAT_7_0_EDX] = 3649 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3650 /* XSAVES is added in version 5 */ 3651 .features[FEAT_XSAVE] = 3652 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3653 CPUID_XSAVE_XGETBV1, 3654 .features[FEAT_6_EAX] = 3655 CPUID_6_EAX_ARAT, 3656 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3657 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3658 MSR_VMX_BASIC_TRUE_CTLS, 3659 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3660 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3661 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3662 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3663 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3664 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3665 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3666 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3667 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3668 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3669 .features[FEAT_VMX_EXIT_CTLS] = 3670 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3671 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3672 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3673 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3674 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3675 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3676 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3677 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3678 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3679 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3680 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3681 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3682 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3683 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3684 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3685 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3686 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3687 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3688 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3689 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3690 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3691 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3692 .features[FEAT_VMX_SECONDARY_CTLS] = 3693 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3694 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3695 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3696 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3697 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3698 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3699 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3700 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3701 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3702 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3703 .xlevel = 0x80000008, 3704 .model_id = "Intel Xeon Processor (Cascadelake)", 3705 .versions = (X86CPUVersionDefinition[]) { 3706 { .version = 1 }, 3707 { .version = 2, 3708 .note = "ARCH_CAPABILITIES", 3709 .props = (PropValue[]) { 3710 { "arch-capabilities", "on" }, 3711 { "rdctl-no", "on" }, 3712 { "ibrs-all", "on" }, 3713 { "skip-l1dfl-vmentry", "on" }, 3714 { "mds-no", "on" }, 3715 { /* end of list */ } 3716 }, 3717 }, 3718 { .version = 3, 3719 .alias = "Cascadelake-Server-noTSX", 3720 .note = "ARCH_CAPABILITIES, no TSX", 3721 .props = (PropValue[]) { 3722 { "hle", "off" }, 3723 { "rtm", "off" }, 3724 { /* end of list */ } 3725 }, 3726 }, 3727 { .version = 4, 3728 .note = "ARCH_CAPABILITIES, no TSX", 3729 .props = (PropValue[]) { 3730 { "vmx-eptp-switching", "on" }, 3731 { /* end of list */ } 3732 }, 3733 }, 3734 { .version = 5, 3735 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3736 .props = (PropValue[]) { 3737 { "xsaves", "on" }, 3738 { "vmx-xsaves", "on" }, 3739 { /* end of list */ } 3740 }, 3741 }, 3742 { /* end of list */ } 3743 } 3744 }, 3745 { 3746 .name = "Cooperlake", 3747 .level = 0xd, 3748 .vendor = CPUID_VENDOR_INTEL, 3749 .family = 6, 3750 .model = 85, 3751 .stepping = 10, 3752 .features[FEAT_1_EDX] = 3753 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3754 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3755 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3756 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3757 CPUID_DE | CPUID_FP87, 3758 .features[FEAT_1_ECX] = 3759 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3760 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3761 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3762 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3763 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3764 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3765 .features[FEAT_8000_0001_EDX] = 3766 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3767 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3768 .features[FEAT_8000_0001_ECX] = 3769 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3770 .features[FEAT_7_0_EBX] = 3771 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3772 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3773 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3774 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3775 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3776 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3777 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3778 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3779 .features[FEAT_7_0_ECX] = 3780 CPUID_7_0_ECX_PKU | 3781 CPUID_7_0_ECX_AVX512VNNI, 3782 .features[FEAT_7_0_EDX] = 3783 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3784 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3785 .features[FEAT_ARCH_CAPABILITIES] = 3786 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3787 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3788 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3789 .features[FEAT_7_1_EAX] = 3790 CPUID_7_1_EAX_AVX512_BF16, 3791 /* XSAVES is added in version 2 */ 3792 .features[FEAT_XSAVE] = 3793 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3794 CPUID_XSAVE_XGETBV1, 3795 .features[FEAT_6_EAX] = 3796 CPUID_6_EAX_ARAT, 3797 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3798 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3799 MSR_VMX_BASIC_TRUE_CTLS, 3800 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3801 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3802 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3803 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3804 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3805 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3806 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3807 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3808 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3809 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3810 .features[FEAT_VMX_EXIT_CTLS] = 3811 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3812 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3813 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3814 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3815 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3816 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3817 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3818 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3819 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3820 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3821 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3822 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3823 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3824 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3825 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3826 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3827 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3828 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3829 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3830 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3831 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3832 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3833 .features[FEAT_VMX_SECONDARY_CTLS] = 3834 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3835 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3836 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3837 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3838 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3839 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3840 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3841 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3842 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3843 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3844 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3845 .xlevel = 0x80000008, 3846 .model_id = "Intel Xeon Processor (Cooperlake)", 3847 .versions = (X86CPUVersionDefinition[]) { 3848 { .version = 1 }, 3849 { .version = 2, 3850 .note = "XSAVES", 3851 .props = (PropValue[]) { 3852 { "xsaves", "on" }, 3853 { "vmx-xsaves", "on" }, 3854 { /* end of list */ } 3855 }, 3856 }, 3857 { /* end of list */ } 3858 } 3859 }, 3860 { 3861 .name = "Icelake-Server", 3862 .level = 0xd, 3863 .vendor = CPUID_VENDOR_INTEL, 3864 .family = 6, 3865 .model = 134, 3866 .stepping = 0, 3867 .features[FEAT_1_EDX] = 3868 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3869 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3870 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3871 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3872 CPUID_DE | CPUID_FP87, 3873 .features[FEAT_1_ECX] = 3874 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3875 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3876 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3877 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3878 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3879 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3880 .features[FEAT_8000_0001_EDX] = 3881 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3882 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3883 .features[FEAT_8000_0001_ECX] = 3884 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3885 .features[FEAT_8000_0008_EBX] = 3886 CPUID_8000_0008_EBX_WBNOINVD, 3887 .features[FEAT_7_0_EBX] = 3888 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3889 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3890 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3891 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3892 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3893 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3894 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3895 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3896 .features[FEAT_7_0_ECX] = 3897 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3898 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3899 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3900 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3901 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3902 .features[FEAT_7_0_EDX] = 3903 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3904 /* XSAVES is added in version 5 */ 3905 .features[FEAT_XSAVE] = 3906 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3907 CPUID_XSAVE_XGETBV1, 3908 .features[FEAT_6_EAX] = 3909 CPUID_6_EAX_ARAT, 3910 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3911 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3912 MSR_VMX_BASIC_TRUE_CTLS, 3913 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3914 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3915 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3916 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3917 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3918 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3919 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3920 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3921 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3922 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3923 .features[FEAT_VMX_EXIT_CTLS] = 3924 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3925 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3926 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3927 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3928 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3929 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3930 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3931 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3932 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3933 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3934 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3935 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3936 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3937 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3938 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3939 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3940 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3941 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3942 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3943 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3944 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3945 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3946 .features[FEAT_VMX_SECONDARY_CTLS] = 3947 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3948 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3949 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3950 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3951 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3952 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3953 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3954 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3955 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3956 .xlevel = 0x80000008, 3957 .model_id = "Intel Xeon Processor (Icelake)", 3958 .versions = (X86CPUVersionDefinition[]) { 3959 { .version = 1 }, 3960 { 3961 .version = 2, 3962 .note = "no TSX", 3963 .alias = "Icelake-Server-noTSX", 3964 .props = (PropValue[]) { 3965 { "hle", "off" }, 3966 { "rtm", "off" }, 3967 { /* end of list */ } 3968 }, 3969 }, 3970 { 3971 .version = 3, 3972 .props = (PropValue[]) { 3973 { "arch-capabilities", "on" }, 3974 { "rdctl-no", "on" }, 3975 { "ibrs-all", "on" }, 3976 { "skip-l1dfl-vmentry", "on" }, 3977 { "mds-no", "on" }, 3978 { "pschange-mc-no", "on" }, 3979 { "taa-no", "on" }, 3980 { /* end of list */ } 3981 }, 3982 }, 3983 { 3984 .version = 4, 3985 .props = (PropValue[]) { 3986 { "sha-ni", "on" }, 3987 { "avx512ifma", "on" }, 3988 { "rdpid", "on" }, 3989 { "fsrm", "on" }, 3990 { "vmx-rdseed-exit", "on" }, 3991 { "vmx-pml", "on" }, 3992 { "vmx-eptp-switching", "on" }, 3993 { "model", "106" }, 3994 { /* end of list */ } 3995 }, 3996 }, 3997 { 3998 .version = 5, 3999 .note = "XSAVES", 4000 .props = (PropValue[]) { 4001 { "xsaves", "on" }, 4002 { "vmx-xsaves", "on" }, 4003 { /* end of list */ } 4004 }, 4005 }, 4006 { 4007 .version = 6, 4008 .note = "5-level EPT", 4009 .props = (PropValue[]) { 4010 { "vmx-page-walk-5", "on" }, 4011 { /* end of list */ } 4012 }, 4013 }, 4014 { 4015 .version = 7, 4016 .note = "TSX, taa-no", 4017 .props = (PropValue[]) { 4018 /* Restore TSX features removed by -v2 above */ 4019 { "hle", "on" }, 4020 { "rtm", "on" }, 4021 { /* end of list */ } 4022 }, 4023 }, 4024 { /* end of list */ } 4025 } 4026 }, 4027 { 4028 .name = "SapphireRapids", 4029 .level = 0x20, 4030 .vendor = CPUID_VENDOR_INTEL, 4031 .family = 6, 4032 .model = 143, 4033 .stepping = 4, 4034 /* 4035 * please keep the ascending order so that we can have a clear view of 4036 * bit position of each feature. 4037 */ 4038 .features[FEAT_1_EDX] = 4039 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4040 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4041 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4042 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4043 CPUID_SSE | CPUID_SSE2, 4044 .features[FEAT_1_ECX] = 4045 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4046 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4047 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4048 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4049 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4050 .features[FEAT_8000_0001_EDX] = 4051 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4052 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4053 .features[FEAT_8000_0001_ECX] = 4054 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4055 .features[FEAT_8000_0008_EBX] = 4056 CPUID_8000_0008_EBX_WBNOINVD, 4057 .features[FEAT_7_0_EBX] = 4058 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4059 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4060 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4061 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4062 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4063 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4064 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4065 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4066 .features[FEAT_7_0_ECX] = 4067 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4068 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4069 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4070 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4071 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4072 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4073 .features[FEAT_7_0_EDX] = 4074 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4075 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4076 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4077 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4078 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4079 .features[FEAT_ARCH_CAPABILITIES] = 4080 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4081 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4082 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4083 .features[FEAT_XSAVE] = 4084 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4085 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4086 .features[FEAT_6_EAX] = 4087 CPUID_6_EAX_ARAT, 4088 .features[FEAT_7_1_EAX] = 4089 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4090 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4091 .features[FEAT_VMX_BASIC] = 4092 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4093 .features[FEAT_VMX_ENTRY_CTLS] = 4094 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4095 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4096 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4097 .features[FEAT_VMX_EPT_VPID_CAPS] = 4098 MSR_VMX_EPT_EXECONLY | 4099 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4100 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4101 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4102 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4103 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4104 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4105 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4106 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4107 .features[FEAT_VMX_EXIT_CTLS] = 4108 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4109 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4110 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4111 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4112 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4113 .features[FEAT_VMX_MISC] = 4114 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4115 MSR_VMX_MISC_VMWRITE_VMEXIT, 4116 .features[FEAT_VMX_PINBASED_CTLS] = 4117 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4118 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4119 VMX_PIN_BASED_POSTED_INTR, 4120 .features[FEAT_VMX_PROCBASED_CTLS] = 4121 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4122 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4123 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4124 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4125 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4126 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4127 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4128 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4129 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4130 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4131 VMX_CPU_BASED_PAUSE_EXITING | 4132 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4133 .features[FEAT_VMX_SECONDARY_CTLS] = 4134 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4135 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4136 VMX_SECONDARY_EXEC_RDTSCP | 4137 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4138 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4139 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4140 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4141 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4142 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4143 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4144 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4145 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4146 VMX_SECONDARY_EXEC_XSAVES, 4147 .features[FEAT_VMX_VMFUNC] = 4148 MSR_VMX_VMFUNC_EPT_SWITCHING, 4149 .xlevel = 0x80000008, 4150 .model_id = "Intel Xeon Processor (SapphireRapids)", 4151 .versions = (X86CPUVersionDefinition[]) { 4152 { .version = 1 }, 4153 { 4154 .version = 2, 4155 .props = (PropValue[]) { 4156 { "sbdr-ssdp-no", "on" }, 4157 { "fbsdp-no", "on" }, 4158 { "psdp-no", "on" }, 4159 { /* end of list */ } 4160 } 4161 }, 4162 { 4163 .version = 3, 4164 .props = (PropValue[]) { 4165 { "ss", "on" }, 4166 { "tsc-adjust", "on" }, 4167 { "cldemote", "on" }, 4168 { "movdiri", "on" }, 4169 { "movdir64b", "on" }, 4170 { /* end of list */ } 4171 } 4172 }, 4173 { /* end of list */ } 4174 } 4175 }, 4176 { 4177 .name = "GraniteRapids", 4178 .level = 0x20, 4179 .vendor = CPUID_VENDOR_INTEL, 4180 .family = 6, 4181 .model = 173, 4182 .stepping = 0, 4183 /* 4184 * please keep the ascending order so that we can have a clear view of 4185 * bit position of each feature. 4186 */ 4187 .features[FEAT_1_EDX] = 4188 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4189 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4190 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4191 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4192 CPUID_SSE | CPUID_SSE2, 4193 .features[FEAT_1_ECX] = 4194 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4195 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4196 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4197 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4198 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4199 .features[FEAT_8000_0001_EDX] = 4200 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4201 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4202 .features[FEAT_8000_0001_ECX] = 4203 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4204 .features[FEAT_8000_0008_EBX] = 4205 CPUID_8000_0008_EBX_WBNOINVD, 4206 .features[FEAT_7_0_EBX] = 4207 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4208 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4209 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4210 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4211 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4212 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4213 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4214 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4215 .features[FEAT_7_0_ECX] = 4216 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4217 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4218 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4219 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4220 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4221 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4222 .features[FEAT_7_0_EDX] = 4223 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4224 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4225 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4226 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4227 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4228 .features[FEAT_ARCH_CAPABILITIES] = 4229 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4230 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4231 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4232 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4233 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4234 .features[FEAT_XSAVE] = 4235 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4236 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4237 .features[FEAT_6_EAX] = 4238 CPUID_6_EAX_ARAT, 4239 .features[FEAT_7_1_EAX] = 4240 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4241 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4242 CPUID_7_1_EAX_AMX_FP16, 4243 .features[FEAT_7_1_EDX] = 4244 CPUID_7_1_EDX_PREFETCHITI, 4245 .features[FEAT_7_2_EDX] = 4246 CPUID_7_2_EDX_MCDT_NO, 4247 .features[FEAT_VMX_BASIC] = 4248 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4249 .features[FEAT_VMX_ENTRY_CTLS] = 4250 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4251 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4252 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4253 .features[FEAT_VMX_EPT_VPID_CAPS] = 4254 MSR_VMX_EPT_EXECONLY | 4255 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4256 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4257 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4258 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4259 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4260 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4261 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4262 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4263 .features[FEAT_VMX_EXIT_CTLS] = 4264 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4265 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4266 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4267 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4268 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4269 .features[FEAT_VMX_MISC] = 4270 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4271 MSR_VMX_MISC_VMWRITE_VMEXIT, 4272 .features[FEAT_VMX_PINBASED_CTLS] = 4273 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4274 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4275 VMX_PIN_BASED_POSTED_INTR, 4276 .features[FEAT_VMX_PROCBASED_CTLS] = 4277 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4278 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4279 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4280 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4281 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4282 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4283 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4284 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4285 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4286 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4287 VMX_CPU_BASED_PAUSE_EXITING | 4288 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4289 .features[FEAT_VMX_SECONDARY_CTLS] = 4290 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4291 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4292 VMX_SECONDARY_EXEC_RDTSCP | 4293 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4294 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4295 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4296 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4297 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4298 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4299 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4300 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4301 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4302 VMX_SECONDARY_EXEC_XSAVES, 4303 .features[FEAT_VMX_VMFUNC] = 4304 MSR_VMX_VMFUNC_EPT_SWITCHING, 4305 .xlevel = 0x80000008, 4306 .model_id = "Intel Xeon Processor (GraniteRapids)", 4307 .versions = (X86CPUVersionDefinition[]) { 4308 { .version = 1 }, 4309 { /* end of list */ }, 4310 }, 4311 }, 4312 { 4313 .name = "SierraForest", 4314 .level = 0x23, 4315 .vendor = CPUID_VENDOR_INTEL, 4316 .family = 6, 4317 .model = 175, 4318 .stepping = 0, 4319 /* 4320 * please keep the ascending order so that we can have a clear view of 4321 * bit position of each feature. 4322 */ 4323 .features[FEAT_1_EDX] = 4324 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4325 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4326 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4327 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4328 CPUID_SSE | CPUID_SSE2, 4329 .features[FEAT_1_ECX] = 4330 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4331 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4332 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4333 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4334 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4335 .features[FEAT_8000_0001_EDX] = 4336 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4337 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4338 .features[FEAT_8000_0001_ECX] = 4339 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4340 .features[FEAT_8000_0008_EBX] = 4341 CPUID_8000_0008_EBX_WBNOINVD, 4342 .features[FEAT_7_0_EBX] = 4343 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4344 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4345 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4346 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4347 CPUID_7_0_EBX_SHA_NI, 4348 .features[FEAT_7_0_ECX] = 4349 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4350 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4351 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4352 .features[FEAT_7_0_EDX] = 4353 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4354 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4355 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4356 .features[FEAT_ARCH_CAPABILITIES] = 4357 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4358 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4359 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4360 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4361 MSR_ARCH_CAP_PBRSB_NO, 4362 .features[FEAT_XSAVE] = 4363 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4364 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4365 .features[FEAT_6_EAX] = 4366 CPUID_6_EAX_ARAT, 4367 .features[FEAT_7_1_EAX] = 4368 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4369 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4370 .features[FEAT_7_1_EDX] = 4371 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4372 .features[FEAT_7_2_EDX] = 4373 CPUID_7_2_EDX_MCDT_NO, 4374 .features[FEAT_VMX_BASIC] = 4375 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4376 .features[FEAT_VMX_ENTRY_CTLS] = 4377 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4378 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4379 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4380 .features[FEAT_VMX_EPT_VPID_CAPS] = 4381 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4382 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4383 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4384 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4385 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4386 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4387 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4388 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4389 .features[FEAT_VMX_EXIT_CTLS] = 4390 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4391 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4392 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4393 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4394 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4395 .features[FEAT_VMX_MISC] = 4396 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4397 MSR_VMX_MISC_VMWRITE_VMEXIT, 4398 .features[FEAT_VMX_PINBASED_CTLS] = 4399 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4400 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4401 VMX_PIN_BASED_POSTED_INTR, 4402 .features[FEAT_VMX_PROCBASED_CTLS] = 4403 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4404 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4405 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4406 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4407 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4408 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4409 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4410 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4411 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4412 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4413 VMX_CPU_BASED_PAUSE_EXITING | 4414 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4415 .features[FEAT_VMX_SECONDARY_CTLS] = 4416 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4417 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4418 VMX_SECONDARY_EXEC_RDTSCP | 4419 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4420 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4421 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4422 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4423 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4424 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4425 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4426 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4427 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4428 VMX_SECONDARY_EXEC_XSAVES, 4429 .features[FEAT_VMX_VMFUNC] = 4430 MSR_VMX_VMFUNC_EPT_SWITCHING, 4431 .xlevel = 0x80000008, 4432 .model_id = "Intel Xeon Processor (SierraForest)", 4433 .versions = (X86CPUVersionDefinition[]) { 4434 { .version = 1 }, 4435 { /* end of list */ }, 4436 }, 4437 }, 4438 { 4439 .name = "Denverton", 4440 .level = 21, 4441 .vendor = CPUID_VENDOR_INTEL, 4442 .family = 6, 4443 .model = 95, 4444 .stepping = 1, 4445 .features[FEAT_1_EDX] = 4446 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4447 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4448 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4449 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4450 CPUID_SSE | CPUID_SSE2, 4451 .features[FEAT_1_ECX] = 4452 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4453 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4454 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4455 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4456 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4457 .features[FEAT_8000_0001_EDX] = 4458 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4459 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4460 .features[FEAT_8000_0001_ECX] = 4461 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4462 .features[FEAT_7_0_EBX] = 4463 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4464 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4465 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4466 .features[FEAT_7_0_EDX] = 4467 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4468 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4469 /* XSAVES is added in version 3 */ 4470 .features[FEAT_XSAVE] = 4471 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4472 .features[FEAT_6_EAX] = 4473 CPUID_6_EAX_ARAT, 4474 .features[FEAT_ARCH_CAPABILITIES] = 4475 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4476 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4477 MSR_VMX_BASIC_TRUE_CTLS, 4478 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4479 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4480 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4481 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4482 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4483 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4484 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4485 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4486 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4487 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4488 .features[FEAT_VMX_EXIT_CTLS] = 4489 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4490 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4491 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4492 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4493 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4494 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4495 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4496 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4497 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4498 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4499 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4500 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4501 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4502 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4503 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4504 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4505 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4506 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4507 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4508 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4509 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4510 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4511 .features[FEAT_VMX_SECONDARY_CTLS] = 4512 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4513 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4514 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4515 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4516 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4517 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4518 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4519 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4520 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4521 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4522 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4523 .xlevel = 0x80000008, 4524 .model_id = "Intel Atom Processor (Denverton)", 4525 .versions = (X86CPUVersionDefinition[]) { 4526 { .version = 1 }, 4527 { 4528 .version = 2, 4529 .note = "no MPX, no MONITOR", 4530 .props = (PropValue[]) { 4531 { "monitor", "off" }, 4532 { "mpx", "off" }, 4533 { /* end of list */ }, 4534 }, 4535 }, 4536 { 4537 .version = 3, 4538 .note = "XSAVES, no MPX, no MONITOR", 4539 .props = (PropValue[]) { 4540 { "xsaves", "on" }, 4541 { "vmx-xsaves", "on" }, 4542 { /* end of list */ }, 4543 }, 4544 }, 4545 { /* end of list */ }, 4546 }, 4547 }, 4548 { 4549 .name = "Snowridge", 4550 .level = 27, 4551 .vendor = CPUID_VENDOR_INTEL, 4552 .family = 6, 4553 .model = 134, 4554 .stepping = 1, 4555 .features[FEAT_1_EDX] = 4556 /* missing: CPUID_PN CPUID_IA64 */ 4557 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4558 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4559 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4560 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4561 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4562 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4563 CPUID_MMX | 4564 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4565 .features[FEAT_1_ECX] = 4566 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4567 CPUID_EXT_SSSE3 | 4568 CPUID_EXT_CX16 | 4569 CPUID_EXT_SSE41 | 4570 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4571 CPUID_EXT_POPCNT | 4572 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4573 CPUID_EXT_RDRAND, 4574 .features[FEAT_8000_0001_EDX] = 4575 CPUID_EXT2_SYSCALL | 4576 CPUID_EXT2_NX | 4577 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4578 CPUID_EXT2_LM, 4579 .features[FEAT_8000_0001_ECX] = 4580 CPUID_EXT3_LAHF_LM | 4581 CPUID_EXT3_3DNOWPREFETCH, 4582 .features[FEAT_7_0_EBX] = 4583 CPUID_7_0_EBX_FSGSBASE | 4584 CPUID_7_0_EBX_SMEP | 4585 CPUID_7_0_EBX_ERMS | 4586 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4587 CPUID_7_0_EBX_RDSEED | 4588 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4589 CPUID_7_0_EBX_CLWB | 4590 CPUID_7_0_EBX_SHA_NI, 4591 .features[FEAT_7_0_ECX] = 4592 CPUID_7_0_ECX_UMIP | 4593 /* missing bit 5 */ 4594 CPUID_7_0_ECX_GFNI | 4595 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4596 CPUID_7_0_ECX_MOVDIR64B, 4597 .features[FEAT_7_0_EDX] = 4598 CPUID_7_0_EDX_SPEC_CTRL | 4599 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4600 CPUID_7_0_EDX_CORE_CAPABILITY, 4601 .features[FEAT_CORE_CAPABILITY] = 4602 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4603 /* XSAVES is added in version 3 */ 4604 .features[FEAT_XSAVE] = 4605 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4606 CPUID_XSAVE_XGETBV1, 4607 .features[FEAT_6_EAX] = 4608 CPUID_6_EAX_ARAT, 4609 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4610 MSR_VMX_BASIC_TRUE_CTLS, 4611 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4612 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4613 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4614 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4615 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4616 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4617 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4618 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4619 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4620 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4621 .features[FEAT_VMX_EXIT_CTLS] = 4622 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4623 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4624 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4625 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4626 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4627 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4628 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4629 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4630 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4631 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4632 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4633 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4634 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4635 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4636 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4637 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4638 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4639 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4640 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4641 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4642 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4643 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4644 .features[FEAT_VMX_SECONDARY_CTLS] = 4645 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4646 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4647 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4648 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4649 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4650 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4651 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4652 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4653 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4654 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4655 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4656 .xlevel = 0x80000008, 4657 .model_id = "Intel Atom Processor (SnowRidge)", 4658 .versions = (X86CPUVersionDefinition[]) { 4659 { .version = 1 }, 4660 { 4661 .version = 2, 4662 .props = (PropValue[]) { 4663 { "mpx", "off" }, 4664 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4665 { /* end of list */ }, 4666 }, 4667 }, 4668 { 4669 .version = 3, 4670 .note = "XSAVES, no MPX", 4671 .props = (PropValue[]) { 4672 { "xsaves", "on" }, 4673 { "vmx-xsaves", "on" }, 4674 { /* end of list */ }, 4675 }, 4676 }, 4677 { 4678 .version = 4, 4679 .note = "no split lock detect, no core-capability", 4680 .props = (PropValue[]) { 4681 { "split-lock-detect", "off" }, 4682 { "core-capability", "off" }, 4683 { /* end of list */ }, 4684 }, 4685 }, 4686 { /* end of list */ }, 4687 }, 4688 }, 4689 { 4690 .name = "KnightsMill", 4691 .level = 0xd, 4692 .vendor = CPUID_VENDOR_INTEL, 4693 .family = 6, 4694 .model = 133, 4695 .stepping = 0, 4696 .features[FEAT_1_EDX] = 4697 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4698 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4699 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4700 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4701 CPUID_PSE | CPUID_DE | CPUID_FP87, 4702 .features[FEAT_1_ECX] = 4703 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4704 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4705 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4706 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4707 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4708 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4709 .features[FEAT_8000_0001_EDX] = 4710 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4711 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4712 .features[FEAT_8000_0001_ECX] = 4713 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4714 .features[FEAT_7_0_EBX] = 4715 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4716 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4717 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4718 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4719 CPUID_7_0_EBX_AVX512ER, 4720 .features[FEAT_7_0_ECX] = 4721 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4722 .features[FEAT_7_0_EDX] = 4723 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4724 .features[FEAT_XSAVE] = 4725 CPUID_XSAVE_XSAVEOPT, 4726 .features[FEAT_6_EAX] = 4727 CPUID_6_EAX_ARAT, 4728 .xlevel = 0x80000008, 4729 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4730 }, 4731 { 4732 .name = "Opteron_G1", 4733 .level = 5, 4734 .vendor = CPUID_VENDOR_AMD, 4735 .family = 15, 4736 .model = 6, 4737 .stepping = 1, 4738 .features[FEAT_1_EDX] = 4739 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4740 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4741 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4742 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4743 CPUID_DE | CPUID_FP87, 4744 .features[FEAT_1_ECX] = 4745 CPUID_EXT_SSE3, 4746 .features[FEAT_8000_0001_EDX] = 4747 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4748 .xlevel = 0x80000008, 4749 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4750 }, 4751 { 4752 .name = "Opteron_G2", 4753 .level = 5, 4754 .vendor = CPUID_VENDOR_AMD, 4755 .family = 15, 4756 .model = 6, 4757 .stepping = 1, 4758 .features[FEAT_1_EDX] = 4759 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4760 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4761 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4762 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4763 CPUID_DE | CPUID_FP87, 4764 .features[FEAT_1_ECX] = 4765 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4766 .features[FEAT_8000_0001_EDX] = 4767 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4768 .features[FEAT_8000_0001_ECX] = 4769 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4770 .xlevel = 0x80000008, 4771 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4772 }, 4773 { 4774 .name = "Opteron_G3", 4775 .level = 5, 4776 .vendor = CPUID_VENDOR_AMD, 4777 .family = 16, 4778 .model = 2, 4779 .stepping = 3, 4780 .features[FEAT_1_EDX] = 4781 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4782 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4783 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4784 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4785 CPUID_DE | CPUID_FP87, 4786 .features[FEAT_1_ECX] = 4787 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4788 CPUID_EXT_SSE3, 4789 .features[FEAT_8000_0001_EDX] = 4790 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4791 CPUID_EXT2_RDTSCP, 4792 .features[FEAT_8000_0001_ECX] = 4793 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4794 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4795 .xlevel = 0x80000008, 4796 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4797 }, 4798 { 4799 .name = "Opteron_G4", 4800 .level = 0xd, 4801 .vendor = CPUID_VENDOR_AMD, 4802 .family = 21, 4803 .model = 1, 4804 .stepping = 2, 4805 .features[FEAT_1_EDX] = 4806 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4807 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4808 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4809 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4810 CPUID_DE | CPUID_FP87, 4811 .features[FEAT_1_ECX] = 4812 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4813 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4814 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4815 CPUID_EXT_SSE3, 4816 .features[FEAT_8000_0001_EDX] = 4817 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4818 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4819 .features[FEAT_8000_0001_ECX] = 4820 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4821 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4822 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4823 CPUID_EXT3_LAHF_LM, 4824 .features[FEAT_SVM] = 4825 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4826 /* no xsaveopt! */ 4827 .xlevel = 0x8000001A, 4828 .model_id = "AMD Opteron 62xx class CPU", 4829 }, 4830 { 4831 .name = "Opteron_G5", 4832 .level = 0xd, 4833 .vendor = CPUID_VENDOR_AMD, 4834 .family = 21, 4835 .model = 2, 4836 .stepping = 0, 4837 .features[FEAT_1_EDX] = 4838 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4839 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4840 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4841 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4842 CPUID_DE | CPUID_FP87, 4843 .features[FEAT_1_ECX] = 4844 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4845 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4846 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4847 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4848 .features[FEAT_8000_0001_EDX] = 4849 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4850 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4851 .features[FEAT_8000_0001_ECX] = 4852 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4853 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4854 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4855 CPUID_EXT3_LAHF_LM, 4856 .features[FEAT_SVM] = 4857 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4858 /* no xsaveopt! */ 4859 .xlevel = 0x8000001A, 4860 .model_id = "AMD Opteron 63xx class CPU", 4861 }, 4862 { 4863 .name = "EPYC", 4864 .level = 0xd, 4865 .vendor = CPUID_VENDOR_AMD, 4866 .family = 23, 4867 .model = 1, 4868 .stepping = 2, 4869 .features[FEAT_1_EDX] = 4870 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4871 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4872 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4873 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4874 CPUID_VME | CPUID_FP87, 4875 .features[FEAT_1_ECX] = 4876 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4877 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4878 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4879 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4880 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4881 .features[FEAT_8000_0001_EDX] = 4882 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4883 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4884 CPUID_EXT2_SYSCALL, 4885 .features[FEAT_8000_0001_ECX] = 4886 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4887 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4888 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4889 CPUID_EXT3_TOPOEXT, 4890 .features[FEAT_7_0_EBX] = 4891 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4892 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4893 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4894 CPUID_7_0_EBX_SHA_NI, 4895 .features[FEAT_XSAVE] = 4896 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4897 CPUID_XSAVE_XGETBV1, 4898 .features[FEAT_6_EAX] = 4899 CPUID_6_EAX_ARAT, 4900 .features[FEAT_SVM] = 4901 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4902 .xlevel = 0x8000001E, 4903 .model_id = "AMD EPYC Processor", 4904 .cache_info = &epyc_cache_info, 4905 .versions = (X86CPUVersionDefinition[]) { 4906 { .version = 1 }, 4907 { 4908 .version = 2, 4909 .alias = "EPYC-IBPB", 4910 .props = (PropValue[]) { 4911 { "ibpb", "on" }, 4912 { "model-id", 4913 "AMD EPYC Processor (with IBPB)" }, 4914 { /* end of list */ } 4915 } 4916 }, 4917 { 4918 .version = 3, 4919 .props = (PropValue[]) { 4920 { "ibpb", "on" }, 4921 { "perfctr-core", "on" }, 4922 { "clzero", "on" }, 4923 { "xsaveerptr", "on" }, 4924 { "xsaves", "on" }, 4925 { "model-id", 4926 "AMD EPYC Processor" }, 4927 { /* end of list */ } 4928 } 4929 }, 4930 { 4931 .version = 4, 4932 .props = (PropValue[]) { 4933 { "model-id", 4934 "AMD EPYC-v4 Processor" }, 4935 { /* end of list */ } 4936 }, 4937 .cache_info = &epyc_v4_cache_info 4938 }, 4939 { /* end of list */ } 4940 } 4941 }, 4942 { 4943 .name = "Dhyana", 4944 .level = 0xd, 4945 .vendor = CPUID_VENDOR_HYGON, 4946 .family = 24, 4947 .model = 0, 4948 .stepping = 1, 4949 .features[FEAT_1_EDX] = 4950 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4951 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4952 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4953 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4954 CPUID_VME | CPUID_FP87, 4955 .features[FEAT_1_ECX] = 4956 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4957 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4958 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4959 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4960 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4961 .features[FEAT_8000_0001_EDX] = 4962 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4963 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4964 CPUID_EXT2_SYSCALL, 4965 .features[FEAT_8000_0001_ECX] = 4966 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4967 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4968 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4969 CPUID_EXT3_TOPOEXT, 4970 .features[FEAT_8000_0008_EBX] = 4971 CPUID_8000_0008_EBX_IBPB, 4972 .features[FEAT_7_0_EBX] = 4973 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4974 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4975 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4976 /* XSAVES is added in version 2 */ 4977 .features[FEAT_XSAVE] = 4978 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4979 CPUID_XSAVE_XGETBV1, 4980 .features[FEAT_6_EAX] = 4981 CPUID_6_EAX_ARAT, 4982 .features[FEAT_SVM] = 4983 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4984 .xlevel = 0x8000001E, 4985 .model_id = "Hygon Dhyana Processor", 4986 .cache_info = &epyc_cache_info, 4987 .versions = (X86CPUVersionDefinition[]) { 4988 { .version = 1 }, 4989 { .version = 2, 4990 .note = "XSAVES", 4991 .props = (PropValue[]) { 4992 { "xsaves", "on" }, 4993 { /* end of list */ } 4994 }, 4995 }, 4996 { /* end of list */ } 4997 } 4998 }, 4999 { 5000 .name = "EPYC-Rome", 5001 .level = 0xd, 5002 .vendor = CPUID_VENDOR_AMD, 5003 .family = 23, 5004 .model = 49, 5005 .stepping = 0, 5006 .features[FEAT_1_EDX] = 5007 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5008 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5009 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5010 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5011 CPUID_VME | CPUID_FP87, 5012 .features[FEAT_1_ECX] = 5013 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5014 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5015 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5016 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5017 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5018 .features[FEAT_8000_0001_EDX] = 5019 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5020 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5021 CPUID_EXT2_SYSCALL, 5022 .features[FEAT_8000_0001_ECX] = 5023 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5024 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5025 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5026 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5027 .features[FEAT_8000_0008_EBX] = 5028 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5029 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5030 CPUID_8000_0008_EBX_STIBP, 5031 .features[FEAT_7_0_EBX] = 5032 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5033 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5034 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5035 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5036 .features[FEAT_7_0_ECX] = 5037 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5038 .features[FEAT_XSAVE] = 5039 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5040 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5041 .features[FEAT_6_EAX] = 5042 CPUID_6_EAX_ARAT, 5043 .features[FEAT_SVM] = 5044 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5045 .xlevel = 0x8000001E, 5046 .model_id = "AMD EPYC-Rome Processor", 5047 .cache_info = &epyc_rome_cache_info, 5048 .versions = (X86CPUVersionDefinition[]) { 5049 { .version = 1 }, 5050 { 5051 .version = 2, 5052 .props = (PropValue[]) { 5053 { "ibrs", "on" }, 5054 { "amd-ssbd", "on" }, 5055 { /* end of list */ } 5056 } 5057 }, 5058 { 5059 .version = 3, 5060 .props = (PropValue[]) { 5061 { "model-id", 5062 "AMD EPYC-Rome-v3 Processor" }, 5063 { /* end of list */ } 5064 }, 5065 .cache_info = &epyc_rome_v3_cache_info 5066 }, 5067 { 5068 .version = 4, 5069 .props = (PropValue[]) { 5070 /* Erratum 1386 */ 5071 { "model-id", 5072 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5073 { "xsaves", "off" }, 5074 { /* end of list */ } 5075 }, 5076 }, 5077 { /* end of list */ } 5078 } 5079 }, 5080 { 5081 .name = "EPYC-Milan", 5082 .level = 0xd, 5083 .vendor = CPUID_VENDOR_AMD, 5084 .family = 25, 5085 .model = 1, 5086 .stepping = 1, 5087 .features[FEAT_1_EDX] = 5088 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5089 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5090 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5091 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5092 CPUID_VME | CPUID_FP87, 5093 .features[FEAT_1_ECX] = 5094 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5095 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5096 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5097 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5098 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5099 CPUID_EXT_PCID, 5100 .features[FEAT_8000_0001_EDX] = 5101 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5102 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5103 CPUID_EXT2_SYSCALL, 5104 .features[FEAT_8000_0001_ECX] = 5105 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5106 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5107 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5108 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5109 .features[FEAT_8000_0008_EBX] = 5110 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5111 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5112 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5113 CPUID_8000_0008_EBX_AMD_SSBD, 5114 .features[FEAT_7_0_EBX] = 5115 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5116 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5117 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5118 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5119 CPUID_7_0_EBX_INVPCID, 5120 .features[FEAT_7_0_ECX] = 5121 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5122 .features[FEAT_7_0_EDX] = 5123 CPUID_7_0_EDX_FSRM, 5124 .features[FEAT_XSAVE] = 5125 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5126 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5127 .features[FEAT_6_EAX] = 5128 CPUID_6_EAX_ARAT, 5129 .features[FEAT_SVM] = 5130 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5131 .xlevel = 0x8000001E, 5132 .model_id = "AMD EPYC-Milan Processor", 5133 .cache_info = &epyc_milan_cache_info, 5134 .versions = (X86CPUVersionDefinition[]) { 5135 { .version = 1 }, 5136 { 5137 .version = 2, 5138 .props = (PropValue[]) { 5139 { "model-id", 5140 "AMD EPYC-Milan-v2 Processor" }, 5141 { "vaes", "on" }, 5142 { "vpclmulqdq", "on" }, 5143 { "stibp-always-on", "on" }, 5144 { "amd-psfd", "on" }, 5145 { "no-nested-data-bp", "on" }, 5146 { "lfence-always-serializing", "on" }, 5147 { "null-sel-clr-base", "on" }, 5148 { /* end of list */ } 5149 }, 5150 .cache_info = &epyc_milan_v2_cache_info 5151 }, 5152 { /* end of list */ } 5153 } 5154 }, 5155 { 5156 .name = "EPYC-Genoa", 5157 .level = 0xd, 5158 .vendor = CPUID_VENDOR_AMD, 5159 .family = 25, 5160 .model = 17, 5161 .stepping = 0, 5162 .features[FEAT_1_EDX] = 5163 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5164 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5165 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5166 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5167 CPUID_VME | CPUID_FP87, 5168 .features[FEAT_1_ECX] = 5169 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5170 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5171 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5172 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5173 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5174 CPUID_EXT_SSE3, 5175 .features[FEAT_8000_0001_EDX] = 5176 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5177 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5178 CPUID_EXT2_SYSCALL, 5179 .features[FEAT_8000_0001_ECX] = 5180 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5181 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5182 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5183 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5184 .features[FEAT_8000_0008_EBX] = 5185 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5186 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5187 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5188 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5189 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5190 .features[FEAT_8000_0021_EAX] = 5191 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 5192 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5193 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5194 CPUID_8000_0021_EAX_AUTO_IBRS, 5195 .features[FEAT_7_0_EBX] = 5196 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5197 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5198 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5199 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5200 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5201 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5202 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5203 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5204 .features[FEAT_7_0_ECX] = 5205 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5206 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5207 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5208 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5209 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5210 CPUID_7_0_ECX_RDPID, 5211 .features[FEAT_7_0_EDX] = 5212 CPUID_7_0_EDX_FSRM, 5213 .features[FEAT_7_1_EAX] = 5214 CPUID_7_1_EAX_AVX512_BF16, 5215 .features[FEAT_XSAVE] = 5216 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5217 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5218 .features[FEAT_6_EAX] = 5219 CPUID_6_EAX_ARAT, 5220 .features[FEAT_SVM] = 5221 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5222 CPUID_SVM_SVME_ADDR_CHK, 5223 .xlevel = 0x80000022, 5224 .model_id = "AMD EPYC-Genoa Processor", 5225 .cache_info = &epyc_genoa_cache_info, 5226 }, 5227 }; 5228 5229 /* 5230 * We resolve CPU model aliases using -v1 when using "-machine 5231 * none", but this is just for compatibility while libvirt isn't 5232 * adapted to resolve CPU model versions before creating VMs. 5233 * See "Runnability guarantee of CPU models" at 5234 * docs/about/deprecated.rst. 5235 */ 5236 X86CPUVersion default_cpu_version = 1; 5237 5238 void x86_cpu_set_default_version(X86CPUVersion version) 5239 { 5240 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5241 assert(version != CPU_VERSION_AUTO); 5242 default_cpu_version = version; 5243 } 5244 5245 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5246 { 5247 int v = 0; 5248 const X86CPUVersionDefinition *vdef = 5249 x86_cpu_def_get_versions(model->cpudef); 5250 while (vdef->version) { 5251 v = vdef->version; 5252 vdef++; 5253 } 5254 return v; 5255 } 5256 5257 /* Return the actual version being used for a specific CPU model */ 5258 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5259 { 5260 X86CPUVersion v = model->version; 5261 if (v == CPU_VERSION_AUTO) { 5262 v = default_cpu_version; 5263 } 5264 if (v == CPU_VERSION_LATEST) { 5265 return x86_cpu_model_last_version(model); 5266 } 5267 return v; 5268 } 5269 5270 static Property max_x86_cpu_properties[] = { 5271 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5272 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5273 DEFINE_PROP_END_OF_LIST() 5274 }; 5275 5276 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5277 { 5278 Object *obj = OBJECT(dev); 5279 5280 if (!object_property_get_int(obj, "family", &error_abort)) { 5281 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5282 object_property_set_int(obj, "family", 15, &error_abort); 5283 object_property_set_int(obj, "model", 107, &error_abort); 5284 object_property_set_int(obj, "stepping", 1, &error_abort); 5285 } else { 5286 object_property_set_int(obj, "family", 6, &error_abort); 5287 object_property_set_int(obj, "model", 6, &error_abort); 5288 object_property_set_int(obj, "stepping", 3, &error_abort); 5289 } 5290 } 5291 5292 x86_cpu_realizefn(dev, errp); 5293 } 5294 5295 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5296 { 5297 DeviceClass *dc = DEVICE_CLASS(oc); 5298 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5299 5300 xcc->ordering = 9; 5301 5302 xcc->model_description = 5303 "Enables all features supported by the accelerator in the current host"; 5304 5305 device_class_set_props(dc, max_x86_cpu_properties); 5306 dc->realize = max_x86_cpu_realize; 5307 } 5308 5309 static void max_x86_cpu_initfn(Object *obj) 5310 { 5311 X86CPU *cpu = X86_CPU(obj); 5312 5313 /* We can't fill the features array here because we don't know yet if 5314 * "migratable" is true or false. 5315 */ 5316 cpu->max_features = true; 5317 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5318 5319 /* 5320 * these defaults are used for TCG and all other accelerators 5321 * besides KVM and HVF, which overwrite these values 5322 */ 5323 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5324 &error_abort); 5325 object_property_set_str(OBJECT(cpu), "model-id", 5326 "QEMU TCG CPU version " QEMU_HW_VERSION, 5327 &error_abort); 5328 } 5329 5330 static const TypeInfo max_x86_cpu_type_info = { 5331 .name = X86_CPU_TYPE_NAME("max"), 5332 .parent = TYPE_X86_CPU, 5333 .instance_init = max_x86_cpu_initfn, 5334 .class_init = max_x86_cpu_class_init, 5335 }; 5336 5337 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5338 { 5339 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5340 5341 switch (f->type) { 5342 case CPUID_FEATURE_WORD: 5343 { 5344 const char *reg = get_register_name_32(f->cpuid.reg); 5345 assert(reg); 5346 return g_strdup_printf("CPUID.%02XH:%s", 5347 f->cpuid.eax, reg); 5348 } 5349 case MSR_FEATURE_WORD: 5350 return g_strdup_printf("MSR(%02XH)", 5351 f->msr.index); 5352 } 5353 5354 return NULL; 5355 } 5356 5357 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5358 { 5359 FeatureWord w; 5360 5361 for (w = 0; w < FEATURE_WORDS; w++) { 5362 if (cpu->filtered_features[w]) { 5363 return true; 5364 } 5365 } 5366 5367 return false; 5368 } 5369 5370 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5371 const char *verbose_prefix) 5372 { 5373 CPUX86State *env = &cpu->env; 5374 FeatureWordInfo *f = &feature_word_info[w]; 5375 int i; 5376 5377 if (!cpu->force_features) { 5378 env->features[w] &= ~mask; 5379 } 5380 cpu->filtered_features[w] |= mask; 5381 5382 if (!verbose_prefix) { 5383 return; 5384 } 5385 5386 for (i = 0; i < 64; ++i) { 5387 if ((1ULL << i) & mask) { 5388 g_autofree char *feat_word_str = feature_word_description(f, i); 5389 warn_report("%s: %s%s%s [bit %d]", 5390 verbose_prefix, 5391 feat_word_str, 5392 f->feat_names[i] ? "." : "", 5393 f->feat_names[i] ? f->feat_names[i] : "", i); 5394 } 5395 } 5396 } 5397 5398 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5399 const char *name, void *opaque, 5400 Error **errp) 5401 { 5402 X86CPU *cpu = X86_CPU(obj); 5403 CPUX86State *env = &cpu->env; 5404 int64_t value; 5405 5406 value = (env->cpuid_version >> 8) & 0xf; 5407 if (value == 0xf) { 5408 value += (env->cpuid_version >> 20) & 0xff; 5409 } 5410 visit_type_int(v, name, &value, errp); 5411 } 5412 5413 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5414 const char *name, void *opaque, 5415 Error **errp) 5416 { 5417 X86CPU *cpu = X86_CPU(obj); 5418 CPUX86State *env = &cpu->env; 5419 const int64_t min = 0; 5420 const int64_t max = 0xff + 0xf; 5421 int64_t value; 5422 5423 if (!visit_type_int(v, name, &value, errp)) { 5424 return; 5425 } 5426 if (value < min || value > max) { 5427 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5428 name ? name : "null", value, min, max); 5429 return; 5430 } 5431 5432 env->cpuid_version &= ~0xff00f00; 5433 if (value > 0x0f) { 5434 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5435 } else { 5436 env->cpuid_version |= value << 8; 5437 } 5438 } 5439 5440 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5441 const char *name, void *opaque, 5442 Error **errp) 5443 { 5444 X86CPU *cpu = X86_CPU(obj); 5445 CPUX86State *env = &cpu->env; 5446 int64_t value; 5447 5448 value = (env->cpuid_version >> 4) & 0xf; 5449 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5450 visit_type_int(v, name, &value, errp); 5451 } 5452 5453 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5454 const char *name, void *opaque, 5455 Error **errp) 5456 { 5457 X86CPU *cpu = X86_CPU(obj); 5458 CPUX86State *env = &cpu->env; 5459 const int64_t min = 0; 5460 const int64_t max = 0xff; 5461 int64_t value; 5462 5463 if (!visit_type_int(v, name, &value, errp)) { 5464 return; 5465 } 5466 if (value < min || value > max) { 5467 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5468 name ? name : "null", value, min, max); 5469 return; 5470 } 5471 5472 env->cpuid_version &= ~0xf00f0; 5473 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5474 } 5475 5476 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5477 const char *name, void *opaque, 5478 Error **errp) 5479 { 5480 X86CPU *cpu = X86_CPU(obj); 5481 CPUX86State *env = &cpu->env; 5482 int64_t value; 5483 5484 value = env->cpuid_version & 0xf; 5485 visit_type_int(v, name, &value, errp); 5486 } 5487 5488 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5489 const char *name, void *opaque, 5490 Error **errp) 5491 { 5492 X86CPU *cpu = X86_CPU(obj); 5493 CPUX86State *env = &cpu->env; 5494 const int64_t min = 0; 5495 const int64_t max = 0xf; 5496 int64_t value; 5497 5498 if (!visit_type_int(v, name, &value, errp)) { 5499 return; 5500 } 5501 if (value < min || value > max) { 5502 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5503 name ? name : "null", value, min, max); 5504 return; 5505 } 5506 5507 env->cpuid_version &= ~0xf; 5508 env->cpuid_version |= value & 0xf; 5509 } 5510 5511 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5512 { 5513 X86CPU *cpu = X86_CPU(obj); 5514 CPUX86State *env = &cpu->env; 5515 char *value; 5516 5517 value = g_malloc(CPUID_VENDOR_SZ + 1); 5518 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5519 env->cpuid_vendor3); 5520 return value; 5521 } 5522 5523 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5524 Error **errp) 5525 { 5526 X86CPU *cpu = X86_CPU(obj); 5527 CPUX86State *env = &cpu->env; 5528 int i; 5529 5530 if (strlen(value) != CPUID_VENDOR_SZ) { 5531 error_setg(errp, "value of property 'vendor' must consist of" 5532 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5533 return; 5534 } 5535 5536 env->cpuid_vendor1 = 0; 5537 env->cpuid_vendor2 = 0; 5538 env->cpuid_vendor3 = 0; 5539 for (i = 0; i < 4; i++) { 5540 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5541 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5542 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5543 } 5544 } 5545 5546 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5547 { 5548 X86CPU *cpu = X86_CPU(obj); 5549 CPUX86State *env = &cpu->env; 5550 char *value; 5551 int i; 5552 5553 value = g_malloc(48 + 1); 5554 for (i = 0; i < 48; i++) { 5555 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5556 } 5557 value[48] = '\0'; 5558 return value; 5559 } 5560 5561 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5562 Error **errp) 5563 { 5564 X86CPU *cpu = X86_CPU(obj); 5565 CPUX86State *env = &cpu->env; 5566 int c, len, i; 5567 5568 if (model_id == NULL) { 5569 model_id = ""; 5570 } 5571 len = strlen(model_id); 5572 memset(env->cpuid_model, 0, 48); 5573 for (i = 0; i < 48; i++) { 5574 if (i >= len) { 5575 c = '\0'; 5576 } else { 5577 c = (uint8_t)model_id[i]; 5578 } 5579 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5580 } 5581 } 5582 5583 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5584 void *opaque, Error **errp) 5585 { 5586 X86CPU *cpu = X86_CPU(obj); 5587 int64_t value; 5588 5589 value = cpu->env.tsc_khz * 1000; 5590 visit_type_int(v, name, &value, errp); 5591 } 5592 5593 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5594 void *opaque, Error **errp) 5595 { 5596 X86CPU *cpu = X86_CPU(obj); 5597 const int64_t min = 0; 5598 const int64_t max = INT64_MAX; 5599 int64_t value; 5600 5601 if (!visit_type_int(v, name, &value, errp)) { 5602 return; 5603 } 5604 if (value < min || value > max) { 5605 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5606 name ? name : "null", value, min, max); 5607 return; 5608 } 5609 5610 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5611 } 5612 5613 /* Generic getter for "feature-words" and "filtered-features" properties */ 5614 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5615 const char *name, void *opaque, 5616 Error **errp) 5617 { 5618 uint64_t *array = (uint64_t *)opaque; 5619 FeatureWord w; 5620 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5621 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5622 X86CPUFeatureWordInfoList *list = NULL; 5623 5624 for (w = 0; w < FEATURE_WORDS; w++) { 5625 FeatureWordInfo *wi = &feature_word_info[w]; 5626 /* 5627 * We didn't have MSR features when "feature-words" was 5628 * introduced. Therefore skipped other type entries. 5629 */ 5630 if (wi->type != CPUID_FEATURE_WORD) { 5631 continue; 5632 } 5633 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5634 qwi->cpuid_input_eax = wi->cpuid.eax; 5635 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5636 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5637 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5638 qwi->features = array[w]; 5639 5640 /* List will be in reverse order, but order shouldn't matter */ 5641 list_entries[w].next = list; 5642 list_entries[w].value = &word_infos[w]; 5643 list = &list_entries[w]; 5644 } 5645 5646 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5647 } 5648 5649 /* Convert all '_' in a feature string option name to '-', to make feature 5650 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5651 */ 5652 static inline void feat2prop(char *s) 5653 { 5654 while ((s = strchr(s, '_'))) { 5655 *s = '-'; 5656 } 5657 } 5658 5659 /* Return the feature property name for a feature flag bit */ 5660 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5661 { 5662 const char *name; 5663 /* XSAVE components are automatically enabled by other features, 5664 * so return the original feature name instead 5665 */ 5666 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5667 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5668 5669 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5670 x86_ext_save_areas[comp].bits) { 5671 w = x86_ext_save_areas[comp].feature; 5672 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5673 } 5674 } 5675 5676 assert(bitnr < 64); 5677 assert(w < FEATURE_WORDS); 5678 name = feature_word_info[w].feat_names[bitnr]; 5679 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5680 return name; 5681 } 5682 5683 /* Compatibility hack to maintain legacy +-feat semantic, 5684 * where +-feat overwrites any feature set by 5685 * feat=on|feat even if the later is parsed after +-feat 5686 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5687 */ 5688 static GList *plus_features, *minus_features; 5689 5690 static gint compare_string(gconstpointer a, gconstpointer b) 5691 { 5692 return g_strcmp0(a, b); 5693 } 5694 5695 /* Parse "+feature,-feature,feature=foo" CPU feature string 5696 */ 5697 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5698 Error **errp) 5699 { 5700 char *featurestr; /* Single 'key=value" string being parsed */ 5701 static bool cpu_globals_initialized; 5702 bool ambiguous = false; 5703 5704 if (cpu_globals_initialized) { 5705 return; 5706 } 5707 cpu_globals_initialized = true; 5708 5709 if (!features) { 5710 return; 5711 } 5712 5713 for (featurestr = strtok(features, ","); 5714 featurestr; 5715 featurestr = strtok(NULL, ",")) { 5716 const char *name; 5717 const char *val = NULL; 5718 char *eq = NULL; 5719 char num[32]; 5720 GlobalProperty *prop; 5721 5722 /* Compatibility syntax: */ 5723 if (featurestr[0] == '+') { 5724 plus_features = g_list_append(plus_features, 5725 g_strdup(featurestr + 1)); 5726 continue; 5727 } else if (featurestr[0] == '-') { 5728 minus_features = g_list_append(minus_features, 5729 g_strdup(featurestr + 1)); 5730 continue; 5731 } 5732 5733 eq = strchr(featurestr, '='); 5734 if (eq) { 5735 *eq++ = 0; 5736 val = eq; 5737 } else { 5738 val = "on"; 5739 } 5740 5741 feat2prop(featurestr); 5742 name = featurestr; 5743 5744 if (g_list_find_custom(plus_features, name, compare_string)) { 5745 warn_report("Ambiguous CPU model string. " 5746 "Don't mix both \"+%s\" and \"%s=%s\"", 5747 name, name, val); 5748 ambiguous = true; 5749 } 5750 if (g_list_find_custom(minus_features, name, compare_string)) { 5751 warn_report("Ambiguous CPU model string. " 5752 "Don't mix both \"-%s\" and \"%s=%s\"", 5753 name, name, val); 5754 ambiguous = true; 5755 } 5756 5757 /* Special case: */ 5758 if (!strcmp(name, "tsc-freq")) { 5759 int ret; 5760 uint64_t tsc_freq; 5761 5762 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5763 if (ret < 0 || tsc_freq > INT64_MAX) { 5764 error_setg(errp, "bad numerical value %s", val); 5765 return; 5766 } 5767 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5768 val = num; 5769 name = "tsc-frequency"; 5770 } 5771 5772 prop = g_new0(typeof(*prop), 1); 5773 prop->driver = typename; 5774 prop->property = g_strdup(name); 5775 prop->value = g_strdup(val); 5776 qdev_prop_register_global(prop); 5777 } 5778 5779 if (ambiguous) { 5780 warn_report("Compatibility of ambiguous CPU model " 5781 "strings won't be kept on future QEMU versions"); 5782 } 5783 } 5784 5785 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5786 5787 /* Build a list with the name of all features on a feature word array */ 5788 static void x86_cpu_list_feature_names(FeatureWordArray features, 5789 strList **list) 5790 { 5791 strList **tail = list; 5792 FeatureWord w; 5793 5794 for (w = 0; w < FEATURE_WORDS; w++) { 5795 uint64_t filtered = features[w]; 5796 int i; 5797 for (i = 0; i < 64; i++) { 5798 if (filtered & (1ULL << i)) { 5799 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5800 } 5801 } 5802 } 5803 } 5804 5805 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5806 const char *name, void *opaque, 5807 Error **errp) 5808 { 5809 X86CPU *xc = X86_CPU(obj); 5810 strList *result = NULL; 5811 5812 x86_cpu_list_feature_names(xc->filtered_features, &result); 5813 visit_type_strList(v, "unavailable-features", &result, errp); 5814 } 5815 5816 /* Print all cpuid feature names in featureset 5817 */ 5818 static void listflags(GList *features) 5819 { 5820 size_t len = 0; 5821 GList *tmp; 5822 5823 for (tmp = features; tmp; tmp = tmp->next) { 5824 const char *name = tmp->data; 5825 if ((len + strlen(name) + 1) >= 75) { 5826 qemu_printf("\n"); 5827 len = 0; 5828 } 5829 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5830 len += strlen(name) + 1; 5831 } 5832 qemu_printf("\n"); 5833 } 5834 5835 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5836 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5837 { 5838 ObjectClass *class_a = (ObjectClass *)a; 5839 ObjectClass *class_b = (ObjectClass *)b; 5840 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5841 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5842 int ret; 5843 5844 if (cc_a->ordering != cc_b->ordering) { 5845 ret = cc_a->ordering - cc_b->ordering; 5846 } else { 5847 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5848 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5849 ret = strcmp(name_a, name_b); 5850 } 5851 return ret; 5852 } 5853 5854 static GSList *get_sorted_cpu_model_list(void) 5855 { 5856 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5857 list = g_slist_sort(list, x86_cpu_list_compare); 5858 return list; 5859 } 5860 5861 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5862 { 5863 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5864 char *r = object_property_get_str(obj, "model-id", &error_abort); 5865 object_unref(obj); 5866 return r; 5867 } 5868 5869 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5870 { 5871 X86CPUVersion version; 5872 5873 if (!cc->model || !cc->model->is_alias) { 5874 return NULL; 5875 } 5876 version = x86_cpu_model_resolve_version(cc->model); 5877 if (version <= 0) { 5878 return NULL; 5879 } 5880 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5881 } 5882 5883 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5884 { 5885 ObjectClass *oc = data; 5886 X86CPUClass *cc = X86_CPU_CLASS(oc); 5887 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5888 g_autofree char *desc = g_strdup(cc->model_description); 5889 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5890 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5891 5892 if (!desc && alias_of) { 5893 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5894 desc = g_strdup("(alias configured by machine type)"); 5895 } else { 5896 desc = g_strdup_printf("(alias of %s)", alias_of); 5897 } 5898 } 5899 if (!desc && cc->model && cc->model->note) { 5900 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5901 } 5902 if (!desc) { 5903 desc = g_strdup_printf("%s", model_id); 5904 } 5905 5906 if (cc->model && cc->model->cpudef->deprecation_note) { 5907 g_autofree char *olddesc = desc; 5908 desc = g_strdup_printf("%s (deprecated)", olddesc); 5909 } 5910 5911 qemu_printf(" %-20s %s\n", name, desc); 5912 } 5913 5914 /* list available CPU models and flags */ 5915 void x86_cpu_list(void) 5916 { 5917 int i, j; 5918 GSList *list; 5919 GList *names = NULL; 5920 5921 qemu_printf("Available CPUs:\n"); 5922 list = get_sorted_cpu_model_list(); 5923 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5924 g_slist_free(list); 5925 5926 names = NULL; 5927 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5928 FeatureWordInfo *fw = &feature_word_info[i]; 5929 for (j = 0; j < 64; j++) { 5930 if (fw->feat_names[j]) { 5931 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5932 } 5933 } 5934 } 5935 5936 names = g_list_sort(names, (GCompareFunc)strcmp); 5937 5938 qemu_printf("\nRecognized CPUID flags:\n"); 5939 listflags(names); 5940 qemu_printf("\n"); 5941 g_list_free(names); 5942 } 5943 5944 #ifndef CONFIG_USER_ONLY 5945 5946 /* Check for missing features that may prevent the CPU class from 5947 * running using the current machine and accelerator. 5948 */ 5949 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5950 strList **list) 5951 { 5952 strList **tail = list; 5953 X86CPU *xc; 5954 Error *err = NULL; 5955 5956 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5957 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5958 return; 5959 } 5960 5961 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5962 5963 x86_cpu_expand_features(xc, &err); 5964 if (err) { 5965 /* Errors at x86_cpu_expand_features should never happen, 5966 * but in case it does, just report the model as not 5967 * runnable at all using the "type" property. 5968 */ 5969 QAPI_LIST_APPEND(tail, g_strdup("type")); 5970 error_free(err); 5971 } 5972 5973 x86_cpu_filter_features(xc, false); 5974 5975 x86_cpu_list_feature_names(xc->filtered_features, tail); 5976 5977 object_unref(OBJECT(xc)); 5978 } 5979 5980 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5981 { 5982 ObjectClass *oc = data; 5983 X86CPUClass *cc = X86_CPU_CLASS(oc); 5984 CpuDefinitionInfoList **cpu_list = user_data; 5985 CpuDefinitionInfo *info; 5986 5987 info = g_malloc0(sizeof(*info)); 5988 info->name = x86_cpu_class_get_model_name(cc); 5989 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5990 info->has_unavailable_features = true; 5991 info->q_typename = g_strdup(object_class_get_name(oc)); 5992 info->migration_safe = cc->migration_safe; 5993 info->has_migration_safe = true; 5994 info->q_static = cc->static_model; 5995 if (cc->model && cc->model->cpudef->deprecation_note) { 5996 info->deprecated = true; 5997 } else { 5998 info->deprecated = false; 5999 } 6000 /* 6001 * Old machine types won't report aliases, so that alias translation 6002 * doesn't break compatibility with previous QEMU versions. 6003 */ 6004 if (default_cpu_version != CPU_VERSION_LEGACY) { 6005 info->alias_of = x86_cpu_class_get_alias_of(cc); 6006 } 6007 6008 QAPI_LIST_PREPEND(*cpu_list, info); 6009 } 6010 6011 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6012 { 6013 CpuDefinitionInfoList *cpu_list = NULL; 6014 GSList *list = get_sorted_cpu_model_list(); 6015 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6016 g_slist_free(list); 6017 return cpu_list; 6018 } 6019 6020 #endif /* !CONFIG_USER_ONLY */ 6021 6022 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 6023 bool migratable_only) 6024 { 6025 FeatureWordInfo *wi = &feature_word_info[w]; 6026 uint64_t r = 0; 6027 6028 if (kvm_enabled()) { 6029 switch (wi->type) { 6030 case CPUID_FEATURE_WORD: 6031 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6032 wi->cpuid.ecx, 6033 wi->cpuid.reg); 6034 break; 6035 case MSR_FEATURE_WORD: 6036 r = kvm_arch_get_supported_msr_feature(kvm_state, 6037 wi->msr.index); 6038 break; 6039 } 6040 } else if (hvf_enabled()) { 6041 if (wi->type != CPUID_FEATURE_WORD) { 6042 return 0; 6043 } 6044 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6045 wi->cpuid.ecx, 6046 wi->cpuid.reg); 6047 } else if (tcg_enabled()) { 6048 r = wi->tcg_features; 6049 } else { 6050 return ~0; 6051 } 6052 #ifndef TARGET_X86_64 6053 if (w == FEAT_8000_0001_EDX) { 6054 /* 6055 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6056 * way for userspace to get out of its 32-bit jail, we can leave 6057 * the LM bit set. 6058 */ 6059 uint32_t unavail = tcg_enabled() 6060 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6061 : CPUID_EXT2_LM; 6062 r &= ~unavail; 6063 } 6064 #endif 6065 if (migratable_only) { 6066 r &= x86_cpu_get_migratable_flags(w); 6067 } 6068 return r; 6069 } 6070 6071 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6072 uint32_t *eax, uint32_t *ebx, 6073 uint32_t *ecx, uint32_t *edx) 6074 { 6075 if (kvm_enabled()) { 6076 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6077 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6078 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6079 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6080 } else if (hvf_enabled()) { 6081 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6082 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6083 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6084 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6085 } else { 6086 *eax = 0; 6087 *ebx = 0; 6088 *ecx = 0; 6089 *edx = 0; 6090 } 6091 } 6092 6093 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6094 uint32_t *eax, uint32_t *ebx, 6095 uint32_t *ecx, uint32_t *edx) 6096 { 6097 uint32_t level, unused; 6098 6099 /* Only return valid host leaves. */ 6100 switch (func) { 6101 case 2: 6102 case 4: 6103 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6104 break; 6105 case 0x80000005: 6106 case 0x80000006: 6107 case 0x8000001d: 6108 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6109 break; 6110 default: 6111 return; 6112 } 6113 6114 if (func > level) { 6115 *eax = 0; 6116 *ebx = 0; 6117 *ecx = 0; 6118 *edx = 0; 6119 } else { 6120 host_cpuid(func, index, eax, ebx, ecx, edx); 6121 } 6122 } 6123 6124 /* 6125 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6126 */ 6127 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6128 { 6129 PropValue *pv; 6130 for (pv = props; pv->prop; pv++) { 6131 if (!pv->value) { 6132 continue; 6133 } 6134 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6135 &error_abort); 6136 } 6137 } 6138 6139 /* 6140 * Apply properties for the CPU model version specified in model. 6141 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6142 */ 6143 6144 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6145 { 6146 const X86CPUVersionDefinition *vdef; 6147 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6148 6149 if (version == CPU_VERSION_LEGACY) { 6150 return; 6151 } 6152 6153 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6154 PropValue *p; 6155 6156 for (p = vdef->props; p && p->prop; p++) { 6157 object_property_parse(OBJECT(cpu), p->prop, p->value, 6158 &error_abort); 6159 } 6160 6161 if (vdef->version == version) { 6162 break; 6163 } 6164 } 6165 6166 /* 6167 * If we reached the end of the list, version number was invalid 6168 */ 6169 assert(vdef->version == version); 6170 } 6171 6172 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6173 X86CPUModel *model) 6174 { 6175 const X86CPUVersionDefinition *vdef; 6176 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6177 const CPUCaches *cache_info = model->cpudef->cache_info; 6178 6179 if (version == CPU_VERSION_LEGACY) { 6180 return cache_info; 6181 } 6182 6183 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6184 if (vdef->cache_info) { 6185 cache_info = vdef->cache_info; 6186 } 6187 6188 if (vdef->version == version) { 6189 break; 6190 } 6191 } 6192 6193 assert(vdef->version == version); 6194 return cache_info; 6195 } 6196 6197 /* 6198 * Load data from X86CPUDefinition into a X86CPU object. 6199 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6200 */ 6201 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6202 { 6203 const X86CPUDefinition *def = model->cpudef; 6204 CPUX86State *env = &cpu->env; 6205 FeatureWord w; 6206 6207 /*NOTE: any property set by this function should be returned by 6208 * x86_cpu_static_props(), so static expansion of 6209 * query-cpu-model-expansion is always complete. 6210 */ 6211 6212 /* CPU models only set _minimum_ values for level/xlevel: */ 6213 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6214 &error_abort); 6215 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6216 &error_abort); 6217 6218 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6219 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6220 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6221 &error_abort); 6222 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6223 &error_abort); 6224 for (w = 0; w < FEATURE_WORDS; w++) { 6225 env->features[w] = def->features[w]; 6226 } 6227 6228 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6229 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6230 6231 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6232 6233 /* sysenter isn't supported in compatibility mode on AMD, 6234 * syscall isn't supported in compatibility mode on Intel. 6235 * Normally we advertise the actual CPU vendor, but you can 6236 * override this using the 'vendor' property if you want to use 6237 * KVM's sysenter/syscall emulation in compatibility mode and 6238 * when doing cross vendor migration 6239 */ 6240 6241 /* 6242 * vendor property is set here but then overloaded with the 6243 * host cpu vendor for KVM and HVF. 6244 */ 6245 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6246 6247 x86_cpu_apply_version_props(cpu, model); 6248 6249 /* 6250 * Properties in versioned CPU model are not user specified features. 6251 * We can simply clear env->user_features here since it will be filled later 6252 * in x86_cpu_expand_features() based on plus_features and minus_features. 6253 */ 6254 memset(&env->user_features, 0, sizeof(env->user_features)); 6255 } 6256 6257 static const gchar *x86_gdb_arch_name(CPUState *cs) 6258 { 6259 #ifdef TARGET_X86_64 6260 return "i386:x86-64"; 6261 #else 6262 return "i386"; 6263 #endif 6264 } 6265 6266 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6267 { 6268 X86CPUModel *model = data; 6269 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6270 CPUClass *cc = CPU_CLASS(oc); 6271 6272 xcc->model = model; 6273 xcc->migration_safe = true; 6274 cc->deprecation_note = model->cpudef->deprecation_note; 6275 } 6276 6277 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6278 { 6279 g_autofree char *typename = x86_cpu_type_name(name); 6280 TypeInfo ti = { 6281 .name = typename, 6282 .parent = TYPE_X86_CPU, 6283 .class_init = x86_cpu_cpudef_class_init, 6284 .class_data = model, 6285 }; 6286 6287 type_register(&ti); 6288 } 6289 6290 6291 /* 6292 * register builtin_x86_defs; 6293 * "max", "base" and subclasses ("host") are not registered here. 6294 * See x86_cpu_register_types for all model registrations. 6295 */ 6296 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6297 { 6298 X86CPUModel *m; 6299 const X86CPUVersionDefinition *vdef; 6300 6301 /* AMD aliases are handled at runtime based on CPUID vendor, so 6302 * they shouldn't be set on the CPU model table. 6303 */ 6304 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6305 /* catch mistakes instead of silently truncating model_id when too long */ 6306 assert(def->model_id && strlen(def->model_id) <= 48); 6307 6308 /* Unversioned model: */ 6309 m = g_new0(X86CPUModel, 1); 6310 m->cpudef = def; 6311 m->version = CPU_VERSION_AUTO; 6312 m->is_alias = true; 6313 x86_register_cpu_model_type(def->name, m); 6314 6315 /* Versioned models: */ 6316 6317 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6318 g_autofree char *name = 6319 x86_cpu_versioned_model_name(def, vdef->version); 6320 6321 m = g_new0(X86CPUModel, 1); 6322 m->cpudef = def; 6323 m->version = vdef->version; 6324 m->note = vdef->note; 6325 x86_register_cpu_model_type(name, m); 6326 6327 if (vdef->alias) { 6328 X86CPUModel *am = g_new0(X86CPUModel, 1); 6329 am->cpudef = def; 6330 am->version = vdef->version; 6331 am->is_alias = true; 6332 x86_register_cpu_model_type(vdef->alias, am); 6333 } 6334 } 6335 6336 } 6337 6338 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6339 { 6340 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6341 return 57; /* 57 bits virtual */ 6342 } else { 6343 return 48; /* 48 bits virtual */ 6344 } 6345 } 6346 6347 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6348 uint32_t *eax, uint32_t *ebx, 6349 uint32_t *ecx, uint32_t *edx) 6350 { 6351 X86CPU *cpu = env_archcpu(env); 6352 CPUState *cs = env_cpu(env); 6353 uint32_t limit; 6354 uint32_t signature[3]; 6355 X86CPUTopoInfo topo_info; 6356 uint32_t cores_per_pkg; 6357 uint32_t threads_per_pkg; 6358 6359 topo_info.dies_per_pkg = env->nr_dies; 6360 topo_info.modules_per_die = env->nr_modules; 6361 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6362 topo_info.threads_per_core = cs->nr_threads; 6363 6364 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6365 topo_info.dies_per_pkg; 6366 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6367 6368 /* Calculate & apply limits for different index ranges */ 6369 if (index >= 0xC0000000) { 6370 limit = env->cpuid_xlevel2; 6371 } else if (index >= 0x80000000) { 6372 limit = env->cpuid_xlevel; 6373 } else if (index >= 0x40000000) { 6374 limit = 0x40000001; 6375 } else { 6376 limit = env->cpuid_level; 6377 } 6378 6379 if (index > limit) { 6380 /* Intel documentation states that invalid EAX input will 6381 * return the same information as EAX=cpuid_level 6382 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6383 */ 6384 index = env->cpuid_level; 6385 } 6386 6387 switch(index) { 6388 case 0: 6389 *eax = env->cpuid_level; 6390 *ebx = env->cpuid_vendor1; 6391 *edx = env->cpuid_vendor2; 6392 *ecx = env->cpuid_vendor3; 6393 break; 6394 case 1: 6395 *eax = env->cpuid_version; 6396 *ebx = (cpu->apic_id << 24) | 6397 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6398 *ecx = env->features[FEAT_1_ECX]; 6399 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6400 *ecx |= CPUID_EXT_OSXSAVE; 6401 } 6402 *edx = env->features[FEAT_1_EDX]; 6403 if (threads_per_pkg > 1) { 6404 *ebx |= threads_per_pkg << 16; 6405 *edx |= CPUID_HT; 6406 } 6407 if (!cpu->enable_pmu) { 6408 *ecx &= ~CPUID_EXT_PDCM; 6409 } 6410 break; 6411 case 2: 6412 /* cache info: needed for Pentium Pro compatibility */ 6413 if (cpu->cache_info_passthrough) { 6414 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6415 break; 6416 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6417 *eax = *ebx = *ecx = *edx = 0; 6418 break; 6419 } 6420 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6421 *ebx = 0; 6422 if (!cpu->enable_l3_cache) { 6423 *ecx = 0; 6424 } else { 6425 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6426 } 6427 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6428 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6429 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6430 break; 6431 case 4: 6432 /* cache info: needed for Core compatibility */ 6433 if (cpu->cache_info_passthrough) { 6434 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6435 /* 6436 * QEMU has its own number of cores/logical cpus, 6437 * set 24..14, 31..26 bit to configured values 6438 */ 6439 if (*eax & 31) { 6440 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6441 6442 if (cores_per_pkg > 1) { 6443 *eax &= ~0xFC000000; 6444 *eax |= max_core_ids_in_package(&topo_info) << 26; 6445 } 6446 if (host_vcpus_per_cache > threads_per_pkg) { 6447 *eax &= ~0x3FFC000; 6448 6449 /* Share the cache at package level. */ 6450 *eax |= max_thread_ids_for_cache(&topo_info, 6451 CPU_TOPO_LEVEL_PACKAGE) << 14; 6452 } 6453 } 6454 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6455 *eax = *ebx = *ecx = *edx = 0; 6456 } else { 6457 *eax = 0; 6458 6459 switch (count) { 6460 case 0: /* L1 dcache info */ 6461 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6462 &topo_info, 6463 eax, ebx, ecx, edx); 6464 if (!cpu->l1_cache_per_core) { 6465 *eax &= ~MAKE_64BIT_MASK(14, 12); 6466 } 6467 break; 6468 case 1: /* L1 icache info */ 6469 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6470 &topo_info, 6471 eax, ebx, ecx, edx); 6472 if (!cpu->l1_cache_per_core) { 6473 *eax &= ~MAKE_64BIT_MASK(14, 12); 6474 } 6475 break; 6476 case 2: /* L2 cache info */ 6477 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6478 &topo_info, 6479 eax, ebx, ecx, edx); 6480 break; 6481 case 3: /* L3 cache info */ 6482 if (cpu->enable_l3_cache) { 6483 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6484 &topo_info, 6485 eax, ebx, ecx, edx); 6486 break; 6487 } 6488 /* fall through */ 6489 default: /* end of info */ 6490 *eax = *ebx = *ecx = *edx = 0; 6491 break; 6492 } 6493 } 6494 break; 6495 case 5: 6496 /* MONITOR/MWAIT Leaf */ 6497 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6498 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6499 *ecx = cpu->mwait.ecx; /* flags */ 6500 *edx = cpu->mwait.edx; /* mwait substates */ 6501 break; 6502 case 6: 6503 /* Thermal and Power Leaf */ 6504 *eax = env->features[FEAT_6_EAX]; 6505 *ebx = 0; 6506 *ecx = 0; 6507 *edx = 0; 6508 break; 6509 case 7: 6510 /* Structured Extended Feature Flags Enumeration Leaf */ 6511 if (count == 0) { 6512 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused; 6513 6514 /* Maximum ECX value for sub-leaves */ 6515 *eax = env->cpuid_level_func7; 6516 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6517 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6518 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6519 *ecx |= CPUID_7_0_ECX_OSPKE; 6520 } 6521 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6522 6523 /* 6524 * SGX cannot be emulated in software. If hardware does not 6525 * support enabling SGX and/or SGX flexible launch control, 6526 * then we need to update the VM's CPUID values accordingly. 6527 */ 6528 x86_cpu_get_supported_cpuid(0x7, 0, 6529 &eax_0_unused, &ebx_0, 6530 &ecx_0, &edx_0_unused); 6531 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) { 6532 *ebx &= ~CPUID_7_0_EBX_SGX; 6533 } 6534 6535 if ((*ecx & CPUID_7_0_ECX_SGX_LC) 6536 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) { 6537 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 6538 } 6539 } else if (count == 1) { 6540 *eax = env->features[FEAT_7_1_EAX]; 6541 *edx = env->features[FEAT_7_1_EDX]; 6542 *ebx = 0; 6543 *ecx = 0; 6544 } else if (count == 2) { 6545 *edx = env->features[FEAT_7_2_EDX]; 6546 *eax = 0; 6547 *ebx = 0; 6548 *ecx = 0; 6549 } else { 6550 *eax = 0; 6551 *ebx = 0; 6552 *ecx = 0; 6553 *edx = 0; 6554 } 6555 break; 6556 case 9: 6557 /* Direct Cache Access Information Leaf */ 6558 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6559 *ebx = 0; 6560 *ecx = 0; 6561 *edx = 0; 6562 break; 6563 case 0xA: 6564 /* Architectural Performance Monitoring Leaf */ 6565 if (cpu->enable_pmu) { 6566 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6567 } else { 6568 *eax = 0; 6569 *ebx = 0; 6570 *ecx = 0; 6571 *edx = 0; 6572 } 6573 break; 6574 case 0xB: 6575 /* Extended Topology Enumeration Leaf */ 6576 if (!cpu->enable_cpuid_0xb) { 6577 *eax = *ebx = *ecx = *edx = 0; 6578 break; 6579 } 6580 6581 *ecx = count & 0xff; 6582 *edx = cpu->apic_id; 6583 6584 switch (count) { 6585 case 0: 6586 *eax = apicid_core_offset(&topo_info); 6587 *ebx = topo_info.threads_per_core; 6588 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6589 break; 6590 case 1: 6591 *eax = apicid_pkg_offset(&topo_info); 6592 *ebx = threads_per_pkg; 6593 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6594 break; 6595 default: 6596 *eax = 0; 6597 *ebx = 0; 6598 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6599 } 6600 6601 assert(!(*eax & ~0x1f)); 6602 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6603 break; 6604 case 0x1C: 6605 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6606 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6607 *edx = 0; 6608 } 6609 break; 6610 case 0x1F: 6611 /* V2 Extended Topology Enumeration Leaf */ 6612 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6613 *eax = *ebx = *ecx = *edx = 0; 6614 break; 6615 } 6616 6617 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6618 break; 6619 case 0xD: { 6620 /* Processor Extended State */ 6621 *eax = 0; 6622 *ebx = 0; 6623 *ecx = 0; 6624 *edx = 0; 6625 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6626 break; 6627 } 6628 6629 if (count == 0) { 6630 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6631 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6632 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6633 /* 6634 * The initial value of xcr0 and ebx == 0, On host without kvm 6635 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6636 * even through guest update xcr0, this will crash some legacy guest 6637 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6638 */ 6639 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6640 } else if (count == 1) { 6641 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6642 x86_cpu_xsave_xss_components(cpu); 6643 6644 *eax = env->features[FEAT_XSAVE]; 6645 *ebx = xsave_area_size(xstate, true); 6646 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6647 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6648 if (kvm_enabled() && cpu->enable_pmu && 6649 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6650 (*eax & CPUID_XSAVE_XSAVES)) { 6651 *ecx |= XSTATE_ARCH_LBR_MASK; 6652 } else { 6653 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6654 } 6655 } else if (count == 0xf && cpu->enable_pmu 6656 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6657 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6658 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6659 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6660 6661 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6662 *eax = esa->size; 6663 *ebx = esa->offset; 6664 *ecx = esa->ecx & 6665 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6666 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6667 *eax = esa->size; 6668 *ebx = 0; 6669 *ecx = 1; 6670 } 6671 } 6672 break; 6673 } 6674 case 0x12: 6675 #ifndef CONFIG_USER_ONLY 6676 if (!kvm_enabled() || 6677 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6678 *eax = *ebx = *ecx = *edx = 0; 6679 break; 6680 } 6681 6682 /* 6683 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6684 * the EPC properties, e.g. confidentiality and integrity, from the 6685 * host's first EPC section, i.e. assume there is one EPC section or 6686 * that all EPC sections have the same security properties. 6687 */ 6688 if (count > 1) { 6689 uint64_t epc_addr, epc_size; 6690 6691 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6692 *eax = *ebx = *ecx = *edx = 0; 6693 break; 6694 } 6695 host_cpuid(index, 2, eax, ebx, ecx, edx); 6696 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6697 *ebx = (uint32_t)(epc_addr >> 32); 6698 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6699 *edx = (uint32_t)(epc_size >> 32); 6700 break; 6701 } 6702 6703 /* 6704 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6705 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6706 * supports. Features can be further restricted by userspace, but not 6707 * made more permissive. 6708 */ 6709 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6710 6711 if (count == 0) { 6712 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6713 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6714 } else { 6715 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6716 *ebx &= 0; /* ebx reserve */ 6717 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6718 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6719 6720 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6721 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6722 6723 /* Access to PROVISIONKEY requires additional credentials. */ 6724 if ((*eax & (1U << 4)) && 6725 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6726 *eax &= ~(1U << 4); 6727 } 6728 } 6729 #endif 6730 break; 6731 case 0x14: { 6732 /* Intel Processor Trace Enumeration */ 6733 *eax = 0; 6734 *ebx = 0; 6735 *ecx = 0; 6736 *edx = 0; 6737 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6738 !kvm_enabled()) { 6739 break; 6740 } 6741 6742 /* 6743 * If these are changed, they should stay in sync with 6744 * x86_cpu_filter_features(). 6745 */ 6746 if (count == 0) { 6747 *eax = INTEL_PT_MAX_SUBLEAF; 6748 *ebx = INTEL_PT_MINIMAL_EBX; 6749 *ecx = INTEL_PT_MINIMAL_ECX; 6750 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6751 *ecx |= CPUID_14_0_ECX_LIP; 6752 } 6753 } else if (count == 1) { 6754 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6755 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6756 } 6757 break; 6758 } 6759 case 0x1D: { 6760 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6761 *eax = 0; 6762 *ebx = 0; 6763 *ecx = 0; 6764 *edx = 0; 6765 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6766 break; 6767 } 6768 6769 if (count == 0) { 6770 /* Highest numbered palette subleaf */ 6771 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6772 } else if (count == 1) { 6773 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6774 (INTEL_AMX_BYTES_PER_TILE << 16); 6775 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6776 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6777 } 6778 break; 6779 } 6780 case 0x1E: { 6781 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6782 *eax = 0; 6783 *ebx = 0; 6784 *ecx = 0; 6785 *edx = 0; 6786 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6787 break; 6788 } 6789 6790 if (count == 0) { 6791 /* Highest numbered palette subleaf */ 6792 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6793 } 6794 break; 6795 } 6796 case 0x40000000: 6797 /* 6798 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6799 * set here, but we restrict to TCG none the less. 6800 */ 6801 if (tcg_enabled() && cpu->expose_tcg) { 6802 memcpy(signature, "TCGTCGTCGTCG", 12); 6803 *eax = 0x40000001; 6804 *ebx = signature[0]; 6805 *ecx = signature[1]; 6806 *edx = signature[2]; 6807 } else { 6808 *eax = 0; 6809 *ebx = 0; 6810 *ecx = 0; 6811 *edx = 0; 6812 } 6813 break; 6814 case 0x40000001: 6815 *eax = 0; 6816 *ebx = 0; 6817 *ecx = 0; 6818 *edx = 0; 6819 break; 6820 case 0x80000000: 6821 *eax = env->cpuid_xlevel; 6822 *ebx = env->cpuid_vendor1; 6823 *edx = env->cpuid_vendor2; 6824 *ecx = env->cpuid_vendor3; 6825 break; 6826 case 0x80000001: 6827 *eax = env->cpuid_version; 6828 *ebx = 0; 6829 *ecx = env->features[FEAT_8000_0001_ECX]; 6830 *edx = env->features[FEAT_8000_0001_EDX]; 6831 6832 /* The Linux kernel checks for the CMPLegacy bit and 6833 * discards multiple thread information if it is set. 6834 * So don't set it here for Intel to make Linux guests happy. 6835 */ 6836 if (threads_per_pkg > 1) { 6837 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6838 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6839 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6840 *ecx |= 1 << 1; /* CmpLegacy bit */ 6841 } 6842 } 6843 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6844 !(env->hflags & HF_LMA_MASK)) { 6845 *edx &= ~CPUID_EXT2_SYSCALL; 6846 } 6847 break; 6848 case 0x80000002: 6849 case 0x80000003: 6850 case 0x80000004: 6851 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6852 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6853 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6854 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6855 break; 6856 case 0x80000005: 6857 /* cache info (L1 cache) */ 6858 if (cpu->cache_info_passthrough) { 6859 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6860 break; 6861 } 6862 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6863 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6864 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6865 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6866 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6867 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6868 break; 6869 case 0x80000006: 6870 /* cache info (L2 cache) */ 6871 if (cpu->cache_info_passthrough) { 6872 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6873 break; 6874 } 6875 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6876 (L2_DTLB_2M_ENTRIES << 16) | 6877 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6878 (L2_ITLB_2M_ENTRIES); 6879 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6880 (L2_DTLB_4K_ENTRIES << 16) | 6881 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6882 (L2_ITLB_4K_ENTRIES); 6883 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6884 cpu->enable_l3_cache ? 6885 env->cache_info_amd.l3_cache : NULL, 6886 ecx, edx); 6887 break; 6888 case 0x80000007: 6889 *eax = 0; 6890 *ebx = 0; 6891 *ecx = 0; 6892 *edx = env->features[FEAT_8000_0007_EDX]; 6893 break; 6894 case 0x80000008: 6895 /* virtual & phys address size in low 2 bytes. */ 6896 *eax = cpu->phys_bits; 6897 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6898 /* 64 bit processor */ 6899 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6900 *eax |= (cpu->guest_phys_bits << 16); 6901 } 6902 *ebx = env->features[FEAT_8000_0008_EBX]; 6903 if (threads_per_pkg > 1) { 6904 /* 6905 * Bits 15:12 is "The number of bits in the initial 6906 * Core::X86::Apic::ApicId[ApicId] value that indicate 6907 * thread ID within a package". 6908 * Bits 7:0 is "The number of threads in the package is NC+1" 6909 */ 6910 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6911 (threads_per_pkg - 1); 6912 } else { 6913 *ecx = 0; 6914 } 6915 *edx = 0; 6916 break; 6917 case 0x8000000A: 6918 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6919 *eax = 0x00000001; /* SVM Revision */ 6920 *ebx = 0x00000010; /* nr of ASIDs */ 6921 *ecx = 0; 6922 *edx = env->features[FEAT_SVM]; /* optional features */ 6923 } else { 6924 *eax = 0; 6925 *ebx = 0; 6926 *ecx = 0; 6927 *edx = 0; 6928 } 6929 break; 6930 case 0x8000001D: 6931 *eax = 0; 6932 if (cpu->cache_info_passthrough) { 6933 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6934 break; 6935 } 6936 switch (count) { 6937 case 0: /* L1 dcache info */ 6938 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6939 &topo_info, eax, ebx, ecx, edx); 6940 break; 6941 case 1: /* L1 icache info */ 6942 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6943 &topo_info, eax, ebx, ecx, edx); 6944 break; 6945 case 2: /* L2 cache info */ 6946 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6947 &topo_info, eax, ebx, ecx, edx); 6948 break; 6949 case 3: /* L3 cache info */ 6950 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6951 &topo_info, eax, ebx, ecx, edx); 6952 break; 6953 default: /* end of info */ 6954 *eax = *ebx = *ecx = *edx = 0; 6955 break; 6956 } 6957 break; 6958 case 0x8000001E: 6959 if (cpu->core_id <= 255) { 6960 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6961 } else { 6962 *eax = 0; 6963 *ebx = 0; 6964 *ecx = 0; 6965 *edx = 0; 6966 } 6967 break; 6968 case 0xC0000000: 6969 *eax = env->cpuid_xlevel2; 6970 *ebx = 0; 6971 *ecx = 0; 6972 *edx = 0; 6973 break; 6974 case 0xC0000001: 6975 /* Support for VIA CPU's CPUID instruction */ 6976 *eax = env->cpuid_version; 6977 *ebx = 0; 6978 *ecx = 0; 6979 *edx = env->features[FEAT_C000_0001_EDX]; 6980 break; 6981 case 0xC0000002: 6982 case 0xC0000003: 6983 case 0xC0000004: 6984 /* Reserved for the future, and now filled with zero */ 6985 *eax = 0; 6986 *ebx = 0; 6987 *ecx = 0; 6988 *edx = 0; 6989 break; 6990 case 0x8000001F: 6991 *eax = *ebx = *ecx = *edx = 0; 6992 if (sev_enabled()) { 6993 *eax = 0x2; 6994 *eax |= sev_es_enabled() ? 0x8 : 0; 6995 *eax |= sev_snp_enabled() ? 0x10 : 0; 6996 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6997 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6998 } 6999 break; 7000 case 0x80000021: 7001 *eax = env->features[FEAT_8000_0021_EAX]; 7002 *ebx = *ecx = *edx = 0; 7003 break; 7004 default: 7005 /* reserved values: zero */ 7006 *eax = 0; 7007 *ebx = 0; 7008 *ecx = 0; 7009 *edx = 0; 7010 break; 7011 } 7012 } 7013 7014 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7015 { 7016 #ifndef CONFIG_USER_ONLY 7017 /* Those default values are defined in Skylake HW */ 7018 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7019 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7020 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7021 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7022 #endif 7023 } 7024 7025 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7026 { 7027 CPUState *cs = CPU(obj); 7028 X86CPU *cpu = X86_CPU(cs); 7029 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7030 CPUX86State *env = &cpu->env; 7031 target_ulong cr4; 7032 uint64_t xcr0; 7033 int i; 7034 7035 if (xcc->parent_phases.hold) { 7036 xcc->parent_phases.hold(obj, type); 7037 } 7038 7039 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7040 7041 env->old_exception = -1; 7042 7043 /* init to reset state */ 7044 env->int_ctl = 0; 7045 env->hflags2 |= HF2_GIF_MASK; 7046 env->hflags2 |= HF2_VGIF_MASK; 7047 env->hflags &= ~HF_GUEST_MASK; 7048 7049 cpu_x86_update_cr0(env, 0x60000010); 7050 env->a20_mask = ~0x0; 7051 env->smbase = 0x30000; 7052 env->msr_smi_count = 0; 7053 7054 env->idt.limit = 0xffff; 7055 env->gdt.limit = 0xffff; 7056 env->ldt.limit = 0xffff; 7057 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7058 env->tr.limit = 0xffff; 7059 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7060 7061 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7062 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7063 DESC_R_MASK | DESC_A_MASK); 7064 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7065 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7066 DESC_A_MASK); 7067 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7068 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7069 DESC_A_MASK); 7070 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7071 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7072 DESC_A_MASK); 7073 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7074 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7075 DESC_A_MASK); 7076 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7077 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7078 DESC_A_MASK); 7079 7080 env->eip = 0xfff0; 7081 env->regs[R_EDX] = env->cpuid_version; 7082 7083 env->eflags = 0x2; 7084 7085 /* FPU init */ 7086 for (i = 0; i < 8; i++) { 7087 env->fptags[i] = 1; 7088 } 7089 cpu_set_fpuc(env, 0x37f); 7090 7091 env->mxcsr = 0x1f80; 7092 /* All units are in INIT state. */ 7093 env->xstate_bv = 0; 7094 7095 env->pat = 0x0007040600070406ULL; 7096 7097 if (kvm_enabled()) { 7098 /* 7099 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7100 * a new CPU, use 1 instead to force a reset. 7101 */ 7102 if (env->tsc != 0) { 7103 env->tsc = 1; 7104 } 7105 } else { 7106 env->tsc = 0; 7107 } 7108 7109 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7110 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7111 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7112 } 7113 7114 memset(env->dr, 0, sizeof(env->dr)); 7115 env->dr[6] = DR6_FIXED_1; 7116 env->dr[7] = DR7_FIXED_1; 7117 cpu_breakpoint_remove_all(cs, BP_CPU); 7118 cpu_watchpoint_remove_all(cs, BP_CPU); 7119 7120 cr4 = 0; 7121 xcr0 = XSTATE_FP_MASK; 7122 7123 #ifdef CONFIG_USER_ONLY 7124 /* Enable all the features for user-mode. */ 7125 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7126 xcr0 |= XSTATE_SSE_MASK; 7127 } 7128 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7129 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7130 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7131 continue; 7132 } 7133 if (env->features[esa->feature] & esa->bits) { 7134 xcr0 |= 1ull << i; 7135 } 7136 } 7137 7138 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7139 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7140 } 7141 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7142 cr4 |= CR4_FSGSBASE_MASK; 7143 } 7144 #endif 7145 7146 env->xcr0 = xcr0; 7147 cpu_x86_update_cr4(env, cr4); 7148 7149 /* 7150 * SDM 11.11.5 requires: 7151 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7152 * - IA32_MTRR_PHYSMASKn.V = 0 7153 * All other bits are undefined. For simplification, zero it all. 7154 */ 7155 env->mtrr_deftype = 0; 7156 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7157 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7158 7159 env->interrupt_injected = -1; 7160 env->exception_nr = -1; 7161 env->exception_pending = 0; 7162 env->exception_injected = 0; 7163 env->exception_has_payload = false; 7164 env->exception_payload = 0; 7165 env->nmi_injected = false; 7166 env->triple_fault_pending = false; 7167 #if !defined(CONFIG_USER_ONLY) 7168 /* We hard-wire the BSP to the first CPU. */ 7169 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7170 7171 cs->halted = !cpu_is_bsp(cpu); 7172 7173 if (kvm_enabled()) { 7174 kvm_arch_reset_vcpu(cpu); 7175 } 7176 7177 x86_cpu_set_sgxlepubkeyhash(env); 7178 7179 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7180 7181 #endif 7182 } 7183 7184 void x86_cpu_after_reset(X86CPU *cpu) 7185 { 7186 #ifndef CONFIG_USER_ONLY 7187 if (kvm_enabled()) { 7188 kvm_arch_after_reset_vcpu(cpu); 7189 } 7190 7191 if (cpu->apic_state) { 7192 device_cold_reset(cpu->apic_state); 7193 } 7194 #endif 7195 } 7196 7197 static void mce_init(X86CPU *cpu) 7198 { 7199 CPUX86State *cenv = &cpu->env; 7200 unsigned int bank; 7201 7202 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7203 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7204 (CPUID_MCE | CPUID_MCA)) { 7205 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7206 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7207 cenv->mcg_ctl = ~(uint64_t)0; 7208 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7209 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7210 } 7211 } 7212 } 7213 7214 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7215 { 7216 if (*min < value) { 7217 *min = value; 7218 } 7219 } 7220 7221 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7222 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7223 { 7224 CPUX86State *env = &cpu->env; 7225 FeatureWordInfo *fi = &feature_word_info[w]; 7226 uint32_t eax = fi->cpuid.eax; 7227 uint32_t region = eax & 0xF0000000; 7228 7229 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7230 if (!env->features[w]) { 7231 return; 7232 } 7233 7234 switch (region) { 7235 case 0x00000000: 7236 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7237 break; 7238 case 0x80000000: 7239 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7240 break; 7241 case 0xC0000000: 7242 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7243 break; 7244 } 7245 7246 if (eax == 7) { 7247 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7248 fi->cpuid.ecx); 7249 } 7250 } 7251 7252 /* Calculate XSAVE components based on the configured CPU feature flags */ 7253 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7254 { 7255 CPUX86State *env = &cpu->env; 7256 int i; 7257 uint64_t mask; 7258 static bool request_perm; 7259 7260 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7261 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7262 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7263 env->features[FEAT_XSAVE_XSS_LO] = 0; 7264 env->features[FEAT_XSAVE_XSS_HI] = 0; 7265 return; 7266 } 7267 7268 mask = 0; 7269 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7270 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7271 if (env->features[esa->feature] & esa->bits) { 7272 mask |= (1ULL << i); 7273 } 7274 } 7275 7276 /* Only request permission for first vcpu */ 7277 if (kvm_enabled() && !request_perm) { 7278 kvm_request_xsave_components(cpu, mask); 7279 request_perm = true; 7280 } 7281 7282 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7283 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7284 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7285 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7286 } 7287 7288 /***** Steps involved on loading and filtering CPUID data 7289 * 7290 * When initializing and realizing a CPU object, the steps 7291 * involved in setting up CPUID data are: 7292 * 7293 * 1) Loading CPU model definition (X86CPUDefinition). This is 7294 * implemented by x86_cpu_load_model() and should be completely 7295 * transparent, as it is done automatically by instance_init. 7296 * No code should need to look at X86CPUDefinition structs 7297 * outside instance_init. 7298 * 7299 * 2) CPU expansion. This is done by realize before CPUID 7300 * filtering, and will make sure host/accelerator data is 7301 * loaded for CPU models that depend on host capabilities 7302 * (e.g. "host"). Done by x86_cpu_expand_features(). 7303 * 7304 * 3) CPUID filtering. This initializes extra data related to 7305 * CPUID, and checks if the host supports all capabilities 7306 * required by the CPU. Runnability of a CPU model is 7307 * determined at this step. Done by x86_cpu_filter_features(). 7308 * 7309 * Some operations don't require all steps to be performed. 7310 * More precisely: 7311 * 7312 * - CPU instance creation (instance_init) will run only CPU 7313 * model loading. CPU expansion can't run at instance_init-time 7314 * because host/accelerator data may be not available yet. 7315 * - CPU realization will perform both CPU model expansion and CPUID 7316 * filtering, and return an error in case one of them fails. 7317 * - query-cpu-definitions needs to run all 3 steps. It needs 7318 * to run CPUID filtering, as the 'unavailable-features' 7319 * field is set based on the filtering results. 7320 * - The query-cpu-model-expansion QMP command only needs to run 7321 * CPU model loading and CPU expansion. It should not filter 7322 * any CPUID data based on host capabilities. 7323 */ 7324 7325 /* Expand CPU configuration data, based on configured features 7326 * and host/accelerator capabilities when appropriate. 7327 */ 7328 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7329 { 7330 CPUX86State *env = &cpu->env; 7331 FeatureWord w; 7332 int i; 7333 GList *l; 7334 7335 for (l = plus_features; l; l = l->next) { 7336 const char *prop = l->data; 7337 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7338 return; 7339 } 7340 } 7341 7342 for (l = minus_features; l; l = l->next) { 7343 const char *prop = l->data; 7344 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7345 return; 7346 } 7347 } 7348 7349 /*TODO: Now cpu->max_features doesn't overwrite features 7350 * set using QOM properties, and we can convert 7351 * plus_features & minus_features to global properties 7352 * inside x86_cpu_parse_featurestr() too. 7353 */ 7354 if (cpu->max_features) { 7355 for (w = 0; w < FEATURE_WORDS; w++) { 7356 /* Override only features that weren't set explicitly 7357 * by the user. 7358 */ 7359 env->features[w] |= 7360 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 7361 ~env->user_features[w] & 7362 ~feature_word_info[w].no_autoenable_flags; 7363 } 7364 } 7365 7366 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7367 FeatureDep *d = &feature_dependencies[i]; 7368 if (!(env->features[d->from.index] & d->from.mask)) { 7369 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7370 7371 /* Not an error unless the dependent feature was added explicitly. */ 7372 mark_unavailable_features(cpu, d->to.index, 7373 unavailable_features & env->user_features[d->to.index], 7374 "This feature depends on other features that were not requested"); 7375 7376 env->features[d->to.index] &= ~unavailable_features; 7377 } 7378 } 7379 7380 if (!kvm_enabled() || !cpu->expose_kvm) { 7381 env->features[FEAT_KVM] = 0; 7382 } 7383 7384 x86_cpu_enable_xsave_components(cpu); 7385 7386 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7387 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7388 if (cpu->full_cpuid_auto_level) { 7389 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7390 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7391 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7392 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7393 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7394 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7395 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7396 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7397 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7398 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7399 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7400 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7401 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7402 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7403 7404 /* Intel Processor Trace requires CPUID[0x14] */ 7405 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7406 if (cpu->intel_pt_auto_level) { 7407 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7408 } else if (cpu->env.cpuid_min_level < 0x14) { 7409 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7410 CPUID_7_0_EBX_INTEL_PT, 7411 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7412 } 7413 } 7414 7415 /* 7416 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7417 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7418 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7419 * cpu->vendor_cpuid_only has been unset for compatibility with older 7420 * machine types. 7421 */ 7422 if (x86_has_extended_topo(env->avail_cpu_topo) && 7423 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7424 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7425 } 7426 7427 /* SVM requires CPUID[0x8000000A] */ 7428 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7429 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7430 } 7431 7432 /* SEV requires CPUID[0x8000001F] */ 7433 if (sev_enabled()) { 7434 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7435 } 7436 7437 if (env->features[FEAT_8000_0021_EAX]) { 7438 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7439 } 7440 7441 /* SGX requires CPUID[0x12] for EPC enumeration */ 7442 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7443 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7444 } 7445 } 7446 7447 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7448 if (env->cpuid_level_func7 == UINT32_MAX) { 7449 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7450 } 7451 if (env->cpuid_level == UINT32_MAX) { 7452 env->cpuid_level = env->cpuid_min_level; 7453 } 7454 if (env->cpuid_xlevel == UINT32_MAX) { 7455 env->cpuid_xlevel = env->cpuid_min_xlevel; 7456 } 7457 if (env->cpuid_xlevel2 == UINT32_MAX) { 7458 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7459 } 7460 7461 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7462 return; 7463 } 7464 } 7465 7466 /* 7467 * Finishes initialization of CPUID data, filters CPU feature 7468 * words based on host availability of each feature. 7469 * 7470 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7471 */ 7472 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7473 { 7474 CPUX86State *env = &cpu->env; 7475 FeatureWord w; 7476 const char *prefix = NULL; 7477 7478 if (verbose) { 7479 prefix = accel_uses_host_cpuid() 7480 ? "host doesn't support requested feature" 7481 : "TCG doesn't support requested feature"; 7482 } 7483 7484 for (w = 0; w < FEATURE_WORDS; w++) { 7485 uint64_t host_feat = 7486 x86_cpu_get_supported_feature_word(w, false); 7487 uint64_t requested_features = env->features[w]; 7488 uint64_t unavailable_features = requested_features & ~host_feat; 7489 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7490 } 7491 7492 /* 7493 * Check that KVM actually allows the processor tracing features that 7494 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7495 */ 7496 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7497 kvm_enabled()) { 7498 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7499 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7500 7501 x86_cpu_get_supported_cpuid(0x14, 0, 7502 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7503 x86_cpu_get_supported_cpuid(0x14, 1, 7504 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7505 7506 if (!eax_0 || 7507 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7508 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7509 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7510 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7511 INTEL_PT_ADDR_RANGES_NUM) || 7512 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7513 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7514 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7515 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7516 /* 7517 * Processor Trace capabilities aren't configurable, so if the 7518 * host can't emulate the capabilities we report on 7519 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7520 */ 7521 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7522 } 7523 } 7524 } 7525 7526 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7527 { 7528 size_t len; 7529 7530 /* Hyper-V vendor id */ 7531 if (!cpu->hyperv_vendor) { 7532 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7533 &error_abort); 7534 } 7535 len = strlen(cpu->hyperv_vendor); 7536 if (len > 12) { 7537 warn_report("hv-vendor-id truncated to 12 characters"); 7538 len = 12; 7539 } 7540 memset(cpu->hyperv_vendor_id, 0, 12); 7541 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7542 7543 /* 'Hv#1' interface identification*/ 7544 cpu->hyperv_interface_id[0] = 0x31237648; 7545 cpu->hyperv_interface_id[1] = 0; 7546 cpu->hyperv_interface_id[2] = 0; 7547 cpu->hyperv_interface_id[3] = 0; 7548 7549 /* Hypervisor implementation limits */ 7550 cpu->hyperv_limits[0] = 64; 7551 cpu->hyperv_limits[1] = 0; 7552 cpu->hyperv_limits[2] = 0; 7553 } 7554 7555 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7556 { 7557 CPUState *cs = CPU(dev); 7558 X86CPU *cpu = X86_CPU(dev); 7559 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7560 CPUX86State *env = &cpu->env; 7561 Error *local_err = NULL; 7562 unsigned requested_lbr_fmt; 7563 7564 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7565 /* Use pc-relative instructions in system-mode */ 7566 tcg_cflags_set(cs, CF_PCREL); 7567 #endif 7568 7569 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7570 error_setg(errp, "apic-id property was not initialized properly"); 7571 return; 7572 } 7573 7574 /* 7575 * Process Hyper-V enlightenments. 7576 * Note: this currently has to happen before the expansion of CPU features. 7577 */ 7578 x86_cpu_hyperv_realize(cpu); 7579 7580 x86_cpu_expand_features(cpu, &local_err); 7581 if (local_err) { 7582 goto out; 7583 } 7584 7585 /* 7586 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7587 * with user-provided setting. 7588 */ 7589 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7590 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7591 error_setg(errp, "invalid lbr-fmt"); 7592 return; 7593 } 7594 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7595 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7596 } 7597 7598 /* 7599 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7600 * 3)vPMU LBR format matches that of host setting. 7601 */ 7602 requested_lbr_fmt = 7603 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7604 if (requested_lbr_fmt && kvm_enabled()) { 7605 uint64_t host_perf_cap = 7606 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 7607 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7608 7609 if (!cpu->enable_pmu) { 7610 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7611 return; 7612 } 7613 if (requested_lbr_fmt != host_lbr_fmt) { 7614 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7615 "the host value (0x%x).", 7616 requested_lbr_fmt, host_lbr_fmt); 7617 return; 7618 } 7619 } 7620 7621 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7622 7623 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7624 error_setg(&local_err, 7625 accel_uses_host_cpuid() ? 7626 "Host doesn't support requested features" : 7627 "TCG doesn't support requested features"); 7628 goto out; 7629 } 7630 7631 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7632 * CPUID[1].EDX. 7633 */ 7634 if (IS_AMD_CPU(env)) { 7635 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7636 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7637 & CPUID_EXT2_AMD_ALIASES); 7638 } 7639 7640 x86_cpu_set_sgxlepubkeyhash(env); 7641 7642 /* 7643 * note: the call to the framework needs to happen after feature expansion, 7644 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7645 * These may be set by the accel-specific code, 7646 * and the results are subsequently checked / assumed in this function. 7647 */ 7648 cpu_exec_realizefn(cs, &local_err); 7649 if (local_err != NULL) { 7650 error_propagate(errp, local_err); 7651 return; 7652 } 7653 7654 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7655 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7656 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7657 goto out; 7658 } 7659 7660 if (cpu->guest_phys_bits == -1) { 7661 /* 7662 * If it was not set by the user, or by the accelerator via 7663 * cpu_exec_realizefn, clear. 7664 */ 7665 cpu->guest_phys_bits = 0; 7666 } 7667 7668 if (cpu->ucode_rev == 0) { 7669 /* 7670 * The default is the same as KVM's. Note that this check 7671 * needs to happen after the evenual setting of ucode_rev in 7672 * accel-specific code in cpu_exec_realizefn. 7673 */ 7674 if (IS_AMD_CPU(env)) { 7675 cpu->ucode_rev = 0x01000065; 7676 } else { 7677 cpu->ucode_rev = 0x100000000ULL; 7678 } 7679 } 7680 7681 /* 7682 * mwait extended info: needed for Core compatibility 7683 * We always wake on interrupt even if host does not have the capability. 7684 * 7685 * requires the accel-specific code in cpu_exec_realizefn to 7686 * have already acquired the CPUID data into cpu->mwait. 7687 */ 7688 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7689 7690 /* For 64bit systems think about the number of physical bits to present. 7691 * ideally this should be the same as the host; anything other than matching 7692 * the host can cause incorrect guest behaviour. 7693 * QEMU used to pick the magic value of 40 bits that corresponds to 7694 * consumer AMD devices but nothing else. 7695 * 7696 * Note that this code assumes features expansion has already been done 7697 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7698 * phys_bits adjustments to match the host have been already done in 7699 * accel-specific code in cpu_exec_realizefn. 7700 */ 7701 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7702 if (cpu->phys_bits && 7703 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7704 cpu->phys_bits < 32)) { 7705 error_setg(errp, "phys-bits should be between 32 and %u " 7706 " (but is %u)", 7707 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7708 return; 7709 } 7710 /* 7711 * 0 means it was not explicitly set by the user (or by machine 7712 * compat_props or by the host code in host-cpu.c). 7713 * In this case, the default is the value used by TCG (40). 7714 */ 7715 if (cpu->phys_bits == 0) { 7716 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7717 } 7718 if (cpu->guest_phys_bits && 7719 (cpu->guest_phys_bits > cpu->phys_bits || 7720 cpu->guest_phys_bits < 32)) { 7721 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7722 " (but is %u)", 7723 cpu->phys_bits, cpu->guest_phys_bits); 7724 return; 7725 } 7726 } else { 7727 /* For 32 bit systems don't use the user set value, but keep 7728 * phys_bits consistent with what we tell the guest. 7729 */ 7730 if (cpu->phys_bits != 0) { 7731 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7732 return; 7733 } 7734 if (cpu->guest_phys_bits != 0) { 7735 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7736 return; 7737 } 7738 7739 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7740 cpu->phys_bits = 36; 7741 } else { 7742 cpu->phys_bits = 32; 7743 } 7744 } 7745 7746 /* Cache information initialization */ 7747 if (!cpu->legacy_cache) { 7748 const CPUCaches *cache_info = 7749 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7750 7751 if (!xcc->model || !cache_info) { 7752 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7753 error_setg(errp, 7754 "CPU model '%s' doesn't support legacy-cache=off", name); 7755 return; 7756 } 7757 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7758 *cache_info; 7759 } else { 7760 /* Build legacy cache information */ 7761 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7762 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7763 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7764 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7765 7766 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7767 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7768 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7769 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7770 7771 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7772 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7773 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7774 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7775 } 7776 7777 #ifndef CONFIG_USER_ONLY 7778 MachineState *ms = MACHINE(qdev_get_machine()); 7779 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7780 7781 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7782 x86_cpu_apic_create(cpu, &local_err); 7783 if (local_err != NULL) { 7784 goto out; 7785 } 7786 } 7787 #endif 7788 7789 mce_init(cpu); 7790 7791 qemu_init_vcpu(cs); 7792 7793 /* 7794 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7795 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7796 * based on inputs (sockets,cores,threads), it is still better to give 7797 * users a warning. 7798 * 7799 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7800 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7801 */ 7802 if (IS_AMD_CPU(env) && 7803 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7804 cs->nr_threads > 1) { 7805 warn_report_once("This family of AMD CPU doesn't support " 7806 "hyperthreading(%d). Please configure -smp " 7807 "options properly or try enabling topoext " 7808 "feature.", cs->nr_threads); 7809 } 7810 7811 #ifndef CONFIG_USER_ONLY 7812 x86_cpu_apic_realize(cpu, &local_err); 7813 if (local_err != NULL) { 7814 goto out; 7815 } 7816 #endif /* !CONFIG_USER_ONLY */ 7817 cpu_reset(cs); 7818 7819 xcc->parent_realize(dev, &local_err); 7820 7821 out: 7822 if (local_err != NULL) { 7823 error_propagate(errp, local_err); 7824 return; 7825 } 7826 } 7827 7828 static void x86_cpu_unrealizefn(DeviceState *dev) 7829 { 7830 X86CPU *cpu = X86_CPU(dev); 7831 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7832 7833 #ifndef CONFIG_USER_ONLY 7834 cpu_remove_sync(CPU(dev)); 7835 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7836 #endif 7837 7838 if (cpu->apic_state) { 7839 object_unparent(OBJECT(cpu->apic_state)); 7840 cpu->apic_state = NULL; 7841 } 7842 7843 xcc->parent_unrealize(dev); 7844 } 7845 7846 typedef struct BitProperty { 7847 FeatureWord w; 7848 uint64_t mask; 7849 } BitProperty; 7850 7851 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7852 void *opaque, Error **errp) 7853 { 7854 X86CPU *cpu = X86_CPU(obj); 7855 BitProperty *fp = opaque; 7856 uint64_t f = cpu->env.features[fp->w]; 7857 bool value = (f & fp->mask) == fp->mask; 7858 visit_type_bool(v, name, &value, errp); 7859 } 7860 7861 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7862 void *opaque, Error **errp) 7863 { 7864 DeviceState *dev = DEVICE(obj); 7865 X86CPU *cpu = X86_CPU(obj); 7866 BitProperty *fp = opaque; 7867 bool value; 7868 7869 if (dev->realized) { 7870 qdev_prop_set_after_realize(dev, name, errp); 7871 return; 7872 } 7873 7874 if (!visit_type_bool(v, name, &value, errp)) { 7875 return; 7876 } 7877 7878 if (value) { 7879 cpu->env.features[fp->w] |= fp->mask; 7880 } else { 7881 cpu->env.features[fp->w] &= ~fp->mask; 7882 } 7883 cpu->env.user_features[fp->w] |= fp->mask; 7884 } 7885 7886 /* Register a boolean property to get/set a single bit in a uint32_t field. 7887 * 7888 * The same property name can be registered multiple times to make it affect 7889 * multiple bits in the same FeatureWord. In that case, the getter will return 7890 * true only if all bits are set. 7891 */ 7892 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7893 const char *prop_name, 7894 FeatureWord w, 7895 int bitnr) 7896 { 7897 ObjectClass *oc = OBJECT_CLASS(xcc); 7898 BitProperty *fp; 7899 ObjectProperty *op; 7900 uint64_t mask = (1ULL << bitnr); 7901 7902 op = object_class_property_find(oc, prop_name); 7903 if (op) { 7904 fp = op->opaque; 7905 assert(fp->w == w); 7906 fp->mask |= mask; 7907 } else { 7908 fp = g_new0(BitProperty, 1); 7909 fp->w = w; 7910 fp->mask = mask; 7911 object_class_property_add(oc, prop_name, "bool", 7912 x86_cpu_get_bit_prop, 7913 x86_cpu_set_bit_prop, 7914 NULL, fp); 7915 } 7916 } 7917 7918 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7919 FeatureWord w, 7920 int bitnr) 7921 { 7922 FeatureWordInfo *fi = &feature_word_info[w]; 7923 const char *name = fi->feat_names[bitnr]; 7924 7925 if (!name) { 7926 return; 7927 } 7928 7929 /* Property names should use "-" instead of "_". 7930 * Old names containing underscores are registered as aliases 7931 * using object_property_add_alias() 7932 */ 7933 assert(!strchr(name, '_')); 7934 /* aliases don't use "|" delimiters anymore, they are registered 7935 * manually using object_property_add_alias() */ 7936 assert(!strchr(name, '|')); 7937 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7938 } 7939 7940 static void x86_cpu_post_initfn(Object *obj) 7941 { 7942 accel_cpu_instance_init(CPU(obj)); 7943 } 7944 7945 static void x86_cpu_init_default_topo(X86CPU *cpu) 7946 { 7947 CPUX86State *env = &cpu->env; 7948 7949 env->nr_modules = 1; 7950 env->nr_dies = 1; 7951 7952 /* SMT, core and package levels are set by default. */ 7953 set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); 7954 set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); 7955 set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); 7956 } 7957 7958 static void x86_cpu_initfn(Object *obj) 7959 { 7960 X86CPU *cpu = X86_CPU(obj); 7961 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7962 CPUX86State *env = &cpu->env; 7963 7964 x86_cpu_init_default_topo(cpu); 7965 7966 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7967 x86_cpu_get_feature_words, 7968 NULL, NULL, (void *)env->features); 7969 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 7970 x86_cpu_get_feature_words, 7971 NULL, NULL, (void *)cpu->filtered_features); 7972 7973 object_property_add_alias(obj, "sse3", obj, "pni"); 7974 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 7975 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 7976 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 7977 object_property_add_alias(obj, "xd", obj, "nx"); 7978 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 7979 object_property_add_alias(obj, "i64", obj, "lm"); 7980 7981 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7982 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7983 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7984 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7985 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7986 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7987 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7988 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7989 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7990 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7991 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7992 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7993 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7994 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7995 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7996 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7997 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7998 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7999 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8000 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8001 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8002 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8003 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8004 8005 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8006 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8007 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8008 8009 if (xcc->model) { 8010 x86_cpu_load_model(cpu, xcc->model); 8011 } 8012 } 8013 8014 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8015 { 8016 X86CPU *cpu = X86_CPU(cs); 8017 8018 return cpu->apic_id; 8019 } 8020 8021 #if !defined(CONFIG_USER_ONLY) 8022 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8023 { 8024 X86CPU *cpu = X86_CPU(cs); 8025 8026 return cpu->env.cr[0] & CR0_PG_MASK; 8027 } 8028 #endif /* !CONFIG_USER_ONLY */ 8029 8030 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8031 { 8032 X86CPU *cpu = X86_CPU(cs); 8033 8034 cpu->env.eip = value; 8035 } 8036 8037 static vaddr x86_cpu_get_pc(CPUState *cs) 8038 { 8039 X86CPU *cpu = X86_CPU(cs); 8040 8041 /* Match cpu_get_tb_cpu_state. */ 8042 return cpu->env.eip + cpu->env.segs[R_CS].base; 8043 } 8044 8045 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8046 { 8047 X86CPU *cpu = X86_CPU(cs); 8048 CPUX86State *env = &cpu->env; 8049 8050 #if !defined(CONFIG_USER_ONLY) 8051 if (interrupt_request & CPU_INTERRUPT_POLL) { 8052 return CPU_INTERRUPT_POLL; 8053 } 8054 #endif 8055 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8056 return CPU_INTERRUPT_SIPI; 8057 } 8058 8059 if (env->hflags2 & HF2_GIF_MASK) { 8060 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8061 !(env->hflags & HF_SMM_MASK)) { 8062 return CPU_INTERRUPT_SMI; 8063 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8064 !(env->hflags2 & HF2_NMI_MASK)) { 8065 return CPU_INTERRUPT_NMI; 8066 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8067 return CPU_INTERRUPT_MCE; 8068 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8069 (((env->hflags2 & HF2_VINTR_MASK) && 8070 (env->hflags2 & HF2_HIF_MASK)) || 8071 (!(env->hflags2 & HF2_VINTR_MASK) && 8072 (env->eflags & IF_MASK && 8073 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8074 return CPU_INTERRUPT_HARD; 8075 #if !defined(CONFIG_USER_ONLY) 8076 } else if (env->hflags2 & HF2_VGIF_MASK) { 8077 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8078 (env->eflags & IF_MASK) && 8079 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8080 return CPU_INTERRUPT_VIRQ; 8081 } 8082 #endif 8083 } 8084 } 8085 8086 return 0; 8087 } 8088 8089 static bool x86_cpu_has_work(CPUState *cs) 8090 { 8091 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8092 } 8093 8094 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8095 { 8096 CPUX86State *env = cpu_env(cs); 8097 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8098 int mmu_index_base = 8099 (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER64_IDX : 8100 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8101 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8102 8103 return mmu_index_base + mmu_index_32; 8104 } 8105 8106 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8107 { 8108 X86CPU *cpu = X86_CPU(cs); 8109 CPUX86State *env = &cpu->env; 8110 8111 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8112 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8113 : bfd_mach_i386_i8086); 8114 8115 info->cap_arch = CS_ARCH_X86; 8116 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8117 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8118 : CS_MODE_16); 8119 info->cap_insn_unit = 1; 8120 info->cap_insn_split = 8; 8121 } 8122 8123 void x86_update_hflags(CPUX86State *env) 8124 { 8125 uint32_t hflags; 8126 #define HFLAG_COPY_MASK \ 8127 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8128 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8129 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8130 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8131 8132 hflags = env->hflags & HFLAG_COPY_MASK; 8133 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8134 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8135 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8136 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8137 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8138 8139 if (env->cr[4] & CR4_OSFXSR_MASK) { 8140 hflags |= HF_OSFXSR_MASK; 8141 } 8142 8143 if (env->efer & MSR_EFER_LMA) { 8144 hflags |= HF_LMA_MASK; 8145 } 8146 8147 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8148 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8149 } else { 8150 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8151 (DESC_B_SHIFT - HF_CS32_SHIFT); 8152 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8153 (DESC_B_SHIFT - HF_SS32_SHIFT); 8154 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8155 !(hflags & HF_CS32_MASK)) { 8156 hflags |= HF_ADDSEG_MASK; 8157 } else { 8158 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8159 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8160 } 8161 } 8162 env->hflags = hflags; 8163 } 8164 8165 static Property x86_cpu_properties[] = { 8166 #ifdef CONFIG_USER_ONLY 8167 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8168 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8169 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8170 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8171 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8172 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8173 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8174 #else 8175 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8176 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8177 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8178 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8179 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8180 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8181 #endif 8182 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8183 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8184 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8185 8186 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8187 HYPERV_SPINLOCK_NEVER_NOTIFY), 8188 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8189 HYPERV_FEAT_RELAXED, 0), 8190 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8191 HYPERV_FEAT_VAPIC, 0), 8192 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8193 HYPERV_FEAT_TIME, 0), 8194 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8195 HYPERV_FEAT_CRASH, 0), 8196 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8197 HYPERV_FEAT_RESET, 0), 8198 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8199 HYPERV_FEAT_VPINDEX, 0), 8200 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8201 HYPERV_FEAT_RUNTIME, 0), 8202 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8203 HYPERV_FEAT_SYNIC, 0), 8204 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8205 HYPERV_FEAT_STIMER, 0), 8206 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8207 HYPERV_FEAT_FREQUENCIES, 0), 8208 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8209 HYPERV_FEAT_REENLIGHTENMENT, 0), 8210 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8211 HYPERV_FEAT_TLBFLUSH, 0), 8212 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8213 HYPERV_FEAT_EVMCS, 0), 8214 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8215 HYPERV_FEAT_IPI, 0), 8216 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8217 HYPERV_FEAT_STIMER_DIRECT, 0), 8218 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8219 HYPERV_FEAT_AVIC, 0), 8220 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8221 HYPERV_FEAT_MSR_BITMAP, 0), 8222 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8223 HYPERV_FEAT_XMM_INPUT, 0), 8224 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8225 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8226 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8227 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8228 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8229 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8230 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8231 HYPERV_FEAT_SYNDBG, 0), 8232 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8233 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8234 8235 /* WS2008R2 identify by default */ 8236 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8237 0x3839), 8238 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8239 0x000A), 8240 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8241 0x0000), 8242 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8243 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8244 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8245 8246 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8247 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8248 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8249 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8250 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8251 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8252 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8253 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8254 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8255 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8256 UINT32_MAX), 8257 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8258 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8259 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8260 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8261 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8262 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8263 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8264 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8265 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8266 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8267 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8268 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8269 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8270 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 8271 false), 8272 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8273 false), 8274 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8275 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8276 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8277 true), 8278 /* 8279 * lecacy_cache defaults to true unless the CPU model provides its 8280 * own cache information (see x86_cpu_load_def()). 8281 */ 8282 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8283 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8284 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8285 8286 /* 8287 * From "Requirements for Implementing the Microsoft 8288 * Hypervisor Interface": 8289 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8290 * 8291 * "Starting with Windows Server 2012 and Windows 8, if 8292 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8293 * the hypervisor imposes no specific limit to the number of VPs. 8294 * In this case, Windows Server 2012 guest VMs may use more than 8295 * 64 VPs, up to the maximum supported number of processors applicable 8296 * to the specific Windows version being used." 8297 */ 8298 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8299 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8300 false), 8301 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8302 true), 8303 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8304 DEFINE_PROP_END_OF_LIST() 8305 }; 8306 8307 #ifndef CONFIG_USER_ONLY 8308 #include "hw/core/sysemu-cpu-ops.h" 8309 8310 static const struct SysemuCPUOps i386_sysemu_ops = { 8311 .get_memory_mapping = x86_cpu_get_memory_mapping, 8312 .get_paging_enabled = x86_cpu_get_paging_enabled, 8313 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8314 .asidx_from_attrs = x86_asidx_from_attrs, 8315 .get_crash_info = x86_cpu_get_crash_info, 8316 .write_elf32_note = x86_cpu_write_elf32_note, 8317 .write_elf64_note = x86_cpu_write_elf64_note, 8318 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8319 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8320 .legacy_vmsd = &vmstate_x86_cpu, 8321 }; 8322 #endif 8323 8324 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8325 { 8326 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8327 CPUClass *cc = CPU_CLASS(oc); 8328 DeviceClass *dc = DEVICE_CLASS(oc); 8329 ResettableClass *rc = RESETTABLE_CLASS(oc); 8330 FeatureWord w; 8331 8332 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8333 &xcc->parent_realize); 8334 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8335 &xcc->parent_unrealize); 8336 device_class_set_props(dc, x86_cpu_properties); 8337 8338 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8339 &xcc->parent_phases); 8340 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8341 8342 cc->class_by_name = x86_cpu_class_by_name; 8343 cc->parse_features = x86_cpu_parse_featurestr; 8344 cc->has_work = x86_cpu_has_work; 8345 cc->mmu_index = x86_cpu_mmu_index; 8346 cc->dump_state = x86_cpu_dump_state; 8347 cc->set_pc = x86_cpu_set_pc; 8348 cc->get_pc = x86_cpu_get_pc; 8349 cc->gdb_read_register = x86_cpu_gdb_read_register; 8350 cc->gdb_write_register = x86_cpu_gdb_write_register; 8351 cc->get_arch_id = x86_cpu_get_arch_id; 8352 8353 #ifndef CONFIG_USER_ONLY 8354 cc->sysemu_ops = &i386_sysemu_ops; 8355 #endif /* !CONFIG_USER_ONLY */ 8356 8357 cc->gdb_arch_name = x86_gdb_arch_name; 8358 #ifdef TARGET_X86_64 8359 cc->gdb_core_xml_file = "i386-64bit.xml"; 8360 #else 8361 cc->gdb_core_xml_file = "i386-32bit.xml"; 8362 #endif 8363 cc->disas_set_info = x86_disas_set_info; 8364 8365 dc->user_creatable = true; 8366 8367 object_class_property_add(oc, "family", "int", 8368 x86_cpuid_version_get_family, 8369 x86_cpuid_version_set_family, NULL, NULL); 8370 object_class_property_add(oc, "model", "int", 8371 x86_cpuid_version_get_model, 8372 x86_cpuid_version_set_model, NULL, NULL); 8373 object_class_property_add(oc, "stepping", "int", 8374 x86_cpuid_version_get_stepping, 8375 x86_cpuid_version_set_stepping, NULL, NULL); 8376 object_class_property_add_str(oc, "vendor", 8377 x86_cpuid_get_vendor, 8378 x86_cpuid_set_vendor); 8379 object_class_property_add_str(oc, "model-id", 8380 x86_cpuid_get_model_id, 8381 x86_cpuid_set_model_id); 8382 object_class_property_add(oc, "tsc-frequency", "int", 8383 x86_cpuid_get_tsc_freq, 8384 x86_cpuid_set_tsc_freq, NULL, NULL); 8385 /* 8386 * The "unavailable-features" property has the same semantics as 8387 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8388 * QMP command: they list the features that would have prevented the 8389 * CPU from running if the "enforce" flag was set. 8390 */ 8391 object_class_property_add(oc, "unavailable-features", "strList", 8392 x86_cpu_get_unavailable_features, 8393 NULL, NULL, NULL); 8394 8395 #if !defined(CONFIG_USER_ONLY) 8396 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8397 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8398 #endif 8399 8400 for (w = 0; w < FEATURE_WORDS; w++) { 8401 int bitnr; 8402 for (bitnr = 0; bitnr < 64; bitnr++) { 8403 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8404 } 8405 } 8406 } 8407 8408 static const TypeInfo x86_cpu_type_info = { 8409 .name = TYPE_X86_CPU, 8410 .parent = TYPE_CPU, 8411 .instance_size = sizeof(X86CPU), 8412 .instance_align = __alignof(X86CPU), 8413 .instance_init = x86_cpu_initfn, 8414 .instance_post_init = x86_cpu_post_initfn, 8415 8416 .abstract = true, 8417 .class_size = sizeof(X86CPUClass), 8418 .class_init = x86_cpu_common_class_init, 8419 }; 8420 8421 /* "base" CPU model, used by query-cpu-model-expansion */ 8422 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8423 { 8424 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8425 8426 xcc->static_model = true; 8427 xcc->migration_safe = true; 8428 xcc->model_description = "base CPU model type with no features enabled"; 8429 xcc->ordering = 8; 8430 } 8431 8432 static const TypeInfo x86_base_cpu_type_info = { 8433 .name = X86_CPU_TYPE_NAME("base"), 8434 .parent = TYPE_X86_CPU, 8435 .class_init = x86_cpu_base_class_init, 8436 }; 8437 8438 static void x86_cpu_register_types(void) 8439 { 8440 int i; 8441 8442 type_register_static(&x86_cpu_type_info); 8443 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8444 x86_register_cpudef_types(&builtin_x86_defs[i]); 8445 } 8446 type_register_static(&max_x86_cpu_type_info); 8447 type_register_static(&x86_base_cpu_type_info); 8448 } 8449 8450 type_init(x86_cpu_register_types) 8451