1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "cpu.h" 25 #include "tcg/helper-tcg.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/hvf.h" 28 #include "kvm/kvm_i386.h" 29 #include "sev_i386.h" 30 #include "qapi/qapi-visit-machine.h" 31 #include "qapi/qmp/qerror.h" 32 #include "qapi/qapi-commands-machine-target.h" 33 #include "standard-headers/asm-x86/kvm_para.h" 34 #include "hw/qdev-properties.h" 35 #include "hw/i386/topology.h" 36 #ifndef CONFIG_USER_ONLY 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #endif 40 41 #include "disas/capstone.h" 42 #include "cpu-internal.h" 43 44 /* Helpers for building CPUID[2] descriptors: */ 45 46 struct CPUID2CacheDescriptorInfo { 47 enum CacheType type; 48 int level; 49 int size; 50 int line_size; 51 int associativity; 52 }; 53 54 /* 55 * Known CPUID 2 cache descriptors. 56 * From Intel SDM Volume 2A, CPUID instruction 57 */ 58 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 59 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 60 .associativity = 4, .line_size = 32, }, 61 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 62 .associativity = 4, .line_size = 32, }, 63 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 64 .associativity = 4, .line_size = 64, }, 65 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 66 .associativity = 2, .line_size = 32, }, 67 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 68 .associativity = 4, .line_size = 32, }, 69 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 70 .associativity = 4, .line_size = 64, }, 71 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 72 .associativity = 6, .line_size = 64, }, 73 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 74 .associativity = 2, .line_size = 64, }, 75 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 76 .associativity = 8, .line_size = 64, }, 77 /* lines per sector is not supported cpuid2_cache_descriptor(), 78 * so descriptors 0x22, 0x23 are not included 79 */ 80 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 81 .associativity = 16, .line_size = 64, }, 82 /* lines per sector is not supported cpuid2_cache_descriptor(), 83 * so descriptors 0x25, 0x20 are not included 84 */ 85 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 86 .associativity = 8, .line_size = 64, }, 87 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 88 .associativity = 8, .line_size = 64, }, 89 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 90 .associativity = 4, .line_size = 32, }, 91 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 92 .associativity = 4, .line_size = 32, }, 93 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 94 .associativity = 4, .line_size = 32, }, 95 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 96 .associativity = 4, .line_size = 32, }, 97 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 98 .associativity = 4, .line_size = 32, }, 99 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 100 .associativity = 4, .line_size = 64, }, 101 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 102 .associativity = 8, .line_size = 64, }, 103 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 104 .associativity = 12, .line_size = 64, }, 105 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 106 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 107 .associativity = 12, .line_size = 64, }, 108 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 16, .line_size = 64, }, 110 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 113 .associativity = 16, .line_size = 64, }, 114 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 115 .associativity = 24, .line_size = 64, }, 116 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 117 .associativity = 8, .line_size = 64, }, 118 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 119 .associativity = 4, .line_size = 64, }, 120 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 121 .associativity = 4, .line_size = 64, }, 122 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 123 .associativity = 4, .line_size = 64, }, 124 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 125 .associativity = 4, .line_size = 64, }, 126 /* lines per sector is not supported cpuid2_cache_descriptor(), 127 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 128 */ 129 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 130 .associativity = 8, .line_size = 64, }, 131 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 132 .associativity = 2, .line_size = 64, }, 133 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 134 .associativity = 8, .line_size = 64, }, 135 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 136 .associativity = 8, .line_size = 32, }, 137 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 138 .associativity = 8, .line_size = 32, }, 139 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 140 .associativity = 8, .line_size = 32, }, 141 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 142 .associativity = 8, .line_size = 32, }, 143 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 4, .line_size = 64, }, 145 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 146 .associativity = 8, .line_size = 64, }, 147 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 148 .associativity = 4, .line_size = 64, }, 149 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 150 .associativity = 4, .line_size = 64, }, 151 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 152 .associativity = 4, .line_size = 64, }, 153 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 154 .associativity = 8, .line_size = 64, }, 155 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 156 .associativity = 8, .line_size = 64, }, 157 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 158 .associativity = 8, .line_size = 64, }, 159 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 160 .associativity = 12, .line_size = 64, }, 161 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 162 .associativity = 12, .line_size = 64, }, 163 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 164 .associativity = 12, .line_size = 64, }, 165 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 166 .associativity = 16, .line_size = 64, }, 167 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 168 .associativity = 16, .line_size = 64, }, 169 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 170 .associativity = 16, .line_size = 64, }, 171 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 172 .associativity = 24, .line_size = 64, }, 173 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 174 .associativity = 24, .line_size = 64, }, 175 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 176 .associativity = 24, .line_size = 64, }, 177 }; 178 179 /* 180 * "CPUID leaf 2 does not report cache descriptor information, 181 * use CPUID leaf 4 to query cache parameters" 182 */ 183 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 184 185 /* 186 * Return a CPUID 2 cache descriptor for a given cache. 187 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 188 */ 189 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 190 { 191 int i; 192 193 assert(cache->size > 0); 194 assert(cache->level > 0); 195 assert(cache->line_size > 0); 196 assert(cache->associativity > 0); 197 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 198 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 199 if (d->level == cache->level && d->type == cache->type && 200 d->size == cache->size && d->line_size == cache->line_size && 201 d->associativity == cache->associativity) { 202 return i; 203 } 204 } 205 206 return CACHE_DESCRIPTOR_UNAVAILABLE; 207 } 208 209 /* CPUID Leaf 4 constants: */ 210 211 /* EAX: */ 212 #define CACHE_TYPE_D 1 213 #define CACHE_TYPE_I 2 214 #define CACHE_TYPE_UNIFIED 3 215 216 #define CACHE_LEVEL(l) (l << 5) 217 218 #define CACHE_SELF_INIT_LEVEL (1 << 8) 219 220 /* EDX: */ 221 #define CACHE_NO_INVD_SHARING (1 << 0) 222 #define CACHE_INCLUSIVE (1 << 1) 223 #define CACHE_COMPLEX_IDX (1 << 2) 224 225 /* Encode CacheType for CPUID[4].EAX */ 226 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 227 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 228 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 229 0 /* Invalid value */) 230 231 232 /* Encode cache info for CPUID[4] */ 233 static void encode_cache_cpuid4(CPUCacheInfo *cache, 234 int num_apic_ids, int num_cores, 235 uint32_t *eax, uint32_t *ebx, 236 uint32_t *ecx, uint32_t *edx) 237 { 238 assert(cache->size == cache->line_size * cache->associativity * 239 cache->partitions * cache->sets); 240 241 assert(num_apic_ids > 0); 242 *eax = CACHE_TYPE(cache->type) | 243 CACHE_LEVEL(cache->level) | 244 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 245 ((num_cores - 1) << 26) | 246 ((num_apic_ids - 1) << 14); 247 248 assert(cache->line_size > 0); 249 assert(cache->partitions > 0); 250 assert(cache->associativity > 0); 251 /* We don't implement fully-associative caches */ 252 assert(cache->associativity < cache->sets); 253 *ebx = (cache->line_size - 1) | 254 ((cache->partitions - 1) << 12) | 255 ((cache->associativity - 1) << 22); 256 257 assert(cache->sets > 0); 258 *ecx = cache->sets - 1; 259 260 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 261 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 262 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 263 } 264 265 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 266 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 267 { 268 assert(cache->size % 1024 == 0); 269 assert(cache->lines_per_tag > 0); 270 assert(cache->associativity > 0); 271 assert(cache->line_size > 0); 272 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 273 (cache->lines_per_tag << 8) | (cache->line_size); 274 } 275 276 #define ASSOC_FULL 0xFF 277 278 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 279 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 280 a == 2 ? 0x2 : \ 281 a == 4 ? 0x4 : \ 282 a == 8 ? 0x6 : \ 283 a == 16 ? 0x8 : \ 284 a == 32 ? 0xA : \ 285 a == 48 ? 0xB : \ 286 a == 64 ? 0xC : \ 287 a == 96 ? 0xD : \ 288 a == 128 ? 0xE : \ 289 a == ASSOC_FULL ? 0xF : \ 290 0 /* invalid value */) 291 292 /* 293 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 294 * @l3 can be NULL. 295 */ 296 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 297 CPUCacheInfo *l3, 298 uint32_t *ecx, uint32_t *edx) 299 { 300 assert(l2->size % 1024 == 0); 301 assert(l2->associativity > 0); 302 assert(l2->lines_per_tag > 0); 303 assert(l2->line_size > 0); 304 *ecx = ((l2->size / 1024) << 16) | 305 (AMD_ENC_ASSOC(l2->associativity) << 12) | 306 (l2->lines_per_tag << 8) | (l2->line_size); 307 308 if (l3) { 309 assert(l3->size % (512 * 1024) == 0); 310 assert(l3->associativity > 0); 311 assert(l3->lines_per_tag > 0); 312 assert(l3->line_size > 0); 313 *edx = ((l3->size / (512 * 1024)) << 18) | 314 (AMD_ENC_ASSOC(l3->associativity) << 12) | 315 (l3->lines_per_tag << 8) | (l3->line_size); 316 } else { 317 *edx = 0; 318 } 319 } 320 321 /* Encode cache info for CPUID[8000001D] */ 322 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 323 X86CPUTopoInfo *topo_info, 324 uint32_t *eax, uint32_t *ebx, 325 uint32_t *ecx, uint32_t *edx) 326 { 327 uint32_t l3_threads; 328 assert(cache->size == cache->line_size * cache->associativity * 329 cache->partitions * cache->sets); 330 331 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 332 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 333 334 /* L3 is shared among multiple cores */ 335 if (cache->level == 3) { 336 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 337 *eax |= (l3_threads - 1) << 14; 338 } else { 339 *eax |= ((topo_info->threads_per_core - 1) << 14); 340 } 341 342 assert(cache->line_size > 0); 343 assert(cache->partitions > 0); 344 assert(cache->associativity > 0); 345 /* We don't implement fully-associative caches */ 346 assert(cache->associativity < cache->sets); 347 *ebx = (cache->line_size - 1) | 348 ((cache->partitions - 1) << 12) | 349 ((cache->associativity - 1) << 22); 350 351 assert(cache->sets > 0); 352 *ecx = cache->sets - 1; 353 354 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 355 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 356 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 357 } 358 359 /* Encode cache info for CPUID[8000001E] */ 360 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 361 uint32_t *eax, uint32_t *ebx, 362 uint32_t *ecx, uint32_t *edx) 363 { 364 X86CPUTopoIDs topo_ids; 365 366 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 367 368 *eax = cpu->apic_id; 369 370 /* 371 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 372 * Read-only. Reset: 0000_XXXXh. 373 * See Core::X86::Cpuid::ExtApicId. 374 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 375 * Bits Description 376 * 31:16 Reserved. 377 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 378 * The number of threads per core is ThreadsPerCore+1. 379 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 380 * 381 * NOTE: CoreId is already part of apic_id. Just use it. We can 382 * use all the 8 bits to represent the core_id here. 383 */ 384 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 385 386 /* 387 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 388 * Read-only. Reset: 0000_0XXXh. 389 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 390 * Bits Description 391 * 31:11 Reserved. 392 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 393 * ValidValues: 394 * Value Description 395 * 000b 1 node per processor. 396 * 001b 2 nodes per processor. 397 * 010b Reserved. 398 * 011b 4 nodes per processor. 399 * 111b-100b Reserved. 400 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 401 * 402 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 403 * But users can create more nodes than the actual hardware can 404 * support. To genaralize we can use all the upper 8 bits for nodes. 405 * NodeId is combination of node and socket_id which is already decoded 406 * in apic_id. Just use it by shifting. 407 */ 408 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 409 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 410 411 *edx = 0; 412 } 413 414 /* 415 * Definitions of the hardcoded cache entries we expose: 416 * These are legacy cache values. If there is a need to change any 417 * of these values please use builtin_x86_defs 418 */ 419 420 /* L1 data cache: */ 421 static CPUCacheInfo legacy_l1d_cache = { 422 .type = DATA_CACHE, 423 .level = 1, 424 .size = 32 * KiB, 425 .self_init = 1, 426 .line_size = 64, 427 .associativity = 8, 428 .sets = 64, 429 .partitions = 1, 430 .no_invd_sharing = true, 431 }; 432 433 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 434 static CPUCacheInfo legacy_l1d_cache_amd = { 435 .type = DATA_CACHE, 436 .level = 1, 437 .size = 64 * KiB, 438 .self_init = 1, 439 .line_size = 64, 440 .associativity = 2, 441 .sets = 512, 442 .partitions = 1, 443 .lines_per_tag = 1, 444 .no_invd_sharing = true, 445 }; 446 447 /* L1 instruction cache: */ 448 static CPUCacheInfo legacy_l1i_cache = { 449 .type = INSTRUCTION_CACHE, 450 .level = 1, 451 .size = 32 * KiB, 452 .self_init = 1, 453 .line_size = 64, 454 .associativity = 8, 455 .sets = 64, 456 .partitions = 1, 457 .no_invd_sharing = true, 458 }; 459 460 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 461 static CPUCacheInfo legacy_l1i_cache_amd = { 462 .type = INSTRUCTION_CACHE, 463 .level = 1, 464 .size = 64 * KiB, 465 .self_init = 1, 466 .line_size = 64, 467 .associativity = 2, 468 .sets = 512, 469 .partitions = 1, 470 .lines_per_tag = 1, 471 .no_invd_sharing = true, 472 }; 473 474 /* Level 2 unified cache: */ 475 static CPUCacheInfo legacy_l2_cache = { 476 .type = UNIFIED_CACHE, 477 .level = 2, 478 .size = 4 * MiB, 479 .self_init = 1, 480 .line_size = 64, 481 .associativity = 16, 482 .sets = 4096, 483 .partitions = 1, 484 .no_invd_sharing = true, 485 }; 486 487 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 488 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 489 .type = UNIFIED_CACHE, 490 .level = 2, 491 .size = 2 * MiB, 492 .line_size = 64, 493 .associativity = 8, 494 }; 495 496 497 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 498 static CPUCacheInfo legacy_l2_cache_amd = { 499 .type = UNIFIED_CACHE, 500 .level = 2, 501 .size = 512 * KiB, 502 .line_size = 64, 503 .lines_per_tag = 1, 504 .associativity = 16, 505 .sets = 512, 506 .partitions = 1, 507 }; 508 509 /* Level 3 unified cache: */ 510 static CPUCacheInfo legacy_l3_cache = { 511 .type = UNIFIED_CACHE, 512 .level = 3, 513 .size = 16 * MiB, 514 .line_size = 64, 515 .associativity = 16, 516 .sets = 16384, 517 .partitions = 1, 518 .lines_per_tag = 1, 519 .self_init = true, 520 .inclusive = true, 521 .complex_indexing = true, 522 }; 523 524 /* TLB definitions: */ 525 526 #define L1_DTLB_2M_ASSOC 1 527 #define L1_DTLB_2M_ENTRIES 255 528 #define L1_DTLB_4K_ASSOC 1 529 #define L1_DTLB_4K_ENTRIES 255 530 531 #define L1_ITLB_2M_ASSOC 1 532 #define L1_ITLB_2M_ENTRIES 255 533 #define L1_ITLB_4K_ASSOC 1 534 #define L1_ITLB_4K_ENTRIES 255 535 536 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 537 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 538 #define L2_DTLB_4K_ASSOC 4 539 #define L2_DTLB_4K_ENTRIES 512 540 541 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 542 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 543 #define L2_ITLB_4K_ASSOC 4 544 #define L2_ITLB_4K_ENTRIES 512 545 546 /* CPUID Leaf 0x14 constants: */ 547 #define INTEL_PT_MAX_SUBLEAF 0x1 548 /* 549 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 550 * MSR can be accessed; 551 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 552 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 553 * of Intel PT MSRs across warm reset; 554 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 555 */ 556 #define INTEL_PT_MINIMAL_EBX 0xf 557 /* 558 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 559 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 560 * accessed; 561 * bit[01]: ToPA tables can hold any number of output entries, up to the 562 * maximum allowed by the MaskOrTableOffset field of 563 * IA32_RTIT_OUTPUT_MASK_PTRS; 564 * bit[02]: Support Single-Range Output scheme; 565 */ 566 #define INTEL_PT_MINIMAL_ECX 0x7 567 /* generated packets which contain IP payloads have LIP values */ 568 #define INTEL_PT_IP_LIP (1 << 31) 569 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 570 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 571 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 572 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 573 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 574 575 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 576 uint32_t vendor2, uint32_t vendor3) 577 { 578 int i; 579 for (i = 0; i < 4; i++) { 580 dst[i] = vendor1 >> (8 * i); 581 dst[i + 4] = vendor2 >> (8 * i); 582 dst[i + 8] = vendor3 >> (8 * i); 583 } 584 dst[CPUID_VENDOR_SZ] = '\0'; 585 } 586 587 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 588 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 589 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 590 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 591 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 592 CPUID_PSE36 | CPUID_FXSR) 593 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 594 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 595 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 596 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 597 CPUID_PAE | CPUID_SEP | CPUID_APIC) 598 599 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 600 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 601 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 602 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 603 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 604 /* partly implemented: 605 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 606 /* missing: 607 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 608 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 609 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 610 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 611 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 612 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 613 CPUID_EXT_RDRAND) 614 /* missing: 615 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 616 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, 617 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 618 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX, 619 CPUID_EXT_F16C */ 620 621 #ifdef TARGET_X86_64 622 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 623 #else 624 #define TCG_EXT2_X86_64_FEATURES 0 625 #endif 626 627 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 628 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 629 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 630 TCG_EXT2_X86_64_FEATURES) 631 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 632 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 633 #define TCG_EXT4_FEATURES 0 634 #define TCG_SVM_FEATURES CPUID_SVM_NPT 635 #define TCG_KVM_FEATURES 0 636 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 637 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 638 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 639 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 640 CPUID_7_0_EBX_ERMS) 641 /* missing: 642 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, 643 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 644 CPUID_7_0_EBX_RDSEED */ 645 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \ 646 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 647 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS) 648 #define TCG_7_0_EDX_FEATURES 0 649 #define TCG_7_1_EAX_FEATURES 0 650 #define TCG_APM_FEATURES 0 651 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 652 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 653 /* missing: 654 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 655 #define TCG_14_0_ECX_FEATURES 0 656 657 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 658 [FEAT_1_EDX] = { 659 .type = CPUID_FEATURE_WORD, 660 .feat_names = { 661 "fpu", "vme", "de", "pse", 662 "tsc", "msr", "pae", "mce", 663 "cx8", "apic", NULL, "sep", 664 "mtrr", "pge", "mca", "cmov", 665 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 666 NULL, "ds" /* Intel dts */, "acpi", "mmx", 667 "fxsr", "sse", "sse2", "ss", 668 "ht" /* Intel htt */, "tm", "ia64", "pbe", 669 }, 670 .cpuid = {.eax = 1, .reg = R_EDX, }, 671 .tcg_features = TCG_FEATURES, 672 }, 673 [FEAT_1_ECX] = { 674 .type = CPUID_FEATURE_WORD, 675 .feat_names = { 676 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 677 "ds-cpl", "vmx", "smx", "est", 678 "tm2", "ssse3", "cid", NULL, 679 "fma", "cx16", "xtpr", "pdcm", 680 NULL, "pcid", "dca", "sse4.1", 681 "sse4.2", "x2apic", "movbe", "popcnt", 682 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 683 "avx", "f16c", "rdrand", "hypervisor", 684 }, 685 .cpuid = { .eax = 1, .reg = R_ECX, }, 686 .tcg_features = TCG_EXT_FEATURES, 687 }, 688 /* Feature names that are already defined on feature_name[] but 689 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 690 * names on feat_names below. They are copied automatically 691 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 692 */ 693 [FEAT_8000_0001_EDX] = { 694 .type = CPUID_FEATURE_WORD, 695 .feat_names = { 696 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 697 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 698 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 699 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 700 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 701 "nx", NULL, "mmxext", NULL /* mmx */, 702 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 703 NULL, "lm", "3dnowext", "3dnow", 704 }, 705 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 706 .tcg_features = TCG_EXT2_FEATURES, 707 }, 708 [FEAT_8000_0001_ECX] = { 709 .type = CPUID_FEATURE_WORD, 710 .feat_names = { 711 "lahf-lm", "cmp-legacy", "svm", "extapic", 712 "cr8legacy", "abm", "sse4a", "misalignsse", 713 "3dnowprefetch", "osvw", "ibs", "xop", 714 "skinit", "wdt", NULL, "lwp", 715 "fma4", "tce", NULL, "nodeid-msr", 716 NULL, "tbm", "topoext", "perfctr-core", 717 "perfctr-nb", NULL, NULL, NULL, 718 NULL, NULL, NULL, NULL, 719 }, 720 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 721 .tcg_features = TCG_EXT3_FEATURES, 722 /* 723 * TOPOEXT is always allowed but can't be enabled blindly by 724 * "-cpu host", as it requires consistent cache topology info 725 * to be provided so it doesn't confuse guests. 726 */ 727 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 728 }, 729 [FEAT_C000_0001_EDX] = { 730 .type = CPUID_FEATURE_WORD, 731 .feat_names = { 732 NULL, NULL, "xstore", "xstore-en", 733 NULL, NULL, "xcrypt", "xcrypt-en", 734 "ace2", "ace2-en", "phe", "phe-en", 735 "pmm", "pmm-en", NULL, NULL, 736 NULL, NULL, NULL, NULL, 737 NULL, NULL, NULL, NULL, 738 NULL, NULL, NULL, NULL, 739 NULL, NULL, NULL, NULL, 740 }, 741 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 742 .tcg_features = TCG_EXT4_FEATURES, 743 }, 744 [FEAT_KVM] = { 745 .type = CPUID_FEATURE_WORD, 746 .feat_names = { 747 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 748 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 749 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 750 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 751 NULL, NULL, NULL, NULL, 752 NULL, NULL, NULL, NULL, 753 "kvmclock-stable-bit", NULL, NULL, NULL, 754 NULL, NULL, NULL, NULL, 755 }, 756 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 757 .tcg_features = TCG_KVM_FEATURES, 758 }, 759 [FEAT_KVM_HINTS] = { 760 .type = CPUID_FEATURE_WORD, 761 .feat_names = { 762 "kvm-hint-dedicated", NULL, NULL, NULL, 763 NULL, NULL, NULL, NULL, 764 NULL, NULL, NULL, NULL, 765 NULL, NULL, NULL, NULL, 766 NULL, NULL, NULL, NULL, 767 NULL, NULL, NULL, NULL, 768 NULL, NULL, NULL, NULL, 769 NULL, NULL, NULL, NULL, 770 }, 771 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 772 .tcg_features = TCG_KVM_FEATURES, 773 /* 774 * KVM hints aren't auto-enabled by -cpu host, they need to be 775 * explicitly enabled in the command-line. 776 */ 777 .no_autoenable_flags = ~0U, 778 }, 779 [FEAT_SVM] = { 780 .type = CPUID_FEATURE_WORD, 781 .feat_names = { 782 "npt", "lbrv", "svm-lock", "nrip-save", 783 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 784 NULL, NULL, "pause-filter", NULL, 785 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 786 "vgif", NULL, NULL, NULL, 787 NULL, NULL, NULL, NULL, 788 NULL, NULL, NULL, NULL, 789 "svme-addr-chk", NULL, NULL, NULL, 790 }, 791 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 792 .tcg_features = TCG_SVM_FEATURES, 793 }, 794 [FEAT_7_0_EBX] = { 795 .type = CPUID_FEATURE_WORD, 796 .feat_names = { 797 "fsgsbase", "tsc-adjust", NULL, "bmi1", 798 "hle", "avx2", NULL, "smep", 799 "bmi2", "erms", "invpcid", "rtm", 800 NULL, NULL, "mpx", NULL, 801 "avx512f", "avx512dq", "rdseed", "adx", 802 "smap", "avx512ifma", "pcommit", "clflushopt", 803 "clwb", "intel-pt", "avx512pf", "avx512er", 804 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 805 }, 806 .cpuid = { 807 .eax = 7, 808 .needs_ecx = true, .ecx = 0, 809 .reg = R_EBX, 810 }, 811 .tcg_features = TCG_7_0_EBX_FEATURES, 812 }, 813 [FEAT_7_0_ECX] = { 814 .type = CPUID_FEATURE_WORD, 815 .feat_names = { 816 NULL, "avx512vbmi", "umip", "pku", 817 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 818 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 819 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 820 "la57", NULL, NULL, NULL, 821 NULL, NULL, "rdpid", NULL, 822 "bus-lock-detect", "cldemote", NULL, "movdiri", 823 "movdir64b", NULL, NULL, "pks", 824 }, 825 .cpuid = { 826 .eax = 7, 827 .needs_ecx = true, .ecx = 0, 828 .reg = R_ECX, 829 }, 830 .tcg_features = TCG_7_0_ECX_FEATURES, 831 }, 832 [FEAT_7_0_EDX] = { 833 .type = CPUID_FEATURE_WORD, 834 .feat_names = { 835 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 836 "fsrm", NULL, NULL, NULL, 837 "avx512-vp2intersect", NULL, "md-clear", NULL, 838 NULL, NULL, "serialize", NULL, 839 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, 840 NULL, NULL, NULL, "avx512-fp16", 841 NULL, NULL, "spec-ctrl", "stibp", 842 NULL, "arch-capabilities", "core-capability", "ssbd", 843 }, 844 .cpuid = { 845 .eax = 7, 846 .needs_ecx = true, .ecx = 0, 847 .reg = R_EDX, 848 }, 849 .tcg_features = TCG_7_0_EDX_FEATURES, 850 }, 851 [FEAT_7_1_EAX] = { 852 .type = CPUID_FEATURE_WORD, 853 .feat_names = { 854 NULL, NULL, NULL, NULL, 855 "avx-vnni", "avx512-bf16", NULL, NULL, 856 NULL, NULL, NULL, NULL, 857 NULL, NULL, NULL, NULL, 858 NULL, NULL, NULL, NULL, 859 NULL, NULL, NULL, NULL, 860 NULL, NULL, NULL, NULL, 861 NULL, NULL, NULL, NULL, 862 }, 863 .cpuid = { 864 .eax = 7, 865 .needs_ecx = true, .ecx = 1, 866 .reg = R_EAX, 867 }, 868 .tcg_features = TCG_7_1_EAX_FEATURES, 869 }, 870 [FEAT_8000_0007_EDX] = { 871 .type = CPUID_FEATURE_WORD, 872 .feat_names = { 873 NULL, NULL, NULL, NULL, 874 NULL, NULL, NULL, NULL, 875 "invtsc", NULL, NULL, NULL, 876 NULL, NULL, NULL, NULL, 877 NULL, NULL, NULL, NULL, 878 NULL, NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 NULL, NULL, NULL, NULL, 881 }, 882 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 883 .tcg_features = TCG_APM_FEATURES, 884 .unmigratable_flags = CPUID_APM_INVTSC, 885 }, 886 [FEAT_8000_0008_EBX] = { 887 .type = CPUID_FEATURE_WORD, 888 .feat_names = { 889 "clzero", NULL, "xsaveerptr", NULL, 890 NULL, NULL, NULL, NULL, 891 NULL, "wbnoinvd", NULL, NULL, 892 "ibpb", NULL, "ibrs", "amd-stibp", 893 NULL, NULL, NULL, NULL, 894 NULL, NULL, NULL, NULL, 895 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 896 NULL, NULL, NULL, NULL, 897 }, 898 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 899 .tcg_features = 0, 900 .unmigratable_flags = 0, 901 }, 902 [FEAT_XSAVE] = { 903 .type = CPUID_FEATURE_WORD, 904 .feat_names = { 905 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 906 NULL, NULL, NULL, NULL, 907 NULL, NULL, NULL, NULL, 908 NULL, NULL, NULL, NULL, 909 NULL, NULL, NULL, NULL, 910 NULL, NULL, NULL, NULL, 911 NULL, NULL, NULL, NULL, 912 NULL, NULL, NULL, NULL, 913 }, 914 .cpuid = { 915 .eax = 0xd, 916 .needs_ecx = true, .ecx = 1, 917 .reg = R_EAX, 918 }, 919 .tcg_features = TCG_XSAVE_FEATURES, 920 }, 921 [FEAT_6_EAX] = { 922 .type = CPUID_FEATURE_WORD, 923 .feat_names = { 924 NULL, NULL, "arat", NULL, 925 NULL, NULL, NULL, NULL, 926 NULL, NULL, NULL, NULL, 927 NULL, NULL, NULL, NULL, 928 NULL, NULL, NULL, NULL, 929 NULL, NULL, NULL, NULL, 930 NULL, NULL, NULL, NULL, 931 NULL, NULL, NULL, NULL, 932 }, 933 .cpuid = { .eax = 6, .reg = R_EAX, }, 934 .tcg_features = TCG_6_EAX_FEATURES, 935 }, 936 [FEAT_XSAVE_COMP_LO] = { 937 .type = CPUID_FEATURE_WORD, 938 .cpuid = { 939 .eax = 0xD, 940 .needs_ecx = true, .ecx = 0, 941 .reg = R_EAX, 942 }, 943 .tcg_features = ~0U, 944 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 945 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 946 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 947 XSTATE_PKRU_MASK, 948 }, 949 [FEAT_XSAVE_COMP_HI] = { 950 .type = CPUID_FEATURE_WORD, 951 .cpuid = { 952 .eax = 0xD, 953 .needs_ecx = true, .ecx = 0, 954 .reg = R_EDX, 955 }, 956 .tcg_features = ~0U, 957 }, 958 /*Below are MSR exposed features*/ 959 [FEAT_ARCH_CAPABILITIES] = { 960 .type = MSR_FEATURE_WORD, 961 .feat_names = { 962 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 963 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 964 "taa-no", NULL, NULL, NULL, 965 NULL, NULL, NULL, NULL, 966 NULL, NULL, NULL, NULL, 967 NULL, NULL, NULL, NULL, 968 NULL, NULL, NULL, NULL, 969 NULL, NULL, NULL, NULL, 970 }, 971 .msr = { 972 .index = MSR_IA32_ARCH_CAPABILITIES, 973 }, 974 }, 975 [FEAT_CORE_CAPABILITY] = { 976 .type = MSR_FEATURE_WORD, 977 .feat_names = { 978 NULL, NULL, NULL, NULL, 979 NULL, "split-lock-detect", NULL, NULL, 980 NULL, NULL, NULL, NULL, 981 NULL, NULL, NULL, NULL, 982 NULL, NULL, NULL, NULL, 983 NULL, NULL, NULL, NULL, 984 NULL, NULL, NULL, NULL, 985 NULL, NULL, NULL, NULL, 986 }, 987 .msr = { 988 .index = MSR_IA32_CORE_CAPABILITY, 989 }, 990 }, 991 [FEAT_PERF_CAPABILITIES] = { 992 .type = MSR_FEATURE_WORD, 993 .feat_names = { 994 NULL, NULL, NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, "full-width-write", NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 NULL, NULL, NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 }, 1003 .msr = { 1004 .index = MSR_IA32_PERF_CAPABILITIES, 1005 }, 1006 }, 1007 1008 [FEAT_VMX_PROCBASED_CTLS] = { 1009 .type = MSR_FEATURE_WORD, 1010 .feat_names = { 1011 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1012 NULL, NULL, NULL, "vmx-hlt-exit", 1013 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1014 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1015 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1016 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1017 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1018 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1019 }, 1020 .msr = { 1021 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1022 } 1023 }, 1024 1025 [FEAT_VMX_SECONDARY_CTLS] = { 1026 .type = MSR_FEATURE_WORD, 1027 .feat_names = { 1028 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1029 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1030 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1031 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1032 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1033 "vmx-xsaves", NULL, NULL, NULL, 1034 NULL, "vmx-tsc-scaling", NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 }, 1037 .msr = { 1038 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1039 } 1040 }, 1041 1042 [FEAT_VMX_PINBASED_CTLS] = { 1043 .type = MSR_FEATURE_WORD, 1044 .feat_names = { 1045 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1046 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 }, 1054 .msr = { 1055 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1056 } 1057 }, 1058 1059 [FEAT_VMX_EXIT_CTLS] = { 1060 .type = MSR_FEATURE_WORD, 1061 /* 1062 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1063 * the LM CPUID bit. 1064 */ 1065 .feat_names = { 1066 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1067 NULL, NULL, NULL, NULL, 1068 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1069 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1070 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1071 "vmx-exit-save-efer", "vmx-exit-load-efer", 1072 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1073 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1074 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1075 }, 1076 .msr = { 1077 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1078 } 1079 }, 1080 1081 [FEAT_VMX_ENTRY_CTLS] = { 1082 .type = MSR_FEATURE_WORD, 1083 .feat_names = { 1084 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1085 NULL, NULL, NULL, NULL, 1086 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1087 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1088 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1089 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1090 NULL, NULL, NULL, NULL, 1091 NULL, NULL, NULL, NULL, 1092 }, 1093 .msr = { 1094 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1095 } 1096 }, 1097 1098 [FEAT_VMX_MISC] = { 1099 .type = MSR_FEATURE_WORD, 1100 .feat_names = { 1101 NULL, NULL, NULL, NULL, 1102 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1103 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1104 NULL, NULL, NULL, NULL, 1105 NULL, NULL, NULL, NULL, 1106 NULL, NULL, NULL, NULL, 1107 NULL, NULL, NULL, NULL, 1108 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1109 }, 1110 .msr = { 1111 .index = MSR_IA32_VMX_MISC, 1112 } 1113 }, 1114 1115 [FEAT_VMX_EPT_VPID_CAPS] = { 1116 .type = MSR_FEATURE_WORD, 1117 .feat_names = { 1118 "vmx-ept-execonly", NULL, NULL, NULL, 1119 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1120 NULL, NULL, NULL, NULL, 1121 NULL, NULL, NULL, NULL, 1122 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1123 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1124 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1125 NULL, NULL, NULL, NULL, 1126 "vmx-invvpid", NULL, NULL, NULL, 1127 NULL, NULL, NULL, NULL, 1128 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1129 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1130 NULL, NULL, NULL, NULL, 1131 NULL, NULL, NULL, NULL, 1132 NULL, NULL, NULL, NULL, 1133 NULL, NULL, NULL, NULL, 1134 NULL, NULL, NULL, NULL, 1135 }, 1136 .msr = { 1137 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1138 } 1139 }, 1140 1141 [FEAT_VMX_BASIC] = { 1142 .type = MSR_FEATURE_WORD, 1143 .feat_names = { 1144 [54] = "vmx-ins-outs", 1145 [55] = "vmx-true-ctls", 1146 }, 1147 .msr = { 1148 .index = MSR_IA32_VMX_BASIC, 1149 }, 1150 /* Just to be safe - we don't support setting the MSEG version field. */ 1151 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1152 }, 1153 1154 [FEAT_VMX_VMFUNC] = { 1155 .type = MSR_FEATURE_WORD, 1156 .feat_names = { 1157 [0] = "vmx-eptp-switching", 1158 }, 1159 .msr = { 1160 .index = MSR_IA32_VMX_VMFUNC, 1161 } 1162 }, 1163 1164 [FEAT_14_0_ECX] = { 1165 .type = CPUID_FEATURE_WORD, 1166 .feat_names = { 1167 NULL, NULL, NULL, NULL, 1168 NULL, NULL, NULL, NULL, 1169 NULL, NULL, NULL, NULL, 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, "intel-pt-lip", 1175 }, 1176 .cpuid = { 1177 .eax = 0x14, 1178 .needs_ecx = true, .ecx = 0, 1179 .reg = R_ECX, 1180 }, 1181 .tcg_features = TCG_14_0_ECX_FEATURES, 1182 }, 1183 1184 }; 1185 1186 typedef struct FeatureMask { 1187 FeatureWord index; 1188 uint64_t mask; 1189 } FeatureMask; 1190 1191 typedef struct FeatureDep { 1192 FeatureMask from, to; 1193 } FeatureDep; 1194 1195 static FeatureDep feature_dependencies[] = { 1196 { 1197 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1198 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1199 }, 1200 { 1201 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1202 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1203 }, 1204 { 1205 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1206 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1207 }, 1208 { 1209 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1210 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1211 }, 1212 { 1213 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1214 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1215 }, 1216 { 1217 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1218 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1219 }, 1220 { 1221 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1222 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1223 }, 1224 { 1225 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1226 .to = { FEAT_VMX_MISC, ~0ull }, 1227 }, 1228 { 1229 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1230 .to = { FEAT_VMX_BASIC, ~0ull }, 1231 }, 1232 { 1233 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1234 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1235 }, 1236 { 1237 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1238 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1239 }, 1240 { 1241 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1242 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1243 }, 1244 { 1245 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1246 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1247 }, 1248 { 1249 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1250 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1251 }, 1252 { 1253 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1254 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1255 }, 1256 { 1257 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1258 .to = { FEAT_14_0_ECX, ~0ull }, 1259 }, 1260 { 1261 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1262 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1263 }, 1264 { 1265 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1266 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1267 }, 1268 { 1269 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1270 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1271 }, 1272 { 1273 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1274 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1275 }, 1276 { 1277 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1278 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1279 }, 1280 { 1281 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1282 .to = { FEAT_SVM, ~0ull }, 1283 }, 1284 }; 1285 1286 typedef struct X86RegisterInfo32 { 1287 /* Name of register */ 1288 const char *name; 1289 /* QAPI enum value register */ 1290 X86CPURegister32 qapi_enum; 1291 } X86RegisterInfo32; 1292 1293 #define REGISTER(reg) \ 1294 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1295 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1296 REGISTER(EAX), 1297 REGISTER(ECX), 1298 REGISTER(EDX), 1299 REGISTER(EBX), 1300 REGISTER(ESP), 1301 REGISTER(EBP), 1302 REGISTER(ESI), 1303 REGISTER(EDI), 1304 }; 1305 #undef REGISTER 1306 1307 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1308 [XSTATE_FP_BIT] = { 1309 /* x87 FP state component is always enabled if XSAVE is supported */ 1310 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1311 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1312 }, 1313 [XSTATE_SSE_BIT] = { 1314 /* SSE state component is always enabled if XSAVE is supported */ 1315 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1316 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1317 }, 1318 [XSTATE_YMM_BIT] = 1319 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1320 .size = sizeof(XSaveAVX) }, 1321 [XSTATE_BNDREGS_BIT] = 1322 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1323 .size = sizeof(XSaveBNDREG) }, 1324 [XSTATE_BNDCSR_BIT] = 1325 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1326 .size = sizeof(XSaveBNDCSR) }, 1327 [XSTATE_OPMASK_BIT] = 1328 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1329 .size = sizeof(XSaveOpmask) }, 1330 [XSTATE_ZMM_Hi256_BIT] = 1331 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1332 .size = sizeof(XSaveZMM_Hi256) }, 1333 [XSTATE_Hi16_ZMM_BIT] = 1334 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1335 .size = sizeof(XSaveHi16_ZMM) }, 1336 [XSTATE_PKRU_BIT] = 1337 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1338 .size = sizeof(XSavePKRU) }, 1339 }; 1340 1341 static uint32_t xsave_area_size(uint64_t mask) 1342 { 1343 int i; 1344 uint64_t ret = 0; 1345 1346 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1347 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 1348 if ((mask >> i) & 1) { 1349 ret = MAX(ret, esa->offset + esa->size); 1350 } 1351 } 1352 return ret; 1353 } 1354 1355 static inline bool accel_uses_host_cpuid(void) 1356 { 1357 return kvm_enabled() || hvf_enabled(); 1358 } 1359 1360 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) 1361 { 1362 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | 1363 cpu->env.features[FEAT_XSAVE_COMP_LO]; 1364 } 1365 1366 /* Return name of 32-bit register, from a R_* constant */ 1367 static const char *get_register_name_32(unsigned int reg) 1368 { 1369 if (reg >= CPU_NB_REGS32) { 1370 return NULL; 1371 } 1372 return x86_reg_info_32[reg].name; 1373 } 1374 1375 /* 1376 * Returns the set of feature flags that are supported and migratable by 1377 * QEMU, for a given FeatureWord. 1378 */ 1379 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1380 { 1381 FeatureWordInfo *wi = &feature_word_info[w]; 1382 uint64_t r = 0; 1383 int i; 1384 1385 for (i = 0; i < 64; i++) { 1386 uint64_t f = 1ULL << i; 1387 1388 /* If the feature name is known, it is implicitly considered migratable, 1389 * unless it is explicitly set in unmigratable_flags */ 1390 if ((wi->migratable_flags & f) || 1391 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1392 r |= f; 1393 } 1394 } 1395 return r; 1396 } 1397 1398 void host_cpuid(uint32_t function, uint32_t count, 1399 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1400 { 1401 uint32_t vec[4]; 1402 1403 #ifdef __x86_64__ 1404 asm volatile("cpuid" 1405 : "=a"(vec[0]), "=b"(vec[1]), 1406 "=c"(vec[2]), "=d"(vec[3]) 1407 : "0"(function), "c"(count) : "cc"); 1408 #elif defined(__i386__) 1409 asm volatile("pusha \n\t" 1410 "cpuid \n\t" 1411 "mov %%eax, 0(%2) \n\t" 1412 "mov %%ebx, 4(%2) \n\t" 1413 "mov %%ecx, 8(%2) \n\t" 1414 "mov %%edx, 12(%2) \n\t" 1415 "popa" 1416 : : "a"(function), "c"(count), "S"(vec) 1417 : "memory", "cc"); 1418 #else 1419 abort(); 1420 #endif 1421 1422 if (eax) 1423 *eax = vec[0]; 1424 if (ebx) 1425 *ebx = vec[1]; 1426 if (ecx) 1427 *ecx = vec[2]; 1428 if (edx) 1429 *edx = vec[3]; 1430 } 1431 1432 /* CPU class name definitions: */ 1433 1434 /* Return type name for a given CPU model name 1435 * Caller is responsible for freeing the returned string. 1436 */ 1437 static char *x86_cpu_type_name(const char *model_name) 1438 { 1439 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1440 } 1441 1442 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1443 { 1444 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1445 return object_class_by_name(typename); 1446 } 1447 1448 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1449 { 1450 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1451 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1452 return g_strndup(class_name, 1453 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1454 } 1455 1456 typedef struct X86CPUVersionDefinition { 1457 X86CPUVersion version; 1458 const char *alias; 1459 const char *note; 1460 PropValue *props; 1461 } X86CPUVersionDefinition; 1462 1463 /* Base definition for a CPU model */ 1464 typedef struct X86CPUDefinition { 1465 const char *name; 1466 uint32_t level; 1467 uint32_t xlevel; 1468 /* vendor is zero-terminated, 12 character ASCII string */ 1469 char vendor[CPUID_VENDOR_SZ + 1]; 1470 int family; 1471 int model; 1472 int stepping; 1473 FeatureWordArray features; 1474 const char *model_id; 1475 const CPUCaches *const cache_info; 1476 /* 1477 * Definitions for alternative versions of CPU model. 1478 * List is terminated by item with version == 0. 1479 * If NULL, version 1 will be registered automatically. 1480 */ 1481 const X86CPUVersionDefinition *versions; 1482 const char *deprecation_note; 1483 } X86CPUDefinition; 1484 1485 /* Reference to a specific CPU model version */ 1486 struct X86CPUModel { 1487 /* Base CPU definition */ 1488 const X86CPUDefinition *cpudef; 1489 /* CPU model version */ 1490 X86CPUVersion version; 1491 const char *note; 1492 /* 1493 * If true, this is an alias CPU model. 1494 * This matters only for "-cpu help" and query-cpu-definitions 1495 */ 1496 bool is_alias; 1497 }; 1498 1499 /* Get full model name for CPU version */ 1500 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1501 X86CPUVersion version) 1502 { 1503 assert(version > 0); 1504 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1505 } 1506 1507 static const X86CPUVersionDefinition * 1508 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1509 { 1510 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1511 static const X86CPUVersionDefinition default_version_list[] = { 1512 { 1 }, 1513 { /* end of list */ } 1514 }; 1515 1516 return def->versions ?: default_version_list; 1517 } 1518 1519 static const CPUCaches epyc_cache_info = { 1520 .l1d_cache = &(CPUCacheInfo) { 1521 .type = DATA_CACHE, 1522 .level = 1, 1523 .size = 32 * KiB, 1524 .line_size = 64, 1525 .associativity = 8, 1526 .partitions = 1, 1527 .sets = 64, 1528 .lines_per_tag = 1, 1529 .self_init = 1, 1530 .no_invd_sharing = true, 1531 }, 1532 .l1i_cache = &(CPUCacheInfo) { 1533 .type = INSTRUCTION_CACHE, 1534 .level = 1, 1535 .size = 64 * KiB, 1536 .line_size = 64, 1537 .associativity = 4, 1538 .partitions = 1, 1539 .sets = 256, 1540 .lines_per_tag = 1, 1541 .self_init = 1, 1542 .no_invd_sharing = true, 1543 }, 1544 .l2_cache = &(CPUCacheInfo) { 1545 .type = UNIFIED_CACHE, 1546 .level = 2, 1547 .size = 512 * KiB, 1548 .line_size = 64, 1549 .associativity = 8, 1550 .partitions = 1, 1551 .sets = 1024, 1552 .lines_per_tag = 1, 1553 }, 1554 .l3_cache = &(CPUCacheInfo) { 1555 .type = UNIFIED_CACHE, 1556 .level = 3, 1557 .size = 8 * MiB, 1558 .line_size = 64, 1559 .associativity = 16, 1560 .partitions = 1, 1561 .sets = 8192, 1562 .lines_per_tag = 1, 1563 .self_init = true, 1564 .inclusive = true, 1565 .complex_indexing = true, 1566 }, 1567 }; 1568 1569 static const CPUCaches epyc_rome_cache_info = { 1570 .l1d_cache = &(CPUCacheInfo) { 1571 .type = DATA_CACHE, 1572 .level = 1, 1573 .size = 32 * KiB, 1574 .line_size = 64, 1575 .associativity = 8, 1576 .partitions = 1, 1577 .sets = 64, 1578 .lines_per_tag = 1, 1579 .self_init = 1, 1580 .no_invd_sharing = true, 1581 }, 1582 .l1i_cache = &(CPUCacheInfo) { 1583 .type = INSTRUCTION_CACHE, 1584 .level = 1, 1585 .size = 32 * KiB, 1586 .line_size = 64, 1587 .associativity = 8, 1588 .partitions = 1, 1589 .sets = 64, 1590 .lines_per_tag = 1, 1591 .self_init = 1, 1592 .no_invd_sharing = true, 1593 }, 1594 .l2_cache = &(CPUCacheInfo) { 1595 .type = UNIFIED_CACHE, 1596 .level = 2, 1597 .size = 512 * KiB, 1598 .line_size = 64, 1599 .associativity = 8, 1600 .partitions = 1, 1601 .sets = 1024, 1602 .lines_per_tag = 1, 1603 }, 1604 .l3_cache = &(CPUCacheInfo) { 1605 .type = UNIFIED_CACHE, 1606 .level = 3, 1607 .size = 16 * MiB, 1608 .line_size = 64, 1609 .associativity = 16, 1610 .partitions = 1, 1611 .sets = 16384, 1612 .lines_per_tag = 1, 1613 .self_init = true, 1614 .inclusive = true, 1615 .complex_indexing = true, 1616 }, 1617 }; 1618 1619 static const CPUCaches epyc_milan_cache_info = { 1620 .l1d_cache = &(CPUCacheInfo) { 1621 .type = DATA_CACHE, 1622 .level = 1, 1623 .size = 32 * KiB, 1624 .line_size = 64, 1625 .associativity = 8, 1626 .partitions = 1, 1627 .sets = 64, 1628 .lines_per_tag = 1, 1629 .self_init = 1, 1630 .no_invd_sharing = true, 1631 }, 1632 .l1i_cache = &(CPUCacheInfo) { 1633 .type = INSTRUCTION_CACHE, 1634 .level = 1, 1635 .size = 32 * KiB, 1636 .line_size = 64, 1637 .associativity = 8, 1638 .partitions = 1, 1639 .sets = 64, 1640 .lines_per_tag = 1, 1641 .self_init = 1, 1642 .no_invd_sharing = true, 1643 }, 1644 .l2_cache = &(CPUCacheInfo) { 1645 .type = UNIFIED_CACHE, 1646 .level = 2, 1647 .size = 512 * KiB, 1648 .line_size = 64, 1649 .associativity = 8, 1650 .partitions = 1, 1651 .sets = 1024, 1652 .lines_per_tag = 1, 1653 }, 1654 .l3_cache = &(CPUCacheInfo) { 1655 .type = UNIFIED_CACHE, 1656 .level = 3, 1657 .size = 32 * MiB, 1658 .line_size = 64, 1659 .associativity = 16, 1660 .partitions = 1, 1661 .sets = 32768, 1662 .lines_per_tag = 1, 1663 .self_init = true, 1664 .inclusive = true, 1665 .complex_indexing = true, 1666 }, 1667 }; 1668 1669 /* The following VMX features are not supported by KVM and are left out in the 1670 * CPU definitions: 1671 * 1672 * Dual-monitor support (all processors) 1673 * Entry to SMM 1674 * Deactivate dual-monitor treatment 1675 * Number of CR3-target values 1676 * Shutdown activity state 1677 * Wait-for-SIPI activity state 1678 * PAUSE-loop exiting (Westmere and newer) 1679 * EPT-violation #VE (Broadwell and newer) 1680 * Inject event with insn length=0 (Skylake and newer) 1681 * Conceal non-root operation from PT 1682 * Conceal VM exits from PT 1683 * Conceal VM entries from PT 1684 * Enable ENCLS exiting 1685 * Mode-based execute control (XS/XU) 1686 s TSC scaling (Skylake Server and newer) 1687 * GPA translation for PT (IceLake and newer) 1688 * User wait and pause 1689 * ENCLV exiting 1690 * Load IA32_RTIT_CTL 1691 * Clear IA32_RTIT_CTL 1692 * Advanced VM-exit information for EPT violations 1693 * Sub-page write permissions 1694 * PT in VMX operation 1695 */ 1696 1697 static const X86CPUDefinition builtin_x86_defs[] = { 1698 { 1699 .name = "qemu64", 1700 .level = 0xd, 1701 .vendor = CPUID_VENDOR_AMD, 1702 .family = 15, 1703 .model = 107, 1704 .stepping = 1, 1705 .features[FEAT_1_EDX] = 1706 PPRO_FEATURES | 1707 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1708 CPUID_PSE36, 1709 .features[FEAT_1_ECX] = 1710 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1711 .features[FEAT_8000_0001_EDX] = 1712 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1713 .features[FEAT_8000_0001_ECX] = 1714 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1715 .xlevel = 0x8000000A, 1716 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1717 }, 1718 { 1719 .name = "phenom", 1720 .level = 5, 1721 .vendor = CPUID_VENDOR_AMD, 1722 .family = 16, 1723 .model = 2, 1724 .stepping = 3, 1725 /* Missing: CPUID_HT */ 1726 .features[FEAT_1_EDX] = 1727 PPRO_FEATURES | 1728 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1729 CPUID_PSE36 | CPUID_VME, 1730 .features[FEAT_1_ECX] = 1731 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1732 CPUID_EXT_POPCNT, 1733 .features[FEAT_8000_0001_EDX] = 1734 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1735 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1736 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1737 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1738 CPUID_EXT3_CR8LEG, 1739 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1740 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1741 .features[FEAT_8000_0001_ECX] = 1742 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1743 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1744 /* Missing: CPUID_SVM_LBRV */ 1745 .features[FEAT_SVM] = 1746 CPUID_SVM_NPT, 1747 .xlevel = 0x8000001A, 1748 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1749 }, 1750 { 1751 .name = "core2duo", 1752 .level = 10, 1753 .vendor = CPUID_VENDOR_INTEL, 1754 .family = 6, 1755 .model = 15, 1756 .stepping = 11, 1757 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1758 .features[FEAT_1_EDX] = 1759 PPRO_FEATURES | 1760 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1761 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1762 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1763 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1764 .features[FEAT_1_ECX] = 1765 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1766 CPUID_EXT_CX16, 1767 .features[FEAT_8000_0001_EDX] = 1768 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1769 .features[FEAT_8000_0001_ECX] = 1770 CPUID_EXT3_LAHF_LM, 1771 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1772 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1773 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1774 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1775 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1776 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1777 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1778 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1779 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1780 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1781 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1782 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1783 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1784 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 1785 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 1786 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 1787 .features[FEAT_VMX_SECONDARY_CTLS] = 1788 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 1789 .xlevel = 0x80000008, 1790 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1791 }, 1792 { 1793 .name = "kvm64", 1794 .level = 0xd, 1795 .vendor = CPUID_VENDOR_INTEL, 1796 .family = 15, 1797 .model = 6, 1798 .stepping = 1, 1799 /* Missing: CPUID_HT */ 1800 .features[FEAT_1_EDX] = 1801 PPRO_FEATURES | CPUID_VME | 1802 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1803 CPUID_PSE36, 1804 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1805 .features[FEAT_1_ECX] = 1806 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1807 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1808 .features[FEAT_8000_0001_EDX] = 1809 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1810 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1811 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1812 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1813 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1814 .features[FEAT_8000_0001_ECX] = 1815 0, 1816 /* VMX features from Cedar Mill/Prescott */ 1817 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1818 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1819 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1820 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1821 VMX_PIN_BASED_NMI_EXITING, 1822 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1823 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1824 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1825 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1826 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1827 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1828 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1829 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 1830 .xlevel = 0x80000008, 1831 .model_id = "Common KVM processor" 1832 }, 1833 { 1834 .name = "qemu32", 1835 .level = 4, 1836 .vendor = CPUID_VENDOR_INTEL, 1837 .family = 6, 1838 .model = 6, 1839 .stepping = 3, 1840 .features[FEAT_1_EDX] = 1841 PPRO_FEATURES, 1842 .features[FEAT_1_ECX] = 1843 CPUID_EXT_SSE3, 1844 .xlevel = 0x80000004, 1845 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1846 }, 1847 { 1848 .name = "kvm32", 1849 .level = 5, 1850 .vendor = CPUID_VENDOR_INTEL, 1851 .family = 15, 1852 .model = 6, 1853 .stepping = 1, 1854 .features[FEAT_1_EDX] = 1855 PPRO_FEATURES | CPUID_VME | 1856 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 1857 .features[FEAT_1_ECX] = 1858 CPUID_EXT_SSE3, 1859 .features[FEAT_8000_0001_ECX] = 1860 0, 1861 /* VMX features from Yonah */ 1862 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1863 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1864 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1865 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1866 VMX_PIN_BASED_NMI_EXITING, 1867 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1868 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1869 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1870 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1871 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 1872 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 1873 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 1874 .xlevel = 0x80000008, 1875 .model_id = "Common 32-bit KVM processor" 1876 }, 1877 { 1878 .name = "coreduo", 1879 .level = 10, 1880 .vendor = CPUID_VENDOR_INTEL, 1881 .family = 6, 1882 .model = 14, 1883 .stepping = 8, 1884 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1885 .features[FEAT_1_EDX] = 1886 PPRO_FEATURES | CPUID_VME | 1887 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 1888 CPUID_SS, 1889 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 1890 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1891 .features[FEAT_1_ECX] = 1892 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 1893 .features[FEAT_8000_0001_EDX] = 1894 CPUID_EXT2_NX, 1895 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1896 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1897 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1898 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1899 VMX_PIN_BASED_NMI_EXITING, 1900 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1901 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1902 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1903 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1904 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 1905 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 1906 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 1907 .xlevel = 0x80000008, 1908 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 1909 }, 1910 { 1911 .name = "486", 1912 .level = 1, 1913 .vendor = CPUID_VENDOR_INTEL, 1914 .family = 4, 1915 .model = 8, 1916 .stepping = 0, 1917 .features[FEAT_1_EDX] = 1918 I486_FEATURES, 1919 .xlevel = 0, 1920 .model_id = "", 1921 }, 1922 { 1923 .name = "pentium", 1924 .level = 1, 1925 .vendor = CPUID_VENDOR_INTEL, 1926 .family = 5, 1927 .model = 4, 1928 .stepping = 3, 1929 .features[FEAT_1_EDX] = 1930 PENTIUM_FEATURES, 1931 .xlevel = 0, 1932 .model_id = "", 1933 }, 1934 { 1935 .name = "pentium2", 1936 .level = 2, 1937 .vendor = CPUID_VENDOR_INTEL, 1938 .family = 6, 1939 .model = 5, 1940 .stepping = 2, 1941 .features[FEAT_1_EDX] = 1942 PENTIUM2_FEATURES, 1943 .xlevel = 0, 1944 .model_id = "", 1945 }, 1946 { 1947 .name = "pentium3", 1948 .level = 3, 1949 .vendor = CPUID_VENDOR_INTEL, 1950 .family = 6, 1951 .model = 7, 1952 .stepping = 3, 1953 .features[FEAT_1_EDX] = 1954 PENTIUM3_FEATURES, 1955 .xlevel = 0, 1956 .model_id = "", 1957 }, 1958 { 1959 .name = "athlon", 1960 .level = 2, 1961 .vendor = CPUID_VENDOR_AMD, 1962 .family = 6, 1963 .model = 2, 1964 .stepping = 3, 1965 .features[FEAT_1_EDX] = 1966 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 1967 CPUID_MCA, 1968 .features[FEAT_8000_0001_EDX] = 1969 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 1970 .xlevel = 0x80000008, 1971 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1972 }, 1973 { 1974 .name = "n270", 1975 .level = 10, 1976 .vendor = CPUID_VENDOR_INTEL, 1977 .family = 6, 1978 .model = 28, 1979 .stepping = 2, 1980 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1981 .features[FEAT_1_EDX] = 1982 PPRO_FEATURES | 1983 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 1984 CPUID_ACPI | CPUID_SS, 1985 /* Some CPUs got no CPUID_SEP */ 1986 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 1987 * CPUID_EXT_XTPR */ 1988 .features[FEAT_1_ECX] = 1989 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1990 CPUID_EXT_MOVBE, 1991 .features[FEAT_8000_0001_EDX] = 1992 CPUID_EXT2_NX, 1993 .features[FEAT_8000_0001_ECX] = 1994 CPUID_EXT3_LAHF_LM, 1995 .xlevel = 0x80000008, 1996 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 1997 }, 1998 { 1999 .name = "Conroe", 2000 .level = 10, 2001 .vendor = CPUID_VENDOR_INTEL, 2002 .family = 6, 2003 .model = 15, 2004 .stepping = 3, 2005 .features[FEAT_1_EDX] = 2006 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2007 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2008 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2009 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2010 CPUID_DE | CPUID_FP87, 2011 .features[FEAT_1_ECX] = 2012 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2013 .features[FEAT_8000_0001_EDX] = 2014 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2015 .features[FEAT_8000_0001_ECX] = 2016 CPUID_EXT3_LAHF_LM, 2017 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2018 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2019 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2020 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2021 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2022 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2023 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2024 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2025 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2026 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2027 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2028 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2029 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2030 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2031 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2032 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2033 .features[FEAT_VMX_SECONDARY_CTLS] = 2034 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2035 .xlevel = 0x80000008, 2036 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2037 }, 2038 { 2039 .name = "Penryn", 2040 .level = 10, 2041 .vendor = CPUID_VENDOR_INTEL, 2042 .family = 6, 2043 .model = 23, 2044 .stepping = 3, 2045 .features[FEAT_1_EDX] = 2046 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2047 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2048 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2049 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2050 CPUID_DE | CPUID_FP87, 2051 .features[FEAT_1_ECX] = 2052 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2053 CPUID_EXT_SSE3, 2054 .features[FEAT_8000_0001_EDX] = 2055 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2056 .features[FEAT_8000_0001_ECX] = 2057 CPUID_EXT3_LAHF_LM, 2058 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2059 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2060 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2061 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2062 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2063 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2064 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2065 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2066 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2067 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2068 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2069 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2070 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2071 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2072 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2073 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2074 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2075 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2076 .features[FEAT_VMX_SECONDARY_CTLS] = 2077 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2078 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2079 .xlevel = 0x80000008, 2080 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2081 }, 2082 { 2083 .name = "Nehalem", 2084 .level = 11, 2085 .vendor = CPUID_VENDOR_INTEL, 2086 .family = 6, 2087 .model = 26, 2088 .stepping = 3, 2089 .features[FEAT_1_EDX] = 2090 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2091 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2092 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2093 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2094 CPUID_DE | CPUID_FP87, 2095 .features[FEAT_1_ECX] = 2096 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2097 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2098 .features[FEAT_8000_0001_EDX] = 2099 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2100 .features[FEAT_8000_0001_ECX] = 2101 CPUID_EXT3_LAHF_LM, 2102 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2103 MSR_VMX_BASIC_TRUE_CTLS, 2104 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2105 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2106 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2107 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2108 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2109 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2110 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2111 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2112 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2113 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2114 .features[FEAT_VMX_EXIT_CTLS] = 2115 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2116 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2117 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2118 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2119 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2120 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2121 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2122 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2123 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2124 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2125 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2126 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2127 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2128 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2129 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2130 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2131 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2132 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2133 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2134 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2135 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2136 .features[FEAT_VMX_SECONDARY_CTLS] = 2137 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2138 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2139 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2140 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2141 VMX_SECONDARY_EXEC_ENABLE_VPID, 2142 .xlevel = 0x80000008, 2143 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2144 .versions = (X86CPUVersionDefinition[]) { 2145 { .version = 1 }, 2146 { 2147 .version = 2, 2148 .alias = "Nehalem-IBRS", 2149 .props = (PropValue[]) { 2150 { "spec-ctrl", "on" }, 2151 { "model-id", 2152 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2153 { /* end of list */ } 2154 } 2155 }, 2156 { /* end of list */ } 2157 } 2158 }, 2159 { 2160 .name = "Westmere", 2161 .level = 11, 2162 .vendor = CPUID_VENDOR_INTEL, 2163 .family = 6, 2164 .model = 44, 2165 .stepping = 1, 2166 .features[FEAT_1_EDX] = 2167 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2168 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2169 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2170 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2171 CPUID_DE | CPUID_FP87, 2172 .features[FEAT_1_ECX] = 2173 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2174 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2175 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2176 .features[FEAT_8000_0001_EDX] = 2177 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2178 .features[FEAT_8000_0001_ECX] = 2179 CPUID_EXT3_LAHF_LM, 2180 .features[FEAT_6_EAX] = 2181 CPUID_6_EAX_ARAT, 2182 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2183 MSR_VMX_BASIC_TRUE_CTLS, 2184 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2185 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2186 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2187 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2188 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2189 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2190 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2191 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2192 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2193 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2194 .features[FEAT_VMX_EXIT_CTLS] = 2195 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2196 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2197 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2198 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2199 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2200 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2201 MSR_VMX_MISC_STORE_LMA, 2202 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2203 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2204 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2205 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2206 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2207 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2208 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2209 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2210 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2211 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2212 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2213 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2214 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2215 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2216 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2217 .features[FEAT_VMX_SECONDARY_CTLS] = 2218 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2219 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2220 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2221 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2222 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2223 .xlevel = 0x80000008, 2224 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2225 .versions = (X86CPUVersionDefinition[]) { 2226 { .version = 1 }, 2227 { 2228 .version = 2, 2229 .alias = "Westmere-IBRS", 2230 .props = (PropValue[]) { 2231 { "spec-ctrl", "on" }, 2232 { "model-id", 2233 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2234 { /* end of list */ } 2235 } 2236 }, 2237 { /* end of list */ } 2238 } 2239 }, 2240 { 2241 .name = "SandyBridge", 2242 .level = 0xd, 2243 .vendor = CPUID_VENDOR_INTEL, 2244 .family = 6, 2245 .model = 42, 2246 .stepping = 1, 2247 .features[FEAT_1_EDX] = 2248 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2249 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2250 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2251 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2252 CPUID_DE | CPUID_FP87, 2253 .features[FEAT_1_ECX] = 2254 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2255 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2256 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2257 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2258 CPUID_EXT_SSE3, 2259 .features[FEAT_8000_0001_EDX] = 2260 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2261 CPUID_EXT2_SYSCALL, 2262 .features[FEAT_8000_0001_ECX] = 2263 CPUID_EXT3_LAHF_LM, 2264 .features[FEAT_XSAVE] = 2265 CPUID_XSAVE_XSAVEOPT, 2266 .features[FEAT_6_EAX] = 2267 CPUID_6_EAX_ARAT, 2268 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2269 MSR_VMX_BASIC_TRUE_CTLS, 2270 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2271 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2272 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2273 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2274 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2275 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2276 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2277 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2278 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2279 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2280 .features[FEAT_VMX_EXIT_CTLS] = 2281 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2282 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2283 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2284 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2285 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2286 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2287 MSR_VMX_MISC_STORE_LMA, 2288 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2289 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2290 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2291 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2292 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2293 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2294 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2295 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2296 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2297 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2298 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2299 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2300 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2301 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2302 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2303 .features[FEAT_VMX_SECONDARY_CTLS] = 2304 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2305 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2306 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2307 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2308 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2309 .xlevel = 0x80000008, 2310 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2311 .versions = (X86CPUVersionDefinition[]) { 2312 { .version = 1 }, 2313 { 2314 .version = 2, 2315 .alias = "SandyBridge-IBRS", 2316 .props = (PropValue[]) { 2317 { "spec-ctrl", "on" }, 2318 { "model-id", 2319 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2320 { /* end of list */ } 2321 } 2322 }, 2323 { /* end of list */ } 2324 } 2325 }, 2326 { 2327 .name = "IvyBridge", 2328 .level = 0xd, 2329 .vendor = CPUID_VENDOR_INTEL, 2330 .family = 6, 2331 .model = 58, 2332 .stepping = 9, 2333 .features[FEAT_1_EDX] = 2334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2338 CPUID_DE | CPUID_FP87, 2339 .features[FEAT_1_ECX] = 2340 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2341 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2342 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2343 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2344 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2345 .features[FEAT_7_0_EBX] = 2346 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2347 CPUID_7_0_EBX_ERMS, 2348 .features[FEAT_8000_0001_EDX] = 2349 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2350 CPUID_EXT2_SYSCALL, 2351 .features[FEAT_8000_0001_ECX] = 2352 CPUID_EXT3_LAHF_LM, 2353 .features[FEAT_XSAVE] = 2354 CPUID_XSAVE_XSAVEOPT, 2355 .features[FEAT_6_EAX] = 2356 CPUID_6_EAX_ARAT, 2357 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2358 MSR_VMX_BASIC_TRUE_CTLS, 2359 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2360 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2361 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2362 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2363 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2364 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2365 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2366 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2367 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2368 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2369 .features[FEAT_VMX_EXIT_CTLS] = 2370 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2371 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2372 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2373 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2374 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2375 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2376 MSR_VMX_MISC_STORE_LMA, 2377 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2378 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2379 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2380 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2381 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2382 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2383 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2384 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2385 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2386 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2387 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2388 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2389 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2390 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2391 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2392 .features[FEAT_VMX_SECONDARY_CTLS] = 2393 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2394 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2395 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2396 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2397 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2398 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2399 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2400 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2401 .xlevel = 0x80000008, 2402 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2403 .versions = (X86CPUVersionDefinition[]) { 2404 { .version = 1 }, 2405 { 2406 .version = 2, 2407 .alias = "IvyBridge-IBRS", 2408 .props = (PropValue[]) { 2409 { "spec-ctrl", "on" }, 2410 { "model-id", 2411 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2412 { /* end of list */ } 2413 } 2414 }, 2415 { /* end of list */ } 2416 } 2417 }, 2418 { 2419 .name = "Haswell", 2420 .level = 0xd, 2421 .vendor = CPUID_VENDOR_INTEL, 2422 .family = 6, 2423 .model = 60, 2424 .stepping = 4, 2425 .features[FEAT_1_EDX] = 2426 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2427 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2428 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2429 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2430 CPUID_DE | CPUID_FP87, 2431 .features[FEAT_1_ECX] = 2432 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2433 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2434 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2435 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2436 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2437 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2438 .features[FEAT_8000_0001_EDX] = 2439 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2440 CPUID_EXT2_SYSCALL, 2441 .features[FEAT_8000_0001_ECX] = 2442 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2443 .features[FEAT_7_0_EBX] = 2444 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2445 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2446 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2447 CPUID_7_0_EBX_RTM, 2448 .features[FEAT_XSAVE] = 2449 CPUID_XSAVE_XSAVEOPT, 2450 .features[FEAT_6_EAX] = 2451 CPUID_6_EAX_ARAT, 2452 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2453 MSR_VMX_BASIC_TRUE_CTLS, 2454 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2455 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2456 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2457 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2458 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2459 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2460 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2461 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2462 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2463 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2464 .features[FEAT_VMX_EXIT_CTLS] = 2465 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2466 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2467 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2468 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2469 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2470 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2471 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2472 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2473 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2474 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2475 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2476 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2477 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2478 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2479 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2480 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2481 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2482 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2483 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2484 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2485 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2486 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2487 .features[FEAT_VMX_SECONDARY_CTLS] = 2488 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2489 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2490 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2491 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2492 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2493 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2494 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2495 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2496 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2497 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2498 .xlevel = 0x80000008, 2499 .model_id = "Intel Core Processor (Haswell)", 2500 .versions = (X86CPUVersionDefinition[]) { 2501 { .version = 1 }, 2502 { 2503 .version = 2, 2504 .alias = "Haswell-noTSX", 2505 .props = (PropValue[]) { 2506 { "hle", "off" }, 2507 { "rtm", "off" }, 2508 { "stepping", "1" }, 2509 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2510 { /* end of list */ } 2511 }, 2512 }, 2513 { 2514 .version = 3, 2515 .alias = "Haswell-IBRS", 2516 .props = (PropValue[]) { 2517 /* Restore TSX features removed by -v2 above */ 2518 { "hle", "on" }, 2519 { "rtm", "on" }, 2520 /* 2521 * Haswell and Haswell-IBRS had stepping=4 in 2522 * QEMU 4.0 and older 2523 */ 2524 { "stepping", "4" }, 2525 { "spec-ctrl", "on" }, 2526 { "model-id", 2527 "Intel Core Processor (Haswell, IBRS)" }, 2528 { /* end of list */ } 2529 } 2530 }, 2531 { 2532 .version = 4, 2533 .alias = "Haswell-noTSX-IBRS", 2534 .props = (PropValue[]) { 2535 { "hle", "off" }, 2536 { "rtm", "off" }, 2537 /* spec-ctrl was already enabled by -v3 above */ 2538 { "stepping", "1" }, 2539 { "model-id", 2540 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2541 { /* end of list */ } 2542 } 2543 }, 2544 { /* end of list */ } 2545 } 2546 }, 2547 { 2548 .name = "Broadwell", 2549 .level = 0xd, 2550 .vendor = CPUID_VENDOR_INTEL, 2551 .family = 6, 2552 .model = 61, 2553 .stepping = 2, 2554 .features[FEAT_1_EDX] = 2555 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2556 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2557 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2558 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2559 CPUID_DE | CPUID_FP87, 2560 .features[FEAT_1_ECX] = 2561 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2562 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2563 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2564 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2565 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2566 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2567 .features[FEAT_8000_0001_EDX] = 2568 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2569 CPUID_EXT2_SYSCALL, 2570 .features[FEAT_8000_0001_ECX] = 2571 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2572 .features[FEAT_7_0_EBX] = 2573 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2574 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2575 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2576 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2577 CPUID_7_0_EBX_SMAP, 2578 .features[FEAT_XSAVE] = 2579 CPUID_XSAVE_XSAVEOPT, 2580 .features[FEAT_6_EAX] = 2581 CPUID_6_EAX_ARAT, 2582 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2583 MSR_VMX_BASIC_TRUE_CTLS, 2584 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2585 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2586 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2587 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2588 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2589 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2590 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2591 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2592 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2593 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2594 .features[FEAT_VMX_EXIT_CTLS] = 2595 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2596 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2597 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2598 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2599 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2600 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2601 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2602 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2603 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2604 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2605 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2606 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2607 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2608 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2609 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2610 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2611 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2612 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2613 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2614 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2615 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2616 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2617 .features[FEAT_VMX_SECONDARY_CTLS] = 2618 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2619 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2620 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2621 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2622 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2623 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2624 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2625 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2626 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2627 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2628 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2629 .xlevel = 0x80000008, 2630 .model_id = "Intel Core Processor (Broadwell)", 2631 .versions = (X86CPUVersionDefinition[]) { 2632 { .version = 1 }, 2633 { 2634 .version = 2, 2635 .alias = "Broadwell-noTSX", 2636 .props = (PropValue[]) { 2637 { "hle", "off" }, 2638 { "rtm", "off" }, 2639 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2640 { /* end of list */ } 2641 }, 2642 }, 2643 { 2644 .version = 3, 2645 .alias = "Broadwell-IBRS", 2646 .props = (PropValue[]) { 2647 /* Restore TSX features removed by -v2 above */ 2648 { "hle", "on" }, 2649 { "rtm", "on" }, 2650 { "spec-ctrl", "on" }, 2651 { "model-id", 2652 "Intel Core Processor (Broadwell, IBRS)" }, 2653 { /* end of list */ } 2654 } 2655 }, 2656 { 2657 .version = 4, 2658 .alias = "Broadwell-noTSX-IBRS", 2659 .props = (PropValue[]) { 2660 { "hle", "off" }, 2661 { "rtm", "off" }, 2662 /* spec-ctrl was already enabled by -v3 above */ 2663 { "model-id", 2664 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2665 { /* end of list */ } 2666 } 2667 }, 2668 { /* end of list */ } 2669 } 2670 }, 2671 { 2672 .name = "Skylake-Client", 2673 .level = 0xd, 2674 .vendor = CPUID_VENDOR_INTEL, 2675 .family = 6, 2676 .model = 94, 2677 .stepping = 3, 2678 .features[FEAT_1_EDX] = 2679 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2683 CPUID_DE | CPUID_FP87, 2684 .features[FEAT_1_ECX] = 2685 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2686 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2687 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2688 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2690 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2691 .features[FEAT_8000_0001_EDX] = 2692 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2693 CPUID_EXT2_SYSCALL, 2694 .features[FEAT_8000_0001_ECX] = 2695 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2696 .features[FEAT_7_0_EBX] = 2697 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2698 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2699 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2700 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2701 CPUID_7_0_EBX_SMAP, 2702 /* XSAVES is added in version 4 */ 2703 .features[FEAT_XSAVE] = 2704 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2705 CPUID_XSAVE_XGETBV1, 2706 .features[FEAT_6_EAX] = 2707 CPUID_6_EAX_ARAT, 2708 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2709 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2710 MSR_VMX_BASIC_TRUE_CTLS, 2711 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2712 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2713 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2714 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2715 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2716 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2717 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2718 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2719 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2720 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2721 .features[FEAT_VMX_EXIT_CTLS] = 2722 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2723 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2724 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2725 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2726 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2727 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2728 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2729 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2730 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2731 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2732 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2733 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2734 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2735 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2736 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2737 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2738 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2739 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2740 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2741 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2742 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2743 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2744 .features[FEAT_VMX_SECONDARY_CTLS] = 2745 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2746 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2747 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2748 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2749 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2750 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2751 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2752 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2753 .xlevel = 0x80000008, 2754 .model_id = "Intel Core Processor (Skylake)", 2755 .versions = (X86CPUVersionDefinition[]) { 2756 { .version = 1 }, 2757 { 2758 .version = 2, 2759 .alias = "Skylake-Client-IBRS", 2760 .props = (PropValue[]) { 2761 { "spec-ctrl", "on" }, 2762 { "model-id", 2763 "Intel Core Processor (Skylake, IBRS)" }, 2764 { /* end of list */ } 2765 } 2766 }, 2767 { 2768 .version = 3, 2769 .alias = "Skylake-Client-noTSX-IBRS", 2770 .props = (PropValue[]) { 2771 { "hle", "off" }, 2772 { "rtm", "off" }, 2773 { "model-id", 2774 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2775 { /* end of list */ } 2776 } 2777 }, 2778 { 2779 .version = 4, 2780 .note = "IBRS, XSAVES, no TSX", 2781 .props = (PropValue[]) { 2782 { "xsaves", "on" }, 2783 { "vmx-xsaves", "on" }, 2784 { /* end of list */ } 2785 } 2786 }, 2787 { /* end of list */ } 2788 } 2789 }, 2790 { 2791 .name = "Skylake-Server", 2792 .level = 0xd, 2793 .vendor = CPUID_VENDOR_INTEL, 2794 .family = 6, 2795 .model = 85, 2796 .stepping = 4, 2797 .features[FEAT_1_EDX] = 2798 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2799 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2800 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2801 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2802 CPUID_DE | CPUID_FP87, 2803 .features[FEAT_1_ECX] = 2804 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2805 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2806 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2807 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2808 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2809 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2810 .features[FEAT_8000_0001_EDX] = 2811 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2812 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2813 .features[FEAT_8000_0001_ECX] = 2814 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2815 .features[FEAT_7_0_EBX] = 2816 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2817 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2818 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2819 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2820 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2821 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2822 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2823 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2824 .features[FEAT_7_0_ECX] = 2825 CPUID_7_0_ECX_PKU, 2826 /* XSAVES is added in version 5 */ 2827 .features[FEAT_XSAVE] = 2828 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2829 CPUID_XSAVE_XGETBV1, 2830 .features[FEAT_6_EAX] = 2831 CPUID_6_EAX_ARAT, 2832 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2833 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2834 MSR_VMX_BASIC_TRUE_CTLS, 2835 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2836 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2837 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2838 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2839 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2840 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2841 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2842 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2843 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2844 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2845 .features[FEAT_VMX_EXIT_CTLS] = 2846 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2847 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2848 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2849 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2850 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2851 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2852 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2853 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2854 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2855 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2856 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2857 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2858 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2859 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2860 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2861 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2862 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2863 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2864 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2865 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2866 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2867 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2868 .features[FEAT_VMX_SECONDARY_CTLS] = 2869 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2870 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2871 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2872 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2873 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2874 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2875 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2876 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2877 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2878 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2879 .xlevel = 0x80000008, 2880 .model_id = "Intel Xeon Processor (Skylake)", 2881 .versions = (X86CPUVersionDefinition[]) { 2882 { .version = 1 }, 2883 { 2884 .version = 2, 2885 .alias = "Skylake-Server-IBRS", 2886 .props = (PropValue[]) { 2887 /* clflushopt was not added to Skylake-Server-IBRS */ 2888 /* TODO: add -v3 including clflushopt */ 2889 { "clflushopt", "off" }, 2890 { "spec-ctrl", "on" }, 2891 { "model-id", 2892 "Intel Xeon Processor (Skylake, IBRS)" }, 2893 { /* end of list */ } 2894 } 2895 }, 2896 { 2897 .version = 3, 2898 .alias = "Skylake-Server-noTSX-IBRS", 2899 .props = (PropValue[]) { 2900 { "hle", "off" }, 2901 { "rtm", "off" }, 2902 { "model-id", 2903 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 2904 { /* end of list */ } 2905 } 2906 }, 2907 { 2908 .version = 4, 2909 .props = (PropValue[]) { 2910 { "vmx-eptp-switching", "on" }, 2911 { /* end of list */ } 2912 } 2913 }, 2914 { 2915 .version = 5, 2916 .note = "IBRS, XSAVES, EPT switching, no TSX", 2917 .props = (PropValue[]) { 2918 { "xsaves", "on" }, 2919 { "vmx-xsaves", "on" }, 2920 { /* end of list */ } 2921 } 2922 }, 2923 { /* end of list */ } 2924 } 2925 }, 2926 { 2927 .name = "Cascadelake-Server", 2928 .level = 0xd, 2929 .vendor = CPUID_VENDOR_INTEL, 2930 .family = 6, 2931 .model = 85, 2932 .stepping = 6, 2933 .features[FEAT_1_EDX] = 2934 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2935 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2936 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2937 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2938 CPUID_DE | CPUID_FP87, 2939 .features[FEAT_1_ECX] = 2940 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2941 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2942 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2943 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2944 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2945 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2946 .features[FEAT_8000_0001_EDX] = 2947 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2948 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2949 .features[FEAT_8000_0001_ECX] = 2950 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2951 .features[FEAT_7_0_EBX] = 2952 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2953 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2954 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2955 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2956 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2957 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2958 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2959 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2960 .features[FEAT_7_0_ECX] = 2961 CPUID_7_0_ECX_PKU | 2962 CPUID_7_0_ECX_AVX512VNNI, 2963 .features[FEAT_7_0_EDX] = 2964 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 2965 /* XSAVES is added in version 5 */ 2966 .features[FEAT_XSAVE] = 2967 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2968 CPUID_XSAVE_XGETBV1, 2969 .features[FEAT_6_EAX] = 2970 CPUID_6_EAX_ARAT, 2971 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2972 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2973 MSR_VMX_BASIC_TRUE_CTLS, 2974 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2975 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2976 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2977 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2978 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2979 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2980 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2981 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2982 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2983 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2984 .features[FEAT_VMX_EXIT_CTLS] = 2985 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2986 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2987 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2988 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2989 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2990 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2991 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2992 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2993 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2994 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2995 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2996 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2997 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2998 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2999 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3000 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3001 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3002 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3003 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3004 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3005 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3006 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3007 .features[FEAT_VMX_SECONDARY_CTLS] = 3008 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3009 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3010 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3011 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3012 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3013 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3014 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3015 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3016 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3017 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3018 .xlevel = 0x80000008, 3019 .model_id = "Intel Xeon Processor (Cascadelake)", 3020 .versions = (X86CPUVersionDefinition[]) { 3021 { .version = 1 }, 3022 { .version = 2, 3023 .note = "ARCH_CAPABILITIES", 3024 .props = (PropValue[]) { 3025 { "arch-capabilities", "on" }, 3026 { "rdctl-no", "on" }, 3027 { "ibrs-all", "on" }, 3028 { "skip-l1dfl-vmentry", "on" }, 3029 { "mds-no", "on" }, 3030 { /* end of list */ } 3031 }, 3032 }, 3033 { .version = 3, 3034 .alias = "Cascadelake-Server-noTSX", 3035 .note = "ARCH_CAPABILITIES, no TSX", 3036 .props = (PropValue[]) { 3037 { "hle", "off" }, 3038 { "rtm", "off" }, 3039 { /* end of list */ } 3040 }, 3041 }, 3042 { .version = 4, 3043 .note = "ARCH_CAPABILITIES, no TSX", 3044 .props = (PropValue[]) { 3045 { "vmx-eptp-switching", "on" }, 3046 { /* end of list */ } 3047 }, 3048 }, 3049 { .version = 5, 3050 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3051 .props = (PropValue[]) { 3052 { "xsaves", "on" }, 3053 { "vmx-xsaves", "on" }, 3054 { /* end of list */ } 3055 }, 3056 }, 3057 { /* end of list */ } 3058 } 3059 }, 3060 { 3061 .name = "Cooperlake", 3062 .level = 0xd, 3063 .vendor = CPUID_VENDOR_INTEL, 3064 .family = 6, 3065 .model = 85, 3066 .stepping = 10, 3067 .features[FEAT_1_EDX] = 3068 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3069 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3070 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3071 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3072 CPUID_DE | CPUID_FP87, 3073 .features[FEAT_1_ECX] = 3074 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3075 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3076 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3077 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3078 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3079 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3080 .features[FEAT_8000_0001_EDX] = 3081 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3082 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3083 .features[FEAT_8000_0001_ECX] = 3084 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3085 .features[FEAT_7_0_EBX] = 3086 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3087 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3088 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3089 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3090 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3091 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3092 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3093 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3094 .features[FEAT_7_0_ECX] = 3095 CPUID_7_0_ECX_PKU | 3096 CPUID_7_0_ECX_AVX512VNNI, 3097 .features[FEAT_7_0_EDX] = 3098 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3099 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3100 .features[FEAT_ARCH_CAPABILITIES] = 3101 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3102 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3103 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3104 .features[FEAT_7_1_EAX] = 3105 CPUID_7_1_EAX_AVX512_BF16, 3106 /* XSAVES is added in version 2 */ 3107 .features[FEAT_XSAVE] = 3108 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3109 CPUID_XSAVE_XGETBV1, 3110 .features[FEAT_6_EAX] = 3111 CPUID_6_EAX_ARAT, 3112 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3113 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3114 MSR_VMX_BASIC_TRUE_CTLS, 3115 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3116 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3117 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3118 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3119 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3120 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3121 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3122 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3123 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3124 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3125 .features[FEAT_VMX_EXIT_CTLS] = 3126 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3127 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3128 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3129 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3130 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3131 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3132 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3133 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3134 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3135 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3136 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3137 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3138 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3139 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3140 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3141 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3142 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3143 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3144 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3145 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3146 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3147 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3148 .features[FEAT_VMX_SECONDARY_CTLS] = 3149 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3150 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3151 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3152 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3153 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3154 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3155 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3156 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3157 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3158 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3159 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3160 .xlevel = 0x80000008, 3161 .model_id = "Intel Xeon Processor (Cooperlake)", 3162 .versions = (X86CPUVersionDefinition[]) { 3163 { .version = 1 }, 3164 { .version = 2, 3165 .note = "XSAVES", 3166 .props = (PropValue[]) { 3167 { "xsaves", "on" }, 3168 { "vmx-xsaves", "on" }, 3169 { /* end of list */ } 3170 }, 3171 }, 3172 { /* end of list */ } 3173 } 3174 }, 3175 { 3176 .name = "Icelake-Client", 3177 .level = 0xd, 3178 .vendor = CPUID_VENDOR_INTEL, 3179 .family = 6, 3180 .model = 126, 3181 .stepping = 0, 3182 .features[FEAT_1_EDX] = 3183 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3184 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3185 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3186 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3187 CPUID_DE | CPUID_FP87, 3188 .features[FEAT_1_ECX] = 3189 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3190 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3191 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3192 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3193 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3194 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3195 .features[FEAT_8000_0001_EDX] = 3196 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3197 CPUID_EXT2_SYSCALL, 3198 .features[FEAT_8000_0001_ECX] = 3199 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3200 .features[FEAT_8000_0008_EBX] = 3201 CPUID_8000_0008_EBX_WBNOINVD, 3202 .features[FEAT_7_0_EBX] = 3203 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3204 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3205 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3206 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3207 CPUID_7_0_EBX_SMAP, 3208 .features[FEAT_7_0_ECX] = 3209 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3210 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3211 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3212 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3213 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3214 .features[FEAT_7_0_EDX] = 3215 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3216 /* XSAVES is added in version 3 */ 3217 .features[FEAT_XSAVE] = 3218 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3219 CPUID_XSAVE_XGETBV1, 3220 .features[FEAT_6_EAX] = 3221 CPUID_6_EAX_ARAT, 3222 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3223 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3224 MSR_VMX_BASIC_TRUE_CTLS, 3225 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3226 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3227 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3228 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3229 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3230 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3231 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3232 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3233 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3234 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3235 .features[FEAT_VMX_EXIT_CTLS] = 3236 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3237 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3238 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3239 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3240 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3241 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3242 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3243 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3244 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3245 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3246 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3247 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3248 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3249 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3250 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3251 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3252 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3253 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3254 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3255 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3256 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3257 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3258 .features[FEAT_VMX_SECONDARY_CTLS] = 3259 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3260 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3261 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3262 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3263 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3264 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3265 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3266 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3267 .xlevel = 0x80000008, 3268 .model_id = "Intel Core Processor (Icelake)", 3269 .versions = (X86CPUVersionDefinition[]) { 3270 { 3271 .version = 1, 3272 .note = "deprecated" 3273 }, 3274 { 3275 .version = 2, 3276 .note = "no TSX, deprecated", 3277 .alias = "Icelake-Client-noTSX", 3278 .props = (PropValue[]) { 3279 { "hle", "off" }, 3280 { "rtm", "off" }, 3281 { /* end of list */ } 3282 }, 3283 }, 3284 { 3285 .version = 3, 3286 .note = "no TSX, XSAVES, deprecated", 3287 .props = (PropValue[]) { 3288 { "xsaves", "on" }, 3289 { "vmx-xsaves", "on" }, 3290 { /* end of list */ } 3291 }, 3292 }, 3293 { /* end of list */ } 3294 }, 3295 .deprecation_note = "use Icelake-Server instead" 3296 }, 3297 { 3298 .name = "Icelake-Server", 3299 .level = 0xd, 3300 .vendor = CPUID_VENDOR_INTEL, 3301 .family = 6, 3302 .model = 134, 3303 .stepping = 0, 3304 .features[FEAT_1_EDX] = 3305 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3306 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3307 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3308 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3309 CPUID_DE | CPUID_FP87, 3310 .features[FEAT_1_ECX] = 3311 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3312 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3313 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3314 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3315 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3316 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3317 .features[FEAT_8000_0001_EDX] = 3318 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3319 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3320 .features[FEAT_8000_0001_ECX] = 3321 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3322 .features[FEAT_8000_0008_EBX] = 3323 CPUID_8000_0008_EBX_WBNOINVD, 3324 .features[FEAT_7_0_EBX] = 3325 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3326 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3327 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3328 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3329 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3330 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3331 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3332 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3333 .features[FEAT_7_0_ECX] = 3334 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3335 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3336 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3337 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3338 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3339 .features[FEAT_7_0_EDX] = 3340 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3341 /* XSAVES is added in version 5 */ 3342 .features[FEAT_XSAVE] = 3343 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3344 CPUID_XSAVE_XGETBV1, 3345 .features[FEAT_6_EAX] = 3346 CPUID_6_EAX_ARAT, 3347 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3348 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3349 MSR_VMX_BASIC_TRUE_CTLS, 3350 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3351 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3352 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3353 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3354 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3355 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3356 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3357 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3358 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3359 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3360 .features[FEAT_VMX_EXIT_CTLS] = 3361 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3362 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3363 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3364 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3365 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3366 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3367 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3368 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3369 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3370 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3371 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3372 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3373 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3374 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3375 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3376 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3377 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3378 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3379 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3380 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3381 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3382 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3383 .features[FEAT_VMX_SECONDARY_CTLS] = 3384 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3385 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3386 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3387 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3388 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3389 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3390 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3391 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3392 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3393 .xlevel = 0x80000008, 3394 .model_id = "Intel Xeon Processor (Icelake)", 3395 .versions = (X86CPUVersionDefinition[]) { 3396 { .version = 1 }, 3397 { 3398 .version = 2, 3399 .note = "no TSX", 3400 .alias = "Icelake-Server-noTSX", 3401 .props = (PropValue[]) { 3402 { "hle", "off" }, 3403 { "rtm", "off" }, 3404 { /* end of list */ } 3405 }, 3406 }, 3407 { 3408 .version = 3, 3409 .props = (PropValue[]) { 3410 { "arch-capabilities", "on" }, 3411 { "rdctl-no", "on" }, 3412 { "ibrs-all", "on" }, 3413 { "skip-l1dfl-vmentry", "on" }, 3414 { "mds-no", "on" }, 3415 { "pschange-mc-no", "on" }, 3416 { "taa-no", "on" }, 3417 { /* end of list */ } 3418 }, 3419 }, 3420 { 3421 .version = 4, 3422 .props = (PropValue[]) { 3423 { "sha-ni", "on" }, 3424 { "avx512ifma", "on" }, 3425 { "rdpid", "on" }, 3426 { "fsrm", "on" }, 3427 { "vmx-rdseed-exit", "on" }, 3428 { "vmx-pml", "on" }, 3429 { "vmx-eptp-switching", "on" }, 3430 { "model", "106" }, 3431 { /* end of list */ } 3432 }, 3433 }, 3434 { 3435 .version = 5, 3436 .note = "XSAVES", 3437 .props = (PropValue[]) { 3438 { "xsaves", "on" }, 3439 { "vmx-xsaves", "on" }, 3440 { /* end of list */ } 3441 }, 3442 }, 3443 { /* end of list */ } 3444 } 3445 }, 3446 { 3447 .name = "Denverton", 3448 .level = 21, 3449 .vendor = CPUID_VENDOR_INTEL, 3450 .family = 6, 3451 .model = 95, 3452 .stepping = 1, 3453 .features[FEAT_1_EDX] = 3454 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3455 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3456 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3457 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3458 CPUID_SSE | CPUID_SSE2, 3459 .features[FEAT_1_ECX] = 3460 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3461 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3462 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3463 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3464 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3465 .features[FEAT_8000_0001_EDX] = 3466 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3467 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3468 .features[FEAT_8000_0001_ECX] = 3469 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3470 .features[FEAT_7_0_EBX] = 3471 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3472 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3473 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3474 .features[FEAT_7_0_EDX] = 3475 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3476 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3477 /* XSAVES is added in version 3 */ 3478 .features[FEAT_XSAVE] = 3479 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3480 .features[FEAT_6_EAX] = 3481 CPUID_6_EAX_ARAT, 3482 .features[FEAT_ARCH_CAPABILITIES] = 3483 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3484 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3485 MSR_VMX_BASIC_TRUE_CTLS, 3486 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3487 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3488 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3489 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3490 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3491 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3492 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3493 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3494 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3495 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3496 .features[FEAT_VMX_EXIT_CTLS] = 3497 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3498 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3499 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3500 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3501 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3502 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3503 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3504 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3505 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3506 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3507 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3508 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3509 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3510 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3511 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3512 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3513 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3514 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3515 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3516 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3517 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3518 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3519 .features[FEAT_VMX_SECONDARY_CTLS] = 3520 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3521 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3522 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3523 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3524 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3525 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3526 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3527 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3528 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3529 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3530 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3531 .xlevel = 0x80000008, 3532 .model_id = "Intel Atom Processor (Denverton)", 3533 .versions = (X86CPUVersionDefinition[]) { 3534 { .version = 1 }, 3535 { 3536 .version = 2, 3537 .note = "no MPX, no MONITOR", 3538 .props = (PropValue[]) { 3539 { "monitor", "off" }, 3540 { "mpx", "off" }, 3541 { /* end of list */ }, 3542 }, 3543 }, 3544 { 3545 .version = 3, 3546 .note = "XSAVES, no MPX, no MONITOR", 3547 .props = (PropValue[]) { 3548 { "xsaves", "on" }, 3549 { "vmx-xsaves", "on" }, 3550 { /* end of list */ }, 3551 }, 3552 }, 3553 { /* end of list */ }, 3554 }, 3555 }, 3556 { 3557 .name = "Snowridge", 3558 .level = 27, 3559 .vendor = CPUID_VENDOR_INTEL, 3560 .family = 6, 3561 .model = 134, 3562 .stepping = 1, 3563 .features[FEAT_1_EDX] = 3564 /* missing: CPUID_PN CPUID_IA64 */ 3565 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3566 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3567 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3568 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3569 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3570 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3571 CPUID_MMX | 3572 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3573 .features[FEAT_1_ECX] = 3574 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3575 CPUID_EXT_SSSE3 | 3576 CPUID_EXT_CX16 | 3577 CPUID_EXT_SSE41 | 3578 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3579 CPUID_EXT_POPCNT | 3580 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3581 CPUID_EXT_RDRAND, 3582 .features[FEAT_8000_0001_EDX] = 3583 CPUID_EXT2_SYSCALL | 3584 CPUID_EXT2_NX | 3585 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3586 CPUID_EXT2_LM, 3587 .features[FEAT_8000_0001_ECX] = 3588 CPUID_EXT3_LAHF_LM | 3589 CPUID_EXT3_3DNOWPREFETCH, 3590 .features[FEAT_7_0_EBX] = 3591 CPUID_7_0_EBX_FSGSBASE | 3592 CPUID_7_0_EBX_SMEP | 3593 CPUID_7_0_EBX_ERMS | 3594 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3595 CPUID_7_0_EBX_RDSEED | 3596 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3597 CPUID_7_0_EBX_CLWB | 3598 CPUID_7_0_EBX_SHA_NI, 3599 .features[FEAT_7_0_ECX] = 3600 CPUID_7_0_ECX_UMIP | 3601 /* missing bit 5 */ 3602 CPUID_7_0_ECX_GFNI | 3603 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3604 CPUID_7_0_ECX_MOVDIR64B, 3605 .features[FEAT_7_0_EDX] = 3606 CPUID_7_0_EDX_SPEC_CTRL | 3607 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3608 CPUID_7_0_EDX_CORE_CAPABILITY, 3609 .features[FEAT_CORE_CAPABILITY] = 3610 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3611 /* XSAVES is is added in version 3 */ 3612 .features[FEAT_XSAVE] = 3613 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3614 CPUID_XSAVE_XGETBV1, 3615 .features[FEAT_6_EAX] = 3616 CPUID_6_EAX_ARAT, 3617 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3618 MSR_VMX_BASIC_TRUE_CTLS, 3619 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3620 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3621 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3622 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3623 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3624 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3625 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3626 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3627 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3628 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3629 .features[FEAT_VMX_EXIT_CTLS] = 3630 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3631 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3632 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3633 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3634 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3635 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3636 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3637 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3638 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3639 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3640 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3641 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3642 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3643 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3644 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3645 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3646 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3647 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3648 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3649 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3650 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3651 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3652 .features[FEAT_VMX_SECONDARY_CTLS] = 3653 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3654 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3655 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3656 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3657 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3658 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3659 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3660 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3661 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3662 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3663 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3664 .xlevel = 0x80000008, 3665 .model_id = "Intel Atom Processor (SnowRidge)", 3666 .versions = (X86CPUVersionDefinition[]) { 3667 { .version = 1 }, 3668 { 3669 .version = 2, 3670 .props = (PropValue[]) { 3671 { "mpx", "off" }, 3672 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3673 { /* end of list */ }, 3674 }, 3675 }, 3676 { 3677 .version = 3, 3678 .note = "XSAVES, no MPX", 3679 .props = (PropValue[]) { 3680 { "xsaves", "on" }, 3681 { "vmx-xsaves", "on" }, 3682 { /* end of list */ }, 3683 }, 3684 }, 3685 { 3686 .version = 4, 3687 .note = "no split lock detect", 3688 .props = (PropValue[]) { 3689 { "split-lock-detect", "off" }, 3690 { /* end of list */ }, 3691 }, 3692 }, 3693 { /* end of list */ }, 3694 }, 3695 }, 3696 { 3697 .name = "KnightsMill", 3698 .level = 0xd, 3699 .vendor = CPUID_VENDOR_INTEL, 3700 .family = 6, 3701 .model = 133, 3702 .stepping = 0, 3703 .features[FEAT_1_EDX] = 3704 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3705 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3706 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3707 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3708 CPUID_PSE | CPUID_DE | CPUID_FP87, 3709 .features[FEAT_1_ECX] = 3710 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3711 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3712 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3713 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3714 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3715 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3716 .features[FEAT_8000_0001_EDX] = 3717 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3718 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3719 .features[FEAT_8000_0001_ECX] = 3720 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3721 .features[FEAT_7_0_EBX] = 3722 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3723 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3724 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3725 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3726 CPUID_7_0_EBX_AVX512ER, 3727 .features[FEAT_7_0_ECX] = 3728 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3729 .features[FEAT_7_0_EDX] = 3730 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3731 .features[FEAT_XSAVE] = 3732 CPUID_XSAVE_XSAVEOPT, 3733 .features[FEAT_6_EAX] = 3734 CPUID_6_EAX_ARAT, 3735 .xlevel = 0x80000008, 3736 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3737 }, 3738 { 3739 .name = "Opteron_G1", 3740 .level = 5, 3741 .vendor = CPUID_VENDOR_AMD, 3742 .family = 15, 3743 .model = 6, 3744 .stepping = 1, 3745 .features[FEAT_1_EDX] = 3746 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3747 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3748 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3749 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3750 CPUID_DE | CPUID_FP87, 3751 .features[FEAT_1_ECX] = 3752 CPUID_EXT_SSE3, 3753 .features[FEAT_8000_0001_EDX] = 3754 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3755 .xlevel = 0x80000008, 3756 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3757 }, 3758 { 3759 .name = "Opteron_G2", 3760 .level = 5, 3761 .vendor = CPUID_VENDOR_AMD, 3762 .family = 15, 3763 .model = 6, 3764 .stepping = 1, 3765 .features[FEAT_1_EDX] = 3766 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3767 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3768 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3769 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3770 CPUID_DE | CPUID_FP87, 3771 .features[FEAT_1_ECX] = 3772 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3773 .features[FEAT_8000_0001_EDX] = 3774 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3775 .features[FEAT_8000_0001_ECX] = 3776 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3777 .xlevel = 0x80000008, 3778 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3779 }, 3780 { 3781 .name = "Opteron_G3", 3782 .level = 5, 3783 .vendor = CPUID_VENDOR_AMD, 3784 .family = 16, 3785 .model = 2, 3786 .stepping = 3, 3787 .features[FEAT_1_EDX] = 3788 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3789 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3790 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3791 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3792 CPUID_DE | CPUID_FP87, 3793 .features[FEAT_1_ECX] = 3794 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 3795 CPUID_EXT_SSE3, 3796 .features[FEAT_8000_0001_EDX] = 3797 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 3798 CPUID_EXT2_RDTSCP, 3799 .features[FEAT_8000_0001_ECX] = 3800 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 3801 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3802 .xlevel = 0x80000008, 3803 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 3804 }, 3805 { 3806 .name = "Opteron_G4", 3807 .level = 0xd, 3808 .vendor = CPUID_VENDOR_AMD, 3809 .family = 21, 3810 .model = 1, 3811 .stepping = 2, 3812 .features[FEAT_1_EDX] = 3813 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3814 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3815 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3816 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3817 CPUID_DE | CPUID_FP87, 3818 .features[FEAT_1_ECX] = 3819 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3820 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3821 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3822 CPUID_EXT_SSE3, 3823 .features[FEAT_8000_0001_EDX] = 3824 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3825 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3826 .features[FEAT_8000_0001_ECX] = 3827 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3828 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3829 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3830 CPUID_EXT3_LAHF_LM, 3831 .features[FEAT_SVM] = 3832 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3833 /* no xsaveopt! */ 3834 .xlevel = 0x8000001A, 3835 .model_id = "AMD Opteron 62xx class CPU", 3836 }, 3837 { 3838 .name = "Opteron_G5", 3839 .level = 0xd, 3840 .vendor = CPUID_VENDOR_AMD, 3841 .family = 21, 3842 .model = 2, 3843 .stepping = 0, 3844 .features[FEAT_1_EDX] = 3845 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3846 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3847 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3848 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3849 CPUID_DE | CPUID_FP87, 3850 .features[FEAT_1_ECX] = 3851 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 3852 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3853 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 3854 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3855 .features[FEAT_8000_0001_EDX] = 3856 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3857 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3858 .features[FEAT_8000_0001_ECX] = 3859 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3860 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3861 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3862 CPUID_EXT3_LAHF_LM, 3863 .features[FEAT_SVM] = 3864 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3865 /* no xsaveopt! */ 3866 .xlevel = 0x8000001A, 3867 .model_id = "AMD Opteron 63xx class CPU", 3868 }, 3869 { 3870 .name = "EPYC", 3871 .level = 0xd, 3872 .vendor = CPUID_VENDOR_AMD, 3873 .family = 23, 3874 .model = 1, 3875 .stepping = 2, 3876 .features[FEAT_1_EDX] = 3877 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 3878 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 3879 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 3880 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 3881 CPUID_VME | CPUID_FP87, 3882 .features[FEAT_1_ECX] = 3883 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 3884 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 3885 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3886 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 3887 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3888 .features[FEAT_8000_0001_EDX] = 3889 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 3890 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 3891 CPUID_EXT2_SYSCALL, 3892 .features[FEAT_8000_0001_ECX] = 3893 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 3894 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 3895 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 3896 CPUID_EXT3_TOPOEXT, 3897 .features[FEAT_7_0_EBX] = 3898 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3899 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 3900 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3901 CPUID_7_0_EBX_SHA_NI, 3902 .features[FEAT_XSAVE] = 3903 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3904 CPUID_XSAVE_XGETBV1, 3905 .features[FEAT_6_EAX] = 3906 CPUID_6_EAX_ARAT, 3907 .features[FEAT_SVM] = 3908 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3909 .xlevel = 0x8000001E, 3910 .model_id = "AMD EPYC Processor", 3911 .cache_info = &epyc_cache_info, 3912 .versions = (X86CPUVersionDefinition[]) { 3913 { .version = 1 }, 3914 { 3915 .version = 2, 3916 .alias = "EPYC-IBPB", 3917 .props = (PropValue[]) { 3918 { "ibpb", "on" }, 3919 { "model-id", 3920 "AMD EPYC Processor (with IBPB)" }, 3921 { /* end of list */ } 3922 } 3923 }, 3924 { 3925 .version = 3, 3926 .props = (PropValue[]) { 3927 { "ibpb", "on" }, 3928 { "perfctr-core", "on" }, 3929 { "clzero", "on" }, 3930 { "xsaveerptr", "on" }, 3931 { "xsaves", "on" }, 3932 { "model-id", 3933 "AMD EPYC Processor" }, 3934 { /* end of list */ } 3935 } 3936 }, 3937 { /* end of list */ } 3938 } 3939 }, 3940 { 3941 .name = "Dhyana", 3942 .level = 0xd, 3943 .vendor = CPUID_VENDOR_HYGON, 3944 .family = 24, 3945 .model = 0, 3946 .stepping = 1, 3947 .features[FEAT_1_EDX] = 3948 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 3949 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 3950 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 3951 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 3952 CPUID_VME | CPUID_FP87, 3953 .features[FEAT_1_ECX] = 3954 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 3955 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 3956 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3957 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 3958 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 3959 .features[FEAT_8000_0001_EDX] = 3960 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 3961 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 3962 CPUID_EXT2_SYSCALL, 3963 .features[FEAT_8000_0001_ECX] = 3964 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 3965 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 3966 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 3967 CPUID_EXT3_TOPOEXT, 3968 .features[FEAT_8000_0008_EBX] = 3969 CPUID_8000_0008_EBX_IBPB, 3970 .features[FEAT_7_0_EBX] = 3971 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3972 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 3973 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 3974 /* XSAVES is added in version 2 */ 3975 .features[FEAT_XSAVE] = 3976 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3977 CPUID_XSAVE_XGETBV1, 3978 .features[FEAT_6_EAX] = 3979 CPUID_6_EAX_ARAT, 3980 .features[FEAT_SVM] = 3981 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3982 .xlevel = 0x8000001E, 3983 .model_id = "Hygon Dhyana Processor", 3984 .cache_info = &epyc_cache_info, 3985 .versions = (X86CPUVersionDefinition[]) { 3986 { .version = 1 }, 3987 { .version = 2, 3988 .note = "XSAVES", 3989 .props = (PropValue[]) { 3990 { "xsaves", "on" }, 3991 { /* end of list */ } 3992 }, 3993 }, 3994 { /* end of list */ } 3995 } 3996 }, 3997 { 3998 .name = "EPYC-Rome", 3999 .level = 0xd, 4000 .vendor = CPUID_VENDOR_AMD, 4001 .family = 23, 4002 .model = 49, 4003 .stepping = 0, 4004 .features[FEAT_1_EDX] = 4005 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4006 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4007 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4008 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4009 CPUID_VME | CPUID_FP87, 4010 .features[FEAT_1_ECX] = 4011 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4012 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4013 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4014 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4015 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4016 .features[FEAT_8000_0001_EDX] = 4017 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4018 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4019 CPUID_EXT2_SYSCALL, 4020 .features[FEAT_8000_0001_ECX] = 4021 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4022 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4023 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4024 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4025 .features[FEAT_8000_0008_EBX] = 4026 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4027 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4028 CPUID_8000_0008_EBX_STIBP, 4029 .features[FEAT_7_0_EBX] = 4030 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4031 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4032 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4033 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4034 .features[FEAT_7_0_ECX] = 4035 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4036 .features[FEAT_XSAVE] = 4037 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4038 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4039 .features[FEAT_6_EAX] = 4040 CPUID_6_EAX_ARAT, 4041 .features[FEAT_SVM] = 4042 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4043 .xlevel = 0x8000001E, 4044 .model_id = "AMD EPYC-Rome Processor", 4045 .cache_info = &epyc_rome_cache_info, 4046 .versions = (X86CPUVersionDefinition[]) { 4047 { .version = 1 }, 4048 { 4049 .version = 2, 4050 .props = (PropValue[]) { 4051 { "ibrs", "on" }, 4052 { "amd-ssbd", "on" }, 4053 { /* end of list */ } 4054 } 4055 }, 4056 { /* end of list */ } 4057 } 4058 }, 4059 { 4060 .name = "EPYC-Milan", 4061 .level = 0xd, 4062 .vendor = CPUID_VENDOR_AMD, 4063 .family = 25, 4064 .model = 1, 4065 .stepping = 1, 4066 .features[FEAT_1_EDX] = 4067 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4068 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4069 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4070 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4071 CPUID_VME | CPUID_FP87, 4072 .features[FEAT_1_ECX] = 4073 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4074 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4075 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4076 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4077 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4078 CPUID_EXT_PCID, 4079 .features[FEAT_8000_0001_EDX] = 4080 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4081 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4082 CPUID_EXT2_SYSCALL, 4083 .features[FEAT_8000_0001_ECX] = 4084 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4085 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4086 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4087 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4088 .features[FEAT_8000_0008_EBX] = 4089 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4090 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4091 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4092 CPUID_8000_0008_EBX_AMD_SSBD, 4093 .features[FEAT_7_0_EBX] = 4094 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4095 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4096 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4097 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4098 CPUID_7_0_EBX_INVPCID, 4099 .features[FEAT_7_0_ECX] = 4100 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4101 .features[FEAT_7_0_EDX] = 4102 CPUID_7_0_EDX_FSRM, 4103 .features[FEAT_XSAVE] = 4104 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4105 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4106 .features[FEAT_6_EAX] = 4107 CPUID_6_EAX_ARAT, 4108 .features[FEAT_SVM] = 4109 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4110 .xlevel = 0x8000001E, 4111 .model_id = "AMD EPYC-Milan Processor", 4112 .cache_info = &epyc_milan_cache_info, 4113 }, 4114 }; 4115 4116 /* 4117 * We resolve CPU model aliases using -v1 when using "-machine 4118 * none", but this is just for compatibility while libvirt isn't 4119 * adapted to resolve CPU model versions before creating VMs. 4120 * See "Runnability guarantee of CPU models" at 4121 * docs/about/deprecated.rst. 4122 */ 4123 X86CPUVersion default_cpu_version = 1; 4124 4125 void x86_cpu_set_default_version(X86CPUVersion version) 4126 { 4127 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4128 assert(version != CPU_VERSION_AUTO); 4129 default_cpu_version = version; 4130 } 4131 4132 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4133 { 4134 int v = 0; 4135 const X86CPUVersionDefinition *vdef = 4136 x86_cpu_def_get_versions(model->cpudef); 4137 while (vdef->version) { 4138 v = vdef->version; 4139 vdef++; 4140 } 4141 return v; 4142 } 4143 4144 /* Return the actual version being used for a specific CPU model */ 4145 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4146 { 4147 X86CPUVersion v = model->version; 4148 if (v == CPU_VERSION_AUTO) { 4149 v = default_cpu_version; 4150 } 4151 if (v == CPU_VERSION_LATEST) { 4152 return x86_cpu_model_last_version(model); 4153 } 4154 return v; 4155 } 4156 4157 static Property max_x86_cpu_properties[] = { 4158 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4159 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4160 DEFINE_PROP_END_OF_LIST() 4161 }; 4162 4163 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4164 { 4165 DeviceClass *dc = DEVICE_CLASS(oc); 4166 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4167 4168 xcc->ordering = 9; 4169 4170 xcc->model_description = 4171 "Enables all features supported by the accelerator in the current host"; 4172 4173 device_class_set_props(dc, max_x86_cpu_properties); 4174 } 4175 4176 static void max_x86_cpu_initfn(Object *obj) 4177 { 4178 X86CPU *cpu = X86_CPU(obj); 4179 4180 /* We can't fill the features array here because we don't know yet if 4181 * "migratable" is true or false. 4182 */ 4183 cpu->max_features = true; 4184 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4185 4186 /* 4187 * these defaults are used for TCG and all other accelerators 4188 * besides KVM and HVF, which overwrite these values 4189 */ 4190 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4191 &error_abort); 4192 #ifdef TARGET_X86_64 4193 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort); 4194 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort); 4195 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort); 4196 #else 4197 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); 4198 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); 4199 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); 4200 #endif 4201 object_property_set_str(OBJECT(cpu), "model-id", 4202 "QEMU TCG CPU version " QEMU_HW_VERSION, 4203 &error_abort); 4204 } 4205 4206 static const TypeInfo max_x86_cpu_type_info = { 4207 .name = X86_CPU_TYPE_NAME("max"), 4208 .parent = TYPE_X86_CPU, 4209 .instance_init = max_x86_cpu_initfn, 4210 .class_init = max_x86_cpu_class_init, 4211 }; 4212 4213 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4214 { 4215 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4216 4217 switch (f->type) { 4218 case CPUID_FEATURE_WORD: 4219 { 4220 const char *reg = get_register_name_32(f->cpuid.reg); 4221 assert(reg); 4222 return g_strdup_printf("CPUID.%02XH:%s", 4223 f->cpuid.eax, reg); 4224 } 4225 case MSR_FEATURE_WORD: 4226 return g_strdup_printf("MSR(%02XH)", 4227 f->msr.index); 4228 } 4229 4230 return NULL; 4231 } 4232 4233 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4234 { 4235 FeatureWord w; 4236 4237 for (w = 0; w < FEATURE_WORDS; w++) { 4238 if (cpu->filtered_features[w]) { 4239 return true; 4240 } 4241 } 4242 4243 return false; 4244 } 4245 4246 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4247 const char *verbose_prefix) 4248 { 4249 CPUX86State *env = &cpu->env; 4250 FeatureWordInfo *f = &feature_word_info[w]; 4251 int i; 4252 4253 if (!cpu->force_features) { 4254 env->features[w] &= ~mask; 4255 } 4256 cpu->filtered_features[w] |= mask; 4257 4258 if (!verbose_prefix) { 4259 return; 4260 } 4261 4262 for (i = 0; i < 64; ++i) { 4263 if ((1ULL << i) & mask) { 4264 g_autofree char *feat_word_str = feature_word_description(f, i); 4265 warn_report("%s: %s%s%s [bit %d]", 4266 verbose_prefix, 4267 feat_word_str, 4268 f->feat_names[i] ? "." : "", 4269 f->feat_names[i] ? f->feat_names[i] : "", i); 4270 } 4271 } 4272 } 4273 4274 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4275 const char *name, void *opaque, 4276 Error **errp) 4277 { 4278 X86CPU *cpu = X86_CPU(obj); 4279 CPUX86State *env = &cpu->env; 4280 int64_t value; 4281 4282 value = (env->cpuid_version >> 8) & 0xf; 4283 if (value == 0xf) { 4284 value += (env->cpuid_version >> 20) & 0xff; 4285 } 4286 visit_type_int(v, name, &value, errp); 4287 } 4288 4289 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4290 const char *name, void *opaque, 4291 Error **errp) 4292 { 4293 X86CPU *cpu = X86_CPU(obj); 4294 CPUX86State *env = &cpu->env; 4295 const int64_t min = 0; 4296 const int64_t max = 0xff + 0xf; 4297 int64_t value; 4298 4299 if (!visit_type_int(v, name, &value, errp)) { 4300 return; 4301 } 4302 if (value < min || value > max) { 4303 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4304 name ? name : "null", value, min, max); 4305 return; 4306 } 4307 4308 env->cpuid_version &= ~0xff00f00; 4309 if (value > 0x0f) { 4310 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4311 } else { 4312 env->cpuid_version |= value << 8; 4313 } 4314 } 4315 4316 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4317 const char *name, void *opaque, 4318 Error **errp) 4319 { 4320 X86CPU *cpu = X86_CPU(obj); 4321 CPUX86State *env = &cpu->env; 4322 int64_t value; 4323 4324 value = (env->cpuid_version >> 4) & 0xf; 4325 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4326 visit_type_int(v, name, &value, errp); 4327 } 4328 4329 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4330 const char *name, void *opaque, 4331 Error **errp) 4332 { 4333 X86CPU *cpu = X86_CPU(obj); 4334 CPUX86State *env = &cpu->env; 4335 const int64_t min = 0; 4336 const int64_t max = 0xff; 4337 int64_t value; 4338 4339 if (!visit_type_int(v, name, &value, errp)) { 4340 return; 4341 } 4342 if (value < min || value > max) { 4343 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4344 name ? name : "null", value, min, max); 4345 return; 4346 } 4347 4348 env->cpuid_version &= ~0xf00f0; 4349 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4350 } 4351 4352 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4353 const char *name, void *opaque, 4354 Error **errp) 4355 { 4356 X86CPU *cpu = X86_CPU(obj); 4357 CPUX86State *env = &cpu->env; 4358 int64_t value; 4359 4360 value = env->cpuid_version & 0xf; 4361 visit_type_int(v, name, &value, errp); 4362 } 4363 4364 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4365 const char *name, void *opaque, 4366 Error **errp) 4367 { 4368 X86CPU *cpu = X86_CPU(obj); 4369 CPUX86State *env = &cpu->env; 4370 const int64_t min = 0; 4371 const int64_t max = 0xf; 4372 int64_t value; 4373 4374 if (!visit_type_int(v, name, &value, errp)) { 4375 return; 4376 } 4377 if (value < min || value > max) { 4378 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4379 name ? name : "null", value, min, max); 4380 return; 4381 } 4382 4383 env->cpuid_version &= ~0xf; 4384 env->cpuid_version |= value & 0xf; 4385 } 4386 4387 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4388 { 4389 X86CPU *cpu = X86_CPU(obj); 4390 CPUX86State *env = &cpu->env; 4391 char *value; 4392 4393 value = g_malloc(CPUID_VENDOR_SZ + 1); 4394 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4395 env->cpuid_vendor3); 4396 return value; 4397 } 4398 4399 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4400 Error **errp) 4401 { 4402 X86CPU *cpu = X86_CPU(obj); 4403 CPUX86State *env = &cpu->env; 4404 int i; 4405 4406 if (strlen(value) != CPUID_VENDOR_SZ) { 4407 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4408 return; 4409 } 4410 4411 env->cpuid_vendor1 = 0; 4412 env->cpuid_vendor2 = 0; 4413 env->cpuid_vendor3 = 0; 4414 for (i = 0; i < 4; i++) { 4415 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4416 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4417 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4418 } 4419 } 4420 4421 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4422 { 4423 X86CPU *cpu = X86_CPU(obj); 4424 CPUX86State *env = &cpu->env; 4425 char *value; 4426 int i; 4427 4428 value = g_malloc(48 + 1); 4429 for (i = 0; i < 48; i++) { 4430 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4431 } 4432 value[48] = '\0'; 4433 return value; 4434 } 4435 4436 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4437 Error **errp) 4438 { 4439 X86CPU *cpu = X86_CPU(obj); 4440 CPUX86State *env = &cpu->env; 4441 int c, len, i; 4442 4443 if (model_id == NULL) { 4444 model_id = ""; 4445 } 4446 len = strlen(model_id); 4447 memset(env->cpuid_model, 0, 48); 4448 for (i = 0; i < 48; i++) { 4449 if (i >= len) { 4450 c = '\0'; 4451 } else { 4452 c = (uint8_t)model_id[i]; 4453 } 4454 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4455 } 4456 } 4457 4458 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4459 void *opaque, Error **errp) 4460 { 4461 X86CPU *cpu = X86_CPU(obj); 4462 int64_t value; 4463 4464 value = cpu->env.tsc_khz * 1000; 4465 visit_type_int(v, name, &value, errp); 4466 } 4467 4468 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4469 void *opaque, Error **errp) 4470 { 4471 X86CPU *cpu = X86_CPU(obj); 4472 const int64_t min = 0; 4473 const int64_t max = INT64_MAX; 4474 int64_t value; 4475 4476 if (!visit_type_int(v, name, &value, errp)) { 4477 return; 4478 } 4479 if (value < min || value > max) { 4480 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4481 name ? name : "null", value, min, max); 4482 return; 4483 } 4484 4485 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4486 } 4487 4488 /* Generic getter for "feature-words" and "filtered-features" properties */ 4489 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4490 const char *name, void *opaque, 4491 Error **errp) 4492 { 4493 uint64_t *array = (uint64_t *)opaque; 4494 FeatureWord w; 4495 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4496 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4497 X86CPUFeatureWordInfoList *list = NULL; 4498 4499 for (w = 0; w < FEATURE_WORDS; w++) { 4500 FeatureWordInfo *wi = &feature_word_info[w]; 4501 /* 4502 * We didn't have MSR features when "feature-words" was 4503 * introduced. Therefore skipped other type entries. 4504 */ 4505 if (wi->type != CPUID_FEATURE_WORD) { 4506 continue; 4507 } 4508 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4509 qwi->cpuid_input_eax = wi->cpuid.eax; 4510 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4511 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4512 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4513 qwi->features = array[w]; 4514 4515 /* List will be in reverse order, but order shouldn't matter */ 4516 list_entries[w].next = list; 4517 list_entries[w].value = &word_infos[w]; 4518 list = &list_entries[w]; 4519 } 4520 4521 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4522 } 4523 4524 /* Convert all '_' in a feature string option name to '-', to make feature 4525 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4526 */ 4527 static inline void feat2prop(char *s) 4528 { 4529 while ((s = strchr(s, '_'))) { 4530 *s = '-'; 4531 } 4532 } 4533 4534 /* Return the feature property name for a feature flag bit */ 4535 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4536 { 4537 const char *name; 4538 /* XSAVE components are automatically enabled by other features, 4539 * so return the original feature name instead 4540 */ 4541 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) { 4542 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; 4543 4544 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4545 x86_ext_save_areas[comp].bits) { 4546 w = x86_ext_save_areas[comp].feature; 4547 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4548 } 4549 } 4550 4551 assert(bitnr < 64); 4552 assert(w < FEATURE_WORDS); 4553 name = feature_word_info[w].feat_names[bitnr]; 4554 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4555 return name; 4556 } 4557 4558 /* Compatibily hack to maintain legacy +-feat semantic, 4559 * where +-feat overwrites any feature set by 4560 * feat=on|feat even if the later is parsed after +-feat 4561 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4562 */ 4563 static GList *plus_features, *minus_features; 4564 4565 static gint compare_string(gconstpointer a, gconstpointer b) 4566 { 4567 return g_strcmp0(a, b); 4568 } 4569 4570 /* Parse "+feature,-feature,feature=foo" CPU feature string 4571 */ 4572 static void x86_cpu_parse_featurestr(const char *typename, char *features, 4573 Error **errp) 4574 { 4575 char *featurestr; /* Single 'key=value" string being parsed */ 4576 static bool cpu_globals_initialized; 4577 bool ambiguous = false; 4578 4579 if (cpu_globals_initialized) { 4580 return; 4581 } 4582 cpu_globals_initialized = true; 4583 4584 if (!features) { 4585 return; 4586 } 4587 4588 for (featurestr = strtok(features, ","); 4589 featurestr; 4590 featurestr = strtok(NULL, ",")) { 4591 const char *name; 4592 const char *val = NULL; 4593 char *eq = NULL; 4594 char num[32]; 4595 GlobalProperty *prop; 4596 4597 /* Compatibility syntax: */ 4598 if (featurestr[0] == '+') { 4599 plus_features = g_list_append(plus_features, 4600 g_strdup(featurestr + 1)); 4601 continue; 4602 } else if (featurestr[0] == '-') { 4603 minus_features = g_list_append(minus_features, 4604 g_strdup(featurestr + 1)); 4605 continue; 4606 } 4607 4608 eq = strchr(featurestr, '='); 4609 if (eq) { 4610 *eq++ = 0; 4611 val = eq; 4612 } else { 4613 val = "on"; 4614 } 4615 4616 feat2prop(featurestr); 4617 name = featurestr; 4618 4619 if (g_list_find_custom(plus_features, name, compare_string)) { 4620 warn_report("Ambiguous CPU model string. " 4621 "Don't mix both \"+%s\" and \"%s=%s\"", 4622 name, name, val); 4623 ambiguous = true; 4624 } 4625 if (g_list_find_custom(minus_features, name, compare_string)) { 4626 warn_report("Ambiguous CPU model string. " 4627 "Don't mix both \"-%s\" and \"%s=%s\"", 4628 name, name, val); 4629 ambiguous = true; 4630 } 4631 4632 /* Special case: */ 4633 if (!strcmp(name, "tsc-freq")) { 4634 int ret; 4635 uint64_t tsc_freq; 4636 4637 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4638 if (ret < 0 || tsc_freq > INT64_MAX) { 4639 error_setg(errp, "bad numerical value %s", val); 4640 return; 4641 } 4642 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4643 val = num; 4644 name = "tsc-frequency"; 4645 } 4646 4647 prop = g_new0(typeof(*prop), 1); 4648 prop->driver = typename; 4649 prop->property = g_strdup(name); 4650 prop->value = g_strdup(val); 4651 qdev_prop_register_global(prop); 4652 } 4653 4654 if (ambiguous) { 4655 warn_report("Compatibility of ambiguous CPU model " 4656 "strings won't be kept on future QEMU versions"); 4657 } 4658 } 4659 4660 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4661 4662 /* Build a list with the name of all features on a feature word array */ 4663 static void x86_cpu_list_feature_names(FeatureWordArray features, 4664 strList **list) 4665 { 4666 strList **tail = list; 4667 FeatureWord w; 4668 4669 for (w = 0; w < FEATURE_WORDS; w++) { 4670 uint64_t filtered = features[w]; 4671 int i; 4672 for (i = 0; i < 64; i++) { 4673 if (filtered & (1ULL << i)) { 4674 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 4675 } 4676 } 4677 } 4678 } 4679 4680 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4681 const char *name, void *opaque, 4682 Error **errp) 4683 { 4684 X86CPU *xc = X86_CPU(obj); 4685 strList *result = NULL; 4686 4687 x86_cpu_list_feature_names(xc->filtered_features, &result); 4688 visit_type_strList(v, "unavailable-features", &result, errp); 4689 } 4690 4691 /* Check for missing features that may prevent the CPU class from 4692 * running using the current machine and accelerator. 4693 */ 4694 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 4695 strList **list) 4696 { 4697 strList **tail = list; 4698 X86CPU *xc; 4699 Error *err = NULL; 4700 4701 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 4702 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 4703 return; 4704 } 4705 4706 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 4707 4708 x86_cpu_expand_features(xc, &err); 4709 if (err) { 4710 /* Errors at x86_cpu_expand_features should never happen, 4711 * but in case it does, just report the model as not 4712 * runnable at all using the "type" property. 4713 */ 4714 QAPI_LIST_APPEND(tail, g_strdup("type")); 4715 error_free(err); 4716 } 4717 4718 x86_cpu_filter_features(xc, false); 4719 4720 x86_cpu_list_feature_names(xc->filtered_features, tail); 4721 4722 object_unref(OBJECT(xc)); 4723 } 4724 4725 /* Print all cpuid feature names in featureset 4726 */ 4727 static void listflags(GList *features) 4728 { 4729 size_t len = 0; 4730 GList *tmp; 4731 4732 for (tmp = features; tmp; tmp = tmp->next) { 4733 const char *name = tmp->data; 4734 if ((len + strlen(name) + 1) >= 75) { 4735 qemu_printf("\n"); 4736 len = 0; 4737 } 4738 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4739 len += strlen(name) + 1; 4740 } 4741 qemu_printf("\n"); 4742 } 4743 4744 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4745 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4746 { 4747 ObjectClass *class_a = (ObjectClass *)a; 4748 ObjectClass *class_b = (ObjectClass *)b; 4749 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4750 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 4751 int ret; 4752 4753 if (cc_a->ordering != cc_b->ordering) { 4754 ret = cc_a->ordering - cc_b->ordering; 4755 } else { 4756 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 4757 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 4758 ret = strcmp(name_a, name_b); 4759 } 4760 return ret; 4761 } 4762 4763 static GSList *get_sorted_cpu_model_list(void) 4764 { 4765 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 4766 list = g_slist_sort(list, x86_cpu_list_compare); 4767 return list; 4768 } 4769 4770 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 4771 { 4772 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 4773 char *r = object_property_get_str(obj, "model-id", &error_abort); 4774 object_unref(obj); 4775 return r; 4776 } 4777 4778 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 4779 { 4780 X86CPUVersion version; 4781 4782 if (!cc->model || !cc->model->is_alias) { 4783 return NULL; 4784 } 4785 version = x86_cpu_model_resolve_version(cc->model); 4786 if (version <= 0) { 4787 return NULL; 4788 } 4789 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 4790 } 4791 4792 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 4793 { 4794 ObjectClass *oc = data; 4795 X86CPUClass *cc = X86_CPU_CLASS(oc); 4796 g_autofree char *name = x86_cpu_class_get_model_name(cc); 4797 g_autofree char *desc = g_strdup(cc->model_description); 4798 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 4799 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 4800 4801 if (!desc && alias_of) { 4802 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 4803 desc = g_strdup("(alias configured by machine type)"); 4804 } else { 4805 desc = g_strdup_printf("(alias of %s)", alias_of); 4806 } 4807 } 4808 if (!desc && cc->model && cc->model->note) { 4809 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 4810 } 4811 if (!desc) { 4812 desc = g_strdup_printf("%s", model_id); 4813 } 4814 4815 qemu_printf("x86 %-20s %-58s\n", name, desc); 4816 } 4817 4818 /* list available CPU models and flags */ 4819 void x86_cpu_list(void) 4820 { 4821 int i, j; 4822 GSList *list; 4823 GList *names = NULL; 4824 4825 qemu_printf("Available CPUs:\n"); 4826 list = get_sorted_cpu_model_list(); 4827 g_slist_foreach(list, x86_cpu_list_entry, NULL); 4828 g_slist_free(list); 4829 4830 names = NULL; 4831 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 4832 FeatureWordInfo *fw = &feature_word_info[i]; 4833 for (j = 0; j < 64; j++) { 4834 if (fw->feat_names[j]) { 4835 names = g_list_append(names, (gpointer)fw->feat_names[j]); 4836 } 4837 } 4838 } 4839 4840 names = g_list_sort(names, (GCompareFunc)strcmp); 4841 4842 qemu_printf("\nRecognized CPUID flags:\n"); 4843 listflags(names); 4844 qemu_printf("\n"); 4845 g_list_free(names); 4846 } 4847 4848 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 4849 { 4850 ObjectClass *oc = data; 4851 X86CPUClass *cc = X86_CPU_CLASS(oc); 4852 CpuDefinitionInfoList **cpu_list = user_data; 4853 CpuDefinitionInfo *info; 4854 4855 info = g_malloc0(sizeof(*info)); 4856 info->name = x86_cpu_class_get_model_name(cc); 4857 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 4858 info->has_unavailable_features = true; 4859 info->q_typename = g_strdup(object_class_get_name(oc)); 4860 info->migration_safe = cc->migration_safe; 4861 info->has_migration_safe = true; 4862 info->q_static = cc->static_model; 4863 if (cc->model && cc->model->cpudef->deprecation_note) { 4864 info->deprecated = true; 4865 } else { 4866 info->deprecated = false; 4867 } 4868 /* 4869 * Old machine types won't report aliases, so that alias translation 4870 * doesn't break compatibility with previous QEMU versions. 4871 */ 4872 if (default_cpu_version != CPU_VERSION_LEGACY) { 4873 info->alias_of = x86_cpu_class_get_alias_of(cc); 4874 info->has_alias_of = !!info->alias_of; 4875 } 4876 4877 QAPI_LIST_PREPEND(*cpu_list, info); 4878 } 4879 4880 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 4881 { 4882 CpuDefinitionInfoList *cpu_list = NULL; 4883 GSList *list = get_sorted_cpu_model_list(); 4884 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 4885 g_slist_free(list); 4886 return cpu_list; 4887 } 4888 4889 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 4890 bool migratable_only) 4891 { 4892 FeatureWordInfo *wi = &feature_word_info[w]; 4893 uint64_t r = 0; 4894 4895 if (kvm_enabled()) { 4896 switch (wi->type) { 4897 case CPUID_FEATURE_WORD: 4898 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 4899 wi->cpuid.ecx, 4900 wi->cpuid.reg); 4901 break; 4902 case MSR_FEATURE_WORD: 4903 r = kvm_arch_get_supported_msr_feature(kvm_state, 4904 wi->msr.index); 4905 break; 4906 } 4907 } else if (hvf_enabled()) { 4908 if (wi->type != CPUID_FEATURE_WORD) { 4909 return 0; 4910 } 4911 r = hvf_get_supported_cpuid(wi->cpuid.eax, 4912 wi->cpuid.ecx, 4913 wi->cpuid.reg); 4914 } else if (tcg_enabled()) { 4915 r = wi->tcg_features; 4916 } else { 4917 return ~0; 4918 } 4919 #ifndef TARGET_X86_64 4920 if (w == FEAT_8000_0001_EDX) { 4921 r &= ~CPUID_EXT2_LM; 4922 } 4923 #endif 4924 if (migratable_only) { 4925 r &= x86_cpu_get_migratable_flags(w); 4926 } 4927 return r; 4928 } 4929 4930 /* 4931 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 4932 */ 4933 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 4934 { 4935 PropValue *pv; 4936 for (pv = props; pv->prop; pv++) { 4937 if (!pv->value) { 4938 continue; 4939 } 4940 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 4941 &error_abort); 4942 } 4943 } 4944 4945 /* 4946 * Apply properties for the CPU model version specified in model. 4947 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 4948 */ 4949 4950 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 4951 { 4952 const X86CPUVersionDefinition *vdef; 4953 X86CPUVersion version = x86_cpu_model_resolve_version(model); 4954 4955 if (version == CPU_VERSION_LEGACY) { 4956 return; 4957 } 4958 4959 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 4960 PropValue *p; 4961 4962 for (p = vdef->props; p && p->prop; p++) { 4963 object_property_parse(OBJECT(cpu), p->prop, p->value, 4964 &error_abort); 4965 } 4966 4967 if (vdef->version == version) { 4968 break; 4969 } 4970 } 4971 4972 /* 4973 * If we reached the end of the list, version number was invalid 4974 */ 4975 assert(vdef->version == version); 4976 } 4977 4978 /* 4979 * Load data from X86CPUDefinition into a X86CPU object. 4980 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 4981 */ 4982 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 4983 { 4984 const X86CPUDefinition *def = model->cpudef; 4985 CPUX86State *env = &cpu->env; 4986 FeatureWord w; 4987 4988 /*NOTE: any property set by this function should be returned by 4989 * x86_cpu_static_props(), so static expansion of 4990 * query-cpu-model-expansion is always complete. 4991 */ 4992 4993 /* CPU models only set _minimum_ values for level/xlevel: */ 4994 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 4995 &error_abort); 4996 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 4997 &error_abort); 4998 4999 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5000 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5001 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5002 &error_abort); 5003 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5004 &error_abort); 5005 for (w = 0; w < FEATURE_WORDS; w++) { 5006 env->features[w] = def->features[w]; 5007 } 5008 5009 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5010 cpu->legacy_cache = !def->cache_info; 5011 5012 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5013 5014 /* sysenter isn't supported in compatibility mode on AMD, 5015 * syscall isn't supported in compatibility mode on Intel. 5016 * Normally we advertise the actual CPU vendor, but you can 5017 * override this using the 'vendor' property if you want to use 5018 * KVM's sysenter/syscall emulation in compatibility mode and 5019 * when doing cross vendor migration 5020 */ 5021 5022 /* 5023 * vendor property is set here but then overloaded with the 5024 * host cpu vendor for KVM and HVF. 5025 */ 5026 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5027 5028 x86_cpu_apply_version_props(cpu, model); 5029 5030 /* 5031 * Properties in versioned CPU model are not user specified features. 5032 * We can simply clear env->user_features here since it will be filled later 5033 * in x86_cpu_expand_features() based on plus_features and minus_features. 5034 */ 5035 memset(&env->user_features, 0, sizeof(env->user_features)); 5036 } 5037 5038 static gchar *x86_gdb_arch_name(CPUState *cs) 5039 { 5040 #ifdef TARGET_X86_64 5041 return g_strdup("i386:x86-64"); 5042 #else 5043 return g_strdup("i386"); 5044 #endif 5045 } 5046 5047 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5048 { 5049 X86CPUModel *model = data; 5050 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5051 CPUClass *cc = CPU_CLASS(oc); 5052 5053 xcc->model = model; 5054 xcc->migration_safe = true; 5055 cc->deprecation_note = model->cpudef->deprecation_note; 5056 } 5057 5058 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5059 { 5060 g_autofree char *typename = x86_cpu_type_name(name); 5061 TypeInfo ti = { 5062 .name = typename, 5063 .parent = TYPE_X86_CPU, 5064 .class_init = x86_cpu_cpudef_class_init, 5065 .class_data = model, 5066 }; 5067 5068 type_register(&ti); 5069 } 5070 5071 5072 /* 5073 * register builtin_x86_defs; 5074 * "max", "base" and subclasses ("host") are not registered here. 5075 * See x86_cpu_register_types for all model registrations. 5076 */ 5077 static void x86_register_cpudef_types(const X86CPUDefinition *def) 5078 { 5079 X86CPUModel *m; 5080 const X86CPUVersionDefinition *vdef; 5081 5082 /* AMD aliases are handled at runtime based on CPUID vendor, so 5083 * they shouldn't be set on the CPU model table. 5084 */ 5085 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5086 /* catch mistakes instead of silently truncating model_id when too long */ 5087 assert(def->model_id && strlen(def->model_id) <= 48); 5088 5089 /* Unversioned model: */ 5090 m = g_new0(X86CPUModel, 1); 5091 m->cpudef = def; 5092 m->version = CPU_VERSION_AUTO; 5093 m->is_alias = true; 5094 x86_register_cpu_model_type(def->name, m); 5095 5096 /* Versioned models: */ 5097 5098 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5099 X86CPUModel *m = g_new0(X86CPUModel, 1); 5100 g_autofree char *name = 5101 x86_cpu_versioned_model_name(def, vdef->version); 5102 m->cpudef = def; 5103 m->version = vdef->version; 5104 m->note = vdef->note; 5105 x86_register_cpu_model_type(name, m); 5106 5107 if (vdef->alias) { 5108 X86CPUModel *am = g_new0(X86CPUModel, 1); 5109 am->cpudef = def; 5110 am->version = vdef->version; 5111 am->is_alias = true; 5112 x86_register_cpu_model_type(vdef->alias, am); 5113 } 5114 } 5115 5116 } 5117 5118 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5119 uint32_t *eax, uint32_t *ebx, 5120 uint32_t *ecx, uint32_t *edx) 5121 { 5122 X86CPU *cpu = env_archcpu(env); 5123 CPUState *cs = env_cpu(env); 5124 uint32_t die_offset; 5125 uint32_t limit; 5126 uint32_t signature[3]; 5127 X86CPUTopoInfo topo_info; 5128 5129 topo_info.dies_per_pkg = env->nr_dies; 5130 topo_info.cores_per_die = cs->nr_cores; 5131 topo_info.threads_per_core = cs->nr_threads; 5132 5133 /* Calculate & apply limits for different index ranges */ 5134 if (index >= 0xC0000000) { 5135 limit = env->cpuid_xlevel2; 5136 } else if (index >= 0x80000000) { 5137 limit = env->cpuid_xlevel; 5138 } else if (index >= 0x40000000) { 5139 limit = 0x40000001; 5140 } else { 5141 limit = env->cpuid_level; 5142 } 5143 5144 if (index > limit) { 5145 /* Intel documentation states that invalid EAX input will 5146 * return the same information as EAX=cpuid_level 5147 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5148 */ 5149 index = env->cpuid_level; 5150 } 5151 5152 switch(index) { 5153 case 0: 5154 *eax = env->cpuid_level; 5155 *ebx = env->cpuid_vendor1; 5156 *edx = env->cpuid_vendor2; 5157 *ecx = env->cpuid_vendor3; 5158 break; 5159 case 1: 5160 *eax = env->cpuid_version; 5161 *ebx = (cpu->apic_id << 24) | 5162 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5163 *ecx = env->features[FEAT_1_ECX]; 5164 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5165 *ecx |= CPUID_EXT_OSXSAVE; 5166 } 5167 *edx = env->features[FEAT_1_EDX]; 5168 if (cs->nr_cores * cs->nr_threads > 1) { 5169 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5170 *edx |= CPUID_HT; 5171 } 5172 if (!cpu->enable_pmu) { 5173 *ecx &= ~CPUID_EXT_PDCM; 5174 } 5175 break; 5176 case 2: 5177 /* cache info: needed for Pentium Pro compatibility */ 5178 if (cpu->cache_info_passthrough) { 5179 host_cpuid(index, 0, eax, ebx, ecx, edx); 5180 break; 5181 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5182 *eax = *ebx = *ecx = *edx = 0; 5183 break; 5184 } 5185 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5186 *ebx = 0; 5187 if (!cpu->enable_l3_cache) { 5188 *ecx = 0; 5189 } else { 5190 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5191 } 5192 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5193 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5194 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5195 break; 5196 case 4: 5197 /* cache info: needed for Core compatibility */ 5198 if (cpu->cache_info_passthrough) { 5199 host_cpuid(index, count, eax, ebx, ecx, edx); 5200 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ 5201 *eax &= ~0xFC000000; 5202 if ((*eax & 31) && cs->nr_cores > 1) { 5203 *eax |= (cs->nr_cores - 1) << 26; 5204 } 5205 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5206 *eax = *ebx = *ecx = *edx = 0; 5207 } else { 5208 *eax = 0; 5209 switch (count) { 5210 case 0: /* L1 dcache info */ 5211 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5212 1, cs->nr_cores, 5213 eax, ebx, ecx, edx); 5214 break; 5215 case 1: /* L1 icache info */ 5216 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5217 1, cs->nr_cores, 5218 eax, ebx, ecx, edx); 5219 break; 5220 case 2: /* L2 cache info */ 5221 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5222 cs->nr_threads, cs->nr_cores, 5223 eax, ebx, ecx, edx); 5224 break; 5225 case 3: /* L3 cache info */ 5226 die_offset = apicid_die_offset(&topo_info); 5227 if (cpu->enable_l3_cache) { 5228 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5229 (1 << die_offset), cs->nr_cores, 5230 eax, ebx, ecx, edx); 5231 break; 5232 } 5233 /* fall through */ 5234 default: /* end of info */ 5235 *eax = *ebx = *ecx = *edx = 0; 5236 break; 5237 } 5238 } 5239 break; 5240 case 5: 5241 /* MONITOR/MWAIT Leaf */ 5242 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5243 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5244 *ecx = cpu->mwait.ecx; /* flags */ 5245 *edx = cpu->mwait.edx; /* mwait substates */ 5246 break; 5247 case 6: 5248 /* Thermal and Power Leaf */ 5249 *eax = env->features[FEAT_6_EAX]; 5250 *ebx = 0; 5251 *ecx = 0; 5252 *edx = 0; 5253 break; 5254 case 7: 5255 /* Structured Extended Feature Flags Enumeration Leaf */ 5256 if (count == 0) { 5257 /* Maximum ECX value for sub-leaves */ 5258 *eax = env->cpuid_level_func7; 5259 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5260 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5261 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5262 *ecx |= CPUID_7_0_ECX_OSPKE; 5263 } 5264 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5265 } else if (count == 1) { 5266 *eax = env->features[FEAT_7_1_EAX]; 5267 *ebx = 0; 5268 *ecx = 0; 5269 *edx = 0; 5270 } else { 5271 *eax = 0; 5272 *ebx = 0; 5273 *ecx = 0; 5274 *edx = 0; 5275 } 5276 break; 5277 case 9: 5278 /* Direct Cache Access Information Leaf */ 5279 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5280 *ebx = 0; 5281 *ecx = 0; 5282 *edx = 0; 5283 break; 5284 case 0xA: 5285 /* Architectural Performance Monitoring Leaf */ 5286 if (kvm_enabled() && cpu->enable_pmu) { 5287 KVMState *s = cs->kvm_state; 5288 5289 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); 5290 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); 5291 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); 5292 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); 5293 } else if (hvf_enabled() && cpu->enable_pmu) { 5294 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX); 5295 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX); 5296 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX); 5297 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX); 5298 } else { 5299 *eax = 0; 5300 *ebx = 0; 5301 *ecx = 0; 5302 *edx = 0; 5303 } 5304 break; 5305 case 0xB: 5306 /* Extended Topology Enumeration Leaf */ 5307 if (!cpu->enable_cpuid_0xb) { 5308 *eax = *ebx = *ecx = *edx = 0; 5309 break; 5310 } 5311 5312 *ecx = count & 0xff; 5313 *edx = cpu->apic_id; 5314 5315 switch (count) { 5316 case 0: 5317 *eax = apicid_core_offset(&topo_info); 5318 *ebx = cs->nr_threads; 5319 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5320 break; 5321 case 1: 5322 *eax = apicid_pkg_offset(&topo_info); 5323 *ebx = cs->nr_cores * cs->nr_threads; 5324 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5325 break; 5326 default: 5327 *eax = 0; 5328 *ebx = 0; 5329 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5330 } 5331 5332 assert(!(*eax & ~0x1f)); 5333 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5334 break; 5335 case 0x1F: 5336 /* V2 Extended Topology Enumeration Leaf */ 5337 if (env->nr_dies < 2) { 5338 *eax = *ebx = *ecx = *edx = 0; 5339 break; 5340 } 5341 5342 *ecx = count & 0xff; 5343 *edx = cpu->apic_id; 5344 switch (count) { 5345 case 0: 5346 *eax = apicid_core_offset(&topo_info); 5347 *ebx = cs->nr_threads; 5348 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5349 break; 5350 case 1: 5351 *eax = apicid_die_offset(&topo_info); 5352 *ebx = cs->nr_cores * cs->nr_threads; 5353 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5354 break; 5355 case 2: 5356 *eax = apicid_pkg_offset(&topo_info); 5357 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5358 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5359 break; 5360 default: 5361 *eax = 0; 5362 *ebx = 0; 5363 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5364 } 5365 assert(!(*eax & ~0x1f)); 5366 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5367 break; 5368 case 0xD: { 5369 /* Processor Extended State */ 5370 *eax = 0; 5371 *ebx = 0; 5372 *ecx = 0; 5373 *edx = 0; 5374 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5375 break; 5376 } 5377 5378 if (count == 0) { 5379 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu)); 5380 *eax = env->features[FEAT_XSAVE_COMP_LO]; 5381 *edx = env->features[FEAT_XSAVE_COMP_HI]; 5382 /* 5383 * The initial value of xcr0 and ebx == 0, On host without kvm 5384 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5385 * even through guest update xcr0, this will crash some legacy guest 5386 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5387 */ 5388 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); 5389 } else if (count == 1) { 5390 *eax = env->features[FEAT_XSAVE]; 5391 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5392 if ((x86_cpu_xsave_components(cpu) >> count) & 1) { 5393 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5394 *eax = esa->size; 5395 *ebx = esa->offset; 5396 } 5397 } 5398 break; 5399 } 5400 case 0x14: { 5401 /* Intel Processor Trace Enumeration */ 5402 *eax = 0; 5403 *ebx = 0; 5404 *ecx = 0; 5405 *edx = 0; 5406 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5407 !kvm_enabled()) { 5408 break; 5409 } 5410 5411 if (count == 0) { 5412 *eax = INTEL_PT_MAX_SUBLEAF; 5413 *ebx = INTEL_PT_MINIMAL_EBX; 5414 *ecx = INTEL_PT_MINIMAL_ECX; 5415 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 5416 *ecx |= CPUID_14_0_ECX_LIP; 5417 } 5418 } else if (count == 1) { 5419 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5420 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5421 } 5422 break; 5423 } 5424 case 0x40000000: 5425 /* 5426 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5427 * set here, but we restrict to TCG none the less. 5428 */ 5429 if (tcg_enabled() && cpu->expose_tcg) { 5430 memcpy(signature, "TCGTCGTCGTCG", 12); 5431 *eax = 0x40000001; 5432 *ebx = signature[0]; 5433 *ecx = signature[1]; 5434 *edx = signature[2]; 5435 } else { 5436 *eax = 0; 5437 *ebx = 0; 5438 *ecx = 0; 5439 *edx = 0; 5440 } 5441 break; 5442 case 0x40000001: 5443 *eax = 0; 5444 *ebx = 0; 5445 *ecx = 0; 5446 *edx = 0; 5447 break; 5448 case 0x80000000: 5449 *eax = env->cpuid_xlevel; 5450 *ebx = env->cpuid_vendor1; 5451 *edx = env->cpuid_vendor2; 5452 *ecx = env->cpuid_vendor3; 5453 break; 5454 case 0x80000001: 5455 *eax = env->cpuid_version; 5456 *ebx = 0; 5457 *ecx = env->features[FEAT_8000_0001_ECX]; 5458 *edx = env->features[FEAT_8000_0001_EDX]; 5459 5460 /* The Linux kernel checks for the CMPLegacy bit and 5461 * discards multiple thread information if it is set. 5462 * So don't set it here for Intel to make Linux guests happy. 5463 */ 5464 if (cs->nr_cores * cs->nr_threads > 1) { 5465 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5466 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5467 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5468 *ecx |= 1 << 1; /* CmpLegacy bit */ 5469 } 5470 } 5471 break; 5472 case 0x80000002: 5473 case 0x80000003: 5474 case 0x80000004: 5475 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5476 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5477 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5478 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5479 break; 5480 case 0x80000005: 5481 /* cache info (L1 cache) */ 5482 if (cpu->cache_info_passthrough) { 5483 host_cpuid(index, 0, eax, ebx, ecx, edx); 5484 break; 5485 } 5486 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5487 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5488 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5489 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5490 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5491 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5492 break; 5493 case 0x80000006: 5494 /* cache info (L2 cache) */ 5495 if (cpu->cache_info_passthrough) { 5496 host_cpuid(index, 0, eax, ebx, ecx, edx); 5497 break; 5498 } 5499 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5500 (L2_DTLB_2M_ENTRIES << 16) | 5501 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5502 (L2_ITLB_2M_ENTRIES); 5503 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5504 (L2_DTLB_4K_ENTRIES << 16) | 5505 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5506 (L2_ITLB_4K_ENTRIES); 5507 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5508 cpu->enable_l3_cache ? 5509 env->cache_info_amd.l3_cache : NULL, 5510 ecx, edx); 5511 break; 5512 case 0x80000007: 5513 *eax = 0; 5514 *ebx = 0; 5515 *ecx = 0; 5516 *edx = env->features[FEAT_8000_0007_EDX]; 5517 break; 5518 case 0x80000008: 5519 /* virtual & phys address size in low 2 bytes. */ 5520 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5521 /* 64 bit processor */ 5522 *eax = cpu->phys_bits; /* configurable physical bits */ 5523 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5524 *eax |= 0x00003900; /* 57 bits virtual */ 5525 } else { 5526 *eax |= 0x00003000; /* 48 bits virtual */ 5527 } 5528 } else { 5529 *eax = cpu->phys_bits; 5530 } 5531 *ebx = env->features[FEAT_8000_0008_EBX]; 5532 if (cs->nr_cores * cs->nr_threads > 1) { 5533 /* 5534 * Bits 15:12 is "The number of bits in the initial 5535 * Core::X86::Apic::ApicId[ApicId] value that indicate 5536 * thread ID within a package". 5537 * Bits 7:0 is "The number of threads in the package is NC+1" 5538 */ 5539 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 5540 ((cs->nr_cores * cs->nr_threads) - 1); 5541 } else { 5542 *ecx = 0; 5543 } 5544 *edx = 0; 5545 break; 5546 case 0x8000000A: 5547 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5548 *eax = 0x00000001; /* SVM Revision */ 5549 *ebx = 0x00000010; /* nr of ASIDs */ 5550 *ecx = 0; 5551 *edx = env->features[FEAT_SVM]; /* optional features */ 5552 } else { 5553 *eax = 0; 5554 *ebx = 0; 5555 *ecx = 0; 5556 *edx = 0; 5557 } 5558 break; 5559 case 0x8000001D: 5560 *eax = 0; 5561 if (cpu->cache_info_passthrough) { 5562 host_cpuid(index, count, eax, ebx, ecx, edx); 5563 break; 5564 } 5565 switch (count) { 5566 case 0: /* L1 dcache info */ 5567 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5568 &topo_info, eax, ebx, ecx, edx); 5569 break; 5570 case 1: /* L1 icache info */ 5571 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5572 &topo_info, eax, ebx, ecx, edx); 5573 break; 5574 case 2: /* L2 cache info */ 5575 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5576 &topo_info, eax, ebx, ecx, edx); 5577 break; 5578 case 3: /* L3 cache info */ 5579 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5580 &topo_info, eax, ebx, ecx, edx); 5581 break; 5582 default: /* end of info */ 5583 *eax = *ebx = *ecx = *edx = 0; 5584 break; 5585 } 5586 break; 5587 case 0x8000001E: 5588 if (cpu->core_id <= 255) { 5589 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 5590 } else { 5591 *eax = 0; 5592 *ebx = 0; 5593 *ecx = 0; 5594 *edx = 0; 5595 } 5596 break; 5597 case 0xC0000000: 5598 *eax = env->cpuid_xlevel2; 5599 *ebx = 0; 5600 *ecx = 0; 5601 *edx = 0; 5602 break; 5603 case 0xC0000001: 5604 /* Support for VIA CPU's CPUID instruction */ 5605 *eax = env->cpuid_version; 5606 *ebx = 0; 5607 *ecx = 0; 5608 *edx = env->features[FEAT_C000_0001_EDX]; 5609 break; 5610 case 0xC0000002: 5611 case 0xC0000003: 5612 case 0xC0000004: 5613 /* Reserved for the future, and now filled with zero */ 5614 *eax = 0; 5615 *ebx = 0; 5616 *ecx = 0; 5617 *edx = 0; 5618 break; 5619 case 0x8000001F: 5620 *eax = sev_enabled() ? 0x2 : 0; 5621 *eax |= sev_es_enabled() ? 0x8 : 0; 5622 *ebx = sev_get_cbit_position(); 5623 *ebx |= sev_get_reduced_phys_bits() << 6; 5624 *ecx = 0; 5625 *edx = 0; 5626 break; 5627 default: 5628 /* reserved values: zero */ 5629 *eax = 0; 5630 *ebx = 0; 5631 *ecx = 0; 5632 *edx = 0; 5633 break; 5634 } 5635 } 5636 5637 static void x86_cpu_reset(DeviceState *dev) 5638 { 5639 CPUState *s = CPU(dev); 5640 X86CPU *cpu = X86_CPU(s); 5641 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 5642 CPUX86State *env = &cpu->env; 5643 target_ulong cr4; 5644 uint64_t xcr0; 5645 int i; 5646 5647 xcc->parent_reset(dev); 5648 5649 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 5650 5651 env->old_exception = -1; 5652 5653 /* init to reset state */ 5654 5655 env->hflags2 |= HF2_GIF_MASK; 5656 env->hflags &= ~HF_GUEST_MASK; 5657 5658 cpu_x86_update_cr0(env, 0x60000010); 5659 env->a20_mask = ~0x0; 5660 env->smbase = 0x30000; 5661 env->msr_smi_count = 0; 5662 5663 env->idt.limit = 0xffff; 5664 env->gdt.limit = 0xffff; 5665 env->ldt.limit = 0xffff; 5666 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 5667 env->tr.limit = 0xffff; 5668 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 5669 5670 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 5671 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 5672 DESC_R_MASK | DESC_A_MASK); 5673 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 5674 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5675 DESC_A_MASK); 5676 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 5677 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5678 DESC_A_MASK); 5679 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 5680 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5681 DESC_A_MASK); 5682 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 5683 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5684 DESC_A_MASK); 5685 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 5686 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5687 DESC_A_MASK); 5688 5689 env->eip = 0xfff0; 5690 env->regs[R_EDX] = env->cpuid_version; 5691 5692 env->eflags = 0x2; 5693 5694 /* FPU init */ 5695 for (i = 0; i < 8; i++) { 5696 env->fptags[i] = 1; 5697 } 5698 cpu_set_fpuc(env, 0x37f); 5699 5700 env->mxcsr = 0x1f80; 5701 /* All units are in INIT state. */ 5702 env->xstate_bv = 0; 5703 5704 env->pat = 0x0007040600070406ULL; 5705 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 5706 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 5707 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 5708 } 5709 5710 memset(env->dr, 0, sizeof(env->dr)); 5711 env->dr[6] = DR6_FIXED_1; 5712 env->dr[7] = DR7_FIXED_1; 5713 cpu_breakpoint_remove_all(s, BP_CPU); 5714 cpu_watchpoint_remove_all(s, BP_CPU); 5715 5716 cr4 = 0; 5717 xcr0 = XSTATE_FP_MASK; 5718 5719 #ifdef CONFIG_USER_ONLY 5720 /* Enable all the features for user-mode. */ 5721 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 5722 xcr0 |= XSTATE_SSE_MASK; 5723 } 5724 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 5725 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 5726 if (env->features[esa->feature] & esa->bits) { 5727 xcr0 |= 1ull << i; 5728 } 5729 } 5730 5731 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 5732 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 5733 } 5734 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 5735 cr4 |= CR4_FSGSBASE_MASK; 5736 } 5737 #endif 5738 5739 env->xcr0 = xcr0; 5740 cpu_x86_update_cr4(env, cr4); 5741 5742 /* 5743 * SDM 11.11.5 requires: 5744 * - IA32_MTRR_DEF_TYPE MSR.E = 0 5745 * - IA32_MTRR_PHYSMASKn.V = 0 5746 * All other bits are undefined. For simplification, zero it all. 5747 */ 5748 env->mtrr_deftype = 0; 5749 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 5750 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 5751 5752 env->interrupt_injected = -1; 5753 env->exception_nr = -1; 5754 env->exception_pending = 0; 5755 env->exception_injected = 0; 5756 env->exception_has_payload = false; 5757 env->exception_payload = 0; 5758 env->nmi_injected = false; 5759 #if !defined(CONFIG_USER_ONLY) 5760 /* We hard-wire the BSP to the first CPU. */ 5761 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 5762 5763 s->halted = !cpu_is_bsp(cpu); 5764 5765 if (kvm_enabled()) { 5766 kvm_arch_reset_vcpu(cpu); 5767 } 5768 #endif 5769 } 5770 5771 static void mce_init(X86CPU *cpu) 5772 { 5773 CPUX86State *cenv = &cpu->env; 5774 unsigned int bank; 5775 5776 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 5777 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 5778 (CPUID_MCE | CPUID_MCA)) { 5779 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 5780 (cpu->enable_lmce ? MCG_LMCE_P : 0); 5781 cenv->mcg_ctl = ~(uint64_t)0; 5782 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 5783 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 5784 } 5785 } 5786 } 5787 5788 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 5789 { 5790 if (*min < value) { 5791 *min = value; 5792 } 5793 } 5794 5795 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 5796 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 5797 { 5798 CPUX86State *env = &cpu->env; 5799 FeatureWordInfo *fi = &feature_word_info[w]; 5800 uint32_t eax = fi->cpuid.eax; 5801 uint32_t region = eax & 0xF0000000; 5802 5803 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 5804 if (!env->features[w]) { 5805 return; 5806 } 5807 5808 switch (region) { 5809 case 0x00000000: 5810 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 5811 break; 5812 case 0x80000000: 5813 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 5814 break; 5815 case 0xC0000000: 5816 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 5817 break; 5818 } 5819 5820 if (eax == 7) { 5821 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 5822 fi->cpuid.ecx); 5823 } 5824 } 5825 5826 /* Calculate XSAVE components based on the configured CPU feature flags */ 5827 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 5828 { 5829 CPUX86State *env = &cpu->env; 5830 int i; 5831 uint64_t mask; 5832 5833 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5834 env->features[FEAT_XSAVE_COMP_LO] = 0; 5835 env->features[FEAT_XSAVE_COMP_HI] = 0; 5836 return; 5837 } 5838 5839 mask = 0; 5840 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 5841 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 5842 if (env->features[esa->feature] & esa->bits) { 5843 mask |= (1ULL << i); 5844 } 5845 } 5846 5847 env->features[FEAT_XSAVE_COMP_LO] = mask; 5848 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32; 5849 } 5850 5851 /***** Steps involved on loading and filtering CPUID data 5852 * 5853 * When initializing and realizing a CPU object, the steps 5854 * involved in setting up CPUID data are: 5855 * 5856 * 1) Loading CPU model definition (X86CPUDefinition). This is 5857 * implemented by x86_cpu_load_model() and should be completely 5858 * transparent, as it is done automatically by instance_init. 5859 * No code should need to look at X86CPUDefinition structs 5860 * outside instance_init. 5861 * 5862 * 2) CPU expansion. This is done by realize before CPUID 5863 * filtering, and will make sure host/accelerator data is 5864 * loaded for CPU models that depend on host capabilities 5865 * (e.g. "host"). Done by x86_cpu_expand_features(). 5866 * 5867 * 3) CPUID filtering. This initializes extra data related to 5868 * CPUID, and checks if the host supports all capabilities 5869 * required by the CPU. Runnability of a CPU model is 5870 * determined at this step. Done by x86_cpu_filter_features(). 5871 * 5872 * Some operations don't require all steps to be performed. 5873 * More precisely: 5874 * 5875 * - CPU instance creation (instance_init) will run only CPU 5876 * model loading. CPU expansion can't run at instance_init-time 5877 * because host/accelerator data may be not available yet. 5878 * - CPU realization will perform both CPU model expansion and CPUID 5879 * filtering, and return an error in case one of them fails. 5880 * - query-cpu-definitions needs to run all 3 steps. It needs 5881 * to run CPUID filtering, as the 'unavailable-features' 5882 * field is set based on the filtering results. 5883 * - The query-cpu-model-expansion QMP command only needs to run 5884 * CPU model loading and CPU expansion. It should not filter 5885 * any CPUID data based on host capabilities. 5886 */ 5887 5888 /* Expand CPU configuration data, based on configured features 5889 * and host/accelerator capabilities when appropriate. 5890 */ 5891 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 5892 { 5893 CPUX86State *env = &cpu->env; 5894 FeatureWord w; 5895 int i; 5896 GList *l; 5897 5898 for (l = plus_features; l; l = l->next) { 5899 const char *prop = l->data; 5900 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 5901 return; 5902 } 5903 } 5904 5905 for (l = minus_features; l; l = l->next) { 5906 const char *prop = l->data; 5907 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 5908 return; 5909 } 5910 } 5911 5912 /*TODO: Now cpu->max_features doesn't overwrite features 5913 * set using QOM properties, and we can convert 5914 * plus_features & minus_features to global properties 5915 * inside x86_cpu_parse_featurestr() too. 5916 */ 5917 if (cpu->max_features) { 5918 for (w = 0; w < FEATURE_WORDS; w++) { 5919 /* Override only features that weren't set explicitly 5920 * by the user. 5921 */ 5922 env->features[w] |= 5923 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 5924 ~env->user_features[w] & 5925 ~feature_word_info[w].no_autoenable_flags; 5926 } 5927 } 5928 5929 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 5930 FeatureDep *d = &feature_dependencies[i]; 5931 if (!(env->features[d->from.index] & d->from.mask)) { 5932 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 5933 5934 /* Not an error unless the dependent feature was added explicitly. */ 5935 mark_unavailable_features(cpu, d->to.index, 5936 unavailable_features & env->user_features[d->to.index], 5937 "This feature depends on other features that were not requested"); 5938 5939 env->features[d->to.index] &= ~unavailable_features; 5940 } 5941 } 5942 5943 if (!kvm_enabled() || !cpu->expose_kvm) { 5944 env->features[FEAT_KVM] = 0; 5945 } 5946 5947 x86_cpu_enable_xsave_components(cpu); 5948 5949 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 5950 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 5951 if (cpu->full_cpuid_auto_level) { 5952 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 5953 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 5954 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 5955 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 5956 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 5957 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 5958 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 5959 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 5960 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 5961 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 5962 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 5963 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 5964 5965 /* Intel Processor Trace requires CPUID[0x14] */ 5966 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 5967 if (cpu->intel_pt_auto_level) { 5968 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 5969 } else if (cpu->env.cpuid_min_level < 0x14) { 5970 mark_unavailable_features(cpu, FEAT_7_0_EBX, 5971 CPUID_7_0_EBX_INTEL_PT, 5972 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 5973 } 5974 } 5975 5976 /* 5977 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 5978 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 5979 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 5980 * cpu->vendor_cpuid_only has been unset for compatibility with older 5981 * machine types. 5982 */ 5983 if ((env->nr_dies > 1) && 5984 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 5985 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 5986 } 5987 5988 /* SVM requires CPUID[0x8000000A] */ 5989 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5990 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 5991 } 5992 5993 /* SEV requires CPUID[0x8000001F] */ 5994 if (sev_enabled()) { 5995 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 5996 } 5997 } 5998 5999 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6000 if (env->cpuid_level_func7 == UINT32_MAX) { 6001 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6002 } 6003 if (env->cpuid_level == UINT32_MAX) { 6004 env->cpuid_level = env->cpuid_min_level; 6005 } 6006 if (env->cpuid_xlevel == UINT32_MAX) { 6007 env->cpuid_xlevel = env->cpuid_min_xlevel; 6008 } 6009 if (env->cpuid_xlevel2 == UINT32_MAX) { 6010 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6011 } 6012 6013 if (kvm_enabled()) { 6014 kvm_hyperv_expand_features(cpu, errp); 6015 } 6016 } 6017 6018 /* 6019 * Finishes initialization of CPUID data, filters CPU feature 6020 * words based on host availability of each feature. 6021 * 6022 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6023 */ 6024 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6025 { 6026 CPUX86State *env = &cpu->env; 6027 FeatureWord w; 6028 const char *prefix = NULL; 6029 6030 if (verbose) { 6031 prefix = accel_uses_host_cpuid() 6032 ? "host doesn't support requested feature" 6033 : "TCG doesn't support requested feature"; 6034 } 6035 6036 for (w = 0; w < FEATURE_WORDS; w++) { 6037 uint64_t host_feat = 6038 x86_cpu_get_supported_feature_word(w, false); 6039 uint64_t requested_features = env->features[w]; 6040 uint64_t unavailable_features = requested_features & ~host_feat; 6041 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6042 } 6043 6044 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6045 kvm_enabled()) { 6046 KVMState *s = CPU(cpu)->kvm_state; 6047 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6048 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6049 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6050 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6051 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6052 6053 if (!eax_0 || 6054 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6055 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6056 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6057 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6058 INTEL_PT_ADDR_RANGES_NUM) || 6059 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6060 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6061 ((ecx_0 & CPUID_14_0_ECX_LIP) != 6062 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 6063 /* 6064 * Processor Trace capabilities aren't configurable, so if the 6065 * host can't emulate the capabilities we report on 6066 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6067 */ 6068 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6069 } 6070 } 6071 } 6072 6073 static void x86_cpu_hyperv_realize(X86CPU *cpu) 6074 { 6075 size_t len; 6076 6077 /* Hyper-V vendor id */ 6078 if (!cpu->hyperv_vendor) { 6079 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 6080 &error_abort); 6081 } 6082 len = strlen(cpu->hyperv_vendor); 6083 if (len > 12) { 6084 warn_report("hv-vendor-id truncated to 12 characters"); 6085 len = 12; 6086 } 6087 memset(cpu->hyperv_vendor_id, 0, 12); 6088 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 6089 6090 /* 'Hv#1' interface identification*/ 6091 cpu->hyperv_interface_id[0] = 0x31237648; 6092 cpu->hyperv_interface_id[1] = 0; 6093 cpu->hyperv_interface_id[2] = 0; 6094 cpu->hyperv_interface_id[3] = 0; 6095 6096 /* Hypervisor system identity */ 6097 cpu->hyperv_version_id[0] = 0x00001bbc; 6098 cpu->hyperv_version_id[1] = 0x00060001; 6099 6100 /* Hypervisor implementation limits */ 6101 cpu->hyperv_limits[0] = 64; 6102 cpu->hyperv_limits[1] = 0; 6103 cpu->hyperv_limits[2] = 0; 6104 } 6105 6106 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6107 { 6108 CPUState *cs = CPU(dev); 6109 X86CPU *cpu = X86_CPU(dev); 6110 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6111 CPUX86State *env = &cpu->env; 6112 Error *local_err = NULL; 6113 static bool ht_warned; 6114 6115 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6116 error_setg(errp, "apic-id property was not initialized properly"); 6117 return; 6118 } 6119 6120 /* 6121 * Process Hyper-V enlightenments. 6122 * Note: this currently has to happen before the expansion of CPU features. 6123 */ 6124 x86_cpu_hyperv_realize(cpu); 6125 6126 x86_cpu_expand_features(cpu, &local_err); 6127 if (local_err) { 6128 goto out; 6129 } 6130 6131 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6132 6133 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6134 error_setg(&local_err, 6135 accel_uses_host_cpuid() ? 6136 "Host doesn't support requested features" : 6137 "TCG doesn't support requested features"); 6138 goto out; 6139 } 6140 6141 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6142 * CPUID[1].EDX. 6143 */ 6144 if (IS_AMD_CPU(env)) { 6145 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6146 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6147 & CPUID_EXT2_AMD_ALIASES); 6148 } 6149 6150 /* 6151 * note: the call to the framework needs to happen after feature expansion, 6152 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 6153 * These may be set by the accel-specific code, 6154 * and the results are subsequently checked / assumed in this function. 6155 */ 6156 cpu_exec_realizefn(cs, &local_err); 6157 if (local_err != NULL) { 6158 error_propagate(errp, local_err); 6159 return; 6160 } 6161 6162 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6163 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6164 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 6165 goto out; 6166 } 6167 6168 if (cpu->ucode_rev == 0) { 6169 /* 6170 * The default is the same as KVM's. Note that this check 6171 * needs to happen after the evenual setting of ucode_rev in 6172 * accel-specific code in cpu_exec_realizefn. 6173 */ 6174 if (IS_AMD_CPU(env)) { 6175 cpu->ucode_rev = 0x01000065; 6176 } else { 6177 cpu->ucode_rev = 0x100000000ULL; 6178 } 6179 } 6180 6181 /* 6182 * mwait extended info: needed for Core compatibility 6183 * We always wake on interrupt even if host does not have the capability. 6184 * 6185 * requires the accel-specific code in cpu_exec_realizefn to 6186 * have already acquired the CPUID data into cpu->mwait. 6187 */ 6188 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6189 6190 /* For 64bit systems think about the number of physical bits to present. 6191 * ideally this should be the same as the host; anything other than matching 6192 * the host can cause incorrect guest behaviour. 6193 * QEMU used to pick the magic value of 40 bits that corresponds to 6194 * consumer AMD devices but nothing else. 6195 * 6196 * Note that this code assumes features expansion has already been done 6197 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 6198 * phys_bits adjustments to match the host have been already done in 6199 * accel-specific code in cpu_exec_realizefn. 6200 */ 6201 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6202 if (cpu->phys_bits && 6203 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6204 cpu->phys_bits < 32)) { 6205 error_setg(errp, "phys-bits should be between 32 and %u " 6206 " (but is %u)", 6207 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6208 return; 6209 } 6210 /* 6211 * 0 means it was not explicitly set by the user (or by machine 6212 * compat_props or by the host code in host-cpu.c). 6213 * In this case, the default is the value used by TCG (40). 6214 */ 6215 if (cpu->phys_bits == 0) { 6216 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6217 } 6218 } else { 6219 /* For 32 bit systems don't use the user set value, but keep 6220 * phys_bits consistent with what we tell the guest. 6221 */ 6222 if (cpu->phys_bits != 0) { 6223 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6224 return; 6225 } 6226 6227 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6228 cpu->phys_bits = 36; 6229 } else { 6230 cpu->phys_bits = 32; 6231 } 6232 } 6233 6234 /* Cache information initialization */ 6235 if (!cpu->legacy_cache) { 6236 if (!xcc->model || !xcc->model->cpudef->cache_info) { 6237 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6238 error_setg(errp, 6239 "CPU model '%s' doesn't support legacy-cache=off", name); 6240 return; 6241 } 6242 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6243 *xcc->model->cpudef->cache_info; 6244 } else { 6245 /* Build legacy cache information */ 6246 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6247 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6248 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6249 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6250 6251 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6252 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6253 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6254 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6255 6256 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6257 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6258 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6259 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6260 } 6261 6262 #ifndef CONFIG_USER_ONLY 6263 MachineState *ms = MACHINE(qdev_get_machine()); 6264 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6265 6266 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6267 x86_cpu_apic_create(cpu, &local_err); 6268 if (local_err != NULL) { 6269 goto out; 6270 } 6271 } 6272 #endif 6273 6274 mce_init(cpu); 6275 6276 qemu_init_vcpu(cs); 6277 6278 /* 6279 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6280 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6281 * based on inputs (sockets,cores,threads), it is still better to give 6282 * users a warning. 6283 * 6284 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6285 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6286 */ 6287 if (IS_AMD_CPU(env) && 6288 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6289 cs->nr_threads > 1 && !ht_warned) { 6290 warn_report("This family of AMD CPU doesn't support " 6291 "hyperthreading(%d)", 6292 cs->nr_threads); 6293 error_printf("Please configure -smp options properly" 6294 " or try enabling topoext feature.\n"); 6295 ht_warned = true; 6296 } 6297 6298 #ifndef CONFIG_USER_ONLY 6299 x86_cpu_apic_realize(cpu, &local_err); 6300 if (local_err != NULL) { 6301 goto out; 6302 } 6303 #endif /* !CONFIG_USER_ONLY */ 6304 cpu_reset(cs); 6305 6306 xcc->parent_realize(dev, &local_err); 6307 6308 out: 6309 if (local_err != NULL) { 6310 error_propagate(errp, local_err); 6311 return; 6312 } 6313 } 6314 6315 static void x86_cpu_unrealizefn(DeviceState *dev) 6316 { 6317 X86CPU *cpu = X86_CPU(dev); 6318 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6319 6320 #ifndef CONFIG_USER_ONLY 6321 cpu_remove_sync(CPU(dev)); 6322 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6323 #endif 6324 6325 if (cpu->apic_state) { 6326 object_unparent(OBJECT(cpu->apic_state)); 6327 cpu->apic_state = NULL; 6328 } 6329 6330 xcc->parent_unrealize(dev); 6331 } 6332 6333 typedef struct BitProperty { 6334 FeatureWord w; 6335 uint64_t mask; 6336 } BitProperty; 6337 6338 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6339 void *opaque, Error **errp) 6340 { 6341 X86CPU *cpu = X86_CPU(obj); 6342 BitProperty *fp = opaque; 6343 uint64_t f = cpu->env.features[fp->w]; 6344 bool value = (f & fp->mask) == fp->mask; 6345 visit_type_bool(v, name, &value, errp); 6346 } 6347 6348 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6349 void *opaque, Error **errp) 6350 { 6351 DeviceState *dev = DEVICE(obj); 6352 X86CPU *cpu = X86_CPU(obj); 6353 BitProperty *fp = opaque; 6354 bool value; 6355 6356 if (dev->realized) { 6357 qdev_prop_set_after_realize(dev, name, errp); 6358 return; 6359 } 6360 6361 if (!visit_type_bool(v, name, &value, errp)) { 6362 return; 6363 } 6364 6365 if (value) { 6366 cpu->env.features[fp->w] |= fp->mask; 6367 } else { 6368 cpu->env.features[fp->w] &= ~fp->mask; 6369 } 6370 cpu->env.user_features[fp->w] |= fp->mask; 6371 } 6372 6373 /* Register a boolean property to get/set a single bit in a uint32_t field. 6374 * 6375 * The same property name can be registered multiple times to make it affect 6376 * multiple bits in the same FeatureWord. In that case, the getter will return 6377 * true only if all bits are set. 6378 */ 6379 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 6380 const char *prop_name, 6381 FeatureWord w, 6382 int bitnr) 6383 { 6384 ObjectClass *oc = OBJECT_CLASS(xcc); 6385 BitProperty *fp; 6386 ObjectProperty *op; 6387 uint64_t mask = (1ULL << bitnr); 6388 6389 op = object_class_property_find(oc, prop_name); 6390 if (op) { 6391 fp = op->opaque; 6392 assert(fp->w == w); 6393 fp->mask |= mask; 6394 } else { 6395 fp = g_new0(BitProperty, 1); 6396 fp->w = w; 6397 fp->mask = mask; 6398 object_class_property_add(oc, prop_name, "bool", 6399 x86_cpu_get_bit_prop, 6400 x86_cpu_set_bit_prop, 6401 NULL, fp); 6402 } 6403 } 6404 6405 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 6406 FeatureWord w, 6407 int bitnr) 6408 { 6409 FeatureWordInfo *fi = &feature_word_info[w]; 6410 const char *name = fi->feat_names[bitnr]; 6411 6412 if (!name) { 6413 return; 6414 } 6415 6416 /* Property names should use "-" instead of "_". 6417 * Old names containing underscores are registered as aliases 6418 * using object_property_add_alias() 6419 */ 6420 assert(!strchr(name, '_')); 6421 /* aliases don't use "|" delimiters anymore, they are registered 6422 * manually using object_property_add_alias() */ 6423 assert(!strchr(name, '|')); 6424 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 6425 } 6426 6427 static void x86_cpu_post_initfn(Object *obj) 6428 { 6429 accel_cpu_instance_init(CPU(obj)); 6430 } 6431 6432 static void x86_cpu_initfn(Object *obj) 6433 { 6434 X86CPU *cpu = X86_CPU(obj); 6435 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6436 CPUX86State *env = &cpu->env; 6437 6438 env->nr_dies = 1; 6439 cpu_set_cpustate_pointers(cpu); 6440 6441 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6442 x86_cpu_get_feature_words, 6443 NULL, NULL, (void *)env->features); 6444 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6445 x86_cpu_get_feature_words, 6446 NULL, NULL, (void *)cpu->filtered_features); 6447 6448 object_property_add_alias(obj, "sse3", obj, "pni"); 6449 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6450 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6451 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6452 object_property_add_alias(obj, "xd", obj, "nx"); 6453 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6454 object_property_add_alias(obj, "i64", obj, "lm"); 6455 6456 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 6457 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 6458 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 6459 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 6460 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 6461 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 6462 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 6463 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 6464 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 6465 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 6466 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 6467 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 6468 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 6469 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 6470 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 6471 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 6472 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 6473 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 6474 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 6475 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 6476 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 6477 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 6478 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 6479 6480 if (xcc->model) { 6481 x86_cpu_load_model(cpu, xcc->model); 6482 } 6483 } 6484 6485 static int64_t x86_cpu_get_arch_id(CPUState *cs) 6486 { 6487 X86CPU *cpu = X86_CPU(cs); 6488 6489 return cpu->apic_id; 6490 } 6491 6492 #if !defined(CONFIG_USER_ONLY) 6493 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 6494 { 6495 X86CPU *cpu = X86_CPU(cs); 6496 6497 return cpu->env.cr[0] & CR0_PG_MASK; 6498 } 6499 #endif /* !CONFIG_USER_ONLY */ 6500 6501 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 6502 { 6503 X86CPU *cpu = X86_CPU(cs); 6504 6505 cpu->env.eip = value; 6506 } 6507 6508 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 6509 { 6510 X86CPU *cpu = X86_CPU(cs); 6511 CPUX86State *env = &cpu->env; 6512 6513 #if !defined(CONFIG_USER_ONLY) 6514 if (interrupt_request & CPU_INTERRUPT_POLL) { 6515 return CPU_INTERRUPT_POLL; 6516 } 6517 #endif 6518 if (interrupt_request & CPU_INTERRUPT_SIPI) { 6519 return CPU_INTERRUPT_SIPI; 6520 } 6521 6522 if (env->hflags2 & HF2_GIF_MASK) { 6523 if ((interrupt_request & CPU_INTERRUPT_SMI) && 6524 !(env->hflags & HF_SMM_MASK)) { 6525 return CPU_INTERRUPT_SMI; 6526 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 6527 !(env->hflags2 & HF2_NMI_MASK)) { 6528 return CPU_INTERRUPT_NMI; 6529 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 6530 return CPU_INTERRUPT_MCE; 6531 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 6532 (((env->hflags2 & HF2_VINTR_MASK) && 6533 (env->hflags2 & HF2_HIF_MASK)) || 6534 (!(env->hflags2 & HF2_VINTR_MASK) && 6535 (env->eflags & IF_MASK && 6536 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 6537 return CPU_INTERRUPT_HARD; 6538 #if !defined(CONFIG_USER_ONLY) 6539 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && 6540 (env->eflags & IF_MASK) && 6541 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 6542 return CPU_INTERRUPT_VIRQ; 6543 #endif 6544 } 6545 } 6546 6547 return 0; 6548 } 6549 6550 static bool x86_cpu_has_work(CPUState *cs) 6551 { 6552 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 6553 } 6554 6555 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 6556 { 6557 X86CPU *cpu = X86_CPU(cs); 6558 CPUX86State *env = &cpu->env; 6559 6560 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 6561 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 6562 : bfd_mach_i386_i8086); 6563 info->print_insn = print_insn_i386; 6564 6565 info->cap_arch = CS_ARCH_X86; 6566 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 6567 : env->hflags & HF_CS32_MASK ? CS_MODE_32 6568 : CS_MODE_16); 6569 info->cap_insn_unit = 1; 6570 info->cap_insn_split = 8; 6571 } 6572 6573 void x86_update_hflags(CPUX86State *env) 6574 { 6575 uint32_t hflags; 6576 #define HFLAG_COPY_MASK \ 6577 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 6578 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 6579 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 6580 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 6581 6582 hflags = env->hflags & HFLAG_COPY_MASK; 6583 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 6584 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 6585 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 6586 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 6587 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 6588 6589 if (env->cr[4] & CR4_OSFXSR_MASK) { 6590 hflags |= HF_OSFXSR_MASK; 6591 } 6592 6593 if (env->efer & MSR_EFER_LMA) { 6594 hflags |= HF_LMA_MASK; 6595 } 6596 6597 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 6598 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 6599 } else { 6600 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 6601 (DESC_B_SHIFT - HF_CS32_SHIFT); 6602 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 6603 (DESC_B_SHIFT - HF_SS32_SHIFT); 6604 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 6605 !(hflags & HF_CS32_MASK)) { 6606 hflags |= HF_ADDSEG_MASK; 6607 } else { 6608 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 6609 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 6610 } 6611 } 6612 env->hflags = hflags; 6613 } 6614 6615 static Property x86_cpu_properties[] = { 6616 #ifdef CONFIG_USER_ONLY 6617 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 6618 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 6619 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 6620 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 6621 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 6622 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 6623 #else 6624 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 6625 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 6626 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 6627 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 6628 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 6629 #endif 6630 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 6631 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 6632 6633 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 6634 HYPERV_SPINLOCK_NEVER_NOTIFY), 6635 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 6636 HYPERV_FEAT_RELAXED, 0), 6637 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 6638 HYPERV_FEAT_VAPIC, 0), 6639 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 6640 HYPERV_FEAT_TIME, 0), 6641 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 6642 HYPERV_FEAT_CRASH, 0), 6643 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 6644 HYPERV_FEAT_RESET, 0), 6645 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 6646 HYPERV_FEAT_VPINDEX, 0), 6647 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 6648 HYPERV_FEAT_RUNTIME, 0), 6649 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 6650 HYPERV_FEAT_SYNIC, 0), 6651 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 6652 HYPERV_FEAT_STIMER, 0), 6653 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 6654 HYPERV_FEAT_FREQUENCIES, 0), 6655 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 6656 HYPERV_FEAT_REENLIGHTENMENT, 0), 6657 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 6658 HYPERV_FEAT_TLBFLUSH, 0), 6659 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 6660 HYPERV_FEAT_EVMCS, 0), 6661 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 6662 HYPERV_FEAT_IPI, 0), 6663 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 6664 HYPERV_FEAT_STIMER_DIRECT, 0), 6665 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 6666 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 6667 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 6668 6669 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 6670 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 6671 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 6672 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 6673 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 6674 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 6675 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 6676 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 6677 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 6678 UINT32_MAX), 6679 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 6680 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 6681 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 6682 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 6683 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 6684 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 6685 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 6686 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 6687 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 6688 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 6689 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 6690 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 6691 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 6692 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 6693 false), 6694 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 6695 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 6696 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 6697 true), 6698 /* 6699 * lecacy_cache defaults to true unless the CPU model provides its 6700 * own cache information (see x86_cpu_load_def()). 6701 */ 6702 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 6703 6704 /* 6705 * From "Requirements for Implementing the Microsoft 6706 * Hypervisor Interface": 6707 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 6708 * 6709 * "Starting with Windows Server 2012 and Windows 8, if 6710 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 6711 * the hypervisor imposes no specific limit to the number of VPs. 6712 * In this case, Windows Server 2012 guest VMs may use more than 6713 * 64 VPs, up to the maximum supported number of processors applicable 6714 * to the specific Windows version being used." 6715 */ 6716 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 6717 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 6718 false), 6719 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 6720 true), 6721 DEFINE_PROP_END_OF_LIST() 6722 }; 6723 6724 #ifndef CONFIG_USER_ONLY 6725 #include "hw/core/sysemu-cpu-ops.h" 6726 6727 static const struct SysemuCPUOps i386_sysemu_ops = { 6728 .get_memory_mapping = x86_cpu_get_memory_mapping, 6729 .get_paging_enabled = x86_cpu_get_paging_enabled, 6730 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 6731 .asidx_from_attrs = x86_asidx_from_attrs, 6732 .get_crash_info = x86_cpu_get_crash_info, 6733 .write_elf32_note = x86_cpu_write_elf32_note, 6734 .write_elf64_note = x86_cpu_write_elf64_note, 6735 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 6736 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 6737 .legacy_vmsd = &vmstate_x86_cpu, 6738 }; 6739 #endif 6740 6741 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 6742 { 6743 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6744 CPUClass *cc = CPU_CLASS(oc); 6745 DeviceClass *dc = DEVICE_CLASS(oc); 6746 FeatureWord w; 6747 6748 device_class_set_parent_realize(dc, x86_cpu_realizefn, 6749 &xcc->parent_realize); 6750 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 6751 &xcc->parent_unrealize); 6752 device_class_set_props(dc, x86_cpu_properties); 6753 6754 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); 6755 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 6756 6757 cc->class_by_name = x86_cpu_class_by_name; 6758 cc->parse_features = x86_cpu_parse_featurestr; 6759 cc->has_work = x86_cpu_has_work; 6760 cc->dump_state = x86_cpu_dump_state; 6761 cc->set_pc = x86_cpu_set_pc; 6762 cc->gdb_read_register = x86_cpu_gdb_read_register; 6763 cc->gdb_write_register = x86_cpu_gdb_write_register; 6764 cc->get_arch_id = x86_cpu_get_arch_id; 6765 6766 #ifndef CONFIG_USER_ONLY 6767 cc->sysemu_ops = &i386_sysemu_ops; 6768 #endif /* !CONFIG_USER_ONLY */ 6769 6770 cc->gdb_arch_name = x86_gdb_arch_name; 6771 #ifdef TARGET_X86_64 6772 cc->gdb_core_xml_file = "i386-64bit.xml"; 6773 cc->gdb_num_core_regs = 66; 6774 #else 6775 cc->gdb_core_xml_file = "i386-32bit.xml"; 6776 cc->gdb_num_core_regs = 50; 6777 #endif 6778 cc->disas_set_info = x86_disas_set_info; 6779 6780 dc->user_creatable = true; 6781 6782 object_class_property_add(oc, "family", "int", 6783 x86_cpuid_version_get_family, 6784 x86_cpuid_version_set_family, NULL, NULL); 6785 object_class_property_add(oc, "model", "int", 6786 x86_cpuid_version_get_model, 6787 x86_cpuid_version_set_model, NULL, NULL); 6788 object_class_property_add(oc, "stepping", "int", 6789 x86_cpuid_version_get_stepping, 6790 x86_cpuid_version_set_stepping, NULL, NULL); 6791 object_class_property_add_str(oc, "vendor", 6792 x86_cpuid_get_vendor, 6793 x86_cpuid_set_vendor); 6794 object_class_property_add_str(oc, "model-id", 6795 x86_cpuid_get_model_id, 6796 x86_cpuid_set_model_id); 6797 object_class_property_add(oc, "tsc-frequency", "int", 6798 x86_cpuid_get_tsc_freq, 6799 x86_cpuid_set_tsc_freq, NULL, NULL); 6800 /* 6801 * The "unavailable-features" property has the same semantics as 6802 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 6803 * QMP command: they list the features that would have prevented the 6804 * CPU from running if the "enforce" flag was set. 6805 */ 6806 object_class_property_add(oc, "unavailable-features", "strList", 6807 x86_cpu_get_unavailable_features, 6808 NULL, NULL, NULL); 6809 6810 #if !defined(CONFIG_USER_ONLY) 6811 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 6812 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 6813 #endif 6814 6815 for (w = 0; w < FEATURE_WORDS; w++) { 6816 int bitnr; 6817 for (bitnr = 0; bitnr < 64; bitnr++) { 6818 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 6819 } 6820 } 6821 } 6822 6823 static const TypeInfo x86_cpu_type_info = { 6824 .name = TYPE_X86_CPU, 6825 .parent = TYPE_CPU, 6826 .instance_size = sizeof(X86CPU), 6827 .instance_init = x86_cpu_initfn, 6828 .instance_post_init = x86_cpu_post_initfn, 6829 6830 .abstract = true, 6831 .class_size = sizeof(X86CPUClass), 6832 .class_init = x86_cpu_common_class_init, 6833 }; 6834 6835 6836 /* "base" CPU model, used by query-cpu-model-expansion */ 6837 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 6838 { 6839 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6840 6841 xcc->static_model = true; 6842 xcc->migration_safe = true; 6843 xcc->model_description = "base CPU model type with no features enabled"; 6844 xcc->ordering = 8; 6845 } 6846 6847 static const TypeInfo x86_base_cpu_type_info = { 6848 .name = X86_CPU_TYPE_NAME("base"), 6849 .parent = TYPE_X86_CPU, 6850 .class_init = x86_cpu_base_class_init, 6851 }; 6852 6853 static void x86_cpu_register_types(void) 6854 { 6855 int i; 6856 6857 type_register_static(&x86_cpu_type_info); 6858 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 6859 x86_register_cpudef_types(&builtin_x86_defs[i]); 6860 } 6861 type_register_static(&max_x86_cpu_type_info); 6862 type_register_static(&x86_base_cpu_type_info); 6863 } 6864 6865 type_init(x86_cpu_register_types) 6866