1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/hvf.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "qapi/qapi-commands-machine-target.h" 40 #include "exec/address-spaces.h" 41 #include "hw/boards.h" 42 #include "hw/i386/sgx-epc.h" 43 #endif 44 45 #include "disas/capstone.h" 46 #include "cpu-internal.h" 47 48 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 49 50 /* Helpers for building CPUID[2] descriptors: */ 51 52 struct CPUID2CacheDescriptorInfo { 53 enum CacheType type; 54 int level; 55 int size; 56 int line_size; 57 int associativity; 58 }; 59 60 /* 61 * Known CPUID 2 cache descriptors. 62 * From Intel SDM Volume 2A, CPUID instruction 63 */ 64 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 65 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 66 .associativity = 4, .line_size = 32, }, 67 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 68 .associativity = 4, .line_size = 32, }, 69 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 70 .associativity = 4, .line_size = 64, }, 71 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 72 .associativity = 2, .line_size = 32, }, 73 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 78 .associativity = 6, .line_size = 64, }, 79 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 80 .associativity = 2, .line_size = 64, }, 81 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 82 .associativity = 8, .line_size = 64, }, 83 /* lines per sector is not supported cpuid2_cache_descriptor(), 84 * so descriptors 0x22, 0x23 are not included 85 */ 86 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 87 .associativity = 16, .line_size = 64, }, 88 /* lines per sector is not supported cpuid2_cache_descriptor(), 89 * so descriptors 0x25, 0x20 are not included 90 */ 91 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 94 .associativity = 8, .line_size = 64, }, 95 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 96 .associativity = 4, .line_size = 32, }, 97 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 98 .associativity = 4, .line_size = 32, }, 99 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 106 .associativity = 4, .line_size = 64, }, 107 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 110 .associativity = 12, .line_size = 64, }, 111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 112 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 113 .associativity = 12, .line_size = 64, }, 114 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 115 .associativity = 16, .line_size = 64, }, 116 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 121 .associativity = 24, .line_size = 64, }, 122 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 123 .associativity = 8, .line_size = 64, }, 124 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 125 .associativity = 4, .line_size = 64, }, 126 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 131 .associativity = 4, .line_size = 64, }, 132 /* lines per sector is not supported cpuid2_cache_descriptor(), 133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 134 */ 135 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 136 .associativity = 8, .line_size = 64, }, 137 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 138 .associativity = 2, .line_size = 64, }, 139 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 142 .associativity = 8, .line_size = 32, }, 143 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 32, }, 145 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 4, .line_size = 64, }, 151 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 64, }, 153 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 4, .line_size = 64, }, 157 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 64, }, 161 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 64, }, 163 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 166 .associativity = 12, .line_size = 64, }, 167 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 168 .associativity = 12, .line_size = 64, }, 169 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 16, .line_size = 64, }, 173 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 174 .associativity = 16, .line_size = 64, }, 175 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 178 .associativity = 24, .line_size = 64, }, 179 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 180 .associativity = 24, .line_size = 64, }, 181 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 }; 184 185 /* 186 * "CPUID leaf 2 does not report cache descriptor information, 187 * use CPUID leaf 4 to query cache parameters" 188 */ 189 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 190 191 /* 192 * Return a CPUID 2 cache descriptor for a given cache. 193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 194 */ 195 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 196 { 197 int i; 198 199 assert(cache->size > 0); 200 assert(cache->level > 0); 201 assert(cache->line_size > 0); 202 assert(cache->associativity > 0); 203 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 204 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 205 if (d->level == cache->level && d->type == cache->type && 206 d->size == cache->size && d->line_size == cache->line_size && 207 d->associativity == cache->associativity) { 208 return i; 209 } 210 } 211 212 return CACHE_DESCRIPTOR_UNAVAILABLE; 213 } 214 215 /* CPUID Leaf 4 constants: */ 216 217 /* EAX: */ 218 #define CACHE_TYPE_D 1 219 #define CACHE_TYPE_I 2 220 #define CACHE_TYPE_UNIFIED 3 221 222 #define CACHE_LEVEL(l) (l << 5) 223 224 #define CACHE_SELF_INIT_LEVEL (1 << 8) 225 226 /* EDX: */ 227 #define CACHE_NO_INVD_SHARING (1 << 0) 228 #define CACHE_INCLUSIVE (1 << 1) 229 #define CACHE_COMPLEX_IDX (1 << 2) 230 231 /* Encode CacheType for CPUID[4].EAX */ 232 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 235 0 /* Invalid value */) 236 237 238 /* Encode cache info for CPUID[4] */ 239 static void encode_cache_cpuid4(CPUCacheInfo *cache, 240 int num_apic_ids, int num_cores, 241 uint32_t *eax, uint32_t *ebx, 242 uint32_t *ecx, uint32_t *edx) 243 { 244 assert(cache->size == cache->line_size * cache->associativity * 245 cache->partitions * cache->sets); 246 247 assert(num_apic_ids > 0); 248 *eax = CACHE_TYPE(cache->type) | 249 CACHE_LEVEL(cache->level) | 250 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 251 ((num_cores - 1) << 26) | 252 ((num_apic_ids - 1) << 14); 253 254 assert(cache->line_size > 0); 255 assert(cache->partitions > 0); 256 assert(cache->associativity > 0); 257 /* We don't implement fully-associative caches */ 258 assert(cache->associativity < cache->sets); 259 *ebx = (cache->line_size - 1) | 260 ((cache->partitions - 1) << 12) | 261 ((cache->associativity - 1) << 22); 262 263 assert(cache->sets > 0); 264 *ecx = cache->sets - 1; 265 266 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 267 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 268 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 269 } 270 271 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 272 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 273 { 274 assert(cache->size % 1024 == 0); 275 assert(cache->lines_per_tag > 0); 276 assert(cache->associativity > 0); 277 assert(cache->line_size > 0); 278 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 279 (cache->lines_per_tag << 8) | (cache->line_size); 280 } 281 282 #define ASSOC_FULL 0xFF 283 284 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 285 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 286 a == 2 ? 0x2 : \ 287 a == 4 ? 0x4 : \ 288 a == 8 ? 0x6 : \ 289 a == 16 ? 0x8 : \ 290 a == 32 ? 0xA : \ 291 a == 48 ? 0xB : \ 292 a == 64 ? 0xC : \ 293 a == 96 ? 0xD : \ 294 a == 128 ? 0xE : \ 295 a == ASSOC_FULL ? 0xF : \ 296 0 /* invalid value */) 297 298 /* 299 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 300 * @l3 can be NULL. 301 */ 302 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 303 CPUCacheInfo *l3, 304 uint32_t *ecx, uint32_t *edx) 305 { 306 assert(l2->size % 1024 == 0); 307 assert(l2->associativity > 0); 308 assert(l2->lines_per_tag > 0); 309 assert(l2->line_size > 0); 310 *ecx = ((l2->size / 1024) << 16) | 311 (AMD_ENC_ASSOC(l2->associativity) << 12) | 312 (l2->lines_per_tag << 8) | (l2->line_size); 313 314 if (l3) { 315 assert(l3->size % (512 * 1024) == 0); 316 assert(l3->associativity > 0); 317 assert(l3->lines_per_tag > 0); 318 assert(l3->line_size > 0); 319 *edx = ((l3->size / (512 * 1024)) << 18) | 320 (AMD_ENC_ASSOC(l3->associativity) << 12) | 321 (l3->lines_per_tag << 8) | (l3->line_size); 322 } else { 323 *edx = 0; 324 } 325 } 326 327 /* Encode cache info for CPUID[8000001D] */ 328 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 329 X86CPUTopoInfo *topo_info, 330 uint32_t *eax, uint32_t *ebx, 331 uint32_t *ecx, uint32_t *edx) 332 { 333 uint32_t l3_threads; 334 assert(cache->size == cache->line_size * cache->associativity * 335 cache->partitions * cache->sets); 336 337 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 338 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 339 340 /* L3 is shared among multiple cores */ 341 if (cache->level == 3) { 342 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 343 *eax |= (l3_threads - 1) << 14; 344 } else { 345 *eax |= ((topo_info->threads_per_core - 1) << 14); 346 } 347 348 assert(cache->line_size > 0); 349 assert(cache->partitions > 0); 350 assert(cache->associativity > 0); 351 /* We don't implement fully-associative caches */ 352 assert(cache->associativity < cache->sets); 353 *ebx = (cache->line_size - 1) | 354 ((cache->partitions - 1) << 12) | 355 ((cache->associativity - 1) << 22); 356 357 assert(cache->sets > 0); 358 *ecx = cache->sets - 1; 359 360 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 361 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 362 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 363 } 364 365 /* Encode cache info for CPUID[8000001E] */ 366 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 367 uint32_t *eax, uint32_t *ebx, 368 uint32_t *ecx, uint32_t *edx) 369 { 370 X86CPUTopoIDs topo_ids; 371 372 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 373 374 *eax = cpu->apic_id; 375 376 /* 377 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 378 * Read-only. Reset: 0000_XXXXh. 379 * See Core::X86::Cpuid::ExtApicId. 380 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 381 * Bits Description 382 * 31:16 Reserved. 383 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 384 * The number of threads per core is ThreadsPerCore+1. 385 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 386 * 387 * NOTE: CoreId is already part of apic_id. Just use it. We can 388 * use all the 8 bits to represent the core_id here. 389 */ 390 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 391 392 /* 393 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 394 * Read-only. Reset: 0000_0XXXh. 395 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 396 * Bits Description 397 * 31:11 Reserved. 398 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 399 * ValidValues: 400 * Value Description 401 * 000b 1 node per processor. 402 * 001b 2 nodes per processor. 403 * 010b Reserved. 404 * 011b 4 nodes per processor. 405 * 111b-100b Reserved. 406 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 407 * 408 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 409 * But users can create more nodes than the actual hardware can 410 * support. To genaralize we can use all the upper 8 bits for nodes. 411 * NodeId is combination of node and socket_id which is already decoded 412 * in apic_id. Just use it by shifting. 413 */ 414 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 415 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 416 417 *edx = 0; 418 } 419 420 /* 421 * Definitions of the hardcoded cache entries we expose: 422 * These are legacy cache values. If there is a need to change any 423 * of these values please use builtin_x86_defs 424 */ 425 426 /* L1 data cache: */ 427 static CPUCacheInfo legacy_l1d_cache = { 428 .type = DATA_CACHE, 429 .level = 1, 430 .size = 32 * KiB, 431 .self_init = 1, 432 .line_size = 64, 433 .associativity = 8, 434 .sets = 64, 435 .partitions = 1, 436 .no_invd_sharing = true, 437 }; 438 439 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 440 static CPUCacheInfo legacy_l1d_cache_amd = { 441 .type = DATA_CACHE, 442 .level = 1, 443 .size = 64 * KiB, 444 .self_init = 1, 445 .line_size = 64, 446 .associativity = 2, 447 .sets = 512, 448 .partitions = 1, 449 .lines_per_tag = 1, 450 .no_invd_sharing = true, 451 }; 452 453 /* L1 instruction cache: */ 454 static CPUCacheInfo legacy_l1i_cache = { 455 .type = INSTRUCTION_CACHE, 456 .level = 1, 457 .size = 32 * KiB, 458 .self_init = 1, 459 .line_size = 64, 460 .associativity = 8, 461 .sets = 64, 462 .partitions = 1, 463 .no_invd_sharing = true, 464 }; 465 466 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 467 static CPUCacheInfo legacy_l1i_cache_amd = { 468 .type = INSTRUCTION_CACHE, 469 .level = 1, 470 .size = 64 * KiB, 471 .self_init = 1, 472 .line_size = 64, 473 .associativity = 2, 474 .sets = 512, 475 .partitions = 1, 476 .lines_per_tag = 1, 477 .no_invd_sharing = true, 478 }; 479 480 /* Level 2 unified cache: */ 481 static CPUCacheInfo legacy_l2_cache = { 482 .type = UNIFIED_CACHE, 483 .level = 2, 484 .size = 4 * MiB, 485 .self_init = 1, 486 .line_size = 64, 487 .associativity = 16, 488 .sets = 4096, 489 .partitions = 1, 490 .no_invd_sharing = true, 491 }; 492 493 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 494 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 495 .type = UNIFIED_CACHE, 496 .level = 2, 497 .size = 2 * MiB, 498 .line_size = 64, 499 .associativity = 8, 500 }; 501 502 503 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 504 static CPUCacheInfo legacy_l2_cache_amd = { 505 .type = UNIFIED_CACHE, 506 .level = 2, 507 .size = 512 * KiB, 508 .line_size = 64, 509 .lines_per_tag = 1, 510 .associativity = 16, 511 .sets = 512, 512 .partitions = 1, 513 }; 514 515 /* Level 3 unified cache: */ 516 static CPUCacheInfo legacy_l3_cache = { 517 .type = UNIFIED_CACHE, 518 .level = 3, 519 .size = 16 * MiB, 520 .line_size = 64, 521 .associativity = 16, 522 .sets = 16384, 523 .partitions = 1, 524 .lines_per_tag = 1, 525 .self_init = true, 526 .inclusive = true, 527 .complex_indexing = true, 528 }; 529 530 /* TLB definitions: */ 531 532 #define L1_DTLB_2M_ASSOC 1 533 #define L1_DTLB_2M_ENTRIES 255 534 #define L1_DTLB_4K_ASSOC 1 535 #define L1_DTLB_4K_ENTRIES 255 536 537 #define L1_ITLB_2M_ASSOC 1 538 #define L1_ITLB_2M_ENTRIES 255 539 #define L1_ITLB_4K_ASSOC 1 540 #define L1_ITLB_4K_ENTRIES 255 541 542 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 543 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 544 #define L2_DTLB_4K_ASSOC 4 545 #define L2_DTLB_4K_ENTRIES 512 546 547 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 548 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 549 #define L2_ITLB_4K_ASSOC 4 550 #define L2_ITLB_4K_ENTRIES 512 551 552 /* CPUID Leaf 0x14 constants: */ 553 #define INTEL_PT_MAX_SUBLEAF 0x1 554 /* 555 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 556 * MSR can be accessed; 557 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 558 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 559 * of Intel PT MSRs across warm reset; 560 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 561 */ 562 #define INTEL_PT_MINIMAL_EBX 0xf 563 /* 564 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 565 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 566 * accessed; 567 * bit[01]: ToPA tables can hold any number of output entries, up to the 568 * maximum allowed by the MaskOrTableOffset field of 569 * IA32_RTIT_OUTPUT_MASK_PTRS; 570 * bit[02]: Support Single-Range Output scheme; 571 */ 572 #define INTEL_PT_MINIMAL_ECX 0x7 573 /* generated packets which contain IP payloads have LIP values */ 574 #define INTEL_PT_IP_LIP (1 << 31) 575 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 576 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 577 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 578 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 579 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 580 581 /* CPUID Leaf 0x1D constants: */ 582 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 583 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 584 #define INTEL_AMX_BYTES_PER_TILE 0x400 585 #define INTEL_AMX_BYTES_PER_ROW 0x40 586 #define INTEL_AMX_TILE_MAX_NAMES 0x8 587 #define INTEL_AMX_TILE_MAX_ROWS 0x10 588 589 /* CPUID Leaf 0x1E constants: */ 590 #define INTEL_AMX_TMUL_MAX_K 0x10 591 #define INTEL_AMX_TMUL_MAX_N 0x40 592 593 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 594 uint32_t vendor2, uint32_t vendor3) 595 { 596 int i; 597 for (i = 0; i < 4; i++) { 598 dst[i] = vendor1 >> (8 * i); 599 dst[i + 4] = vendor2 >> (8 * i); 600 dst[i + 8] = vendor3 >> (8 * i); 601 } 602 dst[CPUID_VENDOR_SZ] = '\0'; 603 } 604 605 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 606 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 607 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 608 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 609 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 610 CPUID_PSE36 | CPUID_FXSR) 611 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 612 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 613 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 614 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 615 CPUID_PAE | CPUID_SEP | CPUID_APIC) 616 617 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 618 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 619 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 620 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 621 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 622 /* partly implemented: 623 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 624 /* missing: 625 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 626 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 627 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 628 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 629 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 630 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 631 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 632 CPUID_EXT_FMA) 633 /* missing: 634 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 635 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 636 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 637 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */ 638 639 #ifdef TARGET_X86_64 640 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 641 #else 642 #define TCG_EXT2_X86_64_FEATURES 0 643 #endif 644 645 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 646 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 647 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 648 TCG_EXT2_X86_64_FEATURES) 649 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 650 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 651 #define TCG_EXT4_FEATURES 0 652 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 653 CPUID_SVM_SVME_ADDR_CHK) 654 #define TCG_KVM_FEATURES 0 655 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 656 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 657 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 658 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 659 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2) 660 /* missing: 661 CPUID_7_0_EBX_HLE 662 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 663 CPUID_7_0_EBX_RDSEED */ 664 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 665 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 666 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES) 667 #define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM 668 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 669 CPUID_7_1_EAX_FSRC) 670 #define TCG_7_1_EDX_FEATURES 0 671 #define TCG_APM_FEATURES 0 672 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 673 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 674 /* missing: 675 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 676 #define TCG_14_0_ECX_FEATURES 0 677 #define TCG_SGX_12_0_EAX_FEATURES 0 678 #define TCG_SGX_12_0_EBX_FEATURES 0 679 #define TCG_SGX_12_1_EAX_FEATURES 0 680 681 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 682 [FEAT_1_EDX] = { 683 .type = CPUID_FEATURE_WORD, 684 .feat_names = { 685 "fpu", "vme", "de", "pse", 686 "tsc", "msr", "pae", "mce", 687 "cx8", "apic", NULL, "sep", 688 "mtrr", "pge", "mca", "cmov", 689 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 690 NULL, "ds" /* Intel dts */, "acpi", "mmx", 691 "fxsr", "sse", "sse2", "ss", 692 "ht" /* Intel htt */, "tm", "ia64", "pbe", 693 }, 694 .cpuid = {.eax = 1, .reg = R_EDX, }, 695 .tcg_features = TCG_FEATURES, 696 }, 697 [FEAT_1_ECX] = { 698 .type = CPUID_FEATURE_WORD, 699 .feat_names = { 700 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 701 "ds-cpl", "vmx", "smx", "est", 702 "tm2", "ssse3", "cid", NULL, 703 "fma", "cx16", "xtpr", "pdcm", 704 NULL, "pcid", "dca", "sse4.1", 705 "sse4.2", "x2apic", "movbe", "popcnt", 706 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 707 "avx", "f16c", "rdrand", "hypervisor", 708 }, 709 .cpuid = { .eax = 1, .reg = R_ECX, }, 710 .tcg_features = TCG_EXT_FEATURES, 711 }, 712 /* Feature names that are already defined on feature_name[] but 713 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 714 * names on feat_names below. They are copied automatically 715 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 716 */ 717 [FEAT_8000_0001_EDX] = { 718 .type = CPUID_FEATURE_WORD, 719 .feat_names = { 720 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 721 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 722 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 723 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 724 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 725 "nx", NULL, "mmxext", NULL /* mmx */, 726 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 727 NULL, "lm", "3dnowext", "3dnow", 728 }, 729 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 730 .tcg_features = TCG_EXT2_FEATURES, 731 }, 732 [FEAT_8000_0001_ECX] = { 733 .type = CPUID_FEATURE_WORD, 734 .feat_names = { 735 "lahf-lm", "cmp-legacy", "svm", "extapic", 736 "cr8legacy", "abm", "sse4a", "misalignsse", 737 "3dnowprefetch", "osvw", "ibs", "xop", 738 "skinit", "wdt", NULL, "lwp", 739 "fma4", "tce", NULL, "nodeid-msr", 740 NULL, "tbm", "topoext", "perfctr-core", 741 "perfctr-nb", NULL, NULL, NULL, 742 NULL, NULL, NULL, NULL, 743 }, 744 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 745 .tcg_features = TCG_EXT3_FEATURES, 746 /* 747 * TOPOEXT is always allowed but can't be enabled blindly by 748 * "-cpu host", as it requires consistent cache topology info 749 * to be provided so it doesn't confuse guests. 750 */ 751 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 752 }, 753 [FEAT_C000_0001_EDX] = { 754 .type = CPUID_FEATURE_WORD, 755 .feat_names = { 756 NULL, NULL, "xstore", "xstore-en", 757 NULL, NULL, "xcrypt", "xcrypt-en", 758 "ace2", "ace2-en", "phe", "phe-en", 759 "pmm", "pmm-en", NULL, NULL, 760 NULL, NULL, NULL, NULL, 761 NULL, NULL, NULL, NULL, 762 NULL, NULL, NULL, NULL, 763 NULL, NULL, NULL, NULL, 764 }, 765 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 766 .tcg_features = TCG_EXT4_FEATURES, 767 }, 768 [FEAT_KVM] = { 769 .type = CPUID_FEATURE_WORD, 770 .feat_names = { 771 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 772 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 773 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 774 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 775 NULL, NULL, NULL, NULL, 776 NULL, NULL, NULL, NULL, 777 "kvmclock-stable-bit", NULL, NULL, NULL, 778 NULL, NULL, NULL, NULL, 779 }, 780 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 781 .tcg_features = TCG_KVM_FEATURES, 782 }, 783 [FEAT_KVM_HINTS] = { 784 .type = CPUID_FEATURE_WORD, 785 .feat_names = { 786 "kvm-hint-dedicated", NULL, NULL, NULL, 787 NULL, NULL, NULL, NULL, 788 NULL, NULL, NULL, NULL, 789 NULL, NULL, NULL, NULL, 790 NULL, NULL, NULL, NULL, 791 NULL, NULL, NULL, NULL, 792 NULL, NULL, NULL, NULL, 793 NULL, NULL, NULL, NULL, 794 }, 795 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 796 .tcg_features = TCG_KVM_FEATURES, 797 /* 798 * KVM hints aren't auto-enabled by -cpu host, they need to be 799 * explicitly enabled in the command-line. 800 */ 801 .no_autoenable_flags = ~0U, 802 }, 803 [FEAT_SVM] = { 804 .type = CPUID_FEATURE_WORD, 805 .feat_names = { 806 "npt", "lbrv", "svm-lock", "nrip-save", 807 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 808 NULL, NULL, "pause-filter", NULL, 809 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 810 "vgif", NULL, NULL, NULL, 811 NULL, NULL, NULL, NULL, 812 NULL, "vnmi", NULL, NULL, 813 "svme-addr-chk", NULL, NULL, NULL, 814 }, 815 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 816 .tcg_features = TCG_SVM_FEATURES, 817 }, 818 [FEAT_7_0_EBX] = { 819 .type = CPUID_FEATURE_WORD, 820 .feat_names = { 821 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 822 "hle", "avx2", NULL, "smep", 823 "bmi2", "erms", "invpcid", "rtm", 824 NULL, NULL, "mpx", NULL, 825 "avx512f", "avx512dq", "rdseed", "adx", 826 "smap", "avx512ifma", "pcommit", "clflushopt", 827 "clwb", "intel-pt", "avx512pf", "avx512er", 828 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 829 }, 830 .cpuid = { 831 .eax = 7, 832 .needs_ecx = true, .ecx = 0, 833 .reg = R_EBX, 834 }, 835 .tcg_features = TCG_7_0_EBX_FEATURES, 836 }, 837 [FEAT_7_0_ECX] = { 838 .type = CPUID_FEATURE_WORD, 839 .feat_names = { 840 NULL, "avx512vbmi", "umip", "pku", 841 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 842 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 843 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 844 "la57", NULL, NULL, NULL, 845 NULL, NULL, "rdpid", NULL, 846 "bus-lock-detect", "cldemote", NULL, "movdiri", 847 "movdir64b", NULL, "sgxlc", "pks", 848 }, 849 .cpuid = { 850 .eax = 7, 851 .needs_ecx = true, .ecx = 0, 852 .reg = R_ECX, 853 }, 854 .tcg_features = TCG_7_0_ECX_FEATURES, 855 }, 856 [FEAT_7_0_EDX] = { 857 .type = CPUID_FEATURE_WORD, 858 .feat_names = { 859 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 860 "fsrm", NULL, NULL, NULL, 861 "avx512-vp2intersect", NULL, "md-clear", NULL, 862 NULL, NULL, "serialize", NULL, 863 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 864 NULL, NULL, "amx-bf16", "avx512-fp16", 865 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 866 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 867 }, 868 .cpuid = { 869 .eax = 7, 870 .needs_ecx = true, .ecx = 0, 871 .reg = R_EDX, 872 }, 873 .tcg_features = TCG_7_0_EDX_FEATURES, 874 }, 875 [FEAT_7_1_EAX] = { 876 .type = CPUID_FEATURE_WORD, 877 .feat_names = { 878 NULL, NULL, NULL, NULL, 879 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 880 NULL, NULL, "fzrm", "fsrs", 881 "fsrc", NULL, NULL, NULL, 882 NULL, NULL, NULL, NULL, 883 NULL, "amx-fp16", NULL, "avx-ifma", 884 NULL, NULL, NULL, NULL, 885 NULL, NULL, NULL, NULL, 886 }, 887 .cpuid = { 888 .eax = 7, 889 .needs_ecx = true, .ecx = 1, 890 .reg = R_EAX, 891 }, 892 .tcg_features = TCG_7_1_EAX_FEATURES, 893 }, 894 [FEAT_7_1_EDX] = { 895 .type = CPUID_FEATURE_WORD, 896 .feat_names = { 897 NULL, NULL, NULL, NULL, 898 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 899 NULL, NULL, NULL, NULL, 900 NULL, NULL, "prefetchiti", NULL, 901 NULL, NULL, NULL, NULL, 902 NULL, NULL, NULL, NULL, 903 NULL, NULL, NULL, NULL, 904 NULL, NULL, NULL, NULL, 905 }, 906 .cpuid = { 907 .eax = 7, 908 .needs_ecx = true, .ecx = 1, 909 .reg = R_EDX, 910 }, 911 .tcg_features = TCG_7_1_EDX_FEATURES, 912 }, 913 [FEAT_8000_0007_EDX] = { 914 .type = CPUID_FEATURE_WORD, 915 .feat_names = { 916 NULL, NULL, NULL, NULL, 917 NULL, NULL, NULL, NULL, 918 "invtsc", NULL, NULL, NULL, 919 NULL, NULL, NULL, NULL, 920 NULL, NULL, NULL, NULL, 921 NULL, NULL, NULL, NULL, 922 NULL, NULL, NULL, NULL, 923 NULL, NULL, NULL, NULL, 924 }, 925 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 926 .tcg_features = TCG_APM_FEATURES, 927 .unmigratable_flags = CPUID_APM_INVTSC, 928 }, 929 [FEAT_8000_0008_EBX] = { 930 .type = CPUID_FEATURE_WORD, 931 .feat_names = { 932 "clzero", NULL, "xsaveerptr", NULL, 933 NULL, NULL, NULL, NULL, 934 NULL, "wbnoinvd", NULL, NULL, 935 "ibpb", NULL, "ibrs", "amd-stibp", 936 NULL, "stibp-always-on", NULL, NULL, 937 NULL, NULL, NULL, NULL, 938 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 939 "amd-psfd", NULL, NULL, NULL, 940 }, 941 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 942 .tcg_features = 0, 943 .unmigratable_flags = 0, 944 }, 945 [FEAT_8000_0021_EAX] = { 946 .type = CPUID_FEATURE_WORD, 947 .feat_names = { 948 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 949 NULL, NULL, "null-sel-clr-base", NULL, 950 "auto-ibrs", NULL, NULL, NULL, 951 NULL, NULL, NULL, NULL, 952 NULL, NULL, NULL, NULL, 953 NULL, NULL, NULL, NULL, 954 NULL, NULL, NULL, NULL, 955 NULL, NULL, NULL, NULL, 956 }, 957 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 958 .tcg_features = 0, 959 .unmigratable_flags = 0, 960 }, 961 [FEAT_XSAVE] = { 962 .type = CPUID_FEATURE_WORD, 963 .feat_names = { 964 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 965 "xfd", NULL, NULL, NULL, 966 NULL, NULL, NULL, NULL, 967 NULL, NULL, NULL, NULL, 968 NULL, NULL, NULL, NULL, 969 NULL, NULL, NULL, NULL, 970 NULL, NULL, NULL, NULL, 971 NULL, NULL, NULL, NULL, 972 }, 973 .cpuid = { 974 .eax = 0xd, 975 .needs_ecx = true, .ecx = 1, 976 .reg = R_EAX, 977 }, 978 .tcg_features = TCG_XSAVE_FEATURES, 979 }, 980 [FEAT_XSAVE_XSS_LO] = { 981 .type = CPUID_FEATURE_WORD, 982 .feat_names = { 983 NULL, NULL, NULL, NULL, 984 NULL, NULL, NULL, NULL, 985 NULL, NULL, NULL, NULL, 986 NULL, NULL, NULL, NULL, 987 NULL, NULL, NULL, NULL, 988 NULL, NULL, NULL, NULL, 989 NULL, NULL, NULL, NULL, 990 NULL, NULL, NULL, NULL, 991 }, 992 .cpuid = { 993 .eax = 0xD, 994 .needs_ecx = true, 995 .ecx = 1, 996 .reg = R_ECX, 997 }, 998 }, 999 [FEAT_XSAVE_XSS_HI] = { 1000 .type = CPUID_FEATURE_WORD, 1001 .cpuid = { 1002 .eax = 0xD, 1003 .needs_ecx = true, 1004 .ecx = 1, 1005 .reg = R_EDX 1006 }, 1007 }, 1008 [FEAT_6_EAX] = { 1009 .type = CPUID_FEATURE_WORD, 1010 .feat_names = { 1011 NULL, NULL, "arat", NULL, 1012 NULL, NULL, NULL, NULL, 1013 NULL, NULL, NULL, NULL, 1014 NULL, NULL, NULL, NULL, 1015 NULL, NULL, NULL, NULL, 1016 NULL, NULL, NULL, NULL, 1017 NULL, NULL, NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 }, 1020 .cpuid = { .eax = 6, .reg = R_EAX, }, 1021 .tcg_features = TCG_6_EAX_FEATURES, 1022 }, 1023 [FEAT_XSAVE_XCR0_LO] = { 1024 .type = CPUID_FEATURE_WORD, 1025 .cpuid = { 1026 .eax = 0xD, 1027 .needs_ecx = true, .ecx = 0, 1028 .reg = R_EAX, 1029 }, 1030 .tcg_features = ~0U, 1031 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1032 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1033 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1034 XSTATE_PKRU_MASK, 1035 }, 1036 [FEAT_XSAVE_XCR0_HI] = { 1037 .type = CPUID_FEATURE_WORD, 1038 .cpuid = { 1039 .eax = 0xD, 1040 .needs_ecx = true, .ecx = 0, 1041 .reg = R_EDX, 1042 }, 1043 .tcg_features = ~0U, 1044 }, 1045 /*Below are MSR exposed features*/ 1046 [FEAT_ARCH_CAPABILITIES] = { 1047 .type = MSR_FEATURE_WORD, 1048 .feat_names = { 1049 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1050 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1051 "taa-no", NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 NULL, "fb-clear", NULL, NULL, 1054 NULL, NULL, NULL, NULL, 1055 NULL, NULL, NULL, NULL, 1056 NULL, NULL, NULL, NULL, 1057 }, 1058 .msr = { 1059 .index = MSR_IA32_ARCH_CAPABILITIES, 1060 }, 1061 }, 1062 [FEAT_CORE_CAPABILITY] = { 1063 .type = MSR_FEATURE_WORD, 1064 .feat_names = { 1065 NULL, NULL, NULL, NULL, 1066 NULL, "split-lock-detect", NULL, NULL, 1067 NULL, NULL, NULL, NULL, 1068 NULL, NULL, NULL, NULL, 1069 NULL, NULL, NULL, NULL, 1070 NULL, NULL, NULL, NULL, 1071 NULL, NULL, NULL, NULL, 1072 NULL, NULL, NULL, NULL, 1073 }, 1074 .msr = { 1075 .index = MSR_IA32_CORE_CAPABILITY, 1076 }, 1077 }, 1078 [FEAT_PERF_CAPABILITIES] = { 1079 .type = MSR_FEATURE_WORD, 1080 .feat_names = { 1081 NULL, NULL, NULL, NULL, 1082 NULL, NULL, NULL, NULL, 1083 NULL, NULL, NULL, NULL, 1084 NULL, "full-width-write", NULL, NULL, 1085 NULL, NULL, NULL, NULL, 1086 NULL, NULL, NULL, NULL, 1087 NULL, NULL, NULL, NULL, 1088 NULL, NULL, NULL, NULL, 1089 }, 1090 .msr = { 1091 .index = MSR_IA32_PERF_CAPABILITIES, 1092 }, 1093 }, 1094 1095 [FEAT_VMX_PROCBASED_CTLS] = { 1096 .type = MSR_FEATURE_WORD, 1097 .feat_names = { 1098 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1099 NULL, NULL, NULL, "vmx-hlt-exit", 1100 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1101 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1102 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1103 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1104 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1105 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1106 }, 1107 .msr = { 1108 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1109 } 1110 }, 1111 1112 [FEAT_VMX_SECONDARY_CTLS] = { 1113 .type = MSR_FEATURE_WORD, 1114 .feat_names = { 1115 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1116 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1117 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1118 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1119 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1120 "vmx-xsaves", NULL, NULL, NULL, 1121 NULL, "vmx-tsc-scaling", NULL, NULL, 1122 NULL, NULL, NULL, NULL, 1123 }, 1124 .msr = { 1125 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1126 } 1127 }, 1128 1129 [FEAT_VMX_PINBASED_CTLS] = { 1130 .type = MSR_FEATURE_WORD, 1131 .feat_names = { 1132 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1133 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1134 NULL, NULL, NULL, NULL, 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .msr = { 1142 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1143 } 1144 }, 1145 1146 [FEAT_VMX_EXIT_CTLS] = { 1147 .type = MSR_FEATURE_WORD, 1148 /* 1149 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1150 * the LM CPUID bit. 1151 */ 1152 .feat_names = { 1153 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1156 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1157 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1158 "vmx-exit-save-efer", "vmx-exit-load-efer", 1159 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1160 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1161 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1162 }, 1163 .msr = { 1164 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1165 } 1166 }, 1167 1168 [FEAT_VMX_ENTRY_CTLS] = { 1169 .type = MSR_FEATURE_WORD, 1170 .feat_names = { 1171 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1174 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1175 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1176 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 }, 1180 .msr = { 1181 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1182 } 1183 }, 1184 1185 [FEAT_VMX_MISC] = { 1186 .type = MSR_FEATURE_WORD, 1187 .feat_names = { 1188 NULL, NULL, NULL, NULL, 1189 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1190 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1196 }, 1197 .msr = { 1198 .index = MSR_IA32_VMX_MISC, 1199 } 1200 }, 1201 1202 [FEAT_VMX_EPT_VPID_CAPS] = { 1203 .type = MSR_FEATURE_WORD, 1204 .feat_names = { 1205 "vmx-ept-execonly", NULL, NULL, NULL, 1206 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1207 NULL, NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1210 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1211 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1212 NULL, NULL, NULL, NULL, 1213 "vmx-invvpid", NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1216 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1217 NULL, NULL, NULL, NULL, 1218 NULL, NULL, NULL, NULL, 1219 NULL, NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 }, 1223 .msr = { 1224 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1225 } 1226 }, 1227 1228 [FEAT_VMX_BASIC] = { 1229 .type = MSR_FEATURE_WORD, 1230 .feat_names = { 1231 [54] = "vmx-ins-outs", 1232 [55] = "vmx-true-ctls", 1233 }, 1234 .msr = { 1235 .index = MSR_IA32_VMX_BASIC, 1236 }, 1237 /* Just to be safe - we don't support setting the MSEG version field. */ 1238 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1239 }, 1240 1241 [FEAT_VMX_VMFUNC] = { 1242 .type = MSR_FEATURE_WORD, 1243 .feat_names = { 1244 [0] = "vmx-eptp-switching", 1245 }, 1246 .msr = { 1247 .index = MSR_IA32_VMX_VMFUNC, 1248 } 1249 }, 1250 1251 [FEAT_14_0_ECX] = { 1252 .type = CPUID_FEATURE_WORD, 1253 .feat_names = { 1254 NULL, NULL, NULL, NULL, 1255 NULL, NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 NULL, NULL, NULL, "intel-pt-lip", 1262 }, 1263 .cpuid = { 1264 .eax = 0x14, 1265 .needs_ecx = true, .ecx = 0, 1266 .reg = R_ECX, 1267 }, 1268 .tcg_features = TCG_14_0_ECX_FEATURES, 1269 }, 1270 1271 [FEAT_SGX_12_0_EAX] = { 1272 .type = CPUID_FEATURE_WORD, 1273 .feat_names = { 1274 "sgx1", "sgx2", NULL, NULL, 1275 NULL, NULL, NULL, NULL, 1276 NULL, NULL, NULL, "sgx-edeccssa", 1277 NULL, NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 }, 1283 .cpuid = { 1284 .eax = 0x12, 1285 .needs_ecx = true, .ecx = 0, 1286 .reg = R_EAX, 1287 }, 1288 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1289 }, 1290 1291 [FEAT_SGX_12_0_EBX] = { 1292 .type = CPUID_FEATURE_WORD, 1293 .feat_names = { 1294 "sgx-exinfo" , NULL, NULL, NULL, 1295 NULL, NULL, NULL, NULL, 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 }, 1303 .cpuid = { 1304 .eax = 0x12, 1305 .needs_ecx = true, .ecx = 0, 1306 .reg = R_EBX, 1307 }, 1308 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1309 }, 1310 1311 [FEAT_SGX_12_1_EAX] = { 1312 .type = CPUID_FEATURE_WORD, 1313 .feat_names = { 1314 NULL, "sgx-debug", "sgx-mode64", NULL, 1315 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1316 NULL, NULL, "sgx-aex-notify", NULL, 1317 NULL, NULL, NULL, NULL, 1318 NULL, NULL, NULL, NULL, 1319 NULL, NULL, NULL, NULL, 1320 NULL, NULL, NULL, NULL, 1321 NULL, NULL, NULL, NULL, 1322 }, 1323 .cpuid = { 1324 .eax = 0x12, 1325 .needs_ecx = true, .ecx = 1, 1326 .reg = R_EAX, 1327 }, 1328 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1329 }, 1330 }; 1331 1332 typedef struct FeatureMask { 1333 FeatureWord index; 1334 uint64_t mask; 1335 } FeatureMask; 1336 1337 typedef struct FeatureDep { 1338 FeatureMask from, to; 1339 } FeatureDep; 1340 1341 static FeatureDep feature_dependencies[] = { 1342 { 1343 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1344 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1345 }, 1346 { 1347 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1348 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1349 }, 1350 { 1351 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1352 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1353 }, 1354 { 1355 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1356 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1357 }, 1358 { 1359 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1360 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1361 }, 1362 { 1363 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1364 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1365 }, 1366 { 1367 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1368 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1369 }, 1370 { 1371 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1372 .to = { FEAT_VMX_MISC, ~0ull }, 1373 }, 1374 { 1375 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1376 .to = { FEAT_VMX_BASIC, ~0ull }, 1377 }, 1378 { 1379 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1380 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1381 }, 1382 { 1383 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1384 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1385 }, 1386 { 1387 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1388 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1389 }, 1390 { 1391 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1392 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1393 }, 1394 { 1395 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1396 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1397 }, 1398 { 1399 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1400 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1401 }, 1402 { 1403 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1404 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1405 }, 1406 { 1407 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1408 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1409 }, 1410 { 1411 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1412 .to = { FEAT_14_0_ECX, ~0ull }, 1413 }, 1414 { 1415 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1416 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1417 }, 1418 { 1419 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1420 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1421 }, 1422 { 1423 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1424 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1425 }, 1426 { 1427 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1428 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1429 }, 1430 { 1431 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1432 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1433 }, 1434 { 1435 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1436 .to = { FEAT_SVM, ~0ull }, 1437 }, 1438 }; 1439 1440 typedef struct X86RegisterInfo32 { 1441 /* Name of register */ 1442 const char *name; 1443 /* QAPI enum value register */ 1444 X86CPURegister32 qapi_enum; 1445 } X86RegisterInfo32; 1446 1447 #define REGISTER(reg) \ 1448 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1449 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1450 REGISTER(EAX), 1451 REGISTER(ECX), 1452 REGISTER(EDX), 1453 REGISTER(EBX), 1454 REGISTER(ESP), 1455 REGISTER(EBP), 1456 REGISTER(ESI), 1457 REGISTER(EDI), 1458 }; 1459 #undef REGISTER 1460 1461 /* CPUID feature bits available in XSS */ 1462 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1463 1464 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1465 [XSTATE_FP_BIT] = { 1466 /* x87 FP state component is always enabled if XSAVE is supported */ 1467 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1468 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1469 }, 1470 [XSTATE_SSE_BIT] = { 1471 /* SSE state component is always enabled if XSAVE is supported */ 1472 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1473 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1474 }, 1475 [XSTATE_YMM_BIT] = 1476 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1477 .size = sizeof(XSaveAVX) }, 1478 [XSTATE_BNDREGS_BIT] = 1479 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1480 .size = sizeof(XSaveBNDREG) }, 1481 [XSTATE_BNDCSR_BIT] = 1482 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1483 .size = sizeof(XSaveBNDCSR) }, 1484 [XSTATE_OPMASK_BIT] = 1485 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1486 .size = sizeof(XSaveOpmask) }, 1487 [XSTATE_ZMM_Hi256_BIT] = 1488 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1489 .size = sizeof(XSaveZMM_Hi256) }, 1490 [XSTATE_Hi16_ZMM_BIT] = 1491 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1492 .size = sizeof(XSaveHi16_ZMM) }, 1493 [XSTATE_PKRU_BIT] = 1494 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1495 .size = sizeof(XSavePKRU) }, 1496 [XSTATE_ARCH_LBR_BIT] = { 1497 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1498 .offset = 0 /*supervisor mode component, offset = 0 */, 1499 .size = sizeof(XSavesArchLBR) }, 1500 [XSTATE_XTILE_CFG_BIT] = { 1501 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1502 .size = sizeof(XSaveXTILECFG), 1503 }, 1504 [XSTATE_XTILE_DATA_BIT] = { 1505 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1506 .size = sizeof(XSaveXTILEDATA) 1507 }, 1508 }; 1509 1510 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1511 { 1512 uint64_t ret = x86_ext_save_areas[0].size; 1513 const ExtSaveArea *esa; 1514 uint32_t offset = 0; 1515 int i; 1516 1517 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1518 esa = &x86_ext_save_areas[i]; 1519 if ((mask >> i) & 1) { 1520 offset = compacted ? ret : esa->offset; 1521 ret = MAX(ret, offset + esa->size); 1522 } 1523 } 1524 return ret; 1525 } 1526 1527 static inline bool accel_uses_host_cpuid(void) 1528 { 1529 return kvm_enabled() || hvf_enabled(); 1530 } 1531 1532 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1533 { 1534 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1535 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1536 } 1537 1538 /* Return name of 32-bit register, from a R_* constant */ 1539 static const char *get_register_name_32(unsigned int reg) 1540 { 1541 if (reg >= CPU_NB_REGS32) { 1542 return NULL; 1543 } 1544 return x86_reg_info_32[reg].name; 1545 } 1546 1547 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1548 { 1549 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1550 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1551 } 1552 1553 /* 1554 * Returns the set of feature flags that are supported and migratable by 1555 * QEMU, for a given FeatureWord. 1556 */ 1557 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1558 { 1559 FeatureWordInfo *wi = &feature_word_info[w]; 1560 uint64_t r = 0; 1561 int i; 1562 1563 for (i = 0; i < 64; i++) { 1564 uint64_t f = 1ULL << i; 1565 1566 /* If the feature name is known, it is implicitly considered migratable, 1567 * unless it is explicitly set in unmigratable_flags */ 1568 if ((wi->migratable_flags & f) || 1569 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1570 r |= f; 1571 } 1572 } 1573 return r; 1574 } 1575 1576 void host_cpuid(uint32_t function, uint32_t count, 1577 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1578 { 1579 uint32_t vec[4]; 1580 1581 #ifdef __x86_64__ 1582 asm volatile("cpuid" 1583 : "=a"(vec[0]), "=b"(vec[1]), 1584 "=c"(vec[2]), "=d"(vec[3]) 1585 : "0"(function), "c"(count) : "cc"); 1586 #elif defined(__i386__) 1587 asm volatile("pusha \n\t" 1588 "cpuid \n\t" 1589 "mov %%eax, 0(%2) \n\t" 1590 "mov %%ebx, 4(%2) \n\t" 1591 "mov %%ecx, 8(%2) \n\t" 1592 "mov %%edx, 12(%2) \n\t" 1593 "popa" 1594 : : "a"(function), "c"(count), "S"(vec) 1595 : "memory", "cc"); 1596 #else 1597 abort(); 1598 #endif 1599 1600 if (eax) 1601 *eax = vec[0]; 1602 if (ebx) 1603 *ebx = vec[1]; 1604 if (ecx) 1605 *ecx = vec[2]; 1606 if (edx) 1607 *edx = vec[3]; 1608 } 1609 1610 /* CPU class name definitions: */ 1611 1612 /* Return type name for a given CPU model name 1613 * Caller is responsible for freeing the returned string. 1614 */ 1615 static char *x86_cpu_type_name(const char *model_name) 1616 { 1617 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1618 } 1619 1620 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1621 { 1622 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1623 return object_class_by_name(typename); 1624 } 1625 1626 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1627 { 1628 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1629 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1630 return g_strndup(class_name, 1631 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1632 } 1633 1634 typedef struct X86CPUVersionDefinition { 1635 X86CPUVersion version; 1636 const char *alias; 1637 const char *note; 1638 PropValue *props; 1639 const CPUCaches *const cache_info; 1640 } X86CPUVersionDefinition; 1641 1642 /* Base definition for a CPU model */ 1643 typedef struct X86CPUDefinition { 1644 const char *name; 1645 uint32_t level; 1646 uint32_t xlevel; 1647 /* vendor is zero-terminated, 12 character ASCII string */ 1648 char vendor[CPUID_VENDOR_SZ + 1]; 1649 int family; 1650 int model; 1651 int stepping; 1652 FeatureWordArray features; 1653 const char *model_id; 1654 const CPUCaches *const cache_info; 1655 /* 1656 * Definitions for alternative versions of CPU model. 1657 * List is terminated by item with version == 0. 1658 * If NULL, version 1 will be registered automatically. 1659 */ 1660 const X86CPUVersionDefinition *versions; 1661 const char *deprecation_note; 1662 } X86CPUDefinition; 1663 1664 /* Reference to a specific CPU model version */ 1665 struct X86CPUModel { 1666 /* Base CPU definition */ 1667 const X86CPUDefinition *cpudef; 1668 /* CPU model version */ 1669 X86CPUVersion version; 1670 const char *note; 1671 /* 1672 * If true, this is an alias CPU model. 1673 * This matters only for "-cpu help" and query-cpu-definitions 1674 */ 1675 bool is_alias; 1676 }; 1677 1678 /* Get full model name for CPU version */ 1679 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1680 X86CPUVersion version) 1681 { 1682 assert(version > 0); 1683 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1684 } 1685 1686 static const X86CPUVersionDefinition * 1687 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1688 { 1689 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1690 static const X86CPUVersionDefinition default_version_list[] = { 1691 { 1 }, 1692 { /* end of list */ } 1693 }; 1694 1695 return def->versions ?: default_version_list; 1696 } 1697 1698 static const CPUCaches epyc_cache_info = { 1699 .l1d_cache = &(CPUCacheInfo) { 1700 .type = DATA_CACHE, 1701 .level = 1, 1702 .size = 32 * KiB, 1703 .line_size = 64, 1704 .associativity = 8, 1705 .partitions = 1, 1706 .sets = 64, 1707 .lines_per_tag = 1, 1708 .self_init = 1, 1709 .no_invd_sharing = true, 1710 }, 1711 .l1i_cache = &(CPUCacheInfo) { 1712 .type = INSTRUCTION_CACHE, 1713 .level = 1, 1714 .size = 64 * KiB, 1715 .line_size = 64, 1716 .associativity = 4, 1717 .partitions = 1, 1718 .sets = 256, 1719 .lines_per_tag = 1, 1720 .self_init = 1, 1721 .no_invd_sharing = true, 1722 }, 1723 .l2_cache = &(CPUCacheInfo) { 1724 .type = UNIFIED_CACHE, 1725 .level = 2, 1726 .size = 512 * KiB, 1727 .line_size = 64, 1728 .associativity = 8, 1729 .partitions = 1, 1730 .sets = 1024, 1731 .lines_per_tag = 1, 1732 }, 1733 .l3_cache = &(CPUCacheInfo) { 1734 .type = UNIFIED_CACHE, 1735 .level = 3, 1736 .size = 8 * MiB, 1737 .line_size = 64, 1738 .associativity = 16, 1739 .partitions = 1, 1740 .sets = 8192, 1741 .lines_per_tag = 1, 1742 .self_init = true, 1743 .inclusive = true, 1744 .complex_indexing = true, 1745 }, 1746 }; 1747 1748 static CPUCaches epyc_v4_cache_info = { 1749 .l1d_cache = &(CPUCacheInfo) { 1750 .type = DATA_CACHE, 1751 .level = 1, 1752 .size = 32 * KiB, 1753 .line_size = 64, 1754 .associativity = 8, 1755 .partitions = 1, 1756 .sets = 64, 1757 .lines_per_tag = 1, 1758 .self_init = 1, 1759 .no_invd_sharing = true, 1760 }, 1761 .l1i_cache = &(CPUCacheInfo) { 1762 .type = INSTRUCTION_CACHE, 1763 .level = 1, 1764 .size = 64 * KiB, 1765 .line_size = 64, 1766 .associativity = 4, 1767 .partitions = 1, 1768 .sets = 256, 1769 .lines_per_tag = 1, 1770 .self_init = 1, 1771 .no_invd_sharing = true, 1772 }, 1773 .l2_cache = &(CPUCacheInfo) { 1774 .type = UNIFIED_CACHE, 1775 .level = 2, 1776 .size = 512 * KiB, 1777 .line_size = 64, 1778 .associativity = 8, 1779 .partitions = 1, 1780 .sets = 1024, 1781 .lines_per_tag = 1, 1782 }, 1783 .l3_cache = &(CPUCacheInfo) { 1784 .type = UNIFIED_CACHE, 1785 .level = 3, 1786 .size = 8 * MiB, 1787 .line_size = 64, 1788 .associativity = 16, 1789 .partitions = 1, 1790 .sets = 8192, 1791 .lines_per_tag = 1, 1792 .self_init = true, 1793 .inclusive = true, 1794 .complex_indexing = false, 1795 }, 1796 }; 1797 1798 static const CPUCaches epyc_rome_cache_info = { 1799 .l1d_cache = &(CPUCacheInfo) { 1800 .type = DATA_CACHE, 1801 .level = 1, 1802 .size = 32 * KiB, 1803 .line_size = 64, 1804 .associativity = 8, 1805 .partitions = 1, 1806 .sets = 64, 1807 .lines_per_tag = 1, 1808 .self_init = 1, 1809 .no_invd_sharing = true, 1810 }, 1811 .l1i_cache = &(CPUCacheInfo) { 1812 .type = INSTRUCTION_CACHE, 1813 .level = 1, 1814 .size = 32 * KiB, 1815 .line_size = 64, 1816 .associativity = 8, 1817 .partitions = 1, 1818 .sets = 64, 1819 .lines_per_tag = 1, 1820 .self_init = 1, 1821 .no_invd_sharing = true, 1822 }, 1823 .l2_cache = &(CPUCacheInfo) { 1824 .type = UNIFIED_CACHE, 1825 .level = 2, 1826 .size = 512 * KiB, 1827 .line_size = 64, 1828 .associativity = 8, 1829 .partitions = 1, 1830 .sets = 1024, 1831 .lines_per_tag = 1, 1832 }, 1833 .l3_cache = &(CPUCacheInfo) { 1834 .type = UNIFIED_CACHE, 1835 .level = 3, 1836 .size = 16 * MiB, 1837 .line_size = 64, 1838 .associativity = 16, 1839 .partitions = 1, 1840 .sets = 16384, 1841 .lines_per_tag = 1, 1842 .self_init = true, 1843 .inclusive = true, 1844 .complex_indexing = true, 1845 }, 1846 }; 1847 1848 static const CPUCaches epyc_rome_v3_cache_info = { 1849 .l1d_cache = &(CPUCacheInfo) { 1850 .type = DATA_CACHE, 1851 .level = 1, 1852 .size = 32 * KiB, 1853 .line_size = 64, 1854 .associativity = 8, 1855 .partitions = 1, 1856 .sets = 64, 1857 .lines_per_tag = 1, 1858 .self_init = 1, 1859 .no_invd_sharing = true, 1860 }, 1861 .l1i_cache = &(CPUCacheInfo) { 1862 .type = INSTRUCTION_CACHE, 1863 .level = 1, 1864 .size = 32 * KiB, 1865 .line_size = 64, 1866 .associativity = 8, 1867 .partitions = 1, 1868 .sets = 64, 1869 .lines_per_tag = 1, 1870 .self_init = 1, 1871 .no_invd_sharing = true, 1872 }, 1873 .l2_cache = &(CPUCacheInfo) { 1874 .type = UNIFIED_CACHE, 1875 .level = 2, 1876 .size = 512 * KiB, 1877 .line_size = 64, 1878 .associativity = 8, 1879 .partitions = 1, 1880 .sets = 1024, 1881 .lines_per_tag = 1, 1882 }, 1883 .l3_cache = &(CPUCacheInfo) { 1884 .type = UNIFIED_CACHE, 1885 .level = 3, 1886 .size = 16 * MiB, 1887 .line_size = 64, 1888 .associativity = 16, 1889 .partitions = 1, 1890 .sets = 16384, 1891 .lines_per_tag = 1, 1892 .self_init = true, 1893 .inclusive = true, 1894 .complex_indexing = false, 1895 }, 1896 }; 1897 1898 static const CPUCaches epyc_milan_cache_info = { 1899 .l1d_cache = &(CPUCacheInfo) { 1900 .type = DATA_CACHE, 1901 .level = 1, 1902 .size = 32 * KiB, 1903 .line_size = 64, 1904 .associativity = 8, 1905 .partitions = 1, 1906 .sets = 64, 1907 .lines_per_tag = 1, 1908 .self_init = 1, 1909 .no_invd_sharing = true, 1910 }, 1911 .l1i_cache = &(CPUCacheInfo) { 1912 .type = INSTRUCTION_CACHE, 1913 .level = 1, 1914 .size = 32 * KiB, 1915 .line_size = 64, 1916 .associativity = 8, 1917 .partitions = 1, 1918 .sets = 64, 1919 .lines_per_tag = 1, 1920 .self_init = 1, 1921 .no_invd_sharing = true, 1922 }, 1923 .l2_cache = &(CPUCacheInfo) { 1924 .type = UNIFIED_CACHE, 1925 .level = 2, 1926 .size = 512 * KiB, 1927 .line_size = 64, 1928 .associativity = 8, 1929 .partitions = 1, 1930 .sets = 1024, 1931 .lines_per_tag = 1, 1932 }, 1933 .l3_cache = &(CPUCacheInfo) { 1934 .type = UNIFIED_CACHE, 1935 .level = 3, 1936 .size = 32 * MiB, 1937 .line_size = 64, 1938 .associativity = 16, 1939 .partitions = 1, 1940 .sets = 32768, 1941 .lines_per_tag = 1, 1942 .self_init = true, 1943 .inclusive = true, 1944 .complex_indexing = true, 1945 }, 1946 }; 1947 1948 static const CPUCaches epyc_milan_v2_cache_info = { 1949 .l1d_cache = &(CPUCacheInfo) { 1950 .type = DATA_CACHE, 1951 .level = 1, 1952 .size = 32 * KiB, 1953 .line_size = 64, 1954 .associativity = 8, 1955 .partitions = 1, 1956 .sets = 64, 1957 .lines_per_tag = 1, 1958 .self_init = 1, 1959 .no_invd_sharing = true, 1960 }, 1961 .l1i_cache = &(CPUCacheInfo) { 1962 .type = INSTRUCTION_CACHE, 1963 .level = 1, 1964 .size = 32 * KiB, 1965 .line_size = 64, 1966 .associativity = 8, 1967 .partitions = 1, 1968 .sets = 64, 1969 .lines_per_tag = 1, 1970 .self_init = 1, 1971 .no_invd_sharing = true, 1972 }, 1973 .l2_cache = &(CPUCacheInfo) { 1974 .type = UNIFIED_CACHE, 1975 .level = 2, 1976 .size = 512 * KiB, 1977 .line_size = 64, 1978 .associativity = 8, 1979 .partitions = 1, 1980 .sets = 1024, 1981 .lines_per_tag = 1, 1982 }, 1983 .l3_cache = &(CPUCacheInfo) { 1984 .type = UNIFIED_CACHE, 1985 .level = 3, 1986 .size = 32 * MiB, 1987 .line_size = 64, 1988 .associativity = 16, 1989 .partitions = 1, 1990 .sets = 32768, 1991 .lines_per_tag = 1, 1992 .self_init = true, 1993 .inclusive = true, 1994 .complex_indexing = false, 1995 }, 1996 }; 1997 1998 static const CPUCaches epyc_genoa_cache_info = { 1999 .l1d_cache = &(CPUCacheInfo) { 2000 .type = DATA_CACHE, 2001 .level = 1, 2002 .size = 32 * KiB, 2003 .line_size = 64, 2004 .associativity = 8, 2005 .partitions = 1, 2006 .sets = 64, 2007 .lines_per_tag = 1, 2008 .self_init = 1, 2009 .no_invd_sharing = true, 2010 }, 2011 .l1i_cache = &(CPUCacheInfo) { 2012 .type = INSTRUCTION_CACHE, 2013 .level = 1, 2014 .size = 32 * KiB, 2015 .line_size = 64, 2016 .associativity = 8, 2017 .partitions = 1, 2018 .sets = 64, 2019 .lines_per_tag = 1, 2020 .self_init = 1, 2021 .no_invd_sharing = true, 2022 }, 2023 .l2_cache = &(CPUCacheInfo) { 2024 .type = UNIFIED_CACHE, 2025 .level = 2, 2026 .size = 1 * MiB, 2027 .line_size = 64, 2028 .associativity = 8, 2029 .partitions = 1, 2030 .sets = 2048, 2031 .lines_per_tag = 1, 2032 }, 2033 .l3_cache = &(CPUCacheInfo) { 2034 .type = UNIFIED_CACHE, 2035 .level = 3, 2036 .size = 32 * MiB, 2037 .line_size = 64, 2038 .associativity = 16, 2039 .partitions = 1, 2040 .sets = 32768, 2041 .lines_per_tag = 1, 2042 .self_init = true, 2043 .inclusive = true, 2044 .complex_indexing = false, 2045 }, 2046 }; 2047 2048 /* The following VMX features are not supported by KVM and are left out in the 2049 * CPU definitions: 2050 * 2051 * Dual-monitor support (all processors) 2052 * Entry to SMM 2053 * Deactivate dual-monitor treatment 2054 * Number of CR3-target values 2055 * Shutdown activity state 2056 * Wait-for-SIPI activity state 2057 * PAUSE-loop exiting (Westmere and newer) 2058 * EPT-violation #VE (Broadwell and newer) 2059 * Inject event with insn length=0 (Skylake and newer) 2060 * Conceal non-root operation from PT 2061 * Conceal VM exits from PT 2062 * Conceal VM entries from PT 2063 * Enable ENCLS exiting 2064 * Mode-based execute control (XS/XU) 2065 s TSC scaling (Skylake Server and newer) 2066 * GPA translation for PT (IceLake and newer) 2067 * User wait and pause 2068 * ENCLV exiting 2069 * Load IA32_RTIT_CTL 2070 * Clear IA32_RTIT_CTL 2071 * Advanced VM-exit information for EPT violations 2072 * Sub-page write permissions 2073 * PT in VMX operation 2074 */ 2075 2076 static const X86CPUDefinition builtin_x86_defs[] = { 2077 { 2078 .name = "qemu64", 2079 .level = 0xd, 2080 .vendor = CPUID_VENDOR_AMD, 2081 .family = 15, 2082 .model = 107, 2083 .stepping = 1, 2084 .features[FEAT_1_EDX] = 2085 PPRO_FEATURES | 2086 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2087 CPUID_PSE36, 2088 .features[FEAT_1_ECX] = 2089 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2090 .features[FEAT_8000_0001_EDX] = 2091 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2092 .features[FEAT_8000_0001_ECX] = 2093 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2094 .xlevel = 0x8000000A, 2095 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2096 }, 2097 { 2098 .name = "phenom", 2099 .level = 5, 2100 .vendor = CPUID_VENDOR_AMD, 2101 .family = 16, 2102 .model = 2, 2103 .stepping = 3, 2104 /* Missing: CPUID_HT */ 2105 .features[FEAT_1_EDX] = 2106 PPRO_FEATURES | 2107 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2108 CPUID_PSE36 | CPUID_VME, 2109 .features[FEAT_1_ECX] = 2110 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2111 CPUID_EXT_POPCNT, 2112 .features[FEAT_8000_0001_EDX] = 2113 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2114 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2115 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2116 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2117 CPUID_EXT3_CR8LEG, 2118 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2119 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2120 .features[FEAT_8000_0001_ECX] = 2121 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2122 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2123 /* Missing: CPUID_SVM_LBRV */ 2124 .features[FEAT_SVM] = 2125 CPUID_SVM_NPT, 2126 .xlevel = 0x8000001A, 2127 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2128 }, 2129 { 2130 .name = "core2duo", 2131 .level = 10, 2132 .vendor = CPUID_VENDOR_INTEL, 2133 .family = 6, 2134 .model = 15, 2135 .stepping = 11, 2136 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2137 .features[FEAT_1_EDX] = 2138 PPRO_FEATURES | 2139 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2140 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2141 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2142 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2143 .features[FEAT_1_ECX] = 2144 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2145 CPUID_EXT_CX16, 2146 .features[FEAT_8000_0001_EDX] = 2147 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2148 .features[FEAT_8000_0001_ECX] = 2149 CPUID_EXT3_LAHF_LM, 2150 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2151 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2152 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2153 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2154 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2155 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2156 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2157 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2158 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2159 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2160 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2161 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2162 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2163 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2164 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2165 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2166 .features[FEAT_VMX_SECONDARY_CTLS] = 2167 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2168 .xlevel = 0x80000008, 2169 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2170 }, 2171 { 2172 .name = "kvm64", 2173 .level = 0xd, 2174 .vendor = CPUID_VENDOR_INTEL, 2175 .family = 15, 2176 .model = 6, 2177 .stepping = 1, 2178 /* Missing: CPUID_HT */ 2179 .features[FEAT_1_EDX] = 2180 PPRO_FEATURES | CPUID_VME | 2181 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2182 CPUID_PSE36, 2183 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2184 .features[FEAT_1_ECX] = 2185 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2186 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2187 .features[FEAT_8000_0001_EDX] = 2188 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2189 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2190 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2191 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2192 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2193 .features[FEAT_8000_0001_ECX] = 2194 0, 2195 /* VMX features from Cedar Mill/Prescott */ 2196 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2197 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2198 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2199 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2200 VMX_PIN_BASED_NMI_EXITING, 2201 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2202 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2203 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2204 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2205 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2206 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2207 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2208 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2209 .xlevel = 0x80000008, 2210 .model_id = "Common KVM processor" 2211 }, 2212 { 2213 .name = "qemu32", 2214 .level = 4, 2215 .vendor = CPUID_VENDOR_INTEL, 2216 .family = 6, 2217 .model = 6, 2218 .stepping = 3, 2219 .features[FEAT_1_EDX] = 2220 PPRO_FEATURES, 2221 .features[FEAT_1_ECX] = 2222 CPUID_EXT_SSE3, 2223 .xlevel = 0x80000004, 2224 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2225 }, 2226 { 2227 .name = "kvm32", 2228 .level = 5, 2229 .vendor = CPUID_VENDOR_INTEL, 2230 .family = 15, 2231 .model = 6, 2232 .stepping = 1, 2233 .features[FEAT_1_EDX] = 2234 PPRO_FEATURES | CPUID_VME | 2235 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2236 .features[FEAT_1_ECX] = 2237 CPUID_EXT_SSE3, 2238 .features[FEAT_8000_0001_ECX] = 2239 0, 2240 /* VMX features from Yonah */ 2241 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2242 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2243 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2244 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2245 VMX_PIN_BASED_NMI_EXITING, 2246 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2247 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2248 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2249 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2250 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2251 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2252 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2253 .xlevel = 0x80000008, 2254 .model_id = "Common 32-bit KVM processor" 2255 }, 2256 { 2257 .name = "coreduo", 2258 .level = 10, 2259 .vendor = CPUID_VENDOR_INTEL, 2260 .family = 6, 2261 .model = 14, 2262 .stepping = 8, 2263 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2264 .features[FEAT_1_EDX] = 2265 PPRO_FEATURES | CPUID_VME | 2266 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2267 CPUID_SS, 2268 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2269 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2270 .features[FEAT_1_ECX] = 2271 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2272 .features[FEAT_8000_0001_EDX] = 2273 CPUID_EXT2_NX, 2274 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2275 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2276 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2277 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2278 VMX_PIN_BASED_NMI_EXITING, 2279 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2280 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2281 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2282 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2283 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2284 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2285 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2286 .xlevel = 0x80000008, 2287 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2288 }, 2289 { 2290 .name = "486", 2291 .level = 1, 2292 .vendor = CPUID_VENDOR_INTEL, 2293 .family = 4, 2294 .model = 8, 2295 .stepping = 0, 2296 .features[FEAT_1_EDX] = 2297 I486_FEATURES, 2298 .xlevel = 0, 2299 .model_id = "", 2300 }, 2301 { 2302 .name = "pentium", 2303 .level = 1, 2304 .vendor = CPUID_VENDOR_INTEL, 2305 .family = 5, 2306 .model = 4, 2307 .stepping = 3, 2308 .features[FEAT_1_EDX] = 2309 PENTIUM_FEATURES, 2310 .xlevel = 0, 2311 .model_id = "", 2312 }, 2313 { 2314 .name = "pentium2", 2315 .level = 2, 2316 .vendor = CPUID_VENDOR_INTEL, 2317 .family = 6, 2318 .model = 5, 2319 .stepping = 2, 2320 .features[FEAT_1_EDX] = 2321 PENTIUM2_FEATURES, 2322 .xlevel = 0, 2323 .model_id = "", 2324 }, 2325 { 2326 .name = "pentium3", 2327 .level = 3, 2328 .vendor = CPUID_VENDOR_INTEL, 2329 .family = 6, 2330 .model = 7, 2331 .stepping = 3, 2332 .features[FEAT_1_EDX] = 2333 PENTIUM3_FEATURES, 2334 .xlevel = 0, 2335 .model_id = "", 2336 }, 2337 { 2338 .name = "athlon", 2339 .level = 2, 2340 .vendor = CPUID_VENDOR_AMD, 2341 .family = 6, 2342 .model = 2, 2343 .stepping = 3, 2344 .features[FEAT_1_EDX] = 2345 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2346 CPUID_MCA, 2347 .features[FEAT_8000_0001_EDX] = 2348 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2349 .xlevel = 0x80000008, 2350 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2351 }, 2352 { 2353 .name = "n270", 2354 .level = 10, 2355 .vendor = CPUID_VENDOR_INTEL, 2356 .family = 6, 2357 .model = 28, 2358 .stepping = 2, 2359 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2360 .features[FEAT_1_EDX] = 2361 PPRO_FEATURES | 2362 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2363 CPUID_ACPI | CPUID_SS, 2364 /* Some CPUs got no CPUID_SEP */ 2365 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2366 * CPUID_EXT_XTPR */ 2367 .features[FEAT_1_ECX] = 2368 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2369 CPUID_EXT_MOVBE, 2370 .features[FEAT_8000_0001_EDX] = 2371 CPUID_EXT2_NX, 2372 .features[FEAT_8000_0001_ECX] = 2373 CPUID_EXT3_LAHF_LM, 2374 .xlevel = 0x80000008, 2375 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2376 }, 2377 { 2378 .name = "Conroe", 2379 .level = 10, 2380 .vendor = CPUID_VENDOR_INTEL, 2381 .family = 6, 2382 .model = 15, 2383 .stepping = 3, 2384 .features[FEAT_1_EDX] = 2385 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2386 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2387 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2388 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2389 CPUID_DE | CPUID_FP87, 2390 .features[FEAT_1_ECX] = 2391 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2392 .features[FEAT_8000_0001_EDX] = 2393 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2394 .features[FEAT_8000_0001_ECX] = 2395 CPUID_EXT3_LAHF_LM, 2396 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2397 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2398 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2399 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2400 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2401 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2402 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2403 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2404 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2405 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2406 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2407 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2408 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2409 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2410 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2411 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2412 .features[FEAT_VMX_SECONDARY_CTLS] = 2413 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2414 .xlevel = 0x80000008, 2415 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2416 }, 2417 { 2418 .name = "Penryn", 2419 .level = 10, 2420 .vendor = CPUID_VENDOR_INTEL, 2421 .family = 6, 2422 .model = 23, 2423 .stepping = 3, 2424 .features[FEAT_1_EDX] = 2425 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2426 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2427 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2428 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2429 CPUID_DE | CPUID_FP87, 2430 .features[FEAT_1_ECX] = 2431 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2432 CPUID_EXT_SSE3, 2433 .features[FEAT_8000_0001_EDX] = 2434 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2435 .features[FEAT_8000_0001_ECX] = 2436 CPUID_EXT3_LAHF_LM, 2437 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2438 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2439 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2440 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2441 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2442 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2443 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2444 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2445 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2446 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2447 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2448 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2449 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2450 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2451 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2452 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2453 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2454 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2455 .features[FEAT_VMX_SECONDARY_CTLS] = 2456 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2457 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2458 .xlevel = 0x80000008, 2459 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2460 }, 2461 { 2462 .name = "Nehalem", 2463 .level = 11, 2464 .vendor = CPUID_VENDOR_INTEL, 2465 .family = 6, 2466 .model = 26, 2467 .stepping = 3, 2468 .features[FEAT_1_EDX] = 2469 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2470 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2471 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2472 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2473 CPUID_DE | CPUID_FP87, 2474 .features[FEAT_1_ECX] = 2475 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2476 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2477 .features[FEAT_8000_0001_EDX] = 2478 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2479 .features[FEAT_8000_0001_ECX] = 2480 CPUID_EXT3_LAHF_LM, 2481 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2482 MSR_VMX_BASIC_TRUE_CTLS, 2483 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2484 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2485 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2486 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2487 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2488 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2489 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2490 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2491 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2492 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2493 .features[FEAT_VMX_EXIT_CTLS] = 2494 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2495 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2496 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2497 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2498 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2499 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2500 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2501 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2502 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2503 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2504 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2505 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2506 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2507 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2508 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2509 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2510 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2511 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2512 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2513 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2514 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2515 .features[FEAT_VMX_SECONDARY_CTLS] = 2516 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2517 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2518 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2519 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2520 VMX_SECONDARY_EXEC_ENABLE_VPID, 2521 .xlevel = 0x80000008, 2522 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2523 .versions = (X86CPUVersionDefinition[]) { 2524 { .version = 1 }, 2525 { 2526 .version = 2, 2527 .alias = "Nehalem-IBRS", 2528 .props = (PropValue[]) { 2529 { "spec-ctrl", "on" }, 2530 { "model-id", 2531 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2532 { /* end of list */ } 2533 } 2534 }, 2535 { /* end of list */ } 2536 } 2537 }, 2538 { 2539 .name = "Westmere", 2540 .level = 11, 2541 .vendor = CPUID_VENDOR_INTEL, 2542 .family = 6, 2543 .model = 44, 2544 .stepping = 1, 2545 .features[FEAT_1_EDX] = 2546 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2547 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2548 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2549 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2550 CPUID_DE | CPUID_FP87, 2551 .features[FEAT_1_ECX] = 2552 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2553 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2554 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2555 .features[FEAT_8000_0001_EDX] = 2556 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2557 .features[FEAT_8000_0001_ECX] = 2558 CPUID_EXT3_LAHF_LM, 2559 .features[FEAT_6_EAX] = 2560 CPUID_6_EAX_ARAT, 2561 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2562 MSR_VMX_BASIC_TRUE_CTLS, 2563 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2564 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2565 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2566 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2567 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2568 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2569 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2570 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2571 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2572 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2573 .features[FEAT_VMX_EXIT_CTLS] = 2574 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2575 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2576 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2577 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2578 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2579 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2580 MSR_VMX_MISC_STORE_LMA, 2581 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2582 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2583 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2584 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2585 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2586 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2587 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2588 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2589 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2590 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2591 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2592 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2593 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2594 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2595 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2596 .features[FEAT_VMX_SECONDARY_CTLS] = 2597 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2598 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2599 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2600 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2601 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2602 .xlevel = 0x80000008, 2603 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2604 .versions = (X86CPUVersionDefinition[]) { 2605 { .version = 1 }, 2606 { 2607 .version = 2, 2608 .alias = "Westmere-IBRS", 2609 .props = (PropValue[]) { 2610 { "spec-ctrl", "on" }, 2611 { "model-id", 2612 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2613 { /* end of list */ } 2614 } 2615 }, 2616 { /* end of list */ } 2617 } 2618 }, 2619 { 2620 .name = "SandyBridge", 2621 .level = 0xd, 2622 .vendor = CPUID_VENDOR_INTEL, 2623 .family = 6, 2624 .model = 42, 2625 .stepping = 1, 2626 .features[FEAT_1_EDX] = 2627 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2628 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2629 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2630 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2631 CPUID_DE | CPUID_FP87, 2632 .features[FEAT_1_ECX] = 2633 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2634 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2635 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2636 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2637 CPUID_EXT_SSE3, 2638 .features[FEAT_8000_0001_EDX] = 2639 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2640 CPUID_EXT2_SYSCALL, 2641 .features[FEAT_8000_0001_ECX] = 2642 CPUID_EXT3_LAHF_LM, 2643 .features[FEAT_XSAVE] = 2644 CPUID_XSAVE_XSAVEOPT, 2645 .features[FEAT_6_EAX] = 2646 CPUID_6_EAX_ARAT, 2647 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2648 MSR_VMX_BASIC_TRUE_CTLS, 2649 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2650 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2651 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2652 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2653 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2654 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2655 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2656 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2657 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2658 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2659 .features[FEAT_VMX_EXIT_CTLS] = 2660 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2661 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2662 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2663 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2664 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2665 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2666 MSR_VMX_MISC_STORE_LMA, 2667 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2668 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2669 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2670 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2671 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2672 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2673 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2674 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2675 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2676 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2677 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2678 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2679 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2680 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2681 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2682 .features[FEAT_VMX_SECONDARY_CTLS] = 2683 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2684 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2685 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2686 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2687 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2688 .xlevel = 0x80000008, 2689 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2690 .versions = (X86CPUVersionDefinition[]) { 2691 { .version = 1 }, 2692 { 2693 .version = 2, 2694 .alias = "SandyBridge-IBRS", 2695 .props = (PropValue[]) { 2696 { "spec-ctrl", "on" }, 2697 { "model-id", 2698 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2699 { /* end of list */ } 2700 } 2701 }, 2702 { /* end of list */ } 2703 } 2704 }, 2705 { 2706 .name = "IvyBridge", 2707 .level = 0xd, 2708 .vendor = CPUID_VENDOR_INTEL, 2709 .family = 6, 2710 .model = 58, 2711 .stepping = 9, 2712 .features[FEAT_1_EDX] = 2713 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2714 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2715 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2716 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2717 CPUID_DE | CPUID_FP87, 2718 .features[FEAT_1_ECX] = 2719 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2720 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2721 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2722 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2723 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2724 .features[FEAT_7_0_EBX] = 2725 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2726 CPUID_7_0_EBX_ERMS, 2727 .features[FEAT_8000_0001_EDX] = 2728 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2729 CPUID_EXT2_SYSCALL, 2730 .features[FEAT_8000_0001_ECX] = 2731 CPUID_EXT3_LAHF_LM, 2732 .features[FEAT_XSAVE] = 2733 CPUID_XSAVE_XSAVEOPT, 2734 .features[FEAT_6_EAX] = 2735 CPUID_6_EAX_ARAT, 2736 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2737 MSR_VMX_BASIC_TRUE_CTLS, 2738 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2739 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2740 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2741 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2742 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2743 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2744 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2745 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2746 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2747 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2748 .features[FEAT_VMX_EXIT_CTLS] = 2749 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2750 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2751 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2752 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2753 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2754 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2755 MSR_VMX_MISC_STORE_LMA, 2756 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2757 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2758 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2759 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2760 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2761 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2762 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2763 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2764 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2765 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2766 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2767 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2768 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2769 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2770 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2771 .features[FEAT_VMX_SECONDARY_CTLS] = 2772 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2773 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2774 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2775 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2776 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2777 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2778 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2779 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2780 .xlevel = 0x80000008, 2781 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2782 .versions = (X86CPUVersionDefinition[]) { 2783 { .version = 1 }, 2784 { 2785 .version = 2, 2786 .alias = "IvyBridge-IBRS", 2787 .props = (PropValue[]) { 2788 { "spec-ctrl", "on" }, 2789 { "model-id", 2790 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2791 { /* end of list */ } 2792 } 2793 }, 2794 { /* end of list */ } 2795 } 2796 }, 2797 { 2798 .name = "Haswell", 2799 .level = 0xd, 2800 .vendor = CPUID_VENDOR_INTEL, 2801 .family = 6, 2802 .model = 60, 2803 .stepping = 4, 2804 .features[FEAT_1_EDX] = 2805 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2809 CPUID_DE | CPUID_FP87, 2810 .features[FEAT_1_ECX] = 2811 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2812 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2813 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2814 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2815 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2816 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2817 .features[FEAT_8000_0001_EDX] = 2818 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2819 CPUID_EXT2_SYSCALL, 2820 .features[FEAT_8000_0001_ECX] = 2821 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2822 .features[FEAT_7_0_EBX] = 2823 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2824 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2825 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2826 CPUID_7_0_EBX_RTM, 2827 .features[FEAT_XSAVE] = 2828 CPUID_XSAVE_XSAVEOPT, 2829 .features[FEAT_6_EAX] = 2830 CPUID_6_EAX_ARAT, 2831 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2832 MSR_VMX_BASIC_TRUE_CTLS, 2833 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2834 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2835 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2836 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2837 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2838 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2839 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2840 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2841 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2842 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2843 .features[FEAT_VMX_EXIT_CTLS] = 2844 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2845 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2846 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2847 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2848 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2849 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2850 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2851 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2852 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2853 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2854 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2855 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2856 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2857 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2858 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2859 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2860 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2861 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2862 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2863 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2864 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2865 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2866 .features[FEAT_VMX_SECONDARY_CTLS] = 2867 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2868 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2869 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2870 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2871 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2872 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2873 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2874 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2875 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2876 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2877 .xlevel = 0x80000008, 2878 .model_id = "Intel Core Processor (Haswell)", 2879 .versions = (X86CPUVersionDefinition[]) { 2880 { .version = 1 }, 2881 { 2882 .version = 2, 2883 .alias = "Haswell-noTSX", 2884 .props = (PropValue[]) { 2885 { "hle", "off" }, 2886 { "rtm", "off" }, 2887 { "stepping", "1" }, 2888 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2889 { /* end of list */ } 2890 }, 2891 }, 2892 { 2893 .version = 3, 2894 .alias = "Haswell-IBRS", 2895 .props = (PropValue[]) { 2896 /* Restore TSX features removed by -v2 above */ 2897 { "hle", "on" }, 2898 { "rtm", "on" }, 2899 /* 2900 * Haswell and Haswell-IBRS had stepping=4 in 2901 * QEMU 4.0 and older 2902 */ 2903 { "stepping", "4" }, 2904 { "spec-ctrl", "on" }, 2905 { "model-id", 2906 "Intel Core Processor (Haswell, IBRS)" }, 2907 { /* end of list */ } 2908 } 2909 }, 2910 { 2911 .version = 4, 2912 .alias = "Haswell-noTSX-IBRS", 2913 .props = (PropValue[]) { 2914 { "hle", "off" }, 2915 { "rtm", "off" }, 2916 /* spec-ctrl was already enabled by -v3 above */ 2917 { "stepping", "1" }, 2918 { "model-id", 2919 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2920 { /* end of list */ } 2921 } 2922 }, 2923 { /* end of list */ } 2924 } 2925 }, 2926 { 2927 .name = "Broadwell", 2928 .level = 0xd, 2929 .vendor = CPUID_VENDOR_INTEL, 2930 .family = 6, 2931 .model = 61, 2932 .stepping = 2, 2933 .features[FEAT_1_EDX] = 2934 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2935 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2936 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2937 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2938 CPUID_DE | CPUID_FP87, 2939 .features[FEAT_1_ECX] = 2940 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2941 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2942 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2943 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2944 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2945 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2946 .features[FEAT_8000_0001_EDX] = 2947 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2948 CPUID_EXT2_SYSCALL, 2949 .features[FEAT_8000_0001_ECX] = 2950 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2951 .features[FEAT_7_0_EBX] = 2952 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2953 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2954 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2955 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2956 CPUID_7_0_EBX_SMAP, 2957 .features[FEAT_XSAVE] = 2958 CPUID_XSAVE_XSAVEOPT, 2959 .features[FEAT_6_EAX] = 2960 CPUID_6_EAX_ARAT, 2961 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2962 MSR_VMX_BASIC_TRUE_CTLS, 2963 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2964 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2965 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2966 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2967 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2968 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2969 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2970 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2971 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2972 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2973 .features[FEAT_VMX_EXIT_CTLS] = 2974 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2975 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2976 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2977 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2978 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2979 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2980 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2981 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2982 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2983 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2984 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2985 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2986 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2987 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2988 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2989 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2990 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2991 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2992 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2993 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2994 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2995 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2996 .features[FEAT_VMX_SECONDARY_CTLS] = 2997 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2998 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2999 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3000 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3001 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3002 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3003 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3004 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3005 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3006 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3007 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3008 .xlevel = 0x80000008, 3009 .model_id = "Intel Core Processor (Broadwell)", 3010 .versions = (X86CPUVersionDefinition[]) { 3011 { .version = 1 }, 3012 { 3013 .version = 2, 3014 .alias = "Broadwell-noTSX", 3015 .props = (PropValue[]) { 3016 { "hle", "off" }, 3017 { "rtm", "off" }, 3018 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3019 { /* end of list */ } 3020 }, 3021 }, 3022 { 3023 .version = 3, 3024 .alias = "Broadwell-IBRS", 3025 .props = (PropValue[]) { 3026 /* Restore TSX features removed by -v2 above */ 3027 { "hle", "on" }, 3028 { "rtm", "on" }, 3029 { "spec-ctrl", "on" }, 3030 { "model-id", 3031 "Intel Core Processor (Broadwell, IBRS)" }, 3032 { /* end of list */ } 3033 } 3034 }, 3035 { 3036 .version = 4, 3037 .alias = "Broadwell-noTSX-IBRS", 3038 .props = (PropValue[]) { 3039 { "hle", "off" }, 3040 { "rtm", "off" }, 3041 /* spec-ctrl was already enabled by -v3 above */ 3042 { "model-id", 3043 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3044 { /* end of list */ } 3045 } 3046 }, 3047 { /* end of list */ } 3048 } 3049 }, 3050 { 3051 .name = "Skylake-Client", 3052 .level = 0xd, 3053 .vendor = CPUID_VENDOR_INTEL, 3054 .family = 6, 3055 .model = 94, 3056 .stepping = 3, 3057 .features[FEAT_1_EDX] = 3058 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3059 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3060 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3061 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3062 CPUID_DE | CPUID_FP87, 3063 .features[FEAT_1_ECX] = 3064 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3065 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3066 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3067 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3068 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3069 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3070 .features[FEAT_8000_0001_EDX] = 3071 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3072 CPUID_EXT2_SYSCALL, 3073 .features[FEAT_8000_0001_ECX] = 3074 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3075 .features[FEAT_7_0_EBX] = 3076 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3077 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3078 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3079 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3080 CPUID_7_0_EBX_SMAP, 3081 /* XSAVES is added in version 4 */ 3082 .features[FEAT_XSAVE] = 3083 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3084 CPUID_XSAVE_XGETBV1, 3085 .features[FEAT_6_EAX] = 3086 CPUID_6_EAX_ARAT, 3087 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3088 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3089 MSR_VMX_BASIC_TRUE_CTLS, 3090 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3091 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3092 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3093 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3094 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3095 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3096 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3097 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3098 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3099 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3100 .features[FEAT_VMX_EXIT_CTLS] = 3101 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3102 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3103 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3104 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3105 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3106 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3107 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3108 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3109 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3110 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3111 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3112 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3113 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3114 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3115 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3116 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3117 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3118 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3119 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3120 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3121 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3122 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3123 .features[FEAT_VMX_SECONDARY_CTLS] = 3124 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3125 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3126 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3127 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3128 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3129 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3130 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3131 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3132 .xlevel = 0x80000008, 3133 .model_id = "Intel Core Processor (Skylake)", 3134 .versions = (X86CPUVersionDefinition[]) { 3135 { .version = 1 }, 3136 { 3137 .version = 2, 3138 .alias = "Skylake-Client-IBRS", 3139 .props = (PropValue[]) { 3140 { "spec-ctrl", "on" }, 3141 { "model-id", 3142 "Intel Core Processor (Skylake, IBRS)" }, 3143 { /* end of list */ } 3144 } 3145 }, 3146 { 3147 .version = 3, 3148 .alias = "Skylake-Client-noTSX-IBRS", 3149 .props = (PropValue[]) { 3150 { "hle", "off" }, 3151 { "rtm", "off" }, 3152 { "model-id", 3153 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3154 { /* end of list */ } 3155 } 3156 }, 3157 { 3158 .version = 4, 3159 .note = "IBRS, XSAVES, no TSX", 3160 .props = (PropValue[]) { 3161 { "xsaves", "on" }, 3162 { "vmx-xsaves", "on" }, 3163 { /* end of list */ } 3164 } 3165 }, 3166 { /* end of list */ } 3167 } 3168 }, 3169 { 3170 .name = "Skylake-Server", 3171 .level = 0xd, 3172 .vendor = CPUID_VENDOR_INTEL, 3173 .family = 6, 3174 .model = 85, 3175 .stepping = 4, 3176 .features[FEAT_1_EDX] = 3177 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3178 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3179 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3180 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3181 CPUID_DE | CPUID_FP87, 3182 .features[FEAT_1_ECX] = 3183 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3184 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3185 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3186 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3187 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3188 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3189 .features[FEAT_8000_0001_EDX] = 3190 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3191 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3192 .features[FEAT_8000_0001_ECX] = 3193 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3194 .features[FEAT_7_0_EBX] = 3195 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3196 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3197 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3198 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3199 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3200 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3201 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3202 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3203 .features[FEAT_7_0_ECX] = 3204 CPUID_7_0_ECX_PKU, 3205 /* XSAVES is added in version 5 */ 3206 .features[FEAT_XSAVE] = 3207 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3208 CPUID_XSAVE_XGETBV1, 3209 .features[FEAT_6_EAX] = 3210 CPUID_6_EAX_ARAT, 3211 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3212 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3213 MSR_VMX_BASIC_TRUE_CTLS, 3214 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3215 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3216 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3217 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3218 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3219 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3220 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3221 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3222 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3223 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3224 .features[FEAT_VMX_EXIT_CTLS] = 3225 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3226 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3227 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3228 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3229 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3230 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3231 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3232 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3233 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3234 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3235 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3236 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3237 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3238 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3239 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3240 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3241 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3242 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3243 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3244 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3245 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3246 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3247 .features[FEAT_VMX_SECONDARY_CTLS] = 3248 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3249 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3250 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3251 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3252 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3253 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3254 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3255 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3256 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3257 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3258 .xlevel = 0x80000008, 3259 .model_id = "Intel Xeon Processor (Skylake)", 3260 .versions = (X86CPUVersionDefinition[]) { 3261 { .version = 1 }, 3262 { 3263 .version = 2, 3264 .alias = "Skylake-Server-IBRS", 3265 .props = (PropValue[]) { 3266 /* clflushopt was not added to Skylake-Server-IBRS */ 3267 /* TODO: add -v3 including clflushopt */ 3268 { "clflushopt", "off" }, 3269 { "spec-ctrl", "on" }, 3270 { "model-id", 3271 "Intel Xeon Processor (Skylake, IBRS)" }, 3272 { /* end of list */ } 3273 } 3274 }, 3275 { 3276 .version = 3, 3277 .alias = "Skylake-Server-noTSX-IBRS", 3278 .props = (PropValue[]) { 3279 { "hle", "off" }, 3280 { "rtm", "off" }, 3281 { "model-id", 3282 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3283 { /* end of list */ } 3284 } 3285 }, 3286 { 3287 .version = 4, 3288 .props = (PropValue[]) { 3289 { "vmx-eptp-switching", "on" }, 3290 { /* end of list */ } 3291 } 3292 }, 3293 { 3294 .version = 5, 3295 .note = "IBRS, XSAVES, EPT switching, no TSX", 3296 .props = (PropValue[]) { 3297 { "xsaves", "on" }, 3298 { "vmx-xsaves", "on" }, 3299 { /* end of list */ } 3300 } 3301 }, 3302 { /* end of list */ } 3303 } 3304 }, 3305 { 3306 .name = "Cascadelake-Server", 3307 .level = 0xd, 3308 .vendor = CPUID_VENDOR_INTEL, 3309 .family = 6, 3310 .model = 85, 3311 .stepping = 6, 3312 .features[FEAT_1_EDX] = 3313 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3314 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3315 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3316 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3317 CPUID_DE | CPUID_FP87, 3318 .features[FEAT_1_ECX] = 3319 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3320 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3321 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3322 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3323 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3324 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3325 .features[FEAT_8000_0001_EDX] = 3326 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3327 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3328 .features[FEAT_8000_0001_ECX] = 3329 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3330 .features[FEAT_7_0_EBX] = 3331 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3332 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3333 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3334 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3335 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3336 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3337 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3338 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3339 .features[FEAT_7_0_ECX] = 3340 CPUID_7_0_ECX_PKU | 3341 CPUID_7_0_ECX_AVX512VNNI, 3342 .features[FEAT_7_0_EDX] = 3343 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3344 /* XSAVES is added in version 5 */ 3345 .features[FEAT_XSAVE] = 3346 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3347 CPUID_XSAVE_XGETBV1, 3348 .features[FEAT_6_EAX] = 3349 CPUID_6_EAX_ARAT, 3350 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3351 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3352 MSR_VMX_BASIC_TRUE_CTLS, 3353 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3354 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3355 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3356 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3357 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3358 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3359 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3360 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3361 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3362 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3363 .features[FEAT_VMX_EXIT_CTLS] = 3364 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3365 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3366 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3367 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3368 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3369 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3370 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3371 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3372 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3373 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3374 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3375 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3376 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3377 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3378 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3379 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3380 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3381 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3382 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3383 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3384 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3385 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3386 .features[FEAT_VMX_SECONDARY_CTLS] = 3387 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3388 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3389 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3390 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3391 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3392 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3393 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3394 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3395 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3396 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3397 .xlevel = 0x80000008, 3398 .model_id = "Intel Xeon Processor (Cascadelake)", 3399 .versions = (X86CPUVersionDefinition[]) { 3400 { .version = 1 }, 3401 { .version = 2, 3402 .note = "ARCH_CAPABILITIES", 3403 .props = (PropValue[]) { 3404 { "arch-capabilities", "on" }, 3405 { "rdctl-no", "on" }, 3406 { "ibrs-all", "on" }, 3407 { "skip-l1dfl-vmentry", "on" }, 3408 { "mds-no", "on" }, 3409 { /* end of list */ } 3410 }, 3411 }, 3412 { .version = 3, 3413 .alias = "Cascadelake-Server-noTSX", 3414 .note = "ARCH_CAPABILITIES, no TSX", 3415 .props = (PropValue[]) { 3416 { "hle", "off" }, 3417 { "rtm", "off" }, 3418 { /* end of list */ } 3419 }, 3420 }, 3421 { .version = 4, 3422 .note = "ARCH_CAPABILITIES, no TSX", 3423 .props = (PropValue[]) { 3424 { "vmx-eptp-switching", "on" }, 3425 { /* end of list */ } 3426 }, 3427 }, 3428 { .version = 5, 3429 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3430 .props = (PropValue[]) { 3431 { "xsaves", "on" }, 3432 { "vmx-xsaves", "on" }, 3433 { /* end of list */ } 3434 }, 3435 }, 3436 { /* end of list */ } 3437 } 3438 }, 3439 { 3440 .name = "Cooperlake", 3441 .level = 0xd, 3442 .vendor = CPUID_VENDOR_INTEL, 3443 .family = 6, 3444 .model = 85, 3445 .stepping = 10, 3446 .features[FEAT_1_EDX] = 3447 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3448 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3449 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3450 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3451 CPUID_DE | CPUID_FP87, 3452 .features[FEAT_1_ECX] = 3453 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3454 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3455 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3456 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3457 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3458 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3459 .features[FEAT_8000_0001_EDX] = 3460 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3461 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3462 .features[FEAT_8000_0001_ECX] = 3463 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3464 .features[FEAT_7_0_EBX] = 3465 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3466 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3467 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3468 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3469 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3470 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3471 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3472 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3473 .features[FEAT_7_0_ECX] = 3474 CPUID_7_0_ECX_PKU | 3475 CPUID_7_0_ECX_AVX512VNNI, 3476 .features[FEAT_7_0_EDX] = 3477 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3478 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3479 .features[FEAT_ARCH_CAPABILITIES] = 3480 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3481 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3482 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3483 .features[FEAT_7_1_EAX] = 3484 CPUID_7_1_EAX_AVX512_BF16, 3485 /* XSAVES is added in version 2 */ 3486 .features[FEAT_XSAVE] = 3487 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3488 CPUID_XSAVE_XGETBV1, 3489 .features[FEAT_6_EAX] = 3490 CPUID_6_EAX_ARAT, 3491 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3492 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3493 MSR_VMX_BASIC_TRUE_CTLS, 3494 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3495 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3496 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3497 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3498 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3499 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3500 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3501 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3502 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3504 .features[FEAT_VMX_EXIT_CTLS] = 3505 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3506 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3507 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3508 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3509 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3510 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3511 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3512 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3513 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3514 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3515 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3516 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3517 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3518 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3519 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3520 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3521 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3522 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3523 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3524 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3525 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3526 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3527 .features[FEAT_VMX_SECONDARY_CTLS] = 3528 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3529 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3530 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3531 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3532 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3533 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3534 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3535 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3536 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3537 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3538 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3539 .xlevel = 0x80000008, 3540 .model_id = "Intel Xeon Processor (Cooperlake)", 3541 .versions = (X86CPUVersionDefinition[]) { 3542 { .version = 1 }, 3543 { .version = 2, 3544 .note = "XSAVES", 3545 .props = (PropValue[]) { 3546 { "xsaves", "on" }, 3547 { "vmx-xsaves", "on" }, 3548 { /* end of list */ } 3549 }, 3550 }, 3551 { /* end of list */ } 3552 } 3553 }, 3554 { 3555 .name = "Icelake-Server", 3556 .level = 0xd, 3557 .vendor = CPUID_VENDOR_INTEL, 3558 .family = 6, 3559 .model = 134, 3560 .stepping = 0, 3561 .features[FEAT_1_EDX] = 3562 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3563 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3564 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3565 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3566 CPUID_DE | CPUID_FP87, 3567 .features[FEAT_1_ECX] = 3568 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3569 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3570 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3571 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3572 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3573 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3574 .features[FEAT_8000_0001_EDX] = 3575 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3576 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3577 .features[FEAT_8000_0001_ECX] = 3578 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3579 .features[FEAT_8000_0008_EBX] = 3580 CPUID_8000_0008_EBX_WBNOINVD, 3581 .features[FEAT_7_0_EBX] = 3582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3586 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3587 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3588 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3589 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3590 .features[FEAT_7_0_ECX] = 3591 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3592 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3593 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3594 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3595 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3596 .features[FEAT_7_0_EDX] = 3597 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3598 /* XSAVES is added in version 5 */ 3599 .features[FEAT_XSAVE] = 3600 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3601 CPUID_XSAVE_XGETBV1, 3602 .features[FEAT_6_EAX] = 3603 CPUID_6_EAX_ARAT, 3604 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3605 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3606 MSR_VMX_BASIC_TRUE_CTLS, 3607 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3608 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3609 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3610 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3611 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3612 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3613 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3614 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3615 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3616 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3617 .features[FEAT_VMX_EXIT_CTLS] = 3618 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3619 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3620 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3621 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3622 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3623 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3624 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3625 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3626 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3627 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3628 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3629 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3630 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3631 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3632 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3633 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3634 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3635 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3636 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3637 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3638 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3639 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3640 .features[FEAT_VMX_SECONDARY_CTLS] = 3641 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3642 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3643 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3644 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3645 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3646 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3647 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3648 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3649 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3650 .xlevel = 0x80000008, 3651 .model_id = "Intel Xeon Processor (Icelake)", 3652 .versions = (X86CPUVersionDefinition[]) { 3653 { .version = 1 }, 3654 { 3655 .version = 2, 3656 .note = "no TSX", 3657 .alias = "Icelake-Server-noTSX", 3658 .props = (PropValue[]) { 3659 { "hle", "off" }, 3660 { "rtm", "off" }, 3661 { /* end of list */ } 3662 }, 3663 }, 3664 { 3665 .version = 3, 3666 .props = (PropValue[]) { 3667 { "arch-capabilities", "on" }, 3668 { "rdctl-no", "on" }, 3669 { "ibrs-all", "on" }, 3670 { "skip-l1dfl-vmentry", "on" }, 3671 { "mds-no", "on" }, 3672 { "pschange-mc-no", "on" }, 3673 { "taa-no", "on" }, 3674 { /* end of list */ } 3675 }, 3676 }, 3677 { 3678 .version = 4, 3679 .props = (PropValue[]) { 3680 { "sha-ni", "on" }, 3681 { "avx512ifma", "on" }, 3682 { "rdpid", "on" }, 3683 { "fsrm", "on" }, 3684 { "vmx-rdseed-exit", "on" }, 3685 { "vmx-pml", "on" }, 3686 { "vmx-eptp-switching", "on" }, 3687 { "model", "106" }, 3688 { /* end of list */ } 3689 }, 3690 }, 3691 { 3692 .version = 5, 3693 .note = "XSAVES", 3694 .props = (PropValue[]) { 3695 { "xsaves", "on" }, 3696 { "vmx-xsaves", "on" }, 3697 { /* end of list */ } 3698 }, 3699 }, 3700 { 3701 .version = 6, 3702 .note = "5-level EPT", 3703 .props = (PropValue[]) { 3704 { "vmx-page-walk-5", "on" }, 3705 { /* end of list */ } 3706 }, 3707 }, 3708 { /* end of list */ } 3709 } 3710 }, 3711 { 3712 .name = "SapphireRapids", 3713 .level = 0x20, 3714 .vendor = CPUID_VENDOR_INTEL, 3715 .family = 6, 3716 .model = 143, 3717 .stepping = 4, 3718 /* 3719 * please keep the ascending order so that we can have a clear view of 3720 * bit position of each feature. 3721 */ 3722 .features[FEAT_1_EDX] = 3723 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3724 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3725 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3726 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3727 CPUID_SSE | CPUID_SSE2, 3728 .features[FEAT_1_ECX] = 3729 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3730 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3731 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3732 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3733 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3734 .features[FEAT_8000_0001_EDX] = 3735 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3736 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3737 .features[FEAT_8000_0001_ECX] = 3738 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 3739 .features[FEAT_8000_0008_EBX] = 3740 CPUID_8000_0008_EBX_WBNOINVD, 3741 .features[FEAT_7_0_EBX] = 3742 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 3743 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 3744 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 3745 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3746 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 3747 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 3748 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 3749 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 3750 .features[FEAT_7_0_ECX] = 3751 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3752 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3753 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3754 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3755 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 3756 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 3757 .features[FEAT_7_0_EDX] = 3758 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 3759 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 3760 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 3761 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 3762 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3763 .features[FEAT_ARCH_CAPABILITIES] = 3764 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3765 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3766 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3767 .features[FEAT_XSAVE] = 3768 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3769 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 3770 .features[FEAT_6_EAX] = 3771 CPUID_6_EAX_ARAT, 3772 .features[FEAT_7_1_EAX] = 3773 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 3774 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 3775 .features[FEAT_VMX_BASIC] = 3776 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 3777 .features[FEAT_VMX_ENTRY_CTLS] = 3778 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 3779 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 3780 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 3781 .features[FEAT_VMX_EPT_VPID_CAPS] = 3782 MSR_VMX_EPT_EXECONLY | 3783 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 3784 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 3785 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 3786 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3787 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3788 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 3789 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3790 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3791 .features[FEAT_VMX_EXIT_CTLS] = 3792 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3793 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3794 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 3795 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3796 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3797 .features[FEAT_VMX_MISC] = 3798 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 3799 MSR_VMX_MISC_VMWRITE_VMEXIT, 3800 .features[FEAT_VMX_PINBASED_CTLS] = 3801 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 3802 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 3803 VMX_PIN_BASED_POSTED_INTR, 3804 .features[FEAT_VMX_PROCBASED_CTLS] = 3805 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3806 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3807 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3808 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3809 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3810 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3811 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 3812 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3813 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3814 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3815 VMX_CPU_BASED_PAUSE_EXITING | 3816 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3817 .features[FEAT_VMX_SECONDARY_CTLS] = 3818 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3819 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 3820 VMX_SECONDARY_EXEC_RDTSCP | 3821 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3822 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 3823 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3824 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3825 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3826 VMX_SECONDARY_EXEC_RDRAND_EXITING | 3827 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3828 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3829 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 3830 VMX_SECONDARY_EXEC_XSAVES, 3831 .features[FEAT_VMX_VMFUNC] = 3832 MSR_VMX_VMFUNC_EPT_SWITCHING, 3833 .xlevel = 0x80000008, 3834 .model_id = "Intel Xeon Processor (SapphireRapids)", 3835 .versions = (X86CPUVersionDefinition[]) { 3836 { .version = 1 }, 3837 { /* end of list */ }, 3838 }, 3839 }, 3840 { 3841 .name = "Denverton", 3842 .level = 21, 3843 .vendor = CPUID_VENDOR_INTEL, 3844 .family = 6, 3845 .model = 95, 3846 .stepping = 1, 3847 .features[FEAT_1_EDX] = 3848 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3849 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3850 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3851 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3852 CPUID_SSE | CPUID_SSE2, 3853 .features[FEAT_1_ECX] = 3854 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3855 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3856 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3857 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3858 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3859 .features[FEAT_8000_0001_EDX] = 3860 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3861 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3862 .features[FEAT_8000_0001_ECX] = 3863 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3864 .features[FEAT_7_0_EBX] = 3865 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3866 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3867 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3868 .features[FEAT_7_0_EDX] = 3869 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3870 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3871 /* XSAVES is added in version 3 */ 3872 .features[FEAT_XSAVE] = 3873 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3874 .features[FEAT_6_EAX] = 3875 CPUID_6_EAX_ARAT, 3876 .features[FEAT_ARCH_CAPABILITIES] = 3877 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3878 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3879 MSR_VMX_BASIC_TRUE_CTLS, 3880 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3881 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3882 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3883 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3884 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3885 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3886 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3887 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3888 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3889 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3890 .features[FEAT_VMX_EXIT_CTLS] = 3891 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3892 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3893 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3894 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3895 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3896 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3897 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3898 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3899 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3900 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3901 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3902 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3903 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3904 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3905 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3906 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3907 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3908 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3909 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3910 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3911 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3912 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3913 .features[FEAT_VMX_SECONDARY_CTLS] = 3914 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3915 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3916 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3917 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3918 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3919 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3920 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3921 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3922 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3923 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3924 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3925 .xlevel = 0x80000008, 3926 .model_id = "Intel Atom Processor (Denverton)", 3927 .versions = (X86CPUVersionDefinition[]) { 3928 { .version = 1 }, 3929 { 3930 .version = 2, 3931 .note = "no MPX, no MONITOR", 3932 .props = (PropValue[]) { 3933 { "monitor", "off" }, 3934 { "mpx", "off" }, 3935 { /* end of list */ }, 3936 }, 3937 }, 3938 { 3939 .version = 3, 3940 .note = "XSAVES, no MPX, no MONITOR", 3941 .props = (PropValue[]) { 3942 { "xsaves", "on" }, 3943 { "vmx-xsaves", "on" }, 3944 { /* end of list */ }, 3945 }, 3946 }, 3947 { /* end of list */ }, 3948 }, 3949 }, 3950 { 3951 .name = "Snowridge", 3952 .level = 27, 3953 .vendor = CPUID_VENDOR_INTEL, 3954 .family = 6, 3955 .model = 134, 3956 .stepping = 1, 3957 .features[FEAT_1_EDX] = 3958 /* missing: CPUID_PN CPUID_IA64 */ 3959 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3960 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3961 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3962 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3963 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3964 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3965 CPUID_MMX | 3966 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3967 .features[FEAT_1_ECX] = 3968 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3969 CPUID_EXT_SSSE3 | 3970 CPUID_EXT_CX16 | 3971 CPUID_EXT_SSE41 | 3972 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3973 CPUID_EXT_POPCNT | 3974 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3975 CPUID_EXT_RDRAND, 3976 .features[FEAT_8000_0001_EDX] = 3977 CPUID_EXT2_SYSCALL | 3978 CPUID_EXT2_NX | 3979 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3980 CPUID_EXT2_LM, 3981 .features[FEAT_8000_0001_ECX] = 3982 CPUID_EXT3_LAHF_LM | 3983 CPUID_EXT3_3DNOWPREFETCH, 3984 .features[FEAT_7_0_EBX] = 3985 CPUID_7_0_EBX_FSGSBASE | 3986 CPUID_7_0_EBX_SMEP | 3987 CPUID_7_0_EBX_ERMS | 3988 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3989 CPUID_7_0_EBX_RDSEED | 3990 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3991 CPUID_7_0_EBX_CLWB | 3992 CPUID_7_0_EBX_SHA_NI, 3993 .features[FEAT_7_0_ECX] = 3994 CPUID_7_0_ECX_UMIP | 3995 /* missing bit 5 */ 3996 CPUID_7_0_ECX_GFNI | 3997 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3998 CPUID_7_0_ECX_MOVDIR64B, 3999 .features[FEAT_7_0_EDX] = 4000 CPUID_7_0_EDX_SPEC_CTRL | 4001 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4002 CPUID_7_0_EDX_CORE_CAPABILITY, 4003 .features[FEAT_CORE_CAPABILITY] = 4004 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4005 /* XSAVES is added in version 3 */ 4006 .features[FEAT_XSAVE] = 4007 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4008 CPUID_XSAVE_XGETBV1, 4009 .features[FEAT_6_EAX] = 4010 CPUID_6_EAX_ARAT, 4011 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4012 MSR_VMX_BASIC_TRUE_CTLS, 4013 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4014 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4015 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4016 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4017 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4018 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4019 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4020 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4021 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4022 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4023 .features[FEAT_VMX_EXIT_CTLS] = 4024 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4025 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4026 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4027 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4028 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4029 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4030 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4031 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4032 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4033 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4034 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4035 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4036 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4037 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4038 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4039 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4040 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4041 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4042 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4043 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4044 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4045 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4046 .features[FEAT_VMX_SECONDARY_CTLS] = 4047 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4048 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4049 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4050 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4051 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4052 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4053 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4054 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4055 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4056 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4057 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4058 .xlevel = 0x80000008, 4059 .model_id = "Intel Atom Processor (SnowRidge)", 4060 .versions = (X86CPUVersionDefinition[]) { 4061 { .version = 1 }, 4062 { 4063 .version = 2, 4064 .props = (PropValue[]) { 4065 { "mpx", "off" }, 4066 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4067 { /* end of list */ }, 4068 }, 4069 }, 4070 { 4071 .version = 3, 4072 .note = "XSAVES, no MPX", 4073 .props = (PropValue[]) { 4074 { "xsaves", "on" }, 4075 { "vmx-xsaves", "on" }, 4076 { /* end of list */ }, 4077 }, 4078 }, 4079 { 4080 .version = 4, 4081 .note = "no split lock detect, no core-capability", 4082 .props = (PropValue[]) { 4083 { "split-lock-detect", "off" }, 4084 { "core-capability", "off" }, 4085 { /* end of list */ }, 4086 }, 4087 }, 4088 { /* end of list */ }, 4089 }, 4090 }, 4091 { 4092 .name = "KnightsMill", 4093 .level = 0xd, 4094 .vendor = CPUID_VENDOR_INTEL, 4095 .family = 6, 4096 .model = 133, 4097 .stepping = 0, 4098 .features[FEAT_1_EDX] = 4099 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4100 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4101 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4102 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4103 CPUID_PSE | CPUID_DE | CPUID_FP87, 4104 .features[FEAT_1_ECX] = 4105 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4106 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4107 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4108 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4109 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4110 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4111 .features[FEAT_8000_0001_EDX] = 4112 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4113 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4114 .features[FEAT_8000_0001_ECX] = 4115 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4116 .features[FEAT_7_0_EBX] = 4117 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4118 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4119 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4120 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4121 CPUID_7_0_EBX_AVX512ER, 4122 .features[FEAT_7_0_ECX] = 4123 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4124 .features[FEAT_7_0_EDX] = 4125 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4126 .features[FEAT_XSAVE] = 4127 CPUID_XSAVE_XSAVEOPT, 4128 .features[FEAT_6_EAX] = 4129 CPUID_6_EAX_ARAT, 4130 .xlevel = 0x80000008, 4131 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4132 }, 4133 { 4134 .name = "Opteron_G1", 4135 .level = 5, 4136 .vendor = CPUID_VENDOR_AMD, 4137 .family = 15, 4138 .model = 6, 4139 .stepping = 1, 4140 .features[FEAT_1_EDX] = 4141 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4142 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4143 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4144 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4145 CPUID_DE | CPUID_FP87, 4146 .features[FEAT_1_ECX] = 4147 CPUID_EXT_SSE3, 4148 .features[FEAT_8000_0001_EDX] = 4149 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4150 .xlevel = 0x80000008, 4151 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4152 }, 4153 { 4154 .name = "Opteron_G2", 4155 .level = 5, 4156 .vendor = CPUID_VENDOR_AMD, 4157 .family = 15, 4158 .model = 6, 4159 .stepping = 1, 4160 .features[FEAT_1_EDX] = 4161 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4162 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4163 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4164 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4165 CPUID_DE | CPUID_FP87, 4166 .features[FEAT_1_ECX] = 4167 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4168 .features[FEAT_8000_0001_EDX] = 4169 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4170 .features[FEAT_8000_0001_ECX] = 4171 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4172 .xlevel = 0x80000008, 4173 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4174 }, 4175 { 4176 .name = "Opteron_G3", 4177 .level = 5, 4178 .vendor = CPUID_VENDOR_AMD, 4179 .family = 16, 4180 .model = 2, 4181 .stepping = 3, 4182 .features[FEAT_1_EDX] = 4183 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4184 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4185 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4186 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4187 CPUID_DE | CPUID_FP87, 4188 .features[FEAT_1_ECX] = 4189 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4190 CPUID_EXT_SSE3, 4191 .features[FEAT_8000_0001_EDX] = 4192 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4193 CPUID_EXT2_RDTSCP, 4194 .features[FEAT_8000_0001_ECX] = 4195 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4196 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4197 .xlevel = 0x80000008, 4198 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4199 }, 4200 { 4201 .name = "Opteron_G4", 4202 .level = 0xd, 4203 .vendor = CPUID_VENDOR_AMD, 4204 .family = 21, 4205 .model = 1, 4206 .stepping = 2, 4207 .features[FEAT_1_EDX] = 4208 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4209 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4210 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4211 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4212 CPUID_DE | CPUID_FP87, 4213 .features[FEAT_1_ECX] = 4214 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4215 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4216 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4217 CPUID_EXT_SSE3, 4218 .features[FEAT_8000_0001_EDX] = 4219 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4220 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4221 .features[FEAT_8000_0001_ECX] = 4222 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4223 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4224 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4225 CPUID_EXT3_LAHF_LM, 4226 .features[FEAT_SVM] = 4227 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4228 /* no xsaveopt! */ 4229 .xlevel = 0x8000001A, 4230 .model_id = "AMD Opteron 62xx class CPU", 4231 }, 4232 { 4233 .name = "Opteron_G5", 4234 .level = 0xd, 4235 .vendor = CPUID_VENDOR_AMD, 4236 .family = 21, 4237 .model = 2, 4238 .stepping = 0, 4239 .features[FEAT_1_EDX] = 4240 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4241 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4242 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4243 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4244 CPUID_DE | CPUID_FP87, 4245 .features[FEAT_1_ECX] = 4246 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4247 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4248 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4249 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4250 .features[FEAT_8000_0001_EDX] = 4251 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4252 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4253 .features[FEAT_8000_0001_ECX] = 4254 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4255 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4256 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4257 CPUID_EXT3_LAHF_LM, 4258 .features[FEAT_SVM] = 4259 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4260 /* no xsaveopt! */ 4261 .xlevel = 0x8000001A, 4262 .model_id = "AMD Opteron 63xx class CPU", 4263 }, 4264 { 4265 .name = "EPYC", 4266 .level = 0xd, 4267 .vendor = CPUID_VENDOR_AMD, 4268 .family = 23, 4269 .model = 1, 4270 .stepping = 2, 4271 .features[FEAT_1_EDX] = 4272 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4273 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4274 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4275 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4276 CPUID_VME | CPUID_FP87, 4277 .features[FEAT_1_ECX] = 4278 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4279 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4280 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4281 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4282 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4283 .features[FEAT_8000_0001_EDX] = 4284 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4285 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4286 CPUID_EXT2_SYSCALL, 4287 .features[FEAT_8000_0001_ECX] = 4288 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4289 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4290 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4291 CPUID_EXT3_TOPOEXT, 4292 .features[FEAT_7_0_EBX] = 4293 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4294 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4295 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4296 CPUID_7_0_EBX_SHA_NI, 4297 .features[FEAT_XSAVE] = 4298 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4299 CPUID_XSAVE_XGETBV1, 4300 .features[FEAT_6_EAX] = 4301 CPUID_6_EAX_ARAT, 4302 .features[FEAT_SVM] = 4303 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4304 .xlevel = 0x8000001E, 4305 .model_id = "AMD EPYC Processor", 4306 .cache_info = &epyc_cache_info, 4307 .versions = (X86CPUVersionDefinition[]) { 4308 { .version = 1 }, 4309 { 4310 .version = 2, 4311 .alias = "EPYC-IBPB", 4312 .props = (PropValue[]) { 4313 { "ibpb", "on" }, 4314 { "model-id", 4315 "AMD EPYC Processor (with IBPB)" }, 4316 { /* end of list */ } 4317 } 4318 }, 4319 { 4320 .version = 3, 4321 .props = (PropValue[]) { 4322 { "ibpb", "on" }, 4323 { "perfctr-core", "on" }, 4324 { "clzero", "on" }, 4325 { "xsaveerptr", "on" }, 4326 { "xsaves", "on" }, 4327 { "model-id", 4328 "AMD EPYC Processor" }, 4329 { /* end of list */ } 4330 } 4331 }, 4332 { 4333 .version = 4, 4334 .props = (PropValue[]) { 4335 { "model-id", 4336 "AMD EPYC-v4 Processor" }, 4337 { /* end of list */ } 4338 }, 4339 .cache_info = &epyc_v4_cache_info 4340 }, 4341 { /* end of list */ } 4342 } 4343 }, 4344 { 4345 .name = "Dhyana", 4346 .level = 0xd, 4347 .vendor = CPUID_VENDOR_HYGON, 4348 .family = 24, 4349 .model = 0, 4350 .stepping = 1, 4351 .features[FEAT_1_EDX] = 4352 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4353 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4354 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4355 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4356 CPUID_VME | CPUID_FP87, 4357 .features[FEAT_1_ECX] = 4358 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4359 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4360 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4361 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4362 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4363 .features[FEAT_8000_0001_EDX] = 4364 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4365 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4366 CPUID_EXT2_SYSCALL, 4367 .features[FEAT_8000_0001_ECX] = 4368 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4369 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4370 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4371 CPUID_EXT3_TOPOEXT, 4372 .features[FEAT_8000_0008_EBX] = 4373 CPUID_8000_0008_EBX_IBPB, 4374 .features[FEAT_7_0_EBX] = 4375 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4376 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4377 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4378 /* XSAVES is added in version 2 */ 4379 .features[FEAT_XSAVE] = 4380 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4381 CPUID_XSAVE_XGETBV1, 4382 .features[FEAT_6_EAX] = 4383 CPUID_6_EAX_ARAT, 4384 .features[FEAT_SVM] = 4385 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4386 .xlevel = 0x8000001E, 4387 .model_id = "Hygon Dhyana Processor", 4388 .cache_info = &epyc_cache_info, 4389 .versions = (X86CPUVersionDefinition[]) { 4390 { .version = 1 }, 4391 { .version = 2, 4392 .note = "XSAVES", 4393 .props = (PropValue[]) { 4394 { "xsaves", "on" }, 4395 { /* end of list */ } 4396 }, 4397 }, 4398 { /* end of list */ } 4399 } 4400 }, 4401 { 4402 .name = "EPYC-Rome", 4403 .level = 0xd, 4404 .vendor = CPUID_VENDOR_AMD, 4405 .family = 23, 4406 .model = 49, 4407 .stepping = 0, 4408 .features[FEAT_1_EDX] = 4409 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4410 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4411 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4412 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4413 CPUID_VME | CPUID_FP87, 4414 .features[FEAT_1_ECX] = 4415 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4416 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4417 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4418 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4419 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4420 .features[FEAT_8000_0001_EDX] = 4421 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4422 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4423 CPUID_EXT2_SYSCALL, 4424 .features[FEAT_8000_0001_ECX] = 4425 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4426 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4427 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4428 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4429 .features[FEAT_8000_0008_EBX] = 4430 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4431 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4432 CPUID_8000_0008_EBX_STIBP, 4433 .features[FEAT_7_0_EBX] = 4434 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4435 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4436 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4437 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4438 .features[FEAT_7_0_ECX] = 4439 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4440 .features[FEAT_XSAVE] = 4441 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4442 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4443 .features[FEAT_6_EAX] = 4444 CPUID_6_EAX_ARAT, 4445 .features[FEAT_SVM] = 4446 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4447 .xlevel = 0x8000001E, 4448 .model_id = "AMD EPYC-Rome Processor", 4449 .cache_info = &epyc_rome_cache_info, 4450 .versions = (X86CPUVersionDefinition[]) { 4451 { .version = 1 }, 4452 { 4453 .version = 2, 4454 .props = (PropValue[]) { 4455 { "ibrs", "on" }, 4456 { "amd-ssbd", "on" }, 4457 { /* end of list */ } 4458 } 4459 }, 4460 { 4461 .version = 3, 4462 .props = (PropValue[]) { 4463 { "model-id", 4464 "AMD EPYC-Rome-v3 Processor" }, 4465 { /* end of list */ } 4466 }, 4467 .cache_info = &epyc_rome_v3_cache_info 4468 }, 4469 { 4470 .version = 4, 4471 .props = (PropValue[]) { 4472 /* Erratum 1386 */ 4473 { "model-id", 4474 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 4475 { "xsaves", "off" }, 4476 { /* end of list */ } 4477 }, 4478 }, 4479 { /* end of list */ } 4480 } 4481 }, 4482 { 4483 .name = "EPYC-Milan", 4484 .level = 0xd, 4485 .vendor = CPUID_VENDOR_AMD, 4486 .family = 25, 4487 .model = 1, 4488 .stepping = 1, 4489 .features[FEAT_1_EDX] = 4490 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4491 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4492 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4493 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4494 CPUID_VME | CPUID_FP87, 4495 .features[FEAT_1_ECX] = 4496 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4497 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4498 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4499 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4500 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4501 CPUID_EXT_PCID, 4502 .features[FEAT_8000_0001_EDX] = 4503 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4504 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4505 CPUID_EXT2_SYSCALL, 4506 .features[FEAT_8000_0001_ECX] = 4507 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4508 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4509 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4510 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4511 .features[FEAT_8000_0008_EBX] = 4512 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4513 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4514 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4515 CPUID_8000_0008_EBX_AMD_SSBD, 4516 .features[FEAT_7_0_EBX] = 4517 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4518 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4519 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4520 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4521 CPUID_7_0_EBX_INVPCID, 4522 .features[FEAT_7_0_ECX] = 4523 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4524 .features[FEAT_7_0_EDX] = 4525 CPUID_7_0_EDX_FSRM, 4526 .features[FEAT_XSAVE] = 4527 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4528 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4529 .features[FEAT_6_EAX] = 4530 CPUID_6_EAX_ARAT, 4531 .features[FEAT_SVM] = 4532 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4533 .xlevel = 0x8000001E, 4534 .model_id = "AMD EPYC-Milan Processor", 4535 .cache_info = &epyc_milan_cache_info, 4536 .versions = (X86CPUVersionDefinition[]) { 4537 { .version = 1 }, 4538 { 4539 .version = 2, 4540 .props = (PropValue[]) { 4541 { "model-id", 4542 "AMD EPYC-Milan-v2 Processor" }, 4543 { "vaes", "on" }, 4544 { "vpclmulqdq", "on" }, 4545 { "stibp-always-on", "on" }, 4546 { "amd-psfd", "on" }, 4547 { "no-nested-data-bp", "on" }, 4548 { "lfence-always-serializing", "on" }, 4549 { "null-sel-clr-base", "on" }, 4550 { /* end of list */ } 4551 }, 4552 .cache_info = &epyc_milan_v2_cache_info 4553 }, 4554 { /* end of list */ } 4555 } 4556 }, 4557 { 4558 .name = "EPYC-Genoa", 4559 .level = 0xd, 4560 .vendor = CPUID_VENDOR_AMD, 4561 .family = 25, 4562 .model = 17, 4563 .stepping = 0, 4564 .features[FEAT_1_EDX] = 4565 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4566 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4567 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4568 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4569 CPUID_VME | CPUID_FP87, 4570 .features[FEAT_1_ECX] = 4571 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4572 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4573 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4574 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4575 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 4576 CPUID_EXT_SSE3, 4577 .features[FEAT_8000_0001_EDX] = 4578 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4579 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4580 CPUID_EXT2_SYSCALL, 4581 .features[FEAT_8000_0001_ECX] = 4582 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4583 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4584 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4585 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4586 .features[FEAT_8000_0008_EBX] = 4587 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4588 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4589 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4590 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 4591 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 4592 .features[FEAT_8000_0021_EAX] = 4593 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 4594 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 4595 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 4596 CPUID_8000_0021_EAX_AUTO_IBRS, 4597 .features[FEAT_7_0_EBX] = 4598 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4599 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4600 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 4601 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4602 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 4603 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4604 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4605 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4606 .features[FEAT_7_0_ECX] = 4607 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4608 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4609 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4610 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4611 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4612 CPUID_7_0_ECX_RDPID, 4613 .features[FEAT_7_0_EDX] = 4614 CPUID_7_0_EDX_FSRM, 4615 .features[FEAT_7_1_EAX] = 4616 CPUID_7_1_EAX_AVX512_BF16, 4617 .features[FEAT_XSAVE] = 4618 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4619 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4620 .features[FEAT_6_EAX] = 4621 CPUID_6_EAX_ARAT, 4622 .features[FEAT_SVM] = 4623 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 4624 CPUID_SVM_SVME_ADDR_CHK, 4625 .xlevel = 0x80000022, 4626 .model_id = "AMD EPYC-Genoa Processor", 4627 .cache_info = &epyc_genoa_cache_info, 4628 }, 4629 }; 4630 4631 /* 4632 * We resolve CPU model aliases using -v1 when using "-machine 4633 * none", but this is just for compatibility while libvirt isn't 4634 * adapted to resolve CPU model versions before creating VMs. 4635 * See "Runnability guarantee of CPU models" at 4636 * docs/about/deprecated.rst. 4637 */ 4638 X86CPUVersion default_cpu_version = 1; 4639 4640 void x86_cpu_set_default_version(X86CPUVersion version) 4641 { 4642 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4643 assert(version != CPU_VERSION_AUTO); 4644 default_cpu_version = version; 4645 } 4646 4647 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4648 { 4649 int v = 0; 4650 const X86CPUVersionDefinition *vdef = 4651 x86_cpu_def_get_versions(model->cpudef); 4652 while (vdef->version) { 4653 v = vdef->version; 4654 vdef++; 4655 } 4656 return v; 4657 } 4658 4659 /* Return the actual version being used for a specific CPU model */ 4660 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4661 { 4662 X86CPUVersion v = model->version; 4663 if (v == CPU_VERSION_AUTO) { 4664 v = default_cpu_version; 4665 } 4666 if (v == CPU_VERSION_LATEST) { 4667 return x86_cpu_model_last_version(model); 4668 } 4669 return v; 4670 } 4671 4672 static Property max_x86_cpu_properties[] = { 4673 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4674 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4675 DEFINE_PROP_END_OF_LIST() 4676 }; 4677 4678 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 4679 { 4680 Object *obj = OBJECT(dev); 4681 4682 if (!object_property_get_int(obj, "family", &error_abort)) { 4683 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 4684 object_property_set_int(obj, "family", 15, &error_abort); 4685 object_property_set_int(obj, "model", 107, &error_abort); 4686 object_property_set_int(obj, "stepping", 1, &error_abort); 4687 } else { 4688 object_property_set_int(obj, "family", 6, &error_abort); 4689 object_property_set_int(obj, "model", 6, &error_abort); 4690 object_property_set_int(obj, "stepping", 3, &error_abort); 4691 } 4692 } 4693 4694 x86_cpu_realizefn(dev, errp); 4695 } 4696 4697 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4698 { 4699 DeviceClass *dc = DEVICE_CLASS(oc); 4700 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4701 4702 xcc->ordering = 9; 4703 4704 xcc->model_description = 4705 "Enables all features supported by the accelerator in the current host"; 4706 4707 device_class_set_props(dc, max_x86_cpu_properties); 4708 dc->realize = max_x86_cpu_realize; 4709 } 4710 4711 static void max_x86_cpu_initfn(Object *obj) 4712 { 4713 X86CPU *cpu = X86_CPU(obj); 4714 4715 /* We can't fill the features array here because we don't know yet if 4716 * "migratable" is true or false. 4717 */ 4718 cpu->max_features = true; 4719 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4720 4721 /* 4722 * these defaults are used for TCG and all other accelerators 4723 * besides KVM and HVF, which overwrite these values 4724 */ 4725 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4726 &error_abort); 4727 object_property_set_str(OBJECT(cpu), "model-id", 4728 "QEMU TCG CPU version " QEMU_HW_VERSION, 4729 &error_abort); 4730 } 4731 4732 static const TypeInfo max_x86_cpu_type_info = { 4733 .name = X86_CPU_TYPE_NAME("max"), 4734 .parent = TYPE_X86_CPU, 4735 .instance_init = max_x86_cpu_initfn, 4736 .class_init = max_x86_cpu_class_init, 4737 }; 4738 4739 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4740 { 4741 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4742 4743 switch (f->type) { 4744 case CPUID_FEATURE_WORD: 4745 { 4746 const char *reg = get_register_name_32(f->cpuid.reg); 4747 assert(reg); 4748 return g_strdup_printf("CPUID.%02XH:%s", 4749 f->cpuid.eax, reg); 4750 } 4751 case MSR_FEATURE_WORD: 4752 return g_strdup_printf("MSR(%02XH)", 4753 f->msr.index); 4754 } 4755 4756 return NULL; 4757 } 4758 4759 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4760 { 4761 FeatureWord w; 4762 4763 for (w = 0; w < FEATURE_WORDS; w++) { 4764 if (cpu->filtered_features[w]) { 4765 return true; 4766 } 4767 } 4768 4769 return false; 4770 } 4771 4772 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4773 const char *verbose_prefix) 4774 { 4775 CPUX86State *env = &cpu->env; 4776 FeatureWordInfo *f = &feature_word_info[w]; 4777 int i; 4778 4779 if (!cpu->force_features) { 4780 env->features[w] &= ~mask; 4781 } 4782 cpu->filtered_features[w] |= mask; 4783 4784 if (!verbose_prefix) { 4785 return; 4786 } 4787 4788 for (i = 0; i < 64; ++i) { 4789 if ((1ULL << i) & mask) { 4790 g_autofree char *feat_word_str = feature_word_description(f, i); 4791 warn_report("%s: %s%s%s [bit %d]", 4792 verbose_prefix, 4793 feat_word_str, 4794 f->feat_names[i] ? "." : "", 4795 f->feat_names[i] ? f->feat_names[i] : "", i); 4796 } 4797 } 4798 } 4799 4800 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4801 const char *name, void *opaque, 4802 Error **errp) 4803 { 4804 X86CPU *cpu = X86_CPU(obj); 4805 CPUX86State *env = &cpu->env; 4806 int64_t value; 4807 4808 value = (env->cpuid_version >> 8) & 0xf; 4809 if (value == 0xf) { 4810 value += (env->cpuid_version >> 20) & 0xff; 4811 } 4812 visit_type_int(v, name, &value, errp); 4813 } 4814 4815 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4816 const char *name, void *opaque, 4817 Error **errp) 4818 { 4819 X86CPU *cpu = X86_CPU(obj); 4820 CPUX86State *env = &cpu->env; 4821 const int64_t min = 0; 4822 const int64_t max = 0xff + 0xf; 4823 int64_t value; 4824 4825 if (!visit_type_int(v, name, &value, errp)) { 4826 return; 4827 } 4828 if (value < min || value > max) { 4829 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4830 name ? name : "null", value, min, max); 4831 return; 4832 } 4833 4834 env->cpuid_version &= ~0xff00f00; 4835 if (value > 0x0f) { 4836 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4837 } else { 4838 env->cpuid_version |= value << 8; 4839 } 4840 } 4841 4842 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4843 const char *name, void *opaque, 4844 Error **errp) 4845 { 4846 X86CPU *cpu = X86_CPU(obj); 4847 CPUX86State *env = &cpu->env; 4848 int64_t value; 4849 4850 value = (env->cpuid_version >> 4) & 0xf; 4851 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4852 visit_type_int(v, name, &value, errp); 4853 } 4854 4855 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4856 const char *name, void *opaque, 4857 Error **errp) 4858 { 4859 X86CPU *cpu = X86_CPU(obj); 4860 CPUX86State *env = &cpu->env; 4861 const int64_t min = 0; 4862 const int64_t max = 0xff; 4863 int64_t value; 4864 4865 if (!visit_type_int(v, name, &value, errp)) { 4866 return; 4867 } 4868 if (value < min || value > max) { 4869 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4870 name ? name : "null", value, min, max); 4871 return; 4872 } 4873 4874 env->cpuid_version &= ~0xf00f0; 4875 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4876 } 4877 4878 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4879 const char *name, void *opaque, 4880 Error **errp) 4881 { 4882 X86CPU *cpu = X86_CPU(obj); 4883 CPUX86State *env = &cpu->env; 4884 int64_t value; 4885 4886 value = env->cpuid_version & 0xf; 4887 visit_type_int(v, name, &value, errp); 4888 } 4889 4890 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4891 const char *name, void *opaque, 4892 Error **errp) 4893 { 4894 X86CPU *cpu = X86_CPU(obj); 4895 CPUX86State *env = &cpu->env; 4896 const int64_t min = 0; 4897 const int64_t max = 0xf; 4898 int64_t value; 4899 4900 if (!visit_type_int(v, name, &value, errp)) { 4901 return; 4902 } 4903 if (value < min || value > max) { 4904 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4905 name ? name : "null", value, min, max); 4906 return; 4907 } 4908 4909 env->cpuid_version &= ~0xf; 4910 env->cpuid_version |= value & 0xf; 4911 } 4912 4913 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4914 { 4915 X86CPU *cpu = X86_CPU(obj); 4916 CPUX86State *env = &cpu->env; 4917 char *value; 4918 4919 value = g_malloc(CPUID_VENDOR_SZ + 1); 4920 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4921 env->cpuid_vendor3); 4922 return value; 4923 } 4924 4925 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4926 Error **errp) 4927 { 4928 X86CPU *cpu = X86_CPU(obj); 4929 CPUX86State *env = &cpu->env; 4930 int i; 4931 4932 if (strlen(value) != CPUID_VENDOR_SZ) { 4933 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4934 return; 4935 } 4936 4937 env->cpuid_vendor1 = 0; 4938 env->cpuid_vendor2 = 0; 4939 env->cpuid_vendor3 = 0; 4940 for (i = 0; i < 4; i++) { 4941 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4942 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4943 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4944 } 4945 } 4946 4947 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4948 { 4949 X86CPU *cpu = X86_CPU(obj); 4950 CPUX86State *env = &cpu->env; 4951 char *value; 4952 int i; 4953 4954 value = g_malloc(48 + 1); 4955 for (i = 0; i < 48; i++) { 4956 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4957 } 4958 value[48] = '\0'; 4959 return value; 4960 } 4961 4962 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4963 Error **errp) 4964 { 4965 X86CPU *cpu = X86_CPU(obj); 4966 CPUX86State *env = &cpu->env; 4967 int c, len, i; 4968 4969 if (model_id == NULL) { 4970 model_id = ""; 4971 } 4972 len = strlen(model_id); 4973 memset(env->cpuid_model, 0, 48); 4974 for (i = 0; i < 48; i++) { 4975 if (i >= len) { 4976 c = '\0'; 4977 } else { 4978 c = (uint8_t)model_id[i]; 4979 } 4980 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4981 } 4982 } 4983 4984 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4985 void *opaque, Error **errp) 4986 { 4987 X86CPU *cpu = X86_CPU(obj); 4988 int64_t value; 4989 4990 value = cpu->env.tsc_khz * 1000; 4991 visit_type_int(v, name, &value, errp); 4992 } 4993 4994 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4995 void *opaque, Error **errp) 4996 { 4997 X86CPU *cpu = X86_CPU(obj); 4998 const int64_t min = 0; 4999 const int64_t max = INT64_MAX; 5000 int64_t value; 5001 5002 if (!visit_type_int(v, name, &value, errp)) { 5003 return; 5004 } 5005 if (value < min || value > max) { 5006 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5007 name ? name : "null", value, min, max); 5008 return; 5009 } 5010 5011 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5012 } 5013 5014 /* Generic getter for "feature-words" and "filtered-features" properties */ 5015 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5016 const char *name, void *opaque, 5017 Error **errp) 5018 { 5019 uint64_t *array = (uint64_t *)opaque; 5020 FeatureWord w; 5021 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5022 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5023 X86CPUFeatureWordInfoList *list = NULL; 5024 5025 for (w = 0; w < FEATURE_WORDS; w++) { 5026 FeatureWordInfo *wi = &feature_word_info[w]; 5027 /* 5028 * We didn't have MSR features when "feature-words" was 5029 * introduced. Therefore skipped other type entries. 5030 */ 5031 if (wi->type != CPUID_FEATURE_WORD) { 5032 continue; 5033 } 5034 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5035 qwi->cpuid_input_eax = wi->cpuid.eax; 5036 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5037 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5038 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5039 qwi->features = array[w]; 5040 5041 /* List will be in reverse order, but order shouldn't matter */ 5042 list_entries[w].next = list; 5043 list_entries[w].value = &word_infos[w]; 5044 list = &list_entries[w]; 5045 } 5046 5047 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5048 } 5049 5050 /* Convert all '_' in a feature string option name to '-', to make feature 5051 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5052 */ 5053 static inline void feat2prop(char *s) 5054 { 5055 while ((s = strchr(s, '_'))) { 5056 *s = '-'; 5057 } 5058 } 5059 5060 /* Return the feature property name for a feature flag bit */ 5061 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5062 { 5063 const char *name; 5064 /* XSAVE components are automatically enabled by other features, 5065 * so return the original feature name instead 5066 */ 5067 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5068 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5069 5070 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5071 x86_ext_save_areas[comp].bits) { 5072 w = x86_ext_save_areas[comp].feature; 5073 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5074 } 5075 } 5076 5077 assert(bitnr < 64); 5078 assert(w < FEATURE_WORDS); 5079 name = feature_word_info[w].feat_names[bitnr]; 5080 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5081 return name; 5082 } 5083 5084 /* Compatibily hack to maintain legacy +-feat semantic, 5085 * where +-feat overwrites any feature set by 5086 * feat=on|feat even if the later is parsed after +-feat 5087 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5088 */ 5089 static GList *plus_features, *minus_features; 5090 5091 static gint compare_string(gconstpointer a, gconstpointer b) 5092 { 5093 return g_strcmp0(a, b); 5094 } 5095 5096 /* Parse "+feature,-feature,feature=foo" CPU feature string 5097 */ 5098 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5099 Error **errp) 5100 { 5101 char *featurestr; /* Single 'key=value" string being parsed */ 5102 static bool cpu_globals_initialized; 5103 bool ambiguous = false; 5104 5105 if (cpu_globals_initialized) { 5106 return; 5107 } 5108 cpu_globals_initialized = true; 5109 5110 if (!features) { 5111 return; 5112 } 5113 5114 for (featurestr = strtok(features, ","); 5115 featurestr; 5116 featurestr = strtok(NULL, ",")) { 5117 const char *name; 5118 const char *val = NULL; 5119 char *eq = NULL; 5120 char num[32]; 5121 GlobalProperty *prop; 5122 5123 /* Compatibility syntax: */ 5124 if (featurestr[0] == '+') { 5125 plus_features = g_list_append(plus_features, 5126 g_strdup(featurestr + 1)); 5127 continue; 5128 } else if (featurestr[0] == '-') { 5129 minus_features = g_list_append(minus_features, 5130 g_strdup(featurestr + 1)); 5131 continue; 5132 } 5133 5134 eq = strchr(featurestr, '='); 5135 if (eq) { 5136 *eq++ = 0; 5137 val = eq; 5138 } else { 5139 val = "on"; 5140 } 5141 5142 feat2prop(featurestr); 5143 name = featurestr; 5144 5145 if (g_list_find_custom(plus_features, name, compare_string)) { 5146 warn_report("Ambiguous CPU model string. " 5147 "Don't mix both \"+%s\" and \"%s=%s\"", 5148 name, name, val); 5149 ambiguous = true; 5150 } 5151 if (g_list_find_custom(minus_features, name, compare_string)) { 5152 warn_report("Ambiguous CPU model string. " 5153 "Don't mix both \"-%s\" and \"%s=%s\"", 5154 name, name, val); 5155 ambiguous = true; 5156 } 5157 5158 /* Special case: */ 5159 if (!strcmp(name, "tsc-freq")) { 5160 int ret; 5161 uint64_t tsc_freq; 5162 5163 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5164 if (ret < 0 || tsc_freq > INT64_MAX) { 5165 error_setg(errp, "bad numerical value %s", val); 5166 return; 5167 } 5168 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5169 val = num; 5170 name = "tsc-frequency"; 5171 } 5172 5173 prop = g_new0(typeof(*prop), 1); 5174 prop->driver = typename; 5175 prop->property = g_strdup(name); 5176 prop->value = g_strdup(val); 5177 qdev_prop_register_global(prop); 5178 } 5179 5180 if (ambiguous) { 5181 warn_report("Compatibility of ambiguous CPU model " 5182 "strings won't be kept on future QEMU versions"); 5183 } 5184 } 5185 5186 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5187 5188 /* Build a list with the name of all features on a feature word array */ 5189 static void x86_cpu_list_feature_names(FeatureWordArray features, 5190 strList **list) 5191 { 5192 strList **tail = list; 5193 FeatureWord w; 5194 5195 for (w = 0; w < FEATURE_WORDS; w++) { 5196 uint64_t filtered = features[w]; 5197 int i; 5198 for (i = 0; i < 64; i++) { 5199 if (filtered & (1ULL << i)) { 5200 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5201 } 5202 } 5203 } 5204 } 5205 5206 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5207 const char *name, void *opaque, 5208 Error **errp) 5209 { 5210 X86CPU *xc = X86_CPU(obj); 5211 strList *result = NULL; 5212 5213 x86_cpu_list_feature_names(xc->filtered_features, &result); 5214 visit_type_strList(v, "unavailable-features", &result, errp); 5215 } 5216 5217 /* Print all cpuid feature names in featureset 5218 */ 5219 static void listflags(GList *features) 5220 { 5221 size_t len = 0; 5222 GList *tmp; 5223 5224 for (tmp = features; tmp; tmp = tmp->next) { 5225 const char *name = tmp->data; 5226 if ((len + strlen(name) + 1) >= 75) { 5227 qemu_printf("\n"); 5228 len = 0; 5229 } 5230 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5231 len += strlen(name) + 1; 5232 } 5233 qemu_printf("\n"); 5234 } 5235 5236 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5237 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5238 { 5239 ObjectClass *class_a = (ObjectClass *)a; 5240 ObjectClass *class_b = (ObjectClass *)b; 5241 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5242 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5243 int ret; 5244 5245 if (cc_a->ordering != cc_b->ordering) { 5246 ret = cc_a->ordering - cc_b->ordering; 5247 } else { 5248 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5249 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5250 ret = strcmp(name_a, name_b); 5251 } 5252 return ret; 5253 } 5254 5255 static GSList *get_sorted_cpu_model_list(void) 5256 { 5257 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5258 list = g_slist_sort(list, x86_cpu_list_compare); 5259 return list; 5260 } 5261 5262 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5263 { 5264 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5265 char *r = object_property_get_str(obj, "model-id", &error_abort); 5266 object_unref(obj); 5267 return r; 5268 } 5269 5270 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5271 { 5272 X86CPUVersion version; 5273 5274 if (!cc->model || !cc->model->is_alias) { 5275 return NULL; 5276 } 5277 version = x86_cpu_model_resolve_version(cc->model); 5278 if (version <= 0) { 5279 return NULL; 5280 } 5281 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5282 } 5283 5284 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5285 { 5286 ObjectClass *oc = data; 5287 X86CPUClass *cc = X86_CPU_CLASS(oc); 5288 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5289 g_autofree char *desc = g_strdup(cc->model_description); 5290 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5291 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5292 5293 if (!desc && alias_of) { 5294 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5295 desc = g_strdup("(alias configured by machine type)"); 5296 } else { 5297 desc = g_strdup_printf("(alias of %s)", alias_of); 5298 } 5299 } 5300 if (!desc && cc->model && cc->model->note) { 5301 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5302 } 5303 if (!desc) { 5304 desc = g_strdup_printf("%s", model_id); 5305 } 5306 5307 if (cc->model && cc->model->cpudef->deprecation_note) { 5308 g_autofree char *olddesc = desc; 5309 desc = g_strdup_printf("%s (deprecated)", olddesc); 5310 } 5311 5312 qemu_printf("x86 %-20s %s\n", name, desc); 5313 } 5314 5315 /* list available CPU models and flags */ 5316 void x86_cpu_list(void) 5317 { 5318 int i, j; 5319 GSList *list; 5320 GList *names = NULL; 5321 5322 qemu_printf("Available CPUs:\n"); 5323 list = get_sorted_cpu_model_list(); 5324 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5325 g_slist_free(list); 5326 5327 names = NULL; 5328 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5329 FeatureWordInfo *fw = &feature_word_info[i]; 5330 for (j = 0; j < 64; j++) { 5331 if (fw->feat_names[j]) { 5332 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5333 } 5334 } 5335 } 5336 5337 names = g_list_sort(names, (GCompareFunc)strcmp); 5338 5339 qemu_printf("\nRecognized CPUID flags:\n"); 5340 listflags(names); 5341 qemu_printf("\n"); 5342 g_list_free(names); 5343 } 5344 5345 #ifndef CONFIG_USER_ONLY 5346 5347 /* Check for missing features that may prevent the CPU class from 5348 * running using the current machine and accelerator. 5349 */ 5350 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5351 strList **list) 5352 { 5353 strList **tail = list; 5354 X86CPU *xc; 5355 Error *err = NULL; 5356 5357 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5358 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5359 return; 5360 } 5361 5362 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5363 5364 x86_cpu_expand_features(xc, &err); 5365 if (err) { 5366 /* Errors at x86_cpu_expand_features should never happen, 5367 * but in case it does, just report the model as not 5368 * runnable at all using the "type" property. 5369 */ 5370 QAPI_LIST_APPEND(tail, g_strdup("type")); 5371 error_free(err); 5372 } 5373 5374 x86_cpu_filter_features(xc, false); 5375 5376 x86_cpu_list_feature_names(xc->filtered_features, tail); 5377 5378 object_unref(OBJECT(xc)); 5379 } 5380 5381 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5382 { 5383 ObjectClass *oc = data; 5384 X86CPUClass *cc = X86_CPU_CLASS(oc); 5385 CpuDefinitionInfoList **cpu_list = user_data; 5386 CpuDefinitionInfo *info; 5387 5388 info = g_malloc0(sizeof(*info)); 5389 info->name = x86_cpu_class_get_model_name(cc); 5390 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5391 info->has_unavailable_features = true; 5392 info->q_typename = g_strdup(object_class_get_name(oc)); 5393 info->migration_safe = cc->migration_safe; 5394 info->has_migration_safe = true; 5395 info->q_static = cc->static_model; 5396 if (cc->model && cc->model->cpudef->deprecation_note) { 5397 info->deprecated = true; 5398 } else { 5399 info->deprecated = false; 5400 } 5401 /* 5402 * Old machine types won't report aliases, so that alias translation 5403 * doesn't break compatibility with previous QEMU versions. 5404 */ 5405 if (default_cpu_version != CPU_VERSION_LEGACY) { 5406 info->alias_of = x86_cpu_class_get_alias_of(cc); 5407 } 5408 5409 QAPI_LIST_PREPEND(*cpu_list, info); 5410 } 5411 5412 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5413 { 5414 CpuDefinitionInfoList *cpu_list = NULL; 5415 GSList *list = get_sorted_cpu_model_list(); 5416 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5417 g_slist_free(list); 5418 return cpu_list; 5419 } 5420 5421 #endif /* !CONFIG_USER_ONLY */ 5422 5423 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5424 bool migratable_only) 5425 { 5426 FeatureWordInfo *wi = &feature_word_info[w]; 5427 uint64_t r = 0; 5428 5429 if (kvm_enabled()) { 5430 switch (wi->type) { 5431 case CPUID_FEATURE_WORD: 5432 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5433 wi->cpuid.ecx, 5434 wi->cpuid.reg); 5435 break; 5436 case MSR_FEATURE_WORD: 5437 r = kvm_arch_get_supported_msr_feature(kvm_state, 5438 wi->msr.index); 5439 break; 5440 } 5441 } else if (hvf_enabled()) { 5442 if (wi->type != CPUID_FEATURE_WORD) { 5443 return 0; 5444 } 5445 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5446 wi->cpuid.ecx, 5447 wi->cpuid.reg); 5448 } else if (tcg_enabled()) { 5449 r = wi->tcg_features; 5450 } else { 5451 return ~0; 5452 } 5453 #ifndef TARGET_X86_64 5454 if (w == FEAT_8000_0001_EDX) { 5455 r &= ~CPUID_EXT2_LM; 5456 } 5457 #endif 5458 if (migratable_only) { 5459 r &= x86_cpu_get_migratable_flags(w); 5460 } 5461 return r; 5462 } 5463 5464 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 5465 uint32_t *eax, uint32_t *ebx, 5466 uint32_t *ecx, uint32_t *edx) 5467 { 5468 if (kvm_enabled()) { 5469 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 5470 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 5471 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 5472 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 5473 } else if (hvf_enabled()) { 5474 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 5475 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 5476 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 5477 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 5478 } else { 5479 *eax = 0; 5480 *ebx = 0; 5481 *ecx = 0; 5482 *edx = 0; 5483 } 5484 } 5485 5486 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 5487 uint32_t *eax, uint32_t *ebx, 5488 uint32_t *ecx, uint32_t *edx) 5489 { 5490 uint32_t level, unused; 5491 5492 /* Only return valid host leaves. */ 5493 switch (func) { 5494 case 2: 5495 case 4: 5496 host_cpuid(0, 0, &level, &unused, &unused, &unused); 5497 break; 5498 case 0x80000005: 5499 case 0x80000006: 5500 case 0x8000001d: 5501 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 5502 break; 5503 default: 5504 return; 5505 } 5506 5507 if (func > level) { 5508 *eax = 0; 5509 *ebx = 0; 5510 *ecx = 0; 5511 *edx = 0; 5512 } else { 5513 host_cpuid(func, index, eax, ebx, ecx, edx); 5514 } 5515 } 5516 5517 /* 5518 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5519 */ 5520 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5521 { 5522 PropValue *pv; 5523 for (pv = props; pv->prop; pv++) { 5524 if (!pv->value) { 5525 continue; 5526 } 5527 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5528 &error_abort); 5529 } 5530 } 5531 5532 /* 5533 * Apply properties for the CPU model version specified in model. 5534 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5535 */ 5536 5537 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5538 { 5539 const X86CPUVersionDefinition *vdef; 5540 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5541 5542 if (version == CPU_VERSION_LEGACY) { 5543 return; 5544 } 5545 5546 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5547 PropValue *p; 5548 5549 for (p = vdef->props; p && p->prop; p++) { 5550 object_property_parse(OBJECT(cpu), p->prop, p->value, 5551 &error_abort); 5552 } 5553 5554 if (vdef->version == version) { 5555 break; 5556 } 5557 } 5558 5559 /* 5560 * If we reached the end of the list, version number was invalid 5561 */ 5562 assert(vdef->version == version); 5563 } 5564 5565 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 5566 X86CPUModel *model) 5567 { 5568 const X86CPUVersionDefinition *vdef; 5569 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5570 const CPUCaches *cache_info = model->cpudef->cache_info; 5571 5572 if (version == CPU_VERSION_LEGACY) { 5573 return cache_info; 5574 } 5575 5576 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5577 if (vdef->cache_info) { 5578 cache_info = vdef->cache_info; 5579 } 5580 5581 if (vdef->version == version) { 5582 break; 5583 } 5584 } 5585 5586 assert(vdef->version == version); 5587 return cache_info; 5588 } 5589 5590 /* 5591 * Load data from X86CPUDefinition into a X86CPU object. 5592 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5593 */ 5594 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5595 { 5596 const X86CPUDefinition *def = model->cpudef; 5597 CPUX86State *env = &cpu->env; 5598 FeatureWord w; 5599 5600 /*NOTE: any property set by this function should be returned by 5601 * x86_cpu_static_props(), so static expansion of 5602 * query-cpu-model-expansion is always complete. 5603 */ 5604 5605 /* CPU models only set _minimum_ values for level/xlevel: */ 5606 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5607 &error_abort); 5608 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5609 &error_abort); 5610 5611 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5612 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5613 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5614 &error_abort); 5615 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5616 &error_abort); 5617 for (w = 0; w < FEATURE_WORDS; w++) { 5618 env->features[w] = def->features[w]; 5619 } 5620 5621 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5622 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 5623 5624 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5625 5626 /* sysenter isn't supported in compatibility mode on AMD, 5627 * syscall isn't supported in compatibility mode on Intel. 5628 * Normally we advertise the actual CPU vendor, but you can 5629 * override this using the 'vendor' property if you want to use 5630 * KVM's sysenter/syscall emulation in compatibility mode and 5631 * when doing cross vendor migration 5632 */ 5633 5634 /* 5635 * vendor property is set here but then overloaded with the 5636 * host cpu vendor for KVM and HVF. 5637 */ 5638 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5639 5640 x86_cpu_apply_version_props(cpu, model); 5641 5642 /* 5643 * Properties in versioned CPU model are not user specified features. 5644 * We can simply clear env->user_features here since it will be filled later 5645 * in x86_cpu_expand_features() based on plus_features and minus_features. 5646 */ 5647 memset(&env->user_features, 0, sizeof(env->user_features)); 5648 } 5649 5650 static gchar *x86_gdb_arch_name(CPUState *cs) 5651 { 5652 #ifdef TARGET_X86_64 5653 return g_strdup("i386:x86-64"); 5654 #else 5655 return g_strdup("i386"); 5656 #endif 5657 } 5658 5659 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5660 { 5661 X86CPUModel *model = data; 5662 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5663 CPUClass *cc = CPU_CLASS(oc); 5664 5665 xcc->model = model; 5666 xcc->migration_safe = true; 5667 cc->deprecation_note = model->cpudef->deprecation_note; 5668 } 5669 5670 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5671 { 5672 g_autofree char *typename = x86_cpu_type_name(name); 5673 TypeInfo ti = { 5674 .name = typename, 5675 .parent = TYPE_X86_CPU, 5676 .class_init = x86_cpu_cpudef_class_init, 5677 .class_data = model, 5678 }; 5679 5680 type_register(&ti); 5681 } 5682 5683 5684 /* 5685 * register builtin_x86_defs; 5686 * "max", "base" and subclasses ("host") are not registered here. 5687 * See x86_cpu_register_types for all model registrations. 5688 */ 5689 static void x86_register_cpudef_types(const X86CPUDefinition *def) 5690 { 5691 X86CPUModel *m; 5692 const X86CPUVersionDefinition *vdef; 5693 5694 /* AMD aliases are handled at runtime based on CPUID vendor, so 5695 * they shouldn't be set on the CPU model table. 5696 */ 5697 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5698 /* catch mistakes instead of silently truncating model_id when too long */ 5699 assert(def->model_id && strlen(def->model_id) <= 48); 5700 5701 /* Unversioned model: */ 5702 m = g_new0(X86CPUModel, 1); 5703 m->cpudef = def; 5704 m->version = CPU_VERSION_AUTO; 5705 m->is_alias = true; 5706 x86_register_cpu_model_type(def->name, m); 5707 5708 /* Versioned models: */ 5709 5710 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5711 X86CPUModel *m = g_new0(X86CPUModel, 1); 5712 g_autofree char *name = 5713 x86_cpu_versioned_model_name(def, vdef->version); 5714 m->cpudef = def; 5715 m->version = vdef->version; 5716 m->note = vdef->note; 5717 x86_register_cpu_model_type(name, m); 5718 5719 if (vdef->alias) { 5720 X86CPUModel *am = g_new0(X86CPUModel, 1); 5721 am->cpudef = def; 5722 am->version = vdef->version; 5723 am->is_alias = true; 5724 x86_register_cpu_model_type(vdef->alias, am); 5725 } 5726 } 5727 5728 } 5729 5730 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 5731 { 5732 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5733 return 57; /* 57 bits virtual */ 5734 } else { 5735 return 48; /* 48 bits virtual */ 5736 } 5737 } 5738 5739 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5740 uint32_t *eax, uint32_t *ebx, 5741 uint32_t *ecx, uint32_t *edx) 5742 { 5743 X86CPU *cpu = env_archcpu(env); 5744 CPUState *cs = env_cpu(env); 5745 uint32_t die_offset; 5746 uint32_t limit; 5747 uint32_t signature[3]; 5748 X86CPUTopoInfo topo_info; 5749 5750 topo_info.dies_per_pkg = env->nr_dies; 5751 topo_info.cores_per_die = cs->nr_cores; 5752 topo_info.threads_per_core = cs->nr_threads; 5753 5754 /* Calculate & apply limits for different index ranges */ 5755 if (index >= 0xC0000000) { 5756 limit = env->cpuid_xlevel2; 5757 } else if (index >= 0x80000000) { 5758 limit = env->cpuid_xlevel; 5759 } else if (index >= 0x40000000) { 5760 limit = 0x40000001; 5761 } else { 5762 limit = env->cpuid_level; 5763 } 5764 5765 if (index > limit) { 5766 /* Intel documentation states that invalid EAX input will 5767 * return the same information as EAX=cpuid_level 5768 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5769 */ 5770 index = env->cpuid_level; 5771 } 5772 5773 switch(index) { 5774 case 0: 5775 *eax = env->cpuid_level; 5776 *ebx = env->cpuid_vendor1; 5777 *edx = env->cpuid_vendor2; 5778 *ecx = env->cpuid_vendor3; 5779 break; 5780 case 1: 5781 *eax = env->cpuid_version; 5782 *ebx = (cpu->apic_id << 24) | 5783 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5784 *ecx = env->features[FEAT_1_ECX]; 5785 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5786 *ecx |= CPUID_EXT_OSXSAVE; 5787 } 5788 *edx = env->features[FEAT_1_EDX]; 5789 if (cs->nr_cores * cs->nr_threads > 1) { 5790 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5791 *edx |= CPUID_HT; 5792 } 5793 if (!cpu->enable_pmu) { 5794 *ecx &= ~CPUID_EXT_PDCM; 5795 } 5796 break; 5797 case 2: 5798 /* cache info: needed for Pentium Pro compatibility */ 5799 if (cpu->cache_info_passthrough) { 5800 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5801 break; 5802 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5803 *eax = *ebx = *ecx = *edx = 0; 5804 break; 5805 } 5806 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5807 *ebx = 0; 5808 if (!cpu->enable_l3_cache) { 5809 *ecx = 0; 5810 } else { 5811 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5812 } 5813 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5814 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5815 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5816 break; 5817 case 4: 5818 /* cache info: needed for Core compatibility */ 5819 if (cpu->cache_info_passthrough) { 5820 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 5821 /* 5822 * QEMU has its own number of cores/logical cpus, 5823 * set 24..14, 31..26 bit to configured values 5824 */ 5825 if (*eax & 31) { 5826 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 5827 int vcpus_per_socket = env->nr_dies * cs->nr_cores * 5828 cs->nr_threads; 5829 if (cs->nr_cores > 1) { 5830 *eax &= ~0xFC000000; 5831 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; 5832 } 5833 if (host_vcpus_per_cache > vcpus_per_socket) { 5834 *eax &= ~0x3FFC000; 5835 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; 5836 } 5837 } 5838 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5839 *eax = *ebx = *ecx = *edx = 0; 5840 } else { 5841 *eax = 0; 5842 switch (count) { 5843 case 0: /* L1 dcache info */ 5844 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5845 1, cs->nr_cores, 5846 eax, ebx, ecx, edx); 5847 break; 5848 case 1: /* L1 icache info */ 5849 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5850 1, cs->nr_cores, 5851 eax, ebx, ecx, edx); 5852 break; 5853 case 2: /* L2 cache info */ 5854 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5855 cs->nr_threads, cs->nr_cores, 5856 eax, ebx, ecx, edx); 5857 break; 5858 case 3: /* L3 cache info */ 5859 die_offset = apicid_die_offset(&topo_info); 5860 if (cpu->enable_l3_cache) { 5861 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5862 (1 << die_offset), cs->nr_cores, 5863 eax, ebx, ecx, edx); 5864 break; 5865 } 5866 /* fall through */ 5867 default: /* end of info */ 5868 *eax = *ebx = *ecx = *edx = 0; 5869 break; 5870 } 5871 } 5872 break; 5873 case 5: 5874 /* MONITOR/MWAIT Leaf */ 5875 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5876 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5877 *ecx = cpu->mwait.ecx; /* flags */ 5878 *edx = cpu->mwait.edx; /* mwait substates */ 5879 break; 5880 case 6: 5881 /* Thermal and Power Leaf */ 5882 *eax = env->features[FEAT_6_EAX]; 5883 *ebx = 0; 5884 *ecx = 0; 5885 *edx = 0; 5886 break; 5887 case 7: 5888 /* Structured Extended Feature Flags Enumeration Leaf */ 5889 if (count == 0) { 5890 /* Maximum ECX value for sub-leaves */ 5891 *eax = env->cpuid_level_func7; 5892 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5893 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5894 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5895 *ecx |= CPUID_7_0_ECX_OSPKE; 5896 } 5897 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5898 5899 /* 5900 * SGX cannot be emulated in software. If hardware does not 5901 * support enabling SGX and/or SGX flexible launch control, 5902 * then we need to update the VM's CPUID values accordingly. 5903 */ 5904 if ((*ebx & CPUID_7_0_EBX_SGX) && 5905 (!kvm_enabled() || 5906 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) & 5907 CPUID_7_0_EBX_SGX))) { 5908 *ebx &= ~CPUID_7_0_EBX_SGX; 5909 } 5910 5911 if ((*ecx & CPUID_7_0_ECX_SGX_LC) && 5912 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() || 5913 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) & 5914 CPUID_7_0_ECX_SGX_LC))) { 5915 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 5916 } 5917 } else if (count == 1) { 5918 *eax = env->features[FEAT_7_1_EAX]; 5919 *edx = env->features[FEAT_7_1_EDX]; 5920 *ebx = 0; 5921 *ecx = 0; 5922 } else { 5923 *eax = 0; 5924 *ebx = 0; 5925 *ecx = 0; 5926 *edx = 0; 5927 } 5928 break; 5929 case 9: 5930 /* Direct Cache Access Information Leaf */ 5931 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5932 *ebx = 0; 5933 *ecx = 0; 5934 *edx = 0; 5935 break; 5936 case 0xA: 5937 /* Architectural Performance Monitoring Leaf */ 5938 if (accel_uses_host_cpuid() && cpu->enable_pmu) { 5939 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 5940 } else { 5941 *eax = 0; 5942 *ebx = 0; 5943 *ecx = 0; 5944 *edx = 0; 5945 } 5946 break; 5947 case 0xB: 5948 /* Extended Topology Enumeration Leaf */ 5949 if (!cpu->enable_cpuid_0xb) { 5950 *eax = *ebx = *ecx = *edx = 0; 5951 break; 5952 } 5953 5954 *ecx = count & 0xff; 5955 *edx = cpu->apic_id; 5956 5957 switch (count) { 5958 case 0: 5959 *eax = apicid_core_offset(&topo_info); 5960 *ebx = cs->nr_threads; 5961 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5962 break; 5963 case 1: 5964 *eax = apicid_pkg_offset(&topo_info); 5965 *ebx = cs->nr_cores * cs->nr_threads; 5966 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5967 break; 5968 default: 5969 *eax = 0; 5970 *ebx = 0; 5971 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5972 } 5973 5974 assert(!(*eax & ~0x1f)); 5975 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5976 break; 5977 case 0x1C: 5978 if (accel_uses_host_cpuid() && cpu->enable_pmu && 5979 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 5980 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 5981 *edx = 0; 5982 } 5983 break; 5984 case 0x1F: 5985 /* V2 Extended Topology Enumeration Leaf */ 5986 if (env->nr_dies < 2) { 5987 *eax = *ebx = *ecx = *edx = 0; 5988 break; 5989 } 5990 5991 *ecx = count & 0xff; 5992 *edx = cpu->apic_id; 5993 switch (count) { 5994 case 0: 5995 *eax = apicid_core_offset(&topo_info); 5996 *ebx = cs->nr_threads; 5997 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5998 break; 5999 case 1: 6000 *eax = apicid_die_offset(&topo_info); 6001 *ebx = cs->nr_cores * cs->nr_threads; 6002 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6003 break; 6004 case 2: 6005 *eax = apicid_pkg_offset(&topo_info); 6006 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 6007 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 6008 break; 6009 default: 6010 *eax = 0; 6011 *ebx = 0; 6012 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6013 } 6014 assert(!(*eax & ~0x1f)); 6015 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6016 break; 6017 case 0xD: { 6018 /* Processor Extended State */ 6019 *eax = 0; 6020 *ebx = 0; 6021 *ecx = 0; 6022 *edx = 0; 6023 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6024 break; 6025 } 6026 6027 if (count == 0) { 6028 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6029 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6030 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6031 /* 6032 * The initial value of xcr0 and ebx == 0, On host without kvm 6033 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6034 * even through guest update xcr0, this will crash some legacy guest 6035 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 6036 */ 6037 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6038 } else if (count == 1) { 6039 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6040 x86_cpu_xsave_xss_components(cpu); 6041 6042 *eax = env->features[FEAT_XSAVE]; 6043 *ebx = xsave_area_size(xstate, true); 6044 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6045 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6046 if (kvm_enabled() && cpu->enable_pmu && 6047 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6048 (*eax & CPUID_XSAVE_XSAVES)) { 6049 *ecx |= XSTATE_ARCH_LBR_MASK; 6050 } else { 6051 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6052 } 6053 } else if (count == 0xf && 6054 accel_uses_host_cpuid() && cpu->enable_pmu && 6055 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6056 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6057 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6058 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6059 6060 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6061 *eax = esa->size; 6062 *ebx = esa->offset; 6063 *ecx = esa->ecx & 6064 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6065 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6066 *eax = esa->size; 6067 *ebx = 0; 6068 *ecx = 1; 6069 } 6070 } 6071 break; 6072 } 6073 case 0x12: 6074 #ifndef CONFIG_USER_ONLY 6075 if (!kvm_enabled() || 6076 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6077 *eax = *ebx = *ecx = *edx = 0; 6078 break; 6079 } 6080 6081 /* 6082 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6083 * the EPC properties, e.g. confidentiality and integrity, from the 6084 * host's first EPC section, i.e. assume there is one EPC section or 6085 * that all EPC sections have the same security properties. 6086 */ 6087 if (count > 1) { 6088 uint64_t epc_addr, epc_size; 6089 6090 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6091 *eax = *ebx = *ecx = *edx = 0; 6092 break; 6093 } 6094 host_cpuid(index, 2, eax, ebx, ecx, edx); 6095 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6096 *ebx = (uint32_t)(epc_addr >> 32); 6097 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6098 *edx = (uint32_t)(epc_size >> 32); 6099 break; 6100 } 6101 6102 /* 6103 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6104 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6105 * supports. Features can be further restricted by userspace, but not 6106 * made more permissive. 6107 */ 6108 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6109 6110 if (count == 0) { 6111 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6112 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6113 } else { 6114 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6115 *ebx &= 0; /* ebx reserve */ 6116 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6117 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6118 6119 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6120 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6121 6122 /* Access to PROVISIONKEY requires additional credentials. */ 6123 if ((*eax & (1U << 4)) && 6124 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6125 *eax &= ~(1U << 4); 6126 } 6127 } 6128 #endif 6129 break; 6130 case 0x14: { 6131 /* Intel Processor Trace Enumeration */ 6132 *eax = 0; 6133 *ebx = 0; 6134 *ecx = 0; 6135 *edx = 0; 6136 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6137 !kvm_enabled()) { 6138 break; 6139 } 6140 6141 if (count == 0) { 6142 *eax = INTEL_PT_MAX_SUBLEAF; 6143 *ebx = INTEL_PT_MINIMAL_EBX; 6144 *ecx = INTEL_PT_MINIMAL_ECX; 6145 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6146 *ecx |= CPUID_14_0_ECX_LIP; 6147 } 6148 } else if (count == 1) { 6149 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6150 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6151 } 6152 break; 6153 } 6154 case 0x1D: { 6155 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6156 *eax = 0; 6157 *ebx = 0; 6158 *ecx = 0; 6159 *edx = 0; 6160 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6161 break; 6162 } 6163 6164 if (count == 0) { 6165 /* Highest numbered palette subleaf */ 6166 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6167 } else if (count == 1) { 6168 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6169 (INTEL_AMX_BYTES_PER_TILE << 16); 6170 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6171 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6172 } 6173 break; 6174 } 6175 case 0x1E: { 6176 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6177 *eax = 0; 6178 *ebx = 0; 6179 *ecx = 0; 6180 *edx = 0; 6181 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6182 break; 6183 } 6184 6185 if (count == 0) { 6186 /* Highest numbered palette subleaf */ 6187 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6188 } 6189 break; 6190 } 6191 case 0x40000000: 6192 /* 6193 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6194 * set here, but we restrict to TCG none the less. 6195 */ 6196 if (tcg_enabled() && cpu->expose_tcg) { 6197 memcpy(signature, "TCGTCGTCGTCG", 12); 6198 *eax = 0x40000001; 6199 *ebx = signature[0]; 6200 *ecx = signature[1]; 6201 *edx = signature[2]; 6202 } else { 6203 *eax = 0; 6204 *ebx = 0; 6205 *ecx = 0; 6206 *edx = 0; 6207 } 6208 break; 6209 case 0x40000001: 6210 *eax = 0; 6211 *ebx = 0; 6212 *ecx = 0; 6213 *edx = 0; 6214 break; 6215 case 0x80000000: 6216 *eax = env->cpuid_xlevel; 6217 *ebx = env->cpuid_vendor1; 6218 *edx = env->cpuid_vendor2; 6219 *ecx = env->cpuid_vendor3; 6220 break; 6221 case 0x80000001: 6222 *eax = env->cpuid_version; 6223 *ebx = 0; 6224 *ecx = env->features[FEAT_8000_0001_ECX]; 6225 *edx = env->features[FEAT_8000_0001_EDX]; 6226 6227 /* The Linux kernel checks for the CMPLegacy bit and 6228 * discards multiple thread information if it is set. 6229 * So don't set it here for Intel to make Linux guests happy. 6230 */ 6231 if (cs->nr_cores * cs->nr_threads > 1) { 6232 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6233 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6234 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6235 *ecx |= 1 << 1; /* CmpLegacy bit */ 6236 } 6237 } 6238 break; 6239 case 0x80000002: 6240 case 0x80000003: 6241 case 0x80000004: 6242 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6243 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6244 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6245 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6246 break; 6247 case 0x80000005: 6248 /* cache info (L1 cache) */ 6249 if (cpu->cache_info_passthrough) { 6250 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6251 break; 6252 } 6253 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6254 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6255 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6256 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6257 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6258 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6259 break; 6260 case 0x80000006: 6261 /* cache info (L2 cache) */ 6262 if (cpu->cache_info_passthrough) { 6263 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6264 break; 6265 } 6266 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6267 (L2_DTLB_2M_ENTRIES << 16) | 6268 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6269 (L2_ITLB_2M_ENTRIES); 6270 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6271 (L2_DTLB_4K_ENTRIES << 16) | 6272 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6273 (L2_ITLB_4K_ENTRIES); 6274 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6275 cpu->enable_l3_cache ? 6276 env->cache_info_amd.l3_cache : NULL, 6277 ecx, edx); 6278 break; 6279 case 0x80000007: 6280 *eax = 0; 6281 *ebx = 0; 6282 *ecx = 0; 6283 *edx = env->features[FEAT_8000_0007_EDX]; 6284 break; 6285 case 0x80000008: 6286 /* virtual & phys address size in low 2 bytes. */ 6287 *eax = cpu->phys_bits; 6288 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6289 /* 64 bit processor */ 6290 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6291 } 6292 *ebx = env->features[FEAT_8000_0008_EBX]; 6293 if (cs->nr_cores * cs->nr_threads > 1) { 6294 /* 6295 * Bits 15:12 is "The number of bits in the initial 6296 * Core::X86::Apic::ApicId[ApicId] value that indicate 6297 * thread ID within a package". 6298 * Bits 7:0 is "The number of threads in the package is NC+1" 6299 */ 6300 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6301 ((cs->nr_cores * cs->nr_threads) - 1); 6302 } else { 6303 *ecx = 0; 6304 } 6305 *edx = 0; 6306 break; 6307 case 0x8000000A: 6308 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6309 *eax = 0x00000001; /* SVM Revision */ 6310 *ebx = 0x00000010; /* nr of ASIDs */ 6311 *ecx = 0; 6312 *edx = env->features[FEAT_SVM]; /* optional features */ 6313 } else { 6314 *eax = 0; 6315 *ebx = 0; 6316 *ecx = 0; 6317 *edx = 0; 6318 } 6319 break; 6320 case 0x8000001D: 6321 *eax = 0; 6322 if (cpu->cache_info_passthrough) { 6323 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6324 break; 6325 } 6326 switch (count) { 6327 case 0: /* L1 dcache info */ 6328 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6329 &topo_info, eax, ebx, ecx, edx); 6330 break; 6331 case 1: /* L1 icache info */ 6332 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6333 &topo_info, eax, ebx, ecx, edx); 6334 break; 6335 case 2: /* L2 cache info */ 6336 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6337 &topo_info, eax, ebx, ecx, edx); 6338 break; 6339 case 3: /* L3 cache info */ 6340 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6341 &topo_info, eax, ebx, ecx, edx); 6342 break; 6343 default: /* end of info */ 6344 *eax = *ebx = *ecx = *edx = 0; 6345 break; 6346 } 6347 break; 6348 case 0x8000001E: 6349 if (cpu->core_id <= 255) { 6350 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6351 } else { 6352 *eax = 0; 6353 *ebx = 0; 6354 *ecx = 0; 6355 *edx = 0; 6356 } 6357 break; 6358 case 0xC0000000: 6359 *eax = env->cpuid_xlevel2; 6360 *ebx = 0; 6361 *ecx = 0; 6362 *edx = 0; 6363 break; 6364 case 0xC0000001: 6365 /* Support for VIA CPU's CPUID instruction */ 6366 *eax = env->cpuid_version; 6367 *ebx = 0; 6368 *ecx = 0; 6369 *edx = env->features[FEAT_C000_0001_EDX]; 6370 break; 6371 case 0xC0000002: 6372 case 0xC0000003: 6373 case 0xC0000004: 6374 /* Reserved for the future, and now filled with zero */ 6375 *eax = 0; 6376 *ebx = 0; 6377 *ecx = 0; 6378 *edx = 0; 6379 break; 6380 case 0x8000001F: 6381 *eax = *ebx = *ecx = *edx = 0; 6382 if (sev_enabled()) { 6383 *eax = 0x2; 6384 *eax |= sev_es_enabled() ? 0x8 : 0; 6385 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6386 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6387 } 6388 break; 6389 case 0x80000021: 6390 *eax = env->features[FEAT_8000_0021_EAX]; 6391 *ebx = *ecx = *edx = 0; 6392 break; 6393 default: 6394 /* reserved values: zero */ 6395 *eax = 0; 6396 *ebx = 0; 6397 *ecx = 0; 6398 *edx = 0; 6399 break; 6400 } 6401 } 6402 6403 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 6404 { 6405 #ifndef CONFIG_USER_ONLY 6406 /* Those default values are defined in Skylake HW */ 6407 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 6408 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 6409 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 6410 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 6411 #endif 6412 } 6413 6414 static void x86_cpu_reset_hold(Object *obj) 6415 { 6416 CPUState *s = CPU(obj); 6417 X86CPU *cpu = X86_CPU(s); 6418 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 6419 CPUX86State *env = &cpu->env; 6420 target_ulong cr4; 6421 uint64_t xcr0; 6422 int i; 6423 6424 if (xcc->parent_phases.hold) { 6425 xcc->parent_phases.hold(obj); 6426 } 6427 6428 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 6429 6430 env->old_exception = -1; 6431 6432 /* init to reset state */ 6433 env->int_ctl = 0; 6434 env->hflags2 |= HF2_GIF_MASK; 6435 env->hflags2 |= HF2_VGIF_MASK; 6436 env->hflags &= ~HF_GUEST_MASK; 6437 6438 cpu_x86_update_cr0(env, 0x60000010); 6439 env->a20_mask = ~0x0; 6440 env->smbase = 0x30000; 6441 env->msr_smi_count = 0; 6442 6443 env->idt.limit = 0xffff; 6444 env->gdt.limit = 0xffff; 6445 env->ldt.limit = 0xffff; 6446 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6447 env->tr.limit = 0xffff; 6448 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6449 6450 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6451 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6452 DESC_R_MASK | DESC_A_MASK); 6453 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6454 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6455 DESC_A_MASK); 6456 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6457 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6458 DESC_A_MASK); 6459 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6460 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6461 DESC_A_MASK); 6462 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6463 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6464 DESC_A_MASK); 6465 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6466 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6467 DESC_A_MASK); 6468 6469 env->eip = 0xfff0; 6470 env->regs[R_EDX] = env->cpuid_version; 6471 6472 env->eflags = 0x2; 6473 6474 /* FPU init */ 6475 for (i = 0; i < 8; i++) { 6476 env->fptags[i] = 1; 6477 } 6478 cpu_set_fpuc(env, 0x37f); 6479 6480 env->mxcsr = 0x1f80; 6481 /* All units are in INIT state. */ 6482 env->xstate_bv = 0; 6483 6484 env->pat = 0x0007040600070406ULL; 6485 6486 if (kvm_enabled()) { 6487 /* 6488 * KVM handles TSC = 0 specially and thinks we are hot-plugging 6489 * a new CPU, use 1 instead to force a reset. 6490 */ 6491 if (env->tsc != 0) { 6492 env->tsc = 1; 6493 } 6494 } else { 6495 env->tsc = 0; 6496 } 6497 6498 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6499 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6500 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6501 } 6502 6503 memset(env->dr, 0, sizeof(env->dr)); 6504 env->dr[6] = DR6_FIXED_1; 6505 env->dr[7] = DR7_FIXED_1; 6506 cpu_breakpoint_remove_all(s, BP_CPU); 6507 cpu_watchpoint_remove_all(s, BP_CPU); 6508 6509 cr4 = 0; 6510 xcr0 = XSTATE_FP_MASK; 6511 6512 #ifdef CONFIG_USER_ONLY 6513 /* Enable all the features for user-mode. */ 6514 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6515 xcr0 |= XSTATE_SSE_MASK; 6516 } 6517 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6518 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6519 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 6520 continue; 6521 } 6522 if (env->features[esa->feature] & esa->bits) { 6523 xcr0 |= 1ull << i; 6524 } 6525 } 6526 6527 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6528 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6529 } 6530 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6531 cr4 |= CR4_FSGSBASE_MASK; 6532 } 6533 #endif 6534 6535 env->xcr0 = xcr0; 6536 cpu_x86_update_cr4(env, cr4); 6537 6538 /* 6539 * SDM 11.11.5 requires: 6540 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6541 * - IA32_MTRR_PHYSMASKn.V = 0 6542 * All other bits are undefined. For simplification, zero it all. 6543 */ 6544 env->mtrr_deftype = 0; 6545 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6546 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6547 6548 env->interrupt_injected = -1; 6549 env->exception_nr = -1; 6550 env->exception_pending = 0; 6551 env->exception_injected = 0; 6552 env->exception_has_payload = false; 6553 env->exception_payload = 0; 6554 env->nmi_injected = false; 6555 env->triple_fault_pending = false; 6556 #if !defined(CONFIG_USER_ONLY) 6557 /* We hard-wire the BSP to the first CPU. */ 6558 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6559 6560 s->halted = !cpu_is_bsp(cpu); 6561 6562 if (kvm_enabled()) { 6563 kvm_arch_reset_vcpu(cpu); 6564 } 6565 6566 x86_cpu_set_sgxlepubkeyhash(env); 6567 6568 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 6569 6570 #endif 6571 } 6572 6573 void x86_cpu_after_reset(X86CPU *cpu) 6574 { 6575 #ifndef CONFIG_USER_ONLY 6576 if (kvm_enabled()) { 6577 kvm_arch_after_reset_vcpu(cpu); 6578 } 6579 6580 if (cpu->apic_state) { 6581 device_cold_reset(cpu->apic_state); 6582 } 6583 #endif 6584 } 6585 6586 static void mce_init(X86CPU *cpu) 6587 { 6588 CPUX86State *cenv = &cpu->env; 6589 unsigned int bank; 6590 6591 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6592 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6593 (CPUID_MCE | CPUID_MCA)) { 6594 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6595 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6596 cenv->mcg_ctl = ~(uint64_t)0; 6597 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6598 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6599 } 6600 } 6601 } 6602 6603 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6604 { 6605 if (*min < value) { 6606 *min = value; 6607 } 6608 } 6609 6610 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6611 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6612 { 6613 CPUX86State *env = &cpu->env; 6614 FeatureWordInfo *fi = &feature_word_info[w]; 6615 uint32_t eax = fi->cpuid.eax; 6616 uint32_t region = eax & 0xF0000000; 6617 6618 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6619 if (!env->features[w]) { 6620 return; 6621 } 6622 6623 switch (region) { 6624 case 0x00000000: 6625 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6626 break; 6627 case 0x80000000: 6628 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6629 break; 6630 case 0xC0000000: 6631 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6632 break; 6633 } 6634 6635 if (eax == 7) { 6636 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6637 fi->cpuid.ecx); 6638 } 6639 } 6640 6641 /* Calculate XSAVE components based on the configured CPU feature flags */ 6642 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6643 { 6644 CPUX86State *env = &cpu->env; 6645 int i; 6646 uint64_t mask; 6647 static bool request_perm; 6648 6649 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6650 env->features[FEAT_XSAVE_XCR0_LO] = 0; 6651 env->features[FEAT_XSAVE_XCR0_HI] = 0; 6652 return; 6653 } 6654 6655 mask = 0; 6656 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6657 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6658 if (env->features[esa->feature] & esa->bits) { 6659 mask |= (1ULL << i); 6660 } 6661 } 6662 6663 /* Only request permission for first vcpu */ 6664 if (kvm_enabled() && !request_perm) { 6665 kvm_request_xsave_components(cpu, mask); 6666 request_perm = true; 6667 } 6668 6669 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 6670 env->features[FEAT_XSAVE_XCR0_HI] = mask >> 32; 6671 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 6672 env->features[FEAT_XSAVE_XSS_HI] = mask >> 32; 6673 } 6674 6675 /***** Steps involved on loading and filtering CPUID data 6676 * 6677 * When initializing and realizing a CPU object, the steps 6678 * involved in setting up CPUID data are: 6679 * 6680 * 1) Loading CPU model definition (X86CPUDefinition). This is 6681 * implemented by x86_cpu_load_model() and should be completely 6682 * transparent, as it is done automatically by instance_init. 6683 * No code should need to look at X86CPUDefinition structs 6684 * outside instance_init. 6685 * 6686 * 2) CPU expansion. This is done by realize before CPUID 6687 * filtering, and will make sure host/accelerator data is 6688 * loaded for CPU models that depend on host capabilities 6689 * (e.g. "host"). Done by x86_cpu_expand_features(). 6690 * 6691 * 3) CPUID filtering. This initializes extra data related to 6692 * CPUID, and checks if the host supports all capabilities 6693 * required by the CPU. Runnability of a CPU model is 6694 * determined at this step. Done by x86_cpu_filter_features(). 6695 * 6696 * Some operations don't require all steps to be performed. 6697 * More precisely: 6698 * 6699 * - CPU instance creation (instance_init) will run only CPU 6700 * model loading. CPU expansion can't run at instance_init-time 6701 * because host/accelerator data may be not available yet. 6702 * - CPU realization will perform both CPU model expansion and CPUID 6703 * filtering, and return an error in case one of them fails. 6704 * - query-cpu-definitions needs to run all 3 steps. It needs 6705 * to run CPUID filtering, as the 'unavailable-features' 6706 * field is set based on the filtering results. 6707 * - The query-cpu-model-expansion QMP command only needs to run 6708 * CPU model loading and CPU expansion. It should not filter 6709 * any CPUID data based on host capabilities. 6710 */ 6711 6712 /* Expand CPU configuration data, based on configured features 6713 * and host/accelerator capabilities when appropriate. 6714 */ 6715 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6716 { 6717 CPUX86State *env = &cpu->env; 6718 FeatureWord w; 6719 int i; 6720 GList *l; 6721 6722 for (l = plus_features; l; l = l->next) { 6723 const char *prop = l->data; 6724 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6725 return; 6726 } 6727 } 6728 6729 for (l = minus_features; l; l = l->next) { 6730 const char *prop = l->data; 6731 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6732 return; 6733 } 6734 } 6735 6736 /*TODO: Now cpu->max_features doesn't overwrite features 6737 * set using QOM properties, and we can convert 6738 * plus_features & minus_features to global properties 6739 * inside x86_cpu_parse_featurestr() too. 6740 */ 6741 if (cpu->max_features) { 6742 for (w = 0; w < FEATURE_WORDS; w++) { 6743 /* Override only features that weren't set explicitly 6744 * by the user. 6745 */ 6746 env->features[w] |= 6747 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6748 ~env->user_features[w] & 6749 ~feature_word_info[w].no_autoenable_flags; 6750 } 6751 } 6752 6753 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6754 FeatureDep *d = &feature_dependencies[i]; 6755 if (!(env->features[d->from.index] & d->from.mask)) { 6756 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6757 6758 /* Not an error unless the dependent feature was added explicitly. */ 6759 mark_unavailable_features(cpu, d->to.index, 6760 unavailable_features & env->user_features[d->to.index], 6761 "This feature depends on other features that were not requested"); 6762 6763 env->features[d->to.index] &= ~unavailable_features; 6764 } 6765 } 6766 6767 if (!kvm_enabled() || !cpu->expose_kvm) { 6768 env->features[FEAT_KVM] = 0; 6769 } 6770 6771 x86_cpu_enable_xsave_components(cpu); 6772 6773 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6774 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6775 if (cpu->full_cpuid_auto_level) { 6776 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6777 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6778 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6779 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6780 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6781 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6782 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6783 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6784 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6785 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6786 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6787 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6788 6789 /* Intel Processor Trace requires CPUID[0x14] */ 6790 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6791 if (cpu->intel_pt_auto_level) { 6792 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6793 } else if (cpu->env.cpuid_min_level < 0x14) { 6794 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6795 CPUID_7_0_EBX_INTEL_PT, 6796 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 6797 } 6798 } 6799 6800 /* 6801 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 6802 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 6803 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 6804 * cpu->vendor_cpuid_only has been unset for compatibility with older 6805 * machine types. 6806 */ 6807 if ((env->nr_dies > 1) && 6808 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 6809 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6810 } 6811 6812 /* SVM requires CPUID[0x8000000A] */ 6813 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6814 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6815 } 6816 6817 /* SEV requires CPUID[0x8000001F] */ 6818 if (sev_enabled()) { 6819 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6820 } 6821 6822 if (env->features[FEAT_8000_0021_EAX]) { 6823 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 6824 } 6825 6826 /* SGX requires CPUID[0x12] for EPC enumeration */ 6827 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 6828 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 6829 } 6830 } 6831 6832 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6833 if (env->cpuid_level_func7 == UINT32_MAX) { 6834 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6835 } 6836 if (env->cpuid_level == UINT32_MAX) { 6837 env->cpuid_level = env->cpuid_min_level; 6838 } 6839 if (env->cpuid_xlevel == UINT32_MAX) { 6840 env->cpuid_xlevel = env->cpuid_min_xlevel; 6841 } 6842 if (env->cpuid_xlevel2 == UINT32_MAX) { 6843 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6844 } 6845 6846 if (kvm_enabled()) { 6847 kvm_hyperv_expand_features(cpu, errp); 6848 } 6849 } 6850 6851 /* 6852 * Finishes initialization of CPUID data, filters CPU feature 6853 * words based on host availability of each feature. 6854 * 6855 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6856 */ 6857 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6858 { 6859 CPUX86State *env = &cpu->env; 6860 FeatureWord w; 6861 const char *prefix = NULL; 6862 6863 if (verbose) { 6864 prefix = accel_uses_host_cpuid() 6865 ? "host doesn't support requested feature" 6866 : "TCG doesn't support requested feature"; 6867 } 6868 6869 for (w = 0; w < FEATURE_WORDS; w++) { 6870 uint64_t host_feat = 6871 x86_cpu_get_supported_feature_word(w, false); 6872 uint64_t requested_features = env->features[w]; 6873 uint64_t unavailable_features = requested_features & ~host_feat; 6874 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6875 } 6876 6877 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6878 kvm_enabled()) { 6879 KVMState *s = CPU(cpu)->kvm_state; 6880 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6881 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6882 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6883 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6884 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6885 6886 if (!eax_0 || 6887 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6888 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6889 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6890 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6891 INTEL_PT_ADDR_RANGES_NUM) || 6892 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6893 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6894 ((ecx_0 & CPUID_14_0_ECX_LIP) != 6895 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 6896 /* 6897 * Processor Trace capabilities aren't configurable, so if the 6898 * host can't emulate the capabilities we report on 6899 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6900 */ 6901 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6902 } 6903 } 6904 } 6905 6906 static void x86_cpu_hyperv_realize(X86CPU *cpu) 6907 { 6908 size_t len; 6909 6910 /* Hyper-V vendor id */ 6911 if (!cpu->hyperv_vendor) { 6912 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 6913 &error_abort); 6914 } 6915 len = strlen(cpu->hyperv_vendor); 6916 if (len > 12) { 6917 warn_report("hv-vendor-id truncated to 12 characters"); 6918 len = 12; 6919 } 6920 memset(cpu->hyperv_vendor_id, 0, 12); 6921 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 6922 6923 /* 'Hv#1' interface identification*/ 6924 cpu->hyperv_interface_id[0] = 0x31237648; 6925 cpu->hyperv_interface_id[1] = 0; 6926 cpu->hyperv_interface_id[2] = 0; 6927 cpu->hyperv_interface_id[3] = 0; 6928 6929 /* Hypervisor implementation limits */ 6930 cpu->hyperv_limits[0] = 64; 6931 cpu->hyperv_limits[1] = 0; 6932 cpu->hyperv_limits[2] = 0; 6933 } 6934 6935 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6936 { 6937 CPUState *cs = CPU(dev); 6938 X86CPU *cpu = X86_CPU(dev); 6939 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6940 CPUX86State *env = &cpu->env; 6941 Error *local_err = NULL; 6942 static bool ht_warned; 6943 unsigned requested_lbr_fmt; 6944 6945 /* Use pc-relative instructions in system-mode */ 6946 #ifndef CONFIG_USER_ONLY 6947 cs->tcg_cflags |= CF_PCREL; 6948 #endif 6949 6950 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6951 error_setg(errp, "apic-id property was not initialized properly"); 6952 return; 6953 } 6954 6955 /* 6956 * Process Hyper-V enlightenments. 6957 * Note: this currently has to happen before the expansion of CPU features. 6958 */ 6959 x86_cpu_hyperv_realize(cpu); 6960 6961 x86_cpu_expand_features(cpu, &local_err); 6962 if (local_err) { 6963 goto out; 6964 } 6965 6966 /* 6967 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 6968 * with user-provided setting. 6969 */ 6970 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 6971 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 6972 error_setg(errp, "invalid lbr-fmt"); 6973 return; 6974 } 6975 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 6976 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 6977 } 6978 6979 /* 6980 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 6981 * 3)vPMU LBR format matches that of host setting. 6982 */ 6983 requested_lbr_fmt = 6984 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 6985 if (requested_lbr_fmt && kvm_enabled()) { 6986 uint64_t host_perf_cap = 6987 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 6988 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 6989 6990 if (!cpu->enable_pmu) { 6991 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 6992 return; 6993 } 6994 if (requested_lbr_fmt != host_lbr_fmt) { 6995 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 6996 "the host value (0x%x).", 6997 requested_lbr_fmt, host_lbr_fmt); 6998 return; 6999 } 7000 } 7001 7002 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7003 7004 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7005 error_setg(&local_err, 7006 accel_uses_host_cpuid() ? 7007 "Host doesn't support requested features" : 7008 "TCG doesn't support requested features"); 7009 goto out; 7010 } 7011 7012 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7013 * CPUID[1].EDX. 7014 */ 7015 if (IS_AMD_CPU(env)) { 7016 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7017 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7018 & CPUID_EXT2_AMD_ALIASES); 7019 } 7020 7021 x86_cpu_set_sgxlepubkeyhash(env); 7022 7023 /* 7024 * note: the call to the framework needs to happen after feature expansion, 7025 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7026 * These may be set by the accel-specific code, 7027 * and the results are subsequently checked / assumed in this function. 7028 */ 7029 cpu_exec_realizefn(cs, &local_err); 7030 if (local_err != NULL) { 7031 error_propagate(errp, local_err); 7032 return; 7033 } 7034 7035 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7036 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7037 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7038 goto out; 7039 } 7040 7041 if (cpu->ucode_rev == 0) { 7042 /* 7043 * The default is the same as KVM's. Note that this check 7044 * needs to happen after the evenual setting of ucode_rev in 7045 * accel-specific code in cpu_exec_realizefn. 7046 */ 7047 if (IS_AMD_CPU(env)) { 7048 cpu->ucode_rev = 0x01000065; 7049 } else { 7050 cpu->ucode_rev = 0x100000000ULL; 7051 } 7052 } 7053 7054 /* 7055 * mwait extended info: needed for Core compatibility 7056 * We always wake on interrupt even if host does not have the capability. 7057 * 7058 * requires the accel-specific code in cpu_exec_realizefn to 7059 * have already acquired the CPUID data into cpu->mwait. 7060 */ 7061 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7062 7063 /* For 64bit systems think about the number of physical bits to present. 7064 * ideally this should be the same as the host; anything other than matching 7065 * the host can cause incorrect guest behaviour. 7066 * QEMU used to pick the magic value of 40 bits that corresponds to 7067 * consumer AMD devices but nothing else. 7068 * 7069 * Note that this code assumes features expansion has already been done 7070 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7071 * phys_bits adjustments to match the host have been already done in 7072 * accel-specific code in cpu_exec_realizefn. 7073 */ 7074 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7075 if (cpu->phys_bits && 7076 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7077 cpu->phys_bits < 32)) { 7078 error_setg(errp, "phys-bits should be between 32 and %u " 7079 " (but is %u)", 7080 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7081 return; 7082 } 7083 /* 7084 * 0 means it was not explicitly set by the user (or by machine 7085 * compat_props or by the host code in host-cpu.c). 7086 * In this case, the default is the value used by TCG (40). 7087 */ 7088 if (cpu->phys_bits == 0) { 7089 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7090 } 7091 } else { 7092 /* For 32 bit systems don't use the user set value, but keep 7093 * phys_bits consistent with what we tell the guest. 7094 */ 7095 if (cpu->phys_bits != 0) { 7096 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7097 return; 7098 } 7099 7100 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 7101 cpu->phys_bits = 36; 7102 } else { 7103 cpu->phys_bits = 32; 7104 } 7105 } 7106 7107 /* Cache information initialization */ 7108 if (!cpu->legacy_cache) { 7109 const CPUCaches *cache_info = 7110 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7111 7112 if (!xcc->model || !cache_info) { 7113 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7114 error_setg(errp, 7115 "CPU model '%s' doesn't support legacy-cache=off", name); 7116 return; 7117 } 7118 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7119 *cache_info; 7120 } else { 7121 /* Build legacy cache information */ 7122 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7123 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7124 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7125 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7126 7127 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7128 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7129 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7130 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7131 7132 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7133 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7134 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7135 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7136 } 7137 7138 #ifndef CONFIG_USER_ONLY 7139 MachineState *ms = MACHINE(qdev_get_machine()); 7140 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7141 7142 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7143 x86_cpu_apic_create(cpu, &local_err); 7144 if (local_err != NULL) { 7145 goto out; 7146 } 7147 } 7148 #endif 7149 7150 mce_init(cpu); 7151 7152 qemu_init_vcpu(cs); 7153 7154 /* 7155 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7156 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7157 * based on inputs (sockets,cores,threads), it is still better to give 7158 * users a warning. 7159 * 7160 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7161 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7162 */ 7163 if (IS_AMD_CPU(env) && 7164 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7165 cs->nr_threads > 1 && !ht_warned) { 7166 warn_report("This family of AMD CPU doesn't support " 7167 "hyperthreading(%d)", 7168 cs->nr_threads); 7169 error_printf("Please configure -smp options properly" 7170 " or try enabling topoext feature.\n"); 7171 ht_warned = true; 7172 } 7173 7174 #ifndef CONFIG_USER_ONLY 7175 x86_cpu_apic_realize(cpu, &local_err); 7176 if (local_err != NULL) { 7177 goto out; 7178 } 7179 #endif /* !CONFIG_USER_ONLY */ 7180 cpu_reset(cs); 7181 7182 xcc->parent_realize(dev, &local_err); 7183 7184 out: 7185 if (local_err != NULL) { 7186 error_propagate(errp, local_err); 7187 return; 7188 } 7189 } 7190 7191 static void x86_cpu_unrealizefn(DeviceState *dev) 7192 { 7193 X86CPU *cpu = X86_CPU(dev); 7194 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7195 7196 #ifndef CONFIG_USER_ONLY 7197 cpu_remove_sync(CPU(dev)); 7198 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7199 #endif 7200 7201 if (cpu->apic_state) { 7202 object_unparent(OBJECT(cpu->apic_state)); 7203 cpu->apic_state = NULL; 7204 } 7205 7206 xcc->parent_unrealize(dev); 7207 } 7208 7209 typedef struct BitProperty { 7210 FeatureWord w; 7211 uint64_t mask; 7212 } BitProperty; 7213 7214 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7215 void *opaque, Error **errp) 7216 { 7217 X86CPU *cpu = X86_CPU(obj); 7218 BitProperty *fp = opaque; 7219 uint64_t f = cpu->env.features[fp->w]; 7220 bool value = (f & fp->mask) == fp->mask; 7221 visit_type_bool(v, name, &value, errp); 7222 } 7223 7224 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7225 void *opaque, Error **errp) 7226 { 7227 DeviceState *dev = DEVICE(obj); 7228 X86CPU *cpu = X86_CPU(obj); 7229 BitProperty *fp = opaque; 7230 bool value; 7231 7232 if (dev->realized) { 7233 qdev_prop_set_after_realize(dev, name, errp); 7234 return; 7235 } 7236 7237 if (!visit_type_bool(v, name, &value, errp)) { 7238 return; 7239 } 7240 7241 if (value) { 7242 cpu->env.features[fp->w] |= fp->mask; 7243 } else { 7244 cpu->env.features[fp->w] &= ~fp->mask; 7245 } 7246 cpu->env.user_features[fp->w] |= fp->mask; 7247 } 7248 7249 /* Register a boolean property to get/set a single bit in a uint32_t field. 7250 * 7251 * The same property name can be registered multiple times to make it affect 7252 * multiple bits in the same FeatureWord. In that case, the getter will return 7253 * true only if all bits are set. 7254 */ 7255 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7256 const char *prop_name, 7257 FeatureWord w, 7258 int bitnr) 7259 { 7260 ObjectClass *oc = OBJECT_CLASS(xcc); 7261 BitProperty *fp; 7262 ObjectProperty *op; 7263 uint64_t mask = (1ULL << bitnr); 7264 7265 op = object_class_property_find(oc, prop_name); 7266 if (op) { 7267 fp = op->opaque; 7268 assert(fp->w == w); 7269 fp->mask |= mask; 7270 } else { 7271 fp = g_new0(BitProperty, 1); 7272 fp->w = w; 7273 fp->mask = mask; 7274 object_class_property_add(oc, prop_name, "bool", 7275 x86_cpu_get_bit_prop, 7276 x86_cpu_set_bit_prop, 7277 NULL, fp); 7278 } 7279 } 7280 7281 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7282 FeatureWord w, 7283 int bitnr) 7284 { 7285 FeatureWordInfo *fi = &feature_word_info[w]; 7286 const char *name = fi->feat_names[bitnr]; 7287 7288 if (!name) { 7289 return; 7290 } 7291 7292 /* Property names should use "-" instead of "_". 7293 * Old names containing underscores are registered as aliases 7294 * using object_property_add_alias() 7295 */ 7296 assert(!strchr(name, '_')); 7297 /* aliases don't use "|" delimiters anymore, they are registered 7298 * manually using object_property_add_alias() */ 7299 assert(!strchr(name, '|')); 7300 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7301 } 7302 7303 static void x86_cpu_post_initfn(Object *obj) 7304 { 7305 accel_cpu_instance_init(CPU(obj)); 7306 } 7307 7308 static void x86_cpu_initfn(Object *obj) 7309 { 7310 X86CPU *cpu = X86_CPU(obj); 7311 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7312 CPUX86State *env = &cpu->env; 7313 7314 env->nr_dies = 1; 7315 cpu_set_cpustate_pointers(cpu); 7316 7317 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7318 x86_cpu_get_feature_words, 7319 NULL, NULL, (void *)env->features); 7320 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 7321 x86_cpu_get_feature_words, 7322 NULL, NULL, (void *)cpu->filtered_features); 7323 7324 object_property_add_alias(obj, "sse3", obj, "pni"); 7325 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 7326 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 7327 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 7328 object_property_add_alias(obj, "xd", obj, "nx"); 7329 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 7330 object_property_add_alias(obj, "i64", obj, "lm"); 7331 7332 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7333 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7334 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7335 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7336 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7337 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7338 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7339 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7340 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7341 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7342 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7343 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7344 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7345 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7346 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7347 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7348 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7349 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7350 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7351 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 7352 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 7353 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 7354 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 7355 7356 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 7357 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 7358 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 7359 7360 if (xcc->model) { 7361 x86_cpu_load_model(cpu, xcc->model); 7362 } 7363 } 7364 7365 static int64_t x86_cpu_get_arch_id(CPUState *cs) 7366 { 7367 X86CPU *cpu = X86_CPU(cs); 7368 7369 return cpu->apic_id; 7370 } 7371 7372 #if !defined(CONFIG_USER_ONLY) 7373 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7374 { 7375 X86CPU *cpu = X86_CPU(cs); 7376 7377 return cpu->env.cr[0] & CR0_PG_MASK; 7378 } 7379 #endif /* !CONFIG_USER_ONLY */ 7380 7381 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7382 { 7383 X86CPU *cpu = X86_CPU(cs); 7384 7385 cpu->env.eip = value; 7386 } 7387 7388 static vaddr x86_cpu_get_pc(CPUState *cs) 7389 { 7390 X86CPU *cpu = X86_CPU(cs); 7391 7392 /* Match cpu_get_tb_cpu_state. */ 7393 return cpu->env.eip + cpu->env.segs[R_CS].base; 7394 } 7395 7396 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7397 { 7398 X86CPU *cpu = X86_CPU(cs); 7399 CPUX86State *env = &cpu->env; 7400 7401 #if !defined(CONFIG_USER_ONLY) 7402 if (interrupt_request & CPU_INTERRUPT_POLL) { 7403 return CPU_INTERRUPT_POLL; 7404 } 7405 #endif 7406 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7407 return CPU_INTERRUPT_SIPI; 7408 } 7409 7410 if (env->hflags2 & HF2_GIF_MASK) { 7411 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7412 !(env->hflags & HF_SMM_MASK)) { 7413 return CPU_INTERRUPT_SMI; 7414 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7415 !(env->hflags2 & HF2_NMI_MASK)) { 7416 return CPU_INTERRUPT_NMI; 7417 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7418 return CPU_INTERRUPT_MCE; 7419 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7420 (((env->hflags2 & HF2_VINTR_MASK) && 7421 (env->hflags2 & HF2_HIF_MASK)) || 7422 (!(env->hflags2 & HF2_VINTR_MASK) && 7423 (env->eflags & IF_MASK && 7424 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7425 return CPU_INTERRUPT_HARD; 7426 #if !defined(CONFIG_USER_ONLY) 7427 } else if (env->hflags2 & HF2_VGIF_MASK) { 7428 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 7429 (env->eflags & IF_MASK) && 7430 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7431 return CPU_INTERRUPT_VIRQ; 7432 } 7433 #endif 7434 } 7435 } 7436 7437 return 0; 7438 } 7439 7440 static bool x86_cpu_has_work(CPUState *cs) 7441 { 7442 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7443 } 7444 7445 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7446 { 7447 X86CPU *cpu = X86_CPU(cs); 7448 CPUX86State *env = &cpu->env; 7449 7450 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7451 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7452 : bfd_mach_i386_i8086); 7453 7454 info->cap_arch = CS_ARCH_X86; 7455 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7456 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7457 : CS_MODE_16); 7458 info->cap_insn_unit = 1; 7459 info->cap_insn_split = 8; 7460 } 7461 7462 void x86_update_hflags(CPUX86State *env) 7463 { 7464 uint32_t hflags; 7465 #define HFLAG_COPY_MASK \ 7466 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7467 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7468 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7469 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7470 7471 hflags = env->hflags & HFLAG_COPY_MASK; 7472 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7473 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7474 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7475 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7476 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7477 7478 if (env->cr[4] & CR4_OSFXSR_MASK) { 7479 hflags |= HF_OSFXSR_MASK; 7480 } 7481 7482 if (env->efer & MSR_EFER_LMA) { 7483 hflags |= HF_LMA_MASK; 7484 } 7485 7486 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7487 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7488 } else { 7489 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7490 (DESC_B_SHIFT - HF_CS32_SHIFT); 7491 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7492 (DESC_B_SHIFT - HF_SS32_SHIFT); 7493 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7494 !(hflags & HF_CS32_MASK)) { 7495 hflags |= HF_ADDSEG_MASK; 7496 } else { 7497 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7498 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7499 } 7500 } 7501 env->hflags = hflags; 7502 } 7503 7504 static Property x86_cpu_properties[] = { 7505 #ifdef CONFIG_USER_ONLY 7506 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7507 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7508 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7509 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7510 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7511 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7512 #else 7513 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7514 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7515 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7516 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7517 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7518 #endif 7519 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7520 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7521 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 7522 7523 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7524 HYPERV_SPINLOCK_NEVER_NOTIFY), 7525 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7526 HYPERV_FEAT_RELAXED, 0), 7527 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7528 HYPERV_FEAT_VAPIC, 0), 7529 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7530 HYPERV_FEAT_TIME, 0), 7531 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7532 HYPERV_FEAT_CRASH, 0), 7533 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7534 HYPERV_FEAT_RESET, 0), 7535 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7536 HYPERV_FEAT_VPINDEX, 0), 7537 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7538 HYPERV_FEAT_RUNTIME, 0), 7539 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7540 HYPERV_FEAT_SYNIC, 0), 7541 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7542 HYPERV_FEAT_STIMER, 0), 7543 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7544 HYPERV_FEAT_FREQUENCIES, 0), 7545 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7546 HYPERV_FEAT_REENLIGHTENMENT, 0), 7547 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7548 HYPERV_FEAT_TLBFLUSH, 0), 7549 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7550 HYPERV_FEAT_EVMCS, 0), 7551 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7552 HYPERV_FEAT_IPI, 0), 7553 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7554 HYPERV_FEAT_STIMER_DIRECT, 0), 7555 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 7556 HYPERV_FEAT_AVIC, 0), 7557 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 7558 HYPERV_FEAT_MSR_BITMAP, 0), 7559 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 7560 HYPERV_FEAT_XMM_INPUT, 0), 7561 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 7562 HYPERV_FEAT_TLBFLUSH_EXT, 0), 7563 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 7564 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 7565 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7566 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7567 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 7568 HYPERV_FEAT_SYNDBG, 0), 7569 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7570 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 7571 7572 /* WS2008R2 identify by default */ 7573 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 7574 0x3839), 7575 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 7576 0x000A), 7577 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 7578 0x0000), 7579 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 7580 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 7581 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 7582 7583 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7584 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7585 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7586 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7587 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7588 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7589 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7590 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7591 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7592 UINT32_MAX), 7593 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7594 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7595 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7596 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7597 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7598 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7599 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7600 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7601 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 7602 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7603 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 7604 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7605 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7606 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7607 false), 7608 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 7609 false), 7610 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7611 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7612 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7613 true), 7614 /* 7615 * lecacy_cache defaults to true unless the CPU model provides its 7616 * own cache information (see x86_cpu_load_def()). 7617 */ 7618 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7619 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 7620 7621 /* 7622 * From "Requirements for Implementing the Microsoft 7623 * Hypervisor Interface": 7624 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7625 * 7626 * "Starting with Windows Server 2012 and Windows 8, if 7627 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7628 * the hypervisor imposes no specific limit to the number of VPs. 7629 * In this case, Windows Server 2012 guest VMs may use more than 7630 * 64 VPs, up to the maximum supported number of processors applicable 7631 * to the specific Windows version being used." 7632 */ 7633 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7634 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7635 false), 7636 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7637 true), 7638 DEFINE_PROP_END_OF_LIST() 7639 }; 7640 7641 #ifndef CONFIG_USER_ONLY 7642 #include "hw/core/sysemu-cpu-ops.h" 7643 7644 static const struct SysemuCPUOps i386_sysemu_ops = { 7645 .get_memory_mapping = x86_cpu_get_memory_mapping, 7646 .get_paging_enabled = x86_cpu_get_paging_enabled, 7647 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 7648 .asidx_from_attrs = x86_asidx_from_attrs, 7649 .get_crash_info = x86_cpu_get_crash_info, 7650 .write_elf32_note = x86_cpu_write_elf32_note, 7651 .write_elf64_note = x86_cpu_write_elf64_note, 7652 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 7653 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 7654 .legacy_vmsd = &vmstate_x86_cpu, 7655 }; 7656 #endif 7657 7658 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7659 { 7660 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7661 CPUClass *cc = CPU_CLASS(oc); 7662 DeviceClass *dc = DEVICE_CLASS(oc); 7663 ResettableClass *rc = RESETTABLE_CLASS(oc); 7664 FeatureWord w; 7665 7666 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7667 &xcc->parent_realize); 7668 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7669 &xcc->parent_unrealize); 7670 device_class_set_props(dc, x86_cpu_properties); 7671 7672 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 7673 &xcc->parent_phases); 7674 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7675 7676 cc->class_by_name = x86_cpu_class_by_name; 7677 cc->parse_features = x86_cpu_parse_featurestr; 7678 cc->has_work = x86_cpu_has_work; 7679 cc->dump_state = x86_cpu_dump_state; 7680 cc->set_pc = x86_cpu_set_pc; 7681 cc->get_pc = x86_cpu_get_pc; 7682 cc->gdb_read_register = x86_cpu_gdb_read_register; 7683 cc->gdb_write_register = x86_cpu_gdb_write_register; 7684 cc->get_arch_id = x86_cpu_get_arch_id; 7685 7686 #ifndef CONFIG_USER_ONLY 7687 cc->sysemu_ops = &i386_sysemu_ops; 7688 #endif /* !CONFIG_USER_ONLY */ 7689 7690 cc->gdb_arch_name = x86_gdb_arch_name; 7691 #ifdef TARGET_X86_64 7692 cc->gdb_core_xml_file = "i386-64bit.xml"; 7693 cc->gdb_num_core_regs = 66; 7694 #else 7695 cc->gdb_core_xml_file = "i386-32bit.xml"; 7696 cc->gdb_num_core_regs = 50; 7697 #endif 7698 cc->disas_set_info = x86_disas_set_info; 7699 7700 dc->user_creatable = true; 7701 7702 object_class_property_add(oc, "family", "int", 7703 x86_cpuid_version_get_family, 7704 x86_cpuid_version_set_family, NULL, NULL); 7705 object_class_property_add(oc, "model", "int", 7706 x86_cpuid_version_get_model, 7707 x86_cpuid_version_set_model, NULL, NULL); 7708 object_class_property_add(oc, "stepping", "int", 7709 x86_cpuid_version_get_stepping, 7710 x86_cpuid_version_set_stepping, NULL, NULL); 7711 object_class_property_add_str(oc, "vendor", 7712 x86_cpuid_get_vendor, 7713 x86_cpuid_set_vendor); 7714 object_class_property_add_str(oc, "model-id", 7715 x86_cpuid_get_model_id, 7716 x86_cpuid_set_model_id); 7717 object_class_property_add(oc, "tsc-frequency", "int", 7718 x86_cpuid_get_tsc_freq, 7719 x86_cpuid_set_tsc_freq, NULL, NULL); 7720 /* 7721 * The "unavailable-features" property has the same semantics as 7722 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 7723 * QMP command: they list the features that would have prevented the 7724 * CPU from running if the "enforce" flag was set. 7725 */ 7726 object_class_property_add(oc, "unavailable-features", "strList", 7727 x86_cpu_get_unavailable_features, 7728 NULL, NULL, NULL); 7729 7730 #if !defined(CONFIG_USER_ONLY) 7731 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 7732 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 7733 #endif 7734 7735 for (w = 0; w < FEATURE_WORDS; w++) { 7736 int bitnr; 7737 for (bitnr = 0; bitnr < 64; bitnr++) { 7738 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 7739 } 7740 } 7741 } 7742 7743 static const TypeInfo x86_cpu_type_info = { 7744 .name = TYPE_X86_CPU, 7745 .parent = TYPE_CPU, 7746 .instance_size = sizeof(X86CPU), 7747 .instance_init = x86_cpu_initfn, 7748 .instance_post_init = x86_cpu_post_initfn, 7749 7750 .abstract = true, 7751 .class_size = sizeof(X86CPUClass), 7752 .class_init = x86_cpu_common_class_init, 7753 }; 7754 7755 /* "base" CPU model, used by query-cpu-model-expansion */ 7756 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7757 { 7758 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7759 7760 xcc->static_model = true; 7761 xcc->migration_safe = true; 7762 xcc->model_description = "base CPU model type with no features enabled"; 7763 xcc->ordering = 8; 7764 } 7765 7766 static const TypeInfo x86_base_cpu_type_info = { 7767 .name = X86_CPU_TYPE_NAME("base"), 7768 .parent = TYPE_X86_CPU, 7769 .class_init = x86_cpu_base_class_init, 7770 }; 7771 7772 static void x86_cpu_register_types(void) 7773 { 7774 int i; 7775 7776 type_register_static(&x86_cpu_type_info); 7777 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7778 x86_register_cpudef_types(&builtin_x86_defs[i]); 7779 } 7780 type_register_static(&max_x86_cpu_type_info); 7781 type_register_static(&x86_base_cpu_type_info); 7782 } 7783 7784 type_init(x86_cpu_register_types) 7785