1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "sysemu/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 51 /* Helpers for building CPUID[2] descriptors: */ 52 53 struct CPUID2CacheDescriptorInfo { 54 enum CacheType type; 55 int level; 56 int size; 57 int line_size; 58 int associativity; 59 }; 60 61 /* 62 * Known CPUID 2 cache descriptors. 63 * From Intel SDM Volume 2A, CPUID instruction 64 */ 65 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 67 .associativity = 4, .line_size = 32, }, 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 73 .associativity = 2, .line_size = 32, }, 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 79 .associativity = 6, .line_size = 64, }, 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 81 .associativity = 2, .line_size = 64, }, 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 83 .associativity = 8, .line_size = 64, }, 84 /* lines per sector is not supported cpuid2_cache_descriptor(), 85 * so descriptors 0x22, 0x23 are not included 86 */ 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 88 .associativity = 16, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x25, 0x20 are not included 91 */ 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 93 .associativity = 8, .line_size = 64, }, 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 107 .associativity = 4, .line_size = 64, }, 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 122 .associativity = 24, .line_size = 64, }, 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 8, .line_size = 64, }, 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 132 .associativity = 4, .line_size = 64, }, 133 /* lines per sector is not supported cpuid2_cache_descriptor(), 134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 135 */ 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 2, .line_size = 64, }, 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 64, }, 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 }; 185 186 /* 187 * "CPUID leaf 2 does not report cache descriptor information, 188 * use CPUID leaf 4 to query cache parameters" 189 */ 190 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 191 192 /* 193 * Return a CPUID 2 cache descriptor for a given cache. 194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 195 */ 196 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 197 { 198 int i; 199 200 assert(cache->size > 0); 201 assert(cache->level > 0); 202 assert(cache->line_size > 0); 203 assert(cache->associativity > 0); 204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 206 if (d->level == cache->level && d->type == cache->type && 207 d->size == cache->size && d->line_size == cache->line_size && 208 d->associativity == cache->associativity) { 209 return i; 210 } 211 } 212 213 return CACHE_DESCRIPTOR_UNAVAILABLE; 214 } 215 216 /* CPUID Leaf 4 constants: */ 217 218 /* EAX: */ 219 #define CACHE_TYPE_D 1 220 #define CACHE_TYPE_I 2 221 #define CACHE_TYPE_UNIFIED 3 222 223 #define CACHE_LEVEL(l) (l << 5) 224 225 #define CACHE_SELF_INIT_LEVEL (1 << 8) 226 227 /* EDX: */ 228 #define CACHE_NO_INVD_SHARING (1 << 0) 229 #define CACHE_INCLUSIVE (1 << 1) 230 #define CACHE_COMPLEX_IDX (1 << 2) 231 232 /* Encode CacheType for CPUID[4].EAX */ 233 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 236 0 /* Invalid value */) 237 238 239 /* Encode cache info for CPUID[4] */ 240 static void encode_cache_cpuid4(CPUCacheInfo *cache, 241 int num_apic_ids, int num_cores, 242 uint32_t *eax, uint32_t *ebx, 243 uint32_t *ecx, uint32_t *edx) 244 { 245 assert(cache->size == cache->line_size * cache->associativity * 246 cache->partitions * cache->sets); 247 248 assert(num_apic_ids > 0); 249 *eax = CACHE_TYPE(cache->type) | 250 CACHE_LEVEL(cache->level) | 251 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 252 ((num_cores - 1) << 26) | 253 ((num_apic_ids - 1) << 14); 254 255 assert(cache->line_size > 0); 256 assert(cache->partitions > 0); 257 assert(cache->associativity > 0); 258 /* We don't implement fully-associative caches */ 259 assert(cache->associativity < cache->sets); 260 *ebx = (cache->line_size - 1) | 261 ((cache->partitions - 1) << 12) | 262 ((cache->associativity - 1) << 22); 263 264 assert(cache->sets > 0); 265 *ecx = cache->sets - 1; 266 267 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 268 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 269 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 270 } 271 272 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 273 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 274 { 275 assert(cache->size % 1024 == 0); 276 assert(cache->lines_per_tag > 0); 277 assert(cache->associativity > 0); 278 assert(cache->line_size > 0); 279 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 280 (cache->lines_per_tag << 8) | (cache->line_size); 281 } 282 283 #define ASSOC_FULL 0xFF 284 285 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 286 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 287 a == 2 ? 0x2 : \ 288 a == 4 ? 0x4 : \ 289 a == 8 ? 0x6 : \ 290 a == 16 ? 0x8 : \ 291 a == 32 ? 0xA : \ 292 a == 48 ? 0xB : \ 293 a == 64 ? 0xC : \ 294 a == 96 ? 0xD : \ 295 a == 128 ? 0xE : \ 296 a == ASSOC_FULL ? 0xF : \ 297 0 /* invalid value */) 298 299 /* 300 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 301 * @l3 can be NULL. 302 */ 303 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 304 CPUCacheInfo *l3, 305 uint32_t *ecx, uint32_t *edx) 306 { 307 assert(l2->size % 1024 == 0); 308 assert(l2->associativity > 0); 309 assert(l2->lines_per_tag > 0); 310 assert(l2->line_size > 0); 311 *ecx = ((l2->size / 1024) << 16) | 312 (AMD_ENC_ASSOC(l2->associativity) << 12) | 313 (l2->lines_per_tag << 8) | (l2->line_size); 314 315 if (l3) { 316 assert(l3->size % (512 * 1024) == 0); 317 assert(l3->associativity > 0); 318 assert(l3->lines_per_tag > 0); 319 assert(l3->line_size > 0); 320 *edx = ((l3->size / (512 * 1024)) << 18) | 321 (AMD_ENC_ASSOC(l3->associativity) << 12) | 322 (l3->lines_per_tag << 8) | (l3->line_size); 323 } else { 324 *edx = 0; 325 } 326 } 327 328 /* Encode cache info for CPUID[8000001D] */ 329 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 330 X86CPUTopoInfo *topo_info, 331 uint32_t *eax, uint32_t *ebx, 332 uint32_t *ecx, uint32_t *edx) 333 { 334 uint32_t l3_threads; 335 assert(cache->size == cache->line_size * cache->associativity * 336 cache->partitions * cache->sets); 337 338 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 339 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 340 341 /* L3 is shared among multiple cores */ 342 if (cache->level == 3) { 343 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 344 *eax |= (l3_threads - 1) << 14; 345 } else { 346 *eax |= ((topo_info->threads_per_core - 1) << 14); 347 } 348 349 assert(cache->line_size > 0); 350 assert(cache->partitions > 0); 351 assert(cache->associativity > 0); 352 /* We don't implement fully-associative caches */ 353 assert(cache->associativity < cache->sets); 354 *ebx = (cache->line_size - 1) | 355 ((cache->partitions - 1) << 12) | 356 ((cache->associativity - 1) << 22); 357 358 assert(cache->sets > 0); 359 *ecx = cache->sets - 1; 360 361 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 362 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 363 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 364 } 365 366 /* Encode cache info for CPUID[8000001E] */ 367 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 368 uint32_t *eax, uint32_t *ebx, 369 uint32_t *ecx, uint32_t *edx) 370 { 371 X86CPUTopoIDs topo_ids; 372 373 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 374 375 *eax = cpu->apic_id; 376 377 /* 378 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 379 * Read-only. Reset: 0000_XXXXh. 380 * See Core::X86::Cpuid::ExtApicId. 381 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 382 * Bits Description 383 * 31:16 Reserved. 384 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 385 * The number of threads per core is ThreadsPerCore+1. 386 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 387 * 388 * NOTE: CoreId is already part of apic_id. Just use it. We can 389 * use all the 8 bits to represent the core_id here. 390 */ 391 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 392 393 /* 394 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 395 * Read-only. Reset: 0000_0XXXh. 396 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 397 * Bits Description 398 * 31:11 Reserved. 399 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 400 * ValidValues: 401 * Value Description 402 * 000b 1 node per processor. 403 * 001b 2 nodes per processor. 404 * 010b Reserved. 405 * 011b 4 nodes per processor. 406 * 111b-100b Reserved. 407 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 408 * 409 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 410 * But users can create more nodes than the actual hardware can 411 * support. To genaralize we can use all the upper 8 bits for nodes. 412 * NodeId is combination of node and socket_id which is already decoded 413 * in apic_id. Just use it by shifting. 414 */ 415 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 416 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 417 418 *edx = 0; 419 } 420 421 /* 422 * Definitions of the hardcoded cache entries we expose: 423 * These are legacy cache values. If there is a need to change any 424 * of these values please use builtin_x86_defs 425 */ 426 427 /* L1 data cache: */ 428 static CPUCacheInfo legacy_l1d_cache = { 429 .type = DATA_CACHE, 430 .level = 1, 431 .size = 32 * KiB, 432 .self_init = 1, 433 .line_size = 64, 434 .associativity = 8, 435 .sets = 64, 436 .partitions = 1, 437 .no_invd_sharing = true, 438 }; 439 440 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 441 static CPUCacheInfo legacy_l1d_cache_amd = { 442 .type = DATA_CACHE, 443 .level = 1, 444 .size = 64 * KiB, 445 .self_init = 1, 446 .line_size = 64, 447 .associativity = 2, 448 .sets = 512, 449 .partitions = 1, 450 .lines_per_tag = 1, 451 .no_invd_sharing = true, 452 }; 453 454 /* L1 instruction cache: */ 455 static CPUCacheInfo legacy_l1i_cache = { 456 .type = INSTRUCTION_CACHE, 457 .level = 1, 458 .size = 32 * KiB, 459 .self_init = 1, 460 .line_size = 64, 461 .associativity = 8, 462 .sets = 64, 463 .partitions = 1, 464 .no_invd_sharing = true, 465 }; 466 467 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 468 static CPUCacheInfo legacy_l1i_cache_amd = { 469 .type = INSTRUCTION_CACHE, 470 .level = 1, 471 .size = 64 * KiB, 472 .self_init = 1, 473 .line_size = 64, 474 .associativity = 2, 475 .sets = 512, 476 .partitions = 1, 477 .lines_per_tag = 1, 478 .no_invd_sharing = true, 479 }; 480 481 /* Level 2 unified cache: */ 482 static CPUCacheInfo legacy_l2_cache = { 483 .type = UNIFIED_CACHE, 484 .level = 2, 485 .size = 4 * MiB, 486 .self_init = 1, 487 .line_size = 64, 488 .associativity = 16, 489 .sets = 4096, 490 .partitions = 1, 491 .no_invd_sharing = true, 492 }; 493 494 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 495 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 496 .type = UNIFIED_CACHE, 497 .level = 2, 498 .size = 2 * MiB, 499 .line_size = 64, 500 .associativity = 8, 501 }; 502 503 504 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 505 static CPUCacheInfo legacy_l2_cache_amd = { 506 .type = UNIFIED_CACHE, 507 .level = 2, 508 .size = 512 * KiB, 509 .line_size = 64, 510 .lines_per_tag = 1, 511 .associativity = 16, 512 .sets = 512, 513 .partitions = 1, 514 }; 515 516 /* Level 3 unified cache: */ 517 static CPUCacheInfo legacy_l3_cache = { 518 .type = UNIFIED_CACHE, 519 .level = 3, 520 .size = 16 * MiB, 521 .line_size = 64, 522 .associativity = 16, 523 .sets = 16384, 524 .partitions = 1, 525 .lines_per_tag = 1, 526 .self_init = true, 527 .inclusive = true, 528 .complex_indexing = true, 529 }; 530 531 /* TLB definitions: */ 532 533 #define L1_DTLB_2M_ASSOC 1 534 #define L1_DTLB_2M_ENTRIES 255 535 #define L1_DTLB_4K_ASSOC 1 536 #define L1_DTLB_4K_ENTRIES 255 537 538 #define L1_ITLB_2M_ASSOC 1 539 #define L1_ITLB_2M_ENTRIES 255 540 #define L1_ITLB_4K_ASSOC 1 541 #define L1_ITLB_4K_ENTRIES 255 542 543 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 544 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 545 #define L2_DTLB_4K_ASSOC 4 546 #define L2_DTLB_4K_ENTRIES 512 547 548 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 549 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 550 #define L2_ITLB_4K_ASSOC 4 551 #define L2_ITLB_4K_ENTRIES 512 552 553 /* CPUID Leaf 0x14 constants: */ 554 #define INTEL_PT_MAX_SUBLEAF 0x1 555 /* 556 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 557 * MSR can be accessed; 558 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 559 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 560 * of Intel PT MSRs across warm reset; 561 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 562 */ 563 #define INTEL_PT_MINIMAL_EBX 0xf 564 /* 565 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 566 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 567 * accessed; 568 * bit[01]: ToPA tables can hold any number of output entries, up to the 569 * maximum allowed by the MaskOrTableOffset field of 570 * IA32_RTIT_OUTPUT_MASK_PTRS; 571 * bit[02]: Support Single-Range Output scheme; 572 */ 573 #define INTEL_PT_MINIMAL_ECX 0x7 574 /* generated packets which contain IP payloads have LIP values */ 575 #define INTEL_PT_IP_LIP (1 << 31) 576 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 577 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 578 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 579 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 580 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 581 582 /* CPUID Leaf 0x1D constants: */ 583 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 584 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 585 #define INTEL_AMX_BYTES_PER_TILE 0x400 586 #define INTEL_AMX_BYTES_PER_ROW 0x40 587 #define INTEL_AMX_TILE_MAX_NAMES 0x8 588 #define INTEL_AMX_TILE_MAX_ROWS 0x10 589 590 /* CPUID Leaf 0x1E constants: */ 591 #define INTEL_AMX_TMUL_MAX_K 0x10 592 #define INTEL_AMX_TMUL_MAX_N 0x40 593 594 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 595 uint32_t vendor2, uint32_t vendor3) 596 { 597 int i; 598 for (i = 0; i < 4; i++) { 599 dst[i] = vendor1 >> (8 * i); 600 dst[i + 4] = vendor2 >> (8 * i); 601 dst[i + 8] = vendor3 >> (8 * i); 602 } 603 dst[CPUID_VENDOR_SZ] = '\0'; 604 } 605 606 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 607 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 608 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 609 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 610 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 611 CPUID_PSE36 | CPUID_FXSR) 612 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 613 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 614 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 615 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 616 CPUID_PAE | CPUID_SEP | CPUID_APIC) 617 618 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 619 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 620 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 621 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 622 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 623 /* partly implemented: 624 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 625 /* missing: 626 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 627 628 /* 629 * Kernel-only features that can be shown to usermode programs even if 630 * they aren't actually supported by TCG, because qemu-user only runs 631 * in CPL=3; remove them if they are ever implemented for system emulation. 632 */ 633 #if defined CONFIG_USER_ONLY 634 #define CPUID_EXT_KERNEL_FEATURES \ 635 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 636 #else 637 #define CPUID_EXT_KERNEL_FEATURES 0 638 #endif 639 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 644 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 645 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 646 /* missing: 647 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 648 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 649 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 650 CPUID_EXT_TSC_DEADLINE_TIMER 651 */ 652 653 #ifdef TARGET_X86_64 654 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 655 #else 656 #define TCG_EXT2_X86_64_FEATURES 0 657 #endif 658 659 /* 660 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 661 * in usermode or by 32-bit programs. Those are added to supported 662 * TCG features unconditionally in user-mode emulation mode. This may 663 * indeed seem strange or incorrect, but it works because code running 664 * under usermode emulation cannot access them. 665 * 666 * Even for long mode, qemu-i386 is not running "a userspace program on a 667 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 668 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 669 * but again the difference is only visible in kernel mode. 670 */ 671 #if defined CONFIG_LINUX_USER 672 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 673 #elif defined CONFIG_USER_ONLY 674 /* FIXME: Long mode not yet supported for i386 bsd-user */ 675 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 676 #else 677 #define CPUID_EXT2_KERNEL_FEATURES 0 678 #endif 679 680 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 681 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 682 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 683 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 684 CPUID_EXT2_KERNEL_FEATURES) 685 686 #if defined CONFIG_USER_ONLY 687 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 688 #else 689 #define CPUID_EXT3_KERNEL_FEATURES 0 690 #endif 691 692 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 693 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 694 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 695 696 #define TCG_EXT4_FEATURES 0 697 698 #if defined CONFIG_USER_ONLY 699 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 700 #else 701 #define CPUID_SVM_KERNEL_FEATURES 0 702 #endif 703 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 704 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 705 706 #define TCG_KVM_FEATURES 0 707 708 #if defined CONFIG_USER_ONLY 709 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 710 #else 711 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 712 #endif 713 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 714 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 715 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 716 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 717 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 718 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 719 /* missing: 720 CPUID_7_0_EBX_HLE 721 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 722 723 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 724 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 725 #else 726 #define TCG_7_0_ECX_RDPID 0 727 #endif 728 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 729 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 730 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 731 TCG_7_0_ECX_RDPID) 732 733 #if defined CONFIG_USER_ONLY 734 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 735 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 736 #else 737 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 738 #endif 739 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 740 741 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 742 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 743 #define TCG_7_1_EDX_FEATURES 0 744 #define TCG_7_2_EDX_FEATURES 0 745 #define TCG_APM_FEATURES 0 746 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 747 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 748 /* missing: 749 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 750 #define TCG_14_0_ECX_FEATURES 0 751 #define TCG_SGX_12_0_EAX_FEATURES 0 752 #define TCG_SGX_12_0_EBX_FEATURES 0 753 #define TCG_SGX_12_1_EAX_FEATURES 0 754 755 #if defined CONFIG_USER_ONLY 756 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 757 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 758 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 759 CPUID_8000_0008_EBX_AMD_PSFD) 760 #else 761 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 762 #endif 763 764 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 765 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 766 767 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 768 [FEAT_1_EDX] = { 769 .type = CPUID_FEATURE_WORD, 770 .feat_names = { 771 "fpu", "vme", "de", "pse", 772 "tsc", "msr", "pae", "mce", 773 "cx8", "apic", NULL, "sep", 774 "mtrr", "pge", "mca", "cmov", 775 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 776 NULL, "ds" /* Intel dts */, "acpi", "mmx", 777 "fxsr", "sse", "sse2", "ss", 778 "ht" /* Intel htt */, "tm", "ia64", "pbe", 779 }, 780 .cpuid = {.eax = 1, .reg = R_EDX, }, 781 .tcg_features = TCG_FEATURES, 782 .no_autoenable_flags = CPUID_HT, 783 }, 784 [FEAT_1_ECX] = { 785 .type = CPUID_FEATURE_WORD, 786 .feat_names = { 787 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 788 "ds-cpl", "vmx", "smx", "est", 789 "tm2", "ssse3", "cid", NULL, 790 "fma", "cx16", "xtpr", "pdcm", 791 NULL, "pcid", "dca", "sse4.1", 792 "sse4.2", "x2apic", "movbe", "popcnt", 793 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 794 "avx", "f16c", "rdrand", "hypervisor", 795 }, 796 .cpuid = { .eax = 1, .reg = R_ECX, }, 797 .tcg_features = TCG_EXT_FEATURES, 798 }, 799 /* Feature names that are already defined on feature_name[] but 800 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 801 * names on feat_names below. They are copied automatically 802 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 803 */ 804 [FEAT_8000_0001_EDX] = { 805 .type = CPUID_FEATURE_WORD, 806 .feat_names = { 807 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 808 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 809 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 810 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 811 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 812 "nx", NULL, "mmxext", NULL /* mmx */, 813 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 814 NULL, "lm", "3dnowext", "3dnow", 815 }, 816 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 817 .tcg_features = TCG_EXT2_FEATURES, 818 }, 819 [FEAT_8000_0001_ECX] = { 820 .type = CPUID_FEATURE_WORD, 821 .feat_names = { 822 "lahf-lm", "cmp-legacy", "svm", "extapic", 823 "cr8legacy", "abm", "sse4a", "misalignsse", 824 "3dnowprefetch", "osvw", "ibs", "xop", 825 "skinit", "wdt", NULL, "lwp", 826 "fma4", "tce", NULL, "nodeid-msr", 827 NULL, "tbm", "topoext", "perfctr-core", 828 "perfctr-nb", NULL, NULL, NULL, 829 NULL, NULL, NULL, NULL, 830 }, 831 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 832 .tcg_features = TCG_EXT3_FEATURES, 833 /* 834 * TOPOEXT is always allowed but can't be enabled blindly by 835 * "-cpu host", as it requires consistent cache topology info 836 * to be provided so it doesn't confuse guests. 837 */ 838 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 839 }, 840 [FEAT_C000_0001_EDX] = { 841 .type = CPUID_FEATURE_WORD, 842 .feat_names = { 843 NULL, NULL, "xstore", "xstore-en", 844 NULL, NULL, "xcrypt", "xcrypt-en", 845 "ace2", "ace2-en", "phe", "phe-en", 846 "pmm", "pmm-en", NULL, NULL, 847 NULL, NULL, NULL, NULL, 848 NULL, NULL, NULL, NULL, 849 NULL, NULL, NULL, NULL, 850 NULL, NULL, NULL, NULL, 851 }, 852 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 853 .tcg_features = TCG_EXT4_FEATURES, 854 }, 855 [FEAT_KVM] = { 856 .type = CPUID_FEATURE_WORD, 857 .feat_names = { 858 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 859 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 860 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 861 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 862 NULL, NULL, NULL, NULL, 863 NULL, NULL, NULL, NULL, 864 "kvmclock-stable-bit", NULL, NULL, NULL, 865 NULL, NULL, NULL, NULL, 866 }, 867 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 868 .tcg_features = TCG_KVM_FEATURES, 869 }, 870 [FEAT_KVM_HINTS] = { 871 .type = CPUID_FEATURE_WORD, 872 .feat_names = { 873 "kvm-hint-dedicated", NULL, NULL, NULL, 874 NULL, NULL, NULL, NULL, 875 NULL, NULL, NULL, NULL, 876 NULL, NULL, NULL, NULL, 877 NULL, NULL, NULL, NULL, 878 NULL, NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 NULL, NULL, NULL, NULL, 881 }, 882 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 883 .tcg_features = TCG_KVM_FEATURES, 884 /* 885 * KVM hints aren't auto-enabled by -cpu host, they need to be 886 * explicitly enabled in the command-line. 887 */ 888 .no_autoenable_flags = ~0U, 889 }, 890 [FEAT_SVM] = { 891 .type = CPUID_FEATURE_WORD, 892 .feat_names = { 893 "npt", "lbrv", "svm-lock", "nrip-save", 894 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 895 NULL, NULL, "pause-filter", NULL, 896 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 897 "vgif", NULL, NULL, NULL, 898 NULL, NULL, NULL, NULL, 899 NULL, "vnmi", NULL, NULL, 900 "svme-addr-chk", NULL, NULL, NULL, 901 }, 902 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 903 .tcg_features = TCG_SVM_FEATURES, 904 }, 905 [FEAT_7_0_EBX] = { 906 .type = CPUID_FEATURE_WORD, 907 .feat_names = { 908 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 909 "hle", "avx2", NULL, "smep", 910 "bmi2", "erms", "invpcid", "rtm", 911 NULL, NULL, "mpx", NULL, 912 "avx512f", "avx512dq", "rdseed", "adx", 913 "smap", "avx512ifma", "pcommit", "clflushopt", 914 "clwb", "intel-pt", "avx512pf", "avx512er", 915 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 916 }, 917 .cpuid = { 918 .eax = 7, 919 .needs_ecx = true, .ecx = 0, 920 .reg = R_EBX, 921 }, 922 .tcg_features = TCG_7_0_EBX_FEATURES, 923 }, 924 [FEAT_7_0_ECX] = { 925 .type = CPUID_FEATURE_WORD, 926 .feat_names = { 927 NULL, "avx512vbmi", "umip", "pku", 928 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 929 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 930 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 931 "la57", NULL, NULL, NULL, 932 NULL, NULL, "rdpid", NULL, 933 "bus-lock-detect", "cldemote", NULL, "movdiri", 934 "movdir64b", NULL, "sgxlc", "pks", 935 }, 936 .cpuid = { 937 .eax = 7, 938 .needs_ecx = true, .ecx = 0, 939 .reg = R_ECX, 940 }, 941 .tcg_features = TCG_7_0_ECX_FEATURES, 942 }, 943 [FEAT_7_0_EDX] = { 944 .type = CPUID_FEATURE_WORD, 945 .feat_names = { 946 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 947 "fsrm", NULL, NULL, NULL, 948 "avx512-vp2intersect", NULL, "md-clear", NULL, 949 NULL, NULL, "serialize", NULL, 950 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 951 NULL, NULL, "amx-bf16", "avx512-fp16", 952 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 953 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 954 }, 955 .cpuid = { 956 .eax = 7, 957 .needs_ecx = true, .ecx = 0, 958 .reg = R_EDX, 959 }, 960 .tcg_features = TCG_7_0_EDX_FEATURES, 961 }, 962 [FEAT_7_1_EAX] = { 963 .type = CPUID_FEATURE_WORD, 964 .feat_names = { 965 NULL, NULL, NULL, NULL, 966 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 967 NULL, NULL, "fzrm", "fsrs", 968 "fsrc", NULL, NULL, NULL, 969 NULL, NULL, NULL, NULL, 970 NULL, "amx-fp16", NULL, "avx-ifma", 971 NULL, NULL, NULL, NULL, 972 NULL, NULL, NULL, NULL, 973 }, 974 .cpuid = { 975 .eax = 7, 976 .needs_ecx = true, .ecx = 1, 977 .reg = R_EAX, 978 }, 979 .tcg_features = TCG_7_1_EAX_FEATURES, 980 }, 981 [FEAT_7_1_EDX] = { 982 .type = CPUID_FEATURE_WORD, 983 .feat_names = { 984 NULL, NULL, NULL, NULL, 985 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 986 "amx-complex", NULL, NULL, NULL, 987 NULL, NULL, "prefetchiti", NULL, 988 NULL, NULL, NULL, NULL, 989 NULL, NULL, NULL, NULL, 990 NULL, NULL, NULL, NULL, 991 NULL, NULL, NULL, NULL, 992 }, 993 .cpuid = { 994 .eax = 7, 995 .needs_ecx = true, .ecx = 1, 996 .reg = R_EDX, 997 }, 998 .tcg_features = TCG_7_1_EDX_FEATURES, 999 }, 1000 [FEAT_7_2_EDX] = { 1001 .type = CPUID_FEATURE_WORD, 1002 .feat_names = { 1003 NULL, NULL, NULL, NULL, 1004 NULL, "mcdt-no", NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 NULL, NULL, NULL, NULL, 1008 NULL, NULL, NULL, NULL, 1009 NULL, NULL, NULL, NULL, 1010 NULL, NULL, NULL, NULL, 1011 }, 1012 .cpuid = { 1013 .eax = 7, 1014 .needs_ecx = true, .ecx = 2, 1015 .reg = R_EDX, 1016 }, 1017 .tcg_features = TCG_7_2_EDX_FEATURES, 1018 }, 1019 [FEAT_8000_0007_EDX] = { 1020 .type = CPUID_FEATURE_WORD, 1021 .feat_names = { 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 "invtsc", NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 NULL, NULL, NULL, NULL, 1030 }, 1031 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1032 .tcg_features = TCG_APM_FEATURES, 1033 .unmigratable_flags = CPUID_APM_INVTSC, 1034 }, 1035 [FEAT_8000_0008_EBX] = { 1036 .type = CPUID_FEATURE_WORD, 1037 .feat_names = { 1038 "clzero", NULL, "xsaveerptr", NULL, 1039 NULL, NULL, NULL, NULL, 1040 NULL, "wbnoinvd", NULL, NULL, 1041 "ibpb", NULL, "ibrs", "amd-stibp", 1042 NULL, "stibp-always-on", NULL, NULL, 1043 NULL, NULL, NULL, NULL, 1044 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1045 "amd-psfd", NULL, NULL, NULL, 1046 }, 1047 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1048 .tcg_features = TCG_8000_0008_EBX, 1049 .unmigratable_flags = 0, 1050 }, 1051 [FEAT_8000_0021_EAX] = { 1052 .type = CPUID_FEATURE_WORD, 1053 .feat_names = { 1054 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1055 NULL, NULL, "null-sel-clr-base", NULL, 1056 "auto-ibrs", NULL, NULL, NULL, 1057 NULL, NULL, NULL, NULL, 1058 NULL, NULL, NULL, NULL, 1059 NULL, NULL, NULL, NULL, 1060 NULL, NULL, NULL, NULL, 1061 NULL, NULL, NULL, NULL, 1062 }, 1063 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1064 .tcg_features = 0, 1065 .unmigratable_flags = 0, 1066 }, 1067 [FEAT_XSAVE] = { 1068 .type = CPUID_FEATURE_WORD, 1069 .feat_names = { 1070 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1071 "xfd", NULL, NULL, NULL, 1072 NULL, NULL, NULL, NULL, 1073 NULL, NULL, NULL, NULL, 1074 NULL, NULL, NULL, NULL, 1075 NULL, NULL, NULL, NULL, 1076 NULL, NULL, NULL, NULL, 1077 NULL, NULL, NULL, NULL, 1078 }, 1079 .cpuid = { 1080 .eax = 0xd, 1081 .needs_ecx = true, .ecx = 1, 1082 .reg = R_EAX, 1083 }, 1084 .tcg_features = TCG_XSAVE_FEATURES, 1085 }, 1086 [FEAT_XSAVE_XSS_LO] = { 1087 .type = CPUID_FEATURE_WORD, 1088 .feat_names = { 1089 NULL, NULL, NULL, NULL, 1090 NULL, NULL, NULL, NULL, 1091 NULL, NULL, NULL, NULL, 1092 NULL, NULL, NULL, NULL, 1093 NULL, NULL, NULL, NULL, 1094 NULL, NULL, NULL, NULL, 1095 NULL, NULL, NULL, NULL, 1096 NULL, NULL, NULL, NULL, 1097 }, 1098 .cpuid = { 1099 .eax = 0xD, 1100 .needs_ecx = true, 1101 .ecx = 1, 1102 .reg = R_ECX, 1103 }, 1104 }, 1105 [FEAT_XSAVE_XSS_HI] = { 1106 .type = CPUID_FEATURE_WORD, 1107 .cpuid = { 1108 .eax = 0xD, 1109 .needs_ecx = true, 1110 .ecx = 1, 1111 .reg = R_EDX 1112 }, 1113 }, 1114 [FEAT_6_EAX] = { 1115 .type = CPUID_FEATURE_WORD, 1116 .feat_names = { 1117 NULL, NULL, "arat", NULL, 1118 NULL, NULL, NULL, NULL, 1119 NULL, NULL, NULL, NULL, 1120 NULL, NULL, NULL, NULL, 1121 NULL, NULL, NULL, NULL, 1122 NULL, NULL, NULL, NULL, 1123 NULL, NULL, NULL, NULL, 1124 NULL, NULL, NULL, NULL, 1125 }, 1126 .cpuid = { .eax = 6, .reg = R_EAX, }, 1127 .tcg_features = TCG_6_EAX_FEATURES, 1128 }, 1129 [FEAT_XSAVE_XCR0_LO] = { 1130 .type = CPUID_FEATURE_WORD, 1131 .cpuid = { 1132 .eax = 0xD, 1133 .needs_ecx = true, .ecx = 0, 1134 .reg = R_EAX, 1135 }, 1136 .tcg_features = ~0U, 1137 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1138 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1139 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1140 XSTATE_PKRU_MASK, 1141 }, 1142 [FEAT_XSAVE_XCR0_HI] = { 1143 .type = CPUID_FEATURE_WORD, 1144 .cpuid = { 1145 .eax = 0xD, 1146 .needs_ecx = true, .ecx = 0, 1147 .reg = R_EDX, 1148 }, 1149 .tcg_features = ~0U, 1150 }, 1151 /*Below are MSR exposed features*/ 1152 [FEAT_ARCH_CAPABILITIES] = { 1153 .type = MSR_FEATURE_WORD, 1154 .feat_names = { 1155 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1156 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1157 "taa-no", NULL, NULL, NULL, 1158 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1159 NULL, "fb-clear", NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 "pbrsb-no", NULL, "gds-no", "rfds-no", 1162 "rfds-clear", NULL, NULL, NULL, 1163 }, 1164 .msr = { 1165 .index = MSR_IA32_ARCH_CAPABILITIES, 1166 }, 1167 /* 1168 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1169 * cannot be read from user mode. Therefore, it has no impact 1170 > on any user-mode operation, and warnings about unsupported 1171 * features do not matter. 1172 */ 1173 .tcg_features = ~0U, 1174 }, 1175 [FEAT_CORE_CAPABILITY] = { 1176 .type = MSR_FEATURE_WORD, 1177 .feat_names = { 1178 NULL, NULL, NULL, NULL, 1179 NULL, "split-lock-detect", NULL, NULL, 1180 NULL, NULL, NULL, NULL, 1181 NULL, NULL, NULL, NULL, 1182 NULL, NULL, NULL, NULL, 1183 NULL, NULL, NULL, NULL, 1184 NULL, NULL, NULL, NULL, 1185 NULL, NULL, NULL, NULL, 1186 }, 1187 .msr = { 1188 .index = MSR_IA32_CORE_CAPABILITY, 1189 }, 1190 }, 1191 [FEAT_PERF_CAPABILITIES] = { 1192 .type = MSR_FEATURE_WORD, 1193 .feat_names = { 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 NULL, "full-width-write", NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 NULL, NULL, NULL, NULL, 1201 NULL, NULL, NULL, NULL, 1202 }, 1203 .msr = { 1204 .index = MSR_IA32_PERF_CAPABILITIES, 1205 }, 1206 }, 1207 1208 [FEAT_VMX_PROCBASED_CTLS] = { 1209 .type = MSR_FEATURE_WORD, 1210 .feat_names = { 1211 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1212 NULL, NULL, NULL, "vmx-hlt-exit", 1213 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1214 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1215 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1216 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1217 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1218 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1219 }, 1220 .msr = { 1221 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1222 } 1223 }, 1224 1225 [FEAT_VMX_SECONDARY_CTLS] = { 1226 .type = MSR_FEATURE_WORD, 1227 .feat_names = { 1228 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1229 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1230 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1231 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1232 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1233 "vmx-xsaves", NULL, NULL, NULL, 1234 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1235 NULL, NULL, NULL, NULL, 1236 }, 1237 .msr = { 1238 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1239 } 1240 }, 1241 1242 [FEAT_VMX_PINBASED_CTLS] = { 1243 .type = MSR_FEATURE_WORD, 1244 .feat_names = { 1245 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1246 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1247 NULL, NULL, NULL, NULL, 1248 NULL, NULL, NULL, NULL, 1249 NULL, NULL, NULL, NULL, 1250 NULL, NULL, NULL, NULL, 1251 NULL, NULL, NULL, NULL, 1252 NULL, NULL, NULL, NULL, 1253 }, 1254 .msr = { 1255 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1256 } 1257 }, 1258 1259 [FEAT_VMX_EXIT_CTLS] = { 1260 .type = MSR_FEATURE_WORD, 1261 /* 1262 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1263 * the LM CPUID bit. 1264 */ 1265 .feat_names = { 1266 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1269 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1270 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1271 "vmx-exit-save-efer", "vmx-exit-load-efer", 1272 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1273 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1274 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1275 }, 1276 .msr = { 1277 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1278 } 1279 }, 1280 1281 [FEAT_VMX_ENTRY_CTLS] = { 1282 .type = MSR_FEATURE_WORD, 1283 .feat_names = { 1284 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1287 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1288 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1289 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1290 NULL, NULL, NULL, NULL, 1291 NULL, NULL, NULL, NULL, 1292 }, 1293 .msr = { 1294 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1295 } 1296 }, 1297 1298 [FEAT_VMX_MISC] = { 1299 .type = MSR_FEATURE_WORD, 1300 .feat_names = { 1301 NULL, NULL, NULL, NULL, 1302 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1303 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 NULL, NULL, NULL, NULL, 1307 NULL, NULL, NULL, NULL, 1308 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1309 }, 1310 .msr = { 1311 .index = MSR_IA32_VMX_MISC, 1312 } 1313 }, 1314 1315 [FEAT_VMX_EPT_VPID_CAPS] = { 1316 .type = MSR_FEATURE_WORD, 1317 .feat_names = { 1318 "vmx-ept-execonly", NULL, NULL, NULL, 1319 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1320 NULL, NULL, NULL, NULL, 1321 NULL, NULL, NULL, NULL, 1322 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1323 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1324 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1325 NULL, NULL, NULL, NULL, 1326 "vmx-invvpid", NULL, NULL, NULL, 1327 NULL, NULL, NULL, NULL, 1328 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1329 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 NULL, NULL, NULL, NULL, 1334 NULL, NULL, NULL, NULL, 1335 }, 1336 .msr = { 1337 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1338 } 1339 }, 1340 1341 [FEAT_VMX_BASIC] = { 1342 .type = MSR_FEATURE_WORD, 1343 .feat_names = { 1344 [54] = "vmx-ins-outs", 1345 [55] = "vmx-true-ctls", 1346 [56] = "vmx-any-errcode", 1347 }, 1348 .msr = { 1349 .index = MSR_IA32_VMX_BASIC, 1350 }, 1351 /* Just to be safe - we don't support setting the MSEG version field. */ 1352 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1353 }, 1354 1355 [FEAT_VMX_VMFUNC] = { 1356 .type = MSR_FEATURE_WORD, 1357 .feat_names = { 1358 [0] = "vmx-eptp-switching", 1359 }, 1360 .msr = { 1361 .index = MSR_IA32_VMX_VMFUNC, 1362 } 1363 }, 1364 1365 [FEAT_14_0_ECX] = { 1366 .type = CPUID_FEATURE_WORD, 1367 .feat_names = { 1368 NULL, NULL, NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 NULL, NULL, NULL, NULL, 1371 NULL, NULL, NULL, NULL, 1372 NULL, NULL, NULL, NULL, 1373 NULL, NULL, NULL, NULL, 1374 NULL, NULL, NULL, NULL, 1375 NULL, NULL, NULL, "intel-pt-lip", 1376 }, 1377 .cpuid = { 1378 .eax = 0x14, 1379 .needs_ecx = true, .ecx = 0, 1380 .reg = R_ECX, 1381 }, 1382 .tcg_features = TCG_14_0_ECX_FEATURES, 1383 }, 1384 1385 [FEAT_SGX_12_0_EAX] = { 1386 .type = CPUID_FEATURE_WORD, 1387 .feat_names = { 1388 "sgx1", "sgx2", NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, "sgx-edeccssa", 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 NULL, NULL, NULL, NULL, 1396 }, 1397 .cpuid = { 1398 .eax = 0x12, 1399 .needs_ecx = true, .ecx = 0, 1400 .reg = R_EAX, 1401 }, 1402 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1403 }, 1404 1405 [FEAT_SGX_12_0_EBX] = { 1406 .type = CPUID_FEATURE_WORD, 1407 .feat_names = { 1408 "sgx-exinfo" , NULL, NULL, NULL, 1409 NULL, NULL, NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 }, 1417 .cpuid = { 1418 .eax = 0x12, 1419 .needs_ecx = true, .ecx = 0, 1420 .reg = R_EBX, 1421 }, 1422 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1423 }, 1424 1425 [FEAT_SGX_12_1_EAX] = { 1426 .type = CPUID_FEATURE_WORD, 1427 .feat_names = { 1428 NULL, "sgx-debug", "sgx-mode64", NULL, 1429 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1430 NULL, NULL, "sgx-aex-notify", NULL, 1431 NULL, NULL, NULL, NULL, 1432 NULL, NULL, NULL, NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, NULL, NULL, NULL, 1435 NULL, NULL, NULL, NULL, 1436 }, 1437 .cpuid = { 1438 .eax = 0x12, 1439 .needs_ecx = true, .ecx = 1, 1440 .reg = R_EAX, 1441 }, 1442 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1443 }, 1444 }; 1445 1446 typedef struct FeatureMask { 1447 FeatureWord index; 1448 uint64_t mask; 1449 } FeatureMask; 1450 1451 typedef struct FeatureDep { 1452 FeatureMask from, to; 1453 } FeatureDep; 1454 1455 static FeatureDep feature_dependencies[] = { 1456 { 1457 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1458 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1459 }, 1460 { 1461 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1462 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1463 }, 1464 { 1465 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1466 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1467 }, 1468 { 1469 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1470 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1471 }, 1472 { 1473 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1474 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1475 }, 1476 { 1477 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1478 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1479 }, 1480 { 1481 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1482 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1483 }, 1484 { 1485 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1486 .to = { FEAT_VMX_MISC, ~0ull }, 1487 }, 1488 { 1489 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1490 .to = { FEAT_VMX_BASIC, ~0ull }, 1491 }, 1492 { 1493 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1494 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1495 }, 1496 { 1497 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1498 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1499 }, 1500 { 1501 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1502 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1503 }, 1504 { 1505 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1506 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1507 }, 1508 { 1509 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1510 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1511 }, 1512 { 1513 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1514 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1515 }, 1516 { 1517 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1518 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1519 }, 1520 { 1521 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1522 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1523 }, 1524 { 1525 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1526 .to = { FEAT_14_0_ECX, ~0ull }, 1527 }, 1528 { 1529 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1530 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1531 }, 1532 { 1533 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1534 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1535 }, 1536 { 1537 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1538 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1539 }, 1540 { 1541 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1542 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1543 }, 1544 { 1545 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1546 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1547 }, 1548 { 1549 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1550 .to = { FEAT_SVM, ~0ull }, 1551 }, 1552 { 1553 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1554 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1555 }, 1556 }; 1557 1558 typedef struct X86RegisterInfo32 { 1559 /* Name of register */ 1560 const char *name; 1561 /* QAPI enum value register */ 1562 X86CPURegister32 qapi_enum; 1563 } X86RegisterInfo32; 1564 1565 #define REGISTER(reg) \ 1566 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1567 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1568 REGISTER(EAX), 1569 REGISTER(ECX), 1570 REGISTER(EDX), 1571 REGISTER(EBX), 1572 REGISTER(ESP), 1573 REGISTER(EBP), 1574 REGISTER(ESI), 1575 REGISTER(EDI), 1576 }; 1577 #undef REGISTER 1578 1579 /* CPUID feature bits available in XSS */ 1580 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1581 1582 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1583 [XSTATE_FP_BIT] = { 1584 /* x87 FP state component is always enabled if XSAVE is supported */ 1585 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1586 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1587 }, 1588 [XSTATE_SSE_BIT] = { 1589 /* SSE state component is always enabled if XSAVE is supported */ 1590 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1591 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1592 }, 1593 [XSTATE_YMM_BIT] = 1594 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1595 .size = sizeof(XSaveAVX) }, 1596 [XSTATE_BNDREGS_BIT] = 1597 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1598 .size = sizeof(XSaveBNDREG) }, 1599 [XSTATE_BNDCSR_BIT] = 1600 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1601 .size = sizeof(XSaveBNDCSR) }, 1602 [XSTATE_OPMASK_BIT] = 1603 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1604 .size = sizeof(XSaveOpmask) }, 1605 [XSTATE_ZMM_Hi256_BIT] = 1606 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1607 .size = sizeof(XSaveZMM_Hi256) }, 1608 [XSTATE_Hi16_ZMM_BIT] = 1609 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1610 .size = sizeof(XSaveHi16_ZMM) }, 1611 [XSTATE_PKRU_BIT] = 1612 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1613 .size = sizeof(XSavePKRU) }, 1614 [XSTATE_ARCH_LBR_BIT] = { 1615 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1616 .offset = 0 /*supervisor mode component, offset = 0 */, 1617 .size = sizeof(XSavesArchLBR) }, 1618 [XSTATE_XTILE_CFG_BIT] = { 1619 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1620 .size = sizeof(XSaveXTILECFG), 1621 }, 1622 [XSTATE_XTILE_DATA_BIT] = { 1623 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1624 .size = sizeof(XSaveXTILEDATA) 1625 }, 1626 }; 1627 1628 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1629 { 1630 uint64_t ret = x86_ext_save_areas[0].size; 1631 const ExtSaveArea *esa; 1632 uint32_t offset = 0; 1633 int i; 1634 1635 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1636 esa = &x86_ext_save_areas[i]; 1637 if ((mask >> i) & 1) { 1638 offset = compacted ? ret : esa->offset; 1639 ret = MAX(ret, offset + esa->size); 1640 } 1641 } 1642 return ret; 1643 } 1644 1645 static inline bool accel_uses_host_cpuid(void) 1646 { 1647 return kvm_enabled() || hvf_enabled(); 1648 } 1649 1650 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1651 { 1652 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1653 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1654 } 1655 1656 /* Return name of 32-bit register, from a R_* constant */ 1657 static const char *get_register_name_32(unsigned int reg) 1658 { 1659 if (reg >= CPU_NB_REGS32) { 1660 return NULL; 1661 } 1662 return x86_reg_info_32[reg].name; 1663 } 1664 1665 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1666 { 1667 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1668 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1669 } 1670 1671 /* 1672 * Returns the set of feature flags that are supported and migratable by 1673 * QEMU, for a given FeatureWord. 1674 */ 1675 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1676 { 1677 FeatureWordInfo *wi = &feature_word_info[w]; 1678 uint64_t r = 0; 1679 int i; 1680 1681 for (i = 0; i < 64; i++) { 1682 uint64_t f = 1ULL << i; 1683 1684 /* If the feature name is known, it is implicitly considered migratable, 1685 * unless it is explicitly set in unmigratable_flags */ 1686 if ((wi->migratable_flags & f) || 1687 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1688 r |= f; 1689 } 1690 } 1691 return r; 1692 } 1693 1694 void host_cpuid(uint32_t function, uint32_t count, 1695 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1696 { 1697 uint32_t vec[4]; 1698 1699 #ifdef __x86_64__ 1700 asm volatile("cpuid" 1701 : "=a"(vec[0]), "=b"(vec[1]), 1702 "=c"(vec[2]), "=d"(vec[3]) 1703 : "0"(function), "c"(count) : "cc"); 1704 #elif defined(__i386__) 1705 asm volatile("pusha \n\t" 1706 "cpuid \n\t" 1707 "mov %%eax, 0(%2) \n\t" 1708 "mov %%ebx, 4(%2) \n\t" 1709 "mov %%ecx, 8(%2) \n\t" 1710 "mov %%edx, 12(%2) \n\t" 1711 "popa" 1712 : : "a"(function), "c"(count), "S"(vec) 1713 : "memory", "cc"); 1714 #else 1715 abort(); 1716 #endif 1717 1718 if (eax) 1719 *eax = vec[0]; 1720 if (ebx) 1721 *ebx = vec[1]; 1722 if (ecx) 1723 *ecx = vec[2]; 1724 if (edx) 1725 *edx = vec[3]; 1726 } 1727 1728 /* CPU class name definitions: */ 1729 1730 /* Return type name for a given CPU model name 1731 * Caller is responsible for freeing the returned string. 1732 */ 1733 static char *x86_cpu_type_name(const char *model_name) 1734 { 1735 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1736 } 1737 1738 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1739 { 1740 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1741 return object_class_by_name(typename); 1742 } 1743 1744 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1745 { 1746 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1747 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1748 return cpu_model_from_type(class_name); 1749 } 1750 1751 typedef struct X86CPUVersionDefinition { 1752 X86CPUVersion version; 1753 const char *alias; 1754 const char *note; 1755 PropValue *props; 1756 const CPUCaches *const cache_info; 1757 } X86CPUVersionDefinition; 1758 1759 /* Base definition for a CPU model */ 1760 typedef struct X86CPUDefinition { 1761 const char *name; 1762 uint32_t level; 1763 uint32_t xlevel; 1764 /* vendor is zero-terminated, 12 character ASCII string */ 1765 char vendor[CPUID_VENDOR_SZ + 1]; 1766 int family; 1767 int model; 1768 int stepping; 1769 FeatureWordArray features; 1770 const char *model_id; 1771 const CPUCaches *const cache_info; 1772 /* 1773 * Definitions for alternative versions of CPU model. 1774 * List is terminated by item with version == 0. 1775 * If NULL, version 1 will be registered automatically. 1776 */ 1777 const X86CPUVersionDefinition *versions; 1778 const char *deprecation_note; 1779 } X86CPUDefinition; 1780 1781 /* Reference to a specific CPU model version */ 1782 struct X86CPUModel { 1783 /* Base CPU definition */ 1784 const X86CPUDefinition *cpudef; 1785 /* CPU model version */ 1786 X86CPUVersion version; 1787 const char *note; 1788 /* 1789 * If true, this is an alias CPU model. 1790 * This matters only for "-cpu help" and query-cpu-definitions 1791 */ 1792 bool is_alias; 1793 }; 1794 1795 /* Get full model name for CPU version */ 1796 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1797 X86CPUVersion version) 1798 { 1799 assert(version > 0); 1800 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1801 } 1802 1803 static const X86CPUVersionDefinition * 1804 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1805 { 1806 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1807 static const X86CPUVersionDefinition default_version_list[] = { 1808 { 1 }, 1809 { /* end of list */ } 1810 }; 1811 1812 return def->versions ?: default_version_list; 1813 } 1814 1815 static const CPUCaches epyc_cache_info = { 1816 .l1d_cache = &(CPUCacheInfo) { 1817 .type = DATA_CACHE, 1818 .level = 1, 1819 .size = 32 * KiB, 1820 .line_size = 64, 1821 .associativity = 8, 1822 .partitions = 1, 1823 .sets = 64, 1824 .lines_per_tag = 1, 1825 .self_init = 1, 1826 .no_invd_sharing = true, 1827 }, 1828 .l1i_cache = &(CPUCacheInfo) { 1829 .type = INSTRUCTION_CACHE, 1830 .level = 1, 1831 .size = 64 * KiB, 1832 .line_size = 64, 1833 .associativity = 4, 1834 .partitions = 1, 1835 .sets = 256, 1836 .lines_per_tag = 1, 1837 .self_init = 1, 1838 .no_invd_sharing = true, 1839 }, 1840 .l2_cache = &(CPUCacheInfo) { 1841 .type = UNIFIED_CACHE, 1842 .level = 2, 1843 .size = 512 * KiB, 1844 .line_size = 64, 1845 .associativity = 8, 1846 .partitions = 1, 1847 .sets = 1024, 1848 .lines_per_tag = 1, 1849 }, 1850 .l3_cache = &(CPUCacheInfo) { 1851 .type = UNIFIED_CACHE, 1852 .level = 3, 1853 .size = 8 * MiB, 1854 .line_size = 64, 1855 .associativity = 16, 1856 .partitions = 1, 1857 .sets = 8192, 1858 .lines_per_tag = 1, 1859 .self_init = true, 1860 .inclusive = true, 1861 .complex_indexing = true, 1862 }, 1863 }; 1864 1865 static CPUCaches epyc_v4_cache_info = { 1866 .l1d_cache = &(CPUCacheInfo) { 1867 .type = DATA_CACHE, 1868 .level = 1, 1869 .size = 32 * KiB, 1870 .line_size = 64, 1871 .associativity = 8, 1872 .partitions = 1, 1873 .sets = 64, 1874 .lines_per_tag = 1, 1875 .self_init = 1, 1876 .no_invd_sharing = true, 1877 }, 1878 .l1i_cache = &(CPUCacheInfo) { 1879 .type = INSTRUCTION_CACHE, 1880 .level = 1, 1881 .size = 64 * KiB, 1882 .line_size = 64, 1883 .associativity = 4, 1884 .partitions = 1, 1885 .sets = 256, 1886 .lines_per_tag = 1, 1887 .self_init = 1, 1888 .no_invd_sharing = true, 1889 }, 1890 .l2_cache = &(CPUCacheInfo) { 1891 .type = UNIFIED_CACHE, 1892 .level = 2, 1893 .size = 512 * KiB, 1894 .line_size = 64, 1895 .associativity = 8, 1896 .partitions = 1, 1897 .sets = 1024, 1898 .lines_per_tag = 1, 1899 }, 1900 .l3_cache = &(CPUCacheInfo) { 1901 .type = UNIFIED_CACHE, 1902 .level = 3, 1903 .size = 8 * MiB, 1904 .line_size = 64, 1905 .associativity = 16, 1906 .partitions = 1, 1907 .sets = 8192, 1908 .lines_per_tag = 1, 1909 .self_init = true, 1910 .inclusive = true, 1911 .complex_indexing = false, 1912 }, 1913 }; 1914 1915 static const CPUCaches epyc_rome_cache_info = { 1916 .l1d_cache = &(CPUCacheInfo) { 1917 .type = DATA_CACHE, 1918 .level = 1, 1919 .size = 32 * KiB, 1920 .line_size = 64, 1921 .associativity = 8, 1922 .partitions = 1, 1923 .sets = 64, 1924 .lines_per_tag = 1, 1925 .self_init = 1, 1926 .no_invd_sharing = true, 1927 }, 1928 .l1i_cache = &(CPUCacheInfo) { 1929 .type = INSTRUCTION_CACHE, 1930 .level = 1, 1931 .size = 32 * KiB, 1932 .line_size = 64, 1933 .associativity = 8, 1934 .partitions = 1, 1935 .sets = 64, 1936 .lines_per_tag = 1, 1937 .self_init = 1, 1938 .no_invd_sharing = true, 1939 }, 1940 .l2_cache = &(CPUCacheInfo) { 1941 .type = UNIFIED_CACHE, 1942 .level = 2, 1943 .size = 512 * KiB, 1944 .line_size = 64, 1945 .associativity = 8, 1946 .partitions = 1, 1947 .sets = 1024, 1948 .lines_per_tag = 1, 1949 }, 1950 .l3_cache = &(CPUCacheInfo) { 1951 .type = UNIFIED_CACHE, 1952 .level = 3, 1953 .size = 16 * MiB, 1954 .line_size = 64, 1955 .associativity = 16, 1956 .partitions = 1, 1957 .sets = 16384, 1958 .lines_per_tag = 1, 1959 .self_init = true, 1960 .inclusive = true, 1961 .complex_indexing = true, 1962 }, 1963 }; 1964 1965 static const CPUCaches epyc_rome_v3_cache_info = { 1966 .l1d_cache = &(CPUCacheInfo) { 1967 .type = DATA_CACHE, 1968 .level = 1, 1969 .size = 32 * KiB, 1970 .line_size = 64, 1971 .associativity = 8, 1972 .partitions = 1, 1973 .sets = 64, 1974 .lines_per_tag = 1, 1975 .self_init = 1, 1976 .no_invd_sharing = true, 1977 }, 1978 .l1i_cache = &(CPUCacheInfo) { 1979 .type = INSTRUCTION_CACHE, 1980 .level = 1, 1981 .size = 32 * KiB, 1982 .line_size = 64, 1983 .associativity = 8, 1984 .partitions = 1, 1985 .sets = 64, 1986 .lines_per_tag = 1, 1987 .self_init = 1, 1988 .no_invd_sharing = true, 1989 }, 1990 .l2_cache = &(CPUCacheInfo) { 1991 .type = UNIFIED_CACHE, 1992 .level = 2, 1993 .size = 512 * KiB, 1994 .line_size = 64, 1995 .associativity = 8, 1996 .partitions = 1, 1997 .sets = 1024, 1998 .lines_per_tag = 1, 1999 }, 2000 .l3_cache = &(CPUCacheInfo) { 2001 .type = UNIFIED_CACHE, 2002 .level = 3, 2003 .size = 16 * MiB, 2004 .line_size = 64, 2005 .associativity = 16, 2006 .partitions = 1, 2007 .sets = 16384, 2008 .lines_per_tag = 1, 2009 .self_init = true, 2010 .inclusive = true, 2011 .complex_indexing = false, 2012 }, 2013 }; 2014 2015 static const CPUCaches epyc_milan_cache_info = { 2016 .l1d_cache = &(CPUCacheInfo) { 2017 .type = DATA_CACHE, 2018 .level = 1, 2019 .size = 32 * KiB, 2020 .line_size = 64, 2021 .associativity = 8, 2022 .partitions = 1, 2023 .sets = 64, 2024 .lines_per_tag = 1, 2025 .self_init = 1, 2026 .no_invd_sharing = true, 2027 }, 2028 .l1i_cache = &(CPUCacheInfo) { 2029 .type = INSTRUCTION_CACHE, 2030 .level = 1, 2031 .size = 32 * KiB, 2032 .line_size = 64, 2033 .associativity = 8, 2034 .partitions = 1, 2035 .sets = 64, 2036 .lines_per_tag = 1, 2037 .self_init = 1, 2038 .no_invd_sharing = true, 2039 }, 2040 .l2_cache = &(CPUCacheInfo) { 2041 .type = UNIFIED_CACHE, 2042 .level = 2, 2043 .size = 512 * KiB, 2044 .line_size = 64, 2045 .associativity = 8, 2046 .partitions = 1, 2047 .sets = 1024, 2048 .lines_per_tag = 1, 2049 }, 2050 .l3_cache = &(CPUCacheInfo) { 2051 .type = UNIFIED_CACHE, 2052 .level = 3, 2053 .size = 32 * MiB, 2054 .line_size = 64, 2055 .associativity = 16, 2056 .partitions = 1, 2057 .sets = 32768, 2058 .lines_per_tag = 1, 2059 .self_init = true, 2060 .inclusive = true, 2061 .complex_indexing = true, 2062 }, 2063 }; 2064 2065 static const CPUCaches epyc_milan_v2_cache_info = { 2066 .l1d_cache = &(CPUCacheInfo) { 2067 .type = DATA_CACHE, 2068 .level = 1, 2069 .size = 32 * KiB, 2070 .line_size = 64, 2071 .associativity = 8, 2072 .partitions = 1, 2073 .sets = 64, 2074 .lines_per_tag = 1, 2075 .self_init = 1, 2076 .no_invd_sharing = true, 2077 }, 2078 .l1i_cache = &(CPUCacheInfo) { 2079 .type = INSTRUCTION_CACHE, 2080 .level = 1, 2081 .size = 32 * KiB, 2082 .line_size = 64, 2083 .associativity = 8, 2084 .partitions = 1, 2085 .sets = 64, 2086 .lines_per_tag = 1, 2087 .self_init = 1, 2088 .no_invd_sharing = true, 2089 }, 2090 .l2_cache = &(CPUCacheInfo) { 2091 .type = UNIFIED_CACHE, 2092 .level = 2, 2093 .size = 512 * KiB, 2094 .line_size = 64, 2095 .associativity = 8, 2096 .partitions = 1, 2097 .sets = 1024, 2098 .lines_per_tag = 1, 2099 }, 2100 .l3_cache = &(CPUCacheInfo) { 2101 .type = UNIFIED_CACHE, 2102 .level = 3, 2103 .size = 32 * MiB, 2104 .line_size = 64, 2105 .associativity = 16, 2106 .partitions = 1, 2107 .sets = 32768, 2108 .lines_per_tag = 1, 2109 .self_init = true, 2110 .inclusive = true, 2111 .complex_indexing = false, 2112 }, 2113 }; 2114 2115 static const CPUCaches epyc_genoa_cache_info = { 2116 .l1d_cache = &(CPUCacheInfo) { 2117 .type = DATA_CACHE, 2118 .level = 1, 2119 .size = 32 * KiB, 2120 .line_size = 64, 2121 .associativity = 8, 2122 .partitions = 1, 2123 .sets = 64, 2124 .lines_per_tag = 1, 2125 .self_init = 1, 2126 .no_invd_sharing = true, 2127 }, 2128 .l1i_cache = &(CPUCacheInfo) { 2129 .type = INSTRUCTION_CACHE, 2130 .level = 1, 2131 .size = 32 * KiB, 2132 .line_size = 64, 2133 .associativity = 8, 2134 .partitions = 1, 2135 .sets = 64, 2136 .lines_per_tag = 1, 2137 .self_init = 1, 2138 .no_invd_sharing = true, 2139 }, 2140 .l2_cache = &(CPUCacheInfo) { 2141 .type = UNIFIED_CACHE, 2142 .level = 2, 2143 .size = 1 * MiB, 2144 .line_size = 64, 2145 .associativity = 8, 2146 .partitions = 1, 2147 .sets = 2048, 2148 .lines_per_tag = 1, 2149 }, 2150 .l3_cache = &(CPUCacheInfo) { 2151 .type = UNIFIED_CACHE, 2152 .level = 3, 2153 .size = 32 * MiB, 2154 .line_size = 64, 2155 .associativity = 16, 2156 .partitions = 1, 2157 .sets = 32768, 2158 .lines_per_tag = 1, 2159 .self_init = true, 2160 .inclusive = true, 2161 .complex_indexing = false, 2162 }, 2163 }; 2164 2165 /* The following VMX features are not supported by KVM and are left out in the 2166 * CPU definitions: 2167 * 2168 * Dual-monitor support (all processors) 2169 * Entry to SMM 2170 * Deactivate dual-monitor treatment 2171 * Number of CR3-target values 2172 * Shutdown activity state 2173 * Wait-for-SIPI activity state 2174 * PAUSE-loop exiting (Westmere and newer) 2175 * EPT-violation #VE (Broadwell and newer) 2176 * Inject event with insn length=0 (Skylake and newer) 2177 * Conceal non-root operation from PT 2178 * Conceal VM exits from PT 2179 * Conceal VM entries from PT 2180 * Enable ENCLS exiting 2181 * Mode-based execute control (XS/XU) 2182 * TSC scaling (Skylake Server and newer) 2183 * GPA translation for PT (IceLake and newer) 2184 * User wait and pause 2185 * ENCLV exiting 2186 * Load IA32_RTIT_CTL 2187 * Clear IA32_RTIT_CTL 2188 * Advanced VM-exit information for EPT violations 2189 * Sub-page write permissions 2190 * PT in VMX operation 2191 */ 2192 2193 static const X86CPUDefinition builtin_x86_defs[] = { 2194 { 2195 .name = "qemu64", 2196 .level = 0xd, 2197 .vendor = CPUID_VENDOR_AMD, 2198 .family = 15, 2199 .model = 107, 2200 .stepping = 1, 2201 .features[FEAT_1_EDX] = 2202 PPRO_FEATURES | 2203 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2204 CPUID_PSE36, 2205 .features[FEAT_1_ECX] = 2206 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2207 .features[FEAT_8000_0001_EDX] = 2208 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2209 .features[FEAT_8000_0001_ECX] = 2210 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2211 .xlevel = 0x8000000A, 2212 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2213 }, 2214 { 2215 .name = "phenom", 2216 .level = 5, 2217 .vendor = CPUID_VENDOR_AMD, 2218 .family = 16, 2219 .model = 2, 2220 .stepping = 3, 2221 /* Missing: CPUID_HT */ 2222 .features[FEAT_1_EDX] = 2223 PPRO_FEATURES | 2224 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2225 CPUID_PSE36 | CPUID_VME, 2226 .features[FEAT_1_ECX] = 2227 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2228 CPUID_EXT_POPCNT, 2229 .features[FEAT_8000_0001_EDX] = 2230 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2231 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2232 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2233 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2234 CPUID_EXT3_CR8LEG, 2235 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2236 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2237 .features[FEAT_8000_0001_ECX] = 2238 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2239 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2240 /* Missing: CPUID_SVM_LBRV */ 2241 .features[FEAT_SVM] = 2242 CPUID_SVM_NPT, 2243 .xlevel = 0x8000001A, 2244 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2245 }, 2246 { 2247 .name = "core2duo", 2248 .level = 10, 2249 .vendor = CPUID_VENDOR_INTEL, 2250 .family = 6, 2251 .model = 15, 2252 .stepping = 11, 2253 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2254 .features[FEAT_1_EDX] = 2255 PPRO_FEATURES | 2256 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2257 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2258 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2259 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2260 .features[FEAT_1_ECX] = 2261 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2262 CPUID_EXT_CX16, 2263 .features[FEAT_8000_0001_EDX] = 2264 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2265 .features[FEAT_8000_0001_ECX] = 2266 CPUID_EXT3_LAHF_LM, 2267 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2268 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2269 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2270 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2271 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2272 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2273 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2274 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2275 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2276 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2277 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2278 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2279 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2280 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2281 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2282 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2283 .features[FEAT_VMX_SECONDARY_CTLS] = 2284 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2285 .xlevel = 0x80000008, 2286 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2287 }, 2288 { 2289 .name = "kvm64", 2290 .level = 0xd, 2291 .vendor = CPUID_VENDOR_INTEL, 2292 .family = 15, 2293 .model = 6, 2294 .stepping = 1, 2295 /* Missing: CPUID_HT */ 2296 .features[FEAT_1_EDX] = 2297 PPRO_FEATURES | CPUID_VME | 2298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2299 CPUID_PSE36, 2300 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2301 .features[FEAT_1_ECX] = 2302 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2303 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2304 .features[FEAT_8000_0001_EDX] = 2305 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2306 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2307 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2308 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2309 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2310 .features[FEAT_8000_0001_ECX] = 2311 0, 2312 /* VMX features from Cedar Mill/Prescott */ 2313 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2314 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2315 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2316 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2317 VMX_PIN_BASED_NMI_EXITING, 2318 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2319 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2320 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2321 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2322 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2323 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2324 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2325 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2326 .xlevel = 0x80000008, 2327 .model_id = "Common KVM processor" 2328 }, 2329 { 2330 .name = "qemu32", 2331 .level = 4, 2332 .vendor = CPUID_VENDOR_INTEL, 2333 .family = 6, 2334 .model = 6, 2335 .stepping = 3, 2336 .features[FEAT_1_EDX] = 2337 PPRO_FEATURES, 2338 .features[FEAT_1_ECX] = 2339 CPUID_EXT_SSE3, 2340 .xlevel = 0x80000004, 2341 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2342 }, 2343 { 2344 .name = "kvm32", 2345 .level = 5, 2346 .vendor = CPUID_VENDOR_INTEL, 2347 .family = 15, 2348 .model = 6, 2349 .stepping = 1, 2350 .features[FEAT_1_EDX] = 2351 PPRO_FEATURES | CPUID_VME | 2352 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2353 .features[FEAT_1_ECX] = 2354 CPUID_EXT_SSE3, 2355 .features[FEAT_8000_0001_ECX] = 2356 0, 2357 /* VMX features from Yonah */ 2358 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2359 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2360 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2361 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2362 VMX_PIN_BASED_NMI_EXITING, 2363 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2364 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2365 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2366 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2367 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2368 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2369 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2370 .xlevel = 0x80000008, 2371 .model_id = "Common 32-bit KVM processor" 2372 }, 2373 { 2374 .name = "coreduo", 2375 .level = 10, 2376 .vendor = CPUID_VENDOR_INTEL, 2377 .family = 6, 2378 .model = 14, 2379 .stepping = 8, 2380 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2381 .features[FEAT_1_EDX] = 2382 PPRO_FEATURES | CPUID_VME | 2383 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2384 CPUID_SS, 2385 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2386 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2387 .features[FEAT_1_ECX] = 2388 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2389 .features[FEAT_8000_0001_EDX] = 2390 CPUID_EXT2_NX, 2391 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2392 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2393 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2394 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2395 VMX_PIN_BASED_NMI_EXITING, 2396 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2397 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2398 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2399 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2400 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2401 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2402 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2403 .xlevel = 0x80000008, 2404 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2405 }, 2406 { 2407 .name = "486", 2408 .level = 1, 2409 .vendor = CPUID_VENDOR_INTEL, 2410 .family = 4, 2411 .model = 8, 2412 .stepping = 0, 2413 .features[FEAT_1_EDX] = 2414 I486_FEATURES, 2415 .xlevel = 0, 2416 .model_id = "", 2417 }, 2418 { 2419 .name = "pentium", 2420 .level = 1, 2421 .vendor = CPUID_VENDOR_INTEL, 2422 .family = 5, 2423 .model = 4, 2424 .stepping = 3, 2425 .features[FEAT_1_EDX] = 2426 PENTIUM_FEATURES, 2427 .xlevel = 0, 2428 .model_id = "", 2429 }, 2430 { 2431 .name = "pentium2", 2432 .level = 2, 2433 .vendor = CPUID_VENDOR_INTEL, 2434 .family = 6, 2435 .model = 5, 2436 .stepping = 2, 2437 .features[FEAT_1_EDX] = 2438 PENTIUM2_FEATURES, 2439 .xlevel = 0, 2440 .model_id = "", 2441 }, 2442 { 2443 .name = "pentium3", 2444 .level = 3, 2445 .vendor = CPUID_VENDOR_INTEL, 2446 .family = 6, 2447 .model = 7, 2448 .stepping = 3, 2449 .features[FEAT_1_EDX] = 2450 PENTIUM3_FEATURES, 2451 .xlevel = 0, 2452 .model_id = "", 2453 }, 2454 { 2455 .name = "athlon", 2456 .level = 2, 2457 .vendor = CPUID_VENDOR_AMD, 2458 .family = 6, 2459 .model = 2, 2460 .stepping = 3, 2461 .features[FEAT_1_EDX] = 2462 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2463 CPUID_MCA, 2464 .features[FEAT_8000_0001_EDX] = 2465 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2466 .xlevel = 0x80000008, 2467 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2468 }, 2469 { 2470 .name = "n270", 2471 .level = 10, 2472 .vendor = CPUID_VENDOR_INTEL, 2473 .family = 6, 2474 .model = 28, 2475 .stepping = 2, 2476 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2477 .features[FEAT_1_EDX] = 2478 PPRO_FEATURES | 2479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2480 CPUID_ACPI | CPUID_SS, 2481 /* Some CPUs got no CPUID_SEP */ 2482 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2483 * CPUID_EXT_XTPR */ 2484 .features[FEAT_1_ECX] = 2485 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2486 CPUID_EXT_MOVBE, 2487 .features[FEAT_8000_0001_EDX] = 2488 CPUID_EXT2_NX, 2489 .features[FEAT_8000_0001_ECX] = 2490 CPUID_EXT3_LAHF_LM, 2491 .xlevel = 0x80000008, 2492 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2493 }, 2494 { 2495 .name = "Conroe", 2496 .level = 10, 2497 .vendor = CPUID_VENDOR_INTEL, 2498 .family = 6, 2499 .model = 15, 2500 .stepping = 3, 2501 .features[FEAT_1_EDX] = 2502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2506 CPUID_DE | CPUID_FP87, 2507 .features[FEAT_1_ECX] = 2508 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2509 .features[FEAT_8000_0001_EDX] = 2510 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2511 .features[FEAT_8000_0001_ECX] = 2512 CPUID_EXT3_LAHF_LM, 2513 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2514 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2515 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2516 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2517 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2518 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2519 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2520 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2521 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2522 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2523 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2524 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2525 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2526 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2527 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2528 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2529 .features[FEAT_VMX_SECONDARY_CTLS] = 2530 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2531 .xlevel = 0x80000008, 2532 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2533 }, 2534 { 2535 .name = "Penryn", 2536 .level = 10, 2537 .vendor = CPUID_VENDOR_INTEL, 2538 .family = 6, 2539 .model = 23, 2540 .stepping = 3, 2541 .features[FEAT_1_EDX] = 2542 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2543 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2544 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2545 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2546 CPUID_DE | CPUID_FP87, 2547 .features[FEAT_1_ECX] = 2548 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2549 CPUID_EXT_SSE3, 2550 .features[FEAT_8000_0001_EDX] = 2551 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2552 .features[FEAT_8000_0001_ECX] = 2553 CPUID_EXT3_LAHF_LM, 2554 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2555 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2556 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2557 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2558 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2559 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2560 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2561 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2562 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2563 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2564 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2565 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2566 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2567 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2568 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2569 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2570 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2571 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2572 .features[FEAT_VMX_SECONDARY_CTLS] = 2573 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2574 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2575 .xlevel = 0x80000008, 2576 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2577 }, 2578 { 2579 .name = "Nehalem", 2580 .level = 11, 2581 .vendor = CPUID_VENDOR_INTEL, 2582 .family = 6, 2583 .model = 26, 2584 .stepping = 3, 2585 .features[FEAT_1_EDX] = 2586 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2587 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2588 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2589 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2590 CPUID_DE | CPUID_FP87, 2591 .features[FEAT_1_ECX] = 2592 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2593 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2594 .features[FEAT_8000_0001_EDX] = 2595 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2596 .features[FEAT_8000_0001_ECX] = 2597 CPUID_EXT3_LAHF_LM, 2598 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2599 MSR_VMX_BASIC_TRUE_CTLS, 2600 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2601 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2602 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2603 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2604 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2605 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2606 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2607 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2608 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2609 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2610 .features[FEAT_VMX_EXIT_CTLS] = 2611 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2612 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2613 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2614 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2615 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2616 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2617 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2618 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2619 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2620 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2621 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2622 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2623 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2624 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2625 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2626 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2627 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2628 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2629 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2630 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2631 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2632 .features[FEAT_VMX_SECONDARY_CTLS] = 2633 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2634 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2635 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2636 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2637 VMX_SECONDARY_EXEC_ENABLE_VPID, 2638 .xlevel = 0x80000008, 2639 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2640 .versions = (X86CPUVersionDefinition[]) { 2641 { .version = 1 }, 2642 { 2643 .version = 2, 2644 .alias = "Nehalem-IBRS", 2645 .props = (PropValue[]) { 2646 { "spec-ctrl", "on" }, 2647 { "model-id", 2648 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2649 { /* end of list */ } 2650 } 2651 }, 2652 { /* end of list */ } 2653 } 2654 }, 2655 { 2656 .name = "Westmere", 2657 .level = 11, 2658 .vendor = CPUID_VENDOR_INTEL, 2659 .family = 6, 2660 .model = 44, 2661 .stepping = 1, 2662 .features[FEAT_1_EDX] = 2663 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2664 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2665 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2666 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2667 CPUID_DE | CPUID_FP87, 2668 .features[FEAT_1_ECX] = 2669 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2670 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2671 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2672 .features[FEAT_8000_0001_EDX] = 2673 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2674 .features[FEAT_8000_0001_ECX] = 2675 CPUID_EXT3_LAHF_LM, 2676 .features[FEAT_6_EAX] = 2677 CPUID_6_EAX_ARAT, 2678 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2679 MSR_VMX_BASIC_TRUE_CTLS, 2680 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2681 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2682 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2683 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2684 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2685 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2686 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2687 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2688 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2689 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2690 .features[FEAT_VMX_EXIT_CTLS] = 2691 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2692 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2693 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2694 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2695 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2696 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2697 MSR_VMX_MISC_STORE_LMA, 2698 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2699 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2700 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2701 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2702 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2703 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2704 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2705 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2706 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2707 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2708 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2709 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2710 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2711 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2712 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2713 .features[FEAT_VMX_SECONDARY_CTLS] = 2714 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2715 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2716 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2717 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2718 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2719 .xlevel = 0x80000008, 2720 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2721 .versions = (X86CPUVersionDefinition[]) { 2722 { .version = 1 }, 2723 { 2724 .version = 2, 2725 .alias = "Westmere-IBRS", 2726 .props = (PropValue[]) { 2727 { "spec-ctrl", "on" }, 2728 { "model-id", 2729 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2730 { /* end of list */ } 2731 } 2732 }, 2733 { /* end of list */ } 2734 } 2735 }, 2736 { 2737 .name = "SandyBridge", 2738 .level = 0xd, 2739 .vendor = CPUID_VENDOR_INTEL, 2740 .family = 6, 2741 .model = 42, 2742 .stepping = 1, 2743 .features[FEAT_1_EDX] = 2744 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2748 CPUID_DE | CPUID_FP87, 2749 .features[FEAT_1_ECX] = 2750 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2751 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2752 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2753 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2754 CPUID_EXT_SSE3, 2755 .features[FEAT_8000_0001_EDX] = 2756 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2757 CPUID_EXT2_SYSCALL, 2758 .features[FEAT_8000_0001_ECX] = 2759 CPUID_EXT3_LAHF_LM, 2760 .features[FEAT_XSAVE] = 2761 CPUID_XSAVE_XSAVEOPT, 2762 .features[FEAT_6_EAX] = 2763 CPUID_6_EAX_ARAT, 2764 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2765 MSR_VMX_BASIC_TRUE_CTLS, 2766 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2767 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2768 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2769 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2770 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2771 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2772 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2773 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2774 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2775 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2776 .features[FEAT_VMX_EXIT_CTLS] = 2777 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2778 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2779 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2780 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2781 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2782 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2783 MSR_VMX_MISC_STORE_LMA, 2784 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2785 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2786 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2787 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2788 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2789 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2790 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2791 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2792 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2793 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2794 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2795 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2796 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2797 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2798 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2799 .features[FEAT_VMX_SECONDARY_CTLS] = 2800 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2801 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2802 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2803 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2804 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2805 .xlevel = 0x80000008, 2806 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2807 .versions = (X86CPUVersionDefinition[]) { 2808 { .version = 1 }, 2809 { 2810 .version = 2, 2811 .alias = "SandyBridge-IBRS", 2812 .props = (PropValue[]) { 2813 { "spec-ctrl", "on" }, 2814 { "model-id", 2815 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2816 { /* end of list */ } 2817 } 2818 }, 2819 { /* end of list */ } 2820 } 2821 }, 2822 { 2823 .name = "IvyBridge", 2824 .level = 0xd, 2825 .vendor = CPUID_VENDOR_INTEL, 2826 .family = 6, 2827 .model = 58, 2828 .stepping = 9, 2829 .features[FEAT_1_EDX] = 2830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2834 CPUID_DE | CPUID_FP87, 2835 .features[FEAT_1_ECX] = 2836 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2837 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2838 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2839 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2840 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2841 .features[FEAT_7_0_EBX] = 2842 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2843 CPUID_7_0_EBX_ERMS, 2844 .features[FEAT_8000_0001_EDX] = 2845 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2846 CPUID_EXT2_SYSCALL, 2847 .features[FEAT_8000_0001_ECX] = 2848 CPUID_EXT3_LAHF_LM, 2849 .features[FEAT_XSAVE] = 2850 CPUID_XSAVE_XSAVEOPT, 2851 .features[FEAT_6_EAX] = 2852 CPUID_6_EAX_ARAT, 2853 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2854 MSR_VMX_BASIC_TRUE_CTLS, 2855 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2856 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2857 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2858 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2859 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2860 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2861 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2862 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2863 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2864 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2865 .features[FEAT_VMX_EXIT_CTLS] = 2866 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2867 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2868 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2869 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2870 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2871 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2872 MSR_VMX_MISC_STORE_LMA, 2873 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2874 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2875 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2876 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2877 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2878 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2879 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2880 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2881 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2882 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2883 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2884 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2885 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2886 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2887 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2888 .features[FEAT_VMX_SECONDARY_CTLS] = 2889 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2890 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2891 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2892 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2893 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2894 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2895 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2896 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2897 .xlevel = 0x80000008, 2898 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2899 .versions = (X86CPUVersionDefinition[]) { 2900 { .version = 1 }, 2901 { 2902 .version = 2, 2903 .alias = "IvyBridge-IBRS", 2904 .props = (PropValue[]) { 2905 { "spec-ctrl", "on" }, 2906 { "model-id", 2907 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2908 { /* end of list */ } 2909 } 2910 }, 2911 { /* end of list */ } 2912 } 2913 }, 2914 { 2915 .name = "Haswell", 2916 .level = 0xd, 2917 .vendor = CPUID_VENDOR_INTEL, 2918 .family = 6, 2919 .model = 60, 2920 .stepping = 4, 2921 .features[FEAT_1_EDX] = 2922 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2923 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2924 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2925 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2926 CPUID_DE | CPUID_FP87, 2927 .features[FEAT_1_ECX] = 2928 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2929 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2930 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2931 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2932 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2933 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2934 .features[FEAT_8000_0001_EDX] = 2935 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2936 CPUID_EXT2_SYSCALL, 2937 .features[FEAT_8000_0001_ECX] = 2938 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2939 .features[FEAT_7_0_EBX] = 2940 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2941 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2942 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2943 CPUID_7_0_EBX_RTM, 2944 .features[FEAT_XSAVE] = 2945 CPUID_XSAVE_XSAVEOPT, 2946 .features[FEAT_6_EAX] = 2947 CPUID_6_EAX_ARAT, 2948 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2949 MSR_VMX_BASIC_TRUE_CTLS, 2950 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2951 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2952 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2953 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2954 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2955 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2956 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2957 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2958 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2959 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2960 .features[FEAT_VMX_EXIT_CTLS] = 2961 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2962 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2963 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2964 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2965 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2966 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2967 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2968 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2969 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2970 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2971 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2972 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2973 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2974 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2975 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2976 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2977 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2978 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2979 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2980 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2981 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2982 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2983 .features[FEAT_VMX_SECONDARY_CTLS] = 2984 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2985 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2986 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2987 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2988 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2989 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2990 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2991 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2992 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2993 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2994 .xlevel = 0x80000008, 2995 .model_id = "Intel Core Processor (Haswell)", 2996 .versions = (X86CPUVersionDefinition[]) { 2997 { .version = 1 }, 2998 { 2999 .version = 2, 3000 .alias = "Haswell-noTSX", 3001 .props = (PropValue[]) { 3002 { "hle", "off" }, 3003 { "rtm", "off" }, 3004 { "stepping", "1" }, 3005 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3006 { /* end of list */ } 3007 }, 3008 }, 3009 { 3010 .version = 3, 3011 .alias = "Haswell-IBRS", 3012 .props = (PropValue[]) { 3013 /* Restore TSX features removed by -v2 above */ 3014 { "hle", "on" }, 3015 { "rtm", "on" }, 3016 /* 3017 * Haswell and Haswell-IBRS had stepping=4 in 3018 * QEMU 4.0 and older 3019 */ 3020 { "stepping", "4" }, 3021 { "spec-ctrl", "on" }, 3022 { "model-id", 3023 "Intel Core Processor (Haswell, IBRS)" }, 3024 { /* end of list */ } 3025 } 3026 }, 3027 { 3028 .version = 4, 3029 .alias = "Haswell-noTSX-IBRS", 3030 .props = (PropValue[]) { 3031 { "hle", "off" }, 3032 { "rtm", "off" }, 3033 /* spec-ctrl was already enabled by -v3 above */ 3034 { "stepping", "1" }, 3035 { "model-id", 3036 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3037 { /* end of list */ } 3038 } 3039 }, 3040 { /* end of list */ } 3041 } 3042 }, 3043 { 3044 .name = "Broadwell", 3045 .level = 0xd, 3046 .vendor = CPUID_VENDOR_INTEL, 3047 .family = 6, 3048 .model = 61, 3049 .stepping = 2, 3050 .features[FEAT_1_EDX] = 3051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3055 CPUID_DE | CPUID_FP87, 3056 .features[FEAT_1_ECX] = 3057 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3058 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3059 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3060 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3061 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3062 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3063 .features[FEAT_8000_0001_EDX] = 3064 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3065 CPUID_EXT2_SYSCALL, 3066 .features[FEAT_8000_0001_ECX] = 3067 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3068 .features[FEAT_7_0_EBX] = 3069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3070 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3071 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3072 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3073 CPUID_7_0_EBX_SMAP, 3074 .features[FEAT_XSAVE] = 3075 CPUID_XSAVE_XSAVEOPT, 3076 .features[FEAT_6_EAX] = 3077 CPUID_6_EAX_ARAT, 3078 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3079 MSR_VMX_BASIC_TRUE_CTLS, 3080 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3081 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3082 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3083 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3084 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3085 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3086 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3087 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3088 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3089 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3090 .features[FEAT_VMX_EXIT_CTLS] = 3091 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3092 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3093 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3094 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3095 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3096 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3097 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3098 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3099 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3100 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3101 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3102 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3103 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3104 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3105 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3106 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3107 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3108 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3109 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3110 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3111 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3112 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3113 .features[FEAT_VMX_SECONDARY_CTLS] = 3114 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3115 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3116 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3117 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3118 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3119 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3120 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3121 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3122 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3123 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3124 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3125 .xlevel = 0x80000008, 3126 .model_id = "Intel Core Processor (Broadwell)", 3127 .versions = (X86CPUVersionDefinition[]) { 3128 { .version = 1 }, 3129 { 3130 .version = 2, 3131 .alias = "Broadwell-noTSX", 3132 .props = (PropValue[]) { 3133 { "hle", "off" }, 3134 { "rtm", "off" }, 3135 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3136 { /* end of list */ } 3137 }, 3138 }, 3139 { 3140 .version = 3, 3141 .alias = "Broadwell-IBRS", 3142 .props = (PropValue[]) { 3143 /* Restore TSX features removed by -v2 above */ 3144 { "hle", "on" }, 3145 { "rtm", "on" }, 3146 { "spec-ctrl", "on" }, 3147 { "model-id", 3148 "Intel Core Processor (Broadwell, IBRS)" }, 3149 { /* end of list */ } 3150 } 3151 }, 3152 { 3153 .version = 4, 3154 .alias = "Broadwell-noTSX-IBRS", 3155 .props = (PropValue[]) { 3156 { "hle", "off" }, 3157 { "rtm", "off" }, 3158 /* spec-ctrl was already enabled by -v3 above */ 3159 { "model-id", 3160 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3161 { /* end of list */ } 3162 } 3163 }, 3164 { /* end of list */ } 3165 } 3166 }, 3167 { 3168 .name = "Skylake-Client", 3169 .level = 0xd, 3170 .vendor = CPUID_VENDOR_INTEL, 3171 .family = 6, 3172 .model = 94, 3173 .stepping = 3, 3174 .features[FEAT_1_EDX] = 3175 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3176 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3177 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3178 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3179 CPUID_DE | CPUID_FP87, 3180 .features[FEAT_1_ECX] = 3181 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3182 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3183 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3184 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3185 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3186 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3187 .features[FEAT_8000_0001_EDX] = 3188 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3189 CPUID_EXT2_SYSCALL, 3190 .features[FEAT_8000_0001_ECX] = 3191 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3192 .features[FEAT_7_0_EBX] = 3193 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3194 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3195 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3196 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3197 CPUID_7_0_EBX_SMAP, 3198 /* XSAVES is added in version 4 */ 3199 .features[FEAT_XSAVE] = 3200 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3201 CPUID_XSAVE_XGETBV1, 3202 .features[FEAT_6_EAX] = 3203 CPUID_6_EAX_ARAT, 3204 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3205 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3206 MSR_VMX_BASIC_TRUE_CTLS, 3207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3208 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3209 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3210 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3211 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3212 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3213 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3214 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3217 .features[FEAT_VMX_EXIT_CTLS] = 3218 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3219 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3220 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3221 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3222 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3223 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3224 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3225 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3226 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3227 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3228 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3229 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3230 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3231 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3232 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3233 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3234 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3235 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3236 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3237 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3238 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3239 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3240 .features[FEAT_VMX_SECONDARY_CTLS] = 3241 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3242 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3243 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3244 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3245 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3246 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3247 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3248 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3249 .xlevel = 0x80000008, 3250 .model_id = "Intel Core Processor (Skylake)", 3251 .versions = (X86CPUVersionDefinition[]) { 3252 { .version = 1 }, 3253 { 3254 .version = 2, 3255 .alias = "Skylake-Client-IBRS", 3256 .props = (PropValue[]) { 3257 { "spec-ctrl", "on" }, 3258 { "model-id", 3259 "Intel Core Processor (Skylake, IBRS)" }, 3260 { /* end of list */ } 3261 } 3262 }, 3263 { 3264 .version = 3, 3265 .alias = "Skylake-Client-noTSX-IBRS", 3266 .props = (PropValue[]) { 3267 { "hle", "off" }, 3268 { "rtm", "off" }, 3269 { "model-id", 3270 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3271 { /* end of list */ } 3272 } 3273 }, 3274 { 3275 .version = 4, 3276 .note = "IBRS, XSAVES, no TSX", 3277 .props = (PropValue[]) { 3278 { "xsaves", "on" }, 3279 { "vmx-xsaves", "on" }, 3280 { /* end of list */ } 3281 } 3282 }, 3283 { /* end of list */ } 3284 } 3285 }, 3286 { 3287 .name = "Skylake-Server", 3288 .level = 0xd, 3289 .vendor = CPUID_VENDOR_INTEL, 3290 .family = 6, 3291 .model = 85, 3292 .stepping = 4, 3293 .features[FEAT_1_EDX] = 3294 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3295 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3296 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3297 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3298 CPUID_DE | CPUID_FP87, 3299 .features[FEAT_1_ECX] = 3300 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3301 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3302 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3303 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3304 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3305 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3306 .features[FEAT_8000_0001_EDX] = 3307 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3308 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3309 .features[FEAT_8000_0001_ECX] = 3310 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3311 .features[FEAT_7_0_EBX] = 3312 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3313 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3314 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3315 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3316 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3317 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3318 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3319 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3320 .features[FEAT_7_0_ECX] = 3321 CPUID_7_0_ECX_PKU, 3322 /* XSAVES is added in version 5 */ 3323 .features[FEAT_XSAVE] = 3324 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3325 CPUID_XSAVE_XGETBV1, 3326 .features[FEAT_6_EAX] = 3327 CPUID_6_EAX_ARAT, 3328 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3329 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3330 MSR_VMX_BASIC_TRUE_CTLS, 3331 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3332 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3333 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3334 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3335 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3336 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3337 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3338 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3339 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3340 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3341 .features[FEAT_VMX_EXIT_CTLS] = 3342 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3343 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3344 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3345 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3346 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3347 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3348 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3349 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3350 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3351 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3352 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3353 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3354 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3355 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3356 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3357 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3358 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3359 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3360 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3361 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3362 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3363 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3364 .features[FEAT_VMX_SECONDARY_CTLS] = 3365 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3366 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3367 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3368 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3369 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3370 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3371 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3372 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3373 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3374 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3375 .xlevel = 0x80000008, 3376 .model_id = "Intel Xeon Processor (Skylake)", 3377 .versions = (X86CPUVersionDefinition[]) { 3378 { .version = 1 }, 3379 { 3380 .version = 2, 3381 .alias = "Skylake-Server-IBRS", 3382 .props = (PropValue[]) { 3383 /* clflushopt was not added to Skylake-Server-IBRS */ 3384 /* TODO: add -v3 including clflushopt */ 3385 { "clflushopt", "off" }, 3386 { "spec-ctrl", "on" }, 3387 { "model-id", 3388 "Intel Xeon Processor (Skylake, IBRS)" }, 3389 { /* end of list */ } 3390 } 3391 }, 3392 { 3393 .version = 3, 3394 .alias = "Skylake-Server-noTSX-IBRS", 3395 .props = (PropValue[]) { 3396 { "hle", "off" }, 3397 { "rtm", "off" }, 3398 { "model-id", 3399 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3400 { /* end of list */ } 3401 } 3402 }, 3403 { 3404 .version = 4, 3405 .props = (PropValue[]) { 3406 { "vmx-eptp-switching", "on" }, 3407 { /* end of list */ } 3408 } 3409 }, 3410 { 3411 .version = 5, 3412 .note = "IBRS, XSAVES, EPT switching, no TSX", 3413 .props = (PropValue[]) { 3414 { "xsaves", "on" }, 3415 { "vmx-xsaves", "on" }, 3416 { /* end of list */ } 3417 } 3418 }, 3419 { /* end of list */ } 3420 } 3421 }, 3422 { 3423 .name = "Cascadelake-Server", 3424 .level = 0xd, 3425 .vendor = CPUID_VENDOR_INTEL, 3426 .family = 6, 3427 .model = 85, 3428 .stepping = 6, 3429 .features[FEAT_1_EDX] = 3430 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3431 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3432 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3433 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3434 CPUID_DE | CPUID_FP87, 3435 .features[FEAT_1_ECX] = 3436 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3437 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3438 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3439 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3440 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3441 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3442 .features[FEAT_8000_0001_EDX] = 3443 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3444 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3445 .features[FEAT_8000_0001_ECX] = 3446 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3447 .features[FEAT_7_0_EBX] = 3448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3449 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3450 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3451 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3452 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3453 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3454 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3455 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3456 .features[FEAT_7_0_ECX] = 3457 CPUID_7_0_ECX_PKU | 3458 CPUID_7_0_ECX_AVX512VNNI, 3459 .features[FEAT_7_0_EDX] = 3460 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3461 /* XSAVES is added in version 5 */ 3462 .features[FEAT_XSAVE] = 3463 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3464 CPUID_XSAVE_XGETBV1, 3465 .features[FEAT_6_EAX] = 3466 CPUID_6_EAX_ARAT, 3467 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3468 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3469 MSR_VMX_BASIC_TRUE_CTLS, 3470 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3471 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3472 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3473 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3474 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3475 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3476 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3477 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3478 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3479 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3480 .features[FEAT_VMX_EXIT_CTLS] = 3481 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3482 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3483 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3484 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3485 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3486 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3487 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3488 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3489 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3490 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3491 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3492 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3493 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3494 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3495 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3496 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3497 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3498 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3499 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3500 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3501 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3502 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3503 .features[FEAT_VMX_SECONDARY_CTLS] = 3504 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3505 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3506 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3507 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3508 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3509 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3510 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3511 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3512 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3513 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3514 .xlevel = 0x80000008, 3515 .model_id = "Intel Xeon Processor (Cascadelake)", 3516 .versions = (X86CPUVersionDefinition[]) { 3517 { .version = 1 }, 3518 { .version = 2, 3519 .note = "ARCH_CAPABILITIES", 3520 .props = (PropValue[]) { 3521 { "arch-capabilities", "on" }, 3522 { "rdctl-no", "on" }, 3523 { "ibrs-all", "on" }, 3524 { "skip-l1dfl-vmentry", "on" }, 3525 { "mds-no", "on" }, 3526 { /* end of list */ } 3527 }, 3528 }, 3529 { .version = 3, 3530 .alias = "Cascadelake-Server-noTSX", 3531 .note = "ARCH_CAPABILITIES, no TSX", 3532 .props = (PropValue[]) { 3533 { "hle", "off" }, 3534 { "rtm", "off" }, 3535 { /* end of list */ } 3536 }, 3537 }, 3538 { .version = 4, 3539 .note = "ARCH_CAPABILITIES, no TSX", 3540 .props = (PropValue[]) { 3541 { "vmx-eptp-switching", "on" }, 3542 { /* end of list */ } 3543 }, 3544 }, 3545 { .version = 5, 3546 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3547 .props = (PropValue[]) { 3548 { "xsaves", "on" }, 3549 { "vmx-xsaves", "on" }, 3550 { /* end of list */ } 3551 }, 3552 }, 3553 { /* end of list */ } 3554 } 3555 }, 3556 { 3557 .name = "Cooperlake", 3558 .level = 0xd, 3559 .vendor = CPUID_VENDOR_INTEL, 3560 .family = 6, 3561 .model = 85, 3562 .stepping = 10, 3563 .features[FEAT_1_EDX] = 3564 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3565 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3566 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3567 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3568 CPUID_DE | CPUID_FP87, 3569 .features[FEAT_1_ECX] = 3570 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3571 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3572 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3573 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3574 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3575 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3576 .features[FEAT_8000_0001_EDX] = 3577 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3578 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3579 .features[FEAT_8000_0001_ECX] = 3580 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3581 .features[FEAT_7_0_EBX] = 3582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3586 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3587 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3588 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3589 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3590 .features[FEAT_7_0_ECX] = 3591 CPUID_7_0_ECX_PKU | 3592 CPUID_7_0_ECX_AVX512VNNI, 3593 .features[FEAT_7_0_EDX] = 3594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3595 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3596 .features[FEAT_ARCH_CAPABILITIES] = 3597 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3598 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3599 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3600 .features[FEAT_7_1_EAX] = 3601 CPUID_7_1_EAX_AVX512_BF16, 3602 /* XSAVES is added in version 2 */ 3603 .features[FEAT_XSAVE] = 3604 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3605 CPUID_XSAVE_XGETBV1, 3606 .features[FEAT_6_EAX] = 3607 CPUID_6_EAX_ARAT, 3608 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3609 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3610 MSR_VMX_BASIC_TRUE_CTLS, 3611 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3612 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3613 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3614 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3615 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3616 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3617 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3618 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3619 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3620 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3621 .features[FEAT_VMX_EXIT_CTLS] = 3622 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3623 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3624 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3625 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3626 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3627 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3628 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3629 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3630 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3631 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3632 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3633 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3634 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3635 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3636 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3637 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3638 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3639 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3640 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3641 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3642 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3643 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3644 .features[FEAT_VMX_SECONDARY_CTLS] = 3645 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3646 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3647 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3648 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3649 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3650 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3651 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3652 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3653 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3654 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3655 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3656 .xlevel = 0x80000008, 3657 .model_id = "Intel Xeon Processor (Cooperlake)", 3658 .versions = (X86CPUVersionDefinition[]) { 3659 { .version = 1 }, 3660 { .version = 2, 3661 .note = "XSAVES", 3662 .props = (PropValue[]) { 3663 { "xsaves", "on" }, 3664 { "vmx-xsaves", "on" }, 3665 { /* end of list */ } 3666 }, 3667 }, 3668 { /* end of list */ } 3669 } 3670 }, 3671 { 3672 .name = "Icelake-Server", 3673 .level = 0xd, 3674 .vendor = CPUID_VENDOR_INTEL, 3675 .family = 6, 3676 .model = 134, 3677 .stepping = 0, 3678 .features[FEAT_1_EDX] = 3679 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3683 CPUID_DE | CPUID_FP87, 3684 .features[FEAT_1_ECX] = 3685 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3686 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3687 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3688 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3690 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3691 .features[FEAT_8000_0001_EDX] = 3692 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3693 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3694 .features[FEAT_8000_0001_ECX] = 3695 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3696 .features[FEAT_8000_0008_EBX] = 3697 CPUID_8000_0008_EBX_WBNOINVD, 3698 .features[FEAT_7_0_EBX] = 3699 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3700 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3701 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3702 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3703 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3704 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3705 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3706 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3707 .features[FEAT_7_0_ECX] = 3708 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3709 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3710 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3711 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3712 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3713 .features[FEAT_7_0_EDX] = 3714 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3715 /* XSAVES is added in version 5 */ 3716 .features[FEAT_XSAVE] = 3717 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3718 CPUID_XSAVE_XGETBV1, 3719 .features[FEAT_6_EAX] = 3720 CPUID_6_EAX_ARAT, 3721 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3722 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3723 MSR_VMX_BASIC_TRUE_CTLS, 3724 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3725 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3726 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3727 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3728 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3729 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3730 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3731 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3732 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3733 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3734 .features[FEAT_VMX_EXIT_CTLS] = 3735 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3736 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3737 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3738 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3739 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3740 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3741 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3742 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3743 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3744 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3745 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3746 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3747 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3748 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3749 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3750 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3751 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3752 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3753 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3754 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3755 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3756 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3757 .features[FEAT_VMX_SECONDARY_CTLS] = 3758 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3759 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3760 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3761 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3762 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3763 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3764 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3765 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3766 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3767 .xlevel = 0x80000008, 3768 .model_id = "Intel Xeon Processor (Icelake)", 3769 .versions = (X86CPUVersionDefinition[]) { 3770 { .version = 1 }, 3771 { 3772 .version = 2, 3773 .note = "no TSX", 3774 .alias = "Icelake-Server-noTSX", 3775 .props = (PropValue[]) { 3776 { "hle", "off" }, 3777 { "rtm", "off" }, 3778 { /* end of list */ } 3779 }, 3780 }, 3781 { 3782 .version = 3, 3783 .props = (PropValue[]) { 3784 { "arch-capabilities", "on" }, 3785 { "rdctl-no", "on" }, 3786 { "ibrs-all", "on" }, 3787 { "skip-l1dfl-vmentry", "on" }, 3788 { "mds-no", "on" }, 3789 { "pschange-mc-no", "on" }, 3790 { "taa-no", "on" }, 3791 { /* end of list */ } 3792 }, 3793 }, 3794 { 3795 .version = 4, 3796 .props = (PropValue[]) { 3797 { "sha-ni", "on" }, 3798 { "avx512ifma", "on" }, 3799 { "rdpid", "on" }, 3800 { "fsrm", "on" }, 3801 { "vmx-rdseed-exit", "on" }, 3802 { "vmx-pml", "on" }, 3803 { "vmx-eptp-switching", "on" }, 3804 { "model", "106" }, 3805 { /* end of list */ } 3806 }, 3807 }, 3808 { 3809 .version = 5, 3810 .note = "XSAVES", 3811 .props = (PropValue[]) { 3812 { "xsaves", "on" }, 3813 { "vmx-xsaves", "on" }, 3814 { /* end of list */ } 3815 }, 3816 }, 3817 { 3818 .version = 6, 3819 .note = "5-level EPT", 3820 .props = (PropValue[]) { 3821 { "vmx-page-walk-5", "on" }, 3822 { /* end of list */ } 3823 }, 3824 }, 3825 { 3826 .version = 7, 3827 .note = "TSX, taa-no", 3828 .props = (PropValue[]) { 3829 /* Restore TSX features removed by -v2 above */ 3830 { "hle", "on" }, 3831 { "rtm", "on" }, 3832 { /* end of list */ } 3833 }, 3834 }, 3835 { /* end of list */ } 3836 } 3837 }, 3838 { 3839 .name = "SapphireRapids", 3840 .level = 0x20, 3841 .vendor = CPUID_VENDOR_INTEL, 3842 .family = 6, 3843 .model = 143, 3844 .stepping = 4, 3845 /* 3846 * please keep the ascending order so that we can have a clear view of 3847 * bit position of each feature. 3848 */ 3849 .features[FEAT_1_EDX] = 3850 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3851 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3852 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3853 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3854 CPUID_SSE | CPUID_SSE2, 3855 .features[FEAT_1_ECX] = 3856 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3857 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3858 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3859 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3860 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3861 .features[FEAT_8000_0001_EDX] = 3862 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3863 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3864 .features[FEAT_8000_0001_ECX] = 3865 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 3866 .features[FEAT_8000_0008_EBX] = 3867 CPUID_8000_0008_EBX_WBNOINVD, 3868 .features[FEAT_7_0_EBX] = 3869 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 3870 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 3871 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 3872 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3873 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 3874 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 3875 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 3876 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 3877 .features[FEAT_7_0_ECX] = 3878 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3879 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3880 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3881 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3882 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 3883 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 3884 .features[FEAT_7_0_EDX] = 3885 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 3886 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 3887 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 3888 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 3889 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3890 .features[FEAT_ARCH_CAPABILITIES] = 3891 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3892 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3893 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3894 .features[FEAT_XSAVE] = 3895 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3896 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 3897 .features[FEAT_6_EAX] = 3898 CPUID_6_EAX_ARAT, 3899 .features[FEAT_7_1_EAX] = 3900 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 3901 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 3902 .features[FEAT_VMX_BASIC] = 3903 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 3904 .features[FEAT_VMX_ENTRY_CTLS] = 3905 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 3906 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 3907 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 3908 .features[FEAT_VMX_EPT_VPID_CAPS] = 3909 MSR_VMX_EPT_EXECONLY | 3910 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 3911 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 3912 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 3913 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3914 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3915 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 3916 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3917 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3918 .features[FEAT_VMX_EXIT_CTLS] = 3919 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3920 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3921 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 3922 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3923 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3924 .features[FEAT_VMX_MISC] = 3925 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 3926 MSR_VMX_MISC_VMWRITE_VMEXIT, 3927 .features[FEAT_VMX_PINBASED_CTLS] = 3928 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 3929 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 3930 VMX_PIN_BASED_POSTED_INTR, 3931 .features[FEAT_VMX_PROCBASED_CTLS] = 3932 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3933 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3934 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3935 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3936 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3937 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3938 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 3939 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3940 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3941 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3942 VMX_CPU_BASED_PAUSE_EXITING | 3943 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3944 .features[FEAT_VMX_SECONDARY_CTLS] = 3945 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3946 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 3947 VMX_SECONDARY_EXEC_RDTSCP | 3948 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3949 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 3950 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3951 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3952 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3953 VMX_SECONDARY_EXEC_RDRAND_EXITING | 3954 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3955 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3956 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 3957 VMX_SECONDARY_EXEC_XSAVES, 3958 .features[FEAT_VMX_VMFUNC] = 3959 MSR_VMX_VMFUNC_EPT_SWITCHING, 3960 .xlevel = 0x80000008, 3961 .model_id = "Intel Xeon Processor (SapphireRapids)", 3962 .versions = (X86CPUVersionDefinition[]) { 3963 { .version = 1 }, 3964 { 3965 .version = 2, 3966 .props = (PropValue[]) { 3967 { "sbdr-ssdp-no", "on" }, 3968 { "fbsdp-no", "on" }, 3969 { "psdp-no", "on" }, 3970 { /* end of list */ } 3971 } 3972 }, 3973 { /* end of list */ } 3974 } 3975 }, 3976 { 3977 .name = "GraniteRapids", 3978 .level = 0x20, 3979 .vendor = CPUID_VENDOR_INTEL, 3980 .family = 6, 3981 .model = 173, 3982 .stepping = 0, 3983 /* 3984 * please keep the ascending order so that we can have a clear view of 3985 * bit position of each feature. 3986 */ 3987 .features[FEAT_1_EDX] = 3988 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3989 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3990 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3991 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3992 CPUID_SSE | CPUID_SSE2, 3993 .features[FEAT_1_ECX] = 3994 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3995 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3996 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3997 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3998 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3999 .features[FEAT_8000_0001_EDX] = 4000 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4001 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4002 .features[FEAT_8000_0001_ECX] = 4003 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4004 .features[FEAT_8000_0008_EBX] = 4005 CPUID_8000_0008_EBX_WBNOINVD, 4006 .features[FEAT_7_0_EBX] = 4007 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4008 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4009 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4010 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4011 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4012 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4013 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4014 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4015 .features[FEAT_7_0_ECX] = 4016 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4017 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4018 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4019 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4020 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4021 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4022 .features[FEAT_7_0_EDX] = 4023 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4024 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4025 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4026 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4027 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4028 .features[FEAT_ARCH_CAPABILITIES] = 4029 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4030 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4031 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4032 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4033 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4034 .features[FEAT_XSAVE] = 4035 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4036 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4037 .features[FEAT_6_EAX] = 4038 CPUID_6_EAX_ARAT, 4039 .features[FEAT_7_1_EAX] = 4040 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4041 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4042 CPUID_7_1_EAX_AMX_FP16, 4043 .features[FEAT_7_1_EDX] = 4044 CPUID_7_1_EDX_PREFETCHITI, 4045 .features[FEAT_7_2_EDX] = 4046 CPUID_7_2_EDX_MCDT_NO, 4047 .features[FEAT_VMX_BASIC] = 4048 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4049 .features[FEAT_VMX_ENTRY_CTLS] = 4050 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4051 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4052 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4053 .features[FEAT_VMX_EPT_VPID_CAPS] = 4054 MSR_VMX_EPT_EXECONLY | 4055 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4056 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4057 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4058 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4059 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4060 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4061 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4062 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4063 .features[FEAT_VMX_EXIT_CTLS] = 4064 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4065 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4066 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4067 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4068 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4069 .features[FEAT_VMX_MISC] = 4070 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4071 MSR_VMX_MISC_VMWRITE_VMEXIT, 4072 .features[FEAT_VMX_PINBASED_CTLS] = 4073 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4074 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4075 VMX_PIN_BASED_POSTED_INTR, 4076 .features[FEAT_VMX_PROCBASED_CTLS] = 4077 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4078 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4079 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4080 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4081 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4082 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4083 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4084 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4085 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4086 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4087 VMX_CPU_BASED_PAUSE_EXITING | 4088 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4089 .features[FEAT_VMX_SECONDARY_CTLS] = 4090 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4091 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4092 VMX_SECONDARY_EXEC_RDTSCP | 4093 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4094 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4095 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4096 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4097 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4098 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4099 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4100 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4101 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4102 VMX_SECONDARY_EXEC_XSAVES, 4103 .features[FEAT_VMX_VMFUNC] = 4104 MSR_VMX_VMFUNC_EPT_SWITCHING, 4105 .xlevel = 0x80000008, 4106 .model_id = "Intel Xeon Processor (GraniteRapids)", 4107 .versions = (X86CPUVersionDefinition[]) { 4108 { .version = 1 }, 4109 { /* end of list */ }, 4110 }, 4111 }, 4112 { 4113 .name = "SierraForest", 4114 .level = 0x23, 4115 .vendor = CPUID_VENDOR_INTEL, 4116 .family = 6, 4117 .model = 175, 4118 .stepping = 0, 4119 /* 4120 * please keep the ascending order so that we can have a clear view of 4121 * bit position of each feature. 4122 */ 4123 .features[FEAT_1_EDX] = 4124 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4125 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4126 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4127 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4128 CPUID_SSE | CPUID_SSE2, 4129 .features[FEAT_1_ECX] = 4130 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4131 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4132 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4133 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4134 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4135 .features[FEAT_8000_0001_EDX] = 4136 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4137 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4138 .features[FEAT_8000_0001_ECX] = 4139 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4140 .features[FEAT_8000_0008_EBX] = 4141 CPUID_8000_0008_EBX_WBNOINVD, 4142 .features[FEAT_7_0_EBX] = 4143 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4144 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4145 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4146 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4147 CPUID_7_0_EBX_SHA_NI, 4148 .features[FEAT_7_0_ECX] = 4149 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4150 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4151 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4152 .features[FEAT_7_0_EDX] = 4153 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4154 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4155 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4156 .features[FEAT_ARCH_CAPABILITIES] = 4157 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4158 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4159 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4160 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4161 MSR_ARCH_CAP_PBRSB_NO, 4162 .features[FEAT_XSAVE] = 4163 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4164 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4165 .features[FEAT_6_EAX] = 4166 CPUID_6_EAX_ARAT, 4167 .features[FEAT_7_1_EAX] = 4168 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4169 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4170 .features[FEAT_7_1_EDX] = 4171 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4172 .features[FEAT_7_2_EDX] = 4173 CPUID_7_2_EDX_MCDT_NO, 4174 .features[FEAT_VMX_BASIC] = 4175 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4176 .features[FEAT_VMX_ENTRY_CTLS] = 4177 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4178 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4179 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4180 .features[FEAT_VMX_EPT_VPID_CAPS] = 4181 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4182 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4183 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4184 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4185 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4186 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4187 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4188 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4189 .features[FEAT_VMX_EXIT_CTLS] = 4190 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4191 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4192 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4193 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4194 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4195 .features[FEAT_VMX_MISC] = 4196 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4197 MSR_VMX_MISC_VMWRITE_VMEXIT, 4198 .features[FEAT_VMX_PINBASED_CTLS] = 4199 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4200 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4201 VMX_PIN_BASED_POSTED_INTR, 4202 .features[FEAT_VMX_PROCBASED_CTLS] = 4203 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4204 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4205 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4206 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4207 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4208 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4209 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4210 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4211 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4212 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4213 VMX_CPU_BASED_PAUSE_EXITING | 4214 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4215 .features[FEAT_VMX_SECONDARY_CTLS] = 4216 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4217 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4218 VMX_SECONDARY_EXEC_RDTSCP | 4219 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4220 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4221 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4222 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4223 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4224 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4225 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4226 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4227 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4228 VMX_SECONDARY_EXEC_XSAVES, 4229 .features[FEAT_VMX_VMFUNC] = 4230 MSR_VMX_VMFUNC_EPT_SWITCHING, 4231 .xlevel = 0x80000008, 4232 .model_id = "Intel Xeon Processor (SierraForest)", 4233 .versions = (X86CPUVersionDefinition[]) { 4234 { .version = 1 }, 4235 { /* end of list */ }, 4236 }, 4237 }, 4238 { 4239 .name = "Denverton", 4240 .level = 21, 4241 .vendor = CPUID_VENDOR_INTEL, 4242 .family = 6, 4243 .model = 95, 4244 .stepping = 1, 4245 .features[FEAT_1_EDX] = 4246 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4247 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4248 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4249 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4250 CPUID_SSE | CPUID_SSE2, 4251 .features[FEAT_1_ECX] = 4252 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4253 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4254 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4255 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4256 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4257 .features[FEAT_8000_0001_EDX] = 4258 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4259 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4260 .features[FEAT_8000_0001_ECX] = 4261 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4262 .features[FEAT_7_0_EBX] = 4263 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4264 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4265 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4266 .features[FEAT_7_0_EDX] = 4267 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4268 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4269 /* XSAVES is added in version 3 */ 4270 .features[FEAT_XSAVE] = 4271 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4272 .features[FEAT_6_EAX] = 4273 CPUID_6_EAX_ARAT, 4274 .features[FEAT_ARCH_CAPABILITIES] = 4275 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4276 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4277 MSR_VMX_BASIC_TRUE_CTLS, 4278 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4279 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4280 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4281 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4282 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4283 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4284 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4285 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4286 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4287 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4288 .features[FEAT_VMX_EXIT_CTLS] = 4289 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4290 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4291 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4292 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4293 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4294 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4295 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4296 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4297 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4298 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4299 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4300 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4301 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4302 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4303 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4304 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4305 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4306 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4307 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4308 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4309 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4310 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4311 .features[FEAT_VMX_SECONDARY_CTLS] = 4312 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4313 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4314 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4315 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4316 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4317 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4318 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4319 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4320 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4321 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4322 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4323 .xlevel = 0x80000008, 4324 .model_id = "Intel Atom Processor (Denverton)", 4325 .versions = (X86CPUVersionDefinition[]) { 4326 { .version = 1 }, 4327 { 4328 .version = 2, 4329 .note = "no MPX, no MONITOR", 4330 .props = (PropValue[]) { 4331 { "monitor", "off" }, 4332 { "mpx", "off" }, 4333 { /* end of list */ }, 4334 }, 4335 }, 4336 { 4337 .version = 3, 4338 .note = "XSAVES, no MPX, no MONITOR", 4339 .props = (PropValue[]) { 4340 { "xsaves", "on" }, 4341 { "vmx-xsaves", "on" }, 4342 { /* end of list */ }, 4343 }, 4344 }, 4345 { /* end of list */ }, 4346 }, 4347 }, 4348 { 4349 .name = "Snowridge", 4350 .level = 27, 4351 .vendor = CPUID_VENDOR_INTEL, 4352 .family = 6, 4353 .model = 134, 4354 .stepping = 1, 4355 .features[FEAT_1_EDX] = 4356 /* missing: CPUID_PN CPUID_IA64 */ 4357 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4358 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4359 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4360 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4361 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4362 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4363 CPUID_MMX | 4364 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4365 .features[FEAT_1_ECX] = 4366 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4367 CPUID_EXT_SSSE3 | 4368 CPUID_EXT_CX16 | 4369 CPUID_EXT_SSE41 | 4370 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4371 CPUID_EXT_POPCNT | 4372 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4373 CPUID_EXT_RDRAND, 4374 .features[FEAT_8000_0001_EDX] = 4375 CPUID_EXT2_SYSCALL | 4376 CPUID_EXT2_NX | 4377 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4378 CPUID_EXT2_LM, 4379 .features[FEAT_8000_0001_ECX] = 4380 CPUID_EXT3_LAHF_LM | 4381 CPUID_EXT3_3DNOWPREFETCH, 4382 .features[FEAT_7_0_EBX] = 4383 CPUID_7_0_EBX_FSGSBASE | 4384 CPUID_7_0_EBX_SMEP | 4385 CPUID_7_0_EBX_ERMS | 4386 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4387 CPUID_7_0_EBX_RDSEED | 4388 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4389 CPUID_7_0_EBX_CLWB | 4390 CPUID_7_0_EBX_SHA_NI, 4391 .features[FEAT_7_0_ECX] = 4392 CPUID_7_0_ECX_UMIP | 4393 /* missing bit 5 */ 4394 CPUID_7_0_ECX_GFNI | 4395 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4396 CPUID_7_0_ECX_MOVDIR64B, 4397 .features[FEAT_7_0_EDX] = 4398 CPUID_7_0_EDX_SPEC_CTRL | 4399 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4400 CPUID_7_0_EDX_CORE_CAPABILITY, 4401 .features[FEAT_CORE_CAPABILITY] = 4402 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4403 /* XSAVES is added in version 3 */ 4404 .features[FEAT_XSAVE] = 4405 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4406 CPUID_XSAVE_XGETBV1, 4407 .features[FEAT_6_EAX] = 4408 CPUID_6_EAX_ARAT, 4409 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4410 MSR_VMX_BASIC_TRUE_CTLS, 4411 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4412 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4413 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4414 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4415 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4416 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4417 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4418 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4419 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4420 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4421 .features[FEAT_VMX_EXIT_CTLS] = 4422 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4423 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4424 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4425 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4426 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4427 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4428 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4429 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4430 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4431 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4432 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4433 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4434 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4435 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4436 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4437 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4438 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4439 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4440 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4441 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4442 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4443 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4444 .features[FEAT_VMX_SECONDARY_CTLS] = 4445 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4446 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4447 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4448 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4449 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4450 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4451 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4452 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4453 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4454 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4455 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4456 .xlevel = 0x80000008, 4457 .model_id = "Intel Atom Processor (SnowRidge)", 4458 .versions = (X86CPUVersionDefinition[]) { 4459 { .version = 1 }, 4460 { 4461 .version = 2, 4462 .props = (PropValue[]) { 4463 { "mpx", "off" }, 4464 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4465 { /* end of list */ }, 4466 }, 4467 }, 4468 { 4469 .version = 3, 4470 .note = "XSAVES, no MPX", 4471 .props = (PropValue[]) { 4472 { "xsaves", "on" }, 4473 { "vmx-xsaves", "on" }, 4474 { /* end of list */ }, 4475 }, 4476 }, 4477 { 4478 .version = 4, 4479 .note = "no split lock detect, no core-capability", 4480 .props = (PropValue[]) { 4481 { "split-lock-detect", "off" }, 4482 { "core-capability", "off" }, 4483 { /* end of list */ }, 4484 }, 4485 }, 4486 { /* end of list */ }, 4487 }, 4488 }, 4489 { 4490 .name = "KnightsMill", 4491 .level = 0xd, 4492 .vendor = CPUID_VENDOR_INTEL, 4493 .family = 6, 4494 .model = 133, 4495 .stepping = 0, 4496 .features[FEAT_1_EDX] = 4497 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4498 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4499 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4500 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4501 CPUID_PSE | CPUID_DE | CPUID_FP87, 4502 .features[FEAT_1_ECX] = 4503 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4504 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4505 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4506 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4507 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4508 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4509 .features[FEAT_8000_0001_EDX] = 4510 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4511 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4512 .features[FEAT_8000_0001_ECX] = 4513 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4514 .features[FEAT_7_0_EBX] = 4515 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4516 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4517 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4518 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4519 CPUID_7_0_EBX_AVX512ER, 4520 .features[FEAT_7_0_ECX] = 4521 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4522 .features[FEAT_7_0_EDX] = 4523 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4524 .features[FEAT_XSAVE] = 4525 CPUID_XSAVE_XSAVEOPT, 4526 .features[FEAT_6_EAX] = 4527 CPUID_6_EAX_ARAT, 4528 .xlevel = 0x80000008, 4529 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4530 }, 4531 { 4532 .name = "Opteron_G1", 4533 .level = 5, 4534 .vendor = CPUID_VENDOR_AMD, 4535 .family = 15, 4536 .model = 6, 4537 .stepping = 1, 4538 .features[FEAT_1_EDX] = 4539 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4540 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4541 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4542 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4543 CPUID_DE | CPUID_FP87, 4544 .features[FEAT_1_ECX] = 4545 CPUID_EXT_SSE3, 4546 .features[FEAT_8000_0001_EDX] = 4547 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4548 .xlevel = 0x80000008, 4549 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4550 }, 4551 { 4552 .name = "Opteron_G2", 4553 .level = 5, 4554 .vendor = CPUID_VENDOR_AMD, 4555 .family = 15, 4556 .model = 6, 4557 .stepping = 1, 4558 .features[FEAT_1_EDX] = 4559 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4560 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4561 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4562 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4563 CPUID_DE | CPUID_FP87, 4564 .features[FEAT_1_ECX] = 4565 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4566 .features[FEAT_8000_0001_EDX] = 4567 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4568 .features[FEAT_8000_0001_ECX] = 4569 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4570 .xlevel = 0x80000008, 4571 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4572 }, 4573 { 4574 .name = "Opteron_G3", 4575 .level = 5, 4576 .vendor = CPUID_VENDOR_AMD, 4577 .family = 16, 4578 .model = 2, 4579 .stepping = 3, 4580 .features[FEAT_1_EDX] = 4581 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4582 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4583 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4584 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4585 CPUID_DE | CPUID_FP87, 4586 .features[FEAT_1_ECX] = 4587 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4588 CPUID_EXT_SSE3, 4589 .features[FEAT_8000_0001_EDX] = 4590 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4591 CPUID_EXT2_RDTSCP, 4592 .features[FEAT_8000_0001_ECX] = 4593 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4594 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4595 .xlevel = 0x80000008, 4596 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4597 }, 4598 { 4599 .name = "Opteron_G4", 4600 .level = 0xd, 4601 .vendor = CPUID_VENDOR_AMD, 4602 .family = 21, 4603 .model = 1, 4604 .stepping = 2, 4605 .features[FEAT_1_EDX] = 4606 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4607 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4608 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4609 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4610 CPUID_DE | CPUID_FP87, 4611 .features[FEAT_1_ECX] = 4612 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4613 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4614 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4615 CPUID_EXT_SSE3, 4616 .features[FEAT_8000_0001_EDX] = 4617 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4618 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4619 .features[FEAT_8000_0001_ECX] = 4620 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4621 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4622 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4623 CPUID_EXT3_LAHF_LM, 4624 .features[FEAT_SVM] = 4625 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4626 /* no xsaveopt! */ 4627 .xlevel = 0x8000001A, 4628 .model_id = "AMD Opteron 62xx class CPU", 4629 }, 4630 { 4631 .name = "Opteron_G5", 4632 .level = 0xd, 4633 .vendor = CPUID_VENDOR_AMD, 4634 .family = 21, 4635 .model = 2, 4636 .stepping = 0, 4637 .features[FEAT_1_EDX] = 4638 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4639 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4640 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4641 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4642 CPUID_DE | CPUID_FP87, 4643 .features[FEAT_1_ECX] = 4644 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4645 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4646 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4647 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4648 .features[FEAT_8000_0001_EDX] = 4649 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4650 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4651 .features[FEAT_8000_0001_ECX] = 4652 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4653 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4654 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4655 CPUID_EXT3_LAHF_LM, 4656 .features[FEAT_SVM] = 4657 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4658 /* no xsaveopt! */ 4659 .xlevel = 0x8000001A, 4660 .model_id = "AMD Opteron 63xx class CPU", 4661 }, 4662 { 4663 .name = "EPYC", 4664 .level = 0xd, 4665 .vendor = CPUID_VENDOR_AMD, 4666 .family = 23, 4667 .model = 1, 4668 .stepping = 2, 4669 .features[FEAT_1_EDX] = 4670 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4671 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4672 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4673 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4674 CPUID_VME | CPUID_FP87, 4675 .features[FEAT_1_ECX] = 4676 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4677 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4678 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4679 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4680 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4681 .features[FEAT_8000_0001_EDX] = 4682 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4683 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4684 CPUID_EXT2_SYSCALL, 4685 .features[FEAT_8000_0001_ECX] = 4686 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4687 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4688 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4689 CPUID_EXT3_TOPOEXT, 4690 .features[FEAT_7_0_EBX] = 4691 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4692 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4693 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4694 CPUID_7_0_EBX_SHA_NI, 4695 .features[FEAT_XSAVE] = 4696 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4697 CPUID_XSAVE_XGETBV1, 4698 .features[FEAT_6_EAX] = 4699 CPUID_6_EAX_ARAT, 4700 .features[FEAT_SVM] = 4701 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4702 .xlevel = 0x8000001E, 4703 .model_id = "AMD EPYC Processor", 4704 .cache_info = &epyc_cache_info, 4705 .versions = (X86CPUVersionDefinition[]) { 4706 { .version = 1 }, 4707 { 4708 .version = 2, 4709 .alias = "EPYC-IBPB", 4710 .props = (PropValue[]) { 4711 { "ibpb", "on" }, 4712 { "model-id", 4713 "AMD EPYC Processor (with IBPB)" }, 4714 { /* end of list */ } 4715 } 4716 }, 4717 { 4718 .version = 3, 4719 .props = (PropValue[]) { 4720 { "ibpb", "on" }, 4721 { "perfctr-core", "on" }, 4722 { "clzero", "on" }, 4723 { "xsaveerptr", "on" }, 4724 { "xsaves", "on" }, 4725 { "model-id", 4726 "AMD EPYC Processor" }, 4727 { /* end of list */ } 4728 } 4729 }, 4730 { 4731 .version = 4, 4732 .props = (PropValue[]) { 4733 { "model-id", 4734 "AMD EPYC-v4 Processor" }, 4735 { /* end of list */ } 4736 }, 4737 .cache_info = &epyc_v4_cache_info 4738 }, 4739 { /* end of list */ } 4740 } 4741 }, 4742 { 4743 .name = "Dhyana", 4744 .level = 0xd, 4745 .vendor = CPUID_VENDOR_HYGON, 4746 .family = 24, 4747 .model = 0, 4748 .stepping = 1, 4749 .features[FEAT_1_EDX] = 4750 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4751 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4752 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4753 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4754 CPUID_VME | CPUID_FP87, 4755 .features[FEAT_1_ECX] = 4756 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4757 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4758 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4759 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4760 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4761 .features[FEAT_8000_0001_EDX] = 4762 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4763 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4764 CPUID_EXT2_SYSCALL, 4765 .features[FEAT_8000_0001_ECX] = 4766 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4767 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4768 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4769 CPUID_EXT3_TOPOEXT, 4770 .features[FEAT_8000_0008_EBX] = 4771 CPUID_8000_0008_EBX_IBPB, 4772 .features[FEAT_7_0_EBX] = 4773 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4774 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4775 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4776 /* XSAVES is added in version 2 */ 4777 .features[FEAT_XSAVE] = 4778 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4779 CPUID_XSAVE_XGETBV1, 4780 .features[FEAT_6_EAX] = 4781 CPUID_6_EAX_ARAT, 4782 .features[FEAT_SVM] = 4783 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4784 .xlevel = 0x8000001E, 4785 .model_id = "Hygon Dhyana Processor", 4786 .cache_info = &epyc_cache_info, 4787 .versions = (X86CPUVersionDefinition[]) { 4788 { .version = 1 }, 4789 { .version = 2, 4790 .note = "XSAVES", 4791 .props = (PropValue[]) { 4792 { "xsaves", "on" }, 4793 { /* end of list */ } 4794 }, 4795 }, 4796 { /* end of list */ } 4797 } 4798 }, 4799 { 4800 .name = "EPYC-Rome", 4801 .level = 0xd, 4802 .vendor = CPUID_VENDOR_AMD, 4803 .family = 23, 4804 .model = 49, 4805 .stepping = 0, 4806 .features[FEAT_1_EDX] = 4807 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4808 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4809 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4810 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4811 CPUID_VME | CPUID_FP87, 4812 .features[FEAT_1_ECX] = 4813 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4814 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4815 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4816 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4817 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4818 .features[FEAT_8000_0001_EDX] = 4819 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4820 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4821 CPUID_EXT2_SYSCALL, 4822 .features[FEAT_8000_0001_ECX] = 4823 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4824 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4825 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4826 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4827 .features[FEAT_8000_0008_EBX] = 4828 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4829 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4830 CPUID_8000_0008_EBX_STIBP, 4831 .features[FEAT_7_0_EBX] = 4832 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4833 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4834 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4835 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4836 .features[FEAT_7_0_ECX] = 4837 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4838 .features[FEAT_XSAVE] = 4839 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4840 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4841 .features[FEAT_6_EAX] = 4842 CPUID_6_EAX_ARAT, 4843 .features[FEAT_SVM] = 4844 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4845 .xlevel = 0x8000001E, 4846 .model_id = "AMD EPYC-Rome Processor", 4847 .cache_info = &epyc_rome_cache_info, 4848 .versions = (X86CPUVersionDefinition[]) { 4849 { .version = 1 }, 4850 { 4851 .version = 2, 4852 .props = (PropValue[]) { 4853 { "ibrs", "on" }, 4854 { "amd-ssbd", "on" }, 4855 { /* end of list */ } 4856 } 4857 }, 4858 { 4859 .version = 3, 4860 .props = (PropValue[]) { 4861 { "model-id", 4862 "AMD EPYC-Rome-v3 Processor" }, 4863 { /* end of list */ } 4864 }, 4865 .cache_info = &epyc_rome_v3_cache_info 4866 }, 4867 { 4868 .version = 4, 4869 .props = (PropValue[]) { 4870 /* Erratum 1386 */ 4871 { "model-id", 4872 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 4873 { "xsaves", "off" }, 4874 { /* end of list */ } 4875 }, 4876 }, 4877 { /* end of list */ } 4878 } 4879 }, 4880 { 4881 .name = "EPYC-Milan", 4882 .level = 0xd, 4883 .vendor = CPUID_VENDOR_AMD, 4884 .family = 25, 4885 .model = 1, 4886 .stepping = 1, 4887 .features[FEAT_1_EDX] = 4888 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4889 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4890 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4891 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4892 CPUID_VME | CPUID_FP87, 4893 .features[FEAT_1_ECX] = 4894 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4895 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4896 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4897 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4898 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4899 CPUID_EXT_PCID, 4900 .features[FEAT_8000_0001_EDX] = 4901 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4902 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4903 CPUID_EXT2_SYSCALL, 4904 .features[FEAT_8000_0001_ECX] = 4905 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4906 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4907 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4908 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4909 .features[FEAT_8000_0008_EBX] = 4910 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4911 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4912 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4913 CPUID_8000_0008_EBX_AMD_SSBD, 4914 .features[FEAT_7_0_EBX] = 4915 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4916 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4917 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4918 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4919 CPUID_7_0_EBX_INVPCID, 4920 .features[FEAT_7_0_ECX] = 4921 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4922 .features[FEAT_7_0_EDX] = 4923 CPUID_7_0_EDX_FSRM, 4924 .features[FEAT_XSAVE] = 4925 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4926 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4927 .features[FEAT_6_EAX] = 4928 CPUID_6_EAX_ARAT, 4929 .features[FEAT_SVM] = 4930 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4931 .xlevel = 0x8000001E, 4932 .model_id = "AMD EPYC-Milan Processor", 4933 .cache_info = &epyc_milan_cache_info, 4934 .versions = (X86CPUVersionDefinition[]) { 4935 { .version = 1 }, 4936 { 4937 .version = 2, 4938 .props = (PropValue[]) { 4939 { "model-id", 4940 "AMD EPYC-Milan-v2 Processor" }, 4941 { "vaes", "on" }, 4942 { "vpclmulqdq", "on" }, 4943 { "stibp-always-on", "on" }, 4944 { "amd-psfd", "on" }, 4945 { "no-nested-data-bp", "on" }, 4946 { "lfence-always-serializing", "on" }, 4947 { "null-sel-clr-base", "on" }, 4948 { /* end of list */ } 4949 }, 4950 .cache_info = &epyc_milan_v2_cache_info 4951 }, 4952 { /* end of list */ } 4953 } 4954 }, 4955 { 4956 .name = "EPYC-Genoa", 4957 .level = 0xd, 4958 .vendor = CPUID_VENDOR_AMD, 4959 .family = 25, 4960 .model = 17, 4961 .stepping = 0, 4962 .features[FEAT_1_EDX] = 4963 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4964 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4965 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4966 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4967 CPUID_VME | CPUID_FP87, 4968 .features[FEAT_1_ECX] = 4969 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4970 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4971 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4972 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4973 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 4974 CPUID_EXT_SSE3, 4975 .features[FEAT_8000_0001_EDX] = 4976 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4977 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4978 CPUID_EXT2_SYSCALL, 4979 .features[FEAT_8000_0001_ECX] = 4980 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4981 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4982 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4983 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4984 .features[FEAT_8000_0008_EBX] = 4985 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4986 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4987 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4988 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 4989 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 4990 .features[FEAT_8000_0021_EAX] = 4991 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 4992 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 4993 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 4994 CPUID_8000_0021_EAX_AUTO_IBRS, 4995 .features[FEAT_7_0_EBX] = 4996 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4997 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4998 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 4999 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5000 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5001 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5002 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5003 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5004 .features[FEAT_7_0_ECX] = 5005 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5006 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5007 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5008 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5009 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5010 CPUID_7_0_ECX_RDPID, 5011 .features[FEAT_7_0_EDX] = 5012 CPUID_7_0_EDX_FSRM, 5013 .features[FEAT_7_1_EAX] = 5014 CPUID_7_1_EAX_AVX512_BF16, 5015 .features[FEAT_XSAVE] = 5016 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5017 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5018 .features[FEAT_6_EAX] = 5019 CPUID_6_EAX_ARAT, 5020 .features[FEAT_SVM] = 5021 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5022 CPUID_SVM_SVME_ADDR_CHK, 5023 .xlevel = 0x80000022, 5024 .model_id = "AMD EPYC-Genoa Processor", 5025 .cache_info = &epyc_genoa_cache_info, 5026 }, 5027 }; 5028 5029 /* 5030 * We resolve CPU model aliases using -v1 when using "-machine 5031 * none", but this is just for compatibility while libvirt isn't 5032 * adapted to resolve CPU model versions before creating VMs. 5033 * See "Runnability guarantee of CPU models" at 5034 * docs/about/deprecated.rst. 5035 */ 5036 X86CPUVersion default_cpu_version = 1; 5037 5038 void x86_cpu_set_default_version(X86CPUVersion version) 5039 { 5040 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5041 assert(version != CPU_VERSION_AUTO); 5042 default_cpu_version = version; 5043 } 5044 5045 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5046 { 5047 int v = 0; 5048 const X86CPUVersionDefinition *vdef = 5049 x86_cpu_def_get_versions(model->cpudef); 5050 while (vdef->version) { 5051 v = vdef->version; 5052 vdef++; 5053 } 5054 return v; 5055 } 5056 5057 /* Return the actual version being used for a specific CPU model */ 5058 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5059 { 5060 X86CPUVersion v = model->version; 5061 if (v == CPU_VERSION_AUTO) { 5062 v = default_cpu_version; 5063 } 5064 if (v == CPU_VERSION_LATEST) { 5065 return x86_cpu_model_last_version(model); 5066 } 5067 return v; 5068 } 5069 5070 static Property max_x86_cpu_properties[] = { 5071 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5072 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5073 DEFINE_PROP_END_OF_LIST() 5074 }; 5075 5076 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5077 { 5078 Object *obj = OBJECT(dev); 5079 5080 if (!object_property_get_int(obj, "family", &error_abort)) { 5081 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5082 object_property_set_int(obj, "family", 15, &error_abort); 5083 object_property_set_int(obj, "model", 107, &error_abort); 5084 object_property_set_int(obj, "stepping", 1, &error_abort); 5085 } else { 5086 object_property_set_int(obj, "family", 6, &error_abort); 5087 object_property_set_int(obj, "model", 6, &error_abort); 5088 object_property_set_int(obj, "stepping", 3, &error_abort); 5089 } 5090 } 5091 5092 x86_cpu_realizefn(dev, errp); 5093 } 5094 5095 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5096 { 5097 DeviceClass *dc = DEVICE_CLASS(oc); 5098 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5099 5100 xcc->ordering = 9; 5101 5102 xcc->model_description = 5103 "Enables all features supported by the accelerator in the current host"; 5104 5105 device_class_set_props(dc, max_x86_cpu_properties); 5106 dc->realize = max_x86_cpu_realize; 5107 } 5108 5109 static void max_x86_cpu_initfn(Object *obj) 5110 { 5111 X86CPU *cpu = X86_CPU(obj); 5112 5113 /* We can't fill the features array here because we don't know yet if 5114 * "migratable" is true or false. 5115 */ 5116 cpu->max_features = true; 5117 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5118 5119 /* 5120 * these defaults are used for TCG and all other accelerators 5121 * besides KVM and HVF, which overwrite these values 5122 */ 5123 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5124 &error_abort); 5125 object_property_set_str(OBJECT(cpu), "model-id", 5126 "QEMU TCG CPU version " QEMU_HW_VERSION, 5127 &error_abort); 5128 } 5129 5130 static const TypeInfo max_x86_cpu_type_info = { 5131 .name = X86_CPU_TYPE_NAME("max"), 5132 .parent = TYPE_X86_CPU, 5133 .instance_init = max_x86_cpu_initfn, 5134 .class_init = max_x86_cpu_class_init, 5135 }; 5136 5137 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5138 { 5139 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5140 5141 switch (f->type) { 5142 case CPUID_FEATURE_WORD: 5143 { 5144 const char *reg = get_register_name_32(f->cpuid.reg); 5145 assert(reg); 5146 return g_strdup_printf("CPUID.%02XH:%s", 5147 f->cpuid.eax, reg); 5148 } 5149 case MSR_FEATURE_WORD: 5150 return g_strdup_printf("MSR(%02XH)", 5151 f->msr.index); 5152 } 5153 5154 return NULL; 5155 } 5156 5157 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5158 { 5159 FeatureWord w; 5160 5161 for (w = 0; w < FEATURE_WORDS; w++) { 5162 if (cpu->filtered_features[w]) { 5163 return true; 5164 } 5165 } 5166 5167 return false; 5168 } 5169 5170 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5171 const char *verbose_prefix) 5172 { 5173 CPUX86State *env = &cpu->env; 5174 FeatureWordInfo *f = &feature_word_info[w]; 5175 int i; 5176 5177 if (!cpu->force_features) { 5178 env->features[w] &= ~mask; 5179 } 5180 cpu->filtered_features[w] |= mask; 5181 5182 if (!verbose_prefix) { 5183 return; 5184 } 5185 5186 for (i = 0; i < 64; ++i) { 5187 if ((1ULL << i) & mask) { 5188 g_autofree char *feat_word_str = feature_word_description(f, i); 5189 warn_report("%s: %s%s%s [bit %d]", 5190 verbose_prefix, 5191 feat_word_str, 5192 f->feat_names[i] ? "." : "", 5193 f->feat_names[i] ? f->feat_names[i] : "", i); 5194 } 5195 } 5196 } 5197 5198 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5199 const char *name, void *opaque, 5200 Error **errp) 5201 { 5202 X86CPU *cpu = X86_CPU(obj); 5203 CPUX86State *env = &cpu->env; 5204 int64_t value; 5205 5206 value = (env->cpuid_version >> 8) & 0xf; 5207 if (value == 0xf) { 5208 value += (env->cpuid_version >> 20) & 0xff; 5209 } 5210 visit_type_int(v, name, &value, errp); 5211 } 5212 5213 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5214 const char *name, void *opaque, 5215 Error **errp) 5216 { 5217 X86CPU *cpu = X86_CPU(obj); 5218 CPUX86State *env = &cpu->env; 5219 const int64_t min = 0; 5220 const int64_t max = 0xff + 0xf; 5221 int64_t value; 5222 5223 if (!visit_type_int(v, name, &value, errp)) { 5224 return; 5225 } 5226 if (value < min || value > max) { 5227 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5228 name ? name : "null", value, min, max); 5229 return; 5230 } 5231 5232 env->cpuid_version &= ~0xff00f00; 5233 if (value > 0x0f) { 5234 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5235 } else { 5236 env->cpuid_version |= value << 8; 5237 } 5238 } 5239 5240 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5241 const char *name, void *opaque, 5242 Error **errp) 5243 { 5244 X86CPU *cpu = X86_CPU(obj); 5245 CPUX86State *env = &cpu->env; 5246 int64_t value; 5247 5248 value = (env->cpuid_version >> 4) & 0xf; 5249 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5250 visit_type_int(v, name, &value, errp); 5251 } 5252 5253 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5254 const char *name, void *opaque, 5255 Error **errp) 5256 { 5257 X86CPU *cpu = X86_CPU(obj); 5258 CPUX86State *env = &cpu->env; 5259 const int64_t min = 0; 5260 const int64_t max = 0xff; 5261 int64_t value; 5262 5263 if (!visit_type_int(v, name, &value, errp)) { 5264 return; 5265 } 5266 if (value < min || value > max) { 5267 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5268 name ? name : "null", value, min, max); 5269 return; 5270 } 5271 5272 env->cpuid_version &= ~0xf00f0; 5273 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5274 } 5275 5276 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5277 const char *name, void *opaque, 5278 Error **errp) 5279 { 5280 X86CPU *cpu = X86_CPU(obj); 5281 CPUX86State *env = &cpu->env; 5282 int64_t value; 5283 5284 value = env->cpuid_version & 0xf; 5285 visit_type_int(v, name, &value, errp); 5286 } 5287 5288 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5289 const char *name, void *opaque, 5290 Error **errp) 5291 { 5292 X86CPU *cpu = X86_CPU(obj); 5293 CPUX86State *env = &cpu->env; 5294 const int64_t min = 0; 5295 const int64_t max = 0xf; 5296 int64_t value; 5297 5298 if (!visit_type_int(v, name, &value, errp)) { 5299 return; 5300 } 5301 if (value < min || value > max) { 5302 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5303 name ? name : "null", value, min, max); 5304 return; 5305 } 5306 5307 env->cpuid_version &= ~0xf; 5308 env->cpuid_version |= value & 0xf; 5309 } 5310 5311 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5312 { 5313 X86CPU *cpu = X86_CPU(obj); 5314 CPUX86State *env = &cpu->env; 5315 char *value; 5316 5317 value = g_malloc(CPUID_VENDOR_SZ + 1); 5318 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5319 env->cpuid_vendor3); 5320 return value; 5321 } 5322 5323 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5324 Error **errp) 5325 { 5326 X86CPU *cpu = X86_CPU(obj); 5327 CPUX86State *env = &cpu->env; 5328 int i; 5329 5330 if (strlen(value) != CPUID_VENDOR_SZ) { 5331 error_setg(errp, "value of property 'vendor' must consist of" 5332 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5333 return; 5334 } 5335 5336 env->cpuid_vendor1 = 0; 5337 env->cpuid_vendor2 = 0; 5338 env->cpuid_vendor3 = 0; 5339 for (i = 0; i < 4; i++) { 5340 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5341 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5342 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5343 } 5344 } 5345 5346 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5347 { 5348 X86CPU *cpu = X86_CPU(obj); 5349 CPUX86State *env = &cpu->env; 5350 char *value; 5351 int i; 5352 5353 value = g_malloc(48 + 1); 5354 for (i = 0; i < 48; i++) { 5355 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5356 } 5357 value[48] = '\0'; 5358 return value; 5359 } 5360 5361 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5362 Error **errp) 5363 { 5364 X86CPU *cpu = X86_CPU(obj); 5365 CPUX86State *env = &cpu->env; 5366 int c, len, i; 5367 5368 if (model_id == NULL) { 5369 model_id = ""; 5370 } 5371 len = strlen(model_id); 5372 memset(env->cpuid_model, 0, 48); 5373 for (i = 0; i < 48; i++) { 5374 if (i >= len) { 5375 c = '\0'; 5376 } else { 5377 c = (uint8_t)model_id[i]; 5378 } 5379 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5380 } 5381 } 5382 5383 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5384 void *opaque, Error **errp) 5385 { 5386 X86CPU *cpu = X86_CPU(obj); 5387 int64_t value; 5388 5389 value = cpu->env.tsc_khz * 1000; 5390 visit_type_int(v, name, &value, errp); 5391 } 5392 5393 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5394 void *opaque, Error **errp) 5395 { 5396 X86CPU *cpu = X86_CPU(obj); 5397 const int64_t min = 0; 5398 const int64_t max = INT64_MAX; 5399 int64_t value; 5400 5401 if (!visit_type_int(v, name, &value, errp)) { 5402 return; 5403 } 5404 if (value < min || value > max) { 5405 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5406 name ? name : "null", value, min, max); 5407 return; 5408 } 5409 5410 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5411 } 5412 5413 /* Generic getter for "feature-words" and "filtered-features" properties */ 5414 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5415 const char *name, void *opaque, 5416 Error **errp) 5417 { 5418 uint64_t *array = (uint64_t *)opaque; 5419 FeatureWord w; 5420 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5421 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5422 X86CPUFeatureWordInfoList *list = NULL; 5423 5424 for (w = 0; w < FEATURE_WORDS; w++) { 5425 FeatureWordInfo *wi = &feature_word_info[w]; 5426 /* 5427 * We didn't have MSR features when "feature-words" was 5428 * introduced. Therefore skipped other type entries. 5429 */ 5430 if (wi->type != CPUID_FEATURE_WORD) { 5431 continue; 5432 } 5433 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5434 qwi->cpuid_input_eax = wi->cpuid.eax; 5435 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5436 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5437 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5438 qwi->features = array[w]; 5439 5440 /* List will be in reverse order, but order shouldn't matter */ 5441 list_entries[w].next = list; 5442 list_entries[w].value = &word_infos[w]; 5443 list = &list_entries[w]; 5444 } 5445 5446 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5447 } 5448 5449 /* Convert all '_' in a feature string option name to '-', to make feature 5450 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5451 */ 5452 static inline void feat2prop(char *s) 5453 { 5454 while ((s = strchr(s, '_'))) { 5455 *s = '-'; 5456 } 5457 } 5458 5459 /* Return the feature property name for a feature flag bit */ 5460 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5461 { 5462 const char *name; 5463 /* XSAVE components are automatically enabled by other features, 5464 * so return the original feature name instead 5465 */ 5466 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5467 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5468 5469 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5470 x86_ext_save_areas[comp].bits) { 5471 w = x86_ext_save_areas[comp].feature; 5472 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5473 } 5474 } 5475 5476 assert(bitnr < 64); 5477 assert(w < FEATURE_WORDS); 5478 name = feature_word_info[w].feat_names[bitnr]; 5479 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5480 return name; 5481 } 5482 5483 /* Compatibility hack to maintain legacy +-feat semantic, 5484 * where +-feat overwrites any feature set by 5485 * feat=on|feat even if the later is parsed after +-feat 5486 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5487 */ 5488 static GList *plus_features, *minus_features; 5489 5490 static gint compare_string(gconstpointer a, gconstpointer b) 5491 { 5492 return g_strcmp0(a, b); 5493 } 5494 5495 /* Parse "+feature,-feature,feature=foo" CPU feature string 5496 */ 5497 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5498 Error **errp) 5499 { 5500 char *featurestr; /* Single 'key=value" string being parsed */ 5501 static bool cpu_globals_initialized; 5502 bool ambiguous = false; 5503 5504 if (cpu_globals_initialized) { 5505 return; 5506 } 5507 cpu_globals_initialized = true; 5508 5509 if (!features) { 5510 return; 5511 } 5512 5513 for (featurestr = strtok(features, ","); 5514 featurestr; 5515 featurestr = strtok(NULL, ",")) { 5516 const char *name; 5517 const char *val = NULL; 5518 char *eq = NULL; 5519 char num[32]; 5520 GlobalProperty *prop; 5521 5522 /* Compatibility syntax: */ 5523 if (featurestr[0] == '+') { 5524 plus_features = g_list_append(plus_features, 5525 g_strdup(featurestr + 1)); 5526 continue; 5527 } else if (featurestr[0] == '-') { 5528 minus_features = g_list_append(minus_features, 5529 g_strdup(featurestr + 1)); 5530 continue; 5531 } 5532 5533 eq = strchr(featurestr, '='); 5534 if (eq) { 5535 *eq++ = 0; 5536 val = eq; 5537 } else { 5538 val = "on"; 5539 } 5540 5541 feat2prop(featurestr); 5542 name = featurestr; 5543 5544 if (g_list_find_custom(plus_features, name, compare_string)) { 5545 warn_report("Ambiguous CPU model string. " 5546 "Don't mix both \"+%s\" and \"%s=%s\"", 5547 name, name, val); 5548 ambiguous = true; 5549 } 5550 if (g_list_find_custom(minus_features, name, compare_string)) { 5551 warn_report("Ambiguous CPU model string. " 5552 "Don't mix both \"-%s\" and \"%s=%s\"", 5553 name, name, val); 5554 ambiguous = true; 5555 } 5556 5557 /* Special case: */ 5558 if (!strcmp(name, "tsc-freq")) { 5559 int ret; 5560 uint64_t tsc_freq; 5561 5562 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5563 if (ret < 0 || tsc_freq > INT64_MAX) { 5564 error_setg(errp, "bad numerical value %s", val); 5565 return; 5566 } 5567 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5568 val = num; 5569 name = "tsc-frequency"; 5570 } 5571 5572 prop = g_new0(typeof(*prop), 1); 5573 prop->driver = typename; 5574 prop->property = g_strdup(name); 5575 prop->value = g_strdup(val); 5576 qdev_prop_register_global(prop); 5577 } 5578 5579 if (ambiguous) { 5580 warn_report("Compatibility of ambiguous CPU model " 5581 "strings won't be kept on future QEMU versions"); 5582 } 5583 } 5584 5585 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5586 5587 /* Build a list with the name of all features on a feature word array */ 5588 static void x86_cpu_list_feature_names(FeatureWordArray features, 5589 strList **list) 5590 { 5591 strList **tail = list; 5592 FeatureWord w; 5593 5594 for (w = 0; w < FEATURE_WORDS; w++) { 5595 uint64_t filtered = features[w]; 5596 int i; 5597 for (i = 0; i < 64; i++) { 5598 if (filtered & (1ULL << i)) { 5599 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5600 } 5601 } 5602 } 5603 } 5604 5605 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5606 const char *name, void *opaque, 5607 Error **errp) 5608 { 5609 X86CPU *xc = X86_CPU(obj); 5610 strList *result = NULL; 5611 5612 x86_cpu_list_feature_names(xc->filtered_features, &result); 5613 visit_type_strList(v, "unavailable-features", &result, errp); 5614 } 5615 5616 /* Print all cpuid feature names in featureset 5617 */ 5618 static void listflags(GList *features) 5619 { 5620 size_t len = 0; 5621 GList *tmp; 5622 5623 for (tmp = features; tmp; tmp = tmp->next) { 5624 const char *name = tmp->data; 5625 if ((len + strlen(name) + 1) >= 75) { 5626 qemu_printf("\n"); 5627 len = 0; 5628 } 5629 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5630 len += strlen(name) + 1; 5631 } 5632 qemu_printf("\n"); 5633 } 5634 5635 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5636 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5637 { 5638 ObjectClass *class_a = (ObjectClass *)a; 5639 ObjectClass *class_b = (ObjectClass *)b; 5640 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5641 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5642 int ret; 5643 5644 if (cc_a->ordering != cc_b->ordering) { 5645 ret = cc_a->ordering - cc_b->ordering; 5646 } else { 5647 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5648 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5649 ret = strcmp(name_a, name_b); 5650 } 5651 return ret; 5652 } 5653 5654 static GSList *get_sorted_cpu_model_list(void) 5655 { 5656 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5657 list = g_slist_sort(list, x86_cpu_list_compare); 5658 return list; 5659 } 5660 5661 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5662 { 5663 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5664 char *r = object_property_get_str(obj, "model-id", &error_abort); 5665 object_unref(obj); 5666 return r; 5667 } 5668 5669 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5670 { 5671 X86CPUVersion version; 5672 5673 if (!cc->model || !cc->model->is_alias) { 5674 return NULL; 5675 } 5676 version = x86_cpu_model_resolve_version(cc->model); 5677 if (version <= 0) { 5678 return NULL; 5679 } 5680 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5681 } 5682 5683 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5684 { 5685 ObjectClass *oc = data; 5686 X86CPUClass *cc = X86_CPU_CLASS(oc); 5687 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5688 g_autofree char *desc = g_strdup(cc->model_description); 5689 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5690 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5691 5692 if (!desc && alias_of) { 5693 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5694 desc = g_strdup("(alias configured by machine type)"); 5695 } else { 5696 desc = g_strdup_printf("(alias of %s)", alias_of); 5697 } 5698 } 5699 if (!desc && cc->model && cc->model->note) { 5700 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5701 } 5702 if (!desc) { 5703 desc = g_strdup_printf("%s", model_id); 5704 } 5705 5706 if (cc->model && cc->model->cpudef->deprecation_note) { 5707 g_autofree char *olddesc = desc; 5708 desc = g_strdup_printf("%s (deprecated)", olddesc); 5709 } 5710 5711 qemu_printf(" %-20s %s\n", name, desc); 5712 } 5713 5714 /* list available CPU models and flags */ 5715 void x86_cpu_list(void) 5716 { 5717 int i, j; 5718 GSList *list; 5719 GList *names = NULL; 5720 5721 qemu_printf("Available CPUs:\n"); 5722 list = get_sorted_cpu_model_list(); 5723 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5724 g_slist_free(list); 5725 5726 names = NULL; 5727 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5728 FeatureWordInfo *fw = &feature_word_info[i]; 5729 for (j = 0; j < 64; j++) { 5730 if (fw->feat_names[j]) { 5731 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5732 } 5733 } 5734 } 5735 5736 names = g_list_sort(names, (GCompareFunc)strcmp); 5737 5738 qemu_printf("\nRecognized CPUID flags:\n"); 5739 listflags(names); 5740 qemu_printf("\n"); 5741 g_list_free(names); 5742 } 5743 5744 #ifndef CONFIG_USER_ONLY 5745 5746 /* Check for missing features that may prevent the CPU class from 5747 * running using the current machine and accelerator. 5748 */ 5749 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5750 strList **list) 5751 { 5752 strList **tail = list; 5753 X86CPU *xc; 5754 Error *err = NULL; 5755 5756 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5757 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5758 return; 5759 } 5760 5761 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5762 5763 x86_cpu_expand_features(xc, &err); 5764 if (err) { 5765 /* Errors at x86_cpu_expand_features should never happen, 5766 * but in case it does, just report the model as not 5767 * runnable at all using the "type" property. 5768 */ 5769 QAPI_LIST_APPEND(tail, g_strdup("type")); 5770 error_free(err); 5771 } 5772 5773 x86_cpu_filter_features(xc, false); 5774 5775 x86_cpu_list_feature_names(xc->filtered_features, tail); 5776 5777 object_unref(OBJECT(xc)); 5778 } 5779 5780 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5781 { 5782 ObjectClass *oc = data; 5783 X86CPUClass *cc = X86_CPU_CLASS(oc); 5784 CpuDefinitionInfoList **cpu_list = user_data; 5785 CpuDefinitionInfo *info; 5786 5787 info = g_malloc0(sizeof(*info)); 5788 info->name = x86_cpu_class_get_model_name(cc); 5789 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5790 info->has_unavailable_features = true; 5791 info->q_typename = g_strdup(object_class_get_name(oc)); 5792 info->migration_safe = cc->migration_safe; 5793 info->has_migration_safe = true; 5794 info->q_static = cc->static_model; 5795 if (cc->model && cc->model->cpudef->deprecation_note) { 5796 info->deprecated = true; 5797 } else { 5798 info->deprecated = false; 5799 } 5800 /* 5801 * Old machine types won't report aliases, so that alias translation 5802 * doesn't break compatibility with previous QEMU versions. 5803 */ 5804 if (default_cpu_version != CPU_VERSION_LEGACY) { 5805 info->alias_of = x86_cpu_class_get_alias_of(cc); 5806 } 5807 5808 QAPI_LIST_PREPEND(*cpu_list, info); 5809 } 5810 5811 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5812 { 5813 CpuDefinitionInfoList *cpu_list = NULL; 5814 GSList *list = get_sorted_cpu_model_list(); 5815 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5816 g_slist_free(list); 5817 return cpu_list; 5818 } 5819 5820 #endif /* !CONFIG_USER_ONLY */ 5821 5822 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5823 bool migratable_only) 5824 { 5825 FeatureWordInfo *wi = &feature_word_info[w]; 5826 uint64_t r = 0; 5827 5828 if (kvm_enabled()) { 5829 switch (wi->type) { 5830 case CPUID_FEATURE_WORD: 5831 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5832 wi->cpuid.ecx, 5833 wi->cpuid.reg); 5834 break; 5835 case MSR_FEATURE_WORD: 5836 r = kvm_arch_get_supported_msr_feature(kvm_state, 5837 wi->msr.index); 5838 break; 5839 } 5840 } else if (hvf_enabled()) { 5841 if (wi->type != CPUID_FEATURE_WORD) { 5842 return 0; 5843 } 5844 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5845 wi->cpuid.ecx, 5846 wi->cpuid.reg); 5847 } else if (tcg_enabled()) { 5848 r = wi->tcg_features; 5849 } else { 5850 return ~0; 5851 } 5852 #ifndef TARGET_X86_64 5853 if (w == FEAT_8000_0001_EDX) { 5854 /* 5855 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 5856 * way for userspace to get out of its 32-bit jail, we can leave 5857 * the LM bit set. 5858 */ 5859 uint32_t unavail = tcg_enabled() 5860 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 5861 : CPUID_EXT2_LM; 5862 r &= ~unavail; 5863 } 5864 #endif 5865 if (migratable_only) { 5866 r &= x86_cpu_get_migratable_flags(w); 5867 } 5868 return r; 5869 } 5870 5871 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 5872 uint32_t *eax, uint32_t *ebx, 5873 uint32_t *ecx, uint32_t *edx) 5874 { 5875 if (kvm_enabled()) { 5876 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 5877 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 5878 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 5879 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 5880 } else if (hvf_enabled()) { 5881 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 5882 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 5883 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 5884 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 5885 } else { 5886 *eax = 0; 5887 *ebx = 0; 5888 *ecx = 0; 5889 *edx = 0; 5890 } 5891 } 5892 5893 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 5894 uint32_t *eax, uint32_t *ebx, 5895 uint32_t *ecx, uint32_t *edx) 5896 { 5897 uint32_t level, unused; 5898 5899 /* Only return valid host leaves. */ 5900 switch (func) { 5901 case 2: 5902 case 4: 5903 host_cpuid(0, 0, &level, &unused, &unused, &unused); 5904 break; 5905 case 0x80000005: 5906 case 0x80000006: 5907 case 0x8000001d: 5908 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 5909 break; 5910 default: 5911 return; 5912 } 5913 5914 if (func > level) { 5915 *eax = 0; 5916 *ebx = 0; 5917 *ecx = 0; 5918 *edx = 0; 5919 } else { 5920 host_cpuid(func, index, eax, ebx, ecx, edx); 5921 } 5922 } 5923 5924 /* 5925 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5926 */ 5927 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5928 { 5929 PropValue *pv; 5930 for (pv = props; pv->prop; pv++) { 5931 if (!pv->value) { 5932 continue; 5933 } 5934 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5935 &error_abort); 5936 } 5937 } 5938 5939 /* 5940 * Apply properties for the CPU model version specified in model. 5941 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5942 */ 5943 5944 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5945 { 5946 const X86CPUVersionDefinition *vdef; 5947 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5948 5949 if (version == CPU_VERSION_LEGACY) { 5950 return; 5951 } 5952 5953 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5954 PropValue *p; 5955 5956 for (p = vdef->props; p && p->prop; p++) { 5957 object_property_parse(OBJECT(cpu), p->prop, p->value, 5958 &error_abort); 5959 } 5960 5961 if (vdef->version == version) { 5962 break; 5963 } 5964 } 5965 5966 /* 5967 * If we reached the end of the list, version number was invalid 5968 */ 5969 assert(vdef->version == version); 5970 } 5971 5972 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 5973 X86CPUModel *model) 5974 { 5975 const X86CPUVersionDefinition *vdef; 5976 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5977 const CPUCaches *cache_info = model->cpudef->cache_info; 5978 5979 if (version == CPU_VERSION_LEGACY) { 5980 return cache_info; 5981 } 5982 5983 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5984 if (vdef->cache_info) { 5985 cache_info = vdef->cache_info; 5986 } 5987 5988 if (vdef->version == version) { 5989 break; 5990 } 5991 } 5992 5993 assert(vdef->version == version); 5994 return cache_info; 5995 } 5996 5997 /* 5998 * Load data from X86CPUDefinition into a X86CPU object. 5999 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6000 */ 6001 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6002 { 6003 const X86CPUDefinition *def = model->cpudef; 6004 CPUX86State *env = &cpu->env; 6005 FeatureWord w; 6006 6007 /*NOTE: any property set by this function should be returned by 6008 * x86_cpu_static_props(), so static expansion of 6009 * query-cpu-model-expansion is always complete. 6010 */ 6011 6012 /* CPU models only set _minimum_ values for level/xlevel: */ 6013 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6014 &error_abort); 6015 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6016 &error_abort); 6017 6018 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6019 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6020 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6021 &error_abort); 6022 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6023 &error_abort); 6024 for (w = 0; w < FEATURE_WORDS; w++) { 6025 env->features[w] = def->features[w]; 6026 } 6027 6028 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6029 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6030 6031 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6032 6033 /* sysenter isn't supported in compatibility mode on AMD, 6034 * syscall isn't supported in compatibility mode on Intel. 6035 * Normally we advertise the actual CPU vendor, but you can 6036 * override this using the 'vendor' property if you want to use 6037 * KVM's sysenter/syscall emulation in compatibility mode and 6038 * when doing cross vendor migration 6039 */ 6040 6041 /* 6042 * vendor property is set here but then overloaded with the 6043 * host cpu vendor for KVM and HVF. 6044 */ 6045 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6046 6047 x86_cpu_apply_version_props(cpu, model); 6048 6049 /* 6050 * Properties in versioned CPU model are not user specified features. 6051 * We can simply clear env->user_features here since it will be filled later 6052 * in x86_cpu_expand_features() based on plus_features and minus_features. 6053 */ 6054 memset(&env->user_features, 0, sizeof(env->user_features)); 6055 } 6056 6057 static const gchar *x86_gdb_arch_name(CPUState *cs) 6058 { 6059 #ifdef TARGET_X86_64 6060 return "i386:x86-64"; 6061 #else 6062 return "i386"; 6063 #endif 6064 } 6065 6066 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6067 { 6068 X86CPUModel *model = data; 6069 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6070 CPUClass *cc = CPU_CLASS(oc); 6071 6072 xcc->model = model; 6073 xcc->migration_safe = true; 6074 cc->deprecation_note = model->cpudef->deprecation_note; 6075 } 6076 6077 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6078 { 6079 g_autofree char *typename = x86_cpu_type_name(name); 6080 TypeInfo ti = { 6081 .name = typename, 6082 .parent = TYPE_X86_CPU, 6083 .class_init = x86_cpu_cpudef_class_init, 6084 .class_data = model, 6085 }; 6086 6087 type_register(&ti); 6088 } 6089 6090 6091 /* 6092 * register builtin_x86_defs; 6093 * "max", "base" and subclasses ("host") are not registered here. 6094 * See x86_cpu_register_types for all model registrations. 6095 */ 6096 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6097 { 6098 X86CPUModel *m; 6099 const X86CPUVersionDefinition *vdef; 6100 6101 /* AMD aliases are handled at runtime based on CPUID vendor, so 6102 * they shouldn't be set on the CPU model table. 6103 */ 6104 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6105 /* catch mistakes instead of silently truncating model_id when too long */ 6106 assert(def->model_id && strlen(def->model_id) <= 48); 6107 6108 /* Unversioned model: */ 6109 m = g_new0(X86CPUModel, 1); 6110 m->cpudef = def; 6111 m->version = CPU_VERSION_AUTO; 6112 m->is_alias = true; 6113 x86_register_cpu_model_type(def->name, m); 6114 6115 /* Versioned models: */ 6116 6117 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6118 g_autofree char *name = 6119 x86_cpu_versioned_model_name(def, vdef->version); 6120 6121 m = g_new0(X86CPUModel, 1); 6122 m->cpudef = def; 6123 m->version = vdef->version; 6124 m->note = vdef->note; 6125 x86_register_cpu_model_type(name, m); 6126 6127 if (vdef->alias) { 6128 X86CPUModel *am = g_new0(X86CPUModel, 1); 6129 am->cpudef = def; 6130 am->version = vdef->version; 6131 am->is_alias = true; 6132 x86_register_cpu_model_type(vdef->alias, am); 6133 } 6134 } 6135 6136 } 6137 6138 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6139 { 6140 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6141 return 57; /* 57 bits virtual */ 6142 } else { 6143 return 48; /* 48 bits virtual */ 6144 } 6145 } 6146 6147 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6148 uint32_t *eax, uint32_t *ebx, 6149 uint32_t *ecx, uint32_t *edx) 6150 { 6151 X86CPU *cpu = env_archcpu(env); 6152 CPUState *cs = env_cpu(env); 6153 uint32_t die_offset; 6154 uint32_t limit; 6155 uint32_t signature[3]; 6156 X86CPUTopoInfo topo_info; 6157 6158 topo_info.dies_per_pkg = env->nr_dies; 6159 topo_info.cores_per_die = cs->nr_cores / env->nr_dies; 6160 topo_info.threads_per_core = cs->nr_threads; 6161 6162 /* Calculate & apply limits for different index ranges */ 6163 if (index >= 0xC0000000) { 6164 limit = env->cpuid_xlevel2; 6165 } else if (index >= 0x80000000) { 6166 limit = env->cpuid_xlevel; 6167 } else if (index >= 0x40000000) { 6168 limit = 0x40000001; 6169 } else { 6170 limit = env->cpuid_level; 6171 } 6172 6173 if (index > limit) { 6174 /* Intel documentation states that invalid EAX input will 6175 * return the same information as EAX=cpuid_level 6176 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6177 */ 6178 index = env->cpuid_level; 6179 } 6180 6181 switch(index) { 6182 case 0: 6183 *eax = env->cpuid_level; 6184 *ebx = env->cpuid_vendor1; 6185 *edx = env->cpuid_vendor2; 6186 *ecx = env->cpuid_vendor3; 6187 break; 6188 case 1: 6189 *eax = env->cpuid_version; 6190 *ebx = (cpu->apic_id << 24) | 6191 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6192 *ecx = env->features[FEAT_1_ECX]; 6193 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6194 *ecx |= CPUID_EXT_OSXSAVE; 6195 } 6196 *edx = env->features[FEAT_1_EDX]; 6197 if (cs->nr_cores * cs->nr_threads > 1) { 6198 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 6199 *edx |= CPUID_HT; 6200 } 6201 if (!cpu->enable_pmu) { 6202 *ecx &= ~CPUID_EXT_PDCM; 6203 } 6204 break; 6205 case 2: 6206 /* cache info: needed for Pentium Pro compatibility */ 6207 if (cpu->cache_info_passthrough) { 6208 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6209 break; 6210 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6211 *eax = *ebx = *ecx = *edx = 0; 6212 break; 6213 } 6214 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6215 *ebx = 0; 6216 if (!cpu->enable_l3_cache) { 6217 *ecx = 0; 6218 } else { 6219 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6220 } 6221 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6222 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6223 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6224 break; 6225 case 4: 6226 /* cache info: needed for Core compatibility */ 6227 if (cpu->cache_info_passthrough) { 6228 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6229 /* 6230 * QEMU has its own number of cores/logical cpus, 6231 * set 24..14, 31..26 bit to configured values 6232 */ 6233 if (*eax & 31) { 6234 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6235 int vcpus_per_socket = cs->nr_cores * cs->nr_threads; 6236 if (cs->nr_cores > 1) { 6237 *eax &= ~0xFC000000; 6238 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; 6239 } 6240 if (host_vcpus_per_cache > vcpus_per_socket) { 6241 *eax &= ~0x3FFC000; 6242 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; 6243 } 6244 } 6245 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6246 *eax = *ebx = *ecx = *edx = 0; 6247 } else { 6248 *eax = 0; 6249 switch (count) { 6250 case 0: /* L1 dcache info */ 6251 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6252 1, cs->nr_cores, 6253 eax, ebx, ecx, edx); 6254 break; 6255 case 1: /* L1 icache info */ 6256 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6257 1, cs->nr_cores, 6258 eax, ebx, ecx, edx); 6259 break; 6260 case 2: /* L2 cache info */ 6261 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6262 cs->nr_threads, cs->nr_cores, 6263 eax, ebx, ecx, edx); 6264 break; 6265 case 3: /* L3 cache info */ 6266 die_offset = apicid_die_offset(&topo_info); 6267 if (cpu->enable_l3_cache) { 6268 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6269 (1 << die_offset), cs->nr_cores, 6270 eax, ebx, ecx, edx); 6271 break; 6272 } 6273 /* fall through */ 6274 default: /* end of info */ 6275 *eax = *ebx = *ecx = *edx = 0; 6276 break; 6277 } 6278 } 6279 break; 6280 case 5: 6281 /* MONITOR/MWAIT Leaf */ 6282 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6283 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6284 *ecx = cpu->mwait.ecx; /* flags */ 6285 *edx = cpu->mwait.edx; /* mwait substates */ 6286 break; 6287 case 6: 6288 /* Thermal and Power Leaf */ 6289 *eax = env->features[FEAT_6_EAX]; 6290 *ebx = 0; 6291 *ecx = 0; 6292 *edx = 0; 6293 break; 6294 case 7: 6295 /* Structured Extended Feature Flags Enumeration Leaf */ 6296 if (count == 0) { 6297 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused; 6298 6299 /* Maximum ECX value for sub-leaves */ 6300 *eax = env->cpuid_level_func7; 6301 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6302 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6303 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6304 *ecx |= CPUID_7_0_ECX_OSPKE; 6305 } 6306 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6307 6308 /* 6309 * SGX cannot be emulated in software. If hardware does not 6310 * support enabling SGX and/or SGX flexible launch control, 6311 * then we need to update the VM's CPUID values accordingly. 6312 */ 6313 x86_cpu_get_supported_cpuid(0x7, 0, 6314 &eax_0_unused, &ebx_0, 6315 &ecx_0, &edx_0_unused); 6316 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) { 6317 *ebx &= ~CPUID_7_0_EBX_SGX; 6318 } 6319 6320 if ((*ecx & CPUID_7_0_ECX_SGX_LC) 6321 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) { 6322 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 6323 } 6324 } else if (count == 1) { 6325 *eax = env->features[FEAT_7_1_EAX]; 6326 *edx = env->features[FEAT_7_1_EDX]; 6327 *ebx = 0; 6328 *ecx = 0; 6329 } else if (count == 2) { 6330 *edx = env->features[FEAT_7_2_EDX]; 6331 *eax = 0; 6332 *ebx = 0; 6333 *ecx = 0; 6334 } else { 6335 *eax = 0; 6336 *ebx = 0; 6337 *ecx = 0; 6338 *edx = 0; 6339 } 6340 break; 6341 case 9: 6342 /* Direct Cache Access Information Leaf */ 6343 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6344 *ebx = 0; 6345 *ecx = 0; 6346 *edx = 0; 6347 break; 6348 case 0xA: 6349 /* Architectural Performance Monitoring Leaf */ 6350 if (cpu->enable_pmu) { 6351 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6352 } else { 6353 *eax = 0; 6354 *ebx = 0; 6355 *ecx = 0; 6356 *edx = 0; 6357 } 6358 break; 6359 case 0xB: 6360 /* Extended Topology Enumeration Leaf */ 6361 if (!cpu->enable_cpuid_0xb) { 6362 *eax = *ebx = *ecx = *edx = 0; 6363 break; 6364 } 6365 6366 *ecx = count & 0xff; 6367 *edx = cpu->apic_id; 6368 6369 switch (count) { 6370 case 0: 6371 *eax = apicid_core_offset(&topo_info); 6372 *ebx = cs->nr_threads; 6373 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 6374 break; 6375 case 1: 6376 *eax = apicid_pkg_offset(&topo_info); 6377 *ebx = cs->nr_cores * cs->nr_threads; 6378 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6379 break; 6380 default: 6381 *eax = 0; 6382 *ebx = 0; 6383 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6384 } 6385 6386 assert(!(*eax & ~0x1f)); 6387 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6388 break; 6389 case 0x1C: 6390 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6391 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6392 *edx = 0; 6393 } 6394 break; 6395 case 0x1F: 6396 /* V2 Extended Topology Enumeration Leaf */ 6397 if (env->nr_dies < 2) { 6398 *eax = *ebx = *ecx = *edx = 0; 6399 break; 6400 } 6401 6402 *ecx = count & 0xff; 6403 *edx = cpu->apic_id; 6404 switch (count) { 6405 case 0: 6406 *eax = apicid_core_offset(&topo_info); 6407 *ebx = cs->nr_threads; 6408 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 6409 break; 6410 case 1: 6411 *eax = apicid_die_offset(&topo_info); 6412 *ebx = topo_info.cores_per_die * topo_info.threads_per_core; 6413 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6414 break; 6415 case 2: 6416 *eax = apicid_pkg_offset(&topo_info); 6417 *ebx = cs->nr_cores * cs->nr_threads; 6418 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 6419 break; 6420 default: 6421 *eax = 0; 6422 *ebx = 0; 6423 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6424 } 6425 assert(!(*eax & ~0x1f)); 6426 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6427 break; 6428 case 0xD: { 6429 /* Processor Extended State */ 6430 *eax = 0; 6431 *ebx = 0; 6432 *ecx = 0; 6433 *edx = 0; 6434 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6435 break; 6436 } 6437 6438 if (count == 0) { 6439 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6440 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6441 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6442 /* 6443 * The initial value of xcr0 and ebx == 0, On host without kvm 6444 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6445 * even through guest update xcr0, this will crash some legacy guest 6446 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6447 */ 6448 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6449 } else if (count == 1) { 6450 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6451 x86_cpu_xsave_xss_components(cpu); 6452 6453 *eax = env->features[FEAT_XSAVE]; 6454 *ebx = xsave_area_size(xstate, true); 6455 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6456 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6457 if (kvm_enabled() && cpu->enable_pmu && 6458 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6459 (*eax & CPUID_XSAVE_XSAVES)) { 6460 *ecx |= XSTATE_ARCH_LBR_MASK; 6461 } else { 6462 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6463 } 6464 } else if (count == 0xf && cpu->enable_pmu 6465 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6466 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6467 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6468 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6469 6470 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6471 *eax = esa->size; 6472 *ebx = esa->offset; 6473 *ecx = esa->ecx & 6474 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6475 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6476 *eax = esa->size; 6477 *ebx = 0; 6478 *ecx = 1; 6479 } 6480 } 6481 break; 6482 } 6483 case 0x12: 6484 #ifndef CONFIG_USER_ONLY 6485 if (!kvm_enabled() || 6486 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6487 *eax = *ebx = *ecx = *edx = 0; 6488 break; 6489 } 6490 6491 /* 6492 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6493 * the EPC properties, e.g. confidentiality and integrity, from the 6494 * host's first EPC section, i.e. assume there is one EPC section or 6495 * that all EPC sections have the same security properties. 6496 */ 6497 if (count > 1) { 6498 uint64_t epc_addr, epc_size; 6499 6500 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6501 *eax = *ebx = *ecx = *edx = 0; 6502 break; 6503 } 6504 host_cpuid(index, 2, eax, ebx, ecx, edx); 6505 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6506 *ebx = (uint32_t)(epc_addr >> 32); 6507 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6508 *edx = (uint32_t)(epc_size >> 32); 6509 break; 6510 } 6511 6512 /* 6513 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6514 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6515 * supports. Features can be further restricted by userspace, but not 6516 * made more permissive. 6517 */ 6518 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6519 6520 if (count == 0) { 6521 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6522 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6523 } else { 6524 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6525 *ebx &= 0; /* ebx reserve */ 6526 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6527 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6528 6529 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6530 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6531 6532 /* Access to PROVISIONKEY requires additional credentials. */ 6533 if ((*eax & (1U << 4)) && 6534 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6535 *eax &= ~(1U << 4); 6536 } 6537 } 6538 #endif 6539 break; 6540 case 0x14: { 6541 /* Intel Processor Trace Enumeration */ 6542 *eax = 0; 6543 *ebx = 0; 6544 *ecx = 0; 6545 *edx = 0; 6546 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6547 !kvm_enabled()) { 6548 break; 6549 } 6550 6551 /* 6552 * If these are changed, they should stay in sync with 6553 * x86_cpu_filter_features(). 6554 */ 6555 if (count == 0) { 6556 *eax = INTEL_PT_MAX_SUBLEAF; 6557 *ebx = INTEL_PT_MINIMAL_EBX; 6558 *ecx = INTEL_PT_MINIMAL_ECX; 6559 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6560 *ecx |= CPUID_14_0_ECX_LIP; 6561 } 6562 } else if (count == 1) { 6563 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6564 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6565 } 6566 break; 6567 } 6568 case 0x1D: { 6569 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6570 *eax = 0; 6571 *ebx = 0; 6572 *ecx = 0; 6573 *edx = 0; 6574 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6575 break; 6576 } 6577 6578 if (count == 0) { 6579 /* Highest numbered palette subleaf */ 6580 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6581 } else if (count == 1) { 6582 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6583 (INTEL_AMX_BYTES_PER_TILE << 16); 6584 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6585 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6586 } 6587 break; 6588 } 6589 case 0x1E: { 6590 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6591 *eax = 0; 6592 *ebx = 0; 6593 *ecx = 0; 6594 *edx = 0; 6595 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6596 break; 6597 } 6598 6599 if (count == 0) { 6600 /* Highest numbered palette subleaf */ 6601 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6602 } 6603 break; 6604 } 6605 case 0x40000000: 6606 /* 6607 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6608 * set here, but we restrict to TCG none the less. 6609 */ 6610 if (tcg_enabled() && cpu->expose_tcg) { 6611 memcpy(signature, "TCGTCGTCGTCG", 12); 6612 *eax = 0x40000001; 6613 *ebx = signature[0]; 6614 *ecx = signature[1]; 6615 *edx = signature[2]; 6616 } else { 6617 *eax = 0; 6618 *ebx = 0; 6619 *ecx = 0; 6620 *edx = 0; 6621 } 6622 break; 6623 case 0x40000001: 6624 *eax = 0; 6625 *ebx = 0; 6626 *ecx = 0; 6627 *edx = 0; 6628 break; 6629 case 0x80000000: 6630 *eax = env->cpuid_xlevel; 6631 *ebx = env->cpuid_vendor1; 6632 *edx = env->cpuid_vendor2; 6633 *ecx = env->cpuid_vendor3; 6634 break; 6635 case 0x80000001: 6636 *eax = env->cpuid_version; 6637 *ebx = 0; 6638 *ecx = env->features[FEAT_8000_0001_ECX]; 6639 *edx = env->features[FEAT_8000_0001_EDX]; 6640 6641 /* The Linux kernel checks for the CMPLegacy bit and 6642 * discards multiple thread information if it is set. 6643 * So don't set it here for Intel to make Linux guests happy. 6644 */ 6645 if (cs->nr_cores * cs->nr_threads > 1) { 6646 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6647 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6648 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6649 *ecx |= 1 << 1; /* CmpLegacy bit */ 6650 } 6651 } 6652 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6653 !(env->hflags & HF_LMA_MASK)) { 6654 *edx &= ~CPUID_EXT2_SYSCALL; 6655 } 6656 break; 6657 case 0x80000002: 6658 case 0x80000003: 6659 case 0x80000004: 6660 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6661 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6662 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6663 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6664 break; 6665 case 0x80000005: 6666 /* cache info (L1 cache) */ 6667 if (cpu->cache_info_passthrough) { 6668 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6669 break; 6670 } 6671 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6672 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6673 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6674 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6675 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6676 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6677 break; 6678 case 0x80000006: 6679 /* cache info (L2 cache) */ 6680 if (cpu->cache_info_passthrough) { 6681 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6682 break; 6683 } 6684 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6685 (L2_DTLB_2M_ENTRIES << 16) | 6686 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6687 (L2_ITLB_2M_ENTRIES); 6688 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6689 (L2_DTLB_4K_ENTRIES << 16) | 6690 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6691 (L2_ITLB_4K_ENTRIES); 6692 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6693 cpu->enable_l3_cache ? 6694 env->cache_info_amd.l3_cache : NULL, 6695 ecx, edx); 6696 break; 6697 case 0x80000007: 6698 *eax = 0; 6699 *ebx = 0; 6700 *ecx = 0; 6701 *edx = env->features[FEAT_8000_0007_EDX]; 6702 break; 6703 case 0x80000008: 6704 /* virtual & phys address size in low 2 bytes. */ 6705 *eax = cpu->phys_bits; 6706 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6707 /* 64 bit processor */ 6708 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6709 *eax |= (cpu->guest_phys_bits << 16); 6710 } 6711 *ebx = env->features[FEAT_8000_0008_EBX]; 6712 if (cs->nr_cores * cs->nr_threads > 1) { 6713 /* 6714 * Bits 15:12 is "The number of bits in the initial 6715 * Core::X86::Apic::ApicId[ApicId] value that indicate 6716 * thread ID within a package". 6717 * Bits 7:0 is "The number of threads in the package is NC+1" 6718 */ 6719 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6720 ((cs->nr_cores * cs->nr_threads) - 1); 6721 } else { 6722 *ecx = 0; 6723 } 6724 *edx = 0; 6725 break; 6726 case 0x8000000A: 6727 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6728 *eax = 0x00000001; /* SVM Revision */ 6729 *ebx = 0x00000010; /* nr of ASIDs */ 6730 *ecx = 0; 6731 *edx = env->features[FEAT_SVM]; /* optional features */ 6732 } else { 6733 *eax = 0; 6734 *ebx = 0; 6735 *ecx = 0; 6736 *edx = 0; 6737 } 6738 break; 6739 case 0x8000001D: 6740 *eax = 0; 6741 if (cpu->cache_info_passthrough) { 6742 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6743 break; 6744 } 6745 switch (count) { 6746 case 0: /* L1 dcache info */ 6747 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6748 &topo_info, eax, ebx, ecx, edx); 6749 break; 6750 case 1: /* L1 icache info */ 6751 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6752 &topo_info, eax, ebx, ecx, edx); 6753 break; 6754 case 2: /* L2 cache info */ 6755 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6756 &topo_info, eax, ebx, ecx, edx); 6757 break; 6758 case 3: /* L3 cache info */ 6759 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6760 &topo_info, eax, ebx, ecx, edx); 6761 break; 6762 default: /* end of info */ 6763 *eax = *ebx = *ecx = *edx = 0; 6764 break; 6765 } 6766 break; 6767 case 0x8000001E: 6768 if (cpu->core_id <= 255) { 6769 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6770 } else { 6771 *eax = 0; 6772 *ebx = 0; 6773 *ecx = 0; 6774 *edx = 0; 6775 } 6776 break; 6777 case 0xC0000000: 6778 *eax = env->cpuid_xlevel2; 6779 *ebx = 0; 6780 *ecx = 0; 6781 *edx = 0; 6782 break; 6783 case 0xC0000001: 6784 /* Support for VIA CPU's CPUID instruction */ 6785 *eax = env->cpuid_version; 6786 *ebx = 0; 6787 *ecx = 0; 6788 *edx = env->features[FEAT_C000_0001_EDX]; 6789 break; 6790 case 0xC0000002: 6791 case 0xC0000003: 6792 case 0xC0000004: 6793 /* Reserved for the future, and now filled with zero */ 6794 *eax = 0; 6795 *ebx = 0; 6796 *ecx = 0; 6797 *edx = 0; 6798 break; 6799 case 0x8000001F: 6800 *eax = *ebx = *ecx = *edx = 0; 6801 if (sev_enabled()) { 6802 *eax = 0x2; 6803 *eax |= sev_es_enabled() ? 0x8 : 0; 6804 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6805 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6806 } 6807 break; 6808 case 0x80000021: 6809 *eax = env->features[FEAT_8000_0021_EAX]; 6810 *ebx = *ecx = *edx = 0; 6811 break; 6812 default: 6813 /* reserved values: zero */ 6814 *eax = 0; 6815 *ebx = 0; 6816 *ecx = 0; 6817 *edx = 0; 6818 break; 6819 } 6820 } 6821 6822 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 6823 { 6824 #ifndef CONFIG_USER_ONLY 6825 /* Those default values are defined in Skylake HW */ 6826 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 6827 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 6828 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 6829 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 6830 #endif 6831 } 6832 6833 static void x86_cpu_reset_hold(Object *obj, ResetType type) 6834 { 6835 CPUState *cs = CPU(obj); 6836 X86CPU *cpu = X86_CPU(cs); 6837 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6838 CPUX86State *env = &cpu->env; 6839 target_ulong cr4; 6840 uint64_t xcr0; 6841 int i; 6842 6843 if (xcc->parent_phases.hold) { 6844 xcc->parent_phases.hold(obj, type); 6845 } 6846 6847 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 6848 6849 env->old_exception = -1; 6850 6851 /* init to reset state */ 6852 env->int_ctl = 0; 6853 env->hflags2 |= HF2_GIF_MASK; 6854 env->hflags2 |= HF2_VGIF_MASK; 6855 env->hflags &= ~HF_GUEST_MASK; 6856 6857 cpu_x86_update_cr0(env, 0x60000010); 6858 env->a20_mask = ~0x0; 6859 env->smbase = 0x30000; 6860 env->msr_smi_count = 0; 6861 6862 env->idt.limit = 0xffff; 6863 env->gdt.limit = 0xffff; 6864 env->ldt.limit = 0xffff; 6865 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6866 env->tr.limit = 0xffff; 6867 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6868 6869 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6870 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6871 DESC_R_MASK | DESC_A_MASK); 6872 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6873 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6874 DESC_A_MASK); 6875 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6876 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6877 DESC_A_MASK); 6878 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6879 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6880 DESC_A_MASK); 6881 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6882 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6883 DESC_A_MASK); 6884 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6885 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6886 DESC_A_MASK); 6887 6888 env->eip = 0xfff0; 6889 env->regs[R_EDX] = env->cpuid_version; 6890 6891 env->eflags = 0x2; 6892 6893 /* FPU init */ 6894 for (i = 0; i < 8; i++) { 6895 env->fptags[i] = 1; 6896 } 6897 cpu_set_fpuc(env, 0x37f); 6898 6899 env->mxcsr = 0x1f80; 6900 /* All units are in INIT state. */ 6901 env->xstate_bv = 0; 6902 6903 env->pat = 0x0007040600070406ULL; 6904 6905 if (kvm_enabled()) { 6906 /* 6907 * KVM handles TSC = 0 specially and thinks we are hot-plugging 6908 * a new CPU, use 1 instead to force a reset. 6909 */ 6910 if (env->tsc != 0) { 6911 env->tsc = 1; 6912 } 6913 } else { 6914 env->tsc = 0; 6915 } 6916 6917 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6918 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6919 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6920 } 6921 6922 memset(env->dr, 0, sizeof(env->dr)); 6923 env->dr[6] = DR6_FIXED_1; 6924 env->dr[7] = DR7_FIXED_1; 6925 cpu_breakpoint_remove_all(cs, BP_CPU); 6926 cpu_watchpoint_remove_all(cs, BP_CPU); 6927 6928 cr4 = 0; 6929 xcr0 = XSTATE_FP_MASK; 6930 6931 #ifdef CONFIG_USER_ONLY 6932 /* Enable all the features for user-mode. */ 6933 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6934 xcr0 |= XSTATE_SSE_MASK; 6935 } 6936 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6937 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6938 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 6939 continue; 6940 } 6941 if (env->features[esa->feature] & esa->bits) { 6942 xcr0 |= 1ull << i; 6943 } 6944 } 6945 6946 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6947 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6948 } 6949 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6950 cr4 |= CR4_FSGSBASE_MASK; 6951 } 6952 #endif 6953 6954 env->xcr0 = xcr0; 6955 cpu_x86_update_cr4(env, cr4); 6956 6957 /* 6958 * SDM 11.11.5 requires: 6959 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6960 * - IA32_MTRR_PHYSMASKn.V = 0 6961 * All other bits are undefined. For simplification, zero it all. 6962 */ 6963 env->mtrr_deftype = 0; 6964 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6965 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6966 6967 env->interrupt_injected = -1; 6968 env->exception_nr = -1; 6969 env->exception_pending = 0; 6970 env->exception_injected = 0; 6971 env->exception_has_payload = false; 6972 env->exception_payload = 0; 6973 env->nmi_injected = false; 6974 env->triple_fault_pending = false; 6975 #if !defined(CONFIG_USER_ONLY) 6976 /* We hard-wire the BSP to the first CPU. */ 6977 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 6978 6979 cs->halted = !cpu_is_bsp(cpu); 6980 6981 if (kvm_enabled()) { 6982 kvm_arch_reset_vcpu(cpu); 6983 } 6984 6985 x86_cpu_set_sgxlepubkeyhash(env); 6986 6987 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 6988 6989 #endif 6990 } 6991 6992 void x86_cpu_after_reset(X86CPU *cpu) 6993 { 6994 #ifndef CONFIG_USER_ONLY 6995 if (kvm_enabled()) { 6996 kvm_arch_after_reset_vcpu(cpu); 6997 } 6998 6999 if (cpu->apic_state) { 7000 device_cold_reset(cpu->apic_state); 7001 } 7002 #endif 7003 } 7004 7005 static void mce_init(X86CPU *cpu) 7006 { 7007 CPUX86State *cenv = &cpu->env; 7008 unsigned int bank; 7009 7010 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7011 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7012 (CPUID_MCE | CPUID_MCA)) { 7013 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7014 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7015 cenv->mcg_ctl = ~(uint64_t)0; 7016 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7017 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7018 } 7019 } 7020 } 7021 7022 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7023 { 7024 if (*min < value) { 7025 *min = value; 7026 } 7027 } 7028 7029 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7030 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7031 { 7032 CPUX86State *env = &cpu->env; 7033 FeatureWordInfo *fi = &feature_word_info[w]; 7034 uint32_t eax = fi->cpuid.eax; 7035 uint32_t region = eax & 0xF0000000; 7036 7037 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7038 if (!env->features[w]) { 7039 return; 7040 } 7041 7042 switch (region) { 7043 case 0x00000000: 7044 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7045 break; 7046 case 0x80000000: 7047 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7048 break; 7049 case 0xC0000000: 7050 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7051 break; 7052 } 7053 7054 if (eax == 7) { 7055 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7056 fi->cpuid.ecx); 7057 } 7058 } 7059 7060 /* Calculate XSAVE components based on the configured CPU feature flags */ 7061 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7062 { 7063 CPUX86State *env = &cpu->env; 7064 int i; 7065 uint64_t mask; 7066 static bool request_perm; 7067 7068 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7069 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7070 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7071 env->features[FEAT_XSAVE_XSS_LO] = 0; 7072 env->features[FEAT_XSAVE_XSS_HI] = 0; 7073 return; 7074 } 7075 7076 mask = 0; 7077 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7078 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7079 if (env->features[esa->feature] & esa->bits) { 7080 mask |= (1ULL << i); 7081 } 7082 } 7083 7084 /* Only request permission for first vcpu */ 7085 if (kvm_enabled() && !request_perm) { 7086 kvm_request_xsave_components(cpu, mask); 7087 request_perm = true; 7088 } 7089 7090 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7091 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7092 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7093 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7094 } 7095 7096 /***** Steps involved on loading and filtering CPUID data 7097 * 7098 * When initializing and realizing a CPU object, the steps 7099 * involved in setting up CPUID data are: 7100 * 7101 * 1) Loading CPU model definition (X86CPUDefinition). This is 7102 * implemented by x86_cpu_load_model() and should be completely 7103 * transparent, as it is done automatically by instance_init. 7104 * No code should need to look at X86CPUDefinition structs 7105 * outside instance_init. 7106 * 7107 * 2) CPU expansion. This is done by realize before CPUID 7108 * filtering, and will make sure host/accelerator data is 7109 * loaded for CPU models that depend on host capabilities 7110 * (e.g. "host"). Done by x86_cpu_expand_features(). 7111 * 7112 * 3) CPUID filtering. This initializes extra data related to 7113 * CPUID, and checks if the host supports all capabilities 7114 * required by the CPU. Runnability of a CPU model is 7115 * determined at this step. Done by x86_cpu_filter_features(). 7116 * 7117 * Some operations don't require all steps to be performed. 7118 * More precisely: 7119 * 7120 * - CPU instance creation (instance_init) will run only CPU 7121 * model loading. CPU expansion can't run at instance_init-time 7122 * because host/accelerator data may be not available yet. 7123 * - CPU realization will perform both CPU model expansion and CPUID 7124 * filtering, and return an error in case one of them fails. 7125 * - query-cpu-definitions needs to run all 3 steps. It needs 7126 * to run CPUID filtering, as the 'unavailable-features' 7127 * field is set based on the filtering results. 7128 * - The query-cpu-model-expansion QMP command only needs to run 7129 * CPU model loading and CPU expansion. It should not filter 7130 * any CPUID data based on host capabilities. 7131 */ 7132 7133 /* Expand CPU configuration data, based on configured features 7134 * and host/accelerator capabilities when appropriate. 7135 */ 7136 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7137 { 7138 CPUX86State *env = &cpu->env; 7139 FeatureWord w; 7140 int i; 7141 GList *l; 7142 7143 for (l = plus_features; l; l = l->next) { 7144 const char *prop = l->data; 7145 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7146 return; 7147 } 7148 } 7149 7150 for (l = minus_features; l; l = l->next) { 7151 const char *prop = l->data; 7152 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7153 return; 7154 } 7155 } 7156 7157 /*TODO: Now cpu->max_features doesn't overwrite features 7158 * set using QOM properties, and we can convert 7159 * plus_features & minus_features to global properties 7160 * inside x86_cpu_parse_featurestr() too. 7161 */ 7162 if (cpu->max_features) { 7163 for (w = 0; w < FEATURE_WORDS; w++) { 7164 /* Override only features that weren't set explicitly 7165 * by the user. 7166 */ 7167 env->features[w] |= 7168 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 7169 ~env->user_features[w] & 7170 ~feature_word_info[w].no_autoenable_flags; 7171 } 7172 } 7173 7174 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7175 FeatureDep *d = &feature_dependencies[i]; 7176 if (!(env->features[d->from.index] & d->from.mask)) { 7177 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7178 7179 /* Not an error unless the dependent feature was added explicitly. */ 7180 mark_unavailable_features(cpu, d->to.index, 7181 unavailable_features & env->user_features[d->to.index], 7182 "This feature depends on other features that were not requested"); 7183 7184 env->features[d->to.index] &= ~unavailable_features; 7185 } 7186 } 7187 7188 if (!kvm_enabled() || !cpu->expose_kvm) { 7189 env->features[FEAT_KVM] = 0; 7190 } 7191 7192 x86_cpu_enable_xsave_components(cpu); 7193 7194 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7195 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7196 if (cpu->full_cpuid_auto_level) { 7197 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7198 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7199 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7200 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7201 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7202 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7203 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7204 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7205 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7206 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7207 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7208 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7209 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7210 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7211 7212 /* Intel Processor Trace requires CPUID[0x14] */ 7213 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7214 if (cpu->intel_pt_auto_level) { 7215 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7216 } else if (cpu->env.cpuid_min_level < 0x14) { 7217 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7218 CPUID_7_0_EBX_INTEL_PT, 7219 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7220 } 7221 } 7222 7223 /* 7224 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7225 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7226 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7227 * cpu->vendor_cpuid_only has been unset for compatibility with older 7228 * machine types. 7229 */ 7230 if ((env->nr_dies > 1) && 7231 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7232 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7233 } 7234 7235 /* SVM requires CPUID[0x8000000A] */ 7236 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7237 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7238 } 7239 7240 /* SEV requires CPUID[0x8000001F] */ 7241 if (sev_enabled()) { 7242 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7243 } 7244 7245 if (env->features[FEAT_8000_0021_EAX]) { 7246 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7247 } 7248 7249 /* SGX requires CPUID[0x12] for EPC enumeration */ 7250 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7251 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7252 } 7253 } 7254 7255 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7256 if (env->cpuid_level_func7 == UINT32_MAX) { 7257 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7258 } 7259 if (env->cpuid_level == UINT32_MAX) { 7260 env->cpuid_level = env->cpuid_min_level; 7261 } 7262 if (env->cpuid_xlevel == UINT32_MAX) { 7263 env->cpuid_xlevel = env->cpuid_min_xlevel; 7264 } 7265 if (env->cpuid_xlevel2 == UINT32_MAX) { 7266 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7267 } 7268 7269 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7270 return; 7271 } 7272 } 7273 7274 /* 7275 * Finishes initialization of CPUID data, filters CPU feature 7276 * words based on host availability of each feature. 7277 * 7278 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7279 */ 7280 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7281 { 7282 CPUX86State *env = &cpu->env; 7283 FeatureWord w; 7284 const char *prefix = NULL; 7285 7286 if (verbose) { 7287 prefix = accel_uses_host_cpuid() 7288 ? "host doesn't support requested feature" 7289 : "TCG doesn't support requested feature"; 7290 } 7291 7292 for (w = 0; w < FEATURE_WORDS; w++) { 7293 uint64_t host_feat = 7294 x86_cpu_get_supported_feature_word(w, false); 7295 uint64_t requested_features = env->features[w]; 7296 uint64_t unavailable_features = requested_features & ~host_feat; 7297 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7298 } 7299 7300 /* 7301 * Check that KVM actually allows the processor tracing features that 7302 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7303 */ 7304 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7305 kvm_enabled()) { 7306 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7307 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7308 7309 x86_cpu_get_supported_cpuid(0x14, 0, 7310 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7311 x86_cpu_get_supported_cpuid(0x14, 1, 7312 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7313 7314 if (!eax_0 || 7315 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7316 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7317 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7318 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7319 INTEL_PT_ADDR_RANGES_NUM) || 7320 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7321 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7322 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7323 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7324 /* 7325 * Processor Trace capabilities aren't configurable, so if the 7326 * host can't emulate the capabilities we report on 7327 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7328 */ 7329 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7330 } 7331 } 7332 } 7333 7334 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7335 { 7336 size_t len; 7337 7338 /* Hyper-V vendor id */ 7339 if (!cpu->hyperv_vendor) { 7340 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7341 &error_abort); 7342 } 7343 len = strlen(cpu->hyperv_vendor); 7344 if (len > 12) { 7345 warn_report("hv-vendor-id truncated to 12 characters"); 7346 len = 12; 7347 } 7348 memset(cpu->hyperv_vendor_id, 0, 12); 7349 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7350 7351 /* 'Hv#1' interface identification*/ 7352 cpu->hyperv_interface_id[0] = 0x31237648; 7353 cpu->hyperv_interface_id[1] = 0; 7354 cpu->hyperv_interface_id[2] = 0; 7355 cpu->hyperv_interface_id[3] = 0; 7356 7357 /* Hypervisor implementation limits */ 7358 cpu->hyperv_limits[0] = 64; 7359 cpu->hyperv_limits[1] = 0; 7360 cpu->hyperv_limits[2] = 0; 7361 } 7362 7363 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7364 { 7365 CPUState *cs = CPU(dev); 7366 X86CPU *cpu = X86_CPU(dev); 7367 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7368 CPUX86State *env = &cpu->env; 7369 Error *local_err = NULL; 7370 unsigned requested_lbr_fmt; 7371 7372 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7373 /* Use pc-relative instructions in system-mode */ 7374 cs->tcg_cflags |= CF_PCREL; 7375 #endif 7376 7377 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7378 error_setg(errp, "apic-id property was not initialized properly"); 7379 return; 7380 } 7381 7382 /* 7383 * Process Hyper-V enlightenments. 7384 * Note: this currently has to happen before the expansion of CPU features. 7385 */ 7386 x86_cpu_hyperv_realize(cpu); 7387 7388 x86_cpu_expand_features(cpu, &local_err); 7389 if (local_err) { 7390 goto out; 7391 } 7392 7393 /* 7394 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7395 * with user-provided setting. 7396 */ 7397 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7398 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7399 error_setg(errp, "invalid lbr-fmt"); 7400 return; 7401 } 7402 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7403 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7404 } 7405 7406 /* 7407 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7408 * 3)vPMU LBR format matches that of host setting. 7409 */ 7410 requested_lbr_fmt = 7411 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7412 if (requested_lbr_fmt && kvm_enabled()) { 7413 uint64_t host_perf_cap = 7414 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 7415 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7416 7417 if (!cpu->enable_pmu) { 7418 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7419 return; 7420 } 7421 if (requested_lbr_fmt != host_lbr_fmt) { 7422 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7423 "the host value (0x%x).", 7424 requested_lbr_fmt, host_lbr_fmt); 7425 return; 7426 } 7427 } 7428 7429 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7430 7431 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7432 error_setg(&local_err, 7433 accel_uses_host_cpuid() ? 7434 "Host doesn't support requested features" : 7435 "TCG doesn't support requested features"); 7436 goto out; 7437 } 7438 7439 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7440 * CPUID[1].EDX. 7441 */ 7442 if (IS_AMD_CPU(env)) { 7443 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7444 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7445 & CPUID_EXT2_AMD_ALIASES); 7446 } 7447 7448 x86_cpu_set_sgxlepubkeyhash(env); 7449 7450 /* 7451 * note: the call to the framework needs to happen after feature expansion, 7452 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7453 * These may be set by the accel-specific code, 7454 * and the results are subsequently checked / assumed in this function. 7455 */ 7456 cpu_exec_realizefn(cs, &local_err); 7457 if (local_err != NULL) { 7458 error_propagate(errp, local_err); 7459 return; 7460 } 7461 7462 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7463 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7464 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7465 goto out; 7466 } 7467 7468 if (cpu->guest_phys_bits == -1) { 7469 /* 7470 * If it was not set by the user, or by the accelerator via 7471 * cpu_exec_realizefn, clear. 7472 */ 7473 cpu->guest_phys_bits = 0; 7474 } 7475 7476 if (cpu->ucode_rev == 0) { 7477 /* 7478 * The default is the same as KVM's. Note that this check 7479 * needs to happen after the evenual setting of ucode_rev in 7480 * accel-specific code in cpu_exec_realizefn. 7481 */ 7482 if (IS_AMD_CPU(env)) { 7483 cpu->ucode_rev = 0x01000065; 7484 } else { 7485 cpu->ucode_rev = 0x100000000ULL; 7486 } 7487 } 7488 7489 /* 7490 * mwait extended info: needed for Core compatibility 7491 * We always wake on interrupt even if host does not have the capability. 7492 * 7493 * requires the accel-specific code in cpu_exec_realizefn to 7494 * have already acquired the CPUID data into cpu->mwait. 7495 */ 7496 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7497 7498 /* For 64bit systems think about the number of physical bits to present. 7499 * ideally this should be the same as the host; anything other than matching 7500 * the host can cause incorrect guest behaviour. 7501 * QEMU used to pick the magic value of 40 bits that corresponds to 7502 * consumer AMD devices but nothing else. 7503 * 7504 * Note that this code assumes features expansion has already been done 7505 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7506 * phys_bits adjustments to match the host have been already done in 7507 * accel-specific code in cpu_exec_realizefn. 7508 */ 7509 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7510 if (cpu->phys_bits && 7511 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7512 cpu->phys_bits < 32)) { 7513 error_setg(errp, "phys-bits should be between 32 and %u " 7514 " (but is %u)", 7515 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7516 return; 7517 } 7518 /* 7519 * 0 means it was not explicitly set by the user (or by machine 7520 * compat_props or by the host code in host-cpu.c). 7521 * In this case, the default is the value used by TCG (40). 7522 */ 7523 if (cpu->phys_bits == 0) { 7524 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7525 } 7526 if (cpu->guest_phys_bits && 7527 (cpu->guest_phys_bits > cpu->phys_bits || 7528 cpu->guest_phys_bits < 32)) { 7529 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7530 " (but is %u)", 7531 cpu->phys_bits, cpu->guest_phys_bits); 7532 return; 7533 } 7534 } else { 7535 /* For 32 bit systems don't use the user set value, but keep 7536 * phys_bits consistent with what we tell the guest. 7537 */ 7538 if (cpu->phys_bits != 0) { 7539 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7540 return; 7541 } 7542 if (cpu->guest_phys_bits != 0) { 7543 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7544 return; 7545 } 7546 7547 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7548 cpu->phys_bits = 36; 7549 } else { 7550 cpu->phys_bits = 32; 7551 } 7552 } 7553 7554 /* Cache information initialization */ 7555 if (!cpu->legacy_cache) { 7556 const CPUCaches *cache_info = 7557 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7558 7559 if (!xcc->model || !cache_info) { 7560 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7561 error_setg(errp, 7562 "CPU model '%s' doesn't support legacy-cache=off", name); 7563 return; 7564 } 7565 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7566 *cache_info; 7567 } else { 7568 /* Build legacy cache information */ 7569 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7570 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7571 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7572 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7573 7574 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7575 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7576 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7577 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7578 7579 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7580 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7581 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7582 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7583 } 7584 7585 #ifndef CONFIG_USER_ONLY 7586 MachineState *ms = MACHINE(qdev_get_machine()); 7587 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7588 7589 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7590 x86_cpu_apic_create(cpu, &local_err); 7591 if (local_err != NULL) { 7592 goto out; 7593 } 7594 } 7595 #endif 7596 7597 mce_init(cpu); 7598 7599 qemu_init_vcpu(cs); 7600 7601 /* 7602 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7603 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7604 * based on inputs (sockets,cores,threads), it is still better to give 7605 * users a warning. 7606 * 7607 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7608 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7609 */ 7610 if (IS_AMD_CPU(env) && 7611 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7612 cs->nr_threads > 1) { 7613 warn_report_once("This family of AMD CPU doesn't support " 7614 "hyperthreading(%d). Please configure -smp " 7615 "options properly or try enabling topoext " 7616 "feature.", cs->nr_threads); 7617 } 7618 7619 #ifndef CONFIG_USER_ONLY 7620 x86_cpu_apic_realize(cpu, &local_err); 7621 if (local_err != NULL) { 7622 goto out; 7623 } 7624 #endif /* !CONFIG_USER_ONLY */ 7625 cpu_reset(cs); 7626 7627 xcc->parent_realize(dev, &local_err); 7628 7629 out: 7630 if (local_err != NULL) { 7631 error_propagate(errp, local_err); 7632 return; 7633 } 7634 } 7635 7636 static void x86_cpu_unrealizefn(DeviceState *dev) 7637 { 7638 X86CPU *cpu = X86_CPU(dev); 7639 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7640 7641 #ifndef CONFIG_USER_ONLY 7642 cpu_remove_sync(CPU(dev)); 7643 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7644 #endif 7645 7646 if (cpu->apic_state) { 7647 object_unparent(OBJECT(cpu->apic_state)); 7648 cpu->apic_state = NULL; 7649 } 7650 7651 xcc->parent_unrealize(dev); 7652 } 7653 7654 typedef struct BitProperty { 7655 FeatureWord w; 7656 uint64_t mask; 7657 } BitProperty; 7658 7659 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7660 void *opaque, Error **errp) 7661 { 7662 X86CPU *cpu = X86_CPU(obj); 7663 BitProperty *fp = opaque; 7664 uint64_t f = cpu->env.features[fp->w]; 7665 bool value = (f & fp->mask) == fp->mask; 7666 visit_type_bool(v, name, &value, errp); 7667 } 7668 7669 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7670 void *opaque, Error **errp) 7671 { 7672 DeviceState *dev = DEVICE(obj); 7673 X86CPU *cpu = X86_CPU(obj); 7674 BitProperty *fp = opaque; 7675 bool value; 7676 7677 if (dev->realized) { 7678 qdev_prop_set_after_realize(dev, name, errp); 7679 return; 7680 } 7681 7682 if (!visit_type_bool(v, name, &value, errp)) { 7683 return; 7684 } 7685 7686 if (value) { 7687 cpu->env.features[fp->w] |= fp->mask; 7688 } else { 7689 cpu->env.features[fp->w] &= ~fp->mask; 7690 } 7691 cpu->env.user_features[fp->w] |= fp->mask; 7692 } 7693 7694 /* Register a boolean property to get/set a single bit in a uint32_t field. 7695 * 7696 * The same property name can be registered multiple times to make it affect 7697 * multiple bits in the same FeatureWord. In that case, the getter will return 7698 * true only if all bits are set. 7699 */ 7700 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7701 const char *prop_name, 7702 FeatureWord w, 7703 int bitnr) 7704 { 7705 ObjectClass *oc = OBJECT_CLASS(xcc); 7706 BitProperty *fp; 7707 ObjectProperty *op; 7708 uint64_t mask = (1ULL << bitnr); 7709 7710 op = object_class_property_find(oc, prop_name); 7711 if (op) { 7712 fp = op->opaque; 7713 assert(fp->w == w); 7714 fp->mask |= mask; 7715 } else { 7716 fp = g_new0(BitProperty, 1); 7717 fp->w = w; 7718 fp->mask = mask; 7719 object_class_property_add(oc, prop_name, "bool", 7720 x86_cpu_get_bit_prop, 7721 x86_cpu_set_bit_prop, 7722 NULL, fp); 7723 } 7724 } 7725 7726 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7727 FeatureWord w, 7728 int bitnr) 7729 { 7730 FeatureWordInfo *fi = &feature_word_info[w]; 7731 const char *name = fi->feat_names[bitnr]; 7732 7733 if (!name) { 7734 return; 7735 } 7736 7737 /* Property names should use "-" instead of "_". 7738 * Old names containing underscores are registered as aliases 7739 * using object_property_add_alias() 7740 */ 7741 assert(!strchr(name, '_')); 7742 /* aliases don't use "|" delimiters anymore, they are registered 7743 * manually using object_property_add_alias() */ 7744 assert(!strchr(name, '|')); 7745 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7746 } 7747 7748 static void x86_cpu_post_initfn(Object *obj) 7749 { 7750 accel_cpu_instance_init(CPU(obj)); 7751 } 7752 7753 static void x86_cpu_initfn(Object *obj) 7754 { 7755 X86CPU *cpu = X86_CPU(obj); 7756 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7757 CPUX86State *env = &cpu->env; 7758 7759 env->nr_dies = 1; 7760 7761 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7762 x86_cpu_get_feature_words, 7763 NULL, NULL, (void *)env->features); 7764 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 7765 x86_cpu_get_feature_words, 7766 NULL, NULL, (void *)cpu->filtered_features); 7767 7768 object_property_add_alias(obj, "sse3", obj, "pni"); 7769 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 7770 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 7771 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 7772 object_property_add_alias(obj, "xd", obj, "nx"); 7773 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 7774 object_property_add_alias(obj, "i64", obj, "lm"); 7775 7776 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7777 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7778 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7779 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7780 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7781 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7782 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7783 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7784 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7785 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7786 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7787 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7788 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7789 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7790 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7791 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7792 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7793 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7794 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7795 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 7796 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 7797 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 7798 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 7799 7800 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 7801 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 7802 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 7803 7804 if (xcc->model) { 7805 x86_cpu_load_model(cpu, xcc->model); 7806 } 7807 } 7808 7809 static int64_t x86_cpu_get_arch_id(CPUState *cs) 7810 { 7811 X86CPU *cpu = X86_CPU(cs); 7812 7813 return cpu->apic_id; 7814 } 7815 7816 #if !defined(CONFIG_USER_ONLY) 7817 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7818 { 7819 X86CPU *cpu = X86_CPU(cs); 7820 7821 return cpu->env.cr[0] & CR0_PG_MASK; 7822 } 7823 #endif /* !CONFIG_USER_ONLY */ 7824 7825 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7826 { 7827 X86CPU *cpu = X86_CPU(cs); 7828 7829 cpu->env.eip = value; 7830 } 7831 7832 static vaddr x86_cpu_get_pc(CPUState *cs) 7833 { 7834 X86CPU *cpu = X86_CPU(cs); 7835 7836 /* Match cpu_get_tb_cpu_state. */ 7837 return cpu->env.eip + cpu->env.segs[R_CS].base; 7838 } 7839 7840 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7841 { 7842 X86CPU *cpu = X86_CPU(cs); 7843 CPUX86State *env = &cpu->env; 7844 7845 #if !defined(CONFIG_USER_ONLY) 7846 if (interrupt_request & CPU_INTERRUPT_POLL) { 7847 return CPU_INTERRUPT_POLL; 7848 } 7849 #endif 7850 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7851 return CPU_INTERRUPT_SIPI; 7852 } 7853 7854 if (env->hflags2 & HF2_GIF_MASK) { 7855 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7856 !(env->hflags & HF_SMM_MASK)) { 7857 return CPU_INTERRUPT_SMI; 7858 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7859 !(env->hflags2 & HF2_NMI_MASK)) { 7860 return CPU_INTERRUPT_NMI; 7861 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7862 return CPU_INTERRUPT_MCE; 7863 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7864 (((env->hflags2 & HF2_VINTR_MASK) && 7865 (env->hflags2 & HF2_HIF_MASK)) || 7866 (!(env->hflags2 & HF2_VINTR_MASK) && 7867 (env->eflags & IF_MASK && 7868 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7869 return CPU_INTERRUPT_HARD; 7870 #if !defined(CONFIG_USER_ONLY) 7871 } else if (env->hflags2 & HF2_VGIF_MASK) { 7872 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 7873 (env->eflags & IF_MASK) && 7874 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7875 return CPU_INTERRUPT_VIRQ; 7876 } 7877 #endif 7878 } 7879 } 7880 7881 return 0; 7882 } 7883 7884 static bool x86_cpu_has_work(CPUState *cs) 7885 { 7886 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7887 } 7888 7889 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 7890 { 7891 CPUX86State *env = cpu_env(cs); 7892 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 7893 int mmu_index_base = 7894 (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER64_IDX : 7895 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 7896 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 7897 7898 return mmu_index_base + mmu_index_32; 7899 } 7900 7901 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7902 { 7903 X86CPU *cpu = X86_CPU(cs); 7904 CPUX86State *env = &cpu->env; 7905 7906 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7907 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7908 : bfd_mach_i386_i8086); 7909 7910 info->cap_arch = CS_ARCH_X86; 7911 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7912 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7913 : CS_MODE_16); 7914 info->cap_insn_unit = 1; 7915 info->cap_insn_split = 8; 7916 } 7917 7918 void x86_update_hflags(CPUX86State *env) 7919 { 7920 uint32_t hflags; 7921 #define HFLAG_COPY_MASK \ 7922 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7923 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7924 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7925 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7926 7927 hflags = env->hflags & HFLAG_COPY_MASK; 7928 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7929 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7930 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7931 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7932 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7933 7934 if (env->cr[4] & CR4_OSFXSR_MASK) { 7935 hflags |= HF_OSFXSR_MASK; 7936 } 7937 7938 if (env->efer & MSR_EFER_LMA) { 7939 hflags |= HF_LMA_MASK; 7940 } 7941 7942 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7943 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7944 } else { 7945 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7946 (DESC_B_SHIFT - HF_CS32_SHIFT); 7947 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7948 (DESC_B_SHIFT - HF_SS32_SHIFT); 7949 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7950 !(hflags & HF_CS32_MASK)) { 7951 hflags |= HF_ADDSEG_MASK; 7952 } else { 7953 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7954 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7955 } 7956 } 7957 env->hflags = hflags; 7958 } 7959 7960 static Property x86_cpu_properties[] = { 7961 #ifdef CONFIG_USER_ONLY 7962 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7963 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7964 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7965 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7966 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7967 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7968 #else 7969 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7970 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7971 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7972 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7973 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7974 #endif 7975 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7976 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7977 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 7978 7979 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7980 HYPERV_SPINLOCK_NEVER_NOTIFY), 7981 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7982 HYPERV_FEAT_RELAXED, 0), 7983 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7984 HYPERV_FEAT_VAPIC, 0), 7985 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7986 HYPERV_FEAT_TIME, 0), 7987 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7988 HYPERV_FEAT_CRASH, 0), 7989 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7990 HYPERV_FEAT_RESET, 0), 7991 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7992 HYPERV_FEAT_VPINDEX, 0), 7993 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7994 HYPERV_FEAT_RUNTIME, 0), 7995 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7996 HYPERV_FEAT_SYNIC, 0), 7997 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7998 HYPERV_FEAT_STIMER, 0), 7999 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8000 HYPERV_FEAT_FREQUENCIES, 0), 8001 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8002 HYPERV_FEAT_REENLIGHTENMENT, 0), 8003 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8004 HYPERV_FEAT_TLBFLUSH, 0), 8005 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8006 HYPERV_FEAT_EVMCS, 0), 8007 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8008 HYPERV_FEAT_IPI, 0), 8009 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8010 HYPERV_FEAT_STIMER_DIRECT, 0), 8011 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8012 HYPERV_FEAT_AVIC, 0), 8013 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8014 HYPERV_FEAT_MSR_BITMAP, 0), 8015 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8016 HYPERV_FEAT_XMM_INPUT, 0), 8017 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8018 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8019 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8020 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8021 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8022 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8023 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8024 HYPERV_FEAT_SYNDBG, 0), 8025 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8026 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8027 8028 /* WS2008R2 identify by default */ 8029 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8030 0x3839), 8031 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8032 0x000A), 8033 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8034 0x0000), 8035 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8036 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8037 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8038 8039 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8040 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8041 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8042 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8043 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8044 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8045 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8046 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8047 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8048 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8049 UINT32_MAX), 8050 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8051 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8052 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8053 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8054 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8055 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8056 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8057 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8058 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8059 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8060 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8061 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8062 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8063 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 8064 false), 8065 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8066 false), 8067 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8068 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8069 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8070 true), 8071 /* 8072 * lecacy_cache defaults to true unless the CPU model provides its 8073 * own cache information (see x86_cpu_load_def()). 8074 */ 8075 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8076 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8077 8078 /* 8079 * From "Requirements for Implementing the Microsoft 8080 * Hypervisor Interface": 8081 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8082 * 8083 * "Starting with Windows Server 2012 and Windows 8, if 8084 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8085 * the hypervisor imposes no specific limit to the number of VPs. 8086 * In this case, Windows Server 2012 guest VMs may use more than 8087 * 64 VPs, up to the maximum supported number of processors applicable 8088 * to the specific Windows version being used." 8089 */ 8090 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8091 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8092 false), 8093 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8094 true), 8095 DEFINE_PROP_END_OF_LIST() 8096 }; 8097 8098 #ifndef CONFIG_USER_ONLY 8099 #include "hw/core/sysemu-cpu-ops.h" 8100 8101 static const struct SysemuCPUOps i386_sysemu_ops = { 8102 .get_memory_mapping = x86_cpu_get_memory_mapping, 8103 .get_paging_enabled = x86_cpu_get_paging_enabled, 8104 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8105 .asidx_from_attrs = x86_asidx_from_attrs, 8106 .get_crash_info = x86_cpu_get_crash_info, 8107 .write_elf32_note = x86_cpu_write_elf32_note, 8108 .write_elf64_note = x86_cpu_write_elf64_note, 8109 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8110 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8111 .legacy_vmsd = &vmstate_x86_cpu, 8112 }; 8113 #endif 8114 8115 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8116 { 8117 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8118 CPUClass *cc = CPU_CLASS(oc); 8119 DeviceClass *dc = DEVICE_CLASS(oc); 8120 ResettableClass *rc = RESETTABLE_CLASS(oc); 8121 FeatureWord w; 8122 8123 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8124 &xcc->parent_realize); 8125 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8126 &xcc->parent_unrealize); 8127 device_class_set_props(dc, x86_cpu_properties); 8128 8129 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8130 &xcc->parent_phases); 8131 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8132 8133 cc->class_by_name = x86_cpu_class_by_name; 8134 cc->parse_features = x86_cpu_parse_featurestr; 8135 cc->has_work = x86_cpu_has_work; 8136 cc->mmu_index = x86_cpu_mmu_index; 8137 cc->dump_state = x86_cpu_dump_state; 8138 cc->set_pc = x86_cpu_set_pc; 8139 cc->get_pc = x86_cpu_get_pc; 8140 cc->gdb_read_register = x86_cpu_gdb_read_register; 8141 cc->gdb_write_register = x86_cpu_gdb_write_register; 8142 cc->get_arch_id = x86_cpu_get_arch_id; 8143 8144 #ifndef CONFIG_USER_ONLY 8145 cc->sysemu_ops = &i386_sysemu_ops; 8146 #endif /* !CONFIG_USER_ONLY */ 8147 8148 cc->gdb_arch_name = x86_gdb_arch_name; 8149 #ifdef TARGET_X86_64 8150 cc->gdb_core_xml_file = "i386-64bit.xml"; 8151 #else 8152 cc->gdb_core_xml_file = "i386-32bit.xml"; 8153 #endif 8154 cc->disas_set_info = x86_disas_set_info; 8155 8156 dc->user_creatable = true; 8157 8158 object_class_property_add(oc, "family", "int", 8159 x86_cpuid_version_get_family, 8160 x86_cpuid_version_set_family, NULL, NULL); 8161 object_class_property_add(oc, "model", "int", 8162 x86_cpuid_version_get_model, 8163 x86_cpuid_version_set_model, NULL, NULL); 8164 object_class_property_add(oc, "stepping", "int", 8165 x86_cpuid_version_get_stepping, 8166 x86_cpuid_version_set_stepping, NULL, NULL); 8167 object_class_property_add_str(oc, "vendor", 8168 x86_cpuid_get_vendor, 8169 x86_cpuid_set_vendor); 8170 object_class_property_add_str(oc, "model-id", 8171 x86_cpuid_get_model_id, 8172 x86_cpuid_set_model_id); 8173 object_class_property_add(oc, "tsc-frequency", "int", 8174 x86_cpuid_get_tsc_freq, 8175 x86_cpuid_set_tsc_freq, NULL, NULL); 8176 /* 8177 * The "unavailable-features" property has the same semantics as 8178 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8179 * QMP command: they list the features that would have prevented the 8180 * CPU from running if the "enforce" flag was set. 8181 */ 8182 object_class_property_add(oc, "unavailable-features", "strList", 8183 x86_cpu_get_unavailable_features, 8184 NULL, NULL, NULL); 8185 8186 #if !defined(CONFIG_USER_ONLY) 8187 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8188 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8189 #endif 8190 8191 for (w = 0; w < FEATURE_WORDS; w++) { 8192 int bitnr; 8193 for (bitnr = 0; bitnr < 64; bitnr++) { 8194 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8195 } 8196 } 8197 } 8198 8199 static const TypeInfo x86_cpu_type_info = { 8200 .name = TYPE_X86_CPU, 8201 .parent = TYPE_CPU, 8202 .instance_size = sizeof(X86CPU), 8203 .instance_align = __alignof(X86CPU), 8204 .instance_init = x86_cpu_initfn, 8205 .instance_post_init = x86_cpu_post_initfn, 8206 8207 .abstract = true, 8208 .class_size = sizeof(X86CPUClass), 8209 .class_init = x86_cpu_common_class_init, 8210 }; 8211 8212 /* "base" CPU model, used by query-cpu-model-expansion */ 8213 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8214 { 8215 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8216 8217 xcc->static_model = true; 8218 xcc->migration_safe = true; 8219 xcc->model_description = "base CPU model type with no features enabled"; 8220 xcc->ordering = 8; 8221 } 8222 8223 static const TypeInfo x86_base_cpu_type_info = { 8224 .name = X86_CPU_TYPE_NAME("base"), 8225 .parent = TYPE_X86_CPU, 8226 .class_init = x86_cpu_base_class_init, 8227 }; 8228 8229 static void x86_cpu_register_types(void) 8230 { 8231 int i; 8232 8233 type_register_static(&x86_cpu_type_info); 8234 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8235 x86_register_cpudef_types(&builtin_x86_defs[i]); 8236 } 8237 type_register_static(&max_x86_cpu_type_info); 8238 type_register_static(&x86_base_cpu_type_info); 8239 } 8240 8241 type_init(x86_cpu_register_types) 8242