1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "standard-headers/asm-x86/kvm_para.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/i386/topology.h" 37 #ifndef CONFIG_USER_ONLY 38 #include "sysemu/reset.h" 39 #include "qapi/qapi-commands-machine-target.h" 40 #include "exec/address-spaces.h" 41 #include "hw/boards.h" 42 #include "hw/i386/sgx-epc.h" 43 #endif 44 45 #include "disas/capstone.h" 46 #include "cpu-internal.h" 47 48 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 49 50 /* Helpers for building CPUID[2] descriptors: */ 51 52 struct CPUID2CacheDescriptorInfo { 53 enum CacheType type; 54 int level; 55 int size; 56 int line_size; 57 int associativity; 58 }; 59 60 /* 61 * Known CPUID 2 cache descriptors. 62 * From Intel SDM Volume 2A, CPUID instruction 63 */ 64 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 65 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 66 .associativity = 4, .line_size = 32, }, 67 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 68 .associativity = 4, .line_size = 32, }, 69 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 70 .associativity = 4, .line_size = 64, }, 71 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 72 .associativity = 2, .line_size = 32, }, 73 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 78 .associativity = 6, .line_size = 64, }, 79 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 80 .associativity = 2, .line_size = 64, }, 81 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 82 .associativity = 8, .line_size = 64, }, 83 /* lines per sector is not supported cpuid2_cache_descriptor(), 84 * so descriptors 0x22, 0x23 are not included 85 */ 86 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 87 .associativity = 16, .line_size = 64, }, 88 /* lines per sector is not supported cpuid2_cache_descriptor(), 89 * so descriptors 0x25, 0x20 are not included 90 */ 91 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 94 .associativity = 8, .line_size = 64, }, 95 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 96 .associativity = 4, .line_size = 32, }, 97 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 98 .associativity = 4, .line_size = 32, }, 99 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 106 .associativity = 4, .line_size = 64, }, 107 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 110 .associativity = 12, .line_size = 64, }, 111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 112 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 113 .associativity = 12, .line_size = 64, }, 114 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 115 .associativity = 16, .line_size = 64, }, 116 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 121 .associativity = 24, .line_size = 64, }, 122 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 123 .associativity = 8, .line_size = 64, }, 124 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 125 .associativity = 4, .line_size = 64, }, 126 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 131 .associativity = 4, .line_size = 64, }, 132 /* lines per sector is not supported cpuid2_cache_descriptor(), 133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 134 */ 135 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 136 .associativity = 8, .line_size = 64, }, 137 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 138 .associativity = 2, .line_size = 64, }, 139 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 142 .associativity = 8, .line_size = 32, }, 143 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 32, }, 145 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 4, .line_size = 64, }, 151 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 64, }, 153 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 4, .line_size = 64, }, 157 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 64, }, 161 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 64, }, 163 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 166 .associativity = 12, .line_size = 64, }, 167 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 168 .associativity = 12, .line_size = 64, }, 169 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 16, .line_size = 64, }, 173 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 174 .associativity = 16, .line_size = 64, }, 175 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 178 .associativity = 24, .line_size = 64, }, 179 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 180 .associativity = 24, .line_size = 64, }, 181 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 }; 184 185 /* 186 * "CPUID leaf 2 does not report cache descriptor information, 187 * use CPUID leaf 4 to query cache parameters" 188 */ 189 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 190 191 /* 192 * Return a CPUID 2 cache descriptor for a given cache. 193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 194 */ 195 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 196 { 197 int i; 198 199 assert(cache->size > 0); 200 assert(cache->level > 0); 201 assert(cache->line_size > 0); 202 assert(cache->associativity > 0); 203 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 204 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 205 if (d->level == cache->level && d->type == cache->type && 206 d->size == cache->size && d->line_size == cache->line_size && 207 d->associativity == cache->associativity) { 208 return i; 209 } 210 } 211 212 return CACHE_DESCRIPTOR_UNAVAILABLE; 213 } 214 215 /* CPUID Leaf 4 constants: */ 216 217 /* EAX: */ 218 #define CACHE_TYPE_D 1 219 #define CACHE_TYPE_I 2 220 #define CACHE_TYPE_UNIFIED 3 221 222 #define CACHE_LEVEL(l) (l << 5) 223 224 #define CACHE_SELF_INIT_LEVEL (1 << 8) 225 226 /* EDX: */ 227 #define CACHE_NO_INVD_SHARING (1 << 0) 228 #define CACHE_INCLUSIVE (1 << 1) 229 #define CACHE_COMPLEX_IDX (1 << 2) 230 231 /* Encode CacheType for CPUID[4].EAX */ 232 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 235 0 /* Invalid value */) 236 237 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 238 enum CPUTopoLevel share_level) 239 { 240 uint32_t num_ids = 0; 241 242 switch (share_level) { 243 case CPU_TOPO_LEVEL_CORE: 244 num_ids = 1 << apicid_core_offset(topo_info); 245 break; 246 case CPU_TOPO_LEVEL_DIE: 247 num_ids = 1 << apicid_die_offset(topo_info); 248 break; 249 case CPU_TOPO_LEVEL_PACKAGE: 250 num_ids = 1 << apicid_pkg_offset(topo_info); 251 break; 252 default: 253 /* 254 * Currently there is no use case for SMT and MODULE, so use 255 * assert directly to facilitate debugging. 256 */ 257 g_assert_not_reached(); 258 } 259 260 return num_ids - 1; 261 } 262 263 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 264 { 265 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 266 apicid_core_offset(topo_info)); 267 return num_cores - 1; 268 } 269 270 /* Encode cache info for CPUID[4] */ 271 static void encode_cache_cpuid4(CPUCacheInfo *cache, 272 X86CPUTopoInfo *topo_info, 273 uint32_t *eax, uint32_t *ebx, 274 uint32_t *ecx, uint32_t *edx) 275 { 276 assert(cache->size == cache->line_size * cache->associativity * 277 cache->partitions * cache->sets); 278 279 *eax = CACHE_TYPE(cache->type) | 280 CACHE_LEVEL(cache->level) | 281 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 282 (max_core_ids_in_package(topo_info) << 26) | 283 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 284 285 assert(cache->line_size > 0); 286 assert(cache->partitions > 0); 287 assert(cache->associativity > 0); 288 /* We don't implement fully-associative caches */ 289 assert(cache->associativity < cache->sets); 290 *ebx = (cache->line_size - 1) | 291 ((cache->partitions - 1) << 12) | 292 ((cache->associativity - 1) << 22); 293 294 assert(cache->sets > 0); 295 *ecx = cache->sets - 1; 296 297 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 298 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 299 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 300 } 301 302 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 303 enum CPUTopoLevel topo_level) 304 { 305 switch (topo_level) { 306 case CPU_TOPO_LEVEL_SMT: 307 return 1; 308 case CPU_TOPO_LEVEL_CORE: 309 return topo_info->threads_per_core; 310 case CPU_TOPO_LEVEL_MODULE: 311 return topo_info->threads_per_core * topo_info->cores_per_module; 312 case CPU_TOPO_LEVEL_DIE: 313 return topo_info->threads_per_core * topo_info->cores_per_module * 314 topo_info->modules_per_die; 315 case CPU_TOPO_LEVEL_PACKAGE: 316 return topo_info->threads_per_core * topo_info->cores_per_module * 317 topo_info->modules_per_die * topo_info->dies_per_pkg; 318 default: 319 g_assert_not_reached(); 320 } 321 return 0; 322 } 323 324 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 325 enum CPUTopoLevel topo_level) 326 { 327 switch (topo_level) { 328 case CPU_TOPO_LEVEL_SMT: 329 return 0; 330 case CPU_TOPO_LEVEL_CORE: 331 return apicid_core_offset(topo_info); 332 case CPU_TOPO_LEVEL_MODULE: 333 return apicid_module_offset(topo_info); 334 case CPU_TOPO_LEVEL_DIE: 335 return apicid_die_offset(topo_info); 336 case CPU_TOPO_LEVEL_PACKAGE: 337 return apicid_pkg_offset(topo_info); 338 default: 339 g_assert_not_reached(); 340 } 341 return 0; 342 } 343 344 static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) 345 { 346 switch (topo_level) { 347 case CPU_TOPO_LEVEL_INVALID: 348 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 349 case CPU_TOPO_LEVEL_SMT: 350 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 351 case CPU_TOPO_LEVEL_CORE: 352 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 353 case CPU_TOPO_LEVEL_MODULE: 354 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 355 case CPU_TOPO_LEVEL_DIE: 356 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 357 default: 358 /* Other types are not supported in QEMU. */ 359 g_assert_not_reached(); 360 } 361 return 0; 362 } 363 364 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 365 X86CPUTopoInfo *topo_info, 366 uint32_t *eax, uint32_t *ebx, 367 uint32_t *ecx, uint32_t *edx) 368 { 369 X86CPU *cpu = env_archcpu(env); 370 unsigned long level, next_level; 371 uint32_t num_threads_next_level, offset_next_level; 372 373 assert(count + 1 < CPU_TOPO_LEVEL_MAX); 374 375 /* 376 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 377 * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). 378 */ 379 level = CPU_TOPO_LEVEL_INVALID; 380 for (int i = 0; i <= count; i++) { 381 level = find_next_bit(env->avail_cpu_topo, 382 CPU_TOPO_LEVEL_PACKAGE, 383 level + 1); 384 385 /* 386 * CPUID[0x1f] doesn't explicitly encode the package level, 387 * and it just encodes the invalid level (all fields are 0) 388 * into the last subleaf of 0x1f. 389 */ 390 if (level == CPU_TOPO_LEVEL_PACKAGE) { 391 level = CPU_TOPO_LEVEL_INVALID; 392 break; 393 } 394 } 395 396 if (level == CPU_TOPO_LEVEL_INVALID) { 397 num_threads_next_level = 0; 398 offset_next_level = 0; 399 } else { 400 next_level = find_next_bit(env->avail_cpu_topo, 401 CPU_TOPO_LEVEL_PACKAGE, 402 level + 1); 403 num_threads_next_level = num_threads_by_topo_level(topo_info, 404 next_level); 405 offset_next_level = apicid_offset_by_topo_level(topo_info, 406 next_level); 407 } 408 409 *eax = offset_next_level; 410 /* The count (bits 15-00) doesn't need to be reliable. */ 411 *ebx = num_threads_next_level & 0xffff; 412 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 413 *edx = cpu->apic_id; 414 415 assert(!(*eax & ~0x1f)); 416 } 417 418 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 419 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 420 { 421 assert(cache->size % 1024 == 0); 422 assert(cache->lines_per_tag > 0); 423 assert(cache->associativity > 0); 424 assert(cache->line_size > 0); 425 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 426 (cache->lines_per_tag << 8) | (cache->line_size); 427 } 428 429 #define ASSOC_FULL 0xFF 430 431 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 432 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 433 a == 2 ? 0x2 : \ 434 a == 4 ? 0x4 : \ 435 a == 8 ? 0x6 : \ 436 a == 16 ? 0x8 : \ 437 a == 32 ? 0xA : \ 438 a == 48 ? 0xB : \ 439 a == 64 ? 0xC : \ 440 a == 96 ? 0xD : \ 441 a == 128 ? 0xE : \ 442 a == ASSOC_FULL ? 0xF : \ 443 0 /* invalid value */) 444 445 /* 446 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 447 * @l3 can be NULL. 448 */ 449 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 450 CPUCacheInfo *l3, 451 uint32_t *ecx, uint32_t *edx) 452 { 453 assert(l2->size % 1024 == 0); 454 assert(l2->associativity > 0); 455 assert(l2->lines_per_tag > 0); 456 assert(l2->line_size > 0); 457 *ecx = ((l2->size / 1024) << 16) | 458 (AMD_ENC_ASSOC(l2->associativity) << 12) | 459 (l2->lines_per_tag << 8) | (l2->line_size); 460 461 if (l3) { 462 assert(l3->size % (512 * 1024) == 0); 463 assert(l3->associativity > 0); 464 assert(l3->lines_per_tag > 0); 465 assert(l3->line_size > 0); 466 *edx = ((l3->size / (512 * 1024)) << 18) | 467 (AMD_ENC_ASSOC(l3->associativity) << 12) | 468 (l3->lines_per_tag << 8) | (l3->line_size); 469 } else { 470 *edx = 0; 471 } 472 } 473 474 /* Encode cache info for CPUID[8000001D] */ 475 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 476 X86CPUTopoInfo *topo_info, 477 uint32_t *eax, uint32_t *ebx, 478 uint32_t *ecx, uint32_t *edx) 479 { 480 assert(cache->size == cache->line_size * cache->associativity * 481 cache->partitions * cache->sets); 482 483 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 484 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 485 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 486 487 assert(cache->line_size > 0); 488 assert(cache->partitions > 0); 489 assert(cache->associativity > 0); 490 /* We don't implement fully-associative caches */ 491 assert(cache->associativity < cache->sets); 492 *ebx = (cache->line_size - 1) | 493 ((cache->partitions - 1) << 12) | 494 ((cache->associativity - 1) << 22); 495 496 assert(cache->sets > 0); 497 *ecx = cache->sets - 1; 498 499 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 500 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 501 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 502 } 503 504 /* Encode cache info for CPUID[8000001E] */ 505 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 506 uint32_t *eax, uint32_t *ebx, 507 uint32_t *ecx, uint32_t *edx) 508 { 509 X86CPUTopoIDs topo_ids; 510 511 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 512 513 *eax = cpu->apic_id; 514 515 /* 516 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 517 * Read-only. Reset: 0000_XXXXh. 518 * See Core::X86::Cpuid::ExtApicId. 519 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 520 * Bits Description 521 * 31:16 Reserved. 522 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 523 * The number of threads per core is ThreadsPerCore+1. 524 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 525 * 526 * NOTE: CoreId is already part of apic_id. Just use it. We can 527 * use all the 8 bits to represent the core_id here. 528 */ 529 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 530 531 /* 532 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 533 * Read-only. Reset: 0000_0XXXh. 534 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 535 * Bits Description 536 * 31:11 Reserved. 537 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 538 * ValidValues: 539 * Value Description 540 * 0h 1 node per processor. 541 * 7h-1h Reserved. 542 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 543 * 544 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 545 * But users can create more nodes than the actual hardware can 546 * support. To genaralize we can use all the upper 8 bits for nodes. 547 * NodeId is combination of node and socket_id which is already decoded 548 * in apic_id. Just use it by shifting. 549 */ 550 if (cpu->legacy_multi_node) { 551 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 552 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 553 } else { 554 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 555 } 556 557 *edx = 0; 558 } 559 560 /* 561 * Definitions of the hardcoded cache entries we expose: 562 * These are legacy cache values. If there is a need to change any 563 * of these values please use builtin_x86_defs 564 */ 565 566 /* L1 data cache: */ 567 static CPUCacheInfo legacy_l1d_cache = { 568 .type = DATA_CACHE, 569 .level = 1, 570 .size = 32 * KiB, 571 .self_init = 1, 572 .line_size = 64, 573 .associativity = 8, 574 .sets = 64, 575 .partitions = 1, 576 .no_invd_sharing = true, 577 .share_level = CPU_TOPO_LEVEL_CORE, 578 }; 579 580 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 581 static CPUCacheInfo legacy_l1d_cache_amd = { 582 .type = DATA_CACHE, 583 .level = 1, 584 .size = 64 * KiB, 585 .self_init = 1, 586 .line_size = 64, 587 .associativity = 2, 588 .sets = 512, 589 .partitions = 1, 590 .lines_per_tag = 1, 591 .no_invd_sharing = true, 592 .share_level = CPU_TOPO_LEVEL_CORE, 593 }; 594 595 /* L1 instruction cache: */ 596 static CPUCacheInfo legacy_l1i_cache = { 597 .type = INSTRUCTION_CACHE, 598 .level = 1, 599 .size = 32 * KiB, 600 .self_init = 1, 601 .line_size = 64, 602 .associativity = 8, 603 .sets = 64, 604 .partitions = 1, 605 .no_invd_sharing = true, 606 .share_level = CPU_TOPO_LEVEL_CORE, 607 }; 608 609 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 610 static CPUCacheInfo legacy_l1i_cache_amd = { 611 .type = INSTRUCTION_CACHE, 612 .level = 1, 613 .size = 64 * KiB, 614 .self_init = 1, 615 .line_size = 64, 616 .associativity = 2, 617 .sets = 512, 618 .partitions = 1, 619 .lines_per_tag = 1, 620 .no_invd_sharing = true, 621 .share_level = CPU_TOPO_LEVEL_CORE, 622 }; 623 624 /* Level 2 unified cache: */ 625 static CPUCacheInfo legacy_l2_cache = { 626 .type = UNIFIED_CACHE, 627 .level = 2, 628 .size = 4 * MiB, 629 .self_init = 1, 630 .line_size = 64, 631 .associativity = 16, 632 .sets = 4096, 633 .partitions = 1, 634 .no_invd_sharing = true, 635 .share_level = CPU_TOPO_LEVEL_CORE, 636 }; 637 638 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 639 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 640 .type = UNIFIED_CACHE, 641 .level = 2, 642 .size = 2 * MiB, 643 .line_size = 64, 644 .associativity = 8, 645 .share_level = CPU_TOPO_LEVEL_INVALID, 646 }; 647 648 649 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 650 static CPUCacheInfo legacy_l2_cache_amd = { 651 .type = UNIFIED_CACHE, 652 .level = 2, 653 .size = 512 * KiB, 654 .line_size = 64, 655 .lines_per_tag = 1, 656 .associativity = 16, 657 .sets = 512, 658 .partitions = 1, 659 .share_level = CPU_TOPO_LEVEL_CORE, 660 }; 661 662 /* Level 3 unified cache: */ 663 static CPUCacheInfo legacy_l3_cache = { 664 .type = UNIFIED_CACHE, 665 .level = 3, 666 .size = 16 * MiB, 667 .line_size = 64, 668 .associativity = 16, 669 .sets = 16384, 670 .partitions = 1, 671 .lines_per_tag = 1, 672 .self_init = true, 673 .inclusive = true, 674 .complex_indexing = true, 675 .share_level = CPU_TOPO_LEVEL_DIE, 676 }; 677 678 /* TLB definitions: */ 679 680 #define L1_DTLB_2M_ASSOC 1 681 #define L1_DTLB_2M_ENTRIES 255 682 #define L1_DTLB_4K_ASSOC 1 683 #define L1_DTLB_4K_ENTRIES 255 684 685 #define L1_ITLB_2M_ASSOC 1 686 #define L1_ITLB_2M_ENTRIES 255 687 #define L1_ITLB_4K_ASSOC 1 688 #define L1_ITLB_4K_ENTRIES 255 689 690 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 691 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 692 #define L2_DTLB_4K_ASSOC 4 693 #define L2_DTLB_4K_ENTRIES 512 694 695 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 696 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 697 #define L2_ITLB_4K_ASSOC 4 698 #define L2_ITLB_4K_ENTRIES 512 699 700 /* CPUID Leaf 0x14 constants: */ 701 #define INTEL_PT_MAX_SUBLEAF 0x1 702 /* 703 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 704 * MSR can be accessed; 705 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 706 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 707 * of Intel PT MSRs across warm reset; 708 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 709 */ 710 #define INTEL_PT_MINIMAL_EBX 0xf 711 /* 712 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 713 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 714 * accessed; 715 * bit[01]: ToPA tables can hold any number of output entries, up to the 716 * maximum allowed by the MaskOrTableOffset field of 717 * IA32_RTIT_OUTPUT_MASK_PTRS; 718 * bit[02]: Support Single-Range Output scheme; 719 */ 720 #define INTEL_PT_MINIMAL_ECX 0x7 721 /* generated packets which contain IP payloads have LIP values */ 722 #define INTEL_PT_IP_LIP (1 << 31) 723 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 724 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 725 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 726 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 727 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 728 729 /* CPUID Leaf 0x1D constants: */ 730 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 731 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 732 #define INTEL_AMX_BYTES_PER_TILE 0x400 733 #define INTEL_AMX_BYTES_PER_ROW 0x40 734 #define INTEL_AMX_TILE_MAX_NAMES 0x8 735 #define INTEL_AMX_TILE_MAX_ROWS 0x10 736 737 /* CPUID Leaf 0x1E constants: */ 738 #define INTEL_AMX_TMUL_MAX_K 0x10 739 #define INTEL_AMX_TMUL_MAX_N 0x40 740 741 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 742 uint32_t vendor2, uint32_t vendor3) 743 { 744 int i; 745 for (i = 0; i < 4; i++) { 746 dst[i] = vendor1 >> (8 * i); 747 dst[i + 4] = vendor2 >> (8 * i); 748 dst[i + 8] = vendor3 >> (8 * i); 749 } 750 dst[CPUID_VENDOR_SZ] = '\0'; 751 } 752 753 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 754 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 755 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 756 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 757 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 758 CPUID_PSE36 | CPUID_FXSR) 759 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 760 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 761 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 762 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 763 CPUID_PAE | CPUID_SEP | CPUID_APIC) 764 765 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 766 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 767 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 768 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 769 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 770 /* partly implemented: 771 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 772 /* missing: 773 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 774 775 /* 776 * Kernel-only features that can be shown to usermode programs even if 777 * they aren't actually supported by TCG, because qemu-user only runs 778 * in CPL=3; remove them if they are ever implemented for system emulation. 779 */ 780 #if defined CONFIG_USER_ONLY 781 #define CPUID_EXT_KERNEL_FEATURES \ 782 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 783 #else 784 #define CPUID_EXT_KERNEL_FEATURES 0 785 #endif 786 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 787 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 788 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 789 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 790 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 791 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 792 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 793 /* missing: 794 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 795 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 796 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 797 CPUID_EXT_TSC_DEADLINE_TIMER 798 */ 799 800 #ifdef TARGET_X86_64 801 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 802 #else 803 #define TCG_EXT2_X86_64_FEATURES 0 804 #endif 805 806 /* 807 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 808 * in usermode or by 32-bit programs. Those are added to supported 809 * TCG features unconditionally in user-mode emulation mode. This may 810 * indeed seem strange or incorrect, but it works because code running 811 * under usermode emulation cannot access them. 812 * 813 * Even for long mode, qemu-i386 is not running "a userspace program on a 814 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 815 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 816 * but again the difference is only visible in kernel mode. 817 */ 818 #if defined CONFIG_LINUX_USER 819 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 820 #elif defined CONFIG_USER_ONLY 821 /* FIXME: Long mode not yet supported for i386 bsd-user */ 822 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 823 #else 824 #define CPUID_EXT2_KERNEL_FEATURES 0 825 #endif 826 827 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 828 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 829 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 830 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 831 CPUID_EXT2_KERNEL_FEATURES) 832 833 #if defined CONFIG_USER_ONLY 834 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 835 #else 836 #define CPUID_EXT3_KERNEL_FEATURES 0 837 #endif 838 839 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 840 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 841 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 842 843 #define TCG_EXT4_FEATURES 0 844 845 #if defined CONFIG_USER_ONLY 846 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 847 #else 848 #define CPUID_SVM_KERNEL_FEATURES 0 849 #endif 850 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 851 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 852 853 #define TCG_KVM_FEATURES 0 854 855 #if defined CONFIG_USER_ONLY 856 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 857 #else 858 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 859 #endif 860 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 861 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 862 CPUID_7_0_EBX_CLFLUSHOPT | \ 863 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 864 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 865 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 866 /* missing: 867 CPUID_7_0_EBX_HLE 868 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 869 870 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 871 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 872 #else 873 #define TCG_7_0_ECX_RDPID 0 874 #endif 875 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 876 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 877 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 878 TCG_7_0_ECX_RDPID) 879 880 #if defined CONFIG_USER_ONLY 881 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 882 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 883 #else 884 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 885 #endif 886 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 887 888 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 889 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 890 #define TCG_7_1_EDX_FEATURES 0 891 #define TCG_7_2_EDX_FEATURES 0 892 #define TCG_APM_FEATURES 0 893 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 894 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 895 /* missing: 896 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 897 #define TCG_14_0_ECX_FEATURES 0 898 #define TCG_SGX_12_0_EAX_FEATURES 0 899 #define TCG_SGX_12_0_EBX_FEATURES 0 900 #define TCG_SGX_12_1_EAX_FEATURES 0 901 902 #if defined CONFIG_USER_ONLY 903 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 904 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 905 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 906 CPUID_8000_0008_EBX_AMD_PSFD) 907 #else 908 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 909 #endif 910 911 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 912 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 913 914 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 915 [FEAT_1_EDX] = { 916 .type = CPUID_FEATURE_WORD, 917 .feat_names = { 918 "fpu", "vme", "de", "pse", 919 "tsc", "msr", "pae", "mce", 920 "cx8", "apic", NULL, "sep", 921 "mtrr", "pge", "mca", "cmov", 922 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 923 NULL, "ds" /* Intel dts */, "acpi", "mmx", 924 "fxsr", "sse", "sse2", "ss", 925 "ht" /* Intel htt */, "tm", "ia64", "pbe", 926 }, 927 .cpuid = {.eax = 1, .reg = R_EDX, }, 928 .tcg_features = TCG_FEATURES, 929 .no_autoenable_flags = CPUID_HT, 930 }, 931 [FEAT_1_ECX] = { 932 .type = CPUID_FEATURE_WORD, 933 .feat_names = { 934 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 935 "ds-cpl", "vmx", "smx", "est", 936 "tm2", "ssse3", "cid", NULL, 937 "fma", "cx16", "xtpr", "pdcm", 938 NULL, "pcid", "dca", "sse4.1", 939 "sse4.2", "x2apic", "movbe", "popcnt", 940 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 941 "avx", "f16c", "rdrand", "hypervisor", 942 }, 943 .cpuid = { .eax = 1, .reg = R_ECX, }, 944 .tcg_features = TCG_EXT_FEATURES, 945 }, 946 /* Feature names that are already defined on feature_name[] but 947 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 948 * names on feat_names below. They are copied automatically 949 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 950 */ 951 [FEAT_8000_0001_EDX] = { 952 .type = CPUID_FEATURE_WORD, 953 .feat_names = { 954 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 955 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 956 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 957 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 958 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 959 "nx", NULL, "mmxext", NULL /* mmx */, 960 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 961 NULL, "lm", "3dnowext", "3dnow", 962 }, 963 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 964 .tcg_features = TCG_EXT2_FEATURES, 965 }, 966 [FEAT_8000_0001_ECX] = { 967 .type = CPUID_FEATURE_WORD, 968 .feat_names = { 969 "lahf-lm", "cmp-legacy", "svm", "extapic", 970 "cr8legacy", "abm", "sse4a", "misalignsse", 971 "3dnowprefetch", "osvw", "ibs", "xop", 972 "skinit", "wdt", NULL, "lwp", 973 "fma4", "tce", NULL, "nodeid-msr", 974 NULL, "tbm", "topoext", "perfctr-core", 975 "perfctr-nb", NULL, NULL, NULL, 976 NULL, NULL, NULL, NULL, 977 }, 978 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 979 .tcg_features = TCG_EXT3_FEATURES, 980 /* 981 * TOPOEXT is always allowed but can't be enabled blindly by 982 * "-cpu host", as it requires consistent cache topology info 983 * to be provided so it doesn't confuse guests. 984 */ 985 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 986 }, 987 [FEAT_C000_0001_EDX] = { 988 .type = CPUID_FEATURE_WORD, 989 .feat_names = { 990 NULL, NULL, "xstore", "xstore-en", 991 NULL, NULL, "xcrypt", "xcrypt-en", 992 "ace2", "ace2-en", "phe", "phe-en", 993 "pmm", "pmm-en", NULL, NULL, 994 NULL, NULL, NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 }, 999 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1000 .tcg_features = TCG_EXT4_FEATURES, 1001 }, 1002 [FEAT_KVM] = { 1003 .type = CPUID_FEATURE_WORD, 1004 .feat_names = { 1005 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1006 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1007 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1008 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1009 NULL, NULL, NULL, NULL, 1010 NULL, NULL, NULL, NULL, 1011 "kvmclock-stable-bit", NULL, NULL, NULL, 1012 NULL, NULL, NULL, NULL, 1013 }, 1014 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1015 .tcg_features = TCG_KVM_FEATURES, 1016 }, 1017 [FEAT_KVM_HINTS] = { 1018 .type = CPUID_FEATURE_WORD, 1019 .feat_names = { 1020 "kvm-hint-dedicated", NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 }, 1029 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1030 .tcg_features = TCG_KVM_FEATURES, 1031 /* 1032 * KVM hints aren't auto-enabled by -cpu host, they need to be 1033 * explicitly enabled in the command-line. 1034 */ 1035 .no_autoenable_flags = ~0U, 1036 }, 1037 [FEAT_SVM] = { 1038 .type = CPUID_FEATURE_WORD, 1039 .feat_names = { 1040 "npt", "lbrv", "svm-lock", "nrip-save", 1041 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1042 NULL, NULL, "pause-filter", NULL, 1043 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1044 "vgif", NULL, NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 NULL, "vnmi", NULL, NULL, 1047 "svme-addr-chk", NULL, NULL, NULL, 1048 }, 1049 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1050 .tcg_features = TCG_SVM_FEATURES, 1051 }, 1052 [FEAT_7_0_EBX] = { 1053 .type = CPUID_FEATURE_WORD, 1054 .feat_names = { 1055 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1056 "hle", "avx2", "fdp-excptn-only", "smep", 1057 "bmi2", "erms", "invpcid", "rtm", 1058 NULL, "zero-fcs-fds", "mpx", NULL, 1059 "avx512f", "avx512dq", "rdseed", "adx", 1060 "smap", "avx512ifma", "pcommit", "clflushopt", 1061 "clwb", "intel-pt", "avx512pf", "avx512er", 1062 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1063 }, 1064 .cpuid = { 1065 .eax = 7, 1066 .needs_ecx = true, .ecx = 0, 1067 .reg = R_EBX, 1068 }, 1069 .tcg_features = TCG_7_0_EBX_FEATURES, 1070 }, 1071 [FEAT_7_0_ECX] = { 1072 .type = CPUID_FEATURE_WORD, 1073 .feat_names = { 1074 NULL, "avx512vbmi", "umip", "pku", 1075 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1076 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1077 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1078 "la57", NULL, NULL, NULL, 1079 NULL, NULL, "rdpid", NULL, 1080 "bus-lock-detect", "cldemote", NULL, "movdiri", 1081 "movdir64b", NULL, "sgxlc", "pks", 1082 }, 1083 .cpuid = { 1084 .eax = 7, 1085 .needs_ecx = true, .ecx = 0, 1086 .reg = R_ECX, 1087 }, 1088 .tcg_features = TCG_7_0_ECX_FEATURES, 1089 }, 1090 [FEAT_7_0_EDX] = { 1091 .type = CPUID_FEATURE_WORD, 1092 .feat_names = { 1093 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1094 "fsrm", NULL, NULL, NULL, 1095 "avx512-vp2intersect", NULL, "md-clear", NULL, 1096 NULL, NULL, "serialize", NULL, 1097 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1098 NULL, NULL, "amx-bf16", "avx512-fp16", 1099 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1100 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1101 }, 1102 .cpuid = { 1103 .eax = 7, 1104 .needs_ecx = true, .ecx = 0, 1105 .reg = R_EDX, 1106 }, 1107 .tcg_features = TCG_7_0_EDX_FEATURES, 1108 }, 1109 [FEAT_7_1_EAX] = { 1110 .type = CPUID_FEATURE_WORD, 1111 .feat_names = { 1112 NULL, NULL, NULL, NULL, 1113 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1114 NULL, NULL, "fzrm", "fsrs", 1115 "fsrc", NULL, NULL, NULL, 1116 NULL, "fred", "lkgs", "wrmsrns", 1117 NULL, "amx-fp16", NULL, "avx-ifma", 1118 NULL, NULL, "lam", NULL, 1119 NULL, NULL, NULL, NULL, 1120 }, 1121 .cpuid = { 1122 .eax = 7, 1123 .needs_ecx = true, .ecx = 1, 1124 .reg = R_EAX, 1125 }, 1126 .tcg_features = TCG_7_1_EAX_FEATURES, 1127 }, 1128 [FEAT_7_1_EDX] = { 1129 .type = CPUID_FEATURE_WORD, 1130 .feat_names = { 1131 NULL, NULL, NULL, NULL, 1132 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1133 "amx-complex", NULL, "avx-vnni-int16", NULL, 1134 NULL, NULL, "prefetchiti", NULL, 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 }, 1140 .cpuid = { 1141 .eax = 7, 1142 .needs_ecx = true, .ecx = 1, 1143 .reg = R_EDX, 1144 }, 1145 .tcg_features = TCG_7_1_EDX_FEATURES, 1146 }, 1147 [FEAT_7_2_EDX] = { 1148 .type = CPUID_FEATURE_WORD, 1149 .feat_names = { 1150 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1151 "bhi-ctrl", "mcdt-no", NULL, NULL, 1152 NULL, NULL, NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 }, 1159 .cpuid = { 1160 .eax = 7, 1161 .needs_ecx = true, .ecx = 2, 1162 .reg = R_EDX, 1163 }, 1164 .tcg_features = TCG_7_2_EDX_FEATURES, 1165 }, 1166 [FEAT_8000_0007_EDX] = { 1167 .type = CPUID_FEATURE_WORD, 1168 .feat_names = { 1169 NULL, NULL, NULL, NULL, 1170 NULL, NULL, NULL, NULL, 1171 "invtsc", NULL, NULL, NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 }, 1178 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1179 .tcg_features = TCG_APM_FEATURES, 1180 .unmigratable_flags = CPUID_APM_INVTSC, 1181 }, 1182 [FEAT_8000_0007_EBX] = { 1183 .type = CPUID_FEATURE_WORD, 1184 .feat_names = { 1185 "overflow-recov", "succor", NULL, NULL, 1186 NULL, NULL, NULL, NULL, 1187 NULL, NULL, NULL, NULL, 1188 NULL, NULL, NULL, NULL, 1189 NULL, NULL, NULL, NULL, 1190 NULL, NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 }, 1194 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1195 .tcg_features = 0, 1196 .unmigratable_flags = 0, 1197 }, 1198 [FEAT_8000_0008_EBX] = { 1199 .type = CPUID_FEATURE_WORD, 1200 .feat_names = { 1201 "clzero", NULL, "xsaveerptr", NULL, 1202 NULL, NULL, NULL, NULL, 1203 NULL, "wbnoinvd", NULL, NULL, 1204 "ibpb", NULL, "ibrs", "amd-stibp", 1205 NULL, "stibp-always-on", NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1208 "amd-psfd", NULL, NULL, NULL, 1209 }, 1210 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1211 .tcg_features = TCG_8000_0008_EBX, 1212 .unmigratable_flags = 0, 1213 }, 1214 [FEAT_8000_0021_EAX] = { 1215 .type = CPUID_FEATURE_WORD, 1216 .feat_names = { 1217 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1218 NULL, NULL, "null-sel-clr-base", NULL, 1219 "auto-ibrs", NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, "sbpb", 1224 "ibpb-brtype", NULL, NULL, NULL, 1225 }, 1226 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1227 .tcg_features = 0, 1228 .unmigratable_flags = 0, 1229 }, 1230 [FEAT_XSAVE] = { 1231 .type = CPUID_FEATURE_WORD, 1232 .feat_names = { 1233 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1234 "xfd", NULL, NULL, NULL, 1235 NULL, NULL, NULL, NULL, 1236 NULL, NULL, NULL, NULL, 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 }, 1242 .cpuid = { 1243 .eax = 0xd, 1244 .needs_ecx = true, .ecx = 1, 1245 .reg = R_EAX, 1246 }, 1247 .tcg_features = TCG_XSAVE_FEATURES, 1248 }, 1249 [FEAT_XSAVE_XSS_LO] = { 1250 .type = CPUID_FEATURE_WORD, 1251 .feat_names = { 1252 NULL, NULL, NULL, NULL, 1253 NULL, NULL, NULL, NULL, 1254 NULL, NULL, NULL, NULL, 1255 NULL, NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 }, 1261 .cpuid = { 1262 .eax = 0xD, 1263 .needs_ecx = true, 1264 .ecx = 1, 1265 .reg = R_ECX, 1266 }, 1267 }, 1268 [FEAT_XSAVE_XSS_HI] = { 1269 .type = CPUID_FEATURE_WORD, 1270 .cpuid = { 1271 .eax = 0xD, 1272 .needs_ecx = true, 1273 .ecx = 1, 1274 .reg = R_EDX 1275 }, 1276 }, 1277 [FEAT_6_EAX] = { 1278 .type = CPUID_FEATURE_WORD, 1279 .feat_names = { 1280 NULL, NULL, "arat", NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, NULL, NULL, NULL, 1287 NULL, NULL, NULL, NULL, 1288 }, 1289 .cpuid = { .eax = 6, .reg = R_EAX, }, 1290 .tcg_features = TCG_6_EAX_FEATURES, 1291 }, 1292 [FEAT_XSAVE_XCR0_LO] = { 1293 .type = CPUID_FEATURE_WORD, 1294 .cpuid = { 1295 .eax = 0xD, 1296 .needs_ecx = true, .ecx = 0, 1297 .reg = R_EAX, 1298 }, 1299 .tcg_features = ~0U, 1300 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1301 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1302 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1303 XSTATE_PKRU_MASK, 1304 }, 1305 [FEAT_XSAVE_XCR0_HI] = { 1306 .type = CPUID_FEATURE_WORD, 1307 .cpuid = { 1308 .eax = 0xD, 1309 .needs_ecx = true, .ecx = 0, 1310 .reg = R_EDX, 1311 }, 1312 .tcg_features = ~0U, 1313 }, 1314 /*Below are MSR exposed features*/ 1315 [FEAT_ARCH_CAPABILITIES] = { 1316 .type = MSR_FEATURE_WORD, 1317 .feat_names = { 1318 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1319 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1320 "taa-no", NULL, NULL, NULL, 1321 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1322 NULL, "fb-clear", NULL, NULL, 1323 NULL, NULL, NULL, NULL, 1324 "pbrsb-no", NULL, "gds-no", "rfds-no", 1325 "rfds-clear", NULL, NULL, NULL, 1326 }, 1327 .msr = { 1328 .index = MSR_IA32_ARCH_CAPABILITIES, 1329 }, 1330 /* 1331 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1332 * cannot be read from user mode. Therefore, it has no impact 1333 > on any user-mode operation, and warnings about unsupported 1334 * features do not matter. 1335 */ 1336 .tcg_features = ~0U, 1337 }, 1338 [FEAT_CORE_CAPABILITY] = { 1339 .type = MSR_FEATURE_WORD, 1340 .feat_names = { 1341 NULL, NULL, NULL, NULL, 1342 NULL, "split-lock-detect", NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 }, 1350 .msr = { 1351 .index = MSR_IA32_CORE_CAPABILITY, 1352 }, 1353 }, 1354 [FEAT_PERF_CAPABILITIES] = { 1355 .type = MSR_FEATURE_WORD, 1356 .feat_names = { 1357 NULL, NULL, NULL, NULL, 1358 NULL, NULL, NULL, NULL, 1359 NULL, NULL, NULL, NULL, 1360 NULL, "full-width-write", NULL, NULL, 1361 NULL, NULL, NULL, NULL, 1362 NULL, NULL, NULL, NULL, 1363 NULL, NULL, NULL, NULL, 1364 NULL, NULL, NULL, NULL, 1365 }, 1366 .msr = { 1367 .index = MSR_IA32_PERF_CAPABILITIES, 1368 }, 1369 }, 1370 1371 [FEAT_VMX_PROCBASED_CTLS] = { 1372 .type = MSR_FEATURE_WORD, 1373 .feat_names = { 1374 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1375 NULL, NULL, NULL, "vmx-hlt-exit", 1376 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1377 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1378 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1379 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1380 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1381 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1382 }, 1383 .msr = { 1384 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1385 } 1386 }, 1387 1388 [FEAT_VMX_SECONDARY_CTLS] = { 1389 .type = MSR_FEATURE_WORD, 1390 .feat_names = { 1391 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1392 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1393 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1394 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1395 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1396 "vmx-xsaves", NULL, NULL, NULL, 1397 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1398 NULL, NULL, NULL, NULL, 1399 }, 1400 .msr = { 1401 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1402 } 1403 }, 1404 1405 [FEAT_VMX_PINBASED_CTLS] = { 1406 .type = MSR_FEATURE_WORD, 1407 .feat_names = { 1408 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1409 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 }, 1417 .msr = { 1418 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1419 } 1420 }, 1421 1422 [FEAT_VMX_EXIT_CTLS] = { 1423 .type = MSR_FEATURE_WORD, 1424 /* 1425 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1426 * the LM CPUID bit. 1427 */ 1428 .feat_names = { 1429 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1430 NULL, NULL, NULL, NULL, 1431 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1432 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1433 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1434 "vmx-exit-save-efer", "vmx-exit-load-efer", 1435 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1436 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1437 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1438 }, 1439 .msr = { 1440 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1441 } 1442 }, 1443 1444 [FEAT_VMX_ENTRY_CTLS] = { 1445 .type = MSR_FEATURE_WORD, 1446 .feat_names = { 1447 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1448 NULL, NULL, NULL, NULL, 1449 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1450 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1451 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1452 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1453 NULL, NULL, NULL, NULL, 1454 NULL, NULL, NULL, NULL, 1455 }, 1456 .msr = { 1457 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1458 } 1459 }, 1460 1461 [FEAT_VMX_MISC] = { 1462 .type = MSR_FEATURE_WORD, 1463 .feat_names = { 1464 NULL, NULL, NULL, NULL, 1465 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1466 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1467 NULL, NULL, NULL, NULL, 1468 NULL, NULL, NULL, NULL, 1469 NULL, NULL, NULL, NULL, 1470 NULL, NULL, NULL, NULL, 1471 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1472 }, 1473 .msr = { 1474 .index = MSR_IA32_VMX_MISC, 1475 } 1476 }, 1477 1478 [FEAT_VMX_EPT_VPID_CAPS] = { 1479 .type = MSR_FEATURE_WORD, 1480 .feat_names = { 1481 "vmx-ept-execonly", NULL, NULL, NULL, 1482 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1483 NULL, NULL, NULL, NULL, 1484 NULL, NULL, NULL, NULL, 1485 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1486 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1487 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1488 NULL, NULL, NULL, NULL, 1489 "vmx-invvpid", NULL, NULL, NULL, 1490 NULL, NULL, NULL, NULL, 1491 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1492 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1493 NULL, NULL, NULL, NULL, 1494 NULL, NULL, NULL, NULL, 1495 NULL, NULL, NULL, NULL, 1496 NULL, NULL, NULL, NULL, 1497 NULL, NULL, NULL, NULL, 1498 }, 1499 .msr = { 1500 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1501 } 1502 }, 1503 1504 [FEAT_VMX_BASIC] = { 1505 .type = MSR_FEATURE_WORD, 1506 .feat_names = { 1507 [54] = "vmx-ins-outs", 1508 [55] = "vmx-true-ctls", 1509 [56] = "vmx-any-errcode", 1510 [58] = "vmx-nested-exception", 1511 }, 1512 .msr = { 1513 .index = MSR_IA32_VMX_BASIC, 1514 }, 1515 /* Just to be safe - we don't support setting the MSEG version field. */ 1516 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1517 }, 1518 1519 [FEAT_VMX_VMFUNC] = { 1520 .type = MSR_FEATURE_WORD, 1521 .feat_names = { 1522 [0] = "vmx-eptp-switching", 1523 }, 1524 .msr = { 1525 .index = MSR_IA32_VMX_VMFUNC, 1526 } 1527 }, 1528 1529 [FEAT_14_0_ECX] = { 1530 .type = CPUID_FEATURE_WORD, 1531 .feat_names = { 1532 NULL, NULL, NULL, NULL, 1533 NULL, NULL, NULL, NULL, 1534 NULL, NULL, NULL, NULL, 1535 NULL, NULL, NULL, NULL, 1536 NULL, NULL, NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, "intel-pt-lip", 1540 }, 1541 .cpuid = { 1542 .eax = 0x14, 1543 .needs_ecx = true, .ecx = 0, 1544 .reg = R_ECX, 1545 }, 1546 .tcg_features = TCG_14_0_ECX_FEATURES, 1547 }, 1548 1549 [FEAT_SGX_12_0_EAX] = { 1550 .type = CPUID_FEATURE_WORD, 1551 .feat_names = { 1552 "sgx1", "sgx2", NULL, NULL, 1553 NULL, NULL, NULL, NULL, 1554 NULL, NULL, NULL, "sgx-edeccssa", 1555 NULL, NULL, NULL, NULL, 1556 NULL, NULL, NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 }, 1561 .cpuid = { 1562 .eax = 0x12, 1563 .needs_ecx = true, .ecx = 0, 1564 .reg = R_EAX, 1565 }, 1566 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1567 }, 1568 1569 [FEAT_SGX_12_0_EBX] = { 1570 .type = CPUID_FEATURE_WORD, 1571 .feat_names = { 1572 "sgx-exinfo" , NULL, NULL, NULL, 1573 NULL, NULL, NULL, NULL, 1574 NULL, NULL, NULL, NULL, 1575 NULL, NULL, NULL, NULL, 1576 NULL, NULL, NULL, NULL, 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 NULL, NULL, NULL, NULL, 1580 }, 1581 .cpuid = { 1582 .eax = 0x12, 1583 .needs_ecx = true, .ecx = 0, 1584 .reg = R_EBX, 1585 }, 1586 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1587 }, 1588 1589 [FEAT_SGX_12_1_EAX] = { 1590 .type = CPUID_FEATURE_WORD, 1591 .feat_names = { 1592 NULL, "sgx-debug", "sgx-mode64", NULL, 1593 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1594 NULL, NULL, "sgx-aex-notify", NULL, 1595 NULL, NULL, NULL, NULL, 1596 NULL, NULL, NULL, NULL, 1597 NULL, NULL, NULL, NULL, 1598 NULL, NULL, NULL, NULL, 1599 NULL, NULL, NULL, NULL, 1600 }, 1601 .cpuid = { 1602 .eax = 0x12, 1603 .needs_ecx = true, .ecx = 1, 1604 .reg = R_EAX, 1605 }, 1606 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1607 }, 1608 }; 1609 1610 typedef struct FeatureMask { 1611 FeatureWord index; 1612 uint64_t mask; 1613 } FeatureMask; 1614 1615 typedef struct FeatureDep { 1616 FeatureMask from, to; 1617 } FeatureDep; 1618 1619 static FeatureDep feature_dependencies[] = { 1620 { 1621 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1622 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1623 }, 1624 { 1625 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1626 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1627 }, 1628 { 1629 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1630 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1631 }, 1632 { 1633 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1634 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1635 }, 1636 { 1637 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1638 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1639 }, 1640 { 1641 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1642 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1643 }, 1644 { 1645 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1646 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1647 }, 1648 { 1649 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1650 .to = { FEAT_VMX_MISC, ~0ull }, 1651 }, 1652 { 1653 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1654 .to = { FEAT_VMX_BASIC, ~0ull }, 1655 }, 1656 { 1657 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1658 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1659 }, 1660 { 1661 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1662 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1663 }, 1664 { 1665 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1666 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1667 }, 1668 { 1669 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1670 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1671 }, 1672 { 1673 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1674 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1675 }, 1676 { 1677 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1678 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1679 }, 1680 { 1681 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1682 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1683 }, 1684 { 1685 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1686 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1687 }, 1688 { 1689 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1690 .to = { FEAT_14_0_ECX, ~0ull }, 1691 }, 1692 { 1693 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1694 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1695 }, 1696 { 1697 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1698 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1699 }, 1700 { 1701 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1702 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1703 }, 1704 { 1705 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1706 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1707 }, 1708 { 1709 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1710 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1711 }, 1712 { 1713 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1714 .to = { FEAT_SVM, ~0ull }, 1715 }, 1716 { 1717 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1718 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1719 }, 1720 { 1721 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1722 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1723 }, 1724 { 1725 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1726 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1727 }, 1728 { 1729 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1730 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1731 }, 1732 { 1733 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1734 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1735 }, 1736 { 1737 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1738 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1739 }, 1740 { 1741 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1742 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1743 }, 1744 { 1745 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1746 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1747 }, 1748 }; 1749 1750 typedef struct X86RegisterInfo32 { 1751 /* Name of register */ 1752 const char *name; 1753 /* QAPI enum value register */ 1754 X86CPURegister32 qapi_enum; 1755 } X86RegisterInfo32; 1756 1757 #define REGISTER(reg) \ 1758 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1759 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1760 REGISTER(EAX), 1761 REGISTER(ECX), 1762 REGISTER(EDX), 1763 REGISTER(EBX), 1764 REGISTER(ESP), 1765 REGISTER(EBP), 1766 REGISTER(ESI), 1767 REGISTER(EDI), 1768 }; 1769 #undef REGISTER 1770 1771 /* CPUID feature bits available in XSS */ 1772 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1773 1774 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1775 [XSTATE_FP_BIT] = { 1776 /* x87 FP state component is always enabled if XSAVE is supported */ 1777 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1778 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1779 }, 1780 [XSTATE_SSE_BIT] = { 1781 /* SSE state component is always enabled if XSAVE is supported */ 1782 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1783 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1784 }, 1785 [XSTATE_YMM_BIT] = 1786 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1787 .size = sizeof(XSaveAVX) }, 1788 [XSTATE_BNDREGS_BIT] = 1789 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1790 .size = sizeof(XSaveBNDREG) }, 1791 [XSTATE_BNDCSR_BIT] = 1792 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1793 .size = sizeof(XSaveBNDCSR) }, 1794 [XSTATE_OPMASK_BIT] = 1795 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1796 .size = sizeof(XSaveOpmask) }, 1797 [XSTATE_ZMM_Hi256_BIT] = 1798 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1799 .size = sizeof(XSaveZMM_Hi256) }, 1800 [XSTATE_Hi16_ZMM_BIT] = 1801 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1802 .size = sizeof(XSaveHi16_ZMM) }, 1803 [XSTATE_PKRU_BIT] = 1804 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1805 .size = sizeof(XSavePKRU) }, 1806 [XSTATE_ARCH_LBR_BIT] = { 1807 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1808 .offset = 0 /*supervisor mode component, offset = 0 */, 1809 .size = sizeof(XSavesArchLBR) }, 1810 [XSTATE_XTILE_CFG_BIT] = { 1811 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1812 .size = sizeof(XSaveXTILECFG), 1813 }, 1814 [XSTATE_XTILE_DATA_BIT] = { 1815 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1816 .size = sizeof(XSaveXTILEDATA) 1817 }, 1818 }; 1819 1820 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1821 { 1822 uint64_t ret = x86_ext_save_areas[0].size; 1823 const ExtSaveArea *esa; 1824 uint32_t offset = 0; 1825 int i; 1826 1827 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1828 esa = &x86_ext_save_areas[i]; 1829 if ((mask >> i) & 1) { 1830 offset = compacted ? ret : esa->offset; 1831 ret = MAX(ret, offset + esa->size); 1832 } 1833 } 1834 return ret; 1835 } 1836 1837 static inline bool accel_uses_host_cpuid(void) 1838 { 1839 return kvm_enabled() || hvf_enabled(); 1840 } 1841 1842 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1843 { 1844 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1845 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1846 } 1847 1848 /* Return name of 32-bit register, from a R_* constant */ 1849 static const char *get_register_name_32(unsigned int reg) 1850 { 1851 if (reg >= CPU_NB_REGS32) { 1852 return NULL; 1853 } 1854 return x86_reg_info_32[reg].name; 1855 } 1856 1857 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1858 { 1859 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1860 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1861 } 1862 1863 /* 1864 * Returns the set of feature flags that are supported and migratable by 1865 * QEMU, for a given FeatureWord. 1866 */ 1867 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1868 { 1869 FeatureWordInfo *wi = &feature_word_info[w]; 1870 CPUX86State *env = &cpu->env; 1871 uint64_t r = 0; 1872 int i; 1873 1874 for (i = 0; i < 64; i++) { 1875 uint64_t f = 1ULL << i; 1876 1877 /* If the feature name is known, it is implicitly considered migratable, 1878 * unless it is explicitly set in unmigratable_flags */ 1879 if ((wi->migratable_flags & f) || 1880 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1881 r |= f; 1882 } 1883 } 1884 1885 /* when tsc-khz is set explicitly, invtsc is migratable */ 1886 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1887 r |= CPUID_APM_INVTSC; 1888 } 1889 1890 return r; 1891 } 1892 1893 void host_cpuid(uint32_t function, uint32_t count, 1894 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1895 { 1896 uint32_t vec[4]; 1897 1898 #ifdef __x86_64__ 1899 asm volatile("cpuid" 1900 : "=a"(vec[0]), "=b"(vec[1]), 1901 "=c"(vec[2]), "=d"(vec[3]) 1902 : "0"(function), "c"(count) : "cc"); 1903 #elif defined(__i386__) 1904 asm volatile("pusha \n\t" 1905 "cpuid \n\t" 1906 "mov %%eax, 0(%2) \n\t" 1907 "mov %%ebx, 4(%2) \n\t" 1908 "mov %%ecx, 8(%2) \n\t" 1909 "mov %%edx, 12(%2) \n\t" 1910 "popa" 1911 : : "a"(function), "c"(count), "S"(vec) 1912 : "memory", "cc"); 1913 #else 1914 abort(); 1915 #endif 1916 1917 if (eax) 1918 *eax = vec[0]; 1919 if (ebx) 1920 *ebx = vec[1]; 1921 if (ecx) 1922 *ecx = vec[2]; 1923 if (edx) 1924 *edx = vec[3]; 1925 } 1926 1927 /* CPU class name definitions: */ 1928 1929 /* Return type name for a given CPU model name 1930 * Caller is responsible for freeing the returned string. 1931 */ 1932 static char *x86_cpu_type_name(const char *model_name) 1933 { 1934 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1935 } 1936 1937 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1938 { 1939 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1940 return object_class_by_name(typename); 1941 } 1942 1943 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1944 { 1945 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1946 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1947 return cpu_model_from_type(class_name); 1948 } 1949 1950 typedef struct X86CPUVersionDefinition { 1951 X86CPUVersion version; 1952 const char *alias; 1953 const char *note; 1954 PropValue *props; 1955 const CPUCaches *const cache_info; 1956 } X86CPUVersionDefinition; 1957 1958 /* Base definition for a CPU model */ 1959 typedef struct X86CPUDefinition { 1960 const char *name; 1961 uint32_t level; 1962 uint32_t xlevel; 1963 /* vendor is zero-terminated, 12 character ASCII string */ 1964 char vendor[CPUID_VENDOR_SZ + 1]; 1965 int family; 1966 int model; 1967 int stepping; 1968 FeatureWordArray features; 1969 const char *model_id; 1970 const CPUCaches *const cache_info; 1971 /* 1972 * Definitions for alternative versions of CPU model. 1973 * List is terminated by item with version == 0. 1974 * If NULL, version 1 will be registered automatically. 1975 */ 1976 const X86CPUVersionDefinition *versions; 1977 const char *deprecation_note; 1978 } X86CPUDefinition; 1979 1980 /* Reference to a specific CPU model version */ 1981 struct X86CPUModel { 1982 /* Base CPU definition */ 1983 const X86CPUDefinition *cpudef; 1984 /* CPU model version */ 1985 X86CPUVersion version; 1986 const char *note; 1987 /* 1988 * If true, this is an alias CPU model. 1989 * This matters only for "-cpu help" and query-cpu-definitions 1990 */ 1991 bool is_alias; 1992 }; 1993 1994 /* Get full model name for CPU version */ 1995 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1996 X86CPUVersion version) 1997 { 1998 assert(version > 0); 1999 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2000 } 2001 2002 static const X86CPUVersionDefinition * 2003 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2004 { 2005 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2006 static const X86CPUVersionDefinition default_version_list[] = { 2007 { 1 }, 2008 { /* end of list */ } 2009 }; 2010 2011 return def->versions ?: default_version_list; 2012 } 2013 2014 static const CPUCaches epyc_cache_info = { 2015 .l1d_cache = &(CPUCacheInfo) { 2016 .type = DATA_CACHE, 2017 .level = 1, 2018 .size = 32 * KiB, 2019 .line_size = 64, 2020 .associativity = 8, 2021 .partitions = 1, 2022 .sets = 64, 2023 .lines_per_tag = 1, 2024 .self_init = 1, 2025 .no_invd_sharing = true, 2026 .share_level = CPU_TOPO_LEVEL_CORE, 2027 }, 2028 .l1i_cache = &(CPUCacheInfo) { 2029 .type = INSTRUCTION_CACHE, 2030 .level = 1, 2031 .size = 64 * KiB, 2032 .line_size = 64, 2033 .associativity = 4, 2034 .partitions = 1, 2035 .sets = 256, 2036 .lines_per_tag = 1, 2037 .self_init = 1, 2038 .no_invd_sharing = true, 2039 .share_level = CPU_TOPO_LEVEL_CORE, 2040 }, 2041 .l2_cache = &(CPUCacheInfo) { 2042 .type = UNIFIED_CACHE, 2043 .level = 2, 2044 .size = 512 * KiB, 2045 .line_size = 64, 2046 .associativity = 8, 2047 .partitions = 1, 2048 .sets = 1024, 2049 .lines_per_tag = 1, 2050 .share_level = CPU_TOPO_LEVEL_CORE, 2051 }, 2052 .l3_cache = &(CPUCacheInfo) { 2053 .type = UNIFIED_CACHE, 2054 .level = 3, 2055 .size = 8 * MiB, 2056 .line_size = 64, 2057 .associativity = 16, 2058 .partitions = 1, 2059 .sets = 8192, 2060 .lines_per_tag = 1, 2061 .self_init = true, 2062 .inclusive = true, 2063 .complex_indexing = true, 2064 .share_level = CPU_TOPO_LEVEL_DIE, 2065 }, 2066 }; 2067 2068 static CPUCaches epyc_v4_cache_info = { 2069 .l1d_cache = &(CPUCacheInfo) { 2070 .type = DATA_CACHE, 2071 .level = 1, 2072 .size = 32 * KiB, 2073 .line_size = 64, 2074 .associativity = 8, 2075 .partitions = 1, 2076 .sets = 64, 2077 .lines_per_tag = 1, 2078 .self_init = 1, 2079 .no_invd_sharing = true, 2080 .share_level = CPU_TOPO_LEVEL_CORE, 2081 }, 2082 .l1i_cache = &(CPUCacheInfo) { 2083 .type = INSTRUCTION_CACHE, 2084 .level = 1, 2085 .size = 64 * KiB, 2086 .line_size = 64, 2087 .associativity = 4, 2088 .partitions = 1, 2089 .sets = 256, 2090 .lines_per_tag = 1, 2091 .self_init = 1, 2092 .no_invd_sharing = true, 2093 .share_level = CPU_TOPO_LEVEL_CORE, 2094 }, 2095 .l2_cache = &(CPUCacheInfo) { 2096 .type = UNIFIED_CACHE, 2097 .level = 2, 2098 .size = 512 * KiB, 2099 .line_size = 64, 2100 .associativity = 8, 2101 .partitions = 1, 2102 .sets = 1024, 2103 .lines_per_tag = 1, 2104 .share_level = CPU_TOPO_LEVEL_CORE, 2105 }, 2106 .l3_cache = &(CPUCacheInfo) { 2107 .type = UNIFIED_CACHE, 2108 .level = 3, 2109 .size = 8 * MiB, 2110 .line_size = 64, 2111 .associativity = 16, 2112 .partitions = 1, 2113 .sets = 8192, 2114 .lines_per_tag = 1, 2115 .self_init = true, 2116 .inclusive = true, 2117 .complex_indexing = false, 2118 .share_level = CPU_TOPO_LEVEL_DIE, 2119 }, 2120 }; 2121 2122 static const CPUCaches epyc_rome_cache_info = { 2123 .l1d_cache = &(CPUCacheInfo) { 2124 .type = DATA_CACHE, 2125 .level = 1, 2126 .size = 32 * KiB, 2127 .line_size = 64, 2128 .associativity = 8, 2129 .partitions = 1, 2130 .sets = 64, 2131 .lines_per_tag = 1, 2132 .self_init = 1, 2133 .no_invd_sharing = true, 2134 .share_level = CPU_TOPO_LEVEL_CORE, 2135 }, 2136 .l1i_cache = &(CPUCacheInfo) { 2137 .type = INSTRUCTION_CACHE, 2138 .level = 1, 2139 .size = 32 * KiB, 2140 .line_size = 64, 2141 .associativity = 8, 2142 .partitions = 1, 2143 .sets = 64, 2144 .lines_per_tag = 1, 2145 .self_init = 1, 2146 .no_invd_sharing = true, 2147 .share_level = CPU_TOPO_LEVEL_CORE, 2148 }, 2149 .l2_cache = &(CPUCacheInfo) { 2150 .type = UNIFIED_CACHE, 2151 .level = 2, 2152 .size = 512 * KiB, 2153 .line_size = 64, 2154 .associativity = 8, 2155 .partitions = 1, 2156 .sets = 1024, 2157 .lines_per_tag = 1, 2158 .share_level = CPU_TOPO_LEVEL_CORE, 2159 }, 2160 .l3_cache = &(CPUCacheInfo) { 2161 .type = UNIFIED_CACHE, 2162 .level = 3, 2163 .size = 16 * MiB, 2164 .line_size = 64, 2165 .associativity = 16, 2166 .partitions = 1, 2167 .sets = 16384, 2168 .lines_per_tag = 1, 2169 .self_init = true, 2170 .inclusive = true, 2171 .complex_indexing = true, 2172 .share_level = CPU_TOPO_LEVEL_DIE, 2173 }, 2174 }; 2175 2176 static const CPUCaches epyc_rome_v3_cache_info = { 2177 .l1d_cache = &(CPUCacheInfo) { 2178 .type = DATA_CACHE, 2179 .level = 1, 2180 .size = 32 * KiB, 2181 .line_size = 64, 2182 .associativity = 8, 2183 .partitions = 1, 2184 .sets = 64, 2185 .lines_per_tag = 1, 2186 .self_init = 1, 2187 .no_invd_sharing = true, 2188 .share_level = CPU_TOPO_LEVEL_CORE, 2189 }, 2190 .l1i_cache = &(CPUCacheInfo) { 2191 .type = INSTRUCTION_CACHE, 2192 .level = 1, 2193 .size = 32 * KiB, 2194 .line_size = 64, 2195 .associativity = 8, 2196 .partitions = 1, 2197 .sets = 64, 2198 .lines_per_tag = 1, 2199 .self_init = 1, 2200 .no_invd_sharing = true, 2201 .share_level = CPU_TOPO_LEVEL_CORE, 2202 }, 2203 .l2_cache = &(CPUCacheInfo) { 2204 .type = UNIFIED_CACHE, 2205 .level = 2, 2206 .size = 512 * KiB, 2207 .line_size = 64, 2208 .associativity = 8, 2209 .partitions = 1, 2210 .sets = 1024, 2211 .lines_per_tag = 1, 2212 .share_level = CPU_TOPO_LEVEL_CORE, 2213 }, 2214 .l3_cache = &(CPUCacheInfo) { 2215 .type = UNIFIED_CACHE, 2216 .level = 3, 2217 .size = 16 * MiB, 2218 .line_size = 64, 2219 .associativity = 16, 2220 .partitions = 1, 2221 .sets = 16384, 2222 .lines_per_tag = 1, 2223 .self_init = true, 2224 .inclusive = true, 2225 .complex_indexing = false, 2226 .share_level = CPU_TOPO_LEVEL_DIE, 2227 }, 2228 }; 2229 2230 static const CPUCaches epyc_milan_cache_info = { 2231 .l1d_cache = &(CPUCacheInfo) { 2232 .type = DATA_CACHE, 2233 .level = 1, 2234 .size = 32 * KiB, 2235 .line_size = 64, 2236 .associativity = 8, 2237 .partitions = 1, 2238 .sets = 64, 2239 .lines_per_tag = 1, 2240 .self_init = 1, 2241 .no_invd_sharing = true, 2242 .share_level = CPU_TOPO_LEVEL_CORE, 2243 }, 2244 .l1i_cache = &(CPUCacheInfo) { 2245 .type = INSTRUCTION_CACHE, 2246 .level = 1, 2247 .size = 32 * KiB, 2248 .line_size = 64, 2249 .associativity = 8, 2250 .partitions = 1, 2251 .sets = 64, 2252 .lines_per_tag = 1, 2253 .self_init = 1, 2254 .no_invd_sharing = true, 2255 .share_level = CPU_TOPO_LEVEL_CORE, 2256 }, 2257 .l2_cache = &(CPUCacheInfo) { 2258 .type = UNIFIED_CACHE, 2259 .level = 2, 2260 .size = 512 * KiB, 2261 .line_size = 64, 2262 .associativity = 8, 2263 .partitions = 1, 2264 .sets = 1024, 2265 .lines_per_tag = 1, 2266 .share_level = CPU_TOPO_LEVEL_CORE, 2267 }, 2268 .l3_cache = &(CPUCacheInfo) { 2269 .type = UNIFIED_CACHE, 2270 .level = 3, 2271 .size = 32 * MiB, 2272 .line_size = 64, 2273 .associativity = 16, 2274 .partitions = 1, 2275 .sets = 32768, 2276 .lines_per_tag = 1, 2277 .self_init = true, 2278 .inclusive = true, 2279 .complex_indexing = true, 2280 .share_level = CPU_TOPO_LEVEL_DIE, 2281 }, 2282 }; 2283 2284 static const CPUCaches epyc_milan_v2_cache_info = { 2285 .l1d_cache = &(CPUCacheInfo) { 2286 .type = DATA_CACHE, 2287 .level = 1, 2288 .size = 32 * KiB, 2289 .line_size = 64, 2290 .associativity = 8, 2291 .partitions = 1, 2292 .sets = 64, 2293 .lines_per_tag = 1, 2294 .self_init = 1, 2295 .no_invd_sharing = true, 2296 .share_level = CPU_TOPO_LEVEL_CORE, 2297 }, 2298 .l1i_cache = &(CPUCacheInfo) { 2299 .type = INSTRUCTION_CACHE, 2300 .level = 1, 2301 .size = 32 * KiB, 2302 .line_size = 64, 2303 .associativity = 8, 2304 .partitions = 1, 2305 .sets = 64, 2306 .lines_per_tag = 1, 2307 .self_init = 1, 2308 .no_invd_sharing = true, 2309 .share_level = CPU_TOPO_LEVEL_CORE, 2310 }, 2311 .l2_cache = &(CPUCacheInfo) { 2312 .type = UNIFIED_CACHE, 2313 .level = 2, 2314 .size = 512 * KiB, 2315 .line_size = 64, 2316 .associativity = 8, 2317 .partitions = 1, 2318 .sets = 1024, 2319 .lines_per_tag = 1, 2320 .share_level = CPU_TOPO_LEVEL_CORE, 2321 }, 2322 .l3_cache = &(CPUCacheInfo) { 2323 .type = UNIFIED_CACHE, 2324 .level = 3, 2325 .size = 32 * MiB, 2326 .line_size = 64, 2327 .associativity = 16, 2328 .partitions = 1, 2329 .sets = 32768, 2330 .lines_per_tag = 1, 2331 .self_init = true, 2332 .inclusive = true, 2333 .complex_indexing = false, 2334 .share_level = CPU_TOPO_LEVEL_DIE, 2335 }, 2336 }; 2337 2338 static const CPUCaches epyc_genoa_cache_info = { 2339 .l1d_cache = &(CPUCacheInfo) { 2340 .type = DATA_CACHE, 2341 .level = 1, 2342 .size = 32 * KiB, 2343 .line_size = 64, 2344 .associativity = 8, 2345 .partitions = 1, 2346 .sets = 64, 2347 .lines_per_tag = 1, 2348 .self_init = 1, 2349 .no_invd_sharing = true, 2350 .share_level = CPU_TOPO_LEVEL_CORE, 2351 }, 2352 .l1i_cache = &(CPUCacheInfo) { 2353 .type = INSTRUCTION_CACHE, 2354 .level = 1, 2355 .size = 32 * KiB, 2356 .line_size = 64, 2357 .associativity = 8, 2358 .partitions = 1, 2359 .sets = 64, 2360 .lines_per_tag = 1, 2361 .self_init = 1, 2362 .no_invd_sharing = true, 2363 .share_level = CPU_TOPO_LEVEL_CORE, 2364 }, 2365 .l2_cache = &(CPUCacheInfo) { 2366 .type = UNIFIED_CACHE, 2367 .level = 2, 2368 .size = 1 * MiB, 2369 .line_size = 64, 2370 .associativity = 8, 2371 .partitions = 1, 2372 .sets = 2048, 2373 .lines_per_tag = 1, 2374 .share_level = CPU_TOPO_LEVEL_CORE, 2375 }, 2376 .l3_cache = &(CPUCacheInfo) { 2377 .type = UNIFIED_CACHE, 2378 .level = 3, 2379 .size = 32 * MiB, 2380 .line_size = 64, 2381 .associativity = 16, 2382 .partitions = 1, 2383 .sets = 32768, 2384 .lines_per_tag = 1, 2385 .self_init = true, 2386 .inclusive = true, 2387 .complex_indexing = false, 2388 .share_level = CPU_TOPO_LEVEL_DIE, 2389 }, 2390 }; 2391 2392 /* The following VMX features are not supported by KVM and are left out in the 2393 * CPU definitions: 2394 * 2395 * Dual-monitor support (all processors) 2396 * Entry to SMM 2397 * Deactivate dual-monitor treatment 2398 * Number of CR3-target values 2399 * Shutdown activity state 2400 * Wait-for-SIPI activity state 2401 * PAUSE-loop exiting (Westmere and newer) 2402 * EPT-violation #VE (Broadwell and newer) 2403 * Inject event with insn length=0 (Skylake and newer) 2404 * Conceal non-root operation from PT 2405 * Conceal VM exits from PT 2406 * Conceal VM entries from PT 2407 * Enable ENCLS exiting 2408 * Mode-based execute control (XS/XU) 2409 * TSC scaling (Skylake Server and newer) 2410 * GPA translation for PT (IceLake and newer) 2411 * User wait and pause 2412 * ENCLV exiting 2413 * Load IA32_RTIT_CTL 2414 * Clear IA32_RTIT_CTL 2415 * Advanced VM-exit information for EPT violations 2416 * Sub-page write permissions 2417 * PT in VMX operation 2418 */ 2419 2420 static const X86CPUDefinition builtin_x86_defs[] = { 2421 { 2422 .name = "qemu64", 2423 .level = 0xd, 2424 .vendor = CPUID_VENDOR_AMD, 2425 .family = 15, 2426 .model = 107, 2427 .stepping = 1, 2428 .features[FEAT_1_EDX] = 2429 PPRO_FEATURES | 2430 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2431 CPUID_PSE36, 2432 .features[FEAT_1_ECX] = 2433 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2434 .features[FEAT_8000_0001_EDX] = 2435 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2436 .features[FEAT_8000_0001_ECX] = 2437 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2438 .xlevel = 0x8000000A, 2439 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2440 }, 2441 { 2442 .name = "phenom", 2443 .level = 5, 2444 .vendor = CPUID_VENDOR_AMD, 2445 .family = 16, 2446 .model = 2, 2447 .stepping = 3, 2448 /* Missing: CPUID_HT */ 2449 .features[FEAT_1_EDX] = 2450 PPRO_FEATURES | 2451 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2452 CPUID_PSE36 | CPUID_VME, 2453 .features[FEAT_1_ECX] = 2454 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2455 CPUID_EXT_POPCNT, 2456 .features[FEAT_8000_0001_EDX] = 2457 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2458 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2459 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2460 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2461 CPUID_EXT3_CR8LEG, 2462 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2463 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2464 .features[FEAT_8000_0001_ECX] = 2465 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2466 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2467 /* Missing: CPUID_SVM_LBRV */ 2468 .features[FEAT_SVM] = 2469 CPUID_SVM_NPT, 2470 .xlevel = 0x8000001A, 2471 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2472 }, 2473 { 2474 .name = "core2duo", 2475 .level = 10, 2476 .vendor = CPUID_VENDOR_INTEL, 2477 .family = 6, 2478 .model = 15, 2479 .stepping = 11, 2480 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2481 .features[FEAT_1_EDX] = 2482 PPRO_FEATURES | 2483 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2484 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2485 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2486 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2487 .features[FEAT_1_ECX] = 2488 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2489 CPUID_EXT_CX16, 2490 .features[FEAT_8000_0001_EDX] = 2491 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2492 .features[FEAT_8000_0001_ECX] = 2493 CPUID_EXT3_LAHF_LM, 2494 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2495 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2496 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2497 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2498 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2499 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2500 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2501 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2502 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2503 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2504 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2505 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2506 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2507 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2508 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2509 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2510 .features[FEAT_VMX_SECONDARY_CTLS] = 2511 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2512 .xlevel = 0x80000008, 2513 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2514 }, 2515 { 2516 .name = "kvm64", 2517 .level = 0xd, 2518 .vendor = CPUID_VENDOR_INTEL, 2519 .family = 15, 2520 .model = 6, 2521 .stepping = 1, 2522 /* Missing: CPUID_HT */ 2523 .features[FEAT_1_EDX] = 2524 PPRO_FEATURES | CPUID_VME | 2525 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2526 CPUID_PSE36, 2527 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2528 .features[FEAT_1_ECX] = 2529 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2530 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2531 .features[FEAT_8000_0001_EDX] = 2532 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2533 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2534 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2535 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2536 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2537 .features[FEAT_8000_0001_ECX] = 2538 0, 2539 /* VMX features from Cedar Mill/Prescott */ 2540 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2541 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2542 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2543 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2544 VMX_PIN_BASED_NMI_EXITING, 2545 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2546 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2547 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2548 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2549 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2550 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2551 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2552 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2553 .xlevel = 0x80000008, 2554 .model_id = "Common KVM processor" 2555 }, 2556 { 2557 .name = "qemu32", 2558 .level = 4, 2559 .vendor = CPUID_VENDOR_INTEL, 2560 .family = 6, 2561 .model = 6, 2562 .stepping = 3, 2563 .features[FEAT_1_EDX] = 2564 PPRO_FEATURES, 2565 .features[FEAT_1_ECX] = 2566 CPUID_EXT_SSE3, 2567 .xlevel = 0x80000004, 2568 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2569 }, 2570 { 2571 .name = "kvm32", 2572 .level = 5, 2573 .vendor = CPUID_VENDOR_INTEL, 2574 .family = 15, 2575 .model = 6, 2576 .stepping = 1, 2577 .features[FEAT_1_EDX] = 2578 PPRO_FEATURES | CPUID_VME | 2579 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2580 .features[FEAT_1_ECX] = 2581 CPUID_EXT_SSE3, 2582 .features[FEAT_8000_0001_ECX] = 2583 0, 2584 /* VMX features from Yonah */ 2585 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2586 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2587 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2588 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2589 VMX_PIN_BASED_NMI_EXITING, 2590 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2591 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2592 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2593 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2594 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2595 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2596 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2597 .xlevel = 0x80000008, 2598 .model_id = "Common 32-bit KVM processor" 2599 }, 2600 { 2601 .name = "coreduo", 2602 .level = 10, 2603 .vendor = CPUID_VENDOR_INTEL, 2604 .family = 6, 2605 .model = 14, 2606 .stepping = 8, 2607 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2608 .features[FEAT_1_EDX] = 2609 PPRO_FEATURES | CPUID_VME | 2610 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2611 CPUID_SS, 2612 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2613 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2614 .features[FEAT_1_ECX] = 2615 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2616 .features[FEAT_8000_0001_EDX] = 2617 CPUID_EXT2_NX, 2618 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2619 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2620 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2621 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2622 VMX_PIN_BASED_NMI_EXITING, 2623 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2624 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2625 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2626 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2627 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2628 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2629 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2630 .xlevel = 0x80000008, 2631 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2632 }, 2633 { 2634 .name = "486", 2635 .level = 1, 2636 .vendor = CPUID_VENDOR_INTEL, 2637 .family = 4, 2638 .model = 8, 2639 .stepping = 0, 2640 .features[FEAT_1_EDX] = 2641 I486_FEATURES, 2642 .xlevel = 0, 2643 .model_id = "", 2644 }, 2645 { 2646 .name = "pentium", 2647 .level = 1, 2648 .vendor = CPUID_VENDOR_INTEL, 2649 .family = 5, 2650 .model = 4, 2651 .stepping = 3, 2652 .features[FEAT_1_EDX] = 2653 PENTIUM_FEATURES, 2654 .xlevel = 0, 2655 .model_id = "", 2656 }, 2657 { 2658 .name = "pentium2", 2659 .level = 2, 2660 .vendor = CPUID_VENDOR_INTEL, 2661 .family = 6, 2662 .model = 5, 2663 .stepping = 2, 2664 .features[FEAT_1_EDX] = 2665 PENTIUM2_FEATURES, 2666 .xlevel = 0, 2667 .model_id = "", 2668 }, 2669 { 2670 .name = "pentium3", 2671 .level = 3, 2672 .vendor = CPUID_VENDOR_INTEL, 2673 .family = 6, 2674 .model = 7, 2675 .stepping = 3, 2676 .features[FEAT_1_EDX] = 2677 PENTIUM3_FEATURES, 2678 .xlevel = 0, 2679 .model_id = "", 2680 }, 2681 { 2682 .name = "athlon", 2683 .level = 2, 2684 .vendor = CPUID_VENDOR_AMD, 2685 .family = 6, 2686 .model = 2, 2687 .stepping = 3, 2688 .features[FEAT_1_EDX] = 2689 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2690 CPUID_MCA, 2691 .features[FEAT_8000_0001_EDX] = 2692 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2693 .xlevel = 0x80000008, 2694 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2695 }, 2696 { 2697 .name = "n270", 2698 .level = 10, 2699 .vendor = CPUID_VENDOR_INTEL, 2700 .family = 6, 2701 .model = 28, 2702 .stepping = 2, 2703 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2704 .features[FEAT_1_EDX] = 2705 PPRO_FEATURES | 2706 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2707 CPUID_ACPI | CPUID_SS, 2708 /* Some CPUs got no CPUID_SEP */ 2709 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2710 * CPUID_EXT_XTPR */ 2711 .features[FEAT_1_ECX] = 2712 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2713 CPUID_EXT_MOVBE, 2714 .features[FEAT_8000_0001_EDX] = 2715 CPUID_EXT2_NX, 2716 .features[FEAT_8000_0001_ECX] = 2717 CPUID_EXT3_LAHF_LM, 2718 .xlevel = 0x80000008, 2719 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2720 }, 2721 { 2722 .name = "Conroe", 2723 .level = 10, 2724 .vendor = CPUID_VENDOR_INTEL, 2725 .family = 6, 2726 .model = 15, 2727 .stepping = 3, 2728 .features[FEAT_1_EDX] = 2729 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2730 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2731 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2732 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2733 CPUID_DE | CPUID_FP87, 2734 .features[FEAT_1_ECX] = 2735 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2736 .features[FEAT_8000_0001_EDX] = 2737 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2738 .features[FEAT_8000_0001_ECX] = 2739 CPUID_EXT3_LAHF_LM, 2740 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2741 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2742 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2743 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2744 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2745 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2746 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2747 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2748 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2749 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2750 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2751 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2752 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2753 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2754 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2755 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2756 .features[FEAT_VMX_SECONDARY_CTLS] = 2757 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2758 .xlevel = 0x80000008, 2759 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2760 }, 2761 { 2762 .name = "Penryn", 2763 .level = 10, 2764 .vendor = CPUID_VENDOR_INTEL, 2765 .family = 6, 2766 .model = 23, 2767 .stepping = 3, 2768 .features[FEAT_1_EDX] = 2769 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2770 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2771 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2772 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2773 CPUID_DE | CPUID_FP87, 2774 .features[FEAT_1_ECX] = 2775 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2776 CPUID_EXT_SSE3, 2777 .features[FEAT_8000_0001_EDX] = 2778 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2779 .features[FEAT_8000_0001_ECX] = 2780 CPUID_EXT3_LAHF_LM, 2781 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2782 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2783 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2784 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2785 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2786 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2787 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2788 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2789 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2790 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2791 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2792 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2793 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2794 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2795 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2796 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2797 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2798 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2799 .features[FEAT_VMX_SECONDARY_CTLS] = 2800 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2801 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2802 .xlevel = 0x80000008, 2803 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2804 }, 2805 { 2806 .name = "Nehalem", 2807 .level = 11, 2808 .vendor = CPUID_VENDOR_INTEL, 2809 .family = 6, 2810 .model = 26, 2811 .stepping = 3, 2812 .features[FEAT_1_EDX] = 2813 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2814 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2815 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2816 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2817 CPUID_DE | CPUID_FP87, 2818 .features[FEAT_1_ECX] = 2819 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2820 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2821 .features[FEAT_8000_0001_EDX] = 2822 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2823 .features[FEAT_8000_0001_ECX] = 2824 CPUID_EXT3_LAHF_LM, 2825 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2826 MSR_VMX_BASIC_TRUE_CTLS, 2827 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2828 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2829 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2830 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2831 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2832 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2833 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2834 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2835 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2836 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2837 .features[FEAT_VMX_EXIT_CTLS] = 2838 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2839 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2840 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2841 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2842 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2843 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2844 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2845 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2846 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2847 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2848 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2849 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2850 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2851 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2852 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2853 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2854 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2855 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2856 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2857 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2858 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2859 .features[FEAT_VMX_SECONDARY_CTLS] = 2860 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2861 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2862 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2863 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2864 VMX_SECONDARY_EXEC_ENABLE_VPID, 2865 .xlevel = 0x80000008, 2866 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2867 .versions = (X86CPUVersionDefinition[]) { 2868 { .version = 1 }, 2869 { 2870 .version = 2, 2871 .alias = "Nehalem-IBRS", 2872 .props = (PropValue[]) { 2873 { "spec-ctrl", "on" }, 2874 { "model-id", 2875 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2876 { /* end of list */ } 2877 } 2878 }, 2879 { /* end of list */ } 2880 } 2881 }, 2882 { 2883 .name = "Westmere", 2884 .level = 11, 2885 .vendor = CPUID_VENDOR_INTEL, 2886 .family = 6, 2887 .model = 44, 2888 .stepping = 1, 2889 .features[FEAT_1_EDX] = 2890 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2891 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2892 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2893 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2894 CPUID_DE | CPUID_FP87, 2895 .features[FEAT_1_ECX] = 2896 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2897 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2898 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2899 .features[FEAT_8000_0001_EDX] = 2900 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2901 .features[FEAT_8000_0001_ECX] = 2902 CPUID_EXT3_LAHF_LM, 2903 .features[FEAT_6_EAX] = 2904 CPUID_6_EAX_ARAT, 2905 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2906 MSR_VMX_BASIC_TRUE_CTLS, 2907 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2908 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2909 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2910 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2911 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2912 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2913 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2914 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2915 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2916 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2917 .features[FEAT_VMX_EXIT_CTLS] = 2918 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2919 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2920 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2921 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2922 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2923 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2924 MSR_VMX_MISC_STORE_LMA, 2925 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2926 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2927 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2928 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2929 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2930 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2931 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2932 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2933 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2934 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2935 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2936 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2937 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2938 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2939 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2940 .features[FEAT_VMX_SECONDARY_CTLS] = 2941 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2942 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2943 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2944 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2945 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2946 .xlevel = 0x80000008, 2947 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2948 .versions = (X86CPUVersionDefinition[]) { 2949 { .version = 1 }, 2950 { 2951 .version = 2, 2952 .alias = "Westmere-IBRS", 2953 .props = (PropValue[]) { 2954 { "spec-ctrl", "on" }, 2955 { "model-id", 2956 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2957 { /* end of list */ } 2958 } 2959 }, 2960 { /* end of list */ } 2961 } 2962 }, 2963 { 2964 .name = "SandyBridge", 2965 .level = 0xd, 2966 .vendor = CPUID_VENDOR_INTEL, 2967 .family = 6, 2968 .model = 42, 2969 .stepping = 1, 2970 .features[FEAT_1_EDX] = 2971 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2972 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2973 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2974 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2975 CPUID_DE | CPUID_FP87, 2976 .features[FEAT_1_ECX] = 2977 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2978 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2979 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2980 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2981 CPUID_EXT_SSE3, 2982 .features[FEAT_8000_0001_EDX] = 2983 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2984 CPUID_EXT2_SYSCALL, 2985 .features[FEAT_8000_0001_ECX] = 2986 CPUID_EXT3_LAHF_LM, 2987 .features[FEAT_XSAVE] = 2988 CPUID_XSAVE_XSAVEOPT, 2989 .features[FEAT_6_EAX] = 2990 CPUID_6_EAX_ARAT, 2991 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2992 MSR_VMX_BASIC_TRUE_CTLS, 2993 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2994 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2995 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2996 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2997 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2998 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2999 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3000 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3001 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3002 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3003 .features[FEAT_VMX_EXIT_CTLS] = 3004 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3005 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3006 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3007 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3008 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3009 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3010 MSR_VMX_MISC_STORE_LMA, 3011 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3012 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3013 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3014 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3015 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3016 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3017 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3018 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3019 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3020 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3021 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3022 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3023 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3024 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3025 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3026 .features[FEAT_VMX_SECONDARY_CTLS] = 3027 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3028 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3029 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3030 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3031 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3032 .xlevel = 0x80000008, 3033 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3034 .versions = (X86CPUVersionDefinition[]) { 3035 { .version = 1 }, 3036 { 3037 .version = 2, 3038 .alias = "SandyBridge-IBRS", 3039 .props = (PropValue[]) { 3040 { "spec-ctrl", "on" }, 3041 { "model-id", 3042 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3043 { /* end of list */ } 3044 } 3045 }, 3046 { /* end of list */ } 3047 } 3048 }, 3049 { 3050 .name = "IvyBridge", 3051 .level = 0xd, 3052 .vendor = CPUID_VENDOR_INTEL, 3053 .family = 6, 3054 .model = 58, 3055 .stepping = 9, 3056 .features[FEAT_1_EDX] = 3057 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3058 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3059 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3060 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3061 CPUID_DE | CPUID_FP87, 3062 .features[FEAT_1_ECX] = 3063 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3064 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3065 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3066 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3067 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3068 .features[FEAT_7_0_EBX] = 3069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3070 CPUID_7_0_EBX_ERMS, 3071 .features[FEAT_8000_0001_EDX] = 3072 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3073 CPUID_EXT2_SYSCALL, 3074 .features[FEAT_8000_0001_ECX] = 3075 CPUID_EXT3_LAHF_LM, 3076 .features[FEAT_XSAVE] = 3077 CPUID_XSAVE_XSAVEOPT, 3078 .features[FEAT_6_EAX] = 3079 CPUID_6_EAX_ARAT, 3080 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3081 MSR_VMX_BASIC_TRUE_CTLS, 3082 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3083 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3084 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3085 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3086 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3087 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3088 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3089 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3090 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3091 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3092 .features[FEAT_VMX_EXIT_CTLS] = 3093 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3094 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3095 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3096 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3097 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3098 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3099 MSR_VMX_MISC_STORE_LMA, 3100 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3101 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3102 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3103 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3104 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3105 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3106 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3107 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3108 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3109 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3110 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3111 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3112 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3113 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3114 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3115 .features[FEAT_VMX_SECONDARY_CTLS] = 3116 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3117 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3118 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3119 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3120 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3121 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3122 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3123 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3124 .xlevel = 0x80000008, 3125 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3126 .versions = (X86CPUVersionDefinition[]) { 3127 { .version = 1 }, 3128 { 3129 .version = 2, 3130 .alias = "IvyBridge-IBRS", 3131 .props = (PropValue[]) { 3132 { "spec-ctrl", "on" }, 3133 { "model-id", 3134 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3135 { /* end of list */ } 3136 } 3137 }, 3138 { /* end of list */ } 3139 } 3140 }, 3141 { 3142 .name = "Haswell", 3143 .level = 0xd, 3144 .vendor = CPUID_VENDOR_INTEL, 3145 .family = 6, 3146 .model = 60, 3147 .stepping = 4, 3148 .features[FEAT_1_EDX] = 3149 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3150 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3151 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3152 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3153 CPUID_DE | CPUID_FP87, 3154 .features[FEAT_1_ECX] = 3155 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3156 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3157 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3158 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3159 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3160 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3161 .features[FEAT_8000_0001_EDX] = 3162 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3163 CPUID_EXT2_SYSCALL, 3164 .features[FEAT_8000_0001_ECX] = 3165 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3166 .features[FEAT_7_0_EBX] = 3167 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3168 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3169 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3170 CPUID_7_0_EBX_RTM, 3171 .features[FEAT_XSAVE] = 3172 CPUID_XSAVE_XSAVEOPT, 3173 .features[FEAT_6_EAX] = 3174 CPUID_6_EAX_ARAT, 3175 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3176 MSR_VMX_BASIC_TRUE_CTLS, 3177 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3178 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3179 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3180 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3181 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3182 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3183 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3184 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3185 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3186 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3187 .features[FEAT_VMX_EXIT_CTLS] = 3188 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3189 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3190 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3191 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3192 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3193 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3194 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3195 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3196 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3197 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3198 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3199 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3200 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3201 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3202 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3203 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3204 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3205 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3206 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3207 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3208 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3209 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3210 .features[FEAT_VMX_SECONDARY_CTLS] = 3211 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3212 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3213 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3214 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3215 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3216 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3217 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3218 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3219 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3220 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3221 .xlevel = 0x80000008, 3222 .model_id = "Intel Core Processor (Haswell)", 3223 .versions = (X86CPUVersionDefinition[]) { 3224 { .version = 1 }, 3225 { 3226 .version = 2, 3227 .alias = "Haswell-noTSX", 3228 .props = (PropValue[]) { 3229 { "hle", "off" }, 3230 { "rtm", "off" }, 3231 { "stepping", "1" }, 3232 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3233 { /* end of list */ } 3234 }, 3235 }, 3236 { 3237 .version = 3, 3238 .alias = "Haswell-IBRS", 3239 .props = (PropValue[]) { 3240 /* Restore TSX features removed by -v2 above */ 3241 { "hle", "on" }, 3242 { "rtm", "on" }, 3243 /* 3244 * Haswell and Haswell-IBRS had stepping=4 in 3245 * QEMU 4.0 and older 3246 */ 3247 { "stepping", "4" }, 3248 { "spec-ctrl", "on" }, 3249 { "model-id", 3250 "Intel Core Processor (Haswell, IBRS)" }, 3251 { /* end of list */ } 3252 } 3253 }, 3254 { 3255 .version = 4, 3256 .alias = "Haswell-noTSX-IBRS", 3257 .props = (PropValue[]) { 3258 { "hle", "off" }, 3259 { "rtm", "off" }, 3260 /* spec-ctrl was already enabled by -v3 above */ 3261 { "stepping", "1" }, 3262 { "model-id", 3263 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3264 { /* end of list */ } 3265 } 3266 }, 3267 { /* end of list */ } 3268 } 3269 }, 3270 { 3271 .name = "Broadwell", 3272 .level = 0xd, 3273 .vendor = CPUID_VENDOR_INTEL, 3274 .family = 6, 3275 .model = 61, 3276 .stepping = 2, 3277 .features[FEAT_1_EDX] = 3278 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3279 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3280 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3281 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3282 CPUID_DE | CPUID_FP87, 3283 .features[FEAT_1_ECX] = 3284 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3285 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3286 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3287 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3288 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3289 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3290 .features[FEAT_8000_0001_EDX] = 3291 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3292 CPUID_EXT2_SYSCALL, 3293 .features[FEAT_8000_0001_ECX] = 3294 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3295 .features[FEAT_7_0_EBX] = 3296 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3297 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3298 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3299 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3300 CPUID_7_0_EBX_SMAP, 3301 .features[FEAT_XSAVE] = 3302 CPUID_XSAVE_XSAVEOPT, 3303 .features[FEAT_6_EAX] = 3304 CPUID_6_EAX_ARAT, 3305 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3306 MSR_VMX_BASIC_TRUE_CTLS, 3307 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3308 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3309 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3310 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3311 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3312 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3313 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3314 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3315 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3316 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3317 .features[FEAT_VMX_EXIT_CTLS] = 3318 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3319 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3320 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3321 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3322 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3323 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3324 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3325 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3326 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3327 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3328 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3329 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3330 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3331 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3332 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3333 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3334 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3335 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3336 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3337 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3338 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3339 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3340 .features[FEAT_VMX_SECONDARY_CTLS] = 3341 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3342 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3343 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3344 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3345 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3346 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3347 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3348 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3349 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3350 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3351 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3352 .xlevel = 0x80000008, 3353 .model_id = "Intel Core Processor (Broadwell)", 3354 .versions = (X86CPUVersionDefinition[]) { 3355 { .version = 1 }, 3356 { 3357 .version = 2, 3358 .alias = "Broadwell-noTSX", 3359 .props = (PropValue[]) { 3360 { "hle", "off" }, 3361 { "rtm", "off" }, 3362 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3363 { /* end of list */ } 3364 }, 3365 }, 3366 { 3367 .version = 3, 3368 .alias = "Broadwell-IBRS", 3369 .props = (PropValue[]) { 3370 /* Restore TSX features removed by -v2 above */ 3371 { "hle", "on" }, 3372 { "rtm", "on" }, 3373 { "spec-ctrl", "on" }, 3374 { "model-id", 3375 "Intel Core Processor (Broadwell, IBRS)" }, 3376 { /* end of list */ } 3377 } 3378 }, 3379 { 3380 .version = 4, 3381 .alias = "Broadwell-noTSX-IBRS", 3382 .props = (PropValue[]) { 3383 { "hle", "off" }, 3384 { "rtm", "off" }, 3385 /* spec-ctrl was already enabled by -v3 above */ 3386 { "model-id", 3387 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3388 { /* end of list */ } 3389 } 3390 }, 3391 { /* end of list */ } 3392 } 3393 }, 3394 { 3395 .name = "Skylake-Client", 3396 .level = 0xd, 3397 .vendor = CPUID_VENDOR_INTEL, 3398 .family = 6, 3399 .model = 94, 3400 .stepping = 3, 3401 .features[FEAT_1_EDX] = 3402 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3403 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3404 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3405 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3406 CPUID_DE | CPUID_FP87, 3407 .features[FEAT_1_ECX] = 3408 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3409 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3410 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3411 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3412 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3413 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3414 .features[FEAT_8000_0001_EDX] = 3415 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3416 CPUID_EXT2_SYSCALL, 3417 .features[FEAT_8000_0001_ECX] = 3418 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3419 .features[FEAT_7_0_EBX] = 3420 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3421 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3422 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3423 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3424 CPUID_7_0_EBX_SMAP, 3425 /* XSAVES is added in version 4 */ 3426 .features[FEAT_XSAVE] = 3427 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3428 CPUID_XSAVE_XGETBV1, 3429 .features[FEAT_6_EAX] = 3430 CPUID_6_EAX_ARAT, 3431 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3432 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3433 MSR_VMX_BASIC_TRUE_CTLS, 3434 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3435 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3436 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3437 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3438 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3439 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3440 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3441 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3442 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3443 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3444 .features[FEAT_VMX_EXIT_CTLS] = 3445 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3446 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3447 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3448 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3449 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3450 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3451 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3452 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3453 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3454 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3455 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3456 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3457 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3458 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3459 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3460 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3461 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3462 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3463 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3464 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3465 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3466 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3467 .features[FEAT_VMX_SECONDARY_CTLS] = 3468 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3469 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3470 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3471 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3472 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3473 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3474 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3475 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3476 .xlevel = 0x80000008, 3477 .model_id = "Intel Core Processor (Skylake)", 3478 .versions = (X86CPUVersionDefinition[]) { 3479 { .version = 1 }, 3480 { 3481 .version = 2, 3482 .alias = "Skylake-Client-IBRS", 3483 .props = (PropValue[]) { 3484 { "spec-ctrl", "on" }, 3485 { "model-id", 3486 "Intel Core Processor (Skylake, IBRS)" }, 3487 { /* end of list */ } 3488 } 3489 }, 3490 { 3491 .version = 3, 3492 .alias = "Skylake-Client-noTSX-IBRS", 3493 .props = (PropValue[]) { 3494 { "hle", "off" }, 3495 { "rtm", "off" }, 3496 { "model-id", 3497 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3498 { /* end of list */ } 3499 } 3500 }, 3501 { 3502 .version = 4, 3503 .note = "IBRS, XSAVES, no TSX", 3504 .props = (PropValue[]) { 3505 { "xsaves", "on" }, 3506 { "vmx-xsaves", "on" }, 3507 { /* end of list */ } 3508 } 3509 }, 3510 { /* end of list */ } 3511 } 3512 }, 3513 { 3514 .name = "Skylake-Server", 3515 .level = 0xd, 3516 .vendor = CPUID_VENDOR_INTEL, 3517 .family = 6, 3518 .model = 85, 3519 .stepping = 4, 3520 .features[FEAT_1_EDX] = 3521 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3522 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3523 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3524 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3525 CPUID_DE | CPUID_FP87, 3526 .features[FEAT_1_ECX] = 3527 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3528 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3529 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3530 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3531 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3532 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3533 .features[FEAT_8000_0001_EDX] = 3534 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3535 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3536 .features[FEAT_8000_0001_ECX] = 3537 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3538 .features[FEAT_7_0_EBX] = 3539 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3540 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3541 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3542 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3543 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3544 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3545 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3546 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3547 .features[FEAT_7_0_ECX] = 3548 CPUID_7_0_ECX_PKU, 3549 /* XSAVES is added in version 5 */ 3550 .features[FEAT_XSAVE] = 3551 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3552 CPUID_XSAVE_XGETBV1, 3553 .features[FEAT_6_EAX] = 3554 CPUID_6_EAX_ARAT, 3555 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3556 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3557 MSR_VMX_BASIC_TRUE_CTLS, 3558 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3559 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3560 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3561 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3562 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3563 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3564 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3565 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3566 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3567 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3568 .features[FEAT_VMX_EXIT_CTLS] = 3569 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3570 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3571 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3572 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3573 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3574 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3575 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3576 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3577 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3578 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3579 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3580 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3581 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3582 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3583 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3584 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3585 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3586 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3587 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3588 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3589 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3590 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3591 .features[FEAT_VMX_SECONDARY_CTLS] = 3592 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3593 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3594 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3595 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3596 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3597 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3598 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3599 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3600 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3601 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3602 .xlevel = 0x80000008, 3603 .model_id = "Intel Xeon Processor (Skylake)", 3604 .versions = (X86CPUVersionDefinition[]) { 3605 { .version = 1 }, 3606 { 3607 .version = 2, 3608 .alias = "Skylake-Server-IBRS", 3609 .props = (PropValue[]) { 3610 /* clflushopt was not added to Skylake-Server-IBRS */ 3611 /* TODO: add -v3 including clflushopt */ 3612 { "clflushopt", "off" }, 3613 { "spec-ctrl", "on" }, 3614 { "model-id", 3615 "Intel Xeon Processor (Skylake, IBRS)" }, 3616 { /* end of list */ } 3617 } 3618 }, 3619 { 3620 .version = 3, 3621 .alias = "Skylake-Server-noTSX-IBRS", 3622 .props = (PropValue[]) { 3623 { "hle", "off" }, 3624 { "rtm", "off" }, 3625 { "model-id", 3626 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3627 { /* end of list */ } 3628 } 3629 }, 3630 { 3631 .version = 4, 3632 .props = (PropValue[]) { 3633 { "vmx-eptp-switching", "on" }, 3634 { /* end of list */ } 3635 } 3636 }, 3637 { 3638 .version = 5, 3639 .note = "IBRS, XSAVES, EPT switching, no TSX", 3640 .props = (PropValue[]) { 3641 { "xsaves", "on" }, 3642 { "vmx-xsaves", "on" }, 3643 { /* end of list */ } 3644 } 3645 }, 3646 { /* end of list */ } 3647 } 3648 }, 3649 { 3650 .name = "Cascadelake-Server", 3651 .level = 0xd, 3652 .vendor = CPUID_VENDOR_INTEL, 3653 .family = 6, 3654 .model = 85, 3655 .stepping = 6, 3656 .features[FEAT_1_EDX] = 3657 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3658 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3659 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3660 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3661 CPUID_DE | CPUID_FP87, 3662 .features[FEAT_1_ECX] = 3663 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3664 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3665 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3666 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3667 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3668 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3669 .features[FEAT_8000_0001_EDX] = 3670 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3671 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3672 .features[FEAT_8000_0001_ECX] = 3673 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3674 .features[FEAT_7_0_EBX] = 3675 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3676 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3677 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3678 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3679 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3680 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3681 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3682 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3683 .features[FEAT_7_0_ECX] = 3684 CPUID_7_0_ECX_PKU | 3685 CPUID_7_0_ECX_AVX512VNNI, 3686 .features[FEAT_7_0_EDX] = 3687 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3688 /* XSAVES is added in version 5 */ 3689 .features[FEAT_XSAVE] = 3690 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3691 CPUID_XSAVE_XGETBV1, 3692 .features[FEAT_6_EAX] = 3693 CPUID_6_EAX_ARAT, 3694 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3695 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3696 MSR_VMX_BASIC_TRUE_CTLS, 3697 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3698 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3699 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3700 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3701 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3702 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3703 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3704 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3705 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3706 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3707 .features[FEAT_VMX_EXIT_CTLS] = 3708 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3709 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3710 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3711 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3712 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3713 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3714 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3715 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3716 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3717 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3718 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3719 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3720 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3721 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3722 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3723 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3724 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3725 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3726 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3727 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3728 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3729 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3730 .features[FEAT_VMX_SECONDARY_CTLS] = 3731 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3732 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3733 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3734 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3735 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3736 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3737 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3738 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3739 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3740 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3741 .xlevel = 0x80000008, 3742 .model_id = "Intel Xeon Processor (Cascadelake)", 3743 .versions = (X86CPUVersionDefinition[]) { 3744 { .version = 1 }, 3745 { .version = 2, 3746 .note = "ARCH_CAPABILITIES", 3747 .props = (PropValue[]) { 3748 { "arch-capabilities", "on" }, 3749 { "rdctl-no", "on" }, 3750 { "ibrs-all", "on" }, 3751 { "skip-l1dfl-vmentry", "on" }, 3752 { "mds-no", "on" }, 3753 { /* end of list */ } 3754 }, 3755 }, 3756 { .version = 3, 3757 .alias = "Cascadelake-Server-noTSX", 3758 .note = "ARCH_CAPABILITIES, no TSX", 3759 .props = (PropValue[]) { 3760 { "hle", "off" }, 3761 { "rtm", "off" }, 3762 { /* end of list */ } 3763 }, 3764 }, 3765 { .version = 4, 3766 .note = "ARCH_CAPABILITIES, no TSX", 3767 .props = (PropValue[]) { 3768 { "vmx-eptp-switching", "on" }, 3769 { /* end of list */ } 3770 }, 3771 }, 3772 { .version = 5, 3773 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3774 .props = (PropValue[]) { 3775 { "xsaves", "on" }, 3776 { "vmx-xsaves", "on" }, 3777 { /* end of list */ } 3778 }, 3779 }, 3780 { /* end of list */ } 3781 } 3782 }, 3783 { 3784 .name = "Cooperlake", 3785 .level = 0xd, 3786 .vendor = CPUID_VENDOR_INTEL, 3787 .family = 6, 3788 .model = 85, 3789 .stepping = 10, 3790 .features[FEAT_1_EDX] = 3791 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3792 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3793 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3794 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3795 CPUID_DE | CPUID_FP87, 3796 .features[FEAT_1_ECX] = 3797 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3798 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3799 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3800 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3801 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3802 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3803 .features[FEAT_8000_0001_EDX] = 3804 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3805 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3806 .features[FEAT_8000_0001_ECX] = 3807 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3808 .features[FEAT_7_0_EBX] = 3809 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3810 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3811 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3812 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3813 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3814 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3815 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3816 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3817 .features[FEAT_7_0_ECX] = 3818 CPUID_7_0_ECX_PKU | 3819 CPUID_7_0_ECX_AVX512VNNI, 3820 .features[FEAT_7_0_EDX] = 3821 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3822 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3823 .features[FEAT_ARCH_CAPABILITIES] = 3824 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3825 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3826 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3827 .features[FEAT_7_1_EAX] = 3828 CPUID_7_1_EAX_AVX512_BF16, 3829 /* XSAVES is added in version 2 */ 3830 .features[FEAT_XSAVE] = 3831 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3832 CPUID_XSAVE_XGETBV1, 3833 .features[FEAT_6_EAX] = 3834 CPUID_6_EAX_ARAT, 3835 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3836 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3837 MSR_VMX_BASIC_TRUE_CTLS, 3838 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3839 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3840 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3841 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3842 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3843 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3844 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3845 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3846 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3847 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3848 .features[FEAT_VMX_EXIT_CTLS] = 3849 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3850 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3851 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3852 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3853 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3854 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3855 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3856 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3857 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3858 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3859 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3860 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3861 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3862 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3863 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3864 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3865 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3866 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3867 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3868 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3869 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3870 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3871 .features[FEAT_VMX_SECONDARY_CTLS] = 3872 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3873 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3874 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3875 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3876 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3877 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3878 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3879 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3880 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3881 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3882 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3883 .xlevel = 0x80000008, 3884 .model_id = "Intel Xeon Processor (Cooperlake)", 3885 .versions = (X86CPUVersionDefinition[]) { 3886 { .version = 1 }, 3887 { .version = 2, 3888 .note = "XSAVES", 3889 .props = (PropValue[]) { 3890 { "xsaves", "on" }, 3891 { "vmx-xsaves", "on" }, 3892 { /* end of list */ } 3893 }, 3894 }, 3895 { /* end of list */ } 3896 } 3897 }, 3898 { 3899 .name = "Icelake-Server", 3900 .level = 0xd, 3901 .vendor = CPUID_VENDOR_INTEL, 3902 .family = 6, 3903 .model = 134, 3904 .stepping = 0, 3905 .features[FEAT_1_EDX] = 3906 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3907 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3908 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3909 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3910 CPUID_DE | CPUID_FP87, 3911 .features[FEAT_1_ECX] = 3912 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3913 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3914 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3915 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3916 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3917 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3918 .features[FEAT_8000_0001_EDX] = 3919 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3920 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3921 .features[FEAT_8000_0001_ECX] = 3922 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3923 .features[FEAT_8000_0008_EBX] = 3924 CPUID_8000_0008_EBX_WBNOINVD, 3925 .features[FEAT_7_0_EBX] = 3926 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3927 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3928 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3929 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3930 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3931 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3932 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3933 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3934 .features[FEAT_7_0_ECX] = 3935 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3936 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3937 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3938 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3939 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3940 .features[FEAT_7_0_EDX] = 3941 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3942 /* XSAVES is added in version 5 */ 3943 .features[FEAT_XSAVE] = 3944 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3945 CPUID_XSAVE_XGETBV1, 3946 .features[FEAT_6_EAX] = 3947 CPUID_6_EAX_ARAT, 3948 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3949 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3950 MSR_VMX_BASIC_TRUE_CTLS, 3951 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3952 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3953 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3954 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3955 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3956 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3957 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3958 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3959 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3960 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3961 .features[FEAT_VMX_EXIT_CTLS] = 3962 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3963 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3964 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3965 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3966 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3967 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3968 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3969 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3970 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3971 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3972 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3973 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3974 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3975 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3976 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3977 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3978 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3979 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3980 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3981 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3982 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3983 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3984 .features[FEAT_VMX_SECONDARY_CTLS] = 3985 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3986 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3987 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3988 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3989 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3990 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3991 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3992 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3993 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3994 .xlevel = 0x80000008, 3995 .model_id = "Intel Xeon Processor (Icelake)", 3996 .versions = (X86CPUVersionDefinition[]) { 3997 { .version = 1 }, 3998 { 3999 .version = 2, 4000 .note = "no TSX", 4001 .alias = "Icelake-Server-noTSX", 4002 .props = (PropValue[]) { 4003 { "hle", "off" }, 4004 { "rtm", "off" }, 4005 { /* end of list */ } 4006 }, 4007 }, 4008 { 4009 .version = 3, 4010 .props = (PropValue[]) { 4011 { "arch-capabilities", "on" }, 4012 { "rdctl-no", "on" }, 4013 { "ibrs-all", "on" }, 4014 { "skip-l1dfl-vmentry", "on" }, 4015 { "mds-no", "on" }, 4016 { "pschange-mc-no", "on" }, 4017 { "taa-no", "on" }, 4018 { /* end of list */ } 4019 }, 4020 }, 4021 { 4022 .version = 4, 4023 .props = (PropValue[]) { 4024 { "sha-ni", "on" }, 4025 { "avx512ifma", "on" }, 4026 { "rdpid", "on" }, 4027 { "fsrm", "on" }, 4028 { "vmx-rdseed-exit", "on" }, 4029 { "vmx-pml", "on" }, 4030 { "vmx-eptp-switching", "on" }, 4031 { "model", "106" }, 4032 { /* end of list */ } 4033 }, 4034 }, 4035 { 4036 .version = 5, 4037 .note = "XSAVES", 4038 .props = (PropValue[]) { 4039 { "xsaves", "on" }, 4040 { "vmx-xsaves", "on" }, 4041 { /* end of list */ } 4042 }, 4043 }, 4044 { 4045 .version = 6, 4046 .note = "5-level EPT", 4047 .props = (PropValue[]) { 4048 { "vmx-page-walk-5", "on" }, 4049 { /* end of list */ } 4050 }, 4051 }, 4052 { 4053 .version = 7, 4054 .note = "TSX, taa-no", 4055 .props = (PropValue[]) { 4056 /* Restore TSX features removed by -v2 above */ 4057 { "hle", "on" }, 4058 { "rtm", "on" }, 4059 { /* end of list */ } 4060 }, 4061 }, 4062 { /* end of list */ } 4063 } 4064 }, 4065 { 4066 .name = "SapphireRapids", 4067 .level = 0x20, 4068 .vendor = CPUID_VENDOR_INTEL, 4069 .family = 6, 4070 .model = 143, 4071 .stepping = 4, 4072 /* 4073 * please keep the ascending order so that we can have a clear view of 4074 * bit position of each feature. 4075 */ 4076 .features[FEAT_1_EDX] = 4077 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4078 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4079 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4080 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4081 CPUID_SSE | CPUID_SSE2, 4082 .features[FEAT_1_ECX] = 4083 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4084 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4085 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4086 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4087 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4088 .features[FEAT_8000_0001_EDX] = 4089 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4090 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4091 .features[FEAT_8000_0001_ECX] = 4092 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4093 .features[FEAT_8000_0008_EBX] = 4094 CPUID_8000_0008_EBX_WBNOINVD, 4095 .features[FEAT_7_0_EBX] = 4096 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4097 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4098 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4099 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4100 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4101 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4102 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4103 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4104 .features[FEAT_7_0_ECX] = 4105 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4106 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4107 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4108 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4109 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4110 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4111 .features[FEAT_7_0_EDX] = 4112 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4113 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4114 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4115 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4116 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4117 .features[FEAT_ARCH_CAPABILITIES] = 4118 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4119 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4120 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4121 .features[FEAT_XSAVE] = 4122 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4123 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4124 .features[FEAT_6_EAX] = 4125 CPUID_6_EAX_ARAT, 4126 .features[FEAT_7_1_EAX] = 4127 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4128 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4129 .features[FEAT_VMX_BASIC] = 4130 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4131 .features[FEAT_VMX_ENTRY_CTLS] = 4132 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4133 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4134 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4135 .features[FEAT_VMX_EPT_VPID_CAPS] = 4136 MSR_VMX_EPT_EXECONLY | 4137 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4138 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4139 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4140 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4141 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4142 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4143 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4144 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4145 .features[FEAT_VMX_EXIT_CTLS] = 4146 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4147 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4148 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4149 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4150 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4151 .features[FEAT_VMX_MISC] = 4152 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4153 MSR_VMX_MISC_VMWRITE_VMEXIT, 4154 .features[FEAT_VMX_PINBASED_CTLS] = 4155 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4156 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4157 VMX_PIN_BASED_POSTED_INTR, 4158 .features[FEAT_VMX_PROCBASED_CTLS] = 4159 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4160 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4161 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4162 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4163 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4164 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4165 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4166 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4167 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4168 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4169 VMX_CPU_BASED_PAUSE_EXITING | 4170 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4171 .features[FEAT_VMX_SECONDARY_CTLS] = 4172 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4173 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4174 VMX_SECONDARY_EXEC_RDTSCP | 4175 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4176 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4177 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4178 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4179 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4180 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4181 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4182 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4183 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4184 VMX_SECONDARY_EXEC_XSAVES, 4185 .features[FEAT_VMX_VMFUNC] = 4186 MSR_VMX_VMFUNC_EPT_SWITCHING, 4187 .xlevel = 0x80000008, 4188 .model_id = "Intel Xeon Processor (SapphireRapids)", 4189 .versions = (X86CPUVersionDefinition[]) { 4190 { .version = 1 }, 4191 { 4192 .version = 2, 4193 .props = (PropValue[]) { 4194 { "sbdr-ssdp-no", "on" }, 4195 { "fbsdp-no", "on" }, 4196 { "psdp-no", "on" }, 4197 { /* end of list */ } 4198 } 4199 }, 4200 { 4201 .version = 3, 4202 .props = (PropValue[]) { 4203 { "ss", "on" }, 4204 { "tsc-adjust", "on" }, 4205 { "cldemote", "on" }, 4206 { "movdiri", "on" }, 4207 { "movdir64b", "on" }, 4208 { /* end of list */ } 4209 } 4210 }, 4211 { /* end of list */ } 4212 } 4213 }, 4214 { 4215 .name = "GraniteRapids", 4216 .level = 0x20, 4217 .vendor = CPUID_VENDOR_INTEL, 4218 .family = 6, 4219 .model = 173, 4220 .stepping = 0, 4221 /* 4222 * please keep the ascending order so that we can have a clear view of 4223 * bit position of each feature. 4224 */ 4225 .features[FEAT_1_EDX] = 4226 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4227 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4228 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4229 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4230 CPUID_SSE | CPUID_SSE2, 4231 .features[FEAT_1_ECX] = 4232 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4233 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4234 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4235 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4236 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4237 .features[FEAT_8000_0001_EDX] = 4238 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4239 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4240 .features[FEAT_8000_0001_ECX] = 4241 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4242 .features[FEAT_8000_0008_EBX] = 4243 CPUID_8000_0008_EBX_WBNOINVD, 4244 .features[FEAT_7_0_EBX] = 4245 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4246 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4247 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4248 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4249 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4250 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4251 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4252 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4253 .features[FEAT_7_0_ECX] = 4254 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4255 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4256 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4257 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4258 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4259 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4260 .features[FEAT_7_0_EDX] = 4261 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4262 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4263 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4264 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4265 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4266 .features[FEAT_ARCH_CAPABILITIES] = 4267 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4268 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4269 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4270 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4271 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4272 .features[FEAT_XSAVE] = 4273 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4274 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4275 .features[FEAT_6_EAX] = 4276 CPUID_6_EAX_ARAT, 4277 .features[FEAT_7_1_EAX] = 4278 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4279 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4280 CPUID_7_1_EAX_AMX_FP16, 4281 .features[FEAT_7_1_EDX] = 4282 CPUID_7_1_EDX_PREFETCHITI, 4283 .features[FEAT_7_2_EDX] = 4284 CPUID_7_2_EDX_MCDT_NO, 4285 .features[FEAT_VMX_BASIC] = 4286 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4287 .features[FEAT_VMX_ENTRY_CTLS] = 4288 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4289 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4290 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4291 .features[FEAT_VMX_EPT_VPID_CAPS] = 4292 MSR_VMX_EPT_EXECONLY | 4293 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4294 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4295 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4296 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4297 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4298 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4299 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4300 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4301 .features[FEAT_VMX_EXIT_CTLS] = 4302 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4303 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4304 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4305 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4306 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4307 .features[FEAT_VMX_MISC] = 4308 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4309 MSR_VMX_MISC_VMWRITE_VMEXIT, 4310 .features[FEAT_VMX_PINBASED_CTLS] = 4311 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4312 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4313 VMX_PIN_BASED_POSTED_INTR, 4314 .features[FEAT_VMX_PROCBASED_CTLS] = 4315 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4316 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4317 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4318 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4319 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4320 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4321 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4322 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4323 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4324 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4325 VMX_CPU_BASED_PAUSE_EXITING | 4326 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4327 .features[FEAT_VMX_SECONDARY_CTLS] = 4328 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4329 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4330 VMX_SECONDARY_EXEC_RDTSCP | 4331 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4332 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4333 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4334 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4335 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4336 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4337 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4338 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4339 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4340 VMX_SECONDARY_EXEC_XSAVES, 4341 .features[FEAT_VMX_VMFUNC] = 4342 MSR_VMX_VMFUNC_EPT_SWITCHING, 4343 .xlevel = 0x80000008, 4344 .model_id = "Intel Xeon Processor (GraniteRapids)", 4345 .versions = (X86CPUVersionDefinition[]) { 4346 { .version = 1 }, 4347 { /* end of list */ }, 4348 }, 4349 }, 4350 { 4351 .name = "SierraForest", 4352 .level = 0x23, 4353 .vendor = CPUID_VENDOR_INTEL, 4354 .family = 6, 4355 .model = 175, 4356 .stepping = 0, 4357 /* 4358 * please keep the ascending order so that we can have a clear view of 4359 * bit position of each feature. 4360 */ 4361 .features[FEAT_1_EDX] = 4362 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4363 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4364 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4365 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4366 CPUID_SSE | CPUID_SSE2, 4367 .features[FEAT_1_ECX] = 4368 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4369 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4370 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4371 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4372 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4373 .features[FEAT_8000_0001_EDX] = 4374 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4375 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4376 .features[FEAT_8000_0001_ECX] = 4377 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4378 .features[FEAT_8000_0008_EBX] = 4379 CPUID_8000_0008_EBX_WBNOINVD, 4380 .features[FEAT_7_0_EBX] = 4381 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4382 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4383 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4384 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4385 CPUID_7_0_EBX_SHA_NI, 4386 .features[FEAT_7_0_ECX] = 4387 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4388 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4389 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4390 .features[FEAT_7_0_EDX] = 4391 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4392 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4393 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4394 .features[FEAT_ARCH_CAPABILITIES] = 4395 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4396 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4397 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4398 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4399 MSR_ARCH_CAP_PBRSB_NO, 4400 .features[FEAT_XSAVE] = 4401 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4402 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4403 .features[FEAT_6_EAX] = 4404 CPUID_6_EAX_ARAT, 4405 .features[FEAT_7_1_EAX] = 4406 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4407 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4408 .features[FEAT_7_1_EDX] = 4409 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4410 .features[FEAT_7_2_EDX] = 4411 CPUID_7_2_EDX_MCDT_NO, 4412 .features[FEAT_VMX_BASIC] = 4413 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4414 .features[FEAT_VMX_ENTRY_CTLS] = 4415 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4416 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4417 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4418 .features[FEAT_VMX_EPT_VPID_CAPS] = 4419 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4420 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4421 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4422 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4423 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4424 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4425 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4426 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4427 .features[FEAT_VMX_EXIT_CTLS] = 4428 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4429 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4430 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4431 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4432 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4433 .features[FEAT_VMX_MISC] = 4434 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4435 MSR_VMX_MISC_VMWRITE_VMEXIT, 4436 .features[FEAT_VMX_PINBASED_CTLS] = 4437 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4438 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4439 VMX_PIN_BASED_POSTED_INTR, 4440 .features[FEAT_VMX_PROCBASED_CTLS] = 4441 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4442 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4443 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4444 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4445 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4446 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4447 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4448 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4449 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4450 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4451 VMX_CPU_BASED_PAUSE_EXITING | 4452 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4453 .features[FEAT_VMX_SECONDARY_CTLS] = 4454 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4455 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4456 VMX_SECONDARY_EXEC_RDTSCP | 4457 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4458 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4459 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4460 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4461 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4462 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4463 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4464 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4465 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4466 VMX_SECONDARY_EXEC_XSAVES, 4467 .features[FEAT_VMX_VMFUNC] = 4468 MSR_VMX_VMFUNC_EPT_SWITCHING, 4469 .xlevel = 0x80000008, 4470 .model_id = "Intel Xeon Processor (SierraForest)", 4471 .versions = (X86CPUVersionDefinition[]) { 4472 { .version = 1 }, 4473 { /* end of list */ }, 4474 }, 4475 }, 4476 { 4477 .name = "Denverton", 4478 .level = 21, 4479 .vendor = CPUID_VENDOR_INTEL, 4480 .family = 6, 4481 .model = 95, 4482 .stepping = 1, 4483 .features[FEAT_1_EDX] = 4484 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4485 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4486 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4487 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4488 CPUID_SSE | CPUID_SSE2, 4489 .features[FEAT_1_ECX] = 4490 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4491 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4492 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4493 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4494 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4495 .features[FEAT_8000_0001_EDX] = 4496 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4497 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4498 .features[FEAT_8000_0001_ECX] = 4499 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4500 .features[FEAT_7_0_EBX] = 4501 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4502 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4503 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4504 .features[FEAT_7_0_EDX] = 4505 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4506 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4507 /* XSAVES is added in version 3 */ 4508 .features[FEAT_XSAVE] = 4509 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4510 .features[FEAT_6_EAX] = 4511 CPUID_6_EAX_ARAT, 4512 .features[FEAT_ARCH_CAPABILITIES] = 4513 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4514 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4515 MSR_VMX_BASIC_TRUE_CTLS, 4516 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4517 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4518 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4519 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4520 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4521 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4522 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4523 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4524 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4525 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4526 .features[FEAT_VMX_EXIT_CTLS] = 4527 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4528 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4529 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4530 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4531 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4532 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4533 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4534 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4535 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4536 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4537 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4538 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4539 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4540 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4541 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4542 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4543 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4544 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4545 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4546 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4547 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4548 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4549 .features[FEAT_VMX_SECONDARY_CTLS] = 4550 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4551 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4552 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4553 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4554 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4555 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4556 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4557 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4558 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4559 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4560 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4561 .xlevel = 0x80000008, 4562 .model_id = "Intel Atom Processor (Denverton)", 4563 .versions = (X86CPUVersionDefinition[]) { 4564 { .version = 1 }, 4565 { 4566 .version = 2, 4567 .note = "no MPX, no MONITOR", 4568 .props = (PropValue[]) { 4569 { "monitor", "off" }, 4570 { "mpx", "off" }, 4571 { /* end of list */ }, 4572 }, 4573 }, 4574 { 4575 .version = 3, 4576 .note = "XSAVES, no MPX, no MONITOR", 4577 .props = (PropValue[]) { 4578 { "xsaves", "on" }, 4579 { "vmx-xsaves", "on" }, 4580 { /* end of list */ }, 4581 }, 4582 }, 4583 { /* end of list */ }, 4584 }, 4585 }, 4586 { 4587 .name = "Snowridge", 4588 .level = 27, 4589 .vendor = CPUID_VENDOR_INTEL, 4590 .family = 6, 4591 .model = 134, 4592 .stepping = 1, 4593 .features[FEAT_1_EDX] = 4594 /* missing: CPUID_PN CPUID_IA64 */ 4595 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4596 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4597 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4598 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4599 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4600 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4601 CPUID_MMX | 4602 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4603 .features[FEAT_1_ECX] = 4604 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4605 CPUID_EXT_SSSE3 | 4606 CPUID_EXT_CX16 | 4607 CPUID_EXT_SSE41 | 4608 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4609 CPUID_EXT_POPCNT | 4610 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4611 CPUID_EXT_RDRAND, 4612 .features[FEAT_8000_0001_EDX] = 4613 CPUID_EXT2_SYSCALL | 4614 CPUID_EXT2_NX | 4615 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4616 CPUID_EXT2_LM, 4617 .features[FEAT_8000_0001_ECX] = 4618 CPUID_EXT3_LAHF_LM | 4619 CPUID_EXT3_3DNOWPREFETCH, 4620 .features[FEAT_7_0_EBX] = 4621 CPUID_7_0_EBX_FSGSBASE | 4622 CPUID_7_0_EBX_SMEP | 4623 CPUID_7_0_EBX_ERMS | 4624 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4625 CPUID_7_0_EBX_RDSEED | 4626 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4627 CPUID_7_0_EBX_CLWB | 4628 CPUID_7_0_EBX_SHA_NI, 4629 .features[FEAT_7_0_ECX] = 4630 CPUID_7_0_ECX_UMIP | 4631 /* missing bit 5 */ 4632 CPUID_7_0_ECX_GFNI | 4633 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4634 CPUID_7_0_ECX_MOVDIR64B, 4635 .features[FEAT_7_0_EDX] = 4636 CPUID_7_0_EDX_SPEC_CTRL | 4637 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4638 CPUID_7_0_EDX_CORE_CAPABILITY, 4639 .features[FEAT_CORE_CAPABILITY] = 4640 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4641 /* XSAVES is added in version 3 */ 4642 .features[FEAT_XSAVE] = 4643 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4644 CPUID_XSAVE_XGETBV1, 4645 .features[FEAT_6_EAX] = 4646 CPUID_6_EAX_ARAT, 4647 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4648 MSR_VMX_BASIC_TRUE_CTLS, 4649 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4650 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4651 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4652 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4653 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4654 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4655 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4656 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4657 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4658 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4659 .features[FEAT_VMX_EXIT_CTLS] = 4660 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4661 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4662 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4663 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4664 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4665 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4666 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4667 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4668 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4669 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4670 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4671 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4672 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4673 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4674 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4675 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4676 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4677 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4678 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4679 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4680 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4681 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4682 .features[FEAT_VMX_SECONDARY_CTLS] = 4683 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4684 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4685 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4686 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4687 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4688 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4689 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4690 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4691 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4692 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4693 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4694 .xlevel = 0x80000008, 4695 .model_id = "Intel Atom Processor (SnowRidge)", 4696 .versions = (X86CPUVersionDefinition[]) { 4697 { .version = 1 }, 4698 { 4699 .version = 2, 4700 .props = (PropValue[]) { 4701 { "mpx", "off" }, 4702 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4703 { /* end of list */ }, 4704 }, 4705 }, 4706 { 4707 .version = 3, 4708 .note = "XSAVES, no MPX", 4709 .props = (PropValue[]) { 4710 { "xsaves", "on" }, 4711 { "vmx-xsaves", "on" }, 4712 { /* end of list */ }, 4713 }, 4714 }, 4715 { 4716 .version = 4, 4717 .note = "no split lock detect, no core-capability", 4718 .props = (PropValue[]) { 4719 { "split-lock-detect", "off" }, 4720 { "core-capability", "off" }, 4721 { /* end of list */ }, 4722 }, 4723 }, 4724 { /* end of list */ }, 4725 }, 4726 }, 4727 { 4728 .name = "KnightsMill", 4729 .level = 0xd, 4730 .vendor = CPUID_VENDOR_INTEL, 4731 .family = 6, 4732 .model = 133, 4733 .stepping = 0, 4734 .features[FEAT_1_EDX] = 4735 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4736 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4737 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4738 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4739 CPUID_PSE | CPUID_DE | CPUID_FP87, 4740 .features[FEAT_1_ECX] = 4741 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4742 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4743 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4744 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4745 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4746 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4747 .features[FEAT_8000_0001_EDX] = 4748 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4749 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4750 .features[FEAT_8000_0001_ECX] = 4751 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4752 .features[FEAT_7_0_EBX] = 4753 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4754 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4755 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4756 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4757 CPUID_7_0_EBX_AVX512ER, 4758 .features[FEAT_7_0_ECX] = 4759 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4760 .features[FEAT_7_0_EDX] = 4761 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4762 .features[FEAT_XSAVE] = 4763 CPUID_XSAVE_XSAVEOPT, 4764 .features[FEAT_6_EAX] = 4765 CPUID_6_EAX_ARAT, 4766 .xlevel = 0x80000008, 4767 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4768 }, 4769 { 4770 .name = "Opteron_G1", 4771 .level = 5, 4772 .vendor = CPUID_VENDOR_AMD, 4773 .family = 15, 4774 .model = 6, 4775 .stepping = 1, 4776 .features[FEAT_1_EDX] = 4777 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4778 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4779 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4780 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4781 CPUID_DE | CPUID_FP87, 4782 .features[FEAT_1_ECX] = 4783 CPUID_EXT_SSE3, 4784 .features[FEAT_8000_0001_EDX] = 4785 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4786 .xlevel = 0x80000008, 4787 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4788 }, 4789 { 4790 .name = "Opteron_G2", 4791 .level = 5, 4792 .vendor = CPUID_VENDOR_AMD, 4793 .family = 15, 4794 .model = 6, 4795 .stepping = 1, 4796 .features[FEAT_1_EDX] = 4797 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4798 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4799 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4800 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4801 CPUID_DE | CPUID_FP87, 4802 .features[FEAT_1_ECX] = 4803 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4804 .features[FEAT_8000_0001_EDX] = 4805 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4806 .features[FEAT_8000_0001_ECX] = 4807 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4808 .xlevel = 0x80000008, 4809 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4810 }, 4811 { 4812 .name = "Opteron_G3", 4813 .level = 5, 4814 .vendor = CPUID_VENDOR_AMD, 4815 .family = 16, 4816 .model = 2, 4817 .stepping = 3, 4818 .features[FEAT_1_EDX] = 4819 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4820 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4821 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4822 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4823 CPUID_DE | CPUID_FP87, 4824 .features[FEAT_1_ECX] = 4825 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4826 CPUID_EXT_SSE3, 4827 .features[FEAT_8000_0001_EDX] = 4828 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4829 CPUID_EXT2_RDTSCP, 4830 .features[FEAT_8000_0001_ECX] = 4831 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4832 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4833 .xlevel = 0x80000008, 4834 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4835 }, 4836 { 4837 .name = "Opteron_G4", 4838 .level = 0xd, 4839 .vendor = CPUID_VENDOR_AMD, 4840 .family = 21, 4841 .model = 1, 4842 .stepping = 2, 4843 .features[FEAT_1_EDX] = 4844 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4845 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4846 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4847 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4848 CPUID_DE | CPUID_FP87, 4849 .features[FEAT_1_ECX] = 4850 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4851 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4852 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4853 CPUID_EXT_SSE3, 4854 .features[FEAT_8000_0001_EDX] = 4855 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4856 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4857 .features[FEAT_8000_0001_ECX] = 4858 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4859 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4860 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4861 CPUID_EXT3_LAHF_LM, 4862 .features[FEAT_SVM] = 4863 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4864 /* no xsaveopt! */ 4865 .xlevel = 0x8000001A, 4866 .model_id = "AMD Opteron 62xx class CPU", 4867 }, 4868 { 4869 .name = "Opteron_G5", 4870 .level = 0xd, 4871 .vendor = CPUID_VENDOR_AMD, 4872 .family = 21, 4873 .model = 2, 4874 .stepping = 0, 4875 .features[FEAT_1_EDX] = 4876 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4880 CPUID_DE | CPUID_FP87, 4881 .features[FEAT_1_ECX] = 4882 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4883 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4884 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4885 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4886 .features[FEAT_8000_0001_EDX] = 4887 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4888 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4889 .features[FEAT_8000_0001_ECX] = 4890 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4891 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4892 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4893 CPUID_EXT3_LAHF_LM, 4894 .features[FEAT_SVM] = 4895 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4896 /* no xsaveopt! */ 4897 .xlevel = 0x8000001A, 4898 .model_id = "AMD Opteron 63xx class CPU", 4899 }, 4900 { 4901 .name = "EPYC", 4902 .level = 0xd, 4903 .vendor = CPUID_VENDOR_AMD, 4904 .family = 23, 4905 .model = 1, 4906 .stepping = 2, 4907 .features[FEAT_1_EDX] = 4908 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4909 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4910 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4911 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4912 CPUID_VME | CPUID_FP87, 4913 .features[FEAT_1_ECX] = 4914 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4915 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4916 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4917 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4918 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4919 .features[FEAT_8000_0001_EDX] = 4920 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4921 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4922 CPUID_EXT2_SYSCALL, 4923 .features[FEAT_8000_0001_ECX] = 4924 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4925 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4926 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4927 CPUID_EXT3_TOPOEXT, 4928 .features[FEAT_7_0_EBX] = 4929 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4930 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4931 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4932 CPUID_7_0_EBX_SHA_NI, 4933 .features[FEAT_XSAVE] = 4934 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4935 CPUID_XSAVE_XGETBV1, 4936 .features[FEAT_6_EAX] = 4937 CPUID_6_EAX_ARAT, 4938 .features[FEAT_SVM] = 4939 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4940 .xlevel = 0x8000001E, 4941 .model_id = "AMD EPYC Processor", 4942 .cache_info = &epyc_cache_info, 4943 .versions = (X86CPUVersionDefinition[]) { 4944 { .version = 1 }, 4945 { 4946 .version = 2, 4947 .alias = "EPYC-IBPB", 4948 .props = (PropValue[]) { 4949 { "ibpb", "on" }, 4950 { "model-id", 4951 "AMD EPYC Processor (with IBPB)" }, 4952 { /* end of list */ } 4953 } 4954 }, 4955 { 4956 .version = 3, 4957 .props = (PropValue[]) { 4958 { "ibpb", "on" }, 4959 { "perfctr-core", "on" }, 4960 { "clzero", "on" }, 4961 { "xsaveerptr", "on" }, 4962 { "xsaves", "on" }, 4963 { "model-id", 4964 "AMD EPYC Processor" }, 4965 { /* end of list */ } 4966 } 4967 }, 4968 { 4969 .version = 4, 4970 .props = (PropValue[]) { 4971 { "model-id", 4972 "AMD EPYC-v4 Processor" }, 4973 { /* end of list */ } 4974 }, 4975 .cache_info = &epyc_v4_cache_info 4976 }, 4977 { /* end of list */ } 4978 } 4979 }, 4980 { 4981 .name = "Dhyana", 4982 .level = 0xd, 4983 .vendor = CPUID_VENDOR_HYGON, 4984 .family = 24, 4985 .model = 0, 4986 .stepping = 1, 4987 .features[FEAT_1_EDX] = 4988 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4989 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4990 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4991 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4992 CPUID_VME | CPUID_FP87, 4993 .features[FEAT_1_ECX] = 4994 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4995 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4996 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4997 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4998 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4999 .features[FEAT_8000_0001_EDX] = 5000 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5001 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5002 CPUID_EXT2_SYSCALL, 5003 .features[FEAT_8000_0001_ECX] = 5004 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5005 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5006 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5007 CPUID_EXT3_TOPOEXT, 5008 .features[FEAT_8000_0008_EBX] = 5009 CPUID_8000_0008_EBX_IBPB, 5010 .features[FEAT_7_0_EBX] = 5011 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5012 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5013 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5014 /* XSAVES is added in version 2 */ 5015 .features[FEAT_XSAVE] = 5016 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5017 CPUID_XSAVE_XGETBV1, 5018 .features[FEAT_6_EAX] = 5019 CPUID_6_EAX_ARAT, 5020 .features[FEAT_SVM] = 5021 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5022 .xlevel = 0x8000001E, 5023 .model_id = "Hygon Dhyana Processor", 5024 .cache_info = &epyc_cache_info, 5025 .versions = (X86CPUVersionDefinition[]) { 5026 { .version = 1 }, 5027 { .version = 2, 5028 .note = "XSAVES", 5029 .props = (PropValue[]) { 5030 { "xsaves", "on" }, 5031 { /* end of list */ } 5032 }, 5033 }, 5034 { /* end of list */ } 5035 } 5036 }, 5037 { 5038 .name = "EPYC-Rome", 5039 .level = 0xd, 5040 .vendor = CPUID_VENDOR_AMD, 5041 .family = 23, 5042 .model = 49, 5043 .stepping = 0, 5044 .features[FEAT_1_EDX] = 5045 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5046 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5047 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5048 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5049 CPUID_VME | CPUID_FP87, 5050 .features[FEAT_1_ECX] = 5051 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5052 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5053 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5054 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5055 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5056 .features[FEAT_8000_0001_EDX] = 5057 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5058 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5059 CPUID_EXT2_SYSCALL, 5060 .features[FEAT_8000_0001_ECX] = 5061 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5062 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5063 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5064 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5065 .features[FEAT_8000_0008_EBX] = 5066 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5067 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5068 CPUID_8000_0008_EBX_STIBP, 5069 .features[FEAT_7_0_EBX] = 5070 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5071 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5072 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5073 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5074 .features[FEAT_7_0_ECX] = 5075 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5076 .features[FEAT_XSAVE] = 5077 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5078 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5079 .features[FEAT_6_EAX] = 5080 CPUID_6_EAX_ARAT, 5081 .features[FEAT_SVM] = 5082 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5083 .xlevel = 0x8000001E, 5084 .model_id = "AMD EPYC-Rome Processor", 5085 .cache_info = &epyc_rome_cache_info, 5086 .versions = (X86CPUVersionDefinition[]) { 5087 { .version = 1 }, 5088 { 5089 .version = 2, 5090 .props = (PropValue[]) { 5091 { "ibrs", "on" }, 5092 { "amd-ssbd", "on" }, 5093 { /* end of list */ } 5094 } 5095 }, 5096 { 5097 .version = 3, 5098 .props = (PropValue[]) { 5099 { "model-id", 5100 "AMD EPYC-Rome-v3 Processor" }, 5101 { /* end of list */ } 5102 }, 5103 .cache_info = &epyc_rome_v3_cache_info 5104 }, 5105 { 5106 .version = 4, 5107 .props = (PropValue[]) { 5108 /* Erratum 1386 */ 5109 { "model-id", 5110 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5111 { "xsaves", "off" }, 5112 { /* end of list */ } 5113 }, 5114 }, 5115 { /* end of list */ } 5116 } 5117 }, 5118 { 5119 .name = "EPYC-Milan", 5120 .level = 0xd, 5121 .vendor = CPUID_VENDOR_AMD, 5122 .family = 25, 5123 .model = 1, 5124 .stepping = 1, 5125 .features[FEAT_1_EDX] = 5126 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5127 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5128 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5129 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5130 CPUID_VME | CPUID_FP87, 5131 .features[FEAT_1_ECX] = 5132 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5133 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5134 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5135 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5136 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5137 CPUID_EXT_PCID, 5138 .features[FEAT_8000_0001_EDX] = 5139 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5140 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5141 CPUID_EXT2_SYSCALL, 5142 .features[FEAT_8000_0001_ECX] = 5143 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5144 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5145 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5146 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5147 .features[FEAT_8000_0008_EBX] = 5148 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5149 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5150 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5151 CPUID_8000_0008_EBX_AMD_SSBD, 5152 .features[FEAT_7_0_EBX] = 5153 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5154 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5155 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5156 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5157 CPUID_7_0_EBX_INVPCID, 5158 .features[FEAT_7_0_ECX] = 5159 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5160 .features[FEAT_7_0_EDX] = 5161 CPUID_7_0_EDX_FSRM, 5162 .features[FEAT_XSAVE] = 5163 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5164 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5165 .features[FEAT_6_EAX] = 5166 CPUID_6_EAX_ARAT, 5167 .features[FEAT_SVM] = 5168 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5169 .xlevel = 0x8000001E, 5170 .model_id = "AMD EPYC-Milan Processor", 5171 .cache_info = &epyc_milan_cache_info, 5172 .versions = (X86CPUVersionDefinition[]) { 5173 { .version = 1 }, 5174 { 5175 .version = 2, 5176 .props = (PropValue[]) { 5177 { "model-id", 5178 "AMD EPYC-Milan-v2 Processor" }, 5179 { "vaes", "on" }, 5180 { "vpclmulqdq", "on" }, 5181 { "stibp-always-on", "on" }, 5182 { "amd-psfd", "on" }, 5183 { "no-nested-data-bp", "on" }, 5184 { "lfence-always-serializing", "on" }, 5185 { "null-sel-clr-base", "on" }, 5186 { /* end of list */ } 5187 }, 5188 .cache_info = &epyc_milan_v2_cache_info 5189 }, 5190 { /* end of list */ } 5191 } 5192 }, 5193 { 5194 .name = "EPYC-Genoa", 5195 .level = 0xd, 5196 .vendor = CPUID_VENDOR_AMD, 5197 .family = 25, 5198 .model = 17, 5199 .stepping = 0, 5200 .features[FEAT_1_EDX] = 5201 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5202 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5203 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5204 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5205 CPUID_VME | CPUID_FP87, 5206 .features[FEAT_1_ECX] = 5207 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5208 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5209 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5210 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5211 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5212 CPUID_EXT_SSE3, 5213 .features[FEAT_8000_0001_EDX] = 5214 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5215 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5216 CPUID_EXT2_SYSCALL, 5217 .features[FEAT_8000_0001_ECX] = 5218 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5219 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5220 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5221 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5222 .features[FEAT_8000_0008_EBX] = 5223 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5224 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5225 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5226 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5227 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5228 .features[FEAT_8000_0021_EAX] = 5229 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 5230 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5231 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5232 CPUID_8000_0021_EAX_AUTO_IBRS, 5233 .features[FEAT_7_0_EBX] = 5234 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5235 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5236 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5237 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5238 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5239 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5240 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5241 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5242 .features[FEAT_7_0_ECX] = 5243 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5244 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5245 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5246 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5247 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5248 CPUID_7_0_ECX_RDPID, 5249 .features[FEAT_7_0_EDX] = 5250 CPUID_7_0_EDX_FSRM, 5251 .features[FEAT_7_1_EAX] = 5252 CPUID_7_1_EAX_AVX512_BF16, 5253 .features[FEAT_XSAVE] = 5254 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5255 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5256 .features[FEAT_6_EAX] = 5257 CPUID_6_EAX_ARAT, 5258 .features[FEAT_SVM] = 5259 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5260 CPUID_SVM_SVME_ADDR_CHK, 5261 .xlevel = 0x80000022, 5262 .model_id = "AMD EPYC-Genoa Processor", 5263 .cache_info = &epyc_genoa_cache_info, 5264 }, 5265 }; 5266 5267 /* 5268 * We resolve CPU model aliases using -v1 when using "-machine 5269 * none", but this is just for compatibility while libvirt isn't 5270 * adapted to resolve CPU model versions before creating VMs. 5271 * See "Runnability guarantee of CPU models" at 5272 * docs/about/deprecated.rst. 5273 */ 5274 X86CPUVersion default_cpu_version = 1; 5275 5276 void x86_cpu_set_default_version(X86CPUVersion version) 5277 { 5278 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5279 assert(version != CPU_VERSION_AUTO); 5280 default_cpu_version = version; 5281 } 5282 5283 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5284 { 5285 int v = 0; 5286 const X86CPUVersionDefinition *vdef = 5287 x86_cpu_def_get_versions(model->cpudef); 5288 while (vdef->version) { 5289 v = vdef->version; 5290 vdef++; 5291 } 5292 return v; 5293 } 5294 5295 /* Return the actual version being used for a specific CPU model */ 5296 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5297 { 5298 X86CPUVersion v = model->version; 5299 if (v == CPU_VERSION_AUTO) { 5300 v = default_cpu_version; 5301 } 5302 if (v == CPU_VERSION_LATEST) { 5303 return x86_cpu_model_last_version(model); 5304 } 5305 return v; 5306 } 5307 5308 static Property max_x86_cpu_properties[] = { 5309 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5310 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5311 DEFINE_PROP_END_OF_LIST() 5312 }; 5313 5314 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5315 { 5316 Object *obj = OBJECT(dev); 5317 5318 if (!object_property_get_int(obj, "family", &error_abort)) { 5319 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5320 object_property_set_int(obj, "family", 15, &error_abort); 5321 object_property_set_int(obj, "model", 107, &error_abort); 5322 object_property_set_int(obj, "stepping", 1, &error_abort); 5323 } else { 5324 object_property_set_int(obj, "family", 6, &error_abort); 5325 object_property_set_int(obj, "model", 6, &error_abort); 5326 object_property_set_int(obj, "stepping", 3, &error_abort); 5327 } 5328 } 5329 5330 x86_cpu_realizefn(dev, errp); 5331 } 5332 5333 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5334 { 5335 DeviceClass *dc = DEVICE_CLASS(oc); 5336 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5337 5338 xcc->ordering = 9; 5339 5340 xcc->model_description = 5341 "Enables all features supported by the accelerator in the current host"; 5342 5343 device_class_set_props(dc, max_x86_cpu_properties); 5344 dc->realize = max_x86_cpu_realize; 5345 } 5346 5347 static void max_x86_cpu_initfn(Object *obj) 5348 { 5349 X86CPU *cpu = X86_CPU(obj); 5350 5351 /* We can't fill the features array here because we don't know yet if 5352 * "migratable" is true or false. 5353 */ 5354 cpu->max_features = true; 5355 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5356 5357 /* 5358 * these defaults are used for TCG and all other accelerators 5359 * besides KVM and HVF, which overwrite these values 5360 */ 5361 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5362 &error_abort); 5363 object_property_set_str(OBJECT(cpu), "model-id", 5364 "QEMU TCG CPU version " QEMU_HW_VERSION, 5365 &error_abort); 5366 } 5367 5368 static const TypeInfo max_x86_cpu_type_info = { 5369 .name = X86_CPU_TYPE_NAME("max"), 5370 .parent = TYPE_X86_CPU, 5371 .instance_init = max_x86_cpu_initfn, 5372 .class_init = max_x86_cpu_class_init, 5373 }; 5374 5375 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5376 { 5377 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5378 5379 switch (f->type) { 5380 case CPUID_FEATURE_WORD: 5381 { 5382 const char *reg = get_register_name_32(f->cpuid.reg); 5383 assert(reg); 5384 return g_strdup_printf("CPUID.%02XH:%s", 5385 f->cpuid.eax, reg); 5386 } 5387 case MSR_FEATURE_WORD: 5388 return g_strdup_printf("MSR(%02XH)", 5389 f->msr.index); 5390 } 5391 5392 return NULL; 5393 } 5394 5395 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5396 { 5397 FeatureWord w; 5398 5399 for (w = 0; w < FEATURE_WORDS; w++) { 5400 if (cpu->filtered_features[w]) { 5401 return true; 5402 } 5403 } 5404 5405 return false; 5406 } 5407 5408 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5409 const char *verbose_prefix) 5410 { 5411 CPUX86State *env = &cpu->env; 5412 FeatureWordInfo *f = &feature_word_info[w]; 5413 int i; 5414 5415 if (!cpu->force_features) { 5416 env->features[w] &= ~mask; 5417 } 5418 cpu->filtered_features[w] |= mask; 5419 5420 if (!verbose_prefix) { 5421 return; 5422 } 5423 5424 for (i = 0; i < 64; ++i) { 5425 if ((1ULL << i) & mask) { 5426 g_autofree char *feat_word_str = feature_word_description(f, i); 5427 warn_report("%s: %s%s%s [bit %d]", 5428 verbose_prefix, 5429 feat_word_str, 5430 f->feat_names[i] ? "." : "", 5431 f->feat_names[i] ? f->feat_names[i] : "", i); 5432 } 5433 } 5434 } 5435 5436 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5437 const char *name, void *opaque, 5438 Error **errp) 5439 { 5440 X86CPU *cpu = X86_CPU(obj); 5441 CPUX86State *env = &cpu->env; 5442 uint64_t value; 5443 5444 value = (env->cpuid_version >> 8) & 0xf; 5445 if (value == 0xf) { 5446 value += (env->cpuid_version >> 20) & 0xff; 5447 } 5448 visit_type_uint64(v, name, &value, errp); 5449 } 5450 5451 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5452 const char *name, void *opaque, 5453 Error **errp) 5454 { 5455 X86CPU *cpu = X86_CPU(obj); 5456 CPUX86State *env = &cpu->env; 5457 const uint64_t max = 0xff + 0xf; 5458 uint64_t value; 5459 5460 if (!visit_type_uint64(v, name, &value, errp)) { 5461 return; 5462 } 5463 if (value > max) { 5464 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5465 name ? name : "null", max); 5466 return; 5467 } 5468 5469 env->cpuid_version &= ~0xff00f00; 5470 if (value > 0x0f) { 5471 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5472 } else { 5473 env->cpuid_version |= value << 8; 5474 } 5475 } 5476 5477 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5478 const char *name, void *opaque, 5479 Error **errp) 5480 { 5481 X86CPU *cpu = X86_CPU(obj); 5482 CPUX86State *env = &cpu->env; 5483 uint64_t value; 5484 5485 value = (env->cpuid_version >> 4) & 0xf; 5486 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5487 visit_type_uint64(v, name, &value, errp); 5488 } 5489 5490 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5491 const char *name, void *opaque, 5492 Error **errp) 5493 { 5494 X86CPU *cpu = X86_CPU(obj); 5495 CPUX86State *env = &cpu->env; 5496 const uint64_t max = 0xff; 5497 uint64_t value; 5498 5499 if (!visit_type_uint64(v, name, &value, errp)) { 5500 return; 5501 } 5502 if (value > max) { 5503 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5504 name ? name : "null", max); 5505 return; 5506 } 5507 5508 env->cpuid_version &= ~0xf00f0; 5509 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5510 } 5511 5512 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5513 const char *name, void *opaque, 5514 Error **errp) 5515 { 5516 X86CPU *cpu = X86_CPU(obj); 5517 CPUX86State *env = &cpu->env; 5518 uint64_t value; 5519 5520 value = env->cpuid_version & 0xf; 5521 visit_type_uint64(v, name, &value, errp); 5522 } 5523 5524 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5525 const char *name, void *opaque, 5526 Error **errp) 5527 { 5528 X86CPU *cpu = X86_CPU(obj); 5529 CPUX86State *env = &cpu->env; 5530 const uint64_t max = 0xf; 5531 uint64_t value; 5532 5533 if (!visit_type_uint64(v, name, &value, errp)) { 5534 return; 5535 } 5536 if (value > max) { 5537 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5538 name ? name : "null", max); 5539 return; 5540 } 5541 5542 env->cpuid_version &= ~0xf; 5543 env->cpuid_version |= value & 0xf; 5544 } 5545 5546 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5547 { 5548 X86CPU *cpu = X86_CPU(obj); 5549 CPUX86State *env = &cpu->env; 5550 char *value; 5551 5552 value = g_malloc(CPUID_VENDOR_SZ + 1); 5553 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5554 env->cpuid_vendor3); 5555 return value; 5556 } 5557 5558 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5559 Error **errp) 5560 { 5561 X86CPU *cpu = X86_CPU(obj); 5562 CPUX86State *env = &cpu->env; 5563 int i; 5564 5565 if (strlen(value) != CPUID_VENDOR_SZ) { 5566 error_setg(errp, "value of property 'vendor' must consist of" 5567 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5568 return; 5569 } 5570 5571 env->cpuid_vendor1 = 0; 5572 env->cpuid_vendor2 = 0; 5573 env->cpuid_vendor3 = 0; 5574 for (i = 0; i < 4; i++) { 5575 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5576 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5577 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5578 } 5579 } 5580 5581 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5582 { 5583 X86CPU *cpu = X86_CPU(obj); 5584 CPUX86State *env = &cpu->env; 5585 char *value; 5586 int i; 5587 5588 value = g_malloc(48 + 1); 5589 for (i = 0; i < 48; i++) { 5590 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5591 } 5592 value[48] = '\0'; 5593 return value; 5594 } 5595 5596 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5597 Error **errp) 5598 { 5599 X86CPU *cpu = X86_CPU(obj); 5600 CPUX86State *env = &cpu->env; 5601 int c, len, i; 5602 5603 if (model_id == NULL) { 5604 model_id = ""; 5605 } 5606 len = strlen(model_id); 5607 memset(env->cpuid_model, 0, 48); 5608 for (i = 0; i < 48; i++) { 5609 if (i >= len) { 5610 c = '\0'; 5611 } else { 5612 c = (uint8_t)model_id[i]; 5613 } 5614 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5615 } 5616 } 5617 5618 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5619 void *opaque, Error **errp) 5620 { 5621 X86CPU *cpu = X86_CPU(obj); 5622 int64_t value; 5623 5624 value = cpu->env.tsc_khz * 1000; 5625 visit_type_int(v, name, &value, errp); 5626 } 5627 5628 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5629 void *opaque, Error **errp) 5630 { 5631 X86CPU *cpu = X86_CPU(obj); 5632 const int64_t max = INT64_MAX; 5633 int64_t value; 5634 5635 if (!visit_type_int(v, name, &value, errp)) { 5636 return; 5637 } 5638 if (value < 0 || value > max) { 5639 error_setg(errp, "parameter '%s' can be at most %" PRId64, 5640 name ? name : "null", max); 5641 return; 5642 } 5643 5644 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5645 } 5646 5647 /* Generic getter for "feature-words" and "filtered-features" properties */ 5648 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5649 const char *name, void *opaque, 5650 Error **errp) 5651 { 5652 uint64_t *array = (uint64_t *)opaque; 5653 FeatureWord w; 5654 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5655 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5656 X86CPUFeatureWordInfoList *list = NULL; 5657 5658 for (w = 0; w < FEATURE_WORDS; w++) { 5659 FeatureWordInfo *wi = &feature_word_info[w]; 5660 /* 5661 * We didn't have MSR features when "feature-words" was 5662 * introduced. Therefore skipped other type entries. 5663 */ 5664 if (wi->type != CPUID_FEATURE_WORD) { 5665 continue; 5666 } 5667 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5668 qwi->cpuid_input_eax = wi->cpuid.eax; 5669 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5670 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5671 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5672 qwi->features = array[w]; 5673 5674 /* List will be in reverse order, but order shouldn't matter */ 5675 list_entries[w].next = list; 5676 list_entries[w].value = &word_infos[w]; 5677 list = &list_entries[w]; 5678 } 5679 5680 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5681 } 5682 5683 /* Convert all '_' in a feature string option name to '-', to make feature 5684 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5685 */ 5686 static inline void feat2prop(char *s) 5687 { 5688 while ((s = strchr(s, '_'))) { 5689 *s = '-'; 5690 } 5691 } 5692 5693 /* Return the feature property name for a feature flag bit */ 5694 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5695 { 5696 const char *name; 5697 /* XSAVE components are automatically enabled by other features, 5698 * so return the original feature name instead 5699 */ 5700 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5701 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5702 5703 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5704 x86_ext_save_areas[comp].bits) { 5705 w = x86_ext_save_areas[comp].feature; 5706 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5707 } 5708 } 5709 5710 assert(bitnr < 64); 5711 assert(w < FEATURE_WORDS); 5712 name = feature_word_info[w].feat_names[bitnr]; 5713 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5714 return name; 5715 } 5716 5717 /* Compatibility hack to maintain legacy +-feat semantic, 5718 * where +-feat overwrites any feature set by 5719 * feat=on|feat even if the later is parsed after +-feat 5720 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5721 */ 5722 static GList *plus_features, *minus_features; 5723 5724 static gint compare_string(gconstpointer a, gconstpointer b) 5725 { 5726 return g_strcmp0(a, b); 5727 } 5728 5729 /* Parse "+feature,-feature,feature=foo" CPU feature string 5730 */ 5731 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5732 Error **errp) 5733 { 5734 char *featurestr; /* Single 'key=value" string being parsed */ 5735 static bool cpu_globals_initialized; 5736 bool ambiguous = false; 5737 5738 if (cpu_globals_initialized) { 5739 return; 5740 } 5741 cpu_globals_initialized = true; 5742 5743 if (!features) { 5744 return; 5745 } 5746 5747 for (featurestr = strtok(features, ","); 5748 featurestr; 5749 featurestr = strtok(NULL, ",")) { 5750 const char *name; 5751 const char *val = NULL; 5752 char *eq = NULL; 5753 char num[32]; 5754 GlobalProperty *prop; 5755 5756 /* Compatibility syntax: */ 5757 if (featurestr[0] == '+') { 5758 plus_features = g_list_append(plus_features, 5759 g_strdup(featurestr + 1)); 5760 continue; 5761 } else if (featurestr[0] == '-') { 5762 minus_features = g_list_append(minus_features, 5763 g_strdup(featurestr + 1)); 5764 continue; 5765 } 5766 5767 eq = strchr(featurestr, '='); 5768 if (eq) { 5769 *eq++ = 0; 5770 val = eq; 5771 } else { 5772 val = "on"; 5773 } 5774 5775 feat2prop(featurestr); 5776 name = featurestr; 5777 5778 if (g_list_find_custom(plus_features, name, compare_string)) { 5779 warn_report("Ambiguous CPU model string. " 5780 "Don't mix both \"+%s\" and \"%s=%s\"", 5781 name, name, val); 5782 ambiguous = true; 5783 } 5784 if (g_list_find_custom(minus_features, name, compare_string)) { 5785 warn_report("Ambiguous CPU model string. " 5786 "Don't mix both \"-%s\" and \"%s=%s\"", 5787 name, name, val); 5788 ambiguous = true; 5789 } 5790 5791 /* Special case: */ 5792 if (!strcmp(name, "tsc-freq")) { 5793 int ret; 5794 uint64_t tsc_freq; 5795 5796 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5797 if (ret < 0 || tsc_freq > INT64_MAX) { 5798 error_setg(errp, "bad numerical value %s", val); 5799 return; 5800 } 5801 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5802 val = num; 5803 name = "tsc-frequency"; 5804 } 5805 5806 prop = g_new0(typeof(*prop), 1); 5807 prop->driver = typename; 5808 prop->property = g_strdup(name); 5809 prop->value = g_strdup(val); 5810 qdev_prop_register_global(prop); 5811 } 5812 5813 if (ambiguous) { 5814 warn_report("Compatibility of ambiguous CPU model " 5815 "strings won't be kept on future QEMU versions"); 5816 } 5817 } 5818 5819 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5820 5821 /* Build a list with the name of all features on a feature word array */ 5822 static void x86_cpu_list_feature_names(FeatureWordArray features, 5823 strList **list) 5824 { 5825 strList **tail = list; 5826 FeatureWord w; 5827 5828 for (w = 0; w < FEATURE_WORDS; w++) { 5829 uint64_t filtered = features[w]; 5830 int i; 5831 for (i = 0; i < 64; i++) { 5832 if (filtered & (1ULL << i)) { 5833 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5834 } 5835 } 5836 } 5837 } 5838 5839 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5840 const char *name, void *opaque, 5841 Error **errp) 5842 { 5843 X86CPU *xc = X86_CPU(obj); 5844 strList *result = NULL; 5845 5846 x86_cpu_list_feature_names(xc->filtered_features, &result); 5847 visit_type_strList(v, "unavailable-features", &result, errp); 5848 } 5849 5850 /* Print all cpuid feature names in featureset 5851 */ 5852 static void listflags(GList *features) 5853 { 5854 size_t len = 0; 5855 GList *tmp; 5856 5857 for (tmp = features; tmp; tmp = tmp->next) { 5858 const char *name = tmp->data; 5859 if ((len + strlen(name) + 1) >= 75) { 5860 qemu_printf("\n"); 5861 len = 0; 5862 } 5863 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5864 len += strlen(name) + 1; 5865 } 5866 qemu_printf("\n"); 5867 } 5868 5869 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5870 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5871 { 5872 ObjectClass *class_a = (ObjectClass *)a; 5873 ObjectClass *class_b = (ObjectClass *)b; 5874 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5875 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5876 int ret; 5877 5878 if (cc_a->ordering != cc_b->ordering) { 5879 ret = cc_a->ordering - cc_b->ordering; 5880 } else { 5881 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5882 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5883 ret = strcmp(name_a, name_b); 5884 } 5885 return ret; 5886 } 5887 5888 static GSList *get_sorted_cpu_model_list(void) 5889 { 5890 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5891 list = g_slist_sort(list, x86_cpu_list_compare); 5892 return list; 5893 } 5894 5895 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5896 { 5897 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5898 char *r = object_property_get_str(obj, "model-id", &error_abort); 5899 object_unref(obj); 5900 return r; 5901 } 5902 5903 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5904 { 5905 X86CPUVersion version; 5906 5907 if (!cc->model || !cc->model->is_alias) { 5908 return NULL; 5909 } 5910 version = x86_cpu_model_resolve_version(cc->model); 5911 if (version <= 0) { 5912 return NULL; 5913 } 5914 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5915 } 5916 5917 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5918 { 5919 ObjectClass *oc = data; 5920 X86CPUClass *cc = X86_CPU_CLASS(oc); 5921 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5922 g_autofree char *desc = g_strdup(cc->model_description); 5923 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5924 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5925 5926 if (!desc && alias_of) { 5927 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5928 desc = g_strdup("(alias configured by machine type)"); 5929 } else { 5930 desc = g_strdup_printf("(alias of %s)", alias_of); 5931 } 5932 } 5933 if (!desc && cc->model && cc->model->note) { 5934 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5935 } 5936 if (!desc) { 5937 desc = g_strdup_printf("%s", model_id); 5938 } 5939 5940 if (cc->model && cc->model->cpudef->deprecation_note) { 5941 g_autofree char *olddesc = desc; 5942 desc = g_strdup_printf("%s (deprecated)", olddesc); 5943 } 5944 5945 qemu_printf(" %-20s %s\n", name, desc); 5946 } 5947 5948 /* list available CPU models and flags */ 5949 void x86_cpu_list(void) 5950 { 5951 int i, j; 5952 GSList *list; 5953 GList *names = NULL; 5954 5955 qemu_printf("Available CPUs:\n"); 5956 list = get_sorted_cpu_model_list(); 5957 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5958 g_slist_free(list); 5959 5960 names = NULL; 5961 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5962 FeatureWordInfo *fw = &feature_word_info[i]; 5963 for (j = 0; j < 64; j++) { 5964 if (fw->feat_names[j]) { 5965 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5966 } 5967 } 5968 } 5969 5970 names = g_list_sort(names, (GCompareFunc)strcmp); 5971 5972 qemu_printf("\nRecognized CPUID flags:\n"); 5973 listflags(names); 5974 qemu_printf("\n"); 5975 g_list_free(names); 5976 } 5977 5978 #ifndef CONFIG_USER_ONLY 5979 5980 /* Check for missing features that may prevent the CPU class from 5981 * running using the current machine and accelerator. 5982 */ 5983 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5984 strList **list) 5985 { 5986 strList **tail = list; 5987 X86CPU *xc; 5988 Error *err = NULL; 5989 5990 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5991 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5992 return; 5993 } 5994 5995 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5996 5997 x86_cpu_expand_features(xc, &err); 5998 if (err) { 5999 /* Errors at x86_cpu_expand_features should never happen, 6000 * but in case it does, just report the model as not 6001 * runnable at all using the "type" property. 6002 */ 6003 QAPI_LIST_APPEND(tail, g_strdup("type")); 6004 error_free(err); 6005 } 6006 6007 x86_cpu_filter_features(xc, false); 6008 6009 x86_cpu_list_feature_names(xc->filtered_features, tail); 6010 6011 object_unref(OBJECT(xc)); 6012 } 6013 6014 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6015 { 6016 ObjectClass *oc = data; 6017 X86CPUClass *cc = X86_CPU_CLASS(oc); 6018 CpuDefinitionInfoList **cpu_list = user_data; 6019 CpuDefinitionInfo *info; 6020 6021 info = g_malloc0(sizeof(*info)); 6022 info->name = x86_cpu_class_get_model_name(cc); 6023 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6024 info->has_unavailable_features = true; 6025 info->q_typename = g_strdup(object_class_get_name(oc)); 6026 info->migration_safe = cc->migration_safe; 6027 info->has_migration_safe = true; 6028 info->q_static = cc->static_model; 6029 if (cc->model && cc->model->cpudef->deprecation_note) { 6030 info->deprecated = true; 6031 } else { 6032 info->deprecated = false; 6033 } 6034 /* 6035 * Old machine types won't report aliases, so that alias translation 6036 * doesn't break compatibility with previous QEMU versions. 6037 */ 6038 if (default_cpu_version != CPU_VERSION_LEGACY) { 6039 info->alias_of = x86_cpu_class_get_alias_of(cc); 6040 } 6041 6042 QAPI_LIST_PREPEND(*cpu_list, info); 6043 } 6044 6045 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6046 { 6047 CpuDefinitionInfoList *cpu_list = NULL; 6048 GSList *list = get_sorted_cpu_model_list(); 6049 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6050 g_slist_free(list); 6051 return cpu_list; 6052 } 6053 6054 #endif /* !CONFIG_USER_ONLY */ 6055 6056 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6057 { 6058 FeatureWordInfo *wi = &feature_word_info[w]; 6059 uint64_t r = 0; 6060 uint64_t unavail = 0; 6061 6062 if (kvm_enabled()) { 6063 switch (wi->type) { 6064 case CPUID_FEATURE_WORD: 6065 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6066 wi->cpuid.ecx, 6067 wi->cpuid.reg); 6068 break; 6069 case MSR_FEATURE_WORD: 6070 r = kvm_arch_get_supported_msr_feature(kvm_state, 6071 wi->msr.index); 6072 break; 6073 } 6074 } else if (hvf_enabled()) { 6075 if (wi->type != CPUID_FEATURE_WORD) { 6076 return 0; 6077 } 6078 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6079 wi->cpuid.ecx, 6080 wi->cpuid.reg); 6081 } else if (tcg_enabled()) { 6082 r = wi->tcg_features; 6083 } else { 6084 return ~0; 6085 } 6086 6087 switch (w) { 6088 #ifndef TARGET_X86_64 6089 case FEAT_8000_0001_EDX: 6090 /* 6091 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6092 * way for userspace to get out of its 32-bit jail, we can leave 6093 * the LM bit set. 6094 */ 6095 unavail = tcg_enabled() 6096 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6097 : CPUID_EXT2_LM; 6098 break; 6099 #endif 6100 6101 case FEAT_8000_0007_EBX: 6102 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6103 /* Disable AMD machine check architecture for Intel CPU. */ 6104 unavail = ~0; 6105 } 6106 break; 6107 6108 case FEAT_7_0_EBX: 6109 #ifndef CONFIG_USER_ONLY 6110 if (!check_sgx_support()) { 6111 unavail = CPUID_7_0_EBX_SGX; 6112 } 6113 #endif 6114 break; 6115 case FEAT_7_0_ECX: 6116 #ifndef CONFIG_USER_ONLY 6117 if (!check_sgx_support()) { 6118 unavail = CPUID_7_0_ECX_SGX_LC; 6119 } 6120 #endif 6121 break; 6122 6123 default: 6124 break; 6125 } 6126 6127 r &= ~unavail; 6128 if (cpu && cpu->migratable) { 6129 r &= x86_cpu_get_migratable_flags(cpu, w); 6130 } 6131 return r; 6132 } 6133 6134 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6135 uint32_t *eax, uint32_t *ebx, 6136 uint32_t *ecx, uint32_t *edx) 6137 { 6138 if (kvm_enabled()) { 6139 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6140 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6141 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6142 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6143 } else if (hvf_enabled()) { 6144 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6145 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6146 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6147 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6148 } else { 6149 *eax = 0; 6150 *ebx = 0; 6151 *ecx = 0; 6152 *edx = 0; 6153 } 6154 } 6155 6156 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6157 uint32_t *eax, uint32_t *ebx, 6158 uint32_t *ecx, uint32_t *edx) 6159 { 6160 uint32_t level, unused; 6161 6162 /* Only return valid host leaves. */ 6163 switch (func) { 6164 case 2: 6165 case 4: 6166 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6167 break; 6168 case 0x80000005: 6169 case 0x80000006: 6170 case 0x8000001d: 6171 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6172 break; 6173 default: 6174 return; 6175 } 6176 6177 if (func > level) { 6178 *eax = 0; 6179 *ebx = 0; 6180 *ecx = 0; 6181 *edx = 0; 6182 } else { 6183 host_cpuid(func, index, eax, ebx, ecx, edx); 6184 } 6185 } 6186 6187 /* 6188 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6189 */ 6190 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6191 { 6192 PropValue *pv; 6193 for (pv = props; pv->prop; pv++) { 6194 if (!pv->value) { 6195 continue; 6196 } 6197 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6198 &error_abort); 6199 } 6200 } 6201 6202 /* 6203 * Apply properties for the CPU model version specified in model. 6204 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6205 */ 6206 6207 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6208 { 6209 const X86CPUVersionDefinition *vdef; 6210 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6211 6212 if (version == CPU_VERSION_LEGACY) { 6213 return; 6214 } 6215 6216 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6217 PropValue *p; 6218 6219 for (p = vdef->props; p && p->prop; p++) { 6220 object_property_parse(OBJECT(cpu), p->prop, p->value, 6221 &error_abort); 6222 } 6223 6224 if (vdef->version == version) { 6225 break; 6226 } 6227 } 6228 6229 /* 6230 * If we reached the end of the list, version number was invalid 6231 */ 6232 assert(vdef->version == version); 6233 } 6234 6235 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6236 X86CPUModel *model) 6237 { 6238 const X86CPUVersionDefinition *vdef; 6239 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6240 const CPUCaches *cache_info = model->cpudef->cache_info; 6241 6242 if (version == CPU_VERSION_LEGACY) { 6243 return cache_info; 6244 } 6245 6246 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6247 if (vdef->cache_info) { 6248 cache_info = vdef->cache_info; 6249 } 6250 6251 if (vdef->version == version) { 6252 break; 6253 } 6254 } 6255 6256 assert(vdef->version == version); 6257 return cache_info; 6258 } 6259 6260 /* 6261 * Load data from X86CPUDefinition into a X86CPU object. 6262 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6263 */ 6264 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6265 { 6266 const X86CPUDefinition *def = model->cpudef; 6267 CPUX86State *env = &cpu->env; 6268 FeatureWord w; 6269 6270 /*NOTE: any property set by this function should be returned by 6271 * x86_cpu_static_props(), so static expansion of 6272 * query-cpu-model-expansion is always complete. 6273 */ 6274 6275 /* CPU models only set _minimum_ values for level/xlevel: */ 6276 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6277 &error_abort); 6278 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6279 &error_abort); 6280 6281 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6282 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6283 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6284 &error_abort); 6285 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6286 &error_abort); 6287 for (w = 0; w < FEATURE_WORDS; w++) { 6288 env->features[w] = def->features[w]; 6289 } 6290 6291 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6292 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6293 6294 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6295 6296 /* sysenter isn't supported in compatibility mode on AMD, 6297 * syscall isn't supported in compatibility mode on Intel. 6298 * Normally we advertise the actual CPU vendor, but you can 6299 * override this using the 'vendor' property if you want to use 6300 * KVM's sysenter/syscall emulation in compatibility mode and 6301 * when doing cross vendor migration 6302 */ 6303 6304 /* 6305 * vendor property is set here but then overloaded with the 6306 * host cpu vendor for KVM and HVF. 6307 */ 6308 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6309 6310 x86_cpu_apply_version_props(cpu, model); 6311 6312 /* 6313 * Properties in versioned CPU model are not user specified features. 6314 * We can simply clear env->user_features here since it will be filled later 6315 * in x86_cpu_expand_features() based on plus_features and minus_features. 6316 */ 6317 memset(&env->user_features, 0, sizeof(env->user_features)); 6318 } 6319 6320 static const gchar *x86_gdb_arch_name(CPUState *cs) 6321 { 6322 #ifdef TARGET_X86_64 6323 return "i386:x86-64"; 6324 #else 6325 return "i386"; 6326 #endif 6327 } 6328 6329 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6330 { 6331 X86CPUModel *model = data; 6332 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6333 CPUClass *cc = CPU_CLASS(oc); 6334 6335 xcc->model = model; 6336 xcc->migration_safe = true; 6337 cc->deprecation_note = model->cpudef->deprecation_note; 6338 } 6339 6340 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6341 { 6342 g_autofree char *typename = x86_cpu_type_name(name); 6343 TypeInfo ti = { 6344 .name = typename, 6345 .parent = TYPE_X86_CPU, 6346 .class_init = x86_cpu_cpudef_class_init, 6347 .class_data = model, 6348 }; 6349 6350 type_register(&ti); 6351 } 6352 6353 6354 /* 6355 * register builtin_x86_defs; 6356 * "max", "base" and subclasses ("host") are not registered here. 6357 * See x86_cpu_register_types for all model registrations. 6358 */ 6359 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6360 { 6361 X86CPUModel *m; 6362 const X86CPUVersionDefinition *vdef; 6363 6364 /* AMD aliases are handled at runtime based on CPUID vendor, so 6365 * they shouldn't be set on the CPU model table. 6366 */ 6367 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6368 /* catch mistakes instead of silently truncating model_id when too long */ 6369 assert(def->model_id && strlen(def->model_id) <= 48); 6370 6371 /* Unversioned model: */ 6372 m = g_new0(X86CPUModel, 1); 6373 m->cpudef = def; 6374 m->version = CPU_VERSION_AUTO; 6375 m->is_alias = true; 6376 x86_register_cpu_model_type(def->name, m); 6377 6378 /* Versioned models: */ 6379 6380 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6381 g_autofree char *name = 6382 x86_cpu_versioned_model_name(def, vdef->version); 6383 6384 m = g_new0(X86CPUModel, 1); 6385 m->cpudef = def; 6386 m->version = vdef->version; 6387 m->note = vdef->note; 6388 x86_register_cpu_model_type(name, m); 6389 6390 if (vdef->alias) { 6391 X86CPUModel *am = g_new0(X86CPUModel, 1); 6392 am->cpudef = def; 6393 am->version = vdef->version; 6394 am->is_alias = true; 6395 x86_register_cpu_model_type(vdef->alias, am); 6396 } 6397 } 6398 6399 } 6400 6401 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6402 { 6403 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6404 return 57; /* 57 bits virtual */ 6405 } else { 6406 return 48; /* 48 bits virtual */ 6407 } 6408 } 6409 6410 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6411 uint32_t *eax, uint32_t *ebx, 6412 uint32_t *ecx, uint32_t *edx) 6413 { 6414 X86CPU *cpu = env_archcpu(env); 6415 CPUState *cs = env_cpu(env); 6416 uint32_t limit; 6417 uint32_t signature[3]; 6418 X86CPUTopoInfo topo_info; 6419 uint32_t cores_per_pkg; 6420 uint32_t threads_per_pkg; 6421 6422 topo_info.dies_per_pkg = env->nr_dies; 6423 topo_info.modules_per_die = env->nr_modules; 6424 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6425 topo_info.threads_per_core = cs->nr_threads; 6426 6427 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6428 topo_info.dies_per_pkg; 6429 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6430 6431 /* Calculate & apply limits for different index ranges */ 6432 if (index >= 0xC0000000) { 6433 limit = env->cpuid_xlevel2; 6434 } else if (index >= 0x80000000) { 6435 limit = env->cpuid_xlevel; 6436 } else if (index >= 0x40000000) { 6437 limit = 0x40000001; 6438 } else { 6439 limit = env->cpuid_level; 6440 } 6441 6442 if (index > limit) { 6443 /* Intel documentation states that invalid EAX input will 6444 * return the same information as EAX=cpuid_level 6445 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6446 */ 6447 index = env->cpuid_level; 6448 } 6449 6450 switch(index) { 6451 case 0: 6452 *eax = env->cpuid_level; 6453 *ebx = env->cpuid_vendor1; 6454 *edx = env->cpuid_vendor2; 6455 *ecx = env->cpuid_vendor3; 6456 break; 6457 case 1: 6458 *eax = env->cpuid_version; 6459 *ebx = (cpu->apic_id << 24) | 6460 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6461 *ecx = env->features[FEAT_1_ECX]; 6462 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6463 *ecx |= CPUID_EXT_OSXSAVE; 6464 } 6465 *edx = env->features[FEAT_1_EDX]; 6466 if (threads_per_pkg > 1) { 6467 *ebx |= threads_per_pkg << 16; 6468 *edx |= CPUID_HT; 6469 } 6470 if (!cpu->enable_pmu) { 6471 *ecx &= ~CPUID_EXT_PDCM; 6472 } 6473 break; 6474 case 2: 6475 /* cache info: needed for Pentium Pro compatibility */ 6476 if (cpu->cache_info_passthrough) { 6477 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6478 break; 6479 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6480 *eax = *ebx = *ecx = *edx = 0; 6481 break; 6482 } 6483 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6484 *ebx = 0; 6485 if (!cpu->enable_l3_cache) { 6486 *ecx = 0; 6487 } else { 6488 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6489 } 6490 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6491 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6492 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6493 break; 6494 case 4: 6495 /* cache info: needed for Core compatibility */ 6496 if (cpu->cache_info_passthrough) { 6497 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6498 /* 6499 * QEMU has its own number of cores/logical cpus, 6500 * set 24..14, 31..26 bit to configured values 6501 */ 6502 if (*eax & 31) { 6503 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6504 6505 *eax &= ~0xFC000000; 6506 *eax |= max_core_ids_in_package(&topo_info) << 26; 6507 if (host_vcpus_per_cache > threads_per_pkg) { 6508 *eax &= ~0x3FFC000; 6509 6510 /* Share the cache at package level. */ 6511 *eax |= max_thread_ids_for_cache(&topo_info, 6512 CPU_TOPO_LEVEL_PACKAGE) << 14; 6513 } 6514 } 6515 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6516 *eax = *ebx = *ecx = *edx = 0; 6517 } else { 6518 *eax = 0; 6519 6520 switch (count) { 6521 case 0: /* L1 dcache info */ 6522 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6523 &topo_info, 6524 eax, ebx, ecx, edx); 6525 if (!cpu->l1_cache_per_core) { 6526 *eax &= ~MAKE_64BIT_MASK(14, 12); 6527 } 6528 break; 6529 case 1: /* L1 icache info */ 6530 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6531 &topo_info, 6532 eax, ebx, ecx, edx); 6533 if (!cpu->l1_cache_per_core) { 6534 *eax &= ~MAKE_64BIT_MASK(14, 12); 6535 } 6536 break; 6537 case 2: /* L2 cache info */ 6538 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6539 &topo_info, 6540 eax, ebx, ecx, edx); 6541 break; 6542 case 3: /* L3 cache info */ 6543 if (cpu->enable_l3_cache) { 6544 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6545 &topo_info, 6546 eax, ebx, ecx, edx); 6547 break; 6548 } 6549 /* fall through */ 6550 default: /* end of info */ 6551 *eax = *ebx = *ecx = *edx = 0; 6552 break; 6553 } 6554 } 6555 break; 6556 case 5: 6557 /* MONITOR/MWAIT Leaf */ 6558 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6559 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6560 *ecx = cpu->mwait.ecx; /* flags */ 6561 *edx = cpu->mwait.edx; /* mwait substates */ 6562 break; 6563 case 6: 6564 /* Thermal and Power Leaf */ 6565 *eax = env->features[FEAT_6_EAX]; 6566 *ebx = 0; 6567 *ecx = 0; 6568 *edx = 0; 6569 break; 6570 case 7: 6571 /* Structured Extended Feature Flags Enumeration Leaf */ 6572 if (count == 0) { 6573 /* Maximum ECX value for sub-leaves */ 6574 *eax = env->cpuid_level_func7; 6575 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6576 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6577 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6578 *ecx |= CPUID_7_0_ECX_OSPKE; 6579 } 6580 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6581 } else if (count == 1) { 6582 *eax = env->features[FEAT_7_1_EAX]; 6583 *edx = env->features[FEAT_7_1_EDX]; 6584 *ebx = 0; 6585 *ecx = 0; 6586 } else if (count == 2) { 6587 *edx = env->features[FEAT_7_2_EDX]; 6588 *eax = 0; 6589 *ebx = 0; 6590 *ecx = 0; 6591 } else { 6592 *eax = 0; 6593 *ebx = 0; 6594 *ecx = 0; 6595 *edx = 0; 6596 } 6597 break; 6598 case 9: 6599 /* Direct Cache Access Information Leaf */ 6600 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6601 *ebx = 0; 6602 *ecx = 0; 6603 *edx = 0; 6604 break; 6605 case 0xA: 6606 /* Architectural Performance Monitoring Leaf */ 6607 if (cpu->enable_pmu) { 6608 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6609 } else { 6610 *eax = 0; 6611 *ebx = 0; 6612 *ecx = 0; 6613 *edx = 0; 6614 } 6615 break; 6616 case 0xB: 6617 /* Extended Topology Enumeration Leaf */ 6618 if (!cpu->enable_cpuid_0xb) { 6619 *eax = *ebx = *ecx = *edx = 0; 6620 break; 6621 } 6622 6623 *ecx = count & 0xff; 6624 *edx = cpu->apic_id; 6625 6626 switch (count) { 6627 case 0: 6628 *eax = apicid_core_offset(&topo_info); 6629 *ebx = topo_info.threads_per_core; 6630 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6631 break; 6632 case 1: 6633 *eax = apicid_pkg_offset(&topo_info); 6634 *ebx = threads_per_pkg; 6635 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6636 break; 6637 default: 6638 *eax = 0; 6639 *ebx = 0; 6640 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6641 } 6642 6643 assert(!(*eax & ~0x1f)); 6644 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6645 break; 6646 case 0x1C: 6647 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6648 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6649 *edx = 0; 6650 } 6651 break; 6652 case 0x1F: 6653 /* V2 Extended Topology Enumeration Leaf */ 6654 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6655 *eax = *ebx = *ecx = *edx = 0; 6656 break; 6657 } 6658 6659 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6660 break; 6661 case 0xD: { 6662 /* Processor Extended State */ 6663 *eax = 0; 6664 *ebx = 0; 6665 *ecx = 0; 6666 *edx = 0; 6667 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6668 break; 6669 } 6670 6671 if (count == 0) { 6672 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6673 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6674 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6675 /* 6676 * The initial value of xcr0 and ebx == 0, On host without kvm 6677 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6678 * even through guest update xcr0, this will crash some legacy guest 6679 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6680 */ 6681 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6682 } else if (count == 1) { 6683 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6684 x86_cpu_xsave_xss_components(cpu); 6685 6686 *eax = env->features[FEAT_XSAVE]; 6687 *ebx = xsave_area_size(xstate, true); 6688 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6689 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6690 if (kvm_enabled() && cpu->enable_pmu && 6691 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6692 (*eax & CPUID_XSAVE_XSAVES)) { 6693 *ecx |= XSTATE_ARCH_LBR_MASK; 6694 } else { 6695 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6696 } 6697 } else if (count == 0xf && cpu->enable_pmu 6698 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6699 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6700 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6701 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6702 6703 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6704 *eax = esa->size; 6705 *ebx = esa->offset; 6706 *ecx = esa->ecx & 6707 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6708 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6709 *eax = esa->size; 6710 *ebx = 0; 6711 *ecx = 1; 6712 } 6713 } 6714 break; 6715 } 6716 case 0x12: 6717 #ifndef CONFIG_USER_ONLY 6718 if (!kvm_enabled() || 6719 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6720 *eax = *ebx = *ecx = *edx = 0; 6721 break; 6722 } 6723 6724 /* 6725 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6726 * the EPC properties, e.g. confidentiality and integrity, from the 6727 * host's first EPC section, i.e. assume there is one EPC section or 6728 * that all EPC sections have the same security properties. 6729 */ 6730 if (count > 1) { 6731 uint64_t epc_addr, epc_size; 6732 6733 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6734 *eax = *ebx = *ecx = *edx = 0; 6735 break; 6736 } 6737 host_cpuid(index, 2, eax, ebx, ecx, edx); 6738 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6739 *ebx = (uint32_t)(epc_addr >> 32); 6740 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6741 *edx = (uint32_t)(epc_size >> 32); 6742 break; 6743 } 6744 6745 /* 6746 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6747 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6748 * supports. Features can be further restricted by userspace, but not 6749 * made more permissive. 6750 */ 6751 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6752 6753 if (count == 0) { 6754 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6755 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6756 } else { 6757 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6758 *ebx &= 0; /* ebx reserve */ 6759 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6760 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6761 6762 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6763 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6764 6765 /* Access to PROVISIONKEY requires additional credentials. */ 6766 if ((*eax & (1U << 4)) && 6767 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6768 *eax &= ~(1U << 4); 6769 } 6770 } 6771 #endif 6772 break; 6773 case 0x14: { 6774 /* Intel Processor Trace Enumeration */ 6775 *eax = 0; 6776 *ebx = 0; 6777 *ecx = 0; 6778 *edx = 0; 6779 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6780 !kvm_enabled()) { 6781 break; 6782 } 6783 6784 /* 6785 * If these are changed, they should stay in sync with 6786 * x86_cpu_filter_features(). 6787 */ 6788 if (count == 0) { 6789 *eax = INTEL_PT_MAX_SUBLEAF; 6790 *ebx = INTEL_PT_MINIMAL_EBX; 6791 *ecx = INTEL_PT_MINIMAL_ECX; 6792 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6793 *ecx |= CPUID_14_0_ECX_LIP; 6794 } 6795 } else if (count == 1) { 6796 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6797 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6798 } 6799 break; 6800 } 6801 case 0x1D: { 6802 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6803 *eax = 0; 6804 *ebx = 0; 6805 *ecx = 0; 6806 *edx = 0; 6807 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6808 break; 6809 } 6810 6811 if (count == 0) { 6812 /* Highest numbered palette subleaf */ 6813 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6814 } else if (count == 1) { 6815 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6816 (INTEL_AMX_BYTES_PER_TILE << 16); 6817 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6818 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6819 } 6820 break; 6821 } 6822 case 0x1E: { 6823 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6824 *eax = 0; 6825 *ebx = 0; 6826 *ecx = 0; 6827 *edx = 0; 6828 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6829 break; 6830 } 6831 6832 if (count == 0) { 6833 /* Highest numbered palette subleaf */ 6834 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6835 } 6836 break; 6837 } 6838 case 0x40000000: 6839 /* 6840 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6841 * set here, but we restrict to TCG none the less. 6842 */ 6843 if (tcg_enabled() && cpu->expose_tcg) { 6844 memcpy(signature, "TCGTCGTCGTCG", 12); 6845 *eax = 0x40000001; 6846 *ebx = signature[0]; 6847 *ecx = signature[1]; 6848 *edx = signature[2]; 6849 } else { 6850 *eax = 0; 6851 *ebx = 0; 6852 *ecx = 0; 6853 *edx = 0; 6854 } 6855 break; 6856 case 0x40000001: 6857 *eax = 0; 6858 *ebx = 0; 6859 *ecx = 0; 6860 *edx = 0; 6861 break; 6862 case 0x80000000: 6863 *eax = env->cpuid_xlevel; 6864 *ebx = env->cpuid_vendor1; 6865 *edx = env->cpuid_vendor2; 6866 *ecx = env->cpuid_vendor3; 6867 break; 6868 case 0x80000001: 6869 *eax = env->cpuid_version; 6870 *ebx = 0; 6871 *ecx = env->features[FEAT_8000_0001_ECX]; 6872 *edx = env->features[FEAT_8000_0001_EDX]; 6873 6874 /* The Linux kernel checks for the CMPLegacy bit and 6875 * discards multiple thread information if it is set. 6876 * So don't set it here for Intel to make Linux guests happy. 6877 */ 6878 if (threads_per_pkg > 1) { 6879 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6880 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6881 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6882 *ecx |= 1 << 1; /* CmpLegacy bit */ 6883 } 6884 } 6885 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6886 !(env->hflags & HF_LMA_MASK)) { 6887 *edx &= ~CPUID_EXT2_SYSCALL; 6888 } 6889 break; 6890 case 0x80000002: 6891 case 0x80000003: 6892 case 0x80000004: 6893 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6894 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6895 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6896 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6897 break; 6898 case 0x80000005: 6899 /* cache info (L1 cache) */ 6900 if (cpu->cache_info_passthrough) { 6901 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6902 break; 6903 } 6904 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6905 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6906 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6907 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6908 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6909 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6910 break; 6911 case 0x80000006: 6912 /* cache info (L2 cache) */ 6913 if (cpu->cache_info_passthrough) { 6914 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6915 break; 6916 } 6917 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6918 (L2_DTLB_2M_ENTRIES << 16) | 6919 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6920 (L2_ITLB_2M_ENTRIES); 6921 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6922 (L2_DTLB_4K_ENTRIES << 16) | 6923 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6924 (L2_ITLB_4K_ENTRIES); 6925 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6926 cpu->enable_l3_cache ? 6927 env->cache_info_amd.l3_cache : NULL, 6928 ecx, edx); 6929 break; 6930 case 0x80000007: 6931 *eax = 0; 6932 *ebx = env->features[FEAT_8000_0007_EBX]; 6933 *ecx = 0; 6934 *edx = env->features[FEAT_8000_0007_EDX]; 6935 break; 6936 case 0x80000008: 6937 /* virtual & phys address size in low 2 bytes. */ 6938 *eax = cpu->phys_bits; 6939 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6940 /* 64 bit processor */ 6941 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6942 *eax |= (cpu->guest_phys_bits << 16); 6943 } 6944 *ebx = env->features[FEAT_8000_0008_EBX]; 6945 if (threads_per_pkg > 1) { 6946 /* 6947 * Bits 15:12 is "The number of bits in the initial 6948 * Core::X86::Apic::ApicId[ApicId] value that indicate 6949 * thread ID within a package". 6950 * Bits 7:0 is "The number of threads in the package is NC+1" 6951 */ 6952 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6953 (threads_per_pkg - 1); 6954 } else { 6955 *ecx = 0; 6956 } 6957 *edx = 0; 6958 break; 6959 case 0x8000000A: 6960 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6961 *eax = 0x00000001; /* SVM Revision */ 6962 *ebx = 0x00000010; /* nr of ASIDs */ 6963 *ecx = 0; 6964 *edx = env->features[FEAT_SVM]; /* optional features */ 6965 } else { 6966 *eax = 0; 6967 *ebx = 0; 6968 *ecx = 0; 6969 *edx = 0; 6970 } 6971 break; 6972 case 0x8000001D: 6973 *eax = 0; 6974 if (cpu->cache_info_passthrough) { 6975 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6976 break; 6977 } 6978 switch (count) { 6979 case 0: /* L1 dcache info */ 6980 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6981 &topo_info, eax, ebx, ecx, edx); 6982 break; 6983 case 1: /* L1 icache info */ 6984 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6985 &topo_info, eax, ebx, ecx, edx); 6986 break; 6987 case 2: /* L2 cache info */ 6988 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6989 &topo_info, eax, ebx, ecx, edx); 6990 break; 6991 case 3: /* L3 cache info */ 6992 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6993 &topo_info, eax, ebx, ecx, edx); 6994 break; 6995 default: /* end of info */ 6996 *eax = *ebx = *ecx = *edx = 0; 6997 break; 6998 } 6999 if (cpu->amd_topoext_features_only) { 7000 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7001 } 7002 break; 7003 case 0x8000001E: 7004 if (cpu->core_id <= 255) { 7005 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 7006 } else { 7007 *eax = 0; 7008 *ebx = 0; 7009 *ecx = 0; 7010 *edx = 0; 7011 } 7012 break; 7013 case 0xC0000000: 7014 *eax = env->cpuid_xlevel2; 7015 *ebx = 0; 7016 *ecx = 0; 7017 *edx = 0; 7018 break; 7019 case 0xC0000001: 7020 /* Support for VIA CPU's CPUID instruction */ 7021 *eax = env->cpuid_version; 7022 *ebx = 0; 7023 *ecx = 0; 7024 *edx = env->features[FEAT_C000_0001_EDX]; 7025 break; 7026 case 0xC0000002: 7027 case 0xC0000003: 7028 case 0xC0000004: 7029 /* Reserved for the future, and now filled with zero */ 7030 *eax = 0; 7031 *ebx = 0; 7032 *ecx = 0; 7033 *edx = 0; 7034 break; 7035 case 0x8000001F: 7036 *eax = *ebx = *ecx = *edx = 0; 7037 if (sev_enabled()) { 7038 *eax = 0x2; 7039 *eax |= sev_es_enabled() ? 0x8 : 0; 7040 *eax |= sev_snp_enabled() ? 0x10 : 0; 7041 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7042 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7043 } 7044 break; 7045 case 0x80000021: 7046 *eax = env->features[FEAT_8000_0021_EAX]; 7047 *ebx = *ecx = *edx = 0; 7048 break; 7049 default: 7050 /* reserved values: zero */ 7051 *eax = 0; 7052 *ebx = 0; 7053 *ecx = 0; 7054 *edx = 0; 7055 break; 7056 } 7057 } 7058 7059 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7060 { 7061 #ifndef CONFIG_USER_ONLY 7062 /* Those default values are defined in Skylake HW */ 7063 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7064 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7065 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7066 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7067 #endif 7068 } 7069 7070 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7071 { 7072 CPUState *cs = CPU(obj); 7073 X86CPU *cpu = X86_CPU(cs); 7074 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7075 CPUX86State *env = &cpu->env; 7076 target_ulong cr4; 7077 uint64_t xcr0; 7078 int i; 7079 7080 if (xcc->parent_phases.hold) { 7081 xcc->parent_phases.hold(obj, type); 7082 } 7083 7084 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7085 7086 env->old_exception = -1; 7087 7088 /* init to reset state */ 7089 env->int_ctl = 0; 7090 env->hflags2 |= HF2_GIF_MASK; 7091 env->hflags2 |= HF2_VGIF_MASK; 7092 env->hflags &= ~HF_GUEST_MASK; 7093 7094 cpu_x86_update_cr0(env, 0x60000010); 7095 env->a20_mask = ~0x0; 7096 env->smbase = 0x30000; 7097 env->msr_smi_count = 0; 7098 7099 env->idt.limit = 0xffff; 7100 env->gdt.limit = 0xffff; 7101 env->ldt.limit = 0xffff; 7102 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7103 env->tr.limit = 0xffff; 7104 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7105 7106 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7107 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7108 DESC_R_MASK | DESC_A_MASK); 7109 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7110 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7111 DESC_A_MASK); 7112 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7113 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7114 DESC_A_MASK); 7115 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7116 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7117 DESC_A_MASK); 7118 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7119 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7120 DESC_A_MASK); 7121 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7122 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7123 DESC_A_MASK); 7124 7125 env->eip = 0xfff0; 7126 env->regs[R_EDX] = env->cpuid_version; 7127 7128 env->eflags = 0x2; 7129 7130 /* FPU init */ 7131 for (i = 0; i < 8; i++) { 7132 env->fptags[i] = 1; 7133 } 7134 cpu_set_fpuc(env, 0x37f); 7135 7136 env->mxcsr = 0x1f80; 7137 /* All units are in INIT state. */ 7138 env->xstate_bv = 0; 7139 7140 env->pat = 0x0007040600070406ULL; 7141 7142 if (kvm_enabled()) { 7143 /* 7144 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7145 * a new CPU, use 1 instead to force a reset. 7146 */ 7147 if (env->tsc != 0) { 7148 env->tsc = 1; 7149 } 7150 } else { 7151 env->tsc = 0; 7152 } 7153 7154 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7155 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7156 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7157 } 7158 7159 memset(env->dr, 0, sizeof(env->dr)); 7160 env->dr[6] = DR6_FIXED_1; 7161 env->dr[7] = DR7_FIXED_1; 7162 cpu_breakpoint_remove_all(cs, BP_CPU); 7163 cpu_watchpoint_remove_all(cs, BP_CPU); 7164 7165 cr4 = 0; 7166 xcr0 = XSTATE_FP_MASK; 7167 7168 #ifdef CONFIG_USER_ONLY 7169 /* Enable all the features for user-mode. */ 7170 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7171 xcr0 |= XSTATE_SSE_MASK; 7172 } 7173 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7174 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7175 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7176 continue; 7177 } 7178 if (env->features[esa->feature] & esa->bits) { 7179 xcr0 |= 1ull << i; 7180 } 7181 } 7182 7183 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7184 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7185 } 7186 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7187 cr4 |= CR4_FSGSBASE_MASK; 7188 } 7189 #endif 7190 7191 env->xcr0 = xcr0; 7192 cpu_x86_update_cr4(env, cr4); 7193 7194 /* 7195 * SDM 11.11.5 requires: 7196 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7197 * - IA32_MTRR_PHYSMASKn.V = 0 7198 * All other bits are undefined. For simplification, zero it all. 7199 */ 7200 env->mtrr_deftype = 0; 7201 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7202 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7203 7204 env->interrupt_injected = -1; 7205 env->exception_nr = -1; 7206 env->exception_pending = 0; 7207 env->exception_injected = 0; 7208 env->exception_has_payload = false; 7209 env->exception_payload = 0; 7210 env->nmi_injected = false; 7211 env->triple_fault_pending = false; 7212 #if !defined(CONFIG_USER_ONLY) 7213 /* We hard-wire the BSP to the first CPU. */ 7214 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7215 7216 cs->halted = !cpu_is_bsp(cpu); 7217 7218 if (kvm_enabled()) { 7219 kvm_arch_reset_vcpu(cpu); 7220 } 7221 7222 x86_cpu_set_sgxlepubkeyhash(env); 7223 7224 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7225 7226 #endif 7227 } 7228 7229 void x86_cpu_after_reset(X86CPU *cpu) 7230 { 7231 #ifndef CONFIG_USER_ONLY 7232 if (kvm_enabled()) { 7233 kvm_arch_after_reset_vcpu(cpu); 7234 } 7235 7236 if (cpu->apic_state) { 7237 device_cold_reset(cpu->apic_state); 7238 } 7239 #endif 7240 } 7241 7242 static void mce_init(X86CPU *cpu) 7243 { 7244 CPUX86State *cenv = &cpu->env; 7245 unsigned int bank; 7246 7247 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7248 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7249 (CPUID_MCE | CPUID_MCA)) { 7250 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7251 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7252 cenv->mcg_ctl = ~(uint64_t)0; 7253 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7254 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7255 } 7256 } 7257 } 7258 7259 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7260 { 7261 if (*min < value) { 7262 *min = value; 7263 } 7264 } 7265 7266 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7267 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7268 { 7269 CPUX86State *env = &cpu->env; 7270 FeatureWordInfo *fi = &feature_word_info[w]; 7271 uint32_t eax = fi->cpuid.eax; 7272 uint32_t region = eax & 0xF0000000; 7273 7274 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7275 if (!env->features[w]) { 7276 return; 7277 } 7278 7279 switch (region) { 7280 case 0x00000000: 7281 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7282 break; 7283 case 0x80000000: 7284 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7285 break; 7286 case 0xC0000000: 7287 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7288 break; 7289 } 7290 7291 if (eax == 7) { 7292 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7293 fi->cpuid.ecx); 7294 } 7295 } 7296 7297 /* Calculate XSAVE components based on the configured CPU feature flags */ 7298 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7299 { 7300 CPUX86State *env = &cpu->env; 7301 int i; 7302 uint64_t mask; 7303 static bool request_perm; 7304 7305 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7306 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7307 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7308 env->features[FEAT_XSAVE_XSS_LO] = 0; 7309 env->features[FEAT_XSAVE_XSS_HI] = 0; 7310 return; 7311 } 7312 7313 mask = 0; 7314 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7315 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7316 if (env->features[esa->feature] & esa->bits) { 7317 mask |= (1ULL << i); 7318 } 7319 } 7320 7321 /* Only request permission for first vcpu */ 7322 if (kvm_enabled() && !request_perm) { 7323 kvm_request_xsave_components(cpu, mask); 7324 request_perm = true; 7325 } 7326 7327 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7328 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7329 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7330 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7331 } 7332 7333 /***** Steps involved on loading and filtering CPUID data 7334 * 7335 * When initializing and realizing a CPU object, the steps 7336 * involved in setting up CPUID data are: 7337 * 7338 * 1) Loading CPU model definition (X86CPUDefinition). This is 7339 * implemented by x86_cpu_load_model() and should be completely 7340 * transparent, as it is done automatically by instance_init. 7341 * No code should need to look at X86CPUDefinition structs 7342 * outside instance_init. 7343 * 7344 * 2) CPU expansion. This is done by realize before CPUID 7345 * filtering, and will make sure host/accelerator data is 7346 * loaded for CPU models that depend on host capabilities 7347 * (e.g. "host"). Done by x86_cpu_expand_features(). 7348 * 7349 * 3) CPUID filtering. This initializes extra data related to 7350 * CPUID, and checks if the host supports all capabilities 7351 * required by the CPU. Runnability of a CPU model is 7352 * determined at this step. Done by x86_cpu_filter_features(). 7353 * 7354 * Some operations don't require all steps to be performed. 7355 * More precisely: 7356 * 7357 * - CPU instance creation (instance_init) will run only CPU 7358 * model loading. CPU expansion can't run at instance_init-time 7359 * because host/accelerator data may be not available yet. 7360 * - CPU realization will perform both CPU model expansion and CPUID 7361 * filtering, and return an error in case one of them fails. 7362 * - query-cpu-definitions needs to run all 3 steps. It needs 7363 * to run CPUID filtering, as the 'unavailable-features' 7364 * field is set based on the filtering results. 7365 * - The query-cpu-model-expansion QMP command only needs to run 7366 * CPU model loading and CPU expansion. It should not filter 7367 * any CPUID data based on host capabilities. 7368 */ 7369 7370 /* Expand CPU configuration data, based on configured features 7371 * and host/accelerator capabilities when appropriate. 7372 */ 7373 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7374 { 7375 CPUX86State *env = &cpu->env; 7376 FeatureWord w; 7377 int i; 7378 GList *l; 7379 7380 for (l = plus_features; l; l = l->next) { 7381 const char *prop = l->data; 7382 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7383 return; 7384 } 7385 } 7386 7387 for (l = minus_features; l; l = l->next) { 7388 const char *prop = l->data; 7389 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7390 return; 7391 } 7392 } 7393 7394 /*TODO: Now cpu->max_features doesn't overwrite features 7395 * set using QOM properties, and we can convert 7396 * plus_features & minus_features to global properties 7397 * inside x86_cpu_parse_featurestr() too. 7398 */ 7399 if (cpu->max_features) { 7400 for (w = 0; w < FEATURE_WORDS; w++) { 7401 /* Override only features that weren't set explicitly 7402 * by the user. 7403 */ 7404 env->features[w] |= 7405 x86_cpu_get_supported_feature_word(cpu, w) & 7406 ~env->user_features[w] & 7407 ~feature_word_info[w].no_autoenable_flags; 7408 } 7409 } 7410 7411 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7412 FeatureDep *d = &feature_dependencies[i]; 7413 if (!(env->features[d->from.index] & d->from.mask)) { 7414 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7415 7416 /* Not an error unless the dependent feature was added explicitly. */ 7417 mark_unavailable_features(cpu, d->to.index, 7418 unavailable_features & env->user_features[d->to.index], 7419 "This feature depends on other features that were not requested"); 7420 7421 env->features[d->to.index] &= ~unavailable_features; 7422 } 7423 } 7424 7425 if (!kvm_enabled() || !cpu->expose_kvm) { 7426 env->features[FEAT_KVM] = 0; 7427 } 7428 7429 x86_cpu_enable_xsave_components(cpu); 7430 7431 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7432 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7433 if (cpu->full_cpuid_auto_level) { 7434 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7435 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7436 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7437 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7438 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7439 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7440 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7441 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7442 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7443 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7444 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7445 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7446 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7447 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7448 7449 /* Intel Processor Trace requires CPUID[0x14] */ 7450 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7451 if (cpu->intel_pt_auto_level) { 7452 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7453 } else if (cpu->env.cpuid_min_level < 0x14) { 7454 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7455 CPUID_7_0_EBX_INTEL_PT, 7456 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7457 } 7458 } 7459 7460 /* 7461 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7462 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7463 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7464 * cpu->vendor_cpuid_only has been unset for compatibility with older 7465 * machine types. 7466 */ 7467 if (x86_has_extended_topo(env->avail_cpu_topo) && 7468 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7469 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7470 } 7471 7472 /* SVM requires CPUID[0x8000000A] */ 7473 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7474 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7475 } 7476 7477 /* SEV requires CPUID[0x8000001F] */ 7478 if (sev_enabled()) { 7479 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7480 } 7481 7482 if (env->features[FEAT_8000_0021_EAX]) { 7483 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7484 } 7485 7486 /* SGX requires CPUID[0x12] for EPC enumeration */ 7487 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7488 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7489 } 7490 } 7491 7492 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7493 if (env->cpuid_level_func7 == UINT32_MAX) { 7494 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7495 } 7496 if (env->cpuid_level == UINT32_MAX) { 7497 env->cpuid_level = env->cpuid_min_level; 7498 } 7499 if (env->cpuid_xlevel == UINT32_MAX) { 7500 env->cpuid_xlevel = env->cpuid_min_xlevel; 7501 } 7502 if (env->cpuid_xlevel2 == UINT32_MAX) { 7503 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7504 } 7505 7506 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7507 return; 7508 } 7509 } 7510 7511 /* 7512 * Finishes initialization of CPUID data, filters CPU feature 7513 * words based on host availability of each feature. 7514 * 7515 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7516 */ 7517 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7518 { 7519 CPUX86State *env = &cpu->env; 7520 FeatureWord w; 7521 const char *prefix = NULL; 7522 7523 if (verbose) { 7524 prefix = accel_uses_host_cpuid() 7525 ? "host doesn't support requested feature" 7526 : "TCG doesn't support requested feature"; 7527 } 7528 7529 for (w = 0; w < FEATURE_WORDS; w++) { 7530 uint64_t host_feat = 7531 x86_cpu_get_supported_feature_word(NULL, w); 7532 uint64_t requested_features = env->features[w]; 7533 uint64_t unavailable_features = requested_features & ~host_feat; 7534 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7535 } 7536 7537 /* 7538 * Check that KVM actually allows the processor tracing features that 7539 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7540 */ 7541 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7542 kvm_enabled()) { 7543 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7544 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7545 7546 x86_cpu_get_supported_cpuid(0x14, 0, 7547 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7548 x86_cpu_get_supported_cpuid(0x14, 1, 7549 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7550 7551 if (!eax_0 || 7552 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7553 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7554 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7555 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7556 INTEL_PT_ADDR_RANGES_NUM) || 7557 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7558 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7559 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7560 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7561 /* 7562 * Processor Trace capabilities aren't configurable, so if the 7563 * host can't emulate the capabilities we report on 7564 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7565 */ 7566 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7567 } 7568 } 7569 } 7570 7571 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7572 { 7573 size_t len; 7574 7575 /* Hyper-V vendor id */ 7576 if (!cpu->hyperv_vendor) { 7577 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7578 &error_abort); 7579 } 7580 len = strlen(cpu->hyperv_vendor); 7581 if (len > 12) { 7582 warn_report("hv-vendor-id truncated to 12 characters"); 7583 len = 12; 7584 } 7585 memset(cpu->hyperv_vendor_id, 0, 12); 7586 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7587 7588 /* 'Hv#1' interface identification*/ 7589 cpu->hyperv_interface_id[0] = 0x31237648; 7590 cpu->hyperv_interface_id[1] = 0; 7591 cpu->hyperv_interface_id[2] = 0; 7592 cpu->hyperv_interface_id[3] = 0; 7593 7594 /* Hypervisor implementation limits */ 7595 cpu->hyperv_limits[0] = 64; 7596 cpu->hyperv_limits[1] = 0; 7597 cpu->hyperv_limits[2] = 0; 7598 } 7599 7600 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7601 { 7602 CPUState *cs = CPU(dev); 7603 X86CPU *cpu = X86_CPU(dev); 7604 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7605 CPUX86State *env = &cpu->env; 7606 Error *local_err = NULL; 7607 unsigned requested_lbr_fmt; 7608 7609 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7610 /* Use pc-relative instructions in system-mode */ 7611 tcg_cflags_set(cs, CF_PCREL); 7612 #endif 7613 7614 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7615 error_setg(errp, "apic-id property was not initialized properly"); 7616 return; 7617 } 7618 7619 /* 7620 * Process Hyper-V enlightenments. 7621 * Note: this currently has to happen before the expansion of CPU features. 7622 */ 7623 x86_cpu_hyperv_realize(cpu); 7624 7625 x86_cpu_expand_features(cpu, &local_err); 7626 if (local_err) { 7627 goto out; 7628 } 7629 7630 /* 7631 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7632 * with user-provided setting. 7633 */ 7634 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7635 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7636 error_setg(errp, "invalid lbr-fmt"); 7637 return; 7638 } 7639 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7640 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7641 } 7642 7643 /* 7644 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7645 * 3)vPMU LBR format matches that of host setting. 7646 */ 7647 requested_lbr_fmt = 7648 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7649 if (requested_lbr_fmt && kvm_enabled()) { 7650 uint64_t host_perf_cap = 7651 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 7652 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7653 7654 if (!cpu->enable_pmu) { 7655 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7656 return; 7657 } 7658 if (requested_lbr_fmt != host_lbr_fmt) { 7659 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7660 "the host value (0x%x).", 7661 requested_lbr_fmt, host_lbr_fmt); 7662 return; 7663 } 7664 } 7665 7666 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7667 7668 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7669 error_setg(&local_err, 7670 accel_uses_host_cpuid() ? 7671 "Host doesn't support requested features" : 7672 "TCG doesn't support requested features"); 7673 goto out; 7674 } 7675 7676 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7677 * CPUID[1].EDX. 7678 */ 7679 if (IS_AMD_CPU(env)) { 7680 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7681 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7682 & CPUID_EXT2_AMD_ALIASES); 7683 } 7684 7685 x86_cpu_set_sgxlepubkeyhash(env); 7686 7687 /* 7688 * note: the call to the framework needs to happen after feature expansion, 7689 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7690 * These may be set by the accel-specific code, 7691 * and the results are subsequently checked / assumed in this function. 7692 */ 7693 cpu_exec_realizefn(cs, &local_err); 7694 if (local_err != NULL) { 7695 error_propagate(errp, local_err); 7696 return; 7697 } 7698 7699 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7700 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7701 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7702 goto out; 7703 } 7704 7705 if (cpu->guest_phys_bits == -1) { 7706 /* 7707 * If it was not set by the user, or by the accelerator via 7708 * cpu_exec_realizefn, clear. 7709 */ 7710 cpu->guest_phys_bits = 0; 7711 } 7712 7713 if (cpu->ucode_rev == 0) { 7714 /* 7715 * The default is the same as KVM's. Note that this check 7716 * needs to happen after the evenual setting of ucode_rev in 7717 * accel-specific code in cpu_exec_realizefn. 7718 */ 7719 if (IS_AMD_CPU(env)) { 7720 cpu->ucode_rev = 0x01000065; 7721 } else { 7722 cpu->ucode_rev = 0x100000000ULL; 7723 } 7724 } 7725 7726 /* 7727 * mwait extended info: needed for Core compatibility 7728 * We always wake on interrupt even if host does not have the capability. 7729 * 7730 * requires the accel-specific code in cpu_exec_realizefn to 7731 * have already acquired the CPUID data into cpu->mwait. 7732 */ 7733 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7734 7735 /* For 64bit systems think about the number of physical bits to present. 7736 * ideally this should be the same as the host; anything other than matching 7737 * the host can cause incorrect guest behaviour. 7738 * QEMU used to pick the magic value of 40 bits that corresponds to 7739 * consumer AMD devices but nothing else. 7740 * 7741 * Note that this code assumes features expansion has already been done 7742 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7743 * phys_bits adjustments to match the host have been already done in 7744 * accel-specific code in cpu_exec_realizefn. 7745 */ 7746 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7747 if (cpu->phys_bits && 7748 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7749 cpu->phys_bits < 32)) { 7750 error_setg(errp, "phys-bits should be between 32 and %u " 7751 " (but is %u)", 7752 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7753 return; 7754 } 7755 /* 7756 * 0 means it was not explicitly set by the user (or by machine 7757 * compat_props or by the host code in host-cpu.c). 7758 * In this case, the default is the value used by TCG (40). 7759 */ 7760 if (cpu->phys_bits == 0) { 7761 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7762 } 7763 if (cpu->guest_phys_bits && 7764 (cpu->guest_phys_bits > cpu->phys_bits || 7765 cpu->guest_phys_bits < 32)) { 7766 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7767 " (but is %u)", 7768 cpu->phys_bits, cpu->guest_phys_bits); 7769 return; 7770 } 7771 } else { 7772 /* For 32 bit systems don't use the user set value, but keep 7773 * phys_bits consistent with what we tell the guest. 7774 */ 7775 if (cpu->phys_bits != 0) { 7776 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7777 return; 7778 } 7779 if (cpu->guest_phys_bits != 0) { 7780 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7781 return; 7782 } 7783 7784 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7785 cpu->phys_bits = 36; 7786 } else { 7787 cpu->phys_bits = 32; 7788 } 7789 } 7790 7791 /* Cache information initialization */ 7792 if (!cpu->legacy_cache) { 7793 const CPUCaches *cache_info = 7794 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7795 7796 if (!xcc->model || !cache_info) { 7797 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7798 error_setg(errp, 7799 "CPU model '%s' doesn't support legacy-cache=off", name); 7800 return; 7801 } 7802 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7803 *cache_info; 7804 } else { 7805 /* Build legacy cache information */ 7806 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7807 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7808 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7809 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7810 7811 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7812 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7813 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7814 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7815 7816 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7817 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7818 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7819 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7820 } 7821 7822 #ifndef CONFIG_USER_ONLY 7823 MachineState *ms = MACHINE(qdev_get_machine()); 7824 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7825 7826 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7827 x86_cpu_apic_create(cpu, &local_err); 7828 if (local_err != NULL) { 7829 goto out; 7830 } 7831 } 7832 #endif 7833 7834 mce_init(cpu); 7835 7836 x86_cpu_gdb_init(cs); 7837 qemu_init_vcpu(cs); 7838 7839 /* 7840 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7841 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7842 * based on inputs (sockets,cores,threads), it is still better to give 7843 * users a warning. 7844 * 7845 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7846 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7847 */ 7848 if (IS_AMD_CPU(env) && 7849 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7850 cs->nr_threads > 1) { 7851 warn_report_once("This family of AMD CPU doesn't support " 7852 "hyperthreading(%d). Please configure -smp " 7853 "options properly or try enabling topoext " 7854 "feature.", cs->nr_threads); 7855 } 7856 7857 #ifndef CONFIG_USER_ONLY 7858 x86_cpu_apic_realize(cpu, &local_err); 7859 if (local_err != NULL) { 7860 goto out; 7861 } 7862 #endif /* !CONFIG_USER_ONLY */ 7863 cpu_reset(cs); 7864 7865 xcc->parent_realize(dev, &local_err); 7866 7867 out: 7868 if (local_err != NULL) { 7869 error_propagate(errp, local_err); 7870 return; 7871 } 7872 } 7873 7874 static void x86_cpu_unrealizefn(DeviceState *dev) 7875 { 7876 X86CPU *cpu = X86_CPU(dev); 7877 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7878 7879 #ifndef CONFIG_USER_ONLY 7880 cpu_remove_sync(CPU(dev)); 7881 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7882 #endif 7883 7884 if (cpu->apic_state) { 7885 object_unparent(OBJECT(cpu->apic_state)); 7886 cpu->apic_state = NULL; 7887 } 7888 7889 xcc->parent_unrealize(dev); 7890 } 7891 7892 typedef struct BitProperty { 7893 FeatureWord w; 7894 uint64_t mask; 7895 } BitProperty; 7896 7897 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7898 void *opaque, Error **errp) 7899 { 7900 X86CPU *cpu = X86_CPU(obj); 7901 BitProperty *fp = opaque; 7902 uint64_t f = cpu->env.features[fp->w]; 7903 bool value = (f & fp->mask) == fp->mask; 7904 visit_type_bool(v, name, &value, errp); 7905 } 7906 7907 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7908 void *opaque, Error **errp) 7909 { 7910 DeviceState *dev = DEVICE(obj); 7911 X86CPU *cpu = X86_CPU(obj); 7912 BitProperty *fp = opaque; 7913 bool value; 7914 7915 if (dev->realized) { 7916 qdev_prop_set_after_realize(dev, name, errp); 7917 return; 7918 } 7919 7920 if (!visit_type_bool(v, name, &value, errp)) { 7921 return; 7922 } 7923 7924 if (value) { 7925 cpu->env.features[fp->w] |= fp->mask; 7926 } else { 7927 cpu->env.features[fp->w] &= ~fp->mask; 7928 } 7929 cpu->env.user_features[fp->w] |= fp->mask; 7930 } 7931 7932 /* Register a boolean property to get/set a single bit in a uint32_t field. 7933 * 7934 * The same property name can be registered multiple times to make it affect 7935 * multiple bits in the same FeatureWord. In that case, the getter will return 7936 * true only if all bits are set. 7937 */ 7938 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7939 const char *prop_name, 7940 FeatureWord w, 7941 int bitnr) 7942 { 7943 ObjectClass *oc = OBJECT_CLASS(xcc); 7944 BitProperty *fp; 7945 ObjectProperty *op; 7946 uint64_t mask = (1ULL << bitnr); 7947 7948 op = object_class_property_find(oc, prop_name); 7949 if (op) { 7950 fp = op->opaque; 7951 assert(fp->w == w); 7952 fp->mask |= mask; 7953 } else { 7954 fp = g_new0(BitProperty, 1); 7955 fp->w = w; 7956 fp->mask = mask; 7957 object_class_property_add(oc, prop_name, "bool", 7958 x86_cpu_get_bit_prop, 7959 x86_cpu_set_bit_prop, 7960 NULL, fp); 7961 } 7962 } 7963 7964 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7965 FeatureWord w, 7966 int bitnr) 7967 { 7968 FeatureWordInfo *fi = &feature_word_info[w]; 7969 const char *name = fi->feat_names[bitnr]; 7970 7971 if (!name) { 7972 return; 7973 } 7974 7975 /* Property names should use "-" instead of "_". 7976 * Old names containing underscores are registered as aliases 7977 * using object_property_add_alias() 7978 */ 7979 assert(!strchr(name, '_')); 7980 /* aliases don't use "|" delimiters anymore, they are registered 7981 * manually using object_property_add_alias() */ 7982 assert(!strchr(name, '|')); 7983 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7984 } 7985 7986 static void x86_cpu_post_initfn(Object *obj) 7987 { 7988 accel_cpu_instance_init(CPU(obj)); 7989 } 7990 7991 static void x86_cpu_init_default_topo(X86CPU *cpu) 7992 { 7993 CPUX86State *env = &cpu->env; 7994 7995 env->nr_modules = 1; 7996 env->nr_dies = 1; 7997 7998 /* SMT, core and package levels are set by default. */ 7999 set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); 8000 set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); 8001 set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); 8002 } 8003 8004 static void x86_cpu_initfn(Object *obj) 8005 { 8006 X86CPU *cpu = X86_CPU(obj); 8007 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8008 CPUX86State *env = &cpu->env; 8009 8010 x86_cpu_init_default_topo(cpu); 8011 8012 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8013 x86_cpu_get_feature_words, 8014 NULL, NULL, (void *)env->features); 8015 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8016 x86_cpu_get_feature_words, 8017 NULL, NULL, (void *)cpu->filtered_features); 8018 8019 object_property_add_alias(obj, "sse3", obj, "pni"); 8020 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8021 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8022 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8023 object_property_add_alias(obj, "xd", obj, "nx"); 8024 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8025 object_property_add_alias(obj, "i64", obj, "lm"); 8026 8027 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8028 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8029 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8030 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8031 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8032 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8033 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8034 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8035 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8036 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8037 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8038 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8039 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8040 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8041 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8042 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8043 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8044 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8045 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8046 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8047 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8048 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8049 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8050 8051 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8052 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8053 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8054 8055 if (xcc->model) { 8056 x86_cpu_load_model(cpu, xcc->model); 8057 } 8058 } 8059 8060 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8061 { 8062 X86CPU *cpu = X86_CPU(cs); 8063 8064 return cpu->apic_id; 8065 } 8066 8067 #if !defined(CONFIG_USER_ONLY) 8068 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8069 { 8070 X86CPU *cpu = X86_CPU(cs); 8071 8072 return cpu->env.cr[0] & CR0_PG_MASK; 8073 } 8074 #endif /* !CONFIG_USER_ONLY */ 8075 8076 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8077 { 8078 X86CPU *cpu = X86_CPU(cs); 8079 8080 cpu->env.eip = value; 8081 } 8082 8083 static vaddr x86_cpu_get_pc(CPUState *cs) 8084 { 8085 X86CPU *cpu = X86_CPU(cs); 8086 8087 /* Match cpu_get_tb_cpu_state. */ 8088 return cpu->env.eip + cpu->env.segs[R_CS].base; 8089 } 8090 8091 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8092 { 8093 X86CPU *cpu = X86_CPU(cs); 8094 CPUX86State *env = &cpu->env; 8095 8096 #if !defined(CONFIG_USER_ONLY) 8097 if (interrupt_request & CPU_INTERRUPT_POLL) { 8098 return CPU_INTERRUPT_POLL; 8099 } 8100 #endif 8101 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8102 return CPU_INTERRUPT_SIPI; 8103 } 8104 8105 if (env->hflags2 & HF2_GIF_MASK) { 8106 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8107 !(env->hflags & HF_SMM_MASK)) { 8108 return CPU_INTERRUPT_SMI; 8109 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8110 !(env->hflags2 & HF2_NMI_MASK)) { 8111 return CPU_INTERRUPT_NMI; 8112 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8113 return CPU_INTERRUPT_MCE; 8114 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8115 (((env->hflags2 & HF2_VINTR_MASK) && 8116 (env->hflags2 & HF2_HIF_MASK)) || 8117 (!(env->hflags2 & HF2_VINTR_MASK) && 8118 (env->eflags & IF_MASK && 8119 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8120 return CPU_INTERRUPT_HARD; 8121 #if !defined(CONFIG_USER_ONLY) 8122 } else if (env->hflags2 & HF2_VGIF_MASK) { 8123 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8124 (env->eflags & IF_MASK) && 8125 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8126 return CPU_INTERRUPT_VIRQ; 8127 } 8128 #endif 8129 } 8130 } 8131 8132 return 0; 8133 } 8134 8135 static bool x86_cpu_has_work(CPUState *cs) 8136 { 8137 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8138 } 8139 8140 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8141 { 8142 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8143 int mmu_index_base = 8144 pl == 3 ? MMU_USER64_IDX : 8145 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8146 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8147 8148 return mmu_index_base + mmu_index_32; 8149 } 8150 8151 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8152 { 8153 CPUX86State *env = cpu_env(cs); 8154 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8155 } 8156 8157 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8158 { 8159 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8160 int mmu_index_base = 8161 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8162 (pl < 3 && (env->eflags & AC_MASK) 8163 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8164 8165 return mmu_index_base + mmu_index_32; 8166 } 8167 8168 int cpu_mmu_index_kernel(CPUX86State *env) 8169 { 8170 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8171 } 8172 8173 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8174 { 8175 X86CPU *cpu = X86_CPU(cs); 8176 CPUX86State *env = &cpu->env; 8177 8178 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8179 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8180 : bfd_mach_i386_i8086); 8181 8182 info->cap_arch = CS_ARCH_X86; 8183 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8184 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8185 : CS_MODE_16); 8186 info->cap_insn_unit = 1; 8187 info->cap_insn_split = 8; 8188 } 8189 8190 void x86_update_hflags(CPUX86State *env) 8191 { 8192 uint32_t hflags; 8193 #define HFLAG_COPY_MASK \ 8194 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8195 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8196 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8197 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8198 8199 hflags = env->hflags & HFLAG_COPY_MASK; 8200 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8201 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8202 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8203 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8204 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8205 8206 if (env->cr[4] & CR4_OSFXSR_MASK) { 8207 hflags |= HF_OSFXSR_MASK; 8208 } 8209 8210 if (env->efer & MSR_EFER_LMA) { 8211 hflags |= HF_LMA_MASK; 8212 } 8213 8214 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8215 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8216 } else { 8217 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8218 (DESC_B_SHIFT - HF_CS32_SHIFT); 8219 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8220 (DESC_B_SHIFT - HF_SS32_SHIFT); 8221 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8222 !(hflags & HF_CS32_MASK)) { 8223 hflags |= HF_ADDSEG_MASK; 8224 } else { 8225 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8226 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8227 } 8228 } 8229 env->hflags = hflags; 8230 } 8231 8232 static Property x86_cpu_properties[] = { 8233 #ifdef CONFIG_USER_ONLY 8234 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8235 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8236 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8237 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8238 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8239 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8240 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8241 #else 8242 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8243 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8244 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8245 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8246 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8247 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8248 #endif 8249 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8250 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8251 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8252 8253 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8254 HYPERV_SPINLOCK_NEVER_NOTIFY), 8255 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8256 HYPERV_FEAT_RELAXED, 0), 8257 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8258 HYPERV_FEAT_VAPIC, 0), 8259 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8260 HYPERV_FEAT_TIME, 0), 8261 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8262 HYPERV_FEAT_CRASH, 0), 8263 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8264 HYPERV_FEAT_RESET, 0), 8265 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8266 HYPERV_FEAT_VPINDEX, 0), 8267 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8268 HYPERV_FEAT_RUNTIME, 0), 8269 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8270 HYPERV_FEAT_SYNIC, 0), 8271 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8272 HYPERV_FEAT_STIMER, 0), 8273 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8274 HYPERV_FEAT_FREQUENCIES, 0), 8275 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8276 HYPERV_FEAT_REENLIGHTENMENT, 0), 8277 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8278 HYPERV_FEAT_TLBFLUSH, 0), 8279 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8280 HYPERV_FEAT_EVMCS, 0), 8281 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8282 HYPERV_FEAT_IPI, 0), 8283 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8284 HYPERV_FEAT_STIMER_DIRECT, 0), 8285 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8286 HYPERV_FEAT_AVIC, 0), 8287 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8288 HYPERV_FEAT_MSR_BITMAP, 0), 8289 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8290 HYPERV_FEAT_XMM_INPUT, 0), 8291 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8292 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8293 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8294 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8295 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8296 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8297 #ifdef CONFIG_SYNDBG 8298 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8299 HYPERV_FEAT_SYNDBG, 0), 8300 #endif 8301 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8302 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8303 8304 /* WS2008R2 identify by default */ 8305 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8306 0x3839), 8307 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8308 0x000A), 8309 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8310 0x0000), 8311 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8312 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8313 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8314 8315 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8316 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8317 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8318 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8319 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8320 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8321 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8322 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8323 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8324 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8325 UINT32_MAX), 8326 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8327 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8328 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8329 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8330 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8331 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8332 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8333 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8334 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8335 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8336 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8337 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8338 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8339 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8340 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8341 false), 8342 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8343 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8344 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8345 true), 8346 /* 8347 * lecacy_cache defaults to true unless the CPU model provides its 8348 * own cache information (see x86_cpu_load_def()). 8349 */ 8350 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8351 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8352 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8353 8354 /* 8355 * From "Requirements for Implementing the Microsoft 8356 * Hypervisor Interface": 8357 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8358 * 8359 * "Starting with Windows Server 2012 and Windows 8, if 8360 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8361 * the hypervisor imposes no specific limit to the number of VPs. 8362 * In this case, Windows Server 2012 guest VMs may use more than 8363 * 64 VPs, up to the maximum supported number of processors applicable 8364 * to the specific Windows version being used." 8365 */ 8366 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8367 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8368 false), 8369 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8370 true), 8371 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8372 DEFINE_PROP_END_OF_LIST() 8373 }; 8374 8375 #ifndef CONFIG_USER_ONLY 8376 #include "hw/core/sysemu-cpu-ops.h" 8377 8378 static const struct SysemuCPUOps i386_sysemu_ops = { 8379 .get_memory_mapping = x86_cpu_get_memory_mapping, 8380 .get_paging_enabled = x86_cpu_get_paging_enabled, 8381 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8382 .asidx_from_attrs = x86_asidx_from_attrs, 8383 .get_crash_info = x86_cpu_get_crash_info, 8384 .write_elf32_note = x86_cpu_write_elf32_note, 8385 .write_elf64_note = x86_cpu_write_elf64_note, 8386 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8387 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8388 .legacy_vmsd = &vmstate_x86_cpu, 8389 }; 8390 #endif 8391 8392 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8393 { 8394 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8395 CPUClass *cc = CPU_CLASS(oc); 8396 DeviceClass *dc = DEVICE_CLASS(oc); 8397 ResettableClass *rc = RESETTABLE_CLASS(oc); 8398 FeatureWord w; 8399 8400 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8401 &xcc->parent_realize); 8402 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8403 &xcc->parent_unrealize); 8404 device_class_set_props(dc, x86_cpu_properties); 8405 8406 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8407 &xcc->parent_phases); 8408 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8409 8410 cc->class_by_name = x86_cpu_class_by_name; 8411 cc->parse_features = x86_cpu_parse_featurestr; 8412 cc->has_work = x86_cpu_has_work; 8413 cc->mmu_index = x86_cpu_mmu_index; 8414 cc->dump_state = x86_cpu_dump_state; 8415 cc->set_pc = x86_cpu_set_pc; 8416 cc->get_pc = x86_cpu_get_pc; 8417 cc->gdb_read_register = x86_cpu_gdb_read_register; 8418 cc->gdb_write_register = x86_cpu_gdb_write_register; 8419 cc->get_arch_id = x86_cpu_get_arch_id; 8420 8421 #ifndef CONFIG_USER_ONLY 8422 cc->sysemu_ops = &i386_sysemu_ops; 8423 #endif /* !CONFIG_USER_ONLY */ 8424 8425 cc->gdb_arch_name = x86_gdb_arch_name; 8426 #ifdef TARGET_X86_64 8427 cc->gdb_core_xml_file = "i386-64bit.xml"; 8428 #else 8429 cc->gdb_core_xml_file = "i386-32bit.xml"; 8430 #endif 8431 cc->disas_set_info = x86_disas_set_info; 8432 8433 dc->user_creatable = true; 8434 8435 object_class_property_add(oc, "family", "int", 8436 x86_cpuid_version_get_family, 8437 x86_cpuid_version_set_family, NULL, NULL); 8438 object_class_property_add(oc, "model", "int", 8439 x86_cpuid_version_get_model, 8440 x86_cpuid_version_set_model, NULL, NULL); 8441 object_class_property_add(oc, "stepping", "int", 8442 x86_cpuid_version_get_stepping, 8443 x86_cpuid_version_set_stepping, NULL, NULL); 8444 object_class_property_add_str(oc, "vendor", 8445 x86_cpuid_get_vendor, 8446 x86_cpuid_set_vendor); 8447 object_class_property_add_str(oc, "model-id", 8448 x86_cpuid_get_model_id, 8449 x86_cpuid_set_model_id); 8450 object_class_property_add(oc, "tsc-frequency", "int", 8451 x86_cpuid_get_tsc_freq, 8452 x86_cpuid_set_tsc_freq, NULL, NULL); 8453 /* 8454 * The "unavailable-features" property has the same semantics as 8455 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8456 * QMP command: they list the features that would have prevented the 8457 * CPU from running if the "enforce" flag was set. 8458 */ 8459 object_class_property_add(oc, "unavailable-features", "strList", 8460 x86_cpu_get_unavailable_features, 8461 NULL, NULL, NULL); 8462 8463 #if !defined(CONFIG_USER_ONLY) 8464 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8465 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8466 #endif 8467 8468 for (w = 0; w < FEATURE_WORDS; w++) { 8469 int bitnr; 8470 for (bitnr = 0; bitnr < 64; bitnr++) { 8471 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8472 } 8473 } 8474 } 8475 8476 static const TypeInfo x86_cpu_type_info = { 8477 .name = TYPE_X86_CPU, 8478 .parent = TYPE_CPU, 8479 .instance_size = sizeof(X86CPU), 8480 .instance_align = __alignof(X86CPU), 8481 .instance_init = x86_cpu_initfn, 8482 .instance_post_init = x86_cpu_post_initfn, 8483 8484 .abstract = true, 8485 .class_size = sizeof(X86CPUClass), 8486 .class_init = x86_cpu_common_class_init, 8487 }; 8488 8489 /* "base" CPU model, used by query-cpu-model-expansion */ 8490 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8491 { 8492 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8493 8494 xcc->static_model = true; 8495 xcc->migration_safe = true; 8496 xcc->model_description = "base CPU model type with no features enabled"; 8497 xcc->ordering = 8; 8498 } 8499 8500 static const TypeInfo x86_base_cpu_type_info = { 8501 .name = X86_CPU_TYPE_NAME("base"), 8502 .parent = TYPE_X86_CPU, 8503 .class_init = x86_cpu_base_class_init, 8504 }; 8505 8506 static void x86_cpu_register_types(void) 8507 { 8508 int i; 8509 8510 type_register_static(&x86_cpu_type_info); 8511 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8512 x86_register_cpudef_types(&builtin_x86_defs[i]); 8513 } 8514 type_register_static(&max_x86_cpu_type_info); 8515 type_register_static(&x86_base_cpu_type_info); 8516 } 8517 8518 type_init(x86_cpu_register_types) 8519