1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "sysemu/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 51 /* Helpers for building CPUID[2] descriptors: */ 52 53 struct CPUID2CacheDescriptorInfo { 54 enum CacheType type; 55 int level; 56 int size; 57 int line_size; 58 int associativity; 59 }; 60 61 /* 62 * Known CPUID 2 cache descriptors. 63 * From Intel SDM Volume 2A, CPUID instruction 64 */ 65 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 67 .associativity = 4, .line_size = 32, }, 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 73 .associativity = 2, .line_size = 32, }, 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 79 .associativity = 6, .line_size = 64, }, 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 81 .associativity = 2, .line_size = 64, }, 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 83 .associativity = 8, .line_size = 64, }, 84 /* lines per sector is not supported cpuid2_cache_descriptor(), 85 * so descriptors 0x22, 0x23 are not included 86 */ 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 88 .associativity = 16, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x25, 0x20 are not included 91 */ 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 93 .associativity = 8, .line_size = 64, }, 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 107 .associativity = 4, .line_size = 64, }, 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 122 .associativity = 24, .line_size = 64, }, 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 8, .line_size = 64, }, 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 132 .associativity = 4, .line_size = 64, }, 133 /* lines per sector is not supported cpuid2_cache_descriptor(), 134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 135 */ 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 2, .line_size = 64, }, 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 64, }, 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 }; 185 186 /* 187 * "CPUID leaf 2 does not report cache descriptor information, 188 * use CPUID leaf 4 to query cache parameters" 189 */ 190 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 191 192 /* 193 * Return a CPUID 2 cache descriptor for a given cache. 194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 195 */ 196 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 197 { 198 int i; 199 200 assert(cache->size > 0); 201 assert(cache->level > 0); 202 assert(cache->line_size > 0); 203 assert(cache->associativity > 0); 204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 206 if (d->level == cache->level && d->type == cache->type && 207 d->size == cache->size && d->line_size == cache->line_size && 208 d->associativity == cache->associativity) { 209 return i; 210 } 211 } 212 213 return CACHE_DESCRIPTOR_UNAVAILABLE; 214 } 215 216 /* CPUID Leaf 4 constants: */ 217 218 /* EAX: */ 219 #define CACHE_TYPE_D 1 220 #define CACHE_TYPE_I 2 221 #define CACHE_TYPE_UNIFIED 3 222 223 #define CACHE_LEVEL(l) (l << 5) 224 225 #define CACHE_SELF_INIT_LEVEL (1 << 8) 226 227 /* EDX: */ 228 #define CACHE_NO_INVD_SHARING (1 << 0) 229 #define CACHE_INCLUSIVE (1 << 1) 230 #define CACHE_COMPLEX_IDX (1 << 2) 231 232 /* Encode CacheType for CPUID[4].EAX */ 233 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 236 0 /* Invalid value */) 237 238 239 /* Encode cache info for CPUID[4] */ 240 static void encode_cache_cpuid4(CPUCacheInfo *cache, 241 int num_apic_ids, int num_cores, 242 uint32_t *eax, uint32_t *ebx, 243 uint32_t *ecx, uint32_t *edx) 244 { 245 assert(cache->size == cache->line_size * cache->associativity * 246 cache->partitions * cache->sets); 247 248 assert(num_apic_ids > 0); 249 *eax = CACHE_TYPE(cache->type) | 250 CACHE_LEVEL(cache->level) | 251 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 252 ((num_cores - 1) << 26) | 253 ((num_apic_ids - 1) << 14); 254 255 assert(cache->line_size > 0); 256 assert(cache->partitions > 0); 257 assert(cache->associativity > 0); 258 /* We don't implement fully-associative caches */ 259 assert(cache->associativity < cache->sets); 260 *ebx = (cache->line_size - 1) | 261 ((cache->partitions - 1) << 12) | 262 ((cache->associativity - 1) << 22); 263 264 assert(cache->sets > 0); 265 *ecx = cache->sets - 1; 266 267 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 268 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 269 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 270 } 271 272 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 273 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 274 { 275 assert(cache->size % 1024 == 0); 276 assert(cache->lines_per_tag > 0); 277 assert(cache->associativity > 0); 278 assert(cache->line_size > 0); 279 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 280 (cache->lines_per_tag << 8) | (cache->line_size); 281 } 282 283 #define ASSOC_FULL 0xFF 284 285 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 286 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 287 a == 2 ? 0x2 : \ 288 a == 4 ? 0x4 : \ 289 a == 8 ? 0x6 : \ 290 a == 16 ? 0x8 : \ 291 a == 32 ? 0xA : \ 292 a == 48 ? 0xB : \ 293 a == 64 ? 0xC : \ 294 a == 96 ? 0xD : \ 295 a == 128 ? 0xE : \ 296 a == ASSOC_FULL ? 0xF : \ 297 0 /* invalid value */) 298 299 /* 300 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 301 * @l3 can be NULL. 302 */ 303 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 304 CPUCacheInfo *l3, 305 uint32_t *ecx, uint32_t *edx) 306 { 307 assert(l2->size % 1024 == 0); 308 assert(l2->associativity > 0); 309 assert(l2->lines_per_tag > 0); 310 assert(l2->line_size > 0); 311 *ecx = ((l2->size / 1024) << 16) | 312 (AMD_ENC_ASSOC(l2->associativity) << 12) | 313 (l2->lines_per_tag << 8) | (l2->line_size); 314 315 if (l3) { 316 assert(l3->size % (512 * 1024) == 0); 317 assert(l3->associativity > 0); 318 assert(l3->lines_per_tag > 0); 319 assert(l3->line_size > 0); 320 *edx = ((l3->size / (512 * 1024)) << 18) | 321 (AMD_ENC_ASSOC(l3->associativity) << 12) | 322 (l3->lines_per_tag << 8) | (l3->line_size); 323 } else { 324 *edx = 0; 325 } 326 } 327 328 /* Encode cache info for CPUID[8000001D] */ 329 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 330 X86CPUTopoInfo *topo_info, 331 uint32_t *eax, uint32_t *ebx, 332 uint32_t *ecx, uint32_t *edx) 333 { 334 uint32_t l3_threads; 335 assert(cache->size == cache->line_size * cache->associativity * 336 cache->partitions * cache->sets); 337 338 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 339 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 340 341 /* L3 is shared among multiple cores */ 342 if (cache->level == 3) { 343 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 344 *eax |= (l3_threads - 1) << 14; 345 } else { 346 *eax |= ((topo_info->threads_per_core - 1) << 14); 347 } 348 349 assert(cache->line_size > 0); 350 assert(cache->partitions > 0); 351 assert(cache->associativity > 0); 352 /* We don't implement fully-associative caches */ 353 assert(cache->associativity < cache->sets); 354 *ebx = (cache->line_size - 1) | 355 ((cache->partitions - 1) << 12) | 356 ((cache->associativity - 1) << 22); 357 358 assert(cache->sets > 0); 359 *ecx = cache->sets - 1; 360 361 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 362 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 363 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 364 } 365 366 /* Encode cache info for CPUID[8000001E] */ 367 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 368 uint32_t *eax, uint32_t *ebx, 369 uint32_t *ecx, uint32_t *edx) 370 { 371 X86CPUTopoIDs topo_ids; 372 373 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 374 375 *eax = cpu->apic_id; 376 377 /* 378 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 379 * Read-only. Reset: 0000_XXXXh. 380 * See Core::X86::Cpuid::ExtApicId. 381 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 382 * Bits Description 383 * 31:16 Reserved. 384 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 385 * The number of threads per core is ThreadsPerCore+1. 386 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 387 * 388 * NOTE: CoreId is already part of apic_id. Just use it. We can 389 * use all the 8 bits to represent the core_id here. 390 */ 391 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 392 393 /* 394 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 395 * Read-only. Reset: 0000_0XXXh. 396 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 397 * Bits Description 398 * 31:11 Reserved. 399 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 400 * ValidValues: 401 * Value Description 402 * 000b 1 node per processor. 403 * 001b 2 nodes per processor. 404 * 010b Reserved. 405 * 011b 4 nodes per processor. 406 * 111b-100b Reserved. 407 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 408 * 409 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 410 * But users can create more nodes than the actual hardware can 411 * support. To genaralize we can use all the upper 8 bits for nodes. 412 * NodeId is combination of node and socket_id which is already decoded 413 * in apic_id. Just use it by shifting. 414 */ 415 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 416 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 417 418 *edx = 0; 419 } 420 421 /* 422 * Definitions of the hardcoded cache entries we expose: 423 * These are legacy cache values. If there is a need to change any 424 * of these values please use builtin_x86_defs 425 */ 426 427 /* L1 data cache: */ 428 static CPUCacheInfo legacy_l1d_cache = { 429 .type = DATA_CACHE, 430 .level = 1, 431 .size = 32 * KiB, 432 .self_init = 1, 433 .line_size = 64, 434 .associativity = 8, 435 .sets = 64, 436 .partitions = 1, 437 .no_invd_sharing = true, 438 }; 439 440 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 441 static CPUCacheInfo legacy_l1d_cache_amd = { 442 .type = DATA_CACHE, 443 .level = 1, 444 .size = 64 * KiB, 445 .self_init = 1, 446 .line_size = 64, 447 .associativity = 2, 448 .sets = 512, 449 .partitions = 1, 450 .lines_per_tag = 1, 451 .no_invd_sharing = true, 452 }; 453 454 /* L1 instruction cache: */ 455 static CPUCacheInfo legacy_l1i_cache = { 456 .type = INSTRUCTION_CACHE, 457 .level = 1, 458 .size = 32 * KiB, 459 .self_init = 1, 460 .line_size = 64, 461 .associativity = 8, 462 .sets = 64, 463 .partitions = 1, 464 .no_invd_sharing = true, 465 }; 466 467 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 468 static CPUCacheInfo legacy_l1i_cache_amd = { 469 .type = INSTRUCTION_CACHE, 470 .level = 1, 471 .size = 64 * KiB, 472 .self_init = 1, 473 .line_size = 64, 474 .associativity = 2, 475 .sets = 512, 476 .partitions = 1, 477 .lines_per_tag = 1, 478 .no_invd_sharing = true, 479 }; 480 481 /* Level 2 unified cache: */ 482 static CPUCacheInfo legacy_l2_cache = { 483 .type = UNIFIED_CACHE, 484 .level = 2, 485 .size = 4 * MiB, 486 .self_init = 1, 487 .line_size = 64, 488 .associativity = 16, 489 .sets = 4096, 490 .partitions = 1, 491 .no_invd_sharing = true, 492 }; 493 494 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 495 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 496 .type = UNIFIED_CACHE, 497 .level = 2, 498 .size = 2 * MiB, 499 .line_size = 64, 500 .associativity = 8, 501 }; 502 503 504 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 505 static CPUCacheInfo legacy_l2_cache_amd = { 506 .type = UNIFIED_CACHE, 507 .level = 2, 508 .size = 512 * KiB, 509 .line_size = 64, 510 .lines_per_tag = 1, 511 .associativity = 16, 512 .sets = 512, 513 .partitions = 1, 514 }; 515 516 /* Level 3 unified cache: */ 517 static CPUCacheInfo legacy_l3_cache = { 518 .type = UNIFIED_CACHE, 519 .level = 3, 520 .size = 16 * MiB, 521 .line_size = 64, 522 .associativity = 16, 523 .sets = 16384, 524 .partitions = 1, 525 .lines_per_tag = 1, 526 .self_init = true, 527 .inclusive = true, 528 .complex_indexing = true, 529 }; 530 531 /* TLB definitions: */ 532 533 #define L1_DTLB_2M_ASSOC 1 534 #define L1_DTLB_2M_ENTRIES 255 535 #define L1_DTLB_4K_ASSOC 1 536 #define L1_DTLB_4K_ENTRIES 255 537 538 #define L1_ITLB_2M_ASSOC 1 539 #define L1_ITLB_2M_ENTRIES 255 540 #define L1_ITLB_4K_ASSOC 1 541 #define L1_ITLB_4K_ENTRIES 255 542 543 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 544 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 545 #define L2_DTLB_4K_ASSOC 4 546 #define L2_DTLB_4K_ENTRIES 512 547 548 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 549 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 550 #define L2_ITLB_4K_ASSOC 4 551 #define L2_ITLB_4K_ENTRIES 512 552 553 /* CPUID Leaf 0x14 constants: */ 554 #define INTEL_PT_MAX_SUBLEAF 0x1 555 /* 556 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 557 * MSR can be accessed; 558 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 559 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 560 * of Intel PT MSRs across warm reset; 561 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 562 */ 563 #define INTEL_PT_MINIMAL_EBX 0xf 564 /* 565 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 566 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 567 * accessed; 568 * bit[01]: ToPA tables can hold any number of output entries, up to the 569 * maximum allowed by the MaskOrTableOffset field of 570 * IA32_RTIT_OUTPUT_MASK_PTRS; 571 * bit[02]: Support Single-Range Output scheme; 572 */ 573 #define INTEL_PT_MINIMAL_ECX 0x7 574 /* generated packets which contain IP payloads have LIP values */ 575 #define INTEL_PT_IP_LIP (1 << 31) 576 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 577 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 578 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 579 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 580 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 581 582 /* CPUID Leaf 0x1D constants: */ 583 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 584 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 585 #define INTEL_AMX_BYTES_PER_TILE 0x400 586 #define INTEL_AMX_BYTES_PER_ROW 0x40 587 #define INTEL_AMX_TILE_MAX_NAMES 0x8 588 #define INTEL_AMX_TILE_MAX_ROWS 0x10 589 590 /* CPUID Leaf 0x1E constants: */ 591 #define INTEL_AMX_TMUL_MAX_K 0x10 592 #define INTEL_AMX_TMUL_MAX_N 0x40 593 594 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 595 uint32_t vendor2, uint32_t vendor3) 596 { 597 int i; 598 for (i = 0; i < 4; i++) { 599 dst[i] = vendor1 >> (8 * i); 600 dst[i + 4] = vendor2 >> (8 * i); 601 dst[i + 8] = vendor3 >> (8 * i); 602 } 603 dst[CPUID_VENDOR_SZ] = '\0'; 604 } 605 606 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 607 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 608 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 609 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 610 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 611 CPUID_PSE36 | CPUID_FXSR) 612 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 613 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 614 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 615 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 616 CPUID_PAE | CPUID_SEP | CPUID_APIC) 617 618 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 619 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 620 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 621 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 622 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 623 /* partly implemented: 624 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 625 /* missing: 626 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 627 628 /* 629 * Kernel-only features that can be shown to usermode programs even if 630 * they aren't actually supported by TCG, because qemu-user only runs 631 * in CPL=3; remove them if they are ever implemented for system emulation. 632 */ 633 #if defined CONFIG_USER_ONLY 634 #define CPUID_EXT_KERNEL_FEATURES \ 635 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 636 #else 637 #define CPUID_EXT_KERNEL_FEATURES 0 638 #endif 639 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 644 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 645 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 646 /* missing: 647 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 648 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 649 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 650 CPUID_EXT_TSC_DEADLINE_TIMER 651 */ 652 653 #ifdef TARGET_X86_64 654 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 655 #else 656 #define TCG_EXT2_X86_64_FEATURES 0 657 #endif 658 659 /* 660 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 661 * in usermode or by 32-bit programs. Those are added to supported 662 * TCG features unconditionally in user-mode emulation mode. This may 663 * indeed seem strange or incorrect, but it works because code running 664 * under usermode emulation cannot access them. 665 * 666 * Even for long mode, qemu-i386 is not running "a userspace program on a 667 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 668 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 669 * but again the difference is only visible in kernel mode. 670 */ 671 #if defined CONFIG_LINUX_USER 672 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 673 #elif defined CONFIG_USER_ONLY 674 /* FIXME: Long mode not yet supported for i386 bsd-user */ 675 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 676 #else 677 #define CPUID_EXT2_KERNEL_FEATURES 0 678 #endif 679 680 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 681 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 682 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 683 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 684 CPUID_EXT2_KERNEL_FEATURES) 685 686 #if defined CONFIG_USER_ONLY 687 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 688 #else 689 #define CPUID_EXT3_KERNEL_FEATURES 0 690 #endif 691 692 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 693 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 694 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 695 696 #define TCG_EXT4_FEATURES 0 697 698 #if defined CONFIG_USER_ONLY 699 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 700 #else 701 #define CPUID_SVM_KERNEL_FEATURES 0 702 #endif 703 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 704 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 705 706 #define TCG_KVM_FEATURES 0 707 708 #if defined CONFIG_USER_ONLY 709 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 710 #else 711 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 712 #endif 713 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 714 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 715 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 716 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 717 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 718 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 719 /* missing: 720 CPUID_7_0_EBX_HLE 721 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 722 723 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 724 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 725 #else 726 #define TCG_7_0_ECX_RDPID 0 727 #endif 728 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 729 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 730 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 731 TCG_7_0_ECX_RDPID) 732 733 #if defined CONFIG_USER_ONLY 734 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 735 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 736 #else 737 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 738 #endif 739 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 740 741 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 742 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 743 #define TCG_7_1_EDX_FEATURES 0 744 #define TCG_7_2_EDX_FEATURES 0 745 #define TCG_APM_FEATURES 0 746 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 747 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 748 /* missing: 749 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 750 #define TCG_14_0_ECX_FEATURES 0 751 #define TCG_SGX_12_0_EAX_FEATURES 0 752 #define TCG_SGX_12_0_EBX_FEATURES 0 753 #define TCG_SGX_12_1_EAX_FEATURES 0 754 755 #if defined CONFIG_USER_ONLY 756 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 757 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 758 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 759 CPUID_8000_0008_EBX_AMD_PSFD) 760 #else 761 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 762 #endif 763 764 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 765 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 766 767 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 768 [FEAT_1_EDX] = { 769 .type = CPUID_FEATURE_WORD, 770 .feat_names = { 771 "fpu", "vme", "de", "pse", 772 "tsc", "msr", "pae", "mce", 773 "cx8", "apic", NULL, "sep", 774 "mtrr", "pge", "mca", "cmov", 775 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 776 NULL, "ds" /* Intel dts */, "acpi", "mmx", 777 "fxsr", "sse", "sse2", "ss", 778 "ht" /* Intel htt */, "tm", "ia64", "pbe", 779 }, 780 .cpuid = {.eax = 1, .reg = R_EDX, }, 781 .tcg_features = TCG_FEATURES, 782 .no_autoenable_flags = CPUID_HT, 783 }, 784 [FEAT_1_ECX] = { 785 .type = CPUID_FEATURE_WORD, 786 .feat_names = { 787 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 788 "ds-cpl", "vmx", "smx", "est", 789 "tm2", "ssse3", "cid", NULL, 790 "fma", "cx16", "xtpr", "pdcm", 791 NULL, "pcid", "dca", "sse4.1", 792 "sse4.2", "x2apic", "movbe", "popcnt", 793 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 794 "avx", "f16c", "rdrand", "hypervisor", 795 }, 796 .cpuid = { .eax = 1, .reg = R_ECX, }, 797 .tcg_features = TCG_EXT_FEATURES, 798 }, 799 /* Feature names that are already defined on feature_name[] but 800 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 801 * names on feat_names below. They are copied automatically 802 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 803 */ 804 [FEAT_8000_0001_EDX] = { 805 .type = CPUID_FEATURE_WORD, 806 .feat_names = { 807 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 808 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 809 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 810 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 811 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 812 "nx", NULL, "mmxext", NULL /* mmx */, 813 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 814 NULL, "lm", "3dnowext", "3dnow", 815 }, 816 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 817 .tcg_features = TCG_EXT2_FEATURES, 818 }, 819 [FEAT_8000_0001_ECX] = { 820 .type = CPUID_FEATURE_WORD, 821 .feat_names = { 822 "lahf-lm", "cmp-legacy", "svm", "extapic", 823 "cr8legacy", "abm", "sse4a", "misalignsse", 824 "3dnowprefetch", "osvw", "ibs", "xop", 825 "skinit", "wdt", NULL, "lwp", 826 "fma4", "tce", NULL, "nodeid-msr", 827 NULL, "tbm", "topoext", "perfctr-core", 828 "perfctr-nb", NULL, NULL, NULL, 829 NULL, NULL, NULL, NULL, 830 }, 831 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 832 .tcg_features = TCG_EXT3_FEATURES, 833 /* 834 * TOPOEXT is always allowed but can't be enabled blindly by 835 * "-cpu host", as it requires consistent cache topology info 836 * to be provided so it doesn't confuse guests. 837 */ 838 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 839 }, 840 [FEAT_C000_0001_EDX] = { 841 .type = CPUID_FEATURE_WORD, 842 .feat_names = { 843 NULL, NULL, "xstore", "xstore-en", 844 NULL, NULL, "xcrypt", "xcrypt-en", 845 "ace2", "ace2-en", "phe", "phe-en", 846 "pmm", "pmm-en", NULL, NULL, 847 NULL, NULL, NULL, NULL, 848 NULL, NULL, NULL, NULL, 849 NULL, NULL, NULL, NULL, 850 NULL, NULL, NULL, NULL, 851 }, 852 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 853 .tcg_features = TCG_EXT4_FEATURES, 854 }, 855 [FEAT_KVM] = { 856 .type = CPUID_FEATURE_WORD, 857 .feat_names = { 858 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 859 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 860 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 861 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 862 NULL, NULL, NULL, NULL, 863 NULL, NULL, NULL, NULL, 864 "kvmclock-stable-bit", NULL, NULL, NULL, 865 NULL, NULL, NULL, NULL, 866 }, 867 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 868 .tcg_features = TCG_KVM_FEATURES, 869 }, 870 [FEAT_KVM_HINTS] = { 871 .type = CPUID_FEATURE_WORD, 872 .feat_names = { 873 "kvm-hint-dedicated", NULL, NULL, NULL, 874 NULL, NULL, NULL, NULL, 875 NULL, NULL, NULL, NULL, 876 NULL, NULL, NULL, NULL, 877 NULL, NULL, NULL, NULL, 878 NULL, NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 NULL, NULL, NULL, NULL, 881 }, 882 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 883 .tcg_features = TCG_KVM_FEATURES, 884 /* 885 * KVM hints aren't auto-enabled by -cpu host, they need to be 886 * explicitly enabled in the command-line. 887 */ 888 .no_autoenable_flags = ~0U, 889 }, 890 [FEAT_SVM] = { 891 .type = CPUID_FEATURE_WORD, 892 .feat_names = { 893 "npt", "lbrv", "svm-lock", "nrip-save", 894 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 895 NULL, NULL, "pause-filter", NULL, 896 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 897 "vgif", NULL, NULL, NULL, 898 NULL, NULL, NULL, NULL, 899 NULL, "vnmi", NULL, NULL, 900 "svme-addr-chk", NULL, NULL, NULL, 901 }, 902 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 903 .tcg_features = TCG_SVM_FEATURES, 904 }, 905 [FEAT_7_0_EBX] = { 906 .type = CPUID_FEATURE_WORD, 907 .feat_names = { 908 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 909 "hle", "avx2", NULL, "smep", 910 "bmi2", "erms", "invpcid", "rtm", 911 NULL, NULL, "mpx", NULL, 912 "avx512f", "avx512dq", "rdseed", "adx", 913 "smap", "avx512ifma", "pcommit", "clflushopt", 914 "clwb", "intel-pt", "avx512pf", "avx512er", 915 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 916 }, 917 .cpuid = { 918 .eax = 7, 919 .needs_ecx = true, .ecx = 0, 920 .reg = R_EBX, 921 }, 922 .tcg_features = TCG_7_0_EBX_FEATURES, 923 }, 924 [FEAT_7_0_ECX] = { 925 .type = CPUID_FEATURE_WORD, 926 .feat_names = { 927 NULL, "avx512vbmi", "umip", "pku", 928 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 929 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 930 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 931 "la57", NULL, NULL, NULL, 932 NULL, NULL, "rdpid", NULL, 933 "bus-lock-detect", "cldemote", NULL, "movdiri", 934 "movdir64b", NULL, "sgxlc", "pks", 935 }, 936 .cpuid = { 937 .eax = 7, 938 .needs_ecx = true, .ecx = 0, 939 .reg = R_ECX, 940 }, 941 .tcg_features = TCG_7_0_ECX_FEATURES, 942 }, 943 [FEAT_7_0_EDX] = { 944 .type = CPUID_FEATURE_WORD, 945 .feat_names = { 946 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 947 "fsrm", NULL, NULL, NULL, 948 "avx512-vp2intersect", NULL, "md-clear", NULL, 949 NULL, NULL, "serialize", NULL, 950 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 951 NULL, NULL, "amx-bf16", "avx512-fp16", 952 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 953 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 954 }, 955 .cpuid = { 956 .eax = 7, 957 .needs_ecx = true, .ecx = 0, 958 .reg = R_EDX, 959 }, 960 .tcg_features = TCG_7_0_EDX_FEATURES, 961 }, 962 [FEAT_7_1_EAX] = { 963 .type = CPUID_FEATURE_WORD, 964 .feat_names = { 965 NULL, NULL, NULL, NULL, 966 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 967 NULL, NULL, "fzrm", "fsrs", 968 "fsrc", NULL, NULL, NULL, 969 NULL, NULL, NULL, NULL, 970 NULL, "amx-fp16", NULL, "avx-ifma", 971 NULL, NULL, NULL, NULL, 972 NULL, NULL, NULL, NULL, 973 }, 974 .cpuid = { 975 .eax = 7, 976 .needs_ecx = true, .ecx = 1, 977 .reg = R_EAX, 978 }, 979 .tcg_features = TCG_7_1_EAX_FEATURES, 980 }, 981 [FEAT_7_1_EDX] = { 982 .type = CPUID_FEATURE_WORD, 983 .feat_names = { 984 NULL, NULL, NULL, NULL, 985 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 986 "amx-complex", NULL, NULL, NULL, 987 NULL, NULL, "prefetchiti", NULL, 988 NULL, NULL, NULL, NULL, 989 NULL, NULL, NULL, NULL, 990 NULL, NULL, NULL, NULL, 991 NULL, NULL, NULL, NULL, 992 }, 993 .cpuid = { 994 .eax = 7, 995 .needs_ecx = true, .ecx = 1, 996 .reg = R_EDX, 997 }, 998 .tcg_features = TCG_7_1_EDX_FEATURES, 999 }, 1000 [FEAT_7_2_EDX] = { 1001 .type = CPUID_FEATURE_WORD, 1002 .feat_names = { 1003 NULL, NULL, NULL, NULL, 1004 NULL, "mcdt-no", NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 NULL, NULL, NULL, NULL, 1008 NULL, NULL, NULL, NULL, 1009 NULL, NULL, NULL, NULL, 1010 NULL, NULL, NULL, NULL, 1011 }, 1012 .cpuid = { 1013 .eax = 7, 1014 .needs_ecx = true, .ecx = 2, 1015 .reg = R_EDX, 1016 }, 1017 .tcg_features = TCG_7_2_EDX_FEATURES, 1018 }, 1019 [FEAT_8000_0007_EDX] = { 1020 .type = CPUID_FEATURE_WORD, 1021 .feat_names = { 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 "invtsc", NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 NULL, NULL, NULL, NULL, 1030 }, 1031 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1032 .tcg_features = TCG_APM_FEATURES, 1033 .unmigratable_flags = CPUID_APM_INVTSC, 1034 }, 1035 [FEAT_8000_0008_EBX] = { 1036 .type = CPUID_FEATURE_WORD, 1037 .feat_names = { 1038 "clzero", NULL, "xsaveerptr", NULL, 1039 NULL, NULL, NULL, NULL, 1040 NULL, "wbnoinvd", NULL, NULL, 1041 "ibpb", NULL, "ibrs", "amd-stibp", 1042 NULL, "stibp-always-on", NULL, NULL, 1043 NULL, NULL, NULL, NULL, 1044 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1045 "amd-psfd", NULL, NULL, NULL, 1046 }, 1047 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1048 .tcg_features = TCG_8000_0008_EBX, 1049 .unmigratable_flags = 0, 1050 }, 1051 [FEAT_8000_0021_EAX] = { 1052 .type = CPUID_FEATURE_WORD, 1053 .feat_names = { 1054 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1055 NULL, NULL, "null-sel-clr-base", NULL, 1056 "auto-ibrs", NULL, NULL, NULL, 1057 NULL, NULL, NULL, NULL, 1058 NULL, NULL, NULL, NULL, 1059 NULL, NULL, NULL, NULL, 1060 NULL, NULL, NULL, NULL, 1061 NULL, NULL, NULL, NULL, 1062 }, 1063 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1064 .tcg_features = 0, 1065 .unmigratable_flags = 0, 1066 }, 1067 [FEAT_XSAVE] = { 1068 .type = CPUID_FEATURE_WORD, 1069 .feat_names = { 1070 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1071 "xfd", NULL, NULL, NULL, 1072 NULL, NULL, NULL, NULL, 1073 NULL, NULL, NULL, NULL, 1074 NULL, NULL, NULL, NULL, 1075 NULL, NULL, NULL, NULL, 1076 NULL, NULL, NULL, NULL, 1077 NULL, NULL, NULL, NULL, 1078 }, 1079 .cpuid = { 1080 .eax = 0xd, 1081 .needs_ecx = true, .ecx = 1, 1082 .reg = R_EAX, 1083 }, 1084 .tcg_features = TCG_XSAVE_FEATURES, 1085 }, 1086 [FEAT_XSAVE_XSS_LO] = { 1087 .type = CPUID_FEATURE_WORD, 1088 .feat_names = { 1089 NULL, NULL, NULL, NULL, 1090 NULL, NULL, NULL, NULL, 1091 NULL, NULL, NULL, NULL, 1092 NULL, NULL, NULL, NULL, 1093 NULL, NULL, NULL, NULL, 1094 NULL, NULL, NULL, NULL, 1095 NULL, NULL, NULL, NULL, 1096 NULL, NULL, NULL, NULL, 1097 }, 1098 .cpuid = { 1099 .eax = 0xD, 1100 .needs_ecx = true, 1101 .ecx = 1, 1102 .reg = R_ECX, 1103 }, 1104 }, 1105 [FEAT_XSAVE_XSS_HI] = { 1106 .type = CPUID_FEATURE_WORD, 1107 .cpuid = { 1108 .eax = 0xD, 1109 .needs_ecx = true, 1110 .ecx = 1, 1111 .reg = R_EDX 1112 }, 1113 }, 1114 [FEAT_6_EAX] = { 1115 .type = CPUID_FEATURE_WORD, 1116 .feat_names = { 1117 NULL, NULL, "arat", NULL, 1118 NULL, NULL, NULL, NULL, 1119 NULL, NULL, NULL, NULL, 1120 NULL, NULL, NULL, NULL, 1121 NULL, NULL, NULL, NULL, 1122 NULL, NULL, NULL, NULL, 1123 NULL, NULL, NULL, NULL, 1124 NULL, NULL, NULL, NULL, 1125 }, 1126 .cpuid = { .eax = 6, .reg = R_EAX, }, 1127 .tcg_features = TCG_6_EAX_FEATURES, 1128 }, 1129 [FEAT_XSAVE_XCR0_LO] = { 1130 .type = CPUID_FEATURE_WORD, 1131 .cpuid = { 1132 .eax = 0xD, 1133 .needs_ecx = true, .ecx = 0, 1134 .reg = R_EAX, 1135 }, 1136 .tcg_features = ~0U, 1137 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1138 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1139 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1140 XSTATE_PKRU_MASK, 1141 }, 1142 [FEAT_XSAVE_XCR0_HI] = { 1143 .type = CPUID_FEATURE_WORD, 1144 .cpuid = { 1145 .eax = 0xD, 1146 .needs_ecx = true, .ecx = 0, 1147 .reg = R_EDX, 1148 }, 1149 .tcg_features = ~0U, 1150 }, 1151 /*Below are MSR exposed features*/ 1152 [FEAT_ARCH_CAPABILITIES] = { 1153 .type = MSR_FEATURE_WORD, 1154 .feat_names = { 1155 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1156 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1157 "taa-no", NULL, NULL, NULL, 1158 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1159 NULL, "fb-clear", NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 "pbrsb-no", NULL, "gds-no", "rfds-no", 1162 "rfds-clear", NULL, NULL, NULL, 1163 }, 1164 .msr = { 1165 .index = MSR_IA32_ARCH_CAPABILITIES, 1166 }, 1167 /* 1168 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1169 * cannot be read from user mode. Therefore, it has no impact 1170 > on any user-mode operation, and warnings about unsupported 1171 * features do not matter. 1172 */ 1173 .tcg_features = ~0U, 1174 }, 1175 [FEAT_CORE_CAPABILITY] = { 1176 .type = MSR_FEATURE_WORD, 1177 .feat_names = { 1178 NULL, NULL, NULL, NULL, 1179 NULL, "split-lock-detect", NULL, NULL, 1180 NULL, NULL, NULL, NULL, 1181 NULL, NULL, NULL, NULL, 1182 NULL, NULL, NULL, NULL, 1183 NULL, NULL, NULL, NULL, 1184 NULL, NULL, NULL, NULL, 1185 NULL, NULL, NULL, NULL, 1186 }, 1187 .msr = { 1188 .index = MSR_IA32_CORE_CAPABILITY, 1189 }, 1190 }, 1191 [FEAT_PERF_CAPABILITIES] = { 1192 .type = MSR_FEATURE_WORD, 1193 .feat_names = { 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 NULL, "full-width-write", NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 NULL, NULL, NULL, NULL, 1201 NULL, NULL, NULL, NULL, 1202 }, 1203 .msr = { 1204 .index = MSR_IA32_PERF_CAPABILITIES, 1205 }, 1206 }, 1207 1208 [FEAT_VMX_PROCBASED_CTLS] = { 1209 .type = MSR_FEATURE_WORD, 1210 .feat_names = { 1211 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1212 NULL, NULL, NULL, "vmx-hlt-exit", 1213 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1214 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1215 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1216 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1217 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1218 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1219 }, 1220 .msr = { 1221 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1222 } 1223 }, 1224 1225 [FEAT_VMX_SECONDARY_CTLS] = { 1226 .type = MSR_FEATURE_WORD, 1227 .feat_names = { 1228 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1229 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1230 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1231 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1232 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1233 "vmx-xsaves", NULL, NULL, NULL, 1234 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1235 NULL, NULL, NULL, NULL, 1236 }, 1237 .msr = { 1238 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1239 } 1240 }, 1241 1242 [FEAT_VMX_PINBASED_CTLS] = { 1243 .type = MSR_FEATURE_WORD, 1244 .feat_names = { 1245 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1246 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1247 NULL, NULL, NULL, NULL, 1248 NULL, NULL, NULL, NULL, 1249 NULL, NULL, NULL, NULL, 1250 NULL, NULL, NULL, NULL, 1251 NULL, NULL, NULL, NULL, 1252 NULL, NULL, NULL, NULL, 1253 }, 1254 .msr = { 1255 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1256 } 1257 }, 1258 1259 [FEAT_VMX_EXIT_CTLS] = { 1260 .type = MSR_FEATURE_WORD, 1261 /* 1262 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1263 * the LM CPUID bit. 1264 */ 1265 .feat_names = { 1266 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1269 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1270 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1271 "vmx-exit-save-efer", "vmx-exit-load-efer", 1272 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1273 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1274 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1275 }, 1276 .msr = { 1277 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1278 } 1279 }, 1280 1281 [FEAT_VMX_ENTRY_CTLS] = { 1282 .type = MSR_FEATURE_WORD, 1283 .feat_names = { 1284 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1287 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1288 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1289 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1290 NULL, NULL, NULL, NULL, 1291 NULL, NULL, NULL, NULL, 1292 }, 1293 .msr = { 1294 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1295 } 1296 }, 1297 1298 [FEAT_VMX_MISC] = { 1299 .type = MSR_FEATURE_WORD, 1300 .feat_names = { 1301 NULL, NULL, NULL, NULL, 1302 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1303 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 NULL, NULL, NULL, NULL, 1307 NULL, NULL, NULL, NULL, 1308 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1309 }, 1310 .msr = { 1311 .index = MSR_IA32_VMX_MISC, 1312 } 1313 }, 1314 1315 [FEAT_VMX_EPT_VPID_CAPS] = { 1316 .type = MSR_FEATURE_WORD, 1317 .feat_names = { 1318 "vmx-ept-execonly", NULL, NULL, NULL, 1319 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1320 NULL, NULL, NULL, NULL, 1321 NULL, NULL, NULL, NULL, 1322 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1323 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1324 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1325 NULL, NULL, NULL, NULL, 1326 "vmx-invvpid", NULL, NULL, NULL, 1327 NULL, NULL, NULL, NULL, 1328 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1329 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 NULL, NULL, NULL, NULL, 1334 NULL, NULL, NULL, NULL, 1335 }, 1336 .msr = { 1337 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1338 } 1339 }, 1340 1341 [FEAT_VMX_BASIC] = { 1342 .type = MSR_FEATURE_WORD, 1343 .feat_names = { 1344 [54] = "vmx-ins-outs", 1345 [55] = "vmx-true-ctls", 1346 [56] = "vmx-any-errcode", 1347 }, 1348 .msr = { 1349 .index = MSR_IA32_VMX_BASIC, 1350 }, 1351 /* Just to be safe - we don't support setting the MSEG version field. */ 1352 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1353 }, 1354 1355 [FEAT_VMX_VMFUNC] = { 1356 .type = MSR_FEATURE_WORD, 1357 .feat_names = { 1358 [0] = "vmx-eptp-switching", 1359 }, 1360 .msr = { 1361 .index = MSR_IA32_VMX_VMFUNC, 1362 } 1363 }, 1364 1365 [FEAT_14_0_ECX] = { 1366 .type = CPUID_FEATURE_WORD, 1367 .feat_names = { 1368 NULL, NULL, NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 NULL, NULL, NULL, NULL, 1371 NULL, NULL, NULL, NULL, 1372 NULL, NULL, NULL, NULL, 1373 NULL, NULL, NULL, NULL, 1374 NULL, NULL, NULL, NULL, 1375 NULL, NULL, NULL, "intel-pt-lip", 1376 }, 1377 .cpuid = { 1378 .eax = 0x14, 1379 .needs_ecx = true, .ecx = 0, 1380 .reg = R_ECX, 1381 }, 1382 .tcg_features = TCG_14_0_ECX_FEATURES, 1383 }, 1384 1385 [FEAT_SGX_12_0_EAX] = { 1386 .type = CPUID_FEATURE_WORD, 1387 .feat_names = { 1388 "sgx1", "sgx2", NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, "sgx-edeccssa", 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 NULL, NULL, NULL, NULL, 1396 }, 1397 .cpuid = { 1398 .eax = 0x12, 1399 .needs_ecx = true, .ecx = 0, 1400 .reg = R_EAX, 1401 }, 1402 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1403 }, 1404 1405 [FEAT_SGX_12_0_EBX] = { 1406 .type = CPUID_FEATURE_WORD, 1407 .feat_names = { 1408 "sgx-exinfo" , NULL, NULL, NULL, 1409 NULL, NULL, NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 }, 1417 .cpuid = { 1418 .eax = 0x12, 1419 .needs_ecx = true, .ecx = 0, 1420 .reg = R_EBX, 1421 }, 1422 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1423 }, 1424 1425 [FEAT_SGX_12_1_EAX] = { 1426 .type = CPUID_FEATURE_WORD, 1427 .feat_names = { 1428 NULL, "sgx-debug", "sgx-mode64", NULL, 1429 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1430 NULL, NULL, "sgx-aex-notify", NULL, 1431 NULL, NULL, NULL, NULL, 1432 NULL, NULL, NULL, NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, NULL, NULL, NULL, 1435 NULL, NULL, NULL, NULL, 1436 }, 1437 .cpuid = { 1438 .eax = 0x12, 1439 .needs_ecx = true, .ecx = 1, 1440 .reg = R_EAX, 1441 }, 1442 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1443 }, 1444 }; 1445 1446 typedef struct FeatureMask { 1447 FeatureWord index; 1448 uint64_t mask; 1449 } FeatureMask; 1450 1451 typedef struct FeatureDep { 1452 FeatureMask from, to; 1453 } FeatureDep; 1454 1455 static FeatureDep feature_dependencies[] = { 1456 { 1457 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1458 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1459 }, 1460 { 1461 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1462 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1463 }, 1464 { 1465 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1466 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1467 }, 1468 { 1469 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1470 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1471 }, 1472 { 1473 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1474 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1475 }, 1476 { 1477 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1478 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1479 }, 1480 { 1481 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1482 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1483 }, 1484 { 1485 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1486 .to = { FEAT_VMX_MISC, ~0ull }, 1487 }, 1488 { 1489 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1490 .to = { FEAT_VMX_BASIC, ~0ull }, 1491 }, 1492 { 1493 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1494 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1495 }, 1496 { 1497 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1498 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1499 }, 1500 { 1501 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1502 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1503 }, 1504 { 1505 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1506 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1507 }, 1508 { 1509 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1510 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1511 }, 1512 { 1513 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1514 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1515 }, 1516 { 1517 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1518 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1519 }, 1520 { 1521 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1522 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1523 }, 1524 { 1525 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1526 .to = { FEAT_14_0_ECX, ~0ull }, 1527 }, 1528 { 1529 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1530 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1531 }, 1532 { 1533 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1534 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1535 }, 1536 { 1537 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1538 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1539 }, 1540 { 1541 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1542 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1543 }, 1544 { 1545 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1546 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1547 }, 1548 { 1549 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1550 .to = { FEAT_SVM, ~0ull }, 1551 }, 1552 { 1553 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1554 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1555 }, 1556 }; 1557 1558 typedef struct X86RegisterInfo32 { 1559 /* Name of register */ 1560 const char *name; 1561 /* QAPI enum value register */ 1562 X86CPURegister32 qapi_enum; 1563 } X86RegisterInfo32; 1564 1565 #define REGISTER(reg) \ 1566 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1567 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1568 REGISTER(EAX), 1569 REGISTER(ECX), 1570 REGISTER(EDX), 1571 REGISTER(EBX), 1572 REGISTER(ESP), 1573 REGISTER(EBP), 1574 REGISTER(ESI), 1575 REGISTER(EDI), 1576 }; 1577 #undef REGISTER 1578 1579 /* CPUID feature bits available in XSS */ 1580 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1581 1582 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1583 [XSTATE_FP_BIT] = { 1584 /* x87 FP state component is always enabled if XSAVE is supported */ 1585 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1586 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1587 }, 1588 [XSTATE_SSE_BIT] = { 1589 /* SSE state component is always enabled if XSAVE is supported */ 1590 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1591 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1592 }, 1593 [XSTATE_YMM_BIT] = 1594 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1595 .size = sizeof(XSaveAVX) }, 1596 [XSTATE_BNDREGS_BIT] = 1597 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1598 .size = sizeof(XSaveBNDREG) }, 1599 [XSTATE_BNDCSR_BIT] = 1600 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1601 .size = sizeof(XSaveBNDCSR) }, 1602 [XSTATE_OPMASK_BIT] = 1603 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1604 .size = sizeof(XSaveOpmask) }, 1605 [XSTATE_ZMM_Hi256_BIT] = 1606 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1607 .size = sizeof(XSaveZMM_Hi256) }, 1608 [XSTATE_Hi16_ZMM_BIT] = 1609 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1610 .size = sizeof(XSaveHi16_ZMM) }, 1611 [XSTATE_PKRU_BIT] = 1612 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1613 .size = sizeof(XSavePKRU) }, 1614 [XSTATE_ARCH_LBR_BIT] = { 1615 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1616 .offset = 0 /*supervisor mode component, offset = 0 */, 1617 .size = sizeof(XSavesArchLBR) }, 1618 [XSTATE_XTILE_CFG_BIT] = { 1619 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1620 .size = sizeof(XSaveXTILECFG), 1621 }, 1622 [XSTATE_XTILE_DATA_BIT] = { 1623 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1624 .size = sizeof(XSaveXTILEDATA) 1625 }, 1626 }; 1627 1628 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1629 { 1630 uint64_t ret = x86_ext_save_areas[0].size; 1631 const ExtSaveArea *esa; 1632 uint32_t offset = 0; 1633 int i; 1634 1635 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1636 esa = &x86_ext_save_areas[i]; 1637 if ((mask >> i) & 1) { 1638 offset = compacted ? ret : esa->offset; 1639 ret = MAX(ret, offset + esa->size); 1640 } 1641 } 1642 return ret; 1643 } 1644 1645 static inline bool accel_uses_host_cpuid(void) 1646 { 1647 return kvm_enabled() || hvf_enabled(); 1648 } 1649 1650 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1651 { 1652 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1653 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1654 } 1655 1656 /* Return name of 32-bit register, from a R_* constant */ 1657 static const char *get_register_name_32(unsigned int reg) 1658 { 1659 if (reg >= CPU_NB_REGS32) { 1660 return NULL; 1661 } 1662 return x86_reg_info_32[reg].name; 1663 } 1664 1665 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1666 { 1667 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1668 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1669 } 1670 1671 /* 1672 * Returns the set of feature flags that are supported and migratable by 1673 * QEMU, for a given FeatureWord. 1674 */ 1675 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1676 { 1677 FeatureWordInfo *wi = &feature_word_info[w]; 1678 uint64_t r = 0; 1679 int i; 1680 1681 for (i = 0; i < 64; i++) { 1682 uint64_t f = 1ULL << i; 1683 1684 /* If the feature name is known, it is implicitly considered migratable, 1685 * unless it is explicitly set in unmigratable_flags */ 1686 if ((wi->migratable_flags & f) || 1687 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1688 r |= f; 1689 } 1690 } 1691 return r; 1692 } 1693 1694 void host_cpuid(uint32_t function, uint32_t count, 1695 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1696 { 1697 uint32_t vec[4]; 1698 1699 #ifdef __x86_64__ 1700 asm volatile("cpuid" 1701 : "=a"(vec[0]), "=b"(vec[1]), 1702 "=c"(vec[2]), "=d"(vec[3]) 1703 : "0"(function), "c"(count) : "cc"); 1704 #elif defined(__i386__) 1705 asm volatile("pusha \n\t" 1706 "cpuid \n\t" 1707 "mov %%eax, 0(%2) \n\t" 1708 "mov %%ebx, 4(%2) \n\t" 1709 "mov %%ecx, 8(%2) \n\t" 1710 "mov %%edx, 12(%2) \n\t" 1711 "popa" 1712 : : "a"(function), "c"(count), "S"(vec) 1713 : "memory", "cc"); 1714 #else 1715 abort(); 1716 #endif 1717 1718 if (eax) 1719 *eax = vec[0]; 1720 if (ebx) 1721 *ebx = vec[1]; 1722 if (ecx) 1723 *ecx = vec[2]; 1724 if (edx) 1725 *edx = vec[3]; 1726 } 1727 1728 /* CPU class name definitions: */ 1729 1730 /* Return type name for a given CPU model name 1731 * Caller is responsible for freeing the returned string. 1732 */ 1733 static char *x86_cpu_type_name(const char *model_name) 1734 { 1735 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1736 } 1737 1738 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1739 { 1740 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1741 return object_class_by_name(typename); 1742 } 1743 1744 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1745 { 1746 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1747 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1748 return cpu_model_from_type(class_name); 1749 } 1750 1751 typedef struct X86CPUVersionDefinition { 1752 X86CPUVersion version; 1753 const char *alias; 1754 const char *note; 1755 PropValue *props; 1756 const CPUCaches *const cache_info; 1757 } X86CPUVersionDefinition; 1758 1759 /* Base definition for a CPU model */ 1760 typedef struct X86CPUDefinition { 1761 const char *name; 1762 uint32_t level; 1763 uint32_t xlevel; 1764 /* vendor is zero-terminated, 12 character ASCII string */ 1765 char vendor[CPUID_VENDOR_SZ + 1]; 1766 int family; 1767 int model; 1768 int stepping; 1769 FeatureWordArray features; 1770 const char *model_id; 1771 const CPUCaches *const cache_info; 1772 /* 1773 * Definitions for alternative versions of CPU model. 1774 * List is terminated by item with version == 0. 1775 * If NULL, version 1 will be registered automatically. 1776 */ 1777 const X86CPUVersionDefinition *versions; 1778 const char *deprecation_note; 1779 } X86CPUDefinition; 1780 1781 /* Reference to a specific CPU model version */ 1782 struct X86CPUModel { 1783 /* Base CPU definition */ 1784 const X86CPUDefinition *cpudef; 1785 /* CPU model version */ 1786 X86CPUVersion version; 1787 const char *note; 1788 /* 1789 * If true, this is an alias CPU model. 1790 * This matters only for "-cpu help" and query-cpu-definitions 1791 */ 1792 bool is_alias; 1793 }; 1794 1795 /* Get full model name for CPU version */ 1796 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1797 X86CPUVersion version) 1798 { 1799 assert(version > 0); 1800 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1801 } 1802 1803 static const X86CPUVersionDefinition * 1804 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1805 { 1806 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1807 static const X86CPUVersionDefinition default_version_list[] = { 1808 { 1 }, 1809 { /* end of list */ } 1810 }; 1811 1812 return def->versions ?: default_version_list; 1813 } 1814 1815 static const CPUCaches epyc_cache_info = { 1816 .l1d_cache = &(CPUCacheInfo) { 1817 .type = DATA_CACHE, 1818 .level = 1, 1819 .size = 32 * KiB, 1820 .line_size = 64, 1821 .associativity = 8, 1822 .partitions = 1, 1823 .sets = 64, 1824 .lines_per_tag = 1, 1825 .self_init = 1, 1826 .no_invd_sharing = true, 1827 }, 1828 .l1i_cache = &(CPUCacheInfo) { 1829 .type = INSTRUCTION_CACHE, 1830 .level = 1, 1831 .size = 64 * KiB, 1832 .line_size = 64, 1833 .associativity = 4, 1834 .partitions = 1, 1835 .sets = 256, 1836 .lines_per_tag = 1, 1837 .self_init = 1, 1838 .no_invd_sharing = true, 1839 }, 1840 .l2_cache = &(CPUCacheInfo) { 1841 .type = UNIFIED_CACHE, 1842 .level = 2, 1843 .size = 512 * KiB, 1844 .line_size = 64, 1845 .associativity = 8, 1846 .partitions = 1, 1847 .sets = 1024, 1848 .lines_per_tag = 1, 1849 }, 1850 .l3_cache = &(CPUCacheInfo) { 1851 .type = UNIFIED_CACHE, 1852 .level = 3, 1853 .size = 8 * MiB, 1854 .line_size = 64, 1855 .associativity = 16, 1856 .partitions = 1, 1857 .sets = 8192, 1858 .lines_per_tag = 1, 1859 .self_init = true, 1860 .inclusive = true, 1861 .complex_indexing = true, 1862 }, 1863 }; 1864 1865 static CPUCaches epyc_v4_cache_info = { 1866 .l1d_cache = &(CPUCacheInfo) { 1867 .type = DATA_CACHE, 1868 .level = 1, 1869 .size = 32 * KiB, 1870 .line_size = 64, 1871 .associativity = 8, 1872 .partitions = 1, 1873 .sets = 64, 1874 .lines_per_tag = 1, 1875 .self_init = 1, 1876 .no_invd_sharing = true, 1877 }, 1878 .l1i_cache = &(CPUCacheInfo) { 1879 .type = INSTRUCTION_CACHE, 1880 .level = 1, 1881 .size = 64 * KiB, 1882 .line_size = 64, 1883 .associativity = 4, 1884 .partitions = 1, 1885 .sets = 256, 1886 .lines_per_tag = 1, 1887 .self_init = 1, 1888 .no_invd_sharing = true, 1889 }, 1890 .l2_cache = &(CPUCacheInfo) { 1891 .type = UNIFIED_CACHE, 1892 .level = 2, 1893 .size = 512 * KiB, 1894 .line_size = 64, 1895 .associativity = 8, 1896 .partitions = 1, 1897 .sets = 1024, 1898 .lines_per_tag = 1, 1899 }, 1900 .l3_cache = &(CPUCacheInfo) { 1901 .type = UNIFIED_CACHE, 1902 .level = 3, 1903 .size = 8 * MiB, 1904 .line_size = 64, 1905 .associativity = 16, 1906 .partitions = 1, 1907 .sets = 8192, 1908 .lines_per_tag = 1, 1909 .self_init = true, 1910 .inclusive = true, 1911 .complex_indexing = false, 1912 }, 1913 }; 1914 1915 static const CPUCaches epyc_rome_cache_info = { 1916 .l1d_cache = &(CPUCacheInfo) { 1917 .type = DATA_CACHE, 1918 .level = 1, 1919 .size = 32 * KiB, 1920 .line_size = 64, 1921 .associativity = 8, 1922 .partitions = 1, 1923 .sets = 64, 1924 .lines_per_tag = 1, 1925 .self_init = 1, 1926 .no_invd_sharing = true, 1927 }, 1928 .l1i_cache = &(CPUCacheInfo) { 1929 .type = INSTRUCTION_CACHE, 1930 .level = 1, 1931 .size = 32 * KiB, 1932 .line_size = 64, 1933 .associativity = 8, 1934 .partitions = 1, 1935 .sets = 64, 1936 .lines_per_tag = 1, 1937 .self_init = 1, 1938 .no_invd_sharing = true, 1939 }, 1940 .l2_cache = &(CPUCacheInfo) { 1941 .type = UNIFIED_CACHE, 1942 .level = 2, 1943 .size = 512 * KiB, 1944 .line_size = 64, 1945 .associativity = 8, 1946 .partitions = 1, 1947 .sets = 1024, 1948 .lines_per_tag = 1, 1949 }, 1950 .l3_cache = &(CPUCacheInfo) { 1951 .type = UNIFIED_CACHE, 1952 .level = 3, 1953 .size = 16 * MiB, 1954 .line_size = 64, 1955 .associativity = 16, 1956 .partitions = 1, 1957 .sets = 16384, 1958 .lines_per_tag = 1, 1959 .self_init = true, 1960 .inclusive = true, 1961 .complex_indexing = true, 1962 }, 1963 }; 1964 1965 static const CPUCaches epyc_rome_v3_cache_info = { 1966 .l1d_cache = &(CPUCacheInfo) { 1967 .type = DATA_CACHE, 1968 .level = 1, 1969 .size = 32 * KiB, 1970 .line_size = 64, 1971 .associativity = 8, 1972 .partitions = 1, 1973 .sets = 64, 1974 .lines_per_tag = 1, 1975 .self_init = 1, 1976 .no_invd_sharing = true, 1977 }, 1978 .l1i_cache = &(CPUCacheInfo) { 1979 .type = INSTRUCTION_CACHE, 1980 .level = 1, 1981 .size = 32 * KiB, 1982 .line_size = 64, 1983 .associativity = 8, 1984 .partitions = 1, 1985 .sets = 64, 1986 .lines_per_tag = 1, 1987 .self_init = 1, 1988 .no_invd_sharing = true, 1989 }, 1990 .l2_cache = &(CPUCacheInfo) { 1991 .type = UNIFIED_CACHE, 1992 .level = 2, 1993 .size = 512 * KiB, 1994 .line_size = 64, 1995 .associativity = 8, 1996 .partitions = 1, 1997 .sets = 1024, 1998 .lines_per_tag = 1, 1999 }, 2000 .l3_cache = &(CPUCacheInfo) { 2001 .type = UNIFIED_CACHE, 2002 .level = 3, 2003 .size = 16 * MiB, 2004 .line_size = 64, 2005 .associativity = 16, 2006 .partitions = 1, 2007 .sets = 16384, 2008 .lines_per_tag = 1, 2009 .self_init = true, 2010 .inclusive = true, 2011 .complex_indexing = false, 2012 }, 2013 }; 2014 2015 static const CPUCaches epyc_milan_cache_info = { 2016 .l1d_cache = &(CPUCacheInfo) { 2017 .type = DATA_CACHE, 2018 .level = 1, 2019 .size = 32 * KiB, 2020 .line_size = 64, 2021 .associativity = 8, 2022 .partitions = 1, 2023 .sets = 64, 2024 .lines_per_tag = 1, 2025 .self_init = 1, 2026 .no_invd_sharing = true, 2027 }, 2028 .l1i_cache = &(CPUCacheInfo) { 2029 .type = INSTRUCTION_CACHE, 2030 .level = 1, 2031 .size = 32 * KiB, 2032 .line_size = 64, 2033 .associativity = 8, 2034 .partitions = 1, 2035 .sets = 64, 2036 .lines_per_tag = 1, 2037 .self_init = 1, 2038 .no_invd_sharing = true, 2039 }, 2040 .l2_cache = &(CPUCacheInfo) { 2041 .type = UNIFIED_CACHE, 2042 .level = 2, 2043 .size = 512 * KiB, 2044 .line_size = 64, 2045 .associativity = 8, 2046 .partitions = 1, 2047 .sets = 1024, 2048 .lines_per_tag = 1, 2049 }, 2050 .l3_cache = &(CPUCacheInfo) { 2051 .type = UNIFIED_CACHE, 2052 .level = 3, 2053 .size = 32 * MiB, 2054 .line_size = 64, 2055 .associativity = 16, 2056 .partitions = 1, 2057 .sets = 32768, 2058 .lines_per_tag = 1, 2059 .self_init = true, 2060 .inclusive = true, 2061 .complex_indexing = true, 2062 }, 2063 }; 2064 2065 static const CPUCaches epyc_milan_v2_cache_info = { 2066 .l1d_cache = &(CPUCacheInfo) { 2067 .type = DATA_CACHE, 2068 .level = 1, 2069 .size = 32 * KiB, 2070 .line_size = 64, 2071 .associativity = 8, 2072 .partitions = 1, 2073 .sets = 64, 2074 .lines_per_tag = 1, 2075 .self_init = 1, 2076 .no_invd_sharing = true, 2077 }, 2078 .l1i_cache = &(CPUCacheInfo) { 2079 .type = INSTRUCTION_CACHE, 2080 .level = 1, 2081 .size = 32 * KiB, 2082 .line_size = 64, 2083 .associativity = 8, 2084 .partitions = 1, 2085 .sets = 64, 2086 .lines_per_tag = 1, 2087 .self_init = 1, 2088 .no_invd_sharing = true, 2089 }, 2090 .l2_cache = &(CPUCacheInfo) { 2091 .type = UNIFIED_CACHE, 2092 .level = 2, 2093 .size = 512 * KiB, 2094 .line_size = 64, 2095 .associativity = 8, 2096 .partitions = 1, 2097 .sets = 1024, 2098 .lines_per_tag = 1, 2099 }, 2100 .l3_cache = &(CPUCacheInfo) { 2101 .type = UNIFIED_CACHE, 2102 .level = 3, 2103 .size = 32 * MiB, 2104 .line_size = 64, 2105 .associativity = 16, 2106 .partitions = 1, 2107 .sets = 32768, 2108 .lines_per_tag = 1, 2109 .self_init = true, 2110 .inclusive = true, 2111 .complex_indexing = false, 2112 }, 2113 }; 2114 2115 static const CPUCaches epyc_genoa_cache_info = { 2116 .l1d_cache = &(CPUCacheInfo) { 2117 .type = DATA_CACHE, 2118 .level = 1, 2119 .size = 32 * KiB, 2120 .line_size = 64, 2121 .associativity = 8, 2122 .partitions = 1, 2123 .sets = 64, 2124 .lines_per_tag = 1, 2125 .self_init = 1, 2126 .no_invd_sharing = true, 2127 }, 2128 .l1i_cache = &(CPUCacheInfo) { 2129 .type = INSTRUCTION_CACHE, 2130 .level = 1, 2131 .size = 32 * KiB, 2132 .line_size = 64, 2133 .associativity = 8, 2134 .partitions = 1, 2135 .sets = 64, 2136 .lines_per_tag = 1, 2137 .self_init = 1, 2138 .no_invd_sharing = true, 2139 }, 2140 .l2_cache = &(CPUCacheInfo) { 2141 .type = UNIFIED_CACHE, 2142 .level = 2, 2143 .size = 1 * MiB, 2144 .line_size = 64, 2145 .associativity = 8, 2146 .partitions = 1, 2147 .sets = 2048, 2148 .lines_per_tag = 1, 2149 }, 2150 .l3_cache = &(CPUCacheInfo) { 2151 .type = UNIFIED_CACHE, 2152 .level = 3, 2153 .size = 32 * MiB, 2154 .line_size = 64, 2155 .associativity = 16, 2156 .partitions = 1, 2157 .sets = 32768, 2158 .lines_per_tag = 1, 2159 .self_init = true, 2160 .inclusive = true, 2161 .complex_indexing = false, 2162 }, 2163 }; 2164 2165 /* The following VMX features are not supported by KVM and are left out in the 2166 * CPU definitions: 2167 * 2168 * Dual-monitor support (all processors) 2169 * Entry to SMM 2170 * Deactivate dual-monitor treatment 2171 * Number of CR3-target values 2172 * Shutdown activity state 2173 * Wait-for-SIPI activity state 2174 * PAUSE-loop exiting (Westmere and newer) 2175 * EPT-violation #VE (Broadwell and newer) 2176 * Inject event with insn length=0 (Skylake and newer) 2177 * Conceal non-root operation from PT 2178 * Conceal VM exits from PT 2179 * Conceal VM entries from PT 2180 * Enable ENCLS exiting 2181 * Mode-based execute control (XS/XU) 2182 * TSC scaling (Skylake Server and newer) 2183 * GPA translation for PT (IceLake and newer) 2184 * User wait and pause 2185 * ENCLV exiting 2186 * Load IA32_RTIT_CTL 2187 * Clear IA32_RTIT_CTL 2188 * Advanced VM-exit information for EPT violations 2189 * Sub-page write permissions 2190 * PT in VMX operation 2191 */ 2192 2193 static const X86CPUDefinition builtin_x86_defs[] = { 2194 { 2195 .name = "qemu64", 2196 .level = 0xd, 2197 .vendor = CPUID_VENDOR_AMD, 2198 .family = 15, 2199 .model = 107, 2200 .stepping = 1, 2201 .features[FEAT_1_EDX] = 2202 PPRO_FEATURES | 2203 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2204 CPUID_PSE36, 2205 .features[FEAT_1_ECX] = 2206 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2207 .features[FEAT_8000_0001_EDX] = 2208 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2209 .features[FEAT_8000_0001_ECX] = 2210 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2211 .xlevel = 0x8000000A, 2212 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2213 }, 2214 { 2215 .name = "phenom", 2216 .level = 5, 2217 .vendor = CPUID_VENDOR_AMD, 2218 .family = 16, 2219 .model = 2, 2220 .stepping = 3, 2221 /* Missing: CPUID_HT */ 2222 .features[FEAT_1_EDX] = 2223 PPRO_FEATURES | 2224 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2225 CPUID_PSE36 | CPUID_VME, 2226 .features[FEAT_1_ECX] = 2227 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2228 CPUID_EXT_POPCNT, 2229 .features[FEAT_8000_0001_EDX] = 2230 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2231 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2232 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2233 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2234 CPUID_EXT3_CR8LEG, 2235 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2236 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2237 .features[FEAT_8000_0001_ECX] = 2238 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2239 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2240 /* Missing: CPUID_SVM_LBRV */ 2241 .features[FEAT_SVM] = 2242 CPUID_SVM_NPT, 2243 .xlevel = 0x8000001A, 2244 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2245 }, 2246 { 2247 .name = "core2duo", 2248 .level = 10, 2249 .vendor = CPUID_VENDOR_INTEL, 2250 .family = 6, 2251 .model = 15, 2252 .stepping = 11, 2253 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2254 .features[FEAT_1_EDX] = 2255 PPRO_FEATURES | 2256 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2257 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2258 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2259 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2260 .features[FEAT_1_ECX] = 2261 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2262 CPUID_EXT_CX16, 2263 .features[FEAT_8000_0001_EDX] = 2264 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2265 .features[FEAT_8000_0001_ECX] = 2266 CPUID_EXT3_LAHF_LM, 2267 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2268 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2269 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2270 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2271 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2272 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2273 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2274 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2275 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2276 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2277 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2278 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2279 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2280 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2281 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2282 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2283 .features[FEAT_VMX_SECONDARY_CTLS] = 2284 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2285 .xlevel = 0x80000008, 2286 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2287 }, 2288 { 2289 .name = "kvm64", 2290 .level = 0xd, 2291 .vendor = CPUID_VENDOR_INTEL, 2292 .family = 15, 2293 .model = 6, 2294 .stepping = 1, 2295 /* Missing: CPUID_HT */ 2296 .features[FEAT_1_EDX] = 2297 PPRO_FEATURES | CPUID_VME | 2298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2299 CPUID_PSE36, 2300 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2301 .features[FEAT_1_ECX] = 2302 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2303 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2304 .features[FEAT_8000_0001_EDX] = 2305 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2306 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2307 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2308 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2309 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2310 .features[FEAT_8000_0001_ECX] = 2311 0, 2312 /* VMX features from Cedar Mill/Prescott */ 2313 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2314 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2315 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2316 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2317 VMX_PIN_BASED_NMI_EXITING, 2318 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2319 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2320 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2321 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2322 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2323 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2324 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2325 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2326 .xlevel = 0x80000008, 2327 .model_id = "Common KVM processor" 2328 }, 2329 { 2330 .name = "qemu32", 2331 .level = 4, 2332 .vendor = CPUID_VENDOR_INTEL, 2333 .family = 6, 2334 .model = 6, 2335 .stepping = 3, 2336 .features[FEAT_1_EDX] = 2337 PPRO_FEATURES, 2338 .features[FEAT_1_ECX] = 2339 CPUID_EXT_SSE3, 2340 .xlevel = 0x80000004, 2341 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2342 }, 2343 { 2344 .name = "kvm32", 2345 .level = 5, 2346 .vendor = CPUID_VENDOR_INTEL, 2347 .family = 15, 2348 .model = 6, 2349 .stepping = 1, 2350 .features[FEAT_1_EDX] = 2351 PPRO_FEATURES | CPUID_VME | 2352 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2353 .features[FEAT_1_ECX] = 2354 CPUID_EXT_SSE3, 2355 .features[FEAT_8000_0001_ECX] = 2356 0, 2357 /* VMX features from Yonah */ 2358 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2359 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2360 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2361 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2362 VMX_PIN_BASED_NMI_EXITING, 2363 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2364 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2365 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2366 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2367 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2368 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2369 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2370 .xlevel = 0x80000008, 2371 .model_id = "Common 32-bit KVM processor" 2372 }, 2373 { 2374 .name = "coreduo", 2375 .level = 10, 2376 .vendor = CPUID_VENDOR_INTEL, 2377 .family = 6, 2378 .model = 14, 2379 .stepping = 8, 2380 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2381 .features[FEAT_1_EDX] = 2382 PPRO_FEATURES | CPUID_VME | 2383 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2384 CPUID_SS, 2385 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2386 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2387 .features[FEAT_1_ECX] = 2388 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2389 .features[FEAT_8000_0001_EDX] = 2390 CPUID_EXT2_NX, 2391 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2392 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2393 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2394 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2395 VMX_PIN_BASED_NMI_EXITING, 2396 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2397 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2398 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2399 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2400 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2401 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2402 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2403 .xlevel = 0x80000008, 2404 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2405 }, 2406 { 2407 .name = "486", 2408 .level = 1, 2409 .vendor = CPUID_VENDOR_INTEL, 2410 .family = 4, 2411 .model = 8, 2412 .stepping = 0, 2413 .features[FEAT_1_EDX] = 2414 I486_FEATURES, 2415 .xlevel = 0, 2416 .model_id = "", 2417 }, 2418 { 2419 .name = "pentium", 2420 .level = 1, 2421 .vendor = CPUID_VENDOR_INTEL, 2422 .family = 5, 2423 .model = 4, 2424 .stepping = 3, 2425 .features[FEAT_1_EDX] = 2426 PENTIUM_FEATURES, 2427 .xlevel = 0, 2428 .model_id = "", 2429 }, 2430 { 2431 .name = "pentium2", 2432 .level = 2, 2433 .vendor = CPUID_VENDOR_INTEL, 2434 .family = 6, 2435 .model = 5, 2436 .stepping = 2, 2437 .features[FEAT_1_EDX] = 2438 PENTIUM2_FEATURES, 2439 .xlevel = 0, 2440 .model_id = "", 2441 }, 2442 { 2443 .name = "pentium3", 2444 .level = 3, 2445 .vendor = CPUID_VENDOR_INTEL, 2446 .family = 6, 2447 .model = 7, 2448 .stepping = 3, 2449 .features[FEAT_1_EDX] = 2450 PENTIUM3_FEATURES, 2451 .xlevel = 0, 2452 .model_id = "", 2453 }, 2454 { 2455 .name = "athlon", 2456 .level = 2, 2457 .vendor = CPUID_VENDOR_AMD, 2458 .family = 6, 2459 .model = 2, 2460 .stepping = 3, 2461 .features[FEAT_1_EDX] = 2462 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2463 CPUID_MCA, 2464 .features[FEAT_8000_0001_EDX] = 2465 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2466 .xlevel = 0x80000008, 2467 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2468 }, 2469 { 2470 .name = "n270", 2471 .level = 10, 2472 .vendor = CPUID_VENDOR_INTEL, 2473 .family = 6, 2474 .model = 28, 2475 .stepping = 2, 2476 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2477 .features[FEAT_1_EDX] = 2478 PPRO_FEATURES | 2479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2480 CPUID_ACPI | CPUID_SS, 2481 /* Some CPUs got no CPUID_SEP */ 2482 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2483 * CPUID_EXT_XTPR */ 2484 .features[FEAT_1_ECX] = 2485 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2486 CPUID_EXT_MOVBE, 2487 .features[FEAT_8000_0001_EDX] = 2488 CPUID_EXT2_NX, 2489 .features[FEAT_8000_0001_ECX] = 2490 CPUID_EXT3_LAHF_LM, 2491 .xlevel = 0x80000008, 2492 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2493 }, 2494 { 2495 .name = "Conroe", 2496 .level = 10, 2497 .vendor = CPUID_VENDOR_INTEL, 2498 .family = 6, 2499 .model = 15, 2500 .stepping = 3, 2501 .features[FEAT_1_EDX] = 2502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2506 CPUID_DE | CPUID_FP87, 2507 .features[FEAT_1_ECX] = 2508 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2509 .features[FEAT_8000_0001_EDX] = 2510 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2511 .features[FEAT_8000_0001_ECX] = 2512 CPUID_EXT3_LAHF_LM, 2513 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2514 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2515 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2516 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2517 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2518 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2519 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2520 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2521 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2522 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2523 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2524 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2525 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2526 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2527 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2528 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2529 .features[FEAT_VMX_SECONDARY_CTLS] = 2530 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2531 .xlevel = 0x80000008, 2532 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2533 }, 2534 { 2535 .name = "Penryn", 2536 .level = 10, 2537 .vendor = CPUID_VENDOR_INTEL, 2538 .family = 6, 2539 .model = 23, 2540 .stepping = 3, 2541 .features[FEAT_1_EDX] = 2542 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2543 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2544 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2545 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2546 CPUID_DE | CPUID_FP87, 2547 .features[FEAT_1_ECX] = 2548 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2549 CPUID_EXT_SSE3, 2550 .features[FEAT_8000_0001_EDX] = 2551 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2552 .features[FEAT_8000_0001_ECX] = 2553 CPUID_EXT3_LAHF_LM, 2554 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2555 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2556 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2557 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2558 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2559 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2560 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2561 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2562 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2563 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2564 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2565 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2566 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2567 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2568 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2569 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2570 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2571 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2572 .features[FEAT_VMX_SECONDARY_CTLS] = 2573 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2574 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2575 .xlevel = 0x80000008, 2576 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2577 }, 2578 { 2579 .name = "Nehalem", 2580 .level = 11, 2581 .vendor = CPUID_VENDOR_INTEL, 2582 .family = 6, 2583 .model = 26, 2584 .stepping = 3, 2585 .features[FEAT_1_EDX] = 2586 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2587 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2588 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2589 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2590 CPUID_DE | CPUID_FP87, 2591 .features[FEAT_1_ECX] = 2592 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2593 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2594 .features[FEAT_8000_0001_EDX] = 2595 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2596 .features[FEAT_8000_0001_ECX] = 2597 CPUID_EXT3_LAHF_LM, 2598 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2599 MSR_VMX_BASIC_TRUE_CTLS, 2600 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2601 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2602 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2603 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2604 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2605 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2606 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2607 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2608 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2609 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2610 .features[FEAT_VMX_EXIT_CTLS] = 2611 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2612 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2613 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2614 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2615 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2616 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2617 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2618 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2619 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2620 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2621 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2622 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2623 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2624 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2625 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2626 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2627 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2628 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2629 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2630 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2631 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2632 .features[FEAT_VMX_SECONDARY_CTLS] = 2633 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2634 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2635 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2636 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2637 VMX_SECONDARY_EXEC_ENABLE_VPID, 2638 .xlevel = 0x80000008, 2639 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2640 .versions = (X86CPUVersionDefinition[]) { 2641 { .version = 1 }, 2642 { 2643 .version = 2, 2644 .alias = "Nehalem-IBRS", 2645 .props = (PropValue[]) { 2646 { "spec-ctrl", "on" }, 2647 { "model-id", 2648 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2649 { /* end of list */ } 2650 } 2651 }, 2652 { /* end of list */ } 2653 } 2654 }, 2655 { 2656 .name = "Westmere", 2657 .level = 11, 2658 .vendor = CPUID_VENDOR_INTEL, 2659 .family = 6, 2660 .model = 44, 2661 .stepping = 1, 2662 .features[FEAT_1_EDX] = 2663 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2664 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2665 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2666 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2667 CPUID_DE | CPUID_FP87, 2668 .features[FEAT_1_ECX] = 2669 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2670 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2671 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2672 .features[FEAT_8000_0001_EDX] = 2673 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2674 .features[FEAT_8000_0001_ECX] = 2675 CPUID_EXT3_LAHF_LM, 2676 .features[FEAT_6_EAX] = 2677 CPUID_6_EAX_ARAT, 2678 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2679 MSR_VMX_BASIC_TRUE_CTLS, 2680 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2681 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2682 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2683 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2684 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2685 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2686 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2687 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2688 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2689 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2690 .features[FEAT_VMX_EXIT_CTLS] = 2691 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2692 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2693 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2694 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2695 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2696 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2697 MSR_VMX_MISC_STORE_LMA, 2698 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2699 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2700 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2701 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2702 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2703 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2704 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2705 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2706 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2707 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2708 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2709 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2710 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2711 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2712 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2713 .features[FEAT_VMX_SECONDARY_CTLS] = 2714 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2715 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2716 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2717 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2718 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2719 .xlevel = 0x80000008, 2720 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2721 .versions = (X86CPUVersionDefinition[]) { 2722 { .version = 1 }, 2723 { 2724 .version = 2, 2725 .alias = "Westmere-IBRS", 2726 .props = (PropValue[]) { 2727 { "spec-ctrl", "on" }, 2728 { "model-id", 2729 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2730 { /* end of list */ } 2731 } 2732 }, 2733 { /* end of list */ } 2734 } 2735 }, 2736 { 2737 .name = "SandyBridge", 2738 .level = 0xd, 2739 .vendor = CPUID_VENDOR_INTEL, 2740 .family = 6, 2741 .model = 42, 2742 .stepping = 1, 2743 .features[FEAT_1_EDX] = 2744 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2748 CPUID_DE | CPUID_FP87, 2749 .features[FEAT_1_ECX] = 2750 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2751 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2752 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2753 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2754 CPUID_EXT_SSE3, 2755 .features[FEAT_8000_0001_EDX] = 2756 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2757 CPUID_EXT2_SYSCALL, 2758 .features[FEAT_8000_0001_ECX] = 2759 CPUID_EXT3_LAHF_LM, 2760 .features[FEAT_XSAVE] = 2761 CPUID_XSAVE_XSAVEOPT, 2762 .features[FEAT_6_EAX] = 2763 CPUID_6_EAX_ARAT, 2764 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2765 MSR_VMX_BASIC_TRUE_CTLS, 2766 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2767 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2768 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2769 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2770 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2771 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2772 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2773 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2774 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2775 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2776 .features[FEAT_VMX_EXIT_CTLS] = 2777 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2778 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2779 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2780 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2781 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2782 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2783 MSR_VMX_MISC_STORE_LMA, 2784 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2785 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2786 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2787 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2788 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2789 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2790 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2791 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2792 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2793 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2794 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2795 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2796 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2797 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2798 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2799 .features[FEAT_VMX_SECONDARY_CTLS] = 2800 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2801 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2802 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2803 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2804 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2805 .xlevel = 0x80000008, 2806 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2807 .versions = (X86CPUVersionDefinition[]) { 2808 { .version = 1 }, 2809 { 2810 .version = 2, 2811 .alias = "SandyBridge-IBRS", 2812 .props = (PropValue[]) { 2813 { "spec-ctrl", "on" }, 2814 { "model-id", 2815 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2816 { /* end of list */ } 2817 } 2818 }, 2819 { /* end of list */ } 2820 } 2821 }, 2822 { 2823 .name = "IvyBridge", 2824 .level = 0xd, 2825 .vendor = CPUID_VENDOR_INTEL, 2826 .family = 6, 2827 .model = 58, 2828 .stepping = 9, 2829 .features[FEAT_1_EDX] = 2830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2834 CPUID_DE | CPUID_FP87, 2835 .features[FEAT_1_ECX] = 2836 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2837 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2838 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2839 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2840 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2841 .features[FEAT_7_0_EBX] = 2842 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2843 CPUID_7_0_EBX_ERMS, 2844 .features[FEAT_8000_0001_EDX] = 2845 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2846 CPUID_EXT2_SYSCALL, 2847 .features[FEAT_8000_0001_ECX] = 2848 CPUID_EXT3_LAHF_LM, 2849 .features[FEAT_XSAVE] = 2850 CPUID_XSAVE_XSAVEOPT, 2851 .features[FEAT_6_EAX] = 2852 CPUID_6_EAX_ARAT, 2853 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2854 MSR_VMX_BASIC_TRUE_CTLS, 2855 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2856 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2857 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2858 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2859 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2860 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2861 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2862 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2863 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2864 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2865 .features[FEAT_VMX_EXIT_CTLS] = 2866 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2867 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2868 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2869 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2870 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2871 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2872 MSR_VMX_MISC_STORE_LMA, 2873 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2874 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2875 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2876 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2877 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2878 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2879 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2880 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2881 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2882 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2883 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2884 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2885 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2886 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2887 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2888 .features[FEAT_VMX_SECONDARY_CTLS] = 2889 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2890 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2891 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2892 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2893 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2894 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2895 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2896 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2897 .xlevel = 0x80000008, 2898 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2899 .versions = (X86CPUVersionDefinition[]) { 2900 { .version = 1 }, 2901 { 2902 .version = 2, 2903 .alias = "IvyBridge-IBRS", 2904 .props = (PropValue[]) { 2905 { "spec-ctrl", "on" }, 2906 { "model-id", 2907 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2908 { /* end of list */ } 2909 } 2910 }, 2911 { /* end of list */ } 2912 } 2913 }, 2914 { 2915 .name = "Haswell", 2916 .level = 0xd, 2917 .vendor = CPUID_VENDOR_INTEL, 2918 .family = 6, 2919 .model = 60, 2920 .stepping = 4, 2921 .features[FEAT_1_EDX] = 2922 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2923 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2924 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2925 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2926 CPUID_DE | CPUID_FP87, 2927 .features[FEAT_1_ECX] = 2928 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2929 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2930 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2931 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2932 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2933 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2934 .features[FEAT_8000_0001_EDX] = 2935 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2936 CPUID_EXT2_SYSCALL, 2937 .features[FEAT_8000_0001_ECX] = 2938 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2939 .features[FEAT_7_0_EBX] = 2940 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2941 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2942 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2943 CPUID_7_0_EBX_RTM, 2944 .features[FEAT_XSAVE] = 2945 CPUID_XSAVE_XSAVEOPT, 2946 .features[FEAT_6_EAX] = 2947 CPUID_6_EAX_ARAT, 2948 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2949 MSR_VMX_BASIC_TRUE_CTLS, 2950 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2951 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2952 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2953 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2954 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2955 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2956 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2957 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2958 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2959 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2960 .features[FEAT_VMX_EXIT_CTLS] = 2961 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2962 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2963 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2964 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2965 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2966 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2967 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2968 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2969 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2970 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2971 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2972 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2973 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2974 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2975 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2976 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2977 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2978 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2979 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2980 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2981 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2982 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2983 .features[FEAT_VMX_SECONDARY_CTLS] = 2984 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2985 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2986 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2987 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2988 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2989 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2990 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2991 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2992 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2993 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2994 .xlevel = 0x80000008, 2995 .model_id = "Intel Core Processor (Haswell)", 2996 .versions = (X86CPUVersionDefinition[]) { 2997 { .version = 1 }, 2998 { 2999 .version = 2, 3000 .alias = "Haswell-noTSX", 3001 .props = (PropValue[]) { 3002 { "hle", "off" }, 3003 { "rtm", "off" }, 3004 { "stepping", "1" }, 3005 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3006 { /* end of list */ } 3007 }, 3008 }, 3009 { 3010 .version = 3, 3011 .alias = "Haswell-IBRS", 3012 .props = (PropValue[]) { 3013 /* Restore TSX features removed by -v2 above */ 3014 { "hle", "on" }, 3015 { "rtm", "on" }, 3016 /* 3017 * Haswell and Haswell-IBRS had stepping=4 in 3018 * QEMU 4.0 and older 3019 */ 3020 { "stepping", "4" }, 3021 { "spec-ctrl", "on" }, 3022 { "model-id", 3023 "Intel Core Processor (Haswell, IBRS)" }, 3024 { /* end of list */ } 3025 } 3026 }, 3027 { 3028 .version = 4, 3029 .alias = "Haswell-noTSX-IBRS", 3030 .props = (PropValue[]) { 3031 { "hle", "off" }, 3032 { "rtm", "off" }, 3033 /* spec-ctrl was already enabled by -v3 above */ 3034 { "stepping", "1" }, 3035 { "model-id", 3036 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3037 { /* end of list */ } 3038 } 3039 }, 3040 { /* end of list */ } 3041 } 3042 }, 3043 { 3044 .name = "Broadwell", 3045 .level = 0xd, 3046 .vendor = CPUID_VENDOR_INTEL, 3047 .family = 6, 3048 .model = 61, 3049 .stepping = 2, 3050 .features[FEAT_1_EDX] = 3051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3055 CPUID_DE | CPUID_FP87, 3056 .features[FEAT_1_ECX] = 3057 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3058 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3059 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3060 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3061 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3062 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3063 .features[FEAT_8000_0001_EDX] = 3064 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3065 CPUID_EXT2_SYSCALL, 3066 .features[FEAT_8000_0001_ECX] = 3067 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3068 .features[FEAT_7_0_EBX] = 3069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3070 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3071 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3072 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3073 CPUID_7_0_EBX_SMAP, 3074 .features[FEAT_XSAVE] = 3075 CPUID_XSAVE_XSAVEOPT, 3076 .features[FEAT_6_EAX] = 3077 CPUID_6_EAX_ARAT, 3078 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3079 MSR_VMX_BASIC_TRUE_CTLS, 3080 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3081 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3082 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3083 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3084 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3085 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3086 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3087 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3088 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3089 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3090 .features[FEAT_VMX_EXIT_CTLS] = 3091 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3092 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3093 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3094 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3095 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3096 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3097 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3098 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3099 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3100 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3101 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3102 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3103 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3104 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3105 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3106 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3107 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3108 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3109 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3110 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3111 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3112 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3113 .features[FEAT_VMX_SECONDARY_CTLS] = 3114 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3115 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3116 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3117 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3118 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3119 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3120 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3121 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3122 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3123 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3124 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3125 .xlevel = 0x80000008, 3126 .model_id = "Intel Core Processor (Broadwell)", 3127 .versions = (X86CPUVersionDefinition[]) { 3128 { .version = 1 }, 3129 { 3130 .version = 2, 3131 .alias = "Broadwell-noTSX", 3132 .props = (PropValue[]) { 3133 { "hle", "off" }, 3134 { "rtm", "off" }, 3135 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3136 { /* end of list */ } 3137 }, 3138 }, 3139 { 3140 .version = 3, 3141 .alias = "Broadwell-IBRS", 3142 .props = (PropValue[]) { 3143 /* Restore TSX features removed by -v2 above */ 3144 { "hle", "on" }, 3145 { "rtm", "on" }, 3146 { "spec-ctrl", "on" }, 3147 { "model-id", 3148 "Intel Core Processor (Broadwell, IBRS)" }, 3149 { /* end of list */ } 3150 } 3151 }, 3152 { 3153 .version = 4, 3154 .alias = "Broadwell-noTSX-IBRS", 3155 .props = (PropValue[]) { 3156 { "hle", "off" }, 3157 { "rtm", "off" }, 3158 /* spec-ctrl was already enabled by -v3 above */ 3159 { "model-id", 3160 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3161 { /* end of list */ } 3162 } 3163 }, 3164 { /* end of list */ } 3165 } 3166 }, 3167 { 3168 .name = "Skylake-Client", 3169 .level = 0xd, 3170 .vendor = CPUID_VENDOR_INTEL, 3171 .family = 6, 3172 .model = 94, 3173 .stepping = 3, 3174 .features[FEAT_1_EDX] = 3175 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3176 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3177 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3178 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3179 CPUID_DE | CPUID_FP87, 3180 .features[FEAT_1_ECX] = 3181 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3182 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3183 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3184 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3185 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3186 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3187 .features[FEAT_8000_0001_EDX] = 3188 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3189 CPUID_EXT2_SYSCALL, 3190 .features[FEAT_8000_0001_ECX] = 3191 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3192 .features[FEAT_7_0_EBX] = 3193 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3194 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3195 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3196 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3197 CPUID_7_0_EBX_SMAP, 3198 /* XSAVES is added in version 4 */ 3199 .features[FEAT_XSAVE] = 3200 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3201 CPUID_XSAVE_XGETBV1, 3202 .features[FEAT_6_EAX] = 3203 CPUID_6_EAX_ARAT, 3204 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3205 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3206 MSR_VMX_BASIC_TRUE_CTLS, 3207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3208 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3209 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3210 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3211 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3212 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3213 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3214 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3217 .features[FEAT_VMX_EXIT_CTLS] = 3218 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3219 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3220 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3221 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3222 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3223 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3224 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3225 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3226 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3227 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3228 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3229 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3230 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3231 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3232 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3233 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3234 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3235 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3236 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3237 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3238 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3239 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3240 .features[FEAT_VMX_SECONDARY_CTLS] = 3241 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3242 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3243 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3244 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3245 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3246 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3247 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3248 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3249 .xlevel = 0x80000008, 3250 .model_id = "Intel Core Processor (Skylake)", 3251 .versions = (X86CPUVersionDefinition[]) { 3252 { .version = 1 }, 3253 { 3254 .version = 2, 3255 .alias = "Skylake-Client-IBRS", 3256 .props = (PropValue[]) { 3257 { "spec-ctrl", "on" }, 3258 { "model-id", 3259 "Intel Core Processor (Skylake, IBRS)" }, 3260 { /* end of list */ } 3261 } 3262 }, 3263 { 3264 .version = 3, 3265 .alias = "Skylake-Client-noTSX-IBRS", 3266 .props = (PropValue[]) { 3267 { "hle", "off" }, 3268 { "rtm", "off" }, 3269 { "model-id", 3270 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3271 { /* end of list */ } 3272 } 3273 }, 3274 { 3275 .version = 4, 3276 .note = "IBRS, XSAVES, no TSX", 3277 .props = (PropValue[]) { 3278 { "xsaves", "on" }, 3279 { "vmx-xsaves", "on" }, 3280 { /* end of list */ } 3281 } 3282 }, 3283 { /* end of list */ } 3284 } 3285 }, 3286 { 3287 .name = "Skylake-Server", 3288 .level = 0xd, 3289 .vendor = CPUID_VENDOR_INTEL, 3290 .family = 6, 3291 .model = 85, 3292 .stepping = 4, 3293 .features[FEAT_1_EDX] = 3294 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3295 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3296 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3297 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3298 CPUID_DE | CPUID_FP87, 3299 .features[FEAT_1_ECX] = 3300 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3301 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3302 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3303 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3304 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3305 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3306 .features[FEAT_8000_0001_EDX] = 3307 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3308 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3309 .features[FEAT_8000_0001_ECX] = 3310 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3311 .features[FEAT_7_0_EBX] = 3312 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3313 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3314 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3315 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3316 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3317 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3318 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3319 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3320 .features[FEAT_7_0_ECX] = 3321 CPUID_7_0_ECX_PKU, 3322 /* XSAVES is added in version 5 */ 3323 .features[FEAT_XSAVE] = 3324 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3325 CPUID_XSAVE_XGETBV1, 3326 .features[FEAT_6_EAX] = 3327 CPUID_6_EAX_ARAT, 3328 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3329 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3330 MSR_VMX_BASIC_TRUE_CTLS, 3331 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3332 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3333 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3334 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3335 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3336 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3337 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3338 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3339 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3340 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3341 .features[FEAT_VMX_EXIT_CTLS] = 3342 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3343 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3344 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3345 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3346 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3347 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3348 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3349 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3350 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3351 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3352 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3353 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3354 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3355 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3356 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3357 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3358 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3359 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3360 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3361 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3362 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3363 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3364 .features[FEAT_VMX_SECONDARY_CTLS] = 3365 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3366 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3367 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3368 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3369 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3370 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3371 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3372 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3373 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3374 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3375 .xlevel = 0x80000008, 3376 .model_id = "Intel Xeon Processor (Skylake)", 3377 .versions = (X86CPUVersionDefinition[]) { 3378 { .version = 1 }, 3379 { 3380 .version = 2, 3381 .alias = "Skylake-Server-IBRS", 3382 .props = (PropValue[]) { 3383 /* clflushopt was not added to Skylake-Server-IBRS */ 3384 /* TODO: add -v3 including clflushopt */ 3385 { "clflushopt", "off" }, 3386 { "spec-ctrl", "on" }, 3387 { "model-id", 3388 "Intel Xeon Processor (Skylake, IBRS)" }, 3389 { /* end of list */ } 3390 } 3391 }, 3392 { 3393 .version = 3, 3394 .alias = "Skylake-Server-noTSX-IBRS", 3395 .props = (PropValue[]) { 3396 { "hle", "off" }, 3397 { "rtm", "off" }, 3398 { "model-id", 3399 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3400 { /* end of list */ } 3401 } 3402 }, 3403 { 3404 .version = 4, 3405 .props = (PropValue[]) { 3406 { "vmx-eptp-switching", "on" }, 3407 { /* end of list */ } 3408 } 3409 }, 3410 { 3411 .version = 5, 3412 .note = "IBRS, XSAVES, EPT switching, no TSX", 3413 .props = (PropValue[]) { 3414 { "xsaves", "on" }, 3415 { "vmx-xsaves", "on" }, 3416 { /* end of list */ } 3417 } 3418 }, 3419 { /* end of list */ } 3420 } 3421 }, 3422 { 3423 .name = "Cascadelake-Server", 3424 .level = 0xd, 3425 .vendor = CPUID_VENDOR_INTEL, 3426 .family = 6, 3427 .model = 85, 3428 .stepping = 6, 3429 .features[FEAT_1_EDX] = 3430 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3431 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3432 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3433 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3434 CPUID_DE | CPUID_FP87, 3435 .features[FEAT_1_ECX] = 3436 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3437 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3438 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3439 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3440 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3441 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3442 .features[FEAT_8000_0001_EDX] = 3443 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3444 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3445 .features[FEAT_8000_0001_ECX] = 3446 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3447 .features[FEAT_7_0_EBX] = 3448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3449 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3450 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3451 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3452 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3453 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3454 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3455 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3456 .features[FEAT_7_0_ECX] = 3457 CPUID_7_0_ECX_PKU | 3458 CPUID_7_0_ECX_AVX512VNNI, 3459 .features[FEAT_7_0_EDX] = 3460 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3461 /* XSAVES is added in version 5 */ 3462 .features[FEAT_XSAVE] = 3463 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3464 CPUID_XSAVE_XGETBV1, 3465 .features[FEAT_6_EAX] = 3466 CPUID_6_EAX_ARAT, 3467 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3468 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3469 MSR_VMX_BASIC_TRUE_CTLS, 3470 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3471 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3472 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3473 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3474 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3475 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3476 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3477 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3478 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3479 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3480 .features[FEAT_VMX_EXIT_CTLS] = 3481 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3482 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3483 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3484 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3485 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3486 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3487 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3488 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3489 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3490 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3491 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3492 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3493 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3494 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3495 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3496 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3497 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3498 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3499 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3500 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3501 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3502 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3503 .features[FEAT_VMX_SECONDARY_CTLS] = 3504 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3505 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3506 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3507 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3508 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3509 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3510 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3511 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3512 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3513 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3514 .xlevel = 0x80000008, 3515 .model_id = "Intel Xeon Processor (Cascadelake)", 3516 .versions = (X86CPUVersionDefinition[]) { 3517 { .version = 1 }, 3518 { .version = 2, 3519 .note = "ARCH_CAPABILITIES", 3520 .props = (PropValue[]) { 3521 { "arch-capabilities", "on" }, 3522 { "rdctl-no", "on" }, 3523 { "ibrs-all", "on" }, 3524 { "skip-l1dfl-vmentry", "on" }, 3525 { "mds-no", "on" }, 3526 { /* end of list */ } 3527 }, 3528 }, 3529 { .version = 3, 3530 .alias = "Cascadelake-Server-noTSX", 3531 .note = "ARCH_CAPABILITIES, no TSX", 3532 .props = (PropValue[]) { 3533 { "hle", "off" }, 3534 { "rtm", "off" }, 3535 { /* end of list */ } 3536 }, 3537 }, 3538 { .version = 4, 3539 .note = "ARCH_CAPABILITIES, no TSX", 3540 .props = (PropValue[]) { 3541 { "vmx-eptp-switching", "on" }, 3542 { /* end of list */ } 3543 }, 3544 }, 3545 { .version = 5, 3546 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3547 .props = (PropValue[]) { 3548 { "xsaves", "on" }, 3549 { "vmx-xsaves", "on" }, 3550 { /* end of list */ } 3551 }, 3552 }, 3553 { /* end of list */ } 3554 } 3555 }, 3556 { 3557 .name = "Cooperlake", 3558 .level = 0xd, 3559 .vendor = CPUID_VENDOR_INTEL, 3560 .family = 6, 3561 .model = 85, 3562 .stepping = 10, 3563 .features[FEAT_1_EDX] = 3564 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3565 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3566 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3567 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3568 CPUID_DE | CPUID_FP87, 3569 .features[FEAT_1_ECX] = 3570 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3571 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3572 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3573 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3574 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3575 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3576 .features[FEAT_8000_0001_EDX] = 3577 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3578 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3579 .features[FEAT_8000_0001_ECX] = 3580 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3581 .features[FEAT_7_0_EBX] = 3582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3586 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3587 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3588 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3589 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3590 .features[FEAT_7_0_ECX] = 3591 CPUID_7_0_ECX_PKU | 3592 CPUID_7_0_ECX_AVX512VNNI, 3593 .features[FEAT_7_0_EDX] = 3594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3595 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3596 .features[FEAT_ARCH_CAPABILITIES] = 3597 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3598 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3599 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3600 .features[FEAT_7_1_EAX] = 3601 CPUID_7_1_EAX_AVX512_BF16, 3602 /* XSAVES is added in version 2 */ 3603 .features[FEAT_XSAVE] = 3604 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3605 CPUID_XSAVE_XGETBV1, 3606 .features[FEAT_6_EAX] = 3607 CPUID_6_EAX_ARAT, 3608 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3609 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3610 MSR_VMX_BASIC_TRUE_CTLS, 3611 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3612 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3613 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3614 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3615 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3616 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3617 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3618 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3619 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3620 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3621 .features[FEAT_VMX_EXIT_CTLS] = 3622 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3623 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3624 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3625 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3626 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3627 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3628 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3629 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3630 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3631 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3632 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3633 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3634 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3635 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3636 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3637 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3638 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3639 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3640 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3641 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3642 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3643 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3644 .features[FEAT_VMX_SECONDARY_CTLS] = 3645 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3646 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3647 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3648 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3649 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3650 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3651 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3652 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3653 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3654 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3655 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3656 .xlevel = 0x80000008, 3657 .model_id = "Intel Xeon Processor (Cooperlake)", 3658 .versions = (X86CPUVersionDefinition[]) { 3659 { .version = 1 }, 3660 { .version = 2, 3661 .note = "XSAVES", 3662 .props = (PropValue[]) { 3663 { "xsaves", "on" }, 3664 { "vmx-xsaves", "on" }, 3665 { /* end of list */ } 3666 }, 3667 }, 3668 { /* end of list */ } 3669 } 3670 }, 3671 { 3672 .name = "Icelake-Server", 3673 .level = 0xd, 3674 .vendor = CPUID_VENDOR_INTEL, 3675 .family = 6, 3676 .model = 134, 3677 .stepping = 0, 3678 .features[FEAT_1_EDX] = 3679 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3683 CPUID_DE | CPUID_FP87, 3684 .features[FEAT_1_ECX] = 3685 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3686 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3687 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3688 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3690 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3691 .features[FEAT_8000_0001_EDX] = 3692 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3693 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3694 .features[FEAT_8000_0001_ECX] = 3695 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3696 .features[FEAT_8000_0008_EBX] = 3697 CPUID_8000_0008_EBX_WBNOINVD, 3698 .features[FEAT_7_0_EBX] = 3699 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3700 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3701 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3702 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3703 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3704 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3705 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3706 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3707 .features[FEAT_7_0_ECX] = 3708 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3709 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3710 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3711 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3712 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3713 .features[FEAT_7_0_EDX] = 3714 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3715 /* XSAVES is added in version 5 */ 3716 .features[FEAT_XSAVE] = 3717 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3718 CPUID_XSAVE_XGETBV1, 3719 .features[FEAT_6_EAX] = 3720 CPUID_6_EAX_ARAT, 3721 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3722 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3723 MSR_VMX_BASIC_TRUE_CTLS, 3724 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3725 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3726 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3727 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3728 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3729 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3730 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3731 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3732 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3733 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3734 .features[FEAT_VMX_EXIT_CTLS] = 3735 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3736 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3737 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3738 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3739 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3740 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3741 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3742 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3743 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3744 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3745 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3746 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3747 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3748 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3749 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3750 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3751 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3752 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3753 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3754 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3755 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3756 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3757 .features[FEAT_VMX_SECONDARY_CTLS] = 3758 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3759 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3760 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3761 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3762 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3763 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3764 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3765 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3766 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3767 .xlevel = 0x80000008, 3768 .model_id = "Intel Xeon Processor (Icelake)", 3769 .versions = (X86CPUVersionDefinition[]) { 3770 { .version = 1 }, 3771 { 3772 .version = 2, 3773 .note = "no TSX", 3774 .alias = "Icelake-Server-noTSX", 3775 .props = (PropValue[]) { 3776 { "hle", "off" }, 3777 { "rtm", "off" }, 3778 { /* end of list */ } 3779 }, 3780 }, 3781 { 3782 .version = 3, 3783 .props = (PropValue[]) { 3784 { "arch-capabilities", "on" }, 3785 { "rdctl-no", "on" }, 3786 { "ibrs-all", "on" }, 3787 { "skip-l1dfl-vmentry", "on" }, 3788 { "mds-no", "on" }, 3789 { "pschange-mc-no", "on" }, 3790 { "taa-no", "on" }, 3791 { /* end of list */ } 3792 }, 3793 }, 3794 { 3795 .version = 4, 3796 .props = (PropValue[]) { 3797 { "sha-ni", "on" }, 3798 { "avx512ifma", "on" }, 3799 { "rdpid", "on" }, 3800 { "fsrm", "on" }, 3801 { "vmx-rdseed-exit", "on" }, 3802 { "vmx-pml", "on" }, 3803 { "vmx-eptp-switching", "on" }, 3804 { "model", "106" }, 3805 { /* end of list */ } 3806 }, 3807 }, 3808 { 3809 .version = 5, 3810 .note = "XSAVES", 3811 .props = (PropValue[]) { 3812 { "xsaves", "on" }, 3813 { "vmx-xsaves", "on" }, 3814 { /* end of list */ } 3815 }, 3816 }, 3817 { 3818 .version = 6, 3819 .note = "5-level EPT", 3820 .props = (PropValue[]) { 3821 { "vmx-page-walk-5", "on" }, 3822 { /* end of list */ } 3823 }, 3824 }, 3825 { 3826 .version = 7, 3827 .note = "TSX, taa-no", 3828 .props = (PropValue[]) { 3829 /* Restore TSX features removed by -v2 above */ 3830 { "hle", "on" }, 3831 { "rtm", "on" }, 3832 { /* end of list */ } 3833 }, 3834 }, 3835 { /* end of list */ } 3836 } 3837 }, 3838 { 3839 .name = "SapphireRapids", 3840 .level = 0x20, 3841 .vendor = CPUID_VENDOR_INTEL, 3842 .family = 6, 3843 .model = 143, 3844 .stepping = 4, 3845 /* 3846 * please keep the ascending order so that we can have a clear view of 3847 * bit position of each feature. 3848 */ 3849 .features[FEAT_1_EDX] = 3850 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3851 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3852 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3853 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3854 CPUID_SSE | CPUID_SSE2, 3855 .features[FEAT_1_ECX] = 3856 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3857 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3858 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3859 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3860 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3861 .features[FEAT_8000_0001_EDX] = 3862 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3863 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3864 .features[FEAT_8000_0001_ECX] = 3865 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 3866 .features[FEAT_8000_0008_EBX] = 3867 CPUID_8000_0008_EBX_WBNOINVD, 3868 .features[FEAT_7_0_EBX] = 3869 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 3870 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 3871 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 3872 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3873 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 3874 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 3875 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 3876 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 3877 .features[FEAT_7_0_ECX] = 3878 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3879 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3880 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3881 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3882 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 3883 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 3884 .features[FEAT_7_0_EDX] = 3885 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 3886 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 3887 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 3888 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 3889 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3890 .features[FEAT_ARCH_CAPABILITIES] = 3891 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3892 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3893 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3894 .features[FEAT_XSAVE] = 3895 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3896 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 3897 .features[FEAT_6_EAX] = 3898 CPUID_6_EAX_ARAT, 3899 .features[FEAT_7_1_EAX] = 3900 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 3901 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 3902 .features[FEAT_VMX_BASIC] = 3903 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 3904 .features[FEAT_VMX_ENTRY_CTLS] = 3905 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 3906 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 3907 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 3908 .features[FEAT_VMX_EPT_VPID_CAPS] = 3909 MSR_VMX_EPT_EXECONLY | 3910 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 3911 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 3912 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 3913 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3914 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3915 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 3916 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3917 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3918 .features[FEAT_VMX_EXIT_CTLS] = 3919 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3920 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3921 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 3922 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3923 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3924 .features[FEAT_VMX_MISC] = 3925 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 3926 MSR_VMX_MISC_VMWRITE_VMEXIT, 3927 .features[FEAT_VMX_PINBASED_CTLS] = 3928 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 3929 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 3930 VMX_PIN_BASED_POSTED_INTR, 3931 .features[FEAT_VMX_PROCBASED_CTLS] = 3932 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3933 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3934 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3935 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3936 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3937 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3938 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 3939 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3940 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3941 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3942 VMX_CPU_BASED_PAUSE_EXITING | 3943 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3944 .features[FEAT_VMX_SECONDARY_CTLS] = 3945 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3946 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 3947 VMX_SECONDARY_EXEC_RDTSCP | 3948 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3949 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 3950 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3951 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3952 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3953 VMX_SECONDARY_EXEC_RDRAND_EXITING | 3954 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3955 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3956 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 3957 VMX_SECONDARY_EXEC_XSAVES, 3958 .features[FEAT_VMX_VMFUNC] = 3959 MSR_VMX_VMFUNC_EPT_SWITCHING, 3960 .xlevel = 0x80000008, 3961 .model_id = "Intel Xeon Processor (SapphireRapids)", 3962 .versions = (X86CPUVersionDefinition[]) { 3963 { .version = 1 }, 3964 { 3965 .version = 2, 3966 .props = (PropValue[]) { 3967 { "sbdr-ssdp-no", "on" }, 3968 { "fbsdp-no", "on" }, 3969 { "psdp-no", "on" }, 3970 { /* end of list */ } 3971 } 3972 }, 3973 { 3974 .version = 3, 3975 .props = (PropValue[]) { 3976 { "ss", "on" }, 3977 { "tsc-adjust", "on" }, 3978 { "cldemote", "on" }, 3979 { "movdiri", "on" }, 3980 { "movdir64b", "on" }, 3981 { /* end of list */ } 3982 } 3983 }, 3984 { /* end of list */ } 3985 } 3986 }, 3987 { 3988 .name = "GraniteRapids", 3989 .level = 0x20, 3990 .vendor = CPUID_VENDOR_INTEL, 3991 .family = 6, 3992 .model = 173, 3993 .stepping = 0, 3994 /* 3995 * please keep the ascending order so that we can have a clear view of 3996 * bit position of each feature. 3997 */ 3998 .features[FEAT_1_EDX] = 3999 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4000 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4001 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4002 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4003 CPUID_SSE | CPUID_SSE2, 4004 .features[FEAT_1_ECX] = 4005 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4006 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4007 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4008 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4009 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4010 .features[FEAT_8000_0001_EDX] = 4011 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4012 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4013 .features[FEAT_8000_0001_ECX] = 4014 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4015 .features[FEAT_8000_0008_EBX] = 4016 CPUID_8000_0008_EBX_WBNOINVD, 4017 .features[FEAT_7_0_EBX] = 4018 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4019 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4020 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4021 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4022 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4023 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4024 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4025 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4026 .features[FEAT_7_0_ECX] = 4027 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4028 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4029 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4030 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4031 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4032 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4033 .features[FEAT_7_0_EDX] = 4034 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4035 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4036 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4037 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4038 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4039 .features[FEAT_ARCH_CAPABILITIES] = 4040 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4041 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4042 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4043 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4044 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4045 .features[FEAT_XSAVE] = 4046 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4047 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4048 .features[FEAT_6_EAX] = 4049 CPUID_6_EAX_ARAT, 4050 .features[FEAT_7_1_EAX] = 4051 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4052 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4053 CPUID_7_1_EAX_AMX_FP16, 4054 .features[FEAT_7_1_EDX] = 4055 CPUID_7_1_EDX_PREFETCHITI, 4056 .features[FEAT_7_2_EDX] = 4057 CPUID_7_2_EDX_MCDT_NO, 4058 .features[FEAT_VMX_BASIC] = 4059 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4060 .features[FEAT_VMX_ENTRY_CTLS] = 4061 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4062 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4063 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4064 .features[FEAT_VMX_EPT_VPID_CAPS] = 4065 MSR_VMX_EPT_EXECONLY | 4066 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4067 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4068 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4069 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4070 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4071 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4072 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4073 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4074 .features[FEAT_VMX_EXIT_CTLS] = 4075 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4076 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4077 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4078 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4079 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4080 .features[FEAT_VMX_MISC] = 4081 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4082 MSR_VMX_MISC_VMWRITE_VMEXIT, 4083 .features[FEAT_VMX_PINBASED_CTLS] = 4084 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4085 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4086 VMX_PIN_BASED_POSTED_INTR, 4087 .features[FEAT_VMX_PROCBASED_CTLS] = 4088 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4089 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4090 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4091 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4092 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4093 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4094 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4095 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4096 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4097 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4098 VMX_CPU_BASED_PAUSE_EXITING | 4099 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4100 .features[FEAT_VMX_SECONDARY_CTLS] = 4101 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4102 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4103 VMX_SECONDARY_EXEC_RDTSCP | 4104 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4105 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4106 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4107 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4108 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4109 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4110 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4111 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4112 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4113 VMX_SECONDARY_EXEC_XSAVES, 4114 .features[FEAT_VMX_VMFUNC] = 4115 MSR_VMX_VMFUNC_EPT_SWITCHING, 4116 .xlevel = 0x80000008, 4117 .model_id = "Intel Xeon Processor (GraniteRapids)", 4118 .versions = (X86CPUVersionDefinition[]) { 4119 { .version = 1 }, 4120 { /* end of list */ }, 4121 }, 4122 }, 4123 { 4124 .name = "SierraForest", 4125 .level = 0x23, 4126 .vendor = CPUID_VENDOR_INTEL, 4127 .family = 6, 4128 .model = 175, 4129 .stepping = 0, 4130 /* 4131 * please keep the ascending order so that we can have a clear view of 4132 * bit position of each feature. 4133 */ 4134 .features[FEAT_1_EDX] = 4135 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4136 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4137 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4138 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4139 CPUID_SSE | CPUID_SSE2, 4140 .features[FEAT_1_ECX] = 4141 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4142 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4143 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4144 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4145 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4146 .features[FEAT_8000_0001_EDX] = 4147 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4148 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4149 .features[FEAT_8000_0001_ECX] = 4150 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4151 .features[FEAT_8000_0008_EBX] = 4152 CPUID_8000_0008_EBX_WBNOINVD, 4153 .features[FEAT_7_0_EBX] = 4154 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4155 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4156 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4157 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4158 CPUID_7_0_EBX_SHA_NI, 4159 .features[FEAT_7_0_ECX] = 4160 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4161 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4162 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4163 .features[FEAT_7_0_EDX] = 4164 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4165 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4166 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4167 .features[FEAT_ARCH_CAPABILITIES] = 4168 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4169 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4170 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4171 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4172 MSR_ARCH_CAP_PBRSB_NO, 4173 .features[FEAT_XSAVE] = 4174 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4175 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4176 .features[FEAT_6_EAX] = 4177 CPUID_6_EAX_ARAT, 4178 .features[FEAT_7_1_EAX] = 4179 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4180 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4181 .features[FEAT_7_1_EDX] = 4182 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4183 .features[FEAT_7_2_EDX] = 4184 CPUID_7_2_EDX_MCDT_NO, 4185 .features[FEAT_VMX_BASIC] = 4186 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4187 .features[FEAT_VMX_ENTRY_CTLS] = 4188 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4189 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4190 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4191 .features[FEAT_VMX_EPT_VPID_CAPS] = 4192 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4193 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4194 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4195 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4196 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4197 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4198 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4199 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4200 .features[FEAT_VMX_EXIT_CTLS] = 4201 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4202 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4203 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4204 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4205 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4206 .features[FEAT_VMX_MISC] = 4207 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4208 MSR_VMX_MISC_VMWRITE_VMEXIT, 4209 .features[FEAT_VMX_PINBASED_CTLS] = 4210 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4211 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4212 VMX_PIN_BASED_POSTED_INTR, 4213 .features[FEAT_VMX_PROCBASED_CTLS] = 4214 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4215 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4216 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4217 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4218 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4219 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4220 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4221 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4222 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4223 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4224 VMX_CPU_BASED_PAUSE_EXITING | 4225 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4226 .features[FEAT_VMX_SECONDARY_CTLS] = 4227 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4228 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4229 VMX_SECONDARY_EXEC_RDTSCP | 4230 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4231 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4232 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4233 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4234 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4235 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4236 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4237 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4238 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4239 VMX_SECONDARY_EXEC_XSAVES, 4240 .features[FEAT_VMX_VMFUNC] = 4241 MSR_VMX_VMFUNC_EPT_SWITCHING, 4242 .xlevel = 0x80000008, 4243 .model_id = "Intel Xeon Processor (SierraForest)", 4244 .versions = (X86CPUVersionDefinition[]) { 4245 { .version = 1 }, 4246 { /* end of list */ }, 4247 }, 4248 }, 4249 { 4250 .name = "Denverton", 4251 .level = 21, 4252 .vendor = CPUID_VENDOR_INTEL, 4253 .family = 6, 4254 .model = 95, 4255 .stepping = 1, 4256 .features[FEAT_1_EDX] = 4257 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4258 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4259 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4260 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4261 CPUID_SSE | CPUID_SSE2, 4262 .features[FEAT_1_ECX] = 4263 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4264 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4265 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4266 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4267 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4268 .features[FEAT_8000_0001_EDX] = 4269 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4270 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4271 .features[FEAT_8000_0001_ECX] = 4272 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4273 .features[FEAT_7_0_EBX] = 4274 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4275 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4276 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4277 .features[FEAT_7_0_EDX] = 4278 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4279 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4280 /* XSAVES is added in version 3 */ 4281 .features[FEAT_XSAVE] = 4282 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4283 .features[FEAT_6_EAX] = 4284 CPUID_6_EAX_ARAT, 4285 .features[FEAT_ARCH_CAPABILITIES] = 4286 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4287 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4288 MSR_VMX_BASIC_TRUE_CTLS, 4289 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4290 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4291 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4292 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4293 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4294 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4295 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4296 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4297 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4298 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4299 .features[FEAT_VMX_EXIT_CTLS] = 4300 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4301 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4302 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4303 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4304 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4305 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4306 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4307 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4308 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4309 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4310 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4311 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4312 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4313 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4314 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4315 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4316 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4317 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4318 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4319 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4320 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4321 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4322 .features[FEAT_VMX_SECONDARY_CTLS] = 4323 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4324 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4325 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4326 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4327 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4328 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4329 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4330 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4331 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4332 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4333 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4334 .xlevel = 0x80000008, 4335 .model_id = "Intel Atom Processor (Denverton)", 4336 .versions = (X86CPUVersionDefinition[]) { 4337 { .version = 1 }, 4338 { 4339 .version = 2, 4340 .note = "no MPX, no MONITOR", 4341 .props = (PropValue[]) { 4342 { "monitor", "off" }, 4343 { "mpx", "off" }, 4344 { /* end of list */ }, 4345 }, 4346 }, 4347 { 4348 .version = 3, 4349 .note = "XSAVES, no MPX, no MONITOR", 4350 .props = (PropValue[]) { 4351 { "xsaves", "on" }, 4352 { "vmx-xsaves", "on" }, 4353 { /* end of list */ }, 4354 }, 4355 }, 4356 { /* end of list */ }, 4357 }, 4358 }, 4359 { 4360 .name = "Snowridge", 4361 .level = 27, 4362 .vendor = CPUID_VENDOR_INTEL, 4363 .family = 6, 4364 .model = 134, 4365 .stepping = 1, 4366 .features[FEAT_1_EDX] = 4367 /* missing: CPUID_PN CPUID_IA64 */ 4368 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4369 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4370 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4371 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4372 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4373 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4374 CPUID_MMX | 4375 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4376 .features[FEAT_1_ECX] = 4377 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4378 CPUID_EXT_SSSE3 | 4379 CPUID_EXT_CX16 | 4380 CPUID_EXT_SSE41 | 4381 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4382 CPUID_EXT_POPCNT | 4383 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4384 CPUID_EXT_RDRAND, 4385 .features[FEAT_8000_0001_EDX] = 4386 CPUID_EXT2_SYSCALL | 4387 CPUID_EXT2_NX | 4388 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4389 CPUID_EXT2_LM, 4390 .features[FEAT_8000_0001_ECX] = 4391 CPUID_EXT3_LAHF_LM | 4392 CPUID_EXT3_3DNOWPREFETCH, 4393 .features[FEAT_7_0_EBX] = 4394 CPUID_7_0_EBX_FSGSBASE | 4395 CPUID_7_0_EBX_SMEP | 4396 CPUID_7_0_EBX_ERMS | 4397 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4398 CPUID_7_0_EBX_RDSEED | 4399 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4400 CPUID_7_0_EBX_CLWB | 4401 CPUID_7_0_EBX_SHA_NI, 4402 .features[FEAT_7_0_ECX] = 4403 CPUID_7_0_ECX_UMIP | 4404 /* missing bit 5 */ 4405 CPUID_7_0_ECX_GFNI | 4406 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4407 CPUID_7_0_ECX_MOVDIR64B, 4408 .features[FEAT_7_0_EDX] = 4409 CPUID_7_0_EDX_SPEC_CTRL | 4410 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4411 CPUID_7_0_EDX_CORE_CAPABILITY, 4412 .features[FEAT_CORE_CAPABILITY] = 4413 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4414 /* XSAVES is added in version 3 */ 4415 .features[FEAT_XSAVE] = 4416 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4417 CPUID_XSAVE_XGETBV1, 4418 .features[FEAT_6_EAX] = 4419 CPUID_6_EAX_ARAT, 4420 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4421 MSR_VMX_BASIC_TRUE_CTLS, 4422 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4423 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4424 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4425 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4426 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4427 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4428 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4429 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4430 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4431 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4432 .features[FEAT_VMX_EXIT_CTLS] = 4433 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4434 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4435 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4436 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4437 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4438 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4439 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4440 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4441 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4442 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4443 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4444 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4445 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4446 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4447 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4448 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4449 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4450 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4451 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4452 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4453 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4454 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4455 .features[FEAT_VMX_SECONDARY_CTLS] = 4456 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4457 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4458 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4459 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4460 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4461 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4462 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4463 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4464 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4465 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4466 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4467 .xlevel = 0x80000008, 4468 .model_id = "Intel Atom Processor (SnowRidge)", 4469 .versions = (X86CPUVersionDefinition[]) { 4470 { .version = 1 }, 4471 { 4472 .version = 2, 4473 .props = (PropValue[]) { 4474 { "mpx", "off" }, 4475 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4476 { /* end of list */ }, 4477 }, 4478 }, 4479 { 4480 .version = 3, 4481 .note = "XSAVES, no MPX", 4482 .props = (PropValue[]) { 4483 { "xsaves", "on" }, 4484 { "vmx-xsaves", "on" }, 4485 { /* end of list */ }, 4486 }, 4487 }, 4488 { 4489 .version = 4, 4490 .note = "no split lock detect, no core-capability", 4491 .props = (PropValue[]) { 4492 { "split-lock-detect", "off" }, 4493 { "core-capability", "off" }, 4494 { /* end of list */ }, 4495 }, 4496 }, 4497 { /* end of list */ }, 4498 }, 4499 }, 4500 { 4501 .name = "KnightsMill", 4502 .level = 0xd, 4503 .vendor = CPUID_VENDOR_INTEL, 4504 .family = 6, 4505 .model = 133, 4506 .stepping = 0, 4507 .features[FEAT_1_EDX] = 4508 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4509 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4510 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4511 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4512 CPUID_PSE | CPUID_DE | CPUID_FP87, 4513 .features[FEAT_1_ECX] = 4514 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4515 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4516 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4517 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4518 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4519 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4520 .features[FEAT_8000_0001_EDX] = 4521 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4522 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4523 .features[FEAT_8000_0001_ECX] = 4524 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4525 .features[FEAT_7_0_EBX] = 4526 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4527 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4528 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4529 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4530 CPUID_7_0_EBX_AVX512ER, 4531 .features[FEAT_7_0_ECX] = 4532 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4533 .features[FEAT_7_0_EDX] = 4534 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4535 .features[FEAT_XSAVE] = 4536 CPUID_XSAVE_XSAVEOPT, 4537 .features[FEAT_6_EAX] = 4538 CPUID_6_EAX_ARAT, 4539 .xlevel = 0x80000008, 4540 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4541 }, 4542 { 4543 .name = "Opteron_G1", 4544 .level = 5, 4545 .vendor = CPUID_VENDOR_AMD, 4546 .family = 15, 4547 .model = 6, 4548 .stepping = 1, 4549 .features[FEAT_1_EDX] = 4550 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4551 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4552 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4553 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4554 CPUID_DE | CPUID_FP87, 4555 .features[FEAT_1_ECX] = 4556 CPUID_EXT_SSE3, 4557 .features[FEAT_8000_0001_EDX] = 4558 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4559 .xlevel = 0x80000008, 4560 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4561 }, 4562 { 4563 .name = "Opteron_G2", 4564 .level = 5, 4565 .vendor = CPUID_VENDOR_AMD, 4566 .family = 15, 4567 .model = 6, 4568 .stepping = 1, 4569 .features[FEAT_1_EDX] = 4570 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4571 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4572 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4573 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4574 CPUID_DE | CPUID_FP87, 4575 .features[FEAT_1_ECX] = 4576 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4577 .features[FEAT_8000_0001_EDX] = 4578 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4579 .features[FEAT_8000_0001_ECX] = 4580 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4581 .xlevel = 0x80000008, 4582 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4583 }, 4584 { 4585 .name = "Opteron_G3", 4586 .level = 5, 4587 .vendor = CPUID_VENDOR_AMD, 4588 .family = 16, 4589 .model = 2, 4590 .stepping = 3, 4591 .features[FEAT_1_EDX] = 4592 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4593 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4594 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4595 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4596 CPUID_DE | CPUID_FP87, 4597 .features[FEAT_1_ECX] = 4598 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4599 CPUID_EXT_SSE3, 4600 .features[FEAT_8000_0001_EDX] = 4601 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4602 CPUID_EXT2_RDTSCP, 4603 .features[FEAT_8000_0001_ECX] = 4604 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4605 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4606 .xlevel = 0x80000008, 4607 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4608 }, 4609 { 4610 .name = "Opteron_G4", 4611 .level = 0xd, 4612 .vendor = CPUID_VENDOR_AMD, 4613 .family = 21, 4614 .model = 1, 4615 .stepping = 2, 4616 .features[FEAT_1_EDX] = 4617 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4618 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4619 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4620 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4621 CPUID_DE | CPUID_FP87, 4622 .features[FEAT_1_ECX] = 4623 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4624 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4625 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4626 CPUID_EXT_SSE3, 4627 .features[FEAT_8000_0001_EDX] = 4628 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4629 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4630 .features[FEAT_8000_0001_ECX] = 4631 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4632 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4633 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4634 CPUID_EXT3_LAHF_LM, 4635 .features[FEAT_SVM] = 4636 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4637 /* no xsaveopt! */ 4638 .xlevel = 0x8000001A, 4639 .model_id = "AMD Opteron 62xx class CPU", 4640 }, 4641 { 4642 .name = "Opteron_G5", 4643 .level = 0xd, 4644 .vendor = CPUID_VENDOR_AMD, 4645 .family = 21, 4646 .model = 2, 4647 .stepping = 0, 4648 .features[FEAT_1_EDX] = 4649 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4650 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4651 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4652 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4653 CPUID_DE | CPUID_FP87, 4654 .features[FEAT_1_ECX] = 4655 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4656 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4657 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4658 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4659 .features[FEAT_8000_0001_EDX] = 4660 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4661 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4662 .features[FEAT_8000_0001_ECX] = 4663 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4664 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4665 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4666 CPUID_EXT3_LAHF_LM, 4667 .features[FEAT_SVM] = 4668 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4669 /* no xsaveopt! */ 4670 .xlevel = 0x8000001A, 4671 .model_id = "AMD Opteron 63xx class CPU", 4672 }, 4673 { 4674 .name = "EPYC", 4675 .level = 0xd, 4676 .vendor = CPUID_VENDOR_AMD, 4677 .family = 23, 4678 .model = 1, 4679 .stepping = 2, 4680 .features[FEAT_1_EDX] = 4681 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4682 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4683 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4684 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4685 CPUID_VME | CPUID_FP87, 4686 .features[FEAT_1_ECX] = 4687 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4688 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4689 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4690 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4691 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4692 .features[FEAT_8000_0001_EDX] = 4693 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4694 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4695 CPUID_EXT2_SYSCALL, 4696 .features[FEAT_8000_0001_ECX] = 4697 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4698 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4699 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4700 CPUID_EXT3_TOPOEXT, 4701 .features[FEAT_7_0_EBX] = 4702 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4703 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4704 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4705 CPUID_7_0_EBX_SHA_NI, 4706 .features[FEAT_XSAVE] = 4707 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4708 CPUID_XSAVE_XGETBV1, 4709 .features[FEAT_6_EAX] = 4710 CPUID_6_EAX_ARAT, 4711 .features[FEAT_SVM] = 4712 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4713 .xlevel = 0x8000001E, 4714 .model_id = "AMD EPYC Processor", 4715 .cache_info = &epyc_cache_info, 4716 .versions = (X86CPUVersionDefinition[]) { 4717 { .version = 1 }, 4718 { 4719 .version = 2, 4720 .alias = "EPYC-IBPB", 4721 .props = (PropValue[]) { 4722 { "ibpb", "on" }, 4723 { "model-id", 4724 "AMD EPYC Processor (with IBPB)" }, 4725 { /* end of list */ } 4726 } 4727 }, 4728 { 4729 .version = 3, 4730 .props = (PropValue[]) { 4731 { "ibpb", "on" }, 4732 { "perfctr-core", "on" }, 4733 { "clzero", "on" }, 4734 { "xsaveerptr", "on" }, 4735 { "xsaves", "on" }, 4736 { "model-id", 4737 "AMD EPYC Processor" }, 4738 { /* end of list */ } 4739 } 4740 }, 4741 { 4742 .version = 4, 4743 .props = (PropValue[]) { 4744 { "model-id", 4745 "AMD EPYC-v4 Processor" }, 4746 { /* end of list */ } 4747 }, 4748 .cache_info = &epyc_v4_cache_info 4749 }, 4750 { /* end of list */ } 4751 } 4752 }, 4753 { 4754 .name = "Dhyana", 4755 .level = 0xd, 4756 .vendor = CPUID_VENDOR_HYGON, 4757 .family = 24, 4758 .model = 0, 4759 .stepping = 1, 4760 .features[FEAT_1_EDX] = 4761 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4762 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4763 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4764 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4765 CPUID_VME | CPUID_FP87, 4766 .features[FEAT_1_ECX] = 4767 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4768 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4769 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4770 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4771 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4772 .features[FEAT_8000_0001_EDX] = 4773 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4774 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4775 CPUID_EXT2_SYSCALL, 4776 .features[FEAT_8000_0001_ECX] = 4777 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4778 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4779 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4780 CPUID_EXT3_TOPOEXT, 4781 .features[FEAT_8000_0008_EBX] = 4782 CPUID_8000_0008_EBX_IBPB, 4783 .features[FEAT_7_0_EBX] = 4784 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4785 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4786 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4787 /* XSAVES is added in version 2 */ 4788 .features[FEAT_XSAVE] = 4789 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4790 CPUID_XSAVE_XGETBV1, 4791 .features[FEAT_6_EAX] = 4792 CPUID_6_EAX_ARAT, 4793 .features[FEAT_SVM] = 4794 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4795 .xlevel = 0x8000001E, 4796 .model_id = "Hygon Dhyana Processor", 4797 .cache_info = &epyc_cache_info, 4798 .versions = (X86CPUVersionDefinition[]) { 4799 { .version = 1 }, 4800 { .version = 2, 4801 .note = "XSAVES", 4802 .props = (PropValue[]) { 4803 { "xsaves", "on" }, 4804 { /* end of list */ } 4805 }, 4806 }, 4807 { /* end of list */ } 4808 } 4809 }, 4810 { 4811 .name = "EPYC-Rome", 4812 .level = 0xd, 4813 .vendor = CPUID_VENDOR_AMD, 4814 .family = 23, 4815 .model = 49, 4816 .stepping = 0, 4817 .features[FEAT_1_EDX] = 4818 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4819 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4820 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4821 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4822 CPUID_VME | CPUID_FP87, 4823 .features[FEAT_1_ECX] = 4824 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4825 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4826 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4827 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4828 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4829 .features[FEAT_8000_0001_EDX] = 4830 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4831 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4832 CPUID_EXT2_SYSCALL, 4833 .features[FEAT_8000_0001_ECX] = 4834 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4835 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4836 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4837 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4838 .features[FEAT_8000_0008_EBX] = 4839 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4840 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4841 CPUID_8000_0008_EBX_STIBP, 4842 .features[FEAT_7_0_EBX] = 4843 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4844 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4845 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4846 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4847 .features[FEAT_7_0_ECX] = 4848 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4849 .features[FEAT_XSAVE] = 4850 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4851 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4852 .features[FEAT_6_EAX] = 4853 CPUID_6_EAX_ARAT, 4854 .features[FEAT_SVM] = 4855 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4856 .xlevel = 0x8000001E, 4857 .model_id = "AMD EPYC-Rome Processor", 4858 .cache_info = &epyc_rome_cache_info, 4859 .versions = (X86CPUVersionDefinition[]) { 4860 { .version = 1 }, 4861 { 4862 .version = 2, 4863 .props = (PropValue[]) { 4864 { "ibrs", "on" }, 4865 { "amd-ssbd", "on" }, 4866 { /* end of list */ } 4867 } 4868 }, 4869 { 4870 .version = 3, 4871 .props = (PropValue[]) { 4872 { "model-id", 4873 "AMD EPYC-Rome-v3 Processor" }, 4874 { /* end of list */ } 4875 }, 4876 .cache_info = &epyc_rome_v3_cache_info 4877 }, 4878 { 4879 .version = 4, 4880 .props = (PropValue[]) { 4881 /* Erratum 1386 */ 4882 { "model-id", 4883 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 4884 { "xsaves", "off" }, 4885 { /* end of list */ } 4886 }, 4887 }, 4888 { /* end of list */ } 4889 } 4890 }, 4891 { 4892 .name = "EPYC-Milan", 4893 .level = 0xd, 4894 .vendor = CPUID_VENDOR_AMD, 4895 .family = 25, 4896 .model = 1, 4897 .stepping = 1, 4898 .features[FEAT_1_EDX] = 4899 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4900 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4901 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4902 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4903 CPUID_VME | CPUID_FP87, 4904 .features[FEAT_1_ECX] = 4905 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4906 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4907 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4908 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4909 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4910 CPUID_EXT_PCID, 4911 .features[FEAT_8000_0001_EDX] = 4912 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4913 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4914 CPUID_EXT2_SYSCALL, 4915 .features[FEAT_8000_0001_ECX] = 4916 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4917 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4918 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4919 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4920 .features[FEAT_8000_0008_EBX] = 4921 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4922 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4923 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4924 CPUID_8000_0008_EBX_AMD_SSBD, 4925 .features[FEAT_7_0_EBX] = 4926 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4927 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4928 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4929 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4930 CPUID_7_0_EBX_INVPCID, 4931 .features[FEAT_7_0_ECX] = 4932 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4933 .features[FEAT_7_0_EDX] = 4934 CPUID_7_0_EDX_FSRM, 4935 .features[FEAT_XSAVE] = 4936 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4937 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4938 .features[FEAT_6_EAX] = 4939 CPUID_6_EAX_ARAT, 4940 .features[FEAT_SVM] = 4941 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4942 .xlevel = 0x8000001E, 4943 .model_id = "AMD EPYC-Milan Processor", 4944 .cache_info = &epyc_milan_cache_info, 4945 .versions = (X86CPUVersionDefinition[]) { 4946 { .version = 1 }, 4947 { 4948 .version = 2, 4949 .props = (PropValue[]) { 4950 { "model-id", 4951 "AMD EPYC-Milan-v2 Processor" }, 4952 { "vaes", "on" }, 4953 { "vpclmulqdq", "on" }, 4954 { "stibp-always-on", "on" }, 4955 { "amd-psfd", "on" }, 4956 { "no-nested-data-bp", "on" }, 4957 { "lfence-always-serializing", "on" }, 4958 { "null-sel-clr-base", "on" }, 4959 { /* end of list */ } 4960 }, 4961 .cache_info = &epyc_milan_v2_cache_info 4962 }, 4963 { /* end of list */ } 4964 } 4965 }, 4966 { 4967 .name = "EPYC-Genoa", 4968 .level = 0xd, 4969 .vendor = CPUID_VENDOR_AMD, 4970 .family = 25, 4971 .model = 17, 4972 .stepping = 0, 4973 .features[FEAT_1_EDX] = 4974 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4975 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4976 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4977 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4978 CPUID_VME | CPUID_FP87, 4979 .features[FEAT_1_ECX] = 4980 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4981 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4982 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4983 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4984 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 4985 CPUID_EXT_SSE3, 4986 .features[FEAT_8000_0001_EDX] = 4987 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4988 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4989 CPUID_EXT2_SYSCALL, 4990 .features[FEAT_8000_0001_ECX] = 4991 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4992 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4993 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4994 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4995 .features[FEAT_8000_0008_EBX] = 4996 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4997 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4998 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4999 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5000 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5001 .features[FEAT_8000_0021_EAX] = 5002 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 5003 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5004 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5005 CPUID_8000_0021_EAX_AUTO_IBRS, 5006 .features[FEAT_7_0_EBX] = 5007 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5008 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5009 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5010 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5011 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5012 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5013 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5014 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5015 .features[FEAT_7_0_ECX] = 5016 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5017 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5018 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5019 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5020 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5021 CPUID_7_0_ECX_RDPID, 5022 .features[FEAT_7_0_EDX] = 5023 CPUID_7_0_EDX_FSRM, 5024 .features[FEAT_7_1_EAX] = 5025 CPUID_7_1_EAX_AVX512_BF16, 5026 .features[FEAT_XSAVE] = 5027 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5028 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5029 .features[FEAT_6_EAX] = 5030 CPUID_6_EAX_ARAT, 5031 .features[FEAT_SVM] = 5032 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5033 CPUID_SVM_SVME_ADDR_CHK, 5034 .xlevel = 0x80000022, 5035 .model_id = "AMD EPYC-Genoa Processor", 5036 .cache_info = &epyc_genoa_cache_info, 5037 }, 5038 }; 5039 5040 /* 5041 * We resolve CPU model aliases using -v1 when using "-machine 5042 * none", but this is just for compatibility while libvirt isn't 5043 * adapted to resolve CPU model versions before creating VMs. 5044 * See "Runnability guarantee of CPU models" at 5045 * docs/about/deprecated.rst. 5046 */ 5047 X86CPUVersion default_cpu_version = 1; 5048 5049 void x86_cpu_set_default_version(X86CPUVersion version) 5050 { 5051 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5052 assert(version != CPU_VERSION_AUTO); 5053 default_cpu_version = version; 5054 } 5055 5056 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5057 { 5058 int v = 0; 5059 const X86CPUVersionDefinition *vdef = 5060 x86_cpu_def_get_versions(model->cpudef); 5061 while (vdef->version) { 5062 v = vdef->version; 5063 vdef++; 5064 } 5065 return v; 5066 } 5067 5068 /* Return the actual version being used for a specific CPU model */ 5069 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5070 { 5071 X86CPUVersion v = model->version; 5072 if (v == CPU_VERSION_AUTO) { 5073 v = default_cpu_version; 5074 } 5075 if (v == CPU_VERSION_LATEST) { 5076 return x86_cpu_model_last_version(model); 5077 } 5078 return v; 5079 } 5080 5081 static Property max_x86_cpu_properties[] = { 5082 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5083 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5084 DEFINE_PROP_END_OF_LIST() 5085 }; 5086 5087 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5088 { 5089 Object *obj = OBJECT(dev); 5090 5091 if (!object_property_get_int(obj, "family", &error_abort)) { 5092 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5093 object_property_set_int(obj, "family", 15, &error_abort); 5094 object_property_set_int(obj, "model", 107, &error_abort); 5095 object_property_set_int(obj, "stepping", 1, &error_abort); 5096 } else { 5097 object_property_set_int(obj, "family", 6, &error_abort); 5098 object_property_set_int(obj, "model", 6, &error_abort); 5099 object_property_set_int(obj, "stepping", 3, &error_abort); 5100 } 5101 } 5102 5103 x86_cpu_realizefn(dev, errp); 5104 } 5105 5106 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5107 { 5108 DeviceClass *dc = DEVICE_CLASS(oc); 5109 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5110 5111 xcc->ordering = 9; 5112 5113 xcc->model_description = 5114 "Enables all features supported by the accelerator in the current host"; 5115 5116 device_class_set_props(dc, max_x86_cpu_properties); 5117 dc->realize = max_x86_cpu_realize; 5118 } 5119 5120 static void max_x86_cpu_initfn(Object *obj) 5121 { 5122 X86CPU *cpu = X86_CPU(obj); 5123 5124 /* We can't fill the features array here because we don't know yet if 5125 * "migratable" is true or false. 5126 */ 5127 cpu->max_features = true; 5128 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5129 5130 /* 5131 * these defaults are used for TCG and all other accelerators 5132 * besides KVM and HVF, which overwrite these values 5133 */ 5134 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5135 &error_abort); 5136 object_property_set_str(OBJECT(cpu), "model-id", 5137 "QEMU TCG CPU version " QEMU_HW_VERSION, 5138 &error_abort); 5139 } 5140 5141 static const TypeInfo max_x86_cpu_type_info = { 5142 .name = X86_CPU_TYPE_NAME("max"), 5143 .parent = TYPE_X86_CPU, 5144 .instance_init = max_x86_cpu_initfn, 5145 .class_init = max_x86_cpu_class_init, 5146 }; 5147 5148 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5149 { 5150 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5151 5152 switch (f->type) { 5153 case CPUID_FEATURE_WORD: 5154 { 5155 const char *reg = get_register_name_32(f->cpuid.reg); 5156 assert(reg); 5157 return g_strdup_printf("CPUID.%02XH:%s", 5158 f->cpuid.eax, reg); 5159 } 5160 case MSR_FEATURE_WORD: 5161 return g_strdup_printf("MSR(%02XH)", 5162 f->msr.index); 5163 } 5164 5165 return NULL; 5166 } 5167 5168 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5169 { 5170 FeatureWord w; 5171 5172 for (w = 0; w < FEATURE_WORDS; w++) { 5173 if (cpu->filtered_features[w]) { 5174 return true; 5175 } 5176 } 5177 5178 return false; 5179 } 5180 5181 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5182 const char *verbose_prefix) 5183 { 5184 CPUX86State *env = &cpu->env; 5185 FeatureWordInfo *f = &feature_word_info[w]; 5186 int i; 5187 5188 if (!cpu->force_features) { 5189 env->features[w] &= ~mask; 5190 } 5191 cpu->filtered_features[w] |= mask; 5192 5193 if (!verbose_prefix) { 5194 return; 5195 } 5196 5197 for (i = 0; i < 64; ++i) { 5198 if ((1ULL << i) & mask) { 5199 g_autofree char *feat_word_str = feature_word_description(f, i); 5200 warn_report("%s: %s%s%s [bit %d]", 5201 verbose_prefix, 5202 feat_word_str, 5203 f->feat_names[i] ? "." : "", 5204 f->feat_names[i] ? f->feat_names[i] : "", i); 5205 } 5206 } 5207 } 5208 5209 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5210 const char *name, void *opaque, 5211 Error **errp) 5212 { 5213 X86CPU *cpu = X86_CPU(obj); 5214 CPUX86State *env = &cpu->env; 5215 int64_t value; 5216 5217 value = (env->cpuid_version >> 8) & 0xf; 5218 if (value == 0xf) { 5219 value += (env->cpuid_version >> 20) & 0xff; 5220 } 5221 visit_type_int(v, name, &value, errp); 5222 } 5223 5224 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5225 const char *name, void *opaque, 5226 Error **errp) 5227 { 5228 X86CPU *cpu = X86_CPU(obj); 5229 CPUX86State *env = &cpu->env; 5230 const int64_t min = 0; 5231 const int64_t max = 0xff + 0xf; 5232 int64_t value; 5233 5234 if (!visit_type_int(v, name, &value, errp)) { 5235 return; 5236 } 5237 if (value < min || value > max) { 5238 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5239 name ? name : "null", value, min, max); 5240 return; 5241 } 5242 5243 env->cpuid_version &= ~0xff00f00; 5244 if (value > 0x0f) { 5245 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5246 } else { 5247 env->cpuid_version |= value << 8; 5248 } 5249 } 5250 5251 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5252 const char *name, void *opaque, 5253 Error **errp) 5254 { 5255 X86CPU *cpu = X86_CPU(obj); 5256 CPUX86State *env = &cpu->env; 5257 int64_t value; 5258 5259 value = (env->cpuid_version >> 4) & 0xf; 5260 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5261 visit_type_int(v, name, &value, errp); 5262 } 5263 5264 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5265 const char *name, void *opaque, 5266 Error **errp) 5267 { 5268 X86CPU *cpu = X86_CPU(obj); 5269 CPUX86State *env = &cpu->env; 5270 const int64_t min = 0; 5271 const int64_t max = 0xff; 5272 int64_t value; 5273 5274 if (!visit_type_int(v, name, &value, errp)) { 5275 return; 5276 } 5277 if (value < min || value > max) { 5278 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5279 name ? name : "null", value, min, max); 5280 return; 5281 } 5282 5283 env->cpuid_version &= ~0xf00f0; 5284 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5285 } 5286 5287 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5288 const char *name, void *opaque, 5289 Error **errp) 5290 { 5291 X86CPU *cpu = X86_CPU(obj); 5292 CPUX86State *env = &cpu->env; 5293 int64_t value; 5294 5295 value = env->cpuid_version & 0xf; 5296 visit_type_int(v, name, &value, errp); 5297 } 5298 5299 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5300 const char *name, void *opaque, 5301 Error **errp) 5302 { 5303 X86CPU *cpu = X86_CPU(obj); 5304 CPUX86State *env = &cpu->env; 5305 const int64_t min = 0; 5306 const int64_t max = 0xf; 5307 int64_t value; 5308 5309 if (!visit_type_int(v, name, &value, errp)) { 5310 return; 5311 } 5312 if (value < min || value > max) { 5313 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5314 name ? name : "null", value, min, max); 5315 return; 5316 } 5317 5318 env->cpuid_version &= ~0xf; 5319 env->cpuid_version |= value & 0xf; 5320 } 5321 5322 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5323 { 5324 X86CPU *cpu = X86_CPU(obj); 5325 CPUX86State *env = &cpu->env; 5326 char *value; 5327 5328 value = g_malloc(CPUID_VENDOR_SZ + 1); 5329 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5330 env->cpuid_vendor3); 5331 return value; 5332 } 5333 5334 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5335 Error **errp) 5336 { 5337 X86CPU *cpu = X86_CPU(obj); 5338 CPUX86State *env = &cpu->env; 5339 int i; 5340 5341 if (strlen(value) != CPUID_VENDOR_SZ) { 5342 error_setg(errp, "value of property 'vendor' must consist of" 5343 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5344 return; 5345 } 5346 5347 env->cpuid_vendor1 = 0; 5348 env->cpuid_vendor2 = 0; 5349 env->cpuid_vendor3 = 0; 5350 for (i = 0; i < 4; i++) { 5351 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5352 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5353 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5354 } 5355 } 5356 5357 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5358 { 5359 X86CPU *cpu = X86_CPU(obj); 5360 CPUX86State *env = &cpu->env; 5361 char *value; 5362 int i; 5363 5364 value = g_malloc(48 + 1); 5365 for (i = 0; i < 48; i++) { 5366 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5367 } 5368 value[48] = '\0'; 5369 return value; 5370 } 5371 5372 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5373 Error **errp) 5374 { 5375 X86CPU *cpu = X86_CPU(obj); 5376 CPUX86State *env = &cpu->env; 5377 int c, len, i; 5378 5379 if (model_id == NULL) { 5380 model_id = ""; 5381 } 5382 len = strlen(model_id); 5383 memset(env->cpuid_model, 0, 48); 5384 for (i = 0; i < 48; i++) { 5385 if (i >= len) { 5386 c = '\0'; 5387 } else { 5388 c = (uint8_t)model_id[i]; 5389 } 5390 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5391 } 5392 } 5393 5394 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5395 void *opaque, Error **errp) 5396 { 5397 X86CPU *cpu = X86_CPU(obj); 5398 int64_t value; 5399 5400 value = cpu->env.tsc_khz * 1000; 5401 visit_type_int(v, name, &value, errp); 5402 } 5403 5404 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5405 void *opaque, Error **errp) 5406 { 5407 X86CPU *cpu = X86_CPU(obj); 5408 const int64_t min = 0; 5409 const int64_t max = INT64_MAX; 5410 int64_t value; 5411 5412 if (!visit_type_int(v, name, &value, errp)) { 5413 return; 5414 } 5415 if (value < min || value > max) { 5416 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5417 name ? name : "null", value, min, max); 5418 return; 5419 } 5420 5421 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5422 } 5423 5424 /* Generic getter for "feature-words" and "filtered-features" properties */ 5425 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5426 const char *name, void *opaque, 5427 Error **errp) 5428 { 5429 uint64_t *array = (uint64_t *)opaque; 5430 FeatureWord w; 5431 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5432 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5433 X86CPUFeatureWordInfoList *list = NULL; 5434 5435 for (w = 0; w < FEATURE_WORDS; w++) { 5436 FeatureWordInfo *wi = &feature_word_info[w]; 5437 /* 5438 * We didn't have MSR features when "feature-words" was 5439 * introduced. Therefore skipped other type entries. 5440 */ 5441 if (wi->type != CPUID_FEATURE_WORD) { 5442 continue; 5443 } 5444 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5445 qwi->cpuid_input_eax = wi->cpuid.eax; 5446 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5447 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5448 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5449 qwi->features = array[w]; 5450 5451 /* List will be in reverse order, but order shouldn't matter */ 5452 list_entries[w].next = list; 5453 list_entries[w].value = &word_infos[w]; 5454 list = &list_entries[w]; 5455 } 5456 5457 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5458 } 5459 5460 /* Convert all '_' in a feature string option name to '-', to make feature 5461 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5462 */ 5463 static inline void feat2prop(char *s) 5464 { 5465 while ((s = strchr(s, '_'))) { 5466 *s = '-'; 5467 } 5468 } 5469 5470 /* Return the feature property name for a feature flag bit */ 5471 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5472 { 5473 const char *name; 5474 /* XSAVE components are automatically enabled by other features, 5475 * so return the original feature name instead 5476 */ 5477 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5478 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5479 5480 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5481 x86_ext_save_areas[comp].bits) { 5482 w = x86_ext_save_areas[comp].feature; 5483 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5484 } 5485 } 5486 5487 assert(bitnr < 64); 5488 assert(w < FEATURE_WORDS); 5489 name = feature_word_info[w].feat_names[bitnr]; 5490 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5491 return name; 5492 } 5493 5494 /* Compatibility hack to maintain legacy +-feat semantic, 5495 * where +-feat overwrites any feature set by 5496 * feat=on|feat even if the later is parsed after +-feat 5497 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5498 */ 5499 static GList *plus_features, *minus_features; 5500 5501 static gint compare_string(gconstpointer a, gconstpointer b) 5502 { 5503 return g_strcmp0(a, b); 5504 } 5505 5506 /* Parse "+feature,-feature,feature=foo" CPU feature string 5507 */ 5508 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5509 Error **errp) 5510 { 5511 char *featurestr; /* Single 'key=value" string being parsed */ 5512 static bool cpu_globals_initialized; 5513 bool ambiguous = false; 5514 5515 if (cpu_globals_initialized) { 5516 return; 5517 } 5518 cpu_globals_initialized = true; 5519 5520 if (!features) { 5521 return; 5522 } 5523 5524 for (featurestr = strtok(features, ","); 5525 featurestr; 5526 featurestr = strtok(NULL, ",")) { 5527 const char *name; 5528 const char *val = NULL; 5529 char *eq = NULL; 5530 char num[32]; 5531 GlobalProperty *prop; 5532 5533 /* Compatibility syntax: */ 5534 if (featurestr[0] == '+') { 5535 plus_features = g_list_append(plus_features, 5536 g_strdup(featurestr + 1)); 5537 continue; 5538 } else if (featurestr[0] == '-') { 5539 minus_features = g_list_append(minus_features, 5540 g_strdup(featurestr + 1)); 5541 continue; 5542 } 5543 5544 eq = strchr(featurestr, '='); 5545 if (eq) { 5546 *eq++ = 0; 5547 val = eq; 5548 } else { 5549 val = "on"; 5550 } 5551 5552 feat2prop(featurestr); 5553 name = featurestr; 5554 5555 if (g_list_find_custom(plus_features, name, compare_string)) { 5556 warn_report("Ambiguous CPU model string. " 5557 "Don't mix both \"+%s\" and \"%s=%s\"", 5558 name, name, val); 5559 ambiguous = true; 5560 } 5561 if (g_list_find_custom(minus_features, name, compare_string)) { 5562 warn_report("Ambiguous CPU model string. " 5563 "Don't mix both \"-%s\" and \"%s=%s\"", 5564 name, name, val); 5565 ambiguous = true; 5566 } 5567 5568 /* Special case: */ 5569 if (!strcmp(name, "tsc-freq")) { 5570 int ret; 5571 uint64_t tsc_freq; 5572 5573 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5574 if (ret < 0 || tsc_freq > INT64_MAX) { 5575 error_setg(errp, "bad numerical value %s", val); 5576 return; 5577 } 5578 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5579 val = num; 5580 name = "tsc-frequency"; 5581 } 5582 5583 prop = g_new0(typeof(*prop), 1); 5584 prop->driver = typename; 5585 prop->property = g_strdup(name); 5586 prop->value = g_strdup(val); 5587 qdev_prop_register_global(prop); 5588 } 5589 5590 if (ambiguous) { 5591 warn_report("Compatibility of ambiguous CPU model " 5592 "strings won't be kept on future QEMU versions"); 5593 } 5594 } 5595 5596 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5597 5598 /* Build a list with the name of all features on a feature word array */ 5599 static void x86_cpu_list_feature_names(FeatureWordArray features, 5600 strList **list) 5601 { 5602 strList **tail = list; 5603 FeatureWord w; 5604 5605 for (w = 0; w < FEATURE_WORDS; w++) { 5606 uint64_t filtered = features[w]; 5607 int i; 5608 for (i = 0; i < 64; i++) { 5609 if (filtered & (1ULL << i)) { 5610 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5611 } 5612 } 5613 } 5614 } 5615 5616 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5617 const char *name, void *opaque, 5618 Error **errp) 5619 { 5620 X86CPU *xc = X86_CPU(obj); 5621 strList *result = NULL; 5622 5623 x86_cpu_list_feature_names(xc->filtered_features, &result); 5624 visit_type_strList(v, "unavailable-features", &result, errp); 5625 } 5626 5627 /* Print all cpuid feature names in featureset 5628 */ 5629 static void listflags(GList *features) 5630 { 5631 size_t len = 0; 5632 GList *tmp; 5633 5634 for (tmp = features; tmp; tmp = tmp->next) { 5635 const char *name = tmp->data; 5636 if ((len + strlen(name) + 1) >= 75) { 5637 qemu_printf("\n"); 5638 len = 0; 5639 } 5640 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5641 len += strlen(name) + 1; 5642 } 5643 qemu_printf("\n"); 5644 } 5645 5646 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5647 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5648 { 5649 ObjectClass *class_a = (ObjectClass *)a; 5650 ObjectClass *class_b = (ObjectClass *)b; 5651 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5652 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5653 int ret; 5654 5655 if (cc_a->ordering != cc_b->ordering) { 5656 ret = cc_a->ordering - cc_b->ordering; 5657 } else { 5658 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5659 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5660 ret = strcmp(name_a, name_b); 5661 } 5662 return ret; 5663 } 5664 5665 static GSList *get_sorted_cpu_model_list(void) 5666 { 5667 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5668 list = g_slist_sort(list, x86_cpu_list_compare); 5669 return list; 5670 } 5671 5672 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5673 { 5674 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5675 char *r = object_property_get_str(obj, "model-id", &error_abort); 5676 object_unref(obj); 5677 return r; 5678 } 5679 5680 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5681 { 5682 X86CPUVersion version; 5683 5684 if (!cc->model || !cc->model->is_alias) { 5685 return NULL; 5686 } 5687 version = x86_cpu_model_resolve_version(cc->model); 5688 if (version <= 0) { 5689 return NULL; 5690 } 5691 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5692 } 5693 5694 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5695 { 5696 ObjectClass *oc = data; 5697 X86CPUClass *cc = X86_CPU_CLASS(oc); 5698 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5699 g_autofree char *desc = g_strdup(cc->model_description); 5700 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5701 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5702 5703 if (!desc && alias_of) { 5704 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5705 desc = g_strdup("(alias configured by machine type)"); 5706 } else { 5707 desc = g_strdup_printf("(alias of %s)", alias_of); 5708 } 5709 } 5710 if (!desc && cc->model && cc->model->note) { 5711 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5712 } 5713 if (!desc) { 5714 desc = g_strdup_printf("%s", model_id); 5715 } 5716 5717 if (cc->model && cc->model->cpudef->deprecation_note) { 5718 g_autofree char *olddesc = desc; 5719 desc = g_strdup_printf("%s (deprecated)", olddesc); 5720 } 5721 5722 qemu_printf(" %-20s %s\n", name, desc); 5723 } 5724 5725 /* list available CPU models and flags */ 5726 void x86_cpu_list(void) 5727 { 5728 int i, j; 5729 GSList *list; 5730 GList *names = NULL; 5731 5732 qemu_printf("Available CPUs:\n"); 5733 list = get_sorted_cpu_model_list(); 5734 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5735 g_slist_free(list); 5736 5737 names = NULL; 5738 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5739 FeatureWordInfo *fw = &feature_word_info[i]; 5740 for (j = 0; j < 64; j++) { 5741 if (fw->feat_names[j]) { 5742 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5743 } 5744 } 5745 } 5746 5747 names = g_list_sort(names, (GCompareFunc)strcmp); 5748 5749 qemu_printf("\nRecognized CPUID flags:\n"); 5750 listflags(names); 5751 qemu_printf("\n"); 5752 g_list_free(names); 5753 } 5754 5755 #ifndef CONFIG_USER_ONLY 5756 5757 /* Check for missing features that may prevent the CPU class from 5758 * running using the current machine and accelerator. 5759 */ 5760 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5761 strList **list) 5762 { 5763 strList **tail = list; 5764 X86CPU *xc; 5765 Error *err = NULL; 5766 5767 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5768 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5769 return; 5770 } 5771 5772 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5773 5774 x86_cpu_expand_features(xc, &err); 5775 if (err) { 5776 /* Errors at x86_cpu_expand_features should never happen, 5777 * but in case it does, just report the model as not 5778 * runnable at all using the "type" property. 5779 */ 5780 QAPI_LIST_APPEND(tail, g_strdup("type")); 5781 error_free(err); 5782 } 5783 5784 x86_cpu_filter_features(xc, false); 5785 5786 x86_cpu_list_feature_names(xc->filtered_features, tail); 5787 5788 object_unref(OBJECT(xc)); 5789 } 5790 5791 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5792 { 5793 ObjectClass *oc = data; 5794 X86CPUClass *cc = X86_CPU_CLASS(oc); 5795 CpuDefinitionInfoList **cpu_list = user_data; 5796 CpuDefinitionInfo *info; 5797 5798 info = g_malloc0(sizeof(*info)); 5799 info->name = x86_cpu_class_get_model_name(cc); 5800 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5801 info->has_unavailable_features = true; 5802 info->q_typename = g_strdup(object_class_get_name(oc)); 5803 info->migration_safe = cc->migration_safe; 5804 info->has_migration_safe = true; 5805 info->q_static = cc->static_model; 5806 if (cc->model && cc->model->cpudef->deprecation_note) { 5807 info->deprecated = true; 5808 } else { 5809 info->deprecated = false; 5810 } 5811 /* 5812 * Old machine types won't report aliases, so that alias translation 5813 * doesn't break compatibility with previous QEMU versions. 5814 */ 5815 if (default_cpu_version != CPU_VERSION_LEGACY) { 5816 info->alias_of = x86_cpu_class_get_alias_of(cc); 5817 } 5818 5819 QAPI_LIST_PREPEND(*cpu_list, info); 5820 } 5821 5822 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5823 { 5824 CpuDefinitionInfoList *cpu_list = NULL; 5825 GSList *list = get_sorted_cpu_model_list(); 5826 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5827 g_slist_free(list); 5828 return cpu_list; 5829 } 5830 5831 #endif /* !CONFIG_USER_ONLY */ 5832 5833 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5834 bool migratable_only) 5835 { 5836 FeatureWordInfo *wi = &feature_word_info[w]; 5837 uint64_t r = 0; 5838 5839 if (kvm_enabled()) { 5840 switch (wi->type) { 5841 case CPUID_FEATURE_WORD: 5842 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5843 wi->cpuid.ecx, 5844 wi->cpuid.reg); 5845 break; 5846 case MSR_FEATURE_WORD: 5847 r = kvm_arch_get_supported_msr_feature(kvm_state, 5848 wi->msr.index); 5849 break; 5850 } 5851 } else if (hvf_enabled()) { 5852 if (wi->type != CPUID_FEATURE_WORD) { 5853 return 0; 5854 } 5855 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5856 wi->cpuid.ecx, 5857 wi->cpuid.reg); 5858 } else if (tcg_enabled()) { 5859 r = wi->tcg_features; 5860 } else { 5861 return ~0; 5862 } 5863 #ifndef TARGET_X86_64 5864 if (w == FEAT_8000_0001_EDX) { 5865 /* 5866 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 5867 * way for userspace to get out of its 32-bit jail, we can leave 5868 * the LM bit set. 5869 */ 5870 uint32_t unavail = tcg_enabled() 5871 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 5872 : CPUID_EXT2_LM; 5873 r &= ~unavail; 5874 } 5875 #endif 5876 if (migratable_only) { 5877 r &= x86_cpu_get_migratable_flags(w); 5878 } 5879 return r; 5880 } 5881 5882 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 5883 uint32_t *eax, uint32_t *ebx, 5884 uint32_t *ecx, uint32_t *edx) 5885 { 5886 if (kvm_enabled()) { 5887 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 5888 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 5889 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 5890 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 5891 } else if (hvf_enabled()) { 5892 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 5893 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 5894 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 5895 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 5896 } else { 5897 *eax = 0; 5898 *ebx = 0; 5899 *ecx = 0; 5900 *edx = 0; 5901 } 5902 } 5903 5904 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 5905 uint32_t *eax, uint32_t *ebx, 5906 uint32_t *ecx, uint32_t *edx) 5907 { 5908 uint32_t level, unused; 5909 5910 /* Only return valid host leaves. */ 5911 switch (func) { 5912 case 2: 5913 case 4: 5914 host_cpuid(0, 0, &level, &unused, &unused, &unused); 5915 break; 5916 case 0x80000005: 5917 case 0x80000006: 5918 case 0x8000001d: 5919 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 5920 break; 5921 default: 5922 return; 5923 } 5924 5925 if (func > level) { 5926 *eax = 0; 5927 *ebx = 0; 5928 *ecx = 0; 5929 *edx = 0; 5930 } else { 5931 host_cpuid(func, index, eax, ebx, ecx, edx); 5932 } 5933 } 5934 5935 /* 5936 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5937 */ 5938 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5939 { 5940 PropValue *pv; 5941 for (pv = props; pv->prop; pv++) { 5942 if (!pv->value) { 5943 continue; 5944 } 5945 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5946 &error_abort); 5947 } 5948 } 5949 5950 /* 5951 * Apply properties for the CPU model version specified in model. 5952 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5953 */ 5954 5955 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5956 { 5957 const X86CPUVersionDefinition *vdef; 5958 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5959 5960 if (version == CPU_VERSION_LEGACY) { 5961 return; 5962 } 5963 5964 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5965 PropValue *p; 5966 5967 for (p = vdef->props; p && p->prop; p++) { 5968 object_property_parse(OBJECT(cpu), p->prop, p->value, 5969 &error_abort); 5970 } 5971 5972 if (vdef->version == version) { 5973 break; 5974 } 5975 } 5976 5977 /* 5978 * If we reached the end of the list, version number was invalid 5979 */ 5980 assert(vdef->version == version); 5981 } 5982 5983 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 5984 X86CPUModel *model) 5985 { 5986 const X86CPUVersionDefinition *vdef; 5987 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5988 const CPUCaches *cache_info = model->cpudef->cache_info; 5989 5990 if (version == CPU_VERSION_LEGACY) { 5991 return cache_info; 5992 } 5993 5994 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5995 if (vdef->cache_info) { 5996 cache_info = vdef->cache_info; 5997 } 5998 5999 if (vdef->version == version) { 6000 break; 6001 } 6002 } 6003 6004 assert(vdef->version == version); 6005 return cache_info; 6006 } 6007 6008 /* 6009 * Load data from X86CPUDefinition into a X86CPU object. 6010 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6011 */ 6012 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6013 { 6014 const X86CPUDefinition *def = model->cpudef; 6015 CPUX86State *env = &cpu->env; 6016 FeatureWord w; 6017 6018 /*NOTE: any property set by this function should be returned by 6019 * x86_cpu_static_props(), so static expansion of 6020 * query-cpu-model-expansion is always complete. 6021 */ 6022 6023 /* CPU models only set _minimum_ values for level/xlevel: */ 6024 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6025 &error_abort); 6026 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6027 &error_abort); 6028 6029 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6030 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6031 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6032 &error_abort); 6033 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6034 &error_abort); 6035 for (w = 0; w < FEATURE_WORDS; w++) { 6036 env->features[w] = def->features[w]; 6037 } 6038 6039 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6040 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6041 6042 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6043 6044 /* sysenter isn't supported in compatibility mode on AMD, 6045 * syscall isn't supported in compatibility mode on Intel. 6046 * Normally we advertise the actual CPU vendor, but you can 6047 * override this using the 'vendor' property if you want to use 6048 * KVM's sysenter/syscall emulation in compatibility mode and 6049 * when doing cross vendor migration 6050 */ 6051 6052 /* 6053 * vendor property is set here but then overloaded with the 6054 * host cpu vendor for KVM and HVF. 6055 */ 6056 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6057 6058 x86_cpu_apply_version_props(cpu, model); 6059 6060 /* 6061 * Properties in versioned CPU model are not user specified features. 6062 * We can simply clear env->user_features here since it will be filled later 6063 * in x86_cpu_expand_features() based on plus_features and minus_features. 6064 */ 6065 memset(&env->user_features, 0, sizeof(env->user_features)); 6066 } 6067 6068 static const gchar *x86_gdb_arch_name(CPUState *cs) 6069 { 6070 #ifdef TARGET_X86_64 6071 return "i386:x86-64"; 6072 #else 6073 return "i386"; 6074 #endif 6075 } 6076 6077 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6078 { 6079 X86CPUModel *model = data; 6080 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6081 CPUClass *cc = CPU_CLASS(oc); 6082 6083 xcc->model = model; 6084 xcc->migration_safe = true; 6085 cc->deprecation_note = model->cpudef->deprecation_note; 6086 } 6087 6088 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6089 { 6090 g_autofree char *typename = x86_cpu_type_name(name); 6091 TypeInfo ti = { 6092 .name = typename, 6093 .parent = TYPE_X86_CPU, 6094 .class_init = x86_cpu_cpudef_class_init, 6095 .class_data = model, 6096 }; 6097 6098 type_register(&ti); 6099 } 6100 6101 6102 /* 6103 * register builtin_x86_defs; 6104 * "max", "base" and subclasses ("host") are not registered here. 6105 * See x86_cpu_register_types for all model registrations. 6106 */ 6107 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6108 { 6109 X86CPUModel *m; 6110 const X86CPUVersionDefinition *vdef; 6111 6112 /* AMD aliases are handled at runtime based on CPUID vendor, so 6113 * they shouldn't be set on the CPU model table. 6114 */ 6115 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6116 /* catch mistakes instead of silently truncating model_id when too long */ 6117 assert(def->model_id && strlen(def->model_id) <= 48); 6118 6119 /* Unversioned model: */ 6120 m = g_new0(X86CPUModel, 1); 6121 m->cpudef = def; 6122 m->version = CPU_VERSION_AUTO; 6123 m->is_alias = true; 6124 x86_register_cpu_model_type(def->name, m); 6125 6126 /* Versioned models: */ 6127 6128 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6129 g_autofree char *name = 6130 x86_cpu_versioned_model_name(def, vdef->version); 6131 6132 m = g_new0(X86CPUModel, 1); 6133 m->cpudef = def; 6134 m->version = vdef->version; 6135 m->note = vdef->note; 6136 x86_register_cpu_model_type(name, m); 6137 6138 if (vdef->alias) { 6139 X86CPUModel *am = g_new0(X86CPUModel, 1); 6140 am->cpudef = def; 6141 am->version = vdef->version; 6142 am->is_alias = true; 6143 x86_register_cpu_model_type(vdef->alias, am); 6144 } 6145 } 6146 6147 } 6148 6149 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6150 { 6151 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6152 return 57; /* 57 bits virtual */ 6153 } else { 6154 return 48; /* 48 bits virtual */ 6155 } 6156 } 6157 6158 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6159 uint32_t *eax, uint32_t *ebx, 6160 uint32_t *ecx, uint32_t *edx) 6161 { 6162 X86CPU *cpu = env_archcpu(env); 6163 CPUState *cs = env_cpu(env); 6164 uint32_t die_offset; 6165 uint32_t limit; 6166 uint32_t signature[3]; 6167 X86CPUTopoInfo topo_info; 6168 6169 topo_info.dies_per_pkg = env->nr_dies; 6170 topo_info.cores_per_die = cs->nr_cores / env->nr_dies; 6171 topo_info.threads_per_core = cs->nr_threads; 6172 6173 /* Calculate & apply limits for different index ranges */ 6174 if (index >= 0xC0000000) { 6175 limit = env->cpuid_xlevel2; 6176 } else if (index >= 0x80000000) { 6177 limit = env->cpuid_xlevel; 6178 } else if (index >= 0x40000000) { 6179 limit = 0x40000001; 6180 } else { 6181 limit = env->cpuid_level; 6182 } 6183 6184 if (index > limit) { 6185 /* Intel documentation states that invalid EAX input will 6186 * return the same information as EAX=cpuid_level 6187 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6188 */ 6189 index = env->cpuid_level; 6190 } 6191 6192 switch(index) { 6193 case 0: 6194 *eax = env->cpuid_level; 6195 *ebx = env->cpuid_vendor1; 6196 *edx = env->cpuid_vendor2; 6197 *ecx = env->cpuid_vendor3; 6198 break; 6199 case 1: 6200 *eax = env->cpuid_version; 6201 *ebx = (cpu->apic_id << 24) | 6202 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6203 *ecx = env->features[FEAT_1_ECX]; 6204 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6205 *ecx |= CPUID_EXT_OSXSAVE; 6206 } 6207 *edx = env->features[FEAT_1_EDX]; 6208 if (cs->nr_cores * cs->nr_threads > 1) { 6209 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 6210 *edx |= CPUID_HT; 6211 } 6212 if (!cpu->enable_pmu) { 6213 *ecx &= ~CPUID_EXT_PDCM; 6214 } 6215 break; 6216 case 2: 6217 /* cache info: needed for Pentium Pro compatibility */ 6218 if (cpu->cache_info_passthrough) { 6219 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6220 break; 6221 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6222 *eax = *ebx = *ecx = *edx = 0; 6223 break; 6224 } 6225 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6226 *ebx = 0; 6227 if (!cpu->enable_l3_cache) { 6228 *ecx = 0; 6229 } else { 6230 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6231 } 6232 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6233 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6234 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6235 break; 6236 case 4: 6237 /* cache info: needed for Core compatibility */ 6238 if (cpu->cache_info_passthrough) { 6239 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6240 /* 6241 * QEMU has its own number of cores/logical cpus, 6242 * set 24..14, 31..26 bit to configured values 6243 */ 6244 if (*eax & 31) { 6245 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6246 int vcpus_per_socket = cs->nr_cores * cs->nr_threads; 6247 if (cs->nr_cores > 1) { 6248 *eax &= ~0xFC000000; 6249 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; 6250 } 6251 if (host_vcpus_per_cache > vcpus_per_socket) { 6252 *eax &= ~0x3FFC000; 6253 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; 6254 } 6255 } 6256 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6257 *eax = *ebx = *ecx = *edx = 0; 6258 } else { 6259 *eax = 0; 6260 switch (count) { 6261 case 0: /* L1 dcache info */ 6262 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6263 1, cs->nr_cores, 6264 eax, ebx, ecx, edx); 6265 break; 6266 case 1: /* L1 icache info */ 6267 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6268 1, cs->nr_cores, 6269 eax, ebx, ecx, edx); 6270 break; 6271 case 2: /* L2 cache info */ 6272 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6273 cs->nr_threads, cs->nr_cores, 6274 eax, ebx, ecx, edx); 6275 break; 6276 case 3: /* L3 cache info */ 6277 die_offset = apicid_die_offset(&topo_info); 6278 if (cpu->enable_l3_cache) { 6279 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6280 (1 << die_offset), cs->nr_cores, 6281 eax, ebx, ecx, edx); 6282 break; 6283 } 6284 /* fall through */ 6285 default: /* end of info */ 6286 *eax = *ebx = *ecx = *edx = 0; 6287 break; 6288 } 6289 } 6290 break; 6291 case 5: 6292 /* MONITOR/MWAIT Leaf */ 6293 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6294 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6295 *ecx = cpu->mwait.ecx; /* flags */ 6296 *edx = cpu->mwait.edx; /* mwait substates */ 6297 break; 6298 case 6: 6299 /* Thermal and Power Leaf */ 6300 *eax = env->features[FEAT_6_EAX]; 6301 *ebx = 0; 6302 *ecx = 0; 6303 *edx = 0; 6304 break; 6305 case 7: 6306 /* Structured Extended Feature Flags Enumeration Leaf */ 6307 if (count == 0) { 6308 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused; 6309 6310 /* Maximum ECX value for sub-leaves */ 6311 *eax = env->cpuid_level_func7; 6312 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6313 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6314 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6315 *ecx |= CPUID_7_0_ECX_OSPKE; 6316 } 6317 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6318 6319 /* 6320 * SGX cannot be emulated in software. If hardware does not 6321 * support enabling SGX and/or SGX flexible launch control, 6322 * then we need to update the VM's CPUID values accordingly. 6323 */ 6324 x86_cpu_get_supported_cpuid(0x7, 0, 6325 &eax_0_unused, &ebx_0, 6326 &ecx_0, &edx_0_unused); 6327 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) { 6328 *ebx &= ~CPUID_7_0_EBX_SGX; 6329 } 6330 6331 if ((*ecx & CPUID_7_0_ECX_SGX_LC) 6332 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) { 6333 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 6334 } 6335 } else if (count == 1) { 6336 *eax = env->features[FEAT_7_1_EAX]; 6337 *edx = env->features[FEAT_7_1_EDX]; 6338 *ebx = 0; 6339 *ecx = 0; 6340 } else if (count == 2) { 6341 *edx = env->features[FEAT_7_2_EDX]; 6342 *eax = 0; 6343 *ebx = 0; 6344 *ecx = 0; 6345 } else { 6346 *eax = 0; 6347 *ebx = 0; 6348 *ecx = 0; 6349 *edx = 0; 6350 } 6351 break; 6352 case 9: 6353 /* Direct Cache Access Information Leaf */ 6354 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6355 *ebx = 0; 6356 *ecx = 0; 6357 *edx = 0; 6358 break; 6359 case 0xA: 6360 /* Architectural Performance Monitoring Leaf */ 6361 if (cpu->enable_pmu) { 6362 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6363 } else { 6364 *eax = 0; 6365 *ebx = 0; 6366 *ecx = 0; 6367 *edx = 0; 6368 } 6369 break; 6370 case 0xB: 6371 /* Extended Topology Enumeration Leaf */ 6372 if (!cpu->enable_cpuid_0xb) { 6373 *eax = *ebx = *ecx = *edx = 0; 6374 break; 6375 } 6376 6377 *ecx = count & 0xff; 6378 *edx = cpu->apic_id; 6379 6380 switch (count) { 6381 case 0: 6382 *eax = apicid_core_offset(&topo_info); 6383 *ebx = cs->nr_threads; 6384 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 6385 break; 6386 case 1: 6387 *eax = apicid_pkg_offset(&topo_info); 6388 *ebx = cs->nr_cores * cs->nr_threads; 6389 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6390 break; 6391 default: 6392 *eax = 0; 6393 *ebx = 0; 6394 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6395 } 6396 6397 assert(!(*eax & ~0x1f)); 6398 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6399 break; 6400 case 0x1C: 6401 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6402 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6403 *edx = 0; 6404 } 6405 break; 6406 case 0x1F: 6407 /* V2 Extended Topology Enumeration Leaf */ 6408 if (env->nr_dies < 2) { 6409 *eax = *ebx = *ecx = *edx = 0; 6410 break; 6411 } 6412 6413 *ecx = count & 0xff; 6414 *edx = cpu->apic_id; 6415 switch (count) { 6416 case 0: 6417 *eax = apicid_core_offset(&topo_info); 6418 *ebx = cs->nr_threads; 6419 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 6420 break; 6421 case 1: 6422 *eax = apicid_die_offset(&topo_info); 6423 *ebx = topo_info.cores_per_die * topo_info.threads_per_core; 6424 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6425 break; 6426 case 2: 6427 *eax = apicid_pkg_offset(&topo_info); 6428 *ebx = cs->nr_cores * cs->nr_threads; 6429 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 6430 break; 6431 default: 6432 *eax = 0; 6433 *ebx = 0; 6434 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6435 } 6436 assert(!(*eax & ~0x1f)); 6437 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6438 break; 6439 case 0xD: { 6440 /* Processor Extended State */ 6441 *eax = 0; 6442 *ebx = 0; 6443 *ecx = 0; 6444 *edx = 0; 6445 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6446 break; 6447 } 6448 6449 if (count == 0) { 6450 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6451 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6452 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6453 /* 6454 * The initial value of xcr0 and ebx == 0, On host without kvm 6455 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6456 * even through guest update xcr0, this will crash some legacy guest 6457 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6458 */ 6459 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6460 } else if (count == 1) { 6461 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6462 x86_cpu_xsave_xss_components(cpu); 6463 6464 *eax = env->features[FEAT_XSAVE]; 6465 *ebx = xsave_area_size(xstate, true); 6466 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6467 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6468 if (kvm_enabled() && cpu->enable_pmu && 6469 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6470 (*eax & CPUID_XSAVE_XSAVES)) { 6471 *ecx |= XSTATE_ARCH_LBR_MASK; 6472 } else { 6473 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6474 } 6475 } else if (count == 0xf && cpu->enable_pmu 6476 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6477 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6478 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6479 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6480 6481 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6482 *eax = esa->size; 6483 *ebx = esa->offset; 6484 *ecx = esa->ecx & 6485 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6486 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6487 *eax = esa->size; 6488 *ebx = 0; 6489 *ecx = 1; 6490 } 6491 } 6492 break; 6493 } 6494 case 0x12: 6495 #ifndef CONFIG_USER_ONLY 6496 if (!kvm_enabled() || 6497 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6498 *eax = *ebx = *ecx = *edx = 0; 6499 break; 6500 } 6501 6502 /* 6503 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6504 * the EPC properties, e.g. confidentiality and integrity, from the 6505 * host's first EPC section, i.e. assume there is one EPC section or 6506 * that all EPC sections have the same security properties. 6507 */ 6508 if (count > 1) { 6509 uint64_t epc_addr, epc_size; 6510 6511 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6512 *eax = *ebx = *ecx = *edx = 0; 6513 break; 6514 } 6515 host_cpuid(index, 2, eax, ebx, ecx, edx); 6516 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6517 *ebx = (uint32_t)(epc_addr >> 32); 6518 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6519 *edx = (uint32_t)(epc_size >> 32); 6520 break; 6521 } 6522 6523 /* 6524 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6525 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6526 * supports. Features can be further restricted by userspace, but not 6527 * made more permissive. 6528 */ 6529 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6530 6531 if (count == 0) { 6532 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6533 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6534 } else { 6535 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6536 *ebx &= 0; /* ebx reserve */ 6537 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6538 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6539 6540 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6541 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6542 6543 /* Access to PROVISIONKEY requires additional credentials. */ 6544 if ((*eax & (1U << 4)) && 6545 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6546 *eax &= ~(1U << 4); 6547 } 6548 } 6549 #endif 6550 break; 6551 case 0x14: { 6552 /* Intel Processor Trace Enumeration */ 6553 *eax = 0; 6554 *ebx = 0; 6555 *ecx = 0; 6556 *edx = 0; 6557 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6558 !kvm_enabled()) { 6559 break; 6560 } 6561 6562 /* 6563 * If these are changed, they should stay in sync with 6564 * x86_cpu_filter_features(). 6565 */ 6566 if (count == 0) { 6567 *eax = INTEL_PT_MAX_SUBLEAF; 6568 *ebx = INTEL_PT_MINIMAL_EBX; 6569 *ecx = INTEL_PT_MINIMAL_ECX; 6570 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6571 *ecx |= CPUID_14_0_ECX_LIP; 6572 } 6573 } else if (count == 1) { 6574 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6575 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6576 } 6577 break; 6578 } 6579 case 0x1D: { 6580 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6581 *eax = 0; 6582 *ebx = 0; 6583 *ecx = 0; 6584 *edx = 0; 6585 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6586 break; 6587 } 6588 6589 if (count == 0) { 6590 /* Highest numbered palette subleaf */ 6591 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6592 } else if (count == 1) { 6593 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6594 (INTEL_AMX_BYTES_PER_TILE << 16); 6595 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6596 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6597 } 6598 break; 6599 } 6600 case 0x1E: { 6601 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6602 *eax = 0; 6603 *ebx = 0; 6604 *ecx = 0; 6605 *edx = 0; 6606 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6607 break; 6608 } 6609 6610 if (count == 0) { 6611 /* Highest numbered palette subleaf */ 6612 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6613 } 6614 break; 6615 } 6616 case 0x40000000: 6617 /* 6618 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6619 * set here, but we restrict to TCG none the less. 6620 */ 6621 if (tcg_enabled() && cpu->expose_tcg) { 6622 memcpy(signature, "TCGTCGTCGTCG", 12); 6623 *eax = 0x40000001; 6624 *ebx = signature[0]; 6625 *ecx = signature[1]; 6626 *edx = signature[2]; 6627 } else { 6628 *eax = 0; 6629 *ebx = 0; 6630 *ecx = 0; 6631 *edx = 0; 6632 } 6633 break; 6634 case 0x40000001: 6635 *eax = 0; 6636 *ebx = 0; 6637 *ecx = 0; 6638 *edx = 0; 6639 break; 6640 case 0x80000000: 6641 *eax = env->cpuid_xlevel; 6642 *ebx = env->cpuid_vendor1; 6643 *edx = env->cpuid_vendor2; 6644 *ecx = env->cpuid_vendor3; 6645 break; 6646 case 0x80000001: 6647 *eax = env->cpuid_version; 6648 *ebx = 0; 6649 *ecx = env->features[FEAT_8000_0001_ECX]; 6650 *edx = env->features[FEAT_8000_0001_EDX]; 6651 6652 /* The Linux kernel checks for the CMPLegacy bit and 6653 * discards multiple thread information if it is set. 6654 * So don't set it here for Intel to make Linux guests happy. 6655 */ 6656 if (cs->nr_cores * cs->nr_threads > 1) { 6657 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6658 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6659 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6660 *ecx |= 1 << 1; /* CmpLegacy bit */ 6661 } 6662 } 6663 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6664 !(env->hflags & HF_LMA_MASK)) { 6665 *edx &= ~CPUID_EXT2_SYSCALL; 6666 } 6667 break; 6668 case 0x80000002: 6669 case 0x80000003: 6670 case 0x80000004: 6671 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6672 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6673 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6674 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6675 break; 6676 case 0x80000005: 6677 /* cache info (L1 cache) */ 6678 if (cpu->cache_info_passthrough) { 6679 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6680 break; 6681 } 6682 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6683 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6684 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6685 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6686 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6687 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6688 break; 6689 case 0x80000006: 6690 /* cache info (L2 cache) */ 6691 if (cpu->cache_info_passthrough) { 6692 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6693 break; 6694 } 6695 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6696 (L2_DTLB_2M_ENTRIES << 16) | 6697 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6698 (L2_ITLB_2M_ENTRIES); 6699 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6700 (L2_DTLB_4K_ENTRIES << 16) | 6701 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6702 (L2_ITLB_4K_ENTRIES); 6703 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6704 cpu->enable_l3_cache ? 6705 env->cache_info_amd.l3_cache : NULL, 6706 ecx, edx); 6707 break; 6708 case 0x80000007: 6709 *eax = 0; 6710 *ebx = 0; 6711 *ecx = 0; 6712 *edx = env->features[FEAT_8000_0007_EDX]; 6713 break; 6714 case 0x80000008: 6715 /* virtual & phys address size in low 2 bytes. */ 6716 *eax = cpu->phys_bits; 6717 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6718 /* 64 bit processor */ 6719 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6720 *eax |= (cpu->guest_phys_bits << 16); 6721 } 6722 *ebx = env->features[FEAT_8000_0008_EBX]; 6723 if (cs->nr_cores * cs->nr_threads > 1) { 6724 /* 6725 * Bits 15:12 is "The number of bits in the initial 6726 * Core::X86::Apic::ApicId[ApicId] value that indicate 6727 * thread ID within a package". 6728 * Bits 7:0 is "The number of threads in the package is NC+1" 6729 */ 6730 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6731 ((cs->nr_cores * cs->nr_threads) - 1); 6732 } else { 6733 *ecx = 0; 6734 } 6735 *edx = 0; 6736 break; 6737 case 0x8000000A: 6738 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6739 *eax = 0x00000001; /* SVM Revision */ 6740 *ebx = 0x00000010; /* nr of ASIDs */ 6741 *ecx = 0; 6742 *edx = env->features[FEAT_SVM]; /* optional features */ 6743 } else { 6744 *eax = 0; 6745 *ebx = 0; 6746 *ecx = 0; 6747 *edx = 0; 6748 } 6749 break; 6750 case 0x8000001D: 6751 *eax = 0; 6752 if (cpu->cache_info_passthrough) { 6753 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6754 break; 6755 } 6756 switch (count) { 6757 case 0: /* L1 dcache info */ 6758 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6759 &topo_info, eax, ebx, ecx, edx); 6760 break; 6761 case 1: /* L1 icache info */ 6762 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6763 &topo_info, eax, ebx, ecx, edx); 6764 break; 6765 case 2: /* L2 cache info */ 6766 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6767 &topo_info, eax, ebx, ecx, edx); 6768 break; 6769 case 3: /* L3 cache info */ 6770 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6771 &topo_info, eax, ebx, ecx, edx); 6772 break; 6773 default: /* end of info */ 6774 *eax = *ebx = *ecx = *edx = 0; 6775 break; 6776 } 6777 break; 6778 case 0x8000001E: 6779 if (cpu->core_id <= 255) { 6780 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6781 } else { 6782 *eax = 0; 6783 *ebx = 0; 6784 *ecx = 0; 6785 *edx = 0; 6786 } 6787 break; 6788 case 0xC0000000: 6789 *eax = env->cpuid_xlevel2; 6790 *ebx = 0; 6791 *ecx = 0; 6792 *edx = 0; 6793 break; 6794 case 0xC0000001: 6795 /* Support for VIA CPU's CPUID instruction */ 6796 *eax = env->cpuid_version; 6797 *ebx = 0; 6798 *ecx = 0; 6799 *edx = env->features[FEAT_C000_0001_EDX]; 6800 break; 6801 case 0xC0000002: 6802 case 0xC0000003: 6803 case 0xC0000004: 6804 /* Reserved for the future, and now filled with zero */ 6805 *eax = 0; 6806 *ebx = 0; 6807 *ecx = 0; 6808 *edx = 0; 6809 break; 6810 case 0x8000001F: 6811 *eax = *ebx = *ecx = *edx = 0; 6812 if (sev_enabled()) { 6813 *eax = 0x2; 6814 *eax |= sev_es_enabled() ? 0x8 : 0; 6815 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6816 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6817 } 6818 break; 6819 case 0x80000021: 6820 *eax = env->features[FEAT_8000_0021_EAX]; 6821 *ebx = *ecx = *edx = 0; 6822 break; 6823 default: 6824 /* reserved values: zero */ 6825 *eax = 0; 6826 *ebx = 0; 6827 *ecx = 0; 6828 *edx = 0; 6829 break; 6830 } 6831 } 6832 6833 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 6834 { 6835 #ifndef CONFIG_USER_ONLY 6836 /* Those default values are defined in Skylake HW */ 6837 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 6838 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 6839 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 6840 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 6841 #endif 6842 } 6843 6844 static void x86_cpu_reset_hold(Object *obj, ResetType type) 6845 { 6846 CPUState *cs = CPU(obj); 6847 X86CPU *cpu = X86_CPU(cs); 6848 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6849 CPUX86State *env = &cpu->env; 6850 target_ulong cr4; 6851 uint64_t xcr0; 6852 int i; 6853 6854 if (xcc->parent_phases.hold) { 6855 xcc->parent_phases.hold(obj, type); 6856 } 6857 6858 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 6859 6860 env->old_exception = -1; 6861 6862 /* init to reset state */ 6863 env->int_ctl = 0; 6864 env->hflags2 |= HF2_GIF_MASK; 6865 env->hflags2 |= HF2_VGIF_MASK; 6866 env->hflags &= ~HF_GUEST_MASK; 6867 6868 cpu_x86_update_cr0(env, 0x60000010); 6869 env->a20_mask = ~0x0; 6870 env->smbase = 0x30000; 6871 env->msr_smi_count = 0; 6872 6873 env->idt.limit = 0xffff; 6874 env->gdt.limit = 0xffff; 6875 env->ldt.limit = 0xffff; 6876 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6877 env->tr.limit = 0xffff; 6878 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6879 6880 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6881 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6882 DESC_R_MASK | DESC_A_MASK); 6883 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6884 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6885 DESC_A_MASK); 6886 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6887 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6888 DESC_A_MASK); 6889 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6890 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6891 DESC_A_MASK); 6892 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6893 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6894 DESC_A_MASK); 6895 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6896 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6897 DESC_A_MASK); 6898 6899 env->eip = 0xfff0; 6900 env->regs[R_EDX] = env->cpuid_version; 6901 6902 env->eflags = 0x2; 6903 6904 /* FPU init */ 6905 for (i = 0; i < 8; i++) { 6906 env->fptags[i] = 1; 6907 } 6908 cpu_set_fpuc(env, 0x37f); 6909 6910 env->mxcsr = 0x1f80; 6911 /* All units are in INIT state. */ 6912 env->xstate_bv = 0; 6913 6914 env->pat = 0x0007040600070406ULL; 6915 6916 if (kvm_enabled()) { 6917 /* 6918 * KVM handles TSC = 0 specially and thinks we are hot-plugging 6919 * a new CPU, use 1 instead to force a reset. 6920 */ 6921 if (env->tsc != 0) { 6922 env->tsc = 1; 6923 } 6924 } else { 6925 env->tsc = 0; 6926 } 6927 6928 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6929 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6930 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6931 } 6932 6933 memset(env->dr, 0, sizeof(env->dr)); 6934 env->dr[6] = DR6_FIXED_1; 6935 env->dr[7] = DR7_FIXED_1; 6936 cpu_breakpoint_remove_all(cs, BP_CPU); 6937 cpu_watchpoint_remove_all(cs, BP_CPU); 6938 6939 cr4 = 0; 6940 xcr0 = XSTATE_FP_MASK; 6941 6942 #ifdef CONFIG_USER_ONLY 6943 /* Enable all the features for user-mode. */ 6944 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6945 xcr0 |= XSTATE_SSE_MASK; 6946 } 6947 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6948 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6949 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 6950 continue; 6951 } 6952 if (env->features[esa->feature] & esa->bits) { 6953 xcr0 |= 1ull << i; 6954 } 6955 } 6956 6957 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6958 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6959 } 6960 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6961 cr4 |= CR4_FSGSBASE_MASK; 6962 } 6963 #endif 6964 6965 env->xcr0 = xcr0; 6966 cpu_x86_update_cr4(env, cr4); 6967 6968 /* 6969 * SDM 11.11.5 requires: 6970 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6971 * - IA32_MTRR_PHYSMASKn.V = 0 6972 * All other bits are undefined. For simplification, zero it all. 6973 */ 6974 env->mtrr_deftype = 0; 6975 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6976 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6977 6978 env->interrupt_injected = -1; 6979 env->exception_nr = -1; 6980 env->exception_pending = 0; 6981 env->exception_injected = 0; 6982 env->exception_has_payload = false; 6983 env->exception_payload = 0; 6984 env->nmi_injected = false; 6985 env->triple_fault_pending = false; 6986 #if !defined(CONFIG_USER_ONLY) 6987 /* We hard-wire the BSP to the first CPU. */ 6988 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 6989 6990 cs->halted = !cpu_is_bsp(cpu); 6991 6992 if (kvm_enabled()) { 6993 kvm_arch_reset_vcpu(cpu); 6994 } 6995 6996 x86_cpu_set_sgxlepubkeyhash(env); 6997 6998 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 6999 7000 #endif 7001 } 7002 7003 void x86_cpu_after_reset(X86CPU *cpu) 7004 { 7005 #ifndef CONFIG_USER_ONLY 7006 if (kvm_enabled()) { 7007 kvm_arch_after_reset_vcpu(cpu); 7008 } 7009 7010 if (cpu->apic_state) { 7011 device_cold_reset(cpu->apic_state); 7012 } 7013 #endif 7014 } 7015 7016 static void mce_init(X86CPU *cpu) 7017 { 7018 CPUX86State *cenv = &cpu->env; 7019 unsigned int bank; 7020 7021 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7022 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7023 (CPUID_MCE | CPUID_MCA)) { 7024 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7025 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7026 cenv->mcg_ctl = ~(uint64_t)0; 7027 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7028 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7029 } 7030 } 7031 } 7032 7033 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7034 { 7035 if (*min < value) { 7036 *min = value; 7037 } 7038 } 7039 7040 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7041 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7042 { 7043 CPUX86State *env = &cpu->env; 7044 FeatureWordInfo *fi = &feature_word_info[w]; 7045 uint32_t eax = fi->cpuid.eax; 7046 uint32_t region = eax & 0xF0000000; 7047 7048 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7049 if (!env->features[w]) { 7050 return; 7051 } 7052 7053 switch (region) { 7054 case 0x00000000: 7055 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7056 break; 7057 case 0x80000000: 7058 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7059 break; 7060 case 0xC0000000: 7061 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7062 break; 7063 } 7064 7065 if (eax == 7) { 7066 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7067 fi->cpuid.ecx); 7068 } 7069 } 7070 7071 /* Calculate XSAVE components based on the configured CPU feature flags */ 7072 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7073 { 7074 CPUX86State *env = &cpu->env; 7075 int i; 7076 uint64_t mask; 7077 static bool request_perm; 7078 7079 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7080 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7081 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7082 env->features[FEAT_XSAVE_XSS_LO] = 0; 7083 env->features[FEAT_XSAVE_XSS_HI] = 0; 7084 return; 7085 } 7086 7087 mask = 0; 7088 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7089 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7090 if (env->features[esa->feature] & esa->bits) { 7091 mask |= (1ULL << i); 7092 } 7093 } 7094 7095 /* Only request permission for first vcpu */ 7096 if (kvm_enabled() && !request_perm) { 7097 kvm_request_xsave_components(cpu, mask); 7098 request_perm = true; 7099 } 7100 7101 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7102 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7103 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7104 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7105 } 7106 7107 /***** Steps involved on loading and filtering CPUID data 7108 * 7109 * When initializing and realizing a CPU object, the steps 7110 * involved in setting up CPUID data are: 7111 * 7112 * 1) Loading CPU model definition (X86CPUDefinition). This is 7113 * implemented by x86_cpu_load_model() and should be completely 7114 * transparent, as it is done automatically by instance_init. 7115 * No code should need to look at X86CPUDefinition structs 7116 * outside instance_init. 7117 * 7118 * 2) CPU expansion. This is done by realize before CPUID 7119 * filtering, and will make sure host/accelerator data is 7120 * loaded for CPU models that depend on host capabilities 7121 * (e.g. "host"). Done by x86_cpu_expand_features(). 7122 * 7123 * 3) CPUID filtering. This initializes extra data related to 7124 * CPUID, and checks if the host supports all capabilities 7125 * required by the CPU. Runnability of a CPU model is 7126 * determined at this step. Done by x86_cpu_filter_features(). 7127 * 7128 * Some operations don't require all steps to be performed. 7129 * More precisely: 7130 * 7131 * - CPU instance creation (instance_init) will run only CPU 7132 * model loading. CPU expansion can't run at instance_init-time 7133 * because host/accelerator data may be not available yet. 7134 * - CPU realization will perform both CPU model expansion and CPUID 7135 * filtering, and return an error in case one of them fails. 7136 * - query-cpu-definitions needs to run all 3 steps. It needs 7137 * to run CPUID filtering, as the 'unavailable-features' 7138 * field is set based on the filtering results. 7139 * - The query-cpu-model-expansion QMP command only needs to run 7140 * CPU model loading and CPU expansion. It should not filter 7141 * any CPUID data based on host capabilities. 7142 */ 7143 7144 /* Expand CPU configuration data, based on configured features 7145 * and host/accelerator capabilities when appropriate. 7146 */ 7147 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7148 { 7149 CPUX86State *env = &cpu->env; 7150 FeatureWord w; 7151 int i; 7152 GList *l; 7153 7154 for (l = plus_features; l; l = l->next) { 7155 const char *prop = l->data; 7156 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7157 return; 7158 } 7159 } 7160 7161 for (l = minus_features; l; l = l->next) { 7162 const char *prop = l->data; 7163 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7164 return; 7165 } 7166 } 7167 7168 /*TODO: Now cpu->max_features doesn't overwrite features 7169 * set using QOM properties, and we can convert 7170 * plus_features & minus_features to global properties 7171 * inside x86_cpu_parse_featurestr() too. 7172 */ 7173 if (cpu->max_features) { 7174 for (w = 0; w < FEATURE_WORDS; w++) { 7175 /* Override only features that weren't set explicitly 7176 * by the user. 7177 */ 7178 env->features[w] |= 7179 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 7180 ~env->user_features[w] & 7181 ~feature_word_info[w].no_autoenable_flags; 7182 } 7183 } 7184 7185 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7186 FeatureDep *d = &feature_dependencies[i]; 7187 if (!(env->features[d->from.index] & d->from.mask)) { 7188 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7189 7190 /* Not an error unless the dependent feature was added explicitly. */ 7191 mark_unavailable_features(cpu, d->to.index, 7192 unavailable_features & env->user_features[d->to.index], 7193 "This feature depends on other features that were not requested"); 7194 7195 env->features[d->to.index] &= ~unavailable_features; 7196 } 7197 } 7198 7199 if (!kvm_enabled() || !cpu->expose_kvm) { 7200 env->features[FEAT_KVM] = 0; 7201 } 7202 7203 x86_cpu_enable_xsave_components(cpu); 7204 7205 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7206 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7207 if (cpu->full_cpuid_auto_level) { 7208 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7209 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7210 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7211 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7212 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7213 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7214 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7215 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7216 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7217 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7218 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7219 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7220 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7221 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7222 7223 /* Intel Processor Trace requires CPUID[0x14] */ 7224 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7225 if (cpu->intel_pt_auto_level) { 7226 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7227 } else if (cpu->env.cpuid_min_level < 0x14) { 7228 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7229 CPUID_7_0_EBX_INTEL_PT, 7230 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7231 } 7232 } 7233 7234 /* 7235 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7236 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7237 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7238 * cpu->vendor_cpuid_only has been unset for compatibility with older 7239 * machine types. 7240 */ 7241 if ((env->nr_dies > 1) && 7242 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7243 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7244 } 7245 7246 /* SVM requires CPUID[0x8000000A] */ 7247 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7248 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7249 } 7250 7251 /* SEV requires CPUID[0x8000001F] */ 7252 if (sev_enabled()) { 7253 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7254 } 7255 7256 if (env->features[FEAT_8000_0021_EAX]) { 7257 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7258 } 7259 7260 /* SGX requires CPUID[0x12] for EPC enumeration */ 7261 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7262 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7263 } 7264 } 7265 7266 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7267 if (env->cpuid_level_func7 == UINT32_MAX) { 7268 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7269 } 7270 if (env->cpuid_level == UINT32_MAX) { 7271 env->cpuid_level = env->cpuid_min_level; 7272 } 7273 if (env->cpuid_xlevel == UINT32_MAX) { 7274 env->cpuid_xlevel = env->cpuid_min_xlevel; 7275 } 7276 if (env->cpuid_xlevel2 == UINT32_MAX) { 7277 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7278 } 7279 7280 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7281 return; 7282 } 7283 } 7284 7285 /* 7286 * Finishes initialization of CPUID data, filters CPU feature 7287 * words based on host availability of each feature. 7288 * 7289 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7290 */ 7291 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7292 { 7293 CPUX86State *env = &cpu->env; 7294 FeatureWord w; 7295 const char *prefix = NULL; 7296 7297 if (verbose) { 7298 prefix = accel_uses_host_cpuid() 7299 ? "host doesn't support requested feature" 7300 : "TCG doesn't support requested feature"; 7301 } 7302 7303 for (w = 0; w < FEATURE_WORDS; w++) { 7304 uint64_t host_feat = 7305 x86_cpu_get_supported_feature_word(w, false); 7306 uint64_t requested_features = env->features[w]; 7307 uint64_t unavailable_features = requested_features & ~host_feat; 7308 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7309 } 7310 7311 /* 7312 * Check that KVM actually allows the processor tracing features that 7313 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7314 */ 7315 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7316 kvm_enabled()) { 7317 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7318 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7319 7320 x86_cpu_get_supported_cpuid(0x14, 0, 7321 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7322 x86_cpu_get_supported_cpuid(0x14, 1, 7323 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7324 7325 if (!eax_0 || 7326 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7327 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7328 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7329 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7330 INTEL_PT_ADDR_RANGES_NUM) || 7331 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7332 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7333 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7334 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7335 /* 7336 * Processor Trace capabilities aren't configurable, so if the 7337 * host can't emulate the capabilities we report on 7338 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7339 */ 7340 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7341 } 7342 } 7343 } 7344 7345 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7346 { 7347 size_t len; 7348 7349 /* Hyper-V vendor id */ 7350 if (!cpu->hyperv_vendor) { 7351 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7352 &error_abort); 7353 } 7354 len = strlen(cpu->hyperv_vendor); 7355 if (len > 12) { 7356 warn_report("hv-vendor-id truncated to 12 characters"); 7357 len = 12; 7358 } 7359 memset(cpu->hyperv_vendor_id, 0, 12); 7360 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7361 7362 /* 'Hv#1' interface identification*/ 7363 cpu->hyperv_interface_id[0] = 0x31237648; 7364 cpu->hyperv_interface_id[1] = 0; 7365 cpu->hyperv_interface_id[2] = 0; 7366 cpu->hyperv_interface_id[3] = 0; 7367 7368 /* Hypervisor implementation limits */ 7369 cpu->hyperv_limits[0] = 64; 7370 cpu->hyperv_limits[1] = 0; 7371 cpu->hyperv_limits[2] = 0; 7372 } 7373 7374 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7375 { 7376 CPUState *cs = CPU(dev); 7377 X86CPU *cpu = X86_CPU(dev); 7378 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7379 CPUX86State *env = &cpu->env; 7380 Error *local_err = NULL; 7381 unsigned requested_lbr_fmt; 7382 7383 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7384 /* Use pc-relative instructions in system-mode */ 7385 cs->tcg_cflags |= CF_PCREL; 7386 #endif 7387 7388 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7389 error_setg(errp, "apic-id property was not initialized properly"); 7390 return; 7391 } 7392 7393 /* 7394 * Process Hyper-V enlightenments. 7395 * Note: this currently has to happen before the expansion of CPU features. 7396 */ 7397 x86_cpu_hyperv_realize(cpu); 7398 7399 x86_cpu_expand_features(cpu, &local_err); 7400 if (local_err) { 7401 goto out; 7402 } 7403 7404 /* 7405 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7406 * with user-provided setting. 7407 */ 7408 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7409 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7410 error_setg(errp, "invalid lbr-fmt"); 7411 return; 7412 } 7413 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7414 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7415 } 7416 7417 /* 7418 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7419 * 3)vPMU LBR format matches that of host setting. 7420 */ 7421 requested_lbr_fmt = 7422 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7423 if (requested_lbr_fmt && kvm_enabled()) { 7424 uint64_t host_perf_cap = 7425 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 7426 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7427 7428 if (!cpu->enable_pmu) { 7429 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7430 return; 7431 } 7432 if (requested_lbr_fmt != host_lbr_fmt) { 7433 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7434 "the host value (0x%x).", 7435 requested_lbr_fmt, host_lbr_fmt); 7436 return; 7437 } 7438 } 7439 7440 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7441 7442 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7443 error_setg(&local_err, 7444 accel_uses_host_cpuid() ? 7445 "Host doesn't support requested features" : 7446 "TCG doesn't support requested features"); 7447 goto out; 7448 } 7449 7450 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7451 * CPUID[1].EDX. 7452 */ 7453 if (IS_AMD_CPU(env)) { 7454 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7455 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7456 & CPUID_EXT2_AMD_ALIASES); 7457 } 7458 7459 x86_cpu_set_sgxlepubkeyhash(env); 7460 7461 /* 7462 * note: the call to the framework needs to happen after feature expansion, 7463 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7464 * These may be set by the accel-specific code, 7465 * and the results are subsequently checked / assumed in this function. 7466 */ 7467 cpu_exec_realizefn(cs, &local_err); 7468 if (local_err != NULL) { 7469 error_propagate(errp, local_err); 7470 return; 7471 } 7472 7473 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7474 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7475 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7476 goto out; 7477 } 7478 7479 if (cpu->guest_phys_bits == -1) { 7480 /* 7481 * If it was not set by the user, or by the accelerator via 7482 * cpu_exec_realizefn, clear. 7483 */ 7484 cpu->guest_phys_bits = 0; 7485 } 7486 7487 if (cpu->ucode_rev == 0) { 7488 /* 7489 * The default is the same as KVM's. Note that this check 7490 * needs to happen after the evenual setting of ucode_rev in 7491 * accel-specific code in cpu_exec_realizefn. 7492 */ 7493 if (IS_AMD_CPU(env)) { 7494 cpu->ucode_rev = 0x01000065; 7495 } else { 7496 cpu->ucode_rev = 0x100000000ULL; 7497 } 7498 } 7499 7500 /* 7501 * mwait extended info: needed for Core compatibility 7502 * We always wake on interrupt even if host does not have the capability. 7503 * 7504 * requires the accel-specific code in cpu_exec_realizefn to 7505 * have already acquired the CPUID data into cpu->mwait. 7506 */ 7507 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7508 7509 /* For 64bit systems think about the number of physical bits to present. 7510 * ideally this should be the same as the host; anything other than matching 7511 * the host can cause incorrect guest behaviour. 7512 * QEMU used to pick the magic value of 40 bits that corresponds to 7513 * consumer AMD devices but nothing else. 7514 * 7515 * Note that this code assumes features expansion has already been done 7516 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7517 * phys_bits adjustments to match the host have been already done in 7518 * accel-specific code in cpu_exec_realizefn. 7519 */ 7520 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7521 if (cpu->phys_bits && 7522 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7523 cpu->phys_bits < 32)) { 7524 error_setg(errp, "phys-bits should be between 32 and %u " 7525 " (but is %u)", 7526 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7527 return; 7528 } 7529 /* 7530 * 0 means it was not explicitly set by the user (or by machine 7531 * compat_props or by the host code in host-cpu.c). 7532 * In this case, the default is the value used by TCG (40). 7533 */ 7534 if (cpu->phys_bits == 0) { 7535 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7536 } 7537 if (cpu->guest_phys_bits && 7538 (cpu->guest_phys_bits > cpu->phys_bits || 7539 cpu->guest_phys_bits < 32)) { 7540 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7541 " (but is %u)", 7542 cpu->phys_bits, cpu->guest_phys_bits); 7543 return; 7544 } 7545 } else { 7546 /* For 32 bit systems don't use the user set value, but keep 7547 * phys_bits consistent with what we tell the guest. 7548 */ 7549 if (cpu->phys_bits != 0) { 7550 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7551 return; 7552 } 7553 if (cpu->guest_phys_bits != 0) { 7554 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7555 return; 7556 } 7557 7558 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7559 cpu->phys_bits = 36; 7560 } else { 7561 cpu->phys_bits = 32; 7562 } 7563 } 7564 7565 /* Cache information initialization */ 7566 if (!cpu->legacy_cache) { 7567 const CPUCaches *cache_info = 7568 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7569 7570 if (!xcc->model || !cache_info) { 7571 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7572 error_setg(errp, 7573 "CPU model '%s' doesn't support legacy-cache=off", name); 7574 return; 7575 } 7576 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7577 *cache_info; 7578 } else { 7579 /* Build legacy cache information */ 7580 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7581 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7582 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7583 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7584 7585 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7586 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7587 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7588 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7589 7590 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7591 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7592 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7593 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7594 } 7595 7596 #ifndef CONFIG_USER_ONLY 7597 MachineState *ms = MACHINE(qdev_get_machine()); 7598 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7599 7600 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7601 x86_cpu_apic_create(cpu, &local_err); 7602 if (local_err != NULL) { 7603 goto out; 7604 } 7605 } 7606 #endif 7607 7608 mce_init(cpu); 7609 7610 qemu_init_vcpu(cs); 7611 7612 /* 7613 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7614 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7615 * based on inputs (sockets,cores,threads), it is still better to give 7616 * users a warning. 7617 * 7618 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7619 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7620 */ 7621 if (IS_AMD_CPU(env) && 7622 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7623 cs->nr_threads > 1) { 7624 warn_report_once("This family of AMD CPU doesn't support " 7625 "hyperthreading(%d). Please configure -smp " 7626 "options properly or try enabling topoext " 7627 "feature.", cs->nr_threads); 7628 } 7629 7630 #ifndef CONFIG_USER_ONLY 7631 x86_cpu_apic_realize(cpu, &local_err); 7632 if (local_err != NULL) { 7633 goto out; 7634 } 7635 #endif /* !CONFIG_USER_ONLY */ 7636 cpu_reset(cs); 7637 7638 xcc->parent_realize(dev, &local_err); 7639 7640 out: 7641 if (local_err != NULL) { 7642 error_propagate(errp, local_err); 7643 return; 7644 } 7645 } 7646 7647 static void x86_cpu_unrealizefn(DeviceState *dev) 7648 { 7649 X86CPU *cpu = X86_CPU(dev); 7650 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7651 7652 #ifndef CONFIG_USER_ONLY 7653 cpu_remove_sync(CPU(dev)); 7654 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7655 #endif 7656 7657 if (cpu->apic_state) { 7658 object_unparent(OBJECT(cpu->apic_state)); 7659 cpu->apic_state = NULL; 7660 } 7661 7662 xcc->parent_unrealize(dev); 7663 } 7664 7665 typedef struct BitProperty { 7666 FeatureWord w; 7667 uint64_t mask; 7668 } BitProperty; 7669 7670 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7671 void *opaque, Error **errp) 7672 { 7673 X86CPU *cpu = X86_CPU(obj); 7674 BitProperty *fp = opaque; 7675 uint64_t f = cpu->env.features[fp->w]; 7676 bool value = (f & fp->mask) == fp->mask; 7677 visit_type_bool(v, name, &value, errp); 7678 } 7679 7680 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7681 void *opaque, Error **errp) 7682 { 7683 DeviceState *dev = DEVICE(obj); 7684 X86CPU *cpu = X86_CPU(obj); 7685 BitProperty *fp = opaque; 7686 bool value; 7687 7688 if (dev->realized) { 7689 qdev_prop_set_after_realize(dev, name, errp); 7690 return; 7691 } 7692 7693 if (!visit_type_bool(v, name, &value, errp)) { 7694 return; 7695 } 7696 7697 if (value) { 7698 cpu->env.features[fp->w] |= fp->mask; 7699 } else { 7700 cpu->env.features[fp->w] &= ~fp->mask; 7701 } 7702 cpu->env.user_features[fp->w] |= fp->mask; 7703 } 7704 7705 /* Register a boolean property to get/set a single bit in a uint32_t field. 7706 * 7707 * The same property name can be registered multiple times to make it affect 7708 * multiple bits in the same FeatureWord. In that case, the getter will return 7709 * true only if all bits are set. 7710 */ 7711 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7712 const char *prop_name, 7713 FeatureWord w, 7714 int bitnr) 7715 { 7716 ObjectClass *oc = OBJECT_CLASS(xcc); 7717 BitProperty *fp; 7718 ObjectProperty *op; 7719 uint64_t mask = (1ULL << bitnr); 7720 7721 op = object_class_property_find(oc, prop_name); 7722 if (op) { 7723 fp = op->opaque; 7724 assert(fp->w == w); 7725 fp->mask |= mask; 7726 } else { 7727 fp = g_new0(BitProperty, 1); 7728 fp->w = w; 7729 fp->mask = mask; 7730 object_class_property_add(oc, prop_name, "bool", 7731 x86_cpu_get_bit_prop, 7732 x86_cpu_set_bit_prop, 7733 NULL, fp); 7734 } 7735 } 7736 7737 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7738 FeatureWord w, 7739 int bitnr) 7740 { 7741 FeatureWordInfo *fi = &feature_word_info[w]; 7742 const char *name = fi->feat_names[bitnr]; 7743 7744 if (!name) { 7745 return; 7746 } 7747 7748 /* Property names should use "-" instead of "_". 7749 * Old names containing underscores are registered as aliases 7750 * using object_property_add_alias() 7751 */ 7752 assert(!strchr(name, '_')); 7753 /* aliases don't use "|" delimiters anymore, they are registered 7754 * manually using object_property_add_alias() */ 7755 assert(!strchr(name, '|')); 7756 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7757 } 7758 7759 static void x86_cpu_post_initfn(Object *obj) 7760 { 7761 accel_cpu_instance_init(CPU(obj)); 7762 } 7763 7764 static void x86_cpu_initfn(Object *obj) 7765 { 7766 X86CPU *cpu = X86_CPU(obj); 7767 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7768 CPUX86State *env = &cpu->env; 7769 7770 env->nr_dies = 1; 7771 7772 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7773 x86_cpu_get_feature_words, 7774 NULL, NULL, (void *)env->features); 7775 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 7776 x86_cpu_get_feature_words, 7777 NULL, NULL, (void *)cpu->filtered_features); 7778 7779 object_property_add_alias(obj, "sse3", obj, "pni"); 7780 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 7781 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 7782 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 7783 object_property_add_alias(obj, "xd", obj, "nx"); 7784 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 7785 object_property_add_alias(obj, "i64", obj, "lm"); 7786 7787 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7788 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7789 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7790 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7791 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7792 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7793 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7794 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7795 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7796 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7797 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7798 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7799 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7800 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7801 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7802 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7803 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7804 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7805 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7806 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 7807 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 7808 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 7809 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 7810 7811 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 7812 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 7813 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 7814 7815 if (xcc->model) { 7816 x86_cpu_load_model(cpu, xcc->model); 7817 } 7818 } 7819 7820 static int64_t x86_cpu_get_arch_id(CPUState *cs) 7821 { 7822 X86CPU *cpu = X86_CPU(cs); 7823 7824 return cpu->apic_id; 7825 } 7826 7827 #if !defined(CONFIG_USER_ONLY) 7828 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7829 { 7830 X86CPU *cpu = X86_CPU(cs); 7831 7832 return cpu->env.cr[0] & CR0_PG_MASK; 7833 } 7834 #endif /* !CONFIG_USER_ONLY */ 7835 7836 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7837 { 7838 X86CPU *cpu = X86_CPU(cs); 7839 7840 cpu->env.eip = value; 7841 } 7842 7843 static vaddr x86_cpu_get_pc(CPUState *cs) 7844 { 7845 X86CPU *cpu = X86_CPU(cs); 7846 7847 /* Match cpu_get_tb_cpu_state. */ 7848 return cpu->env.eip + cpu->env.segs[R_CS].base; 7849 } 7850 7851 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7852 { 7853 X86CPU *cpu = X86_CPU(cs); 7854 CPUX86State *env = &cpu->env; 7855 7856 #if !defined(CONFIG_USER_ONLY) 7857 if (interrupt_request & CPU_INTERRUPT_POLL) { 7858 return CPU_INTERRUPT_POLL; 7859 } 7860 #endif 7861 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7862 return CPU_INTERRUPT_SIPI; 7863 } 7864 7865 if (env->hflags2 & HF2_GIF_MASK) { 7866 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7867 !(env->hflags & HF_SMM_MASK)) { 7868 return CPU_INTERRUPT_SMI; 7869 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7870 !(env->hflags2 & HF2_NMI_MASK)) { 7871 return CPU_INTERRUPT_NMI; 7872 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7873 return CPU_INTERRUPT_MCE; 7874 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7875 (((env->hflags2 & HF2_VINTR_MASK) && 7876 (env->hflags2 & HF2_HIF_MASK)) || 7877 (!(env->hflags2 & HF2_VINTR_MASK) && 7878 (env->eflags & IF_MASK && 7879 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7880 return CPU_INTERRUPT_HARD; 7881 #if !defined(CONFIG_USER_ONLY) 7882 } else if (env->hflags2 & HF2_VGIF_MASK) { 7883 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 7884 (env->eflags & IF_MASK) && 7885 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7886 return CPU_INTERRUPT_VIRQ; 7887 } 7888 #endif 7889 } 7890 } 7891 7892 return 0; 7893 } 7894 7895 static bool x86_cpu_has_work(CPUState *cs) 7896 { 7897 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7898 } 7899 7900 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 7901 { 7902 CPUX86State *env = cpu_env(cs); 7903 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 7904 int mmu_index_base = 7905 (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER64_IDX : 7906 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 7907 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 7908 7909 return mmu_index_base + mmu_index_32; 7910 } 7911 7912 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7913 { 7914 X86CPU *cpu = X86_CPU(cs); 7915 CPUX86State *env = &cpu->env; 7916 7917 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7918 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7919 : bfd_mach_i386_i8086); 7920 7921 info->cap_arch = CS_ARCH_X86; 7922 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7923 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7924 : CS_MODE_16); 7925 info->cap_insn_unit = 1; 7926 info->cap_insn_split = 8; 7927 } 7928 7929 void x86_update_hflags(CPUX86State *env) 7930 { 7931 uint32_t hflags; 7932 #define HFLAG_COPY_MASK \ 7933 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7934 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7935 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7936 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7937 7938 hflags = env->hflags & HFLAG_COPY_MASK; 7939 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7940 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7941 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7942 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7943 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7944 7945 if (env->cr[4] & CR4_OSFXSR_MASK) { 7946 hflags |= HF_OSFXSR_MASK; 7947 } 7948 7949 if (env->efer & MSR_EFER_LMA) { 7950 hflags |= HF_LMA_MASK; 7951 } 7952 7953 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7954 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7955 } else { 7956 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7957 (DESC_B_SHIFT - HF_CS32_SHIFT); 7958 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7959 (DESC_B_SHIFT - HF_SS32_SHIFT); 7960 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7961 !(hflags & HF_CS32_MASK)) { 7962 hflags |= HF_ADDSEG_MASK; 7963 } else { 7964 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7965 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7966 } 7967 } 7968 env->hflags = hflags; 7969 } 7970 7971 static Property x86_cpu_properties[] = { 7972 #ifdef CONFIG_USER_ONLY 7973 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7974 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7975 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7976 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7977 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7978 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7979 #else 7980 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7981 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7982 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7983 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7984 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7985 #endif 7986 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7987 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7988 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 7989 7990 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7991 HYPERV_SPINLOCK_NEVER_NOTIFY), 7992 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7993 HYPERV_FEAT_RELAXED, 0), 7994 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7995 HYPERV_FEAT_VAPIC, 0), 7996 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7997 HYPERV_FEAT_TIME, 0), 7998 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7999 HYPERV_FEAT_CRASH, 0), 8000 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8001 HYPERV_FEAT_RESET, 0), 8002 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8003 HYPERV_FEAT_VPINDEX, 0), 8004 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8005 HYPERV_FEAT_RUNTIME, 0), 8006 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8007 HYPERV_FEAT_SYNIC, 0), 8008 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8009 HYPERV_FEAT_STIMER, 0), 8010 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8011 HYPERV_FEAT_FREQUENCIES, 0), 8012 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8013 HYPERV_FEAT_REENLIGHTENMENT, 0), 8014 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8015 HYPERV_FEAT_TLBFLUSH, 0), 8016 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8017 HYPERV_FEAT_EVMCS, 0), 8018 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8019 HYPERV_FEAT_IPI, 0), 8020 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8021 HYPERV_FEAT_STIMER_DIRECT, 0), 8022 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8023 HYPERV_FEAT_AVIC, 0), 8024 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8025 HYPERV_FEAT_MSR_BITMAP, 0), 8026 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8027 HYPERV_FEAT_XMM_INPUT, 0), 8028 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8029 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8030 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8031 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8032 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8033 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8034 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8035 HYPERV_FEAT_SYNDBG, 0), 8036 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8037 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8038 8039 /* WS2008R2 identify by default */ 8040 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8041 0x3839), 8042 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8043 0x000A), 8044 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8045 0x0000), 8046 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8047 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8048 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8049 8050 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8051 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8052 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8053 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8054 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8055 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8056 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8057 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8058 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8059 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8060 UINT32_MAX), 8061 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8062 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8063 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8064 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8065 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8066 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8067 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8068 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8069 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8070 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8071 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8072 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8073 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8074 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 8075 false), 8076 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8077 false), 8078 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8079 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8080 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8081 true), 8082 /* 8083 * lecacy_cache defaults to true unless the CPU model provides its 8084 * own cache information (see x86_cpu_load_def()). 8085 */ 8086 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8087 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8088 8089 /* 8090 * From "Requirements for Implementing the Microsoft 8091 * Hypervisor Interface": 8092 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8093 * 8094 * "Starting with Windows Server 2012 and Windows 8, if 8095 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8096 * the hypervisor imposes no specific limit to the number of VPs. 8097 * In this case, Windows Server 2012 guest VMs may use more than 8098 * 64 VPs, up to the maximum supported number of processors applicable 8099 * to the specific Windows version being used." 8100 */ 8101 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8102 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8103 false), 8104 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8105 true), 8106 DEFINE_PROP_END_OF_LIST() 8107 }; 8108 8109 #ifndef CONFIG_USER_ONLY 8110 #include "hw/core/sysemu-cpu-ops.h" 8111 8112 static const struct SysemuCPUOps i386_sysemu_ops = { 8113 .get_memory_mapping = x86_cpu_get_memory_mapping, 8114 .get_paging_enabled = x86_cpu_get_paging_enabled, 8115 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8116 .asidx_from_attrs = x86_asidx_from_attrs, 8117 .get_crash_info = x86_cpu_get_crash_info, 8118 .write_elf32_note = x86_cpu_write_elf32_note, 8119 .write_elf64_note = x86_cpu_write_elf64_note, 8120 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8121 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8122 .legacy_vmsd = &vmstate_x86_cpu, 8123 }; 8124 #endif 8125 8126 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8127 { 8128 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8129 CPUClass *cc = CPU_CLASS(oc); 8130 DeviceClass *dc = DEVICE_CLASS(oc); 8131 ResettableClass *rc = RESETTABLE_CLASS(oc); 8132 FeatureWord w; 8133 8134 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8135 &xcc->parent_realize); 8136 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8137 &xcc->parent_unrealize); 8138 device_class_set_props(dc, x86_cpu_properties); 8139 8140 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8141 &xcc->parent_phases); 8142 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8143 8144 cc->class_by_name = x86_cpu_class_by_name; 8145 cc->parse_features = x86_cpu_parse_featurestr; 8146 cc->has_work = x86_cpu_has_work; 8147 cc->mmu_index = x86_cpu_mmu_index; 8148 cc->dump_state = x86_cpu_dump_state; 8149 cc->set_pc = x86_cpu_set_pc; 8150 cc->get_pc = x86_cpu_get_pc; 8151 cc->gdb_read_register = x86_cpu_gdb_read_register; 8152 cc->gdb_write_register = x86_cpu_gdb_write_register; 8153 cc->get_arch_id = x86_cpu_get_arch_id; 8154 8155 #ifndef CONFIG_USER_ONLY 8156 cc->sysemu_ops = &i386_sysemu_ops; 8157 #endif /* !CONFIG_USER_ONLY */ 8158 8159 cc->gdb_arch_name = x86_gdb_arch_name; 8160 #ifdef TARGET_X86_64 8161 cc->gdb_core_xml_file = "i386-64bit.xml"; 8162 #else 8163 cc->gdb_core_xml_file = "i386-32bit.xml"; 8164 #endif 8165 cc->disas_set_info = x86_disas_set_info; 8166 8167 dc->user_creatable = true; 8168 8169 object_class_property_add(oc, "family", "int", 8170 x86_cpuid_version_get_family, 8171 x86_cpuid_version_set_family, NULL, NULL); 8172 object_class_property_add(oc, "model", "int", 8173 x86_cpuid_version_get_model, 8174 x86_cpuid_version_set_model, NULL, NULL); 8175 object_class_property_add(oc, "stepping", "int", 8176 x86_cpuid_version_get_stepping, 8177 x86_cpuid_version_set_stepping, NULL, NULL); 8178 object_class_property_add_str(oc, "vendor", 8179 x86_cpuid_get_vendor, 8180 x86_cpuid_set_vendor); 8181 object_class_property_add_str(oc, "model-id", 8182 x86_cpuid_get_model_id, 8183 x86_cpuid_set_model_id); 8184 object_class_property_add(oc, "tsc-frequency", "int", 8185 x86_cpuid_get_tsc_freq, 8186 x86_cpuid_set_tsc_freq, NULL, NULL); 8187 /* 8188 * The "unavailable-features" property has the same semantics as 8189 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8190 * QMP command: they list the features that would have prevented the 8191 * CPU from running if the "enforce" flag was set. 8192 */ 8193 object_class_property_add(oc, "unavailable-features", "strList", 8194 x86_cpu_get_unavailable_features, 8195 NULL, NULL, NULL); 8196 8197 #if !defined(CONFIG_USER_ONLY) 8198 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8199 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8200 #endif 8201 8202 for (w = 0; w < FEATURE_WORDS; w++) { 8203 int bitnr; 8204 for (bitnr = 0; bitnr < 64; bitnr++) { 8205 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8206 } 8207 } 8208 } 8209 8210 static const TypeInfo x86_cpu_type_info = { 8211 .name = TYPE_X86_CPU, 8212 .parent = TYPE_CPU, 8213 .instance_size = sizeof(X86CPU), 8214 .instance_align = __alignof(X86CPU), 8215 .instance_init = x86_cpu_initfn, 8216 .instance_post_init = x86_cpu_post_initfn, 8217 8218 .abstract = true, 8219 .class_size = sizeof(X86CPUClass), 8220 .class_init = x86_cpu_common_class_init, 8221 }; 8222 8223 /* "base" CPU model, used by query-cpu-model-expansion */ 8224 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8225 { 8226 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8227 8228 xcc->static_model = true; 8229 xcc->migration_safe = true; 8230 xcc->model_description = "base CPU model type with no features enabled"; 8231 xcc->ordering = 8; 8232 } 8233 8234 static const TypeInfo x86_base_cpu_type_info = { 8235 .name = X86_CPU_TYPE_NAME("base"), 8236 .parent = TYPE_X86_CPU, 8237 .class_init = x86_cpu_base_class_init, 8238 }; 8239 8240 static void x86_cpu_register_types(void) 8241 { 8242 int i; 8243 8244 type_register_static(&x86_cpu_type_info); 8245 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8246 x86_register_cpudef_types(&builtin_x86_defs[i]); 8247 } 8248 type_register_static(&max_x86_cpu_type_info); 8249 type_register_static(&x86_base_cpu_type_info); 8250 } 8251 8252 type_init(x86_cpu_register_types) 8253