1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "sysemu/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 51 /* Helpers for building CPUID[2] descriptors: */ 52 53 struct CPUID2CacheDescriptorInfo { 54 enum CacheType type; 55 int level; 56 int size; 57 int line_size; 58 int associativity; 59 }; 60 61 /* 62 * Known CPUID 2 cache descriptors. 63 * From Intel SDM Volume 2A, CPUID instruction 64 */ 65 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 67 .associativity = 4, .line_size = 32, }, 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 73 .associativity = 2, .line_size = 32, }, 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 79 .associativity = 6, .line_size = 64, }, 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 81 .associativity = 2, .line_size = 64, }, 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 83 .associativity = 8, .line_size = 64, }, 84 /* lines per sector is not supported cpuid2_cache_descriptor(), 85 * so descriptors 0x22, 0x23 are not included 86 */ 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 88 .associativity = 16, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x25, 0x20 are not included 91 */ 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 93 .associativity = 8, .line_size = 64, }, 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 107 .associativity = 4, .line_size = 64, }, 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 122 .associativity = 24, .line_size = 64, }, 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 8, .line_size = 64, }, 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 132 .associativity = 4, .line_size = 64, }, 133 /* lines per sector is not supported cpuid2_cache_descriptor(), 134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 135 */ 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 2, .line_size = 64, }, 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 64, }, 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 }; 185 186 /* 187 * "CPUID leaf 2 does not report cache descriptor information, 188 * use CPUID leaf 4 to query cache parameters" 189 */ 190 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 191 192 /* 193 * Return a CPUID 2 cache descriptor for a given cache. 194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 195 */ 196 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 197 { 198 int i; 199 200 assert(cache->size > 0); 201 assert(cache->level > 0); 202 assert(cache->line_size > 0); 203 assert(cache->associativity > 0); 204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 206 if (d->level == cache->level && d->type == cache->type && 207 d->size == cache->size && d->line_size == cache->line_size && 208 d->associativity == cache->associativity) { 209 return i; 210 } 211 } 212 213 return CACHE_DESCRIPTOR_UNAVAILABLE; 214 } 215 216 /* CPUID Leaf 4 constants: */ 217 218 /* EAX: */ 219 #define CACHE_TYPE_D 1 220 #define CACHE_TYPE_I 2 221 #define CACHE_TYPE_UNIFIED 3 222 223 #define CACHE_LEVEL(l) (l << 5) 224 225 #define CACHE_SELF_INIT_LEVEL (1 << 8) 226 227 /* EDX: */ 228 #define CACHE_NO_INVD_SHARING (1 << 0) 229 #define CACHE_INCLUSIVE (1 << 1) 230 #define CACHE_COMPLEX_IDX (1 << 2) 231 232 /* Encode CacheType for CPUID[4].EAX */ 233 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 236 0 /* Invalid value */) 237 238 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 239 enum CPUTopoLevel share_level) 240 { 241 uint32_t num_ids = 0; 242 243 switch (share_level) { 244 case CPU_TOPO_LEVEL_CORE: 245 num_ids = 1 << apicid_core_offset(topo_info); 246 break; 247 case CPU_TOPO_LEVEL_DIE: 248 num_ids = 1 << apicid_die_offset(topo_info); 249 break; 250 case CPU_TOPO_LEVEL_PACKAGE: 251 num_ids = 1 << apicid_pkg_offset(topo_info); 252 break; 253 default: 254 /* 255 * Currently there is no use case for SMT and MODULE, so use 256 * assert directly to facilitate debugging. 257 */ 258 g_assert_not_reached(); 259 } 260 261 return num_ids - 1; 262 } 263 264 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 265 { 266 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 267 apicid_core_offset(topo_info)); 268 return num_cores - 1; 269 } 270 271 /* Encode cache info for CPUID[4] */ 272 static void encode_cache_cpuid4(CPUCacheInfo *cache, 273 X86CPUTopoInfo *topo_info, 274 uint32_t *eax, uint32_t *ebx, 275 uint32_t *ecx, uint32_t *edx) 276 { 277 assert(cache->size == cache->line_size * cache->associativity * 278 cache->partitions * cache->sets); 279 280 *eax = CACHE_TYPE(cache->type) | 281 CACHE_LEVEL(cache->level) | 282 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 283 (max_core_ids_in_package(topo_info) << 26) | 284 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 285 286 assert(cache->line_size > 0); 287 assert(cache->partitions > 0); 288 assert(cache->associativity > 0); 289 /* We don't implement fully-associative caches */ 290 assert(cache->associativity < cache->sets); 291 *ebx = (cache->line_size - 1) | 292 ((cache->partitions - 1) << 12) | 293 ((cache->associativity - 1) << 22); 294 295 assert(cache->sets > 0); 296 *ecx = cache->sets - 1; 297 298 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 299 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 300 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 301 } 302 303 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 304 enum CPUTopoLevel topo_level) 305 { 306 switch (topo_level) { 307 case CPU_TOPO_LEVEL_SMT: 308 return 1; 309 case CPU_TOPO_LEVEL_CORE: 310 return topo_info->threads_per_core; 311 case CPU_TOPO_LEVEL_MODULE: 312 return topo_info->threads_per_core * topo_info->cores_per_module; 313 case CPU_TOPO_LEVEL_DIE: 314 return topo_info->threads_per_core * topo_info->cores_per_module * 315 topo_info->modules_per_die; 316 case CPU_TOPO_LEVEL_PACKAGE: 317 return topo_info->threads_per_core * topo_info->cores_per_module * 318 topo_info->modules_per_die * topo_info->dies_per_pkg; 319 default: 320 g_assert_not_reached(); 321 } 322 return 0; 323 } 324 325 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 326 enum CPUTopoLevel topo_level) 327 { 328 switch (topo_level) { 329 case CPU_TOPO_LEVEL_SMT: 330 return 0; 331 case CPU_TOPO_LEVEL_CORE: 332 return apicid_core_offset(topo_info); 333 case CPU_TOPO_LEVEL_MODULE: 334 return apicid_module_offset(topo_info); 335 case CPU_TOPO_LEVEL_DIE: 336 return apicid_die_offset(topo_info); 337 case CPU_TOPO_LEVEL_PACKAGE: 338 return apicid_pkg_offset(topo_info); 339 default: 340 g_assert_not_reached(); 341 } 342 return 0; 343 } 344 345 static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) 346 { 347 switch (topo_level) { 348 case CPU_TOPO_LEVEL_INVALID: 349 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 350 case CPU_TOPO_LEVEL_SMT: 351 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 352 case CPU_TOPO_LEVEL_CORE: 353 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 354 case CPU_TOPO_LEVEL_MODULE: 355 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 356 case CPU_TOPO_LEVEL_DIE: 357 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 358 default: 359 /* Other types are not supported in QEMU. */ 360 g_assert_not_reached(); 361 } 362 return 0; 363 } 364 365 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 366 X86CPUTopoInfo *topo_info, 367 uint32_t *eax, uint32_t *ebx, 368 uint32_t *ecx, uint32_t *edx) 369 { 370 X86CPU *cpu = env_archcpu(env); 371 unsigned long level, next_level; 372 uint32_t num_threads_next_level, offset_next_level; 373 374 assert(count + 1 < CPU_TOPO_LEVEL_MAX); 375 376 /* 377 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 378 * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). 379 */ 380 level = CPU_TOPO_LEVEL_INVALID; 381 for (int i = 0; i <= count; i++) { 382 level = find_next_bit(env->avail_cpu_topo, 383 CPU_TOPO_LEVEL_PACKAGE, 384 level + 1); 385 386 /* 387 * CPUID[0x1f] doesn't explicitly encode the package level, 388 * and it just encodes the invalid level (all fields are 0) 389 * into the last subleaf of 0x1f. 390 */ 391 if (level == CPU_TOPO_LEVEL_PACKAGE) { 392 level = CPU_TOPO_LEVEL_INVALID; 393 break; 394 } 395 } 396 397 if (level == CPU_TOPO_LEVEL_INVALID) { 398 num_threads_next_level = 0; 399 offset_next_level = 0; 400 } else { 401 next_level = find_next_bit(env->avail_cpu_topo, 402 CPU_TOPO_LEVEL_PACKAGE, 403 level + 1); 404 num_threads_next_level = num_threads_by_topo_level(topo_info, 405 next_level); 406 offset_next_level = apicid_offset_by_topo_level(topo_info, 407 next_level); 408 } 409 410 *eax = offset_next_level; 411 /* The count (bits 15-00) doesn't need to be reliable. */ 412 *ebx = num_threads_next_level & 0xffff; 413 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 414 *edx = cpu->apic_id; 415 416 assert(!(*eax & ~0x1f)); 417 } 418 419 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 420 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 421 { 422 assert(cache->size % 1024 == 0); 423 assert(cache->lines_per_tag > 0); 424 assert(cache->associativity > 0); 425 assert(cache->line_size > 0); 426 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 427 (cache->lines_per_tag << 8) | (cache->line_size); 428 } 429 430 #define ASSOC_FULL 0xFF 431 432 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 433 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 434 a == 2 ? 0x2 : \ 435 a == 4 ? 0x4 : \ 436 a == 8 ? 0x6 : \ 437 a == 16 ? 0x8 : \ 438 a == 32 ? 0xA : \ 439 a == 48 ? 0xB : \ 440 a == 64 ? 0xC : \ 441 a == 96 ? 0xD : \ 442 a == 128 ? 0xE : \ 443 a == ASSOC_FULL ? 0xF : \ 444 0 /* invalid value */) 445 446 /* 447 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 448 * @l3 can be NULL. 449 */ 450 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 451 CPUCacheInfo *l3, 452 uint32_t *ecx, uint32_t *edx) 453 { 454 assert(l2->size % 1024 == 0); 455 assert(l2->associativity > 0); 456 assert(l2->lines_per_tag > 0); 457 assert(l2->line_size > 0); 458 *ecx = ((l2->size / 1024) << 16) | 459 (AMD_ENC_ASSOC(l2->associativity) << 12) | 460 (l2->lines_per_tag << 8) | (l2->line_size); 461 462 if (l3) { 463 assert(l3->size % (512 * 1024) == 0); 464 assert(l3->associativity > 0); 465 assert(l3->lines_per_tag > 0); 466 assert(l3->line_size > 0); 467 *edx = ((l3->size / (512 * 1024)) << 18) | 468 (AMD_ENC_ASSOC(l3->associativity) << 12) | 469 (l3->lines_per_tag << 8) | (l3->line_size); 470 } else { 471 *edx = 0; 472 } 473 } 474 475 /* Encode cache info for CPUID[8000001D] */ 476 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 477 X86CPUTopoInfo *topo_info, 478 uint32_t *eax, uint32_t *ebx, 479 uint32_t *ecx, uint32_t *edx) 480 { 481 assert(cache->size == cache->line_size * cache->associativity * 482 cache->partitions * cache->sets); 483 484 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 485 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 486 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 487 488 assert(cache->line_size > 0); 489 assert(cache->partitions > 0); 490 assert(cache->associativity > 0); 491 /* We don't implement fully-associative caches */ 492 assert(cache->associativity < cache->sets); 493 *ebx = (cache->line_size - 1) | 494 ((cache->partitions - 1) << 12) | 495 ((cache->associativity - 1) << 22); 496 497 assert(cache->sets > 0); 498 *ecx = cache->sets - 1; 499 500 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 501 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 502 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 503 } 504 505 /* Encode cache info for CPUID[8000001E] */ 506 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 507 uint32_t *eax, uint32_t *ebx, 508 uint32_t *ecx, uint32_t *edx) 509 { 510 X86CPUTopoIDs topo_ids; 511 512 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 513 514 *eax = cpu->apic_id; 515 516 /* 517 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 518 * Read-only. Reset: 0000_XXXXh. 519 * See Core::X86::Cpuid::ExtApicId. 520 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 521 * Bits Description 522 * 31:16 Reserved. 523 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 524 * The number of threads per core is ThreadsPerCore+1. 525 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 526 * 527 * NOTE: CoreId is already part of apic_id. Just use it. We can 528 * use all the 8 bits to represent the core_id here. 529 */ 530 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 531 532 /* 533 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 534 * Read-only. Reset: 0000_0XXXh. 535 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 536 * Bits Description 537 * 31:11 Reserved. 538 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 539 * ValidValues: 540 * Value Description 541 * 0h 1 node per processor. 542 * 7h-1h Reserved. 543 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 544 * 545 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 546 * But users can create more nodes than the actual hardware can 547 * support. To genaralize we can use all the upper 8 bits for nodes. 548 * NodeId is combination of node and socket_id which is already decoded 549 * in apic_id. Just use it by shifting. 550 */ 551 if (cpu->legacy_multi_node) { 552 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 553 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 554 } else { 555 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 556 } 557 558 *edx = 0; 559 } 560 561 /* 562 * Definitions of the hardcoded cache entries we expose: 563 * These are legacy cache values. If there is a need to change any 564 * of these values please use builtin_x86_defs 565 */ 566 567 /* L1 data cache: */ 568 static CPUCacheInfo legacy_l1d_cache = { 569 .type = DATA_CACHE, 570 .level = 1, 571 .size = 32 * KiB, 572 .self_init = 1, 573 .line_size = 64, 574 .associativity = 8, 575 .sets = 64, 576 .partitions = 1, 577 .no_invd_sharing = true, 578 .share_level = CPU_TOPO_LEVEL_CORE, 579 }; 580 581 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 582 static CPUCacheInfo legacy_l1d_cache_amd = { 583 .type = DATA_CACHE, 584 .level = 1, 585 .size = 64 * KiB, 586 .self_init = 1, 587 .line_size = 64, 588 .associativity = 2, 589 .sets = 512, 590 .partitions = 1, 591 .lines_per_tag = 1, 592 .no_invd_sharing = true, 593 .share_level = CPU_TOPO_LEVEL_CORE, 594 }; 595 596 /* L1 instruction cache: */ 597 static CPUCacheInfo legacy_l1i_cache = { 598 .type = INSTRUCTION_CACHE, 599 .level = 1, 600 .size = 32 * KiB, 601 .self_init = 1, 602 .line_size = 64, 603 .associativity = 8, 604 .sets = 64, 605 .partitions = 1, 606 .no_invd_sharing = true, 607 .share_level = CPU_TOPO_LEVEL_CORE, 608 }; 609 610 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 611 static CPUCacheInfo legacy_l1i_cache_amd = { 612 .type = INSTRUCTION_CACHE, 613 .level = 1, 614 .size = 64 * KiB, 615 .self_init = 1, 616 .line_size = 64, 617 .associativity = 2, 618 .sets = 512, 619 .partitions = 1, 620 .lines_per_tag = 1, 621 .no_invd_sharing = true, 622 .share_level = CPU_TOPO_LEVEL_CORE, 623 }; 624 625 /* Level 2 unified cache: */ 626 static CPUCacheInfo legacy_l2_cache = { 627 .type = UNIFIED_CACHE, 628 .level = 2, 629 .size = 4 * MiB, 630 .self_init = 1, 631 .line_size = 64, 632 .associativity = 16, 633 .sets = 4096, 634 .partitions = 1, 635 .no_invd_sharing = true, 636 .share_level = CPU_TOPO_LEVEL_CORE, 637 }; 638 639 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 640 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 641 .type = UNIFIED_CACHE, 642 .level = 2, 643 .size = 2 * MiB, 644 .line_size = 64, 645 .associativity = 8, 646 .share_level = CPU_TOPO_LEVEL_INVALID, 647 }; 648 649 650 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 651 static CPUCacheInfo legacy_l2_cache_amd = { 652 .type = UNIFIED_CACHE, 653 .level = 2, 654 .size = 512 * KiB, 655 .line_size = 64, 656 .lines_per_tag = 1, 657 .associativity = 16, 658 .sets = 512, 659 .partitions = 1, 660 .share_level = CPU_TOPO_LEVEL_CORE, 661 }; 662 663 /* Level 3 unified cache: */ 664 static CPUCacheInfo legacy_l3_cache = { 665 .type = UNIFIED_CACHE, 666 .level = 3, 667 .size = 16 * MiB, 668 .line_size = 64, 669 .associativity = 16, 670 .sets = 16384, 671 .partitions = 1, 672 .lines_per_tag = 1, 673 .self_init = true, 674 .inclusive = true, 675 .complex_indexing = true, 676 .share_level = CPU_TOPO_LEVEL_DIE, 677 }; 678 679 /* TLB definitions: */ 680 681 #define L1_DTLB_2M_ASSOC 1 682 #define L1_DTLB_2M_ENTRIES 255 683 #define L1_DTLB_4K_ASSOC 1 684 #define L1_DTLB_4K_ENTRIES 255 685 686 #define L1_ITLB_2M_ASSOC 1 687 #define L1_ITLB_2M_ENTRIES 255 688 #define L1_ITLB_4K_ASSOC 1 689 #define L1_ITLB_4K_ENTRIES 255 690 691 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 692 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 693 #define L2_DTLB_4K_ASSOC 4 694 #define L2_DTLB_4K_ENTRIES 512 695 696 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 697 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 698 #define L2_ITLB_4K_ASSOC 4 699 #define L2_ITLB_4K_ENTRIES 512 700 701 /* CPUID Leaf 0x14 constants: */ 702 #define INTEL_PT_MAX_SUBLEAF 0x1 703 /* 704 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 705 * MSR can be accessed; 706 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 707 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 708 * of Intel PT MSRs across warm reset; 709 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 710 */ 711 #define INTEL_PT_MINIMAL_EBX 0xf 712 /* 713 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 714 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 715 * accessed; 716 * bit[01]: ToPA tables can hold any number of output entries, up to the 717 * maximum allowed by the MaskOrTableOffset field of 718 * IA32_RTIT_OUTPUT_MASK_PTRS; 719 * bit[02]: Support Single-Range Output scheme; 720 */ 721 #define INTEL_PT_MINIMAL_ECX 0x7 722 /* generated packets which contain IP payloads have LIP values */ 723 #define INTEL_PT_IP_LIP (1 << 31) 724 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 725 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 726 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 727 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 728 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 729 730 /* CPUID Leaf 0x1D constants: */ 731 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 732 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 733 #define INTEL_AMX_BYTES_PER_TILE 0x400 734 #define INTEL_AMX_BYTES_PER_ROW 0x40 735 #define INTEL_AMX_TILE_MAX_NAMES 0x8 736 #define INTEL_AMX_TILE_MAX_ROWS 0x10 737 738 /* CPUID Leaf 0x1E constants: */ 739 #define INTEL_AMX_TMUL_MAX_K 0x10 740 #define INTEL_AMX_TMUL_MAX_N 0x40 741 742 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 743 uint32_t vendor2, uint32_t vendor3) 744 { 745 int i; 746 for (i = 0; i < 4; i++) { 747 dst[i] = vendor1 >> (8 * i); 748 dst[i + 4] = vendor2 >> (8 * i); 749 dst[i + 8] = vendor3 >> (8 * i); 750 } 751 dst[CPUID_VENDOR_SZ] = '\0'; 752 } 753 754 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 755 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 756 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 757 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 758 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 759 CPUID_PSE36 | CPUID_FXSR) 760 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 761 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 762 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 763 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 764 CPUID_PAE | CPUID_SEP | CPUID_APIC) 765 766 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 767 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 768 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 769 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 770 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 771 /* partly implemented: 772 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 773 /* missing: 774 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 775 776 /* 777 * Kernel-only features that can be shown to usermode programs even if 778 * they aren't actually supported by TCG, because qemu-user only runs 779 * in CPL=3; remove them if they are ever implemented for system emulation. 780 */ 781 #if defined CONFIG_USER_ONLY 782 #define CPUID_EXT_KERNEL_FEATURES \ 783 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 784 #else 785 #define CPUID_EXT_KERNEL_FEATURES 0 786 #endif 787 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 788 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 789 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 790 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 791 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 792 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 793 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 794 /* missing: 795 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 796 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 797 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 798 CPUID_EXT_TSC_DEADLINE_TIMER 799 */ 800 801 #ifdef TARGET_X86_64 802 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 803 #else 804 #define TCG_EXT2_X86_64_FEATURES 0 805 #endif 806 807 /* 808 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 809 * in usermode or by 32-bit programs. Those are added to supported 810 * TCG features unconditionally in user-mode emulation mode. This may 811 * indeed seem strange or incorrect, but it works because code running 812 * under usermode emulation cannot access them. 813 * 814 * Even for long mode, qemu-i386 is not running "a userspace program on a 815 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 816 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 817 * but again the difference is only visible in kernel mode. 818 */ 819 #if defined CONFIG_LINUX_USER 820 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 821 #elif defined CONFIG_USER_ONLY 822 /* FIXME: Long mode not yet supported for i386 bsd-user */ 823 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 824 #else 825 #define CPUID_EXT2_KERNEL_FEATURES 0 826 #endif 827 828 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 829 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 830 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 831 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 832 CPUID_EXT2_KERNEL_FEATURES) 833 834 #if defined CONFIG_USER_ONLY 835 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 836 #else 837 #define CPUID_EXT3_KERNEL_FEATURES 0 838 #endif 839 840 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 841 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 842 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 843 844 #define TCG_EXT4_FEATURES 0 845 846 #if defined CONFIG_USER_ONLY 847 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 848 #else 849 #define CPUID_SVM_KERNEL_FEATURES 0 850 #endif 851 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 852 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 853 854 #define TCG_KVM_FEATURES 0 855 856 #if defined CONFIG_USER_ONLY 857 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 858 #else 859 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 860 #endif 861 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 862 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 863 CPUID_7_0_EBX_CLFLUSHOPT | \ 864 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 865 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 866 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 867 /* missing: 868 CPUID_7_0_EBX_HLE 869 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 870 871 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 872 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 873 #else 874 #define TCG_7_0_ECX_RDPID 0 875 #endif 876 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 877 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 878 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 879 TCG_7_0_ECX_RDPID) 880 881 #if defined CONFIG_USER_ONLY 882 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 883 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 884 #else 885 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 886 #endif 887 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 888 889 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 890 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 891 #define TCG_7_1_EDX_FEATURES 0 892 #define TCG_7_2_EDX_FEATURES 0 893 #define TCG_APM_FEATURES 0 894 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 895 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 896 /* missing: 897 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 898 #define TCG_14_0_ECX_FEATURES 0 899 #define TCG_SGX_12_0_EAX_FEATURES 0 900 #define TCG_SGX_12_0_EBX_FEATURES 0 901 #define TCG_SGX_12_1_EAX_FEATURES 0 902 903 #if defined CONFIG_USER_ONLY 904 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 905 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 906 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 907 CPUID_8000_0008_EBX_AMD_PSFD) 908 #else 909 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 910 #endif 911 912 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 913 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 914 915 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 916 [FEAT_1_EDX] = { 917 .type = CPUID_FEATURE_WORD, 918 .feat_names = { 919 "fpu", "vme", "de", "pse", 920 "tsc", "msr", "pae", "mce", 921 "cx8", "apic", NULL, "sep", 922 "mtrr", "pge", "mca", "cmov", 923 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 924 NULL, "ds" /* Intel dts */, "acpi", "mmx", 925 "fxsr", "sse", "sse2", "ss", 926 "ht" /* Intel htt */, "tm", "ia64", "pbe", 927 }, 928 .cpuid = {.eax = 1, .reg = R_EDX, }, 929 .tcg_features = TCG_FEATURES, 930 .no_autoenable_flags = CPUID_HT, 931 }, 932 [FEAT_1_ECX] = { 933 .type = CPUID_FEATURE_WORD, 934 .feat_names = { 935 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 936 "ds-cpl", "vmx", "smx", "est", 937 "tm2", "ssse3", "cid", NULL, 938 "fma", "cx16", "xtpr", "pdcm", 939 NULL, "pcid", "dca", "sse4.1", 940 "sse4.2", "x2apic", "movbe", "popcnt", 941 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 942 "avx", "f16c", "rdrand", "hypervisor", 943 }, 944 .cpuid = { .eax = 1, .reg = R_ECX, }, 945 .tcg_features = TCG_EXT_FEATURES, 946 }, 947 /* Feature names that are already defined on feature_name[] but 948 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 949 * names on feat_names below. They are copied automatically 950 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 951 */ 952 [FEAT_8000_0001_EDX] = { 953 .type = CPUID_FEATURE_WORD, 954 .feat_names = { 955 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 956 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 957 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 958 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 959 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 960 "nx", NULL, "mmxext", NULL /* mmx */, 961 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 962 NULL, "lm", "3dnowext", "3dnow", 963 }, 964 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 965 .tcg_features = TCG_EXT2_FEATURES, 966 }, 967 [FEAT_8000_0001_ECX] = { 968 .type = CPUID_FEATURE_WORD, 969 .feat_names = { 970 "lahf-lm", "cmp-legacy", "svm", "extapic", 971 "cr8legacy", "abm", "sse4a", "misalignsse", 972 "3dnowprefetch", "osvw", "ibs", "xop", 973 "skinit", "wdt", NULL, "lwp", 974 "fma4", "tce", NULL, "nodeid-msr", 975 NULL, "tbm", "topoext", "perfctr-core", 976 "perfctr-nb", NULL, NULL, NULL, 977 NULL, NULL, NULL, NULL, 978 }, 979 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 980 .tcg_features = TCG_EXT3_FEATURES, 981 /* 982 * TOPOEXT is always allowed but can't be enabled blindly by 983 * "-cpu host", as it requires consistent cache topology info 984 * to be provided so it doesn't confuse guests. 985 */ 986 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 987 }, 988 [FEAT_C000_0001_EDX] = { 989 .type = CPUID_FEATURE_WORD, 990 .feat_names = { 991 NULL, NULL, "xstore", "xstore-en", 992 NULL, NULL, "xcrypt", "xcrypt-en", 993 "ace2", "ace2-en", "phe", "phe-en", 994 "pmm", "pmm-en", NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 }, 1000 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1001 .tcg_features = TCG_EXT4_FEATURES, 1002 }, 1003 [FEAT_KVM] = { 1004 .type = CPUID_FEATURE_WORD, 1005 .feat_names = { 1006 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1007 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1008 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1009 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1010 NULL, NULL, NULL, NULL, 1011 NULL, NULL, NULL, NULL, 1012 "kvmclock-stable-bit", NULL, NULL, NULL, 1013 NULL, NULL, NULL, NULL, 1014 }, 1015 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1016 .tcg_features = TCG_KVM_FEATURES, 1017 }, 1018 [FEAT_KVM_HINTS] = { 1019 .type = CPUID_FEATURE_WORD, 1020 .feat_names = { 1021 "kvm-hint-dedicated", NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 }, 1030 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1031 .tcg_features = TCG_KVM_FEATURES, 1032 /* 1033 * KVM hints aren't auto-enabled by -cpu host, they need to be 1034 * explicitly enabled in the command-line. 1035 */ 1036 .no_autoenable_flags = ~0U, 1037 }, 1038 [FEAT_SVM] = { 1039 .type = CPUID_FEATURE_WORD, 1040 .feat_names = { 1041 "npt", "lbrv", "svm-lock", "nrip-save", 1042 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1043 NULL, NULL, "pause-filter", NULL, 1044 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1045 "vgif", NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, "vnmi", NULL, NULL, 1048 "svme-addr-chk", NULL, NULL, NULL, 1049 }, 1050 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1051 .tcg_features = TCG_SVM_FEATURES, 1052 }, 1053 [FEAT_7_0_EBX] = { 1054 .type = CPUID_FEATURE_WORD, 1055 .feat_names = { 1056 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1057 "hle", "avx2", NULL, "smep", 1058 "bmi2", "erms", "invpcid", "rtm", 1059 NULL, NULL, "mpx", NULL, 1060 "avx512f", "avx512dq", "rdseed", "adx", 1061 "smap", "avx512ifma", "pcommit", "clflushopt", 1062 "clwb", "intel-pt", "avx512pf", "avx512er", 1063 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1064 }, 1065 .cpuid = { 1066 .eax = 7, 1067 .needs_ecx = true, .ecx = 0, 1068 .reg = R_EBX, 1069 }, 1070 .tcg_features = TCG_7_0_EBX_FEATURES, 1071 }, 1072 [FEAT_7_0_ECX] = { 1073 .type = CPUID_FEATURE_WORD, 1074 .feat_names = { 1075 NULL, "avx512vbmi", "umip", "pku", 1076 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1077 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1078 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1079 "la57", NULL, NULL, NULL, 1080 NULL, NULL, "rdpid", NULL, 1081 "bus-lock-detect", "cldemote", NULL, "movdiri", 1082 "movdir64b", NULL, "sgxlc", "pks", 1083 }, 1084 .cpuid = { 1085 .eax = 7, 1086 .needs_ecx = true, .ecx = 0, 1087 .reg = R_ECX, 1088 }, 1089 .tcg_features = TCG_7_0_ECX_FEATURES, 1090 }, 1091 [FEAT_7_0_EDX] = { 1092 .type = CPUID_FEATURE_WORD, 1093 .feat_names = { 1094 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1095 "fsrm", NULL, NULL, NULL, 1096 "avx512-vp2intersect", NULL, "md-clear", NULL, 1097 NULL, NULL, "serialize", NULL, 1098 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1099 NULL, NULL, "amx-bf16", "avx512-fp16", 1100 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1101 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1102 }, 1103 .cpuid = { 1104 .eax = 7, 1105 .needs_ecx = true, .ecx = 0, 1106 .reg = R_EDX, 1107 }, 1108 .tcg_features = TCG_7_0_EDX_FEATURES, 1109 }, 1110 [FEAT_7_1_EAX] = { 1111 .type = CPUID_FEATURE_WORD, 1112 .feat_names = { 1113 NULL, NULL, NULL, NULL, 1114 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1115 NULL, NULL, "fzrm", "fsrs", 1116 "fsrc", NULL, NULL, NULL, 1117 NULL, "fred", "lkgs", "wrmsrns", 1118 NULL, "amx-fp16", NULL, "avx-ifma", 1119 NULL, NULL, "lam", NULL, 1120 NULL, NULL, NULL, NULL, 1121 }, 1122 .cpuid = { 1123 .eax = 7, 1124 .needs_ecx = true, .ecx = 1, 1125 .reg = R_EAX, 1126 }, 1127 .tcg_features = TCG_7_1_EAX_FEATURES, 1128 }, 1129 [FEAT_7_1_EDX] = { 1130 .type = CPUID_FEATURE_WORD, 1131 .feat_names = { 1132 NULL, NULL, NULL, NULL, 1133 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1134 "amx-complex", NULL, "avx-vnni-int16", NULL, 1135 NULL, NULL, "prefetchiti", NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .cpuid = { 1142 .eax = 7, 1143 .needs_ecx = true, .ecx = 1, 1144 .reg = R_EDX, 1145 }, 1146 .tcg_features = TCG_7_1_EDX_FEATURES, 1147 }, 1148 [FEAT_7_2_EDX] = { 1149 .type = CPUID_FEATURE_WORD, 1150 .feat_names = { 1151 NULL, NULL, NULL, NULL, 1152 NULL, "mcdt-no", NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 NULL, NULL, NULL, NULL, 1159 }, 1160 .cpuid = { 1161 .eax = 7, 1162 .needs_ecx = true, .ecx = 2, 1163 .reg = R_EDX, 1164 }, 1165 .tcg_features = TCG_7_2_EDX_FEATURES, 1166 }, 1167 [FEAT_8000_0007_EDX] = { 1168 .type = CPUID_FEATURE_WORD, 1169 .feat_names = { 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 "invtsc", NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 }, 1179 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1180 .tcg_features = TCG_APM_FEATURES, 1181 .unmigratable_flags = CPUID_APM_INVTSC, 1182 }, 1183 [FEAT_8000_0007_EBX] = { 1184 .type = CPUID_FEATURE_WORD, 1185 .feat_names = { 1186 "overflow-recov", "succor", NULL, NULL, 1187 NULL, NULL, NULL, NULL, 1188 NULL, NULL, NULL, NULL, 1189 NULL, NULL, NULL, NULL, 1190 NULL, NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 }, 1195 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1196 .tcg_features = 0, 1197 .unmigratable_flags = 0, 1198 }, 1199 [FEAT_8000_0008_EBX] = { 1200 .type = CPUID_FEATURE_WORD, 1201 .feat_names = { 1202 "clzero", NULL, "xsaveerptr", NULL, 1203 NULL, NULL, NULL, NULL, 1204 NULL, "wbnoinvd", NULL, NULL, 1205 "ibpb", NULL, "ibrs", "amd-stibp", 1206 NULL, "stibp-always-on", NULL, NULL, 1207 NULL, NULL, NULL, NULL, 1208 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1209 "amd-psfd", NULL, NULL, NULL, 1210 }, 1211 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1212 .tcg_features = TCG_8000_0008_EBX, 1213 .unmigratable_flags = 0, 1214 }, 1215 [FEAT_8000_0021_EAX] = { 1216 .type = CPUID_FEATURE_WORD, 1217 .feat_names = { 1218 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1219 NULL, NULL, "null-sel-clr-base", NULL, 1220 "auto-ibrs", NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 }, 1227 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1228 .tcg_features = 0, 1229 .unmigratable_flags = 0, 1230 }, 1231 [FEAT_XSAVE] = { 1232 .type = CPUID_FEATURE_WORD, 1233 .feat_names = { 1234 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1235 "xfd", NULL, NULL, NULL, 1236 NULL, NULL, NULL, NULL, 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 }, 1243 .cpuid = { 1244 .eax = 0xd, 1245 .needs_ecx = true, .ecx = 1, 1246 .reg = R_EAX, 1247 }, 1248 .tcg_features = TCG_XSAVE_FEATURES, 1249 }, 1250 [FEAT_XSAVE_XSS_LO] = { 1251 .type = CPUID_FEATURE_WORD, 1252 .feat_names = { 1253 NULL, NULL, NULL, NULL, 1254 NULL, NULL, NULL, NULL, 1255 NULL, NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 }, 1262 .cpuid = { 1263 .eax = 0xD, 1264 .needs_ecx = true, 1265 .ecx = 1, 1266 .reg = R_ECX, 1267 }, 1268 }, 1269 [FEAT_XSAVE_XSS_HI] = { 1270 .type = CPUID_FEATURE_WORD, 1271 .cpuid = { 1272 .eax = 0xD, 1273 .needs_ecx = true, 1274 .ecx = 1, 1275 .reg = R_EDX 1276 }, 1277 }, 1278 [FEAT_6_EAX] = { 1279 .type = CPUID_FEATURE_WORD, 1280 .feat_names = { 1281 NULL, NULL, "arat", NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, NULL, NULL, NULL, 1287 NULL, NULL, NULL, NULL, 1288 NULL, NULL, NULL, NULL, 1289 }, 1290 .cpuid = { .eax = 6, .reg = R_EAX, }, 1291 .tcg_features = TCG_6_EAX_FEATURES, 1292 }, 1293 [FEAT_XSAVE_XCR0_LO] = { 1294 .type = CPUID_FEATURE_WORD, 1295 .cpuid = { 1296 .eax = 0xD, 1297 .needs_ecx = true, .ecx = 0, 1298 .reg = R_EAX, 1299 }, 1300 .tcg_features = ~0U, 1301 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1302 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1303 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1304 XSTATE_PKRU_MASK, 1305 }, 1306 [FEAT_XSAVE_XCR0_HI] = { 1307 .type = CPUID_FEATURE_WORD, 1308 .cpuid = { 1309 .eax = 0xD, 1310 .needs_ecx = true, .ecx = 0, 1311 .reg = R_EDX, 1312 }, 1313 .tcg_features = ~0U, 1314 }, 1315 /*Below are MSR exposed features*/ 1316 [FEAT_ARCH_CAPABILITIES] = { 1317 .type = MSR_FEATURE_WORD, 1318 .feat_names = { 1319 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1320 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1321 "taa-no", NULL, NULL, NULL, 1322 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1323 NULL, "fb-clear", NULL, NULL, 1324 NULL, NULL, NULL, NULL, 1325 "pbrsb-no", NULL, "gds-no", "rfds-no", 1326 "rfds-clear", NULL, NULL, NULL, 1327 }, 1328 .msr = { 1329 .index = MSR_IA32_ARCH_CAPABILITIES, 1330 }, 1331 /* 1332 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1333 * cannot be read from user mode. Therefore, it has no impact 1334 > on any user-mode operation, and warnings about unsupported 1335 * features do not matter. 1336 */ 1337 .tcg_features = ~0U, 1338 }, 1339 [FEAT_CORE_CAPABILITY] = { 1340 .type = MSR_FEATURE_WORD, 1341 .feat_names = { 1342 NULL, NULL, NULL, NULL, 1343 NULL, "split-lock-detect", NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 NULL, NULL, NULL, NULL, 1350 }, 1351 .msr = { 1352 .index = MSR_IA32_CORE_CAPABILITY, 1353 }, 1354 }, 1355 [FEAT_PERF_CAPABILITIES] = { 1356 .type = MSR_FEATURE_WORD, 1357 .feat_names = { 1358 NULL, NULL, NULL, NULL, 1359 NULL, NULL, NULL, NULL, 1360 NULL, NULL, NULL, NULL, 1361 NULL, "full-width-write", NULL, NULL, 1362 NULL, NULL, NULL, NULL, 1363 NULL, NULL, NULL, NULL, 1364 NULL, NULL, NULL, NULL, 1365 NULL, NULL, NULL, NULL, 1366 }, 1367 .msr = { 1368 .index = MSR_IA32_PERF_CAPABILITIES, 1369 }, 1370 }, 1371 1372 [FEAT_VMX_PROCBASED_CTLS] = { 1373 .type = MSR_FEATURE_WORD, 1374 .feat_names = { 1375 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1376 NULL, NULL, NULL, "vmx-hlt-exit", 1377 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1378 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1379 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1380 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1381 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1382 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1383 }, 1384 .msr = { 1385 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1386 } 1387 }, 1388 1389 [FEAT_VMX_SECONDARY_CTLS] = { 1390 .type = MSR_FEATURE_WORD, 1391 .feat_names = { 1392 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1393 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1394 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1395 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1396 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1397 "vmx-xsaves", NULL, NULL, NULL, 1398 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1399 NULL, NULL, NULL, NULL, 1400 }, 1401 .msr = { 1402 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1403 } 1404 }, 1405 1406 [FEAT_VMX_PINBASED_CTLS] = { 1407 .type = MSR_FEATURE_WORD, 1408 .feat_names = { 1409 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1410 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL, NULL, NULL, 1417 }, 1418 .msr = { 1419 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1420 } 1421 }, 1422 1423 [FEAT_VMX_EXIT_CTLS] = { 1424 .type = MSR_FEATURE_WORD, 1425 /* 1426 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1427 * the LM CPUID bit. 1428 */ 1429 .feat_names = { 1430 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1431 NULL, NULL, NULL, NULL, 1432 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1433 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1434 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1435 "vmx-exit-save-efer", "vmx-exit-load-efer", 1436 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1437 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1438 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1439 }, 1440 .msr = { 1441 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1442 } 1443 }, 1444 1445 [FEAT_VMX_ENTRY_CTLS] = { 1446 .type = MSR_FEATURE_WORD, 1447 .feat_names = { 1448 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1449 NULL, NULL, NULL, NULL, 1450 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1451 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1452 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1453 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1454 NULL, NULL, NULL, NULL, 1455 NULL, NULL, NULL, NULL, 1456 }, 1457 .msr = { 1458 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1459 } 1460 }, 1461 1462 [FEAT_VMX_MISC] = { 1463 .type = MSR_FEATURE_WORD, 1464 .feat_names = { 1465 NULL, NULL, NULL, NULL, 1466 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1467 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1468 NULL, NULL, NULL, NULL, 1469 NULL, NULL, NULL, NULL, 1470 NULL, NULL, NULL, NULL, 1471 NULL, NULL, NULL, NULL, 1472 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1473 }, 1474 .msr = { 1475 .index = MSR_IA32_VMX_MISC, 1476 } 1477 }, 1478 1479 [FEAT_VMX_EPT_VPID_CAPS] = { 1480 .type = MSR_FEATURE_WORD, 1481 .feat_names = { 1482 "vmx-ept-execonly", NULL, NULL, NULL, 1483 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1484 NULL, NULL, NULL, NULL, 1485 NULL, NULL, NULL, NULL, 1486 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1487 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1488 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1489 NULL, NULL, NULL, NULL, 1490 "vmx-invvpid", NULL, NULL, NULL, 1491 NULL, NULL, NULL, NULL, 1492 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1493 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1494 NULL, NULL, NULL, NULL, 1495 NULL, NULL, NULL, NULL, 1496 NULL, NULL, NULL, NULL, 1497 NULL, NULL, NULL, NULL, 1498 NULL, NULL, NULL, NULL, 1499 }, 1500 .msr = { 1501 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1502 } 1503 }, 1504 1505 [FEAT_VMX_BASIC] = { 1506 .type = MSR_FEATURE_WORD, 1507 .feat_names = { 1508 [54] = "vmx-ins-outs", 1509 [55] = "vmx-true-ctls", 1510 [56] = "vmx-any-errcode", 1511 [58] = "vmx-nested-exception", 1512 }, 1513 .msr = { 1514 .index = MSR_IA32_VMX_BASIC, 1515 }, 1516 /* Just to be safe - we don't support setting the MSEG version field. */ 1517 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1518 }, 1519 1520 [FEAT_VMX_VMFUNC] = { 1521 .type = MSR_FEATURE_WORD, 1522 .feat_names = { 1523 [0] = "vmx-eptp-switching", 1524 }, 1525 .msr = { 1526 .index = MSR_IA32_VMX_VMFUNC, 1527 } 1528 }, 1529 1530 [FEAT_14_0_ECX] = { 1531 .type = CPUID_FEATURE_WORD, 1532 .feat_names = { 1533 NULL, NULL, NULL, NULL, 1534 NULL, NULL, NULL, NULL, 1535 NULL, NULL, NULL, NULL, 1536 NULL, NULL, NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, "intel-pt-lip", 1541 }, 1542 .cpuid = { 1543 .eax = 0x14, 1544 .needs_ecx = true, .ecx = 0, 1545 .reg = R_ECX, 1546 }, 1547 .tcg_features = TCG_14_0_ECX_FEATURES, 1548 }, 1549 1550 [FEAT_SGX_12_0_EAX] = { 1551 .type = CPUID_FEATURE_WORD, 1552 .feat_names = { 1553 "sgx1", "sgx2", NULL, NULL, 1554 NULL, NULL, NULL, NULL, 1555 NULL, NULL, NULL, "sgx-edeccssa", 1556 NULL, NULL, NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 }, 1562 .cpuid = { 1563 .eax = 0x12, 1564 .needs_ecx = true, .ecx = 0, 1565 .reg = R_EAX, 1566 }, 1567 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1568 }, 1569 1570 [FEAT_SGX_12_0_EBX] = { 1571 .type = CPUID_FEATURE_WORD, 1572 .feat_names = { 1573 "sgx-exinfo" , NULL, NULL, NULL, 1574 NULL, NULL, NULL, NULL, 1575 NULL, NULL, NULL, NULL, 1576 NULL, NULL, NULL, NULL, 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 }, 1582 .cpuid = { 1583 .eax = 0x12, 1584 .needs_ecx = true, .ecx = 0, 1585 .reg = R_EBX, 1586 }, 1587 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1588 }, 1589 1590 [FEAT_SGX_12_1_EAX] = { 1591 .type = CPUID_FEATURE_WORD, 1592 .feat_names = { 1593 NULL, "sgx-debug", "sgx-mode64", NULL, 1594 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1595 NULL, NULL, "sgx-aex-notify", NULL, 1596 NULL, NULL, NULL, NULL, 1597 NULL, NULL, NULL, NULL, 1598 NULL, NULL, NULL, NULL, 1599 NULL, NULL, NULL, NULL, 1600 NULL, NULL, NULL, NULL, 1601 }, 1602 .cpuid = { 1603 .eax = 0x12, 1604 .needs_ecx = true, .ecx = 1, 1605 .reg = R_EAX, 1606 }, 1607 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1608 }, 1609 }; 1610 1611 typedef struct FeatureMask { 1612 FeatureWord index; 1613 uint64_t mask; 1614 } FeatureMask; 1615 1616 typedef struct FeatureDep { 1617 FeatureMask from, to; 1618 } FeatureDep; 1619 1620 static FeatureDep feature_dependencies[] = { 1621 { 1622 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1623 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1624 }, 1625 { 1626 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1627 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1628 }, 1629 { 1630 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1631 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1632 }, 1633 { 1634 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1635 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1636 }, 1637 { 1638 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1639 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1640 }, 1641 { 1642 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1643 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1644 }, 1645 { 1646 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1647 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1648 }, 1649 { 1650 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1651 .to = { FEAT_VMX_MISC, ~0ull }, 1652 }, 1653 { 1654 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1655 .to = { FEAT_VMX_BASIC, ~0ull }, 1656 }, 1657 { 1658 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1659 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1660 }, 1661 { 1662 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1663 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1664 }, 1665 { 1666 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1667 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1668 }, 1669 { 1670 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1671 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1672 }, 1673 { 1674 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1675 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1676 }, 1677 { 1678 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1679 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1680 }, 1681 { 1682 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1683 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1684 }, 1685 { 1686 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1687 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1688 }, 1689 { 1690 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1691 .to = { FEAT_14_0_ECX, ~0ull }, 1692 }, 1693 { 1694 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1695 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1696 }, 1697 { 1698 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1699 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1700 }, 1701 { 1702 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1703 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1704 }, 1705 { 1706 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1707 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1708 }, 1709 { 1710 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1711 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1712 }, 1713 { 1714 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1715 .to = { FEAT_SVM, ~0ull }, 1716 }, 1717 { 1718 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1719 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1720 }, 1721 { 1722 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1723 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1724 }, 1725 { 1726 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1727 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1728 }, 1729 { 1730 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1731 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1732 }, 1733 }; 1734 1735 typedef struct X86RegisterInfo32 { 1736 /* Name of register */ 1737 const char *name; 1738 /* QAPI enum value register */ 1739 X86CPURegister32 qapi_enum; 1740 } X86RegisterInfo32; 1741 1742 #define REGISTER(reg) \ 1743 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1744 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1745 REGISTER(EAX), 1746 REGISTER(ECX), 1747 REGISTER(EDX), 1748 REGISTER(EBX), 1749 REGISTER(ESP), 1750 REGISTER(EBP), 1751 REGISTER(ESI), 1752 REGISTER(EDI), 1753 }; 1754 #undef REGISTER 1755 1756 /* CPUID feature bits available in XSS */ 1757 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1758 1759 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1760 [XSTATE_FP_BIT] = { 1761 /* x87 FP state component is always enabled if XSAVE is supported */ 1762 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1763 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1764 }, 1765 [XSTATE_SSE_BIT] = { 1766 /* SSE state component is always enabled if XSAVE is supported */ 1767 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1768 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1769 }, 1770 [XSTATE_YMM_BIT] = 1771 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1772 .size = sizeof(XSaveAVX) }, 1773 [XSTATE_BNDREGS_BIT] = 1774 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1775 .size = sizeof(XSaveBNDREG) }, 1776 [XSTATE_BNDCSR_BIT] = 1777 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1778 .size = sizeof(XSaveBNDCSR) }, 1779 [XSTATE_OPMASK_BIT] = 1780 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1781 .size = sizeof(XSaveOpmask) }, 1782 [XSTATE_ZMM_Hi256_BIT] = 1783 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1784 .size = sizeof(XSaveZMM_Hi256) }, 1785 [XSTATE_Hi16_ZMM_BIT] = 1786 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1787 .size = sizeof(XSaveHi16_ZMM) }, 1788 [XSTATE_PKRU_BIT] = 1789 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1790 .size = sizeof(XSavePKRU) }, 1791 [XSTATE_ARCH_LBR_BIT] = { 1792 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1793 .offset = 0 /*supervisor mode component, offset = 0 */, 1794 .size = sizeof(XSavesArchLBR) }, 1795 [XSTATE_XTILE_CFG_BIT] = { 1796 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1797 .size = sizeof(XSaveXTILECFG), 1798 }, 1799 [XSTATE_XTILE_DATA_BIT] = { 1800 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1801 .size = sizeof(XSaveXTILEDATA) 1802 }, 1803 }; 1804 1805 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1806 { 1807 uint64_t ret = x86_ext_save_areas[0].size; 1808 const ExtSaveArea *esa; 1809 uint32_t offset = 0; 1810 int i; 1811 1812 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1813 esa = &x86_ext_save_areas[i]; 1814 if ((mask >> i) & 1) { 1815 offset = compacted ? ret : esa->offset; 1816 ret = MAX(ret, offset + esa->size); 1817 } 1818 } 1819 return ret; 1820 } 1821 1822 static inline bool accel_uses_host_cpuid(void) 1823 { 1824 return kvm_enabled() || hvf_enabled(); 1825 } 1826 1827 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1828 { 1829 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1830 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1831 } 1832 1833 /* Return name of 32-bit register, from a R_* constant */ 1834 static const char *get_register_name_32(unsigned int reg) 1835 { 1836 if (reg >= CPU_NB_REGS32) { 1837 return NULL; 1838 } 1839 return x86_reg_info_32[reg].name; 1840 } 1841 1842 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1843 { 1844 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1845 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1846 } 1847 1848 /* 1849 * Returns the set of feature flags that are supported and migratable by 1850 * QEMU, for a given FeatureWord. 1851 */ 1852 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1853 { 1854 FeatureWordInfo *wi = &feature_word_info[w]; 1855 uint64_t r = 0; 1856 int i; 1857 1858 for (i = 0; i < 64; i++) { 1859 uint64_t f = 1ULL << i; 1860 1861 /* If the feature name is known, it is implicitly considered migratable, 1862 * unless it is explicitly set in unmigratable_flags */ 1863 if ((wi->migratable_flags & f) || 1864 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1865 r |= f; 1866 } 1867 } 1868 return r; 1869 } 1870 1871 void host_cpuid(uint32_t function, uint32_t count, 1872 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1873 { 1874 uint32_t vec[4]; 1875 1876 #ifdef __x86_64__ 1877 asm volatile("cpuid" 1878 : "=a"(vec[0]), "=b"(vec[1]), 1879 "=c"(vec[2]), "=d"(vec[3]) 1880 : "0"(function), "c"(count) : "cc"); 1881 #elif defined(__i386__) 1882 asm volatile("pusha \n\t" 1883 "cpuid \n\t" 1884 "mov %%eax, 0(%2) \n\t" 1885 "mov %%ebx, 4(%2) \n\t" 1886 "mov %%ecx, 8(%2) \n\t" 1887 "mov %%edx, 12(%2) \n\t" 1888 "popa" 1889 : : "a"(function), "c"(count), "S"(vec) 1890 : "memory", "cc"); 1891 #else 1892 abort(); 1893 #endif 1894 1895 if (eax) 1896 *eax = vec[0]; 1897 if (ebx) 1898 *ebx = vec[1]; 1899 if (ecx) 1900 *ecx = vec[2]; 1901 if (edx) 1902 *edx = vec[3]; 1903 } 1904 1905 /* CPU class name definitions: */ 1906 1907 /* Return type name for a given CPU model name 1908 * Caller is responsible for freeing the returned string. 1909 */ 1910 static char *x86_cpu_type_name(const char *model_name) 1911 { 1912 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1913 } 1914 1915 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1916 { 1917 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1918 return object_class_by_name(typename); 1919 } 1920 1921 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1922 { 1923 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1924 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1925 return cpu_model_from_type(class_name); 1926 } 1927 1928 typedef struct X86CPUVersionDefinition { 1929 X86CPUVersion version; 1930 const char *alias; 1931 const char *note; 1932 PropValue *props; 1933 const CPUCaches *const cache_info; 1934 } X86CPUVersionDefinition; 1935 1936 /* Base definition for a CPU model */ 1937 typedef struct X86CPUDefinition { 1938 const char *name; 1939 uint32_t level; 1940 uint32_t xlevel; 1941 /* vendor is zero-terminated, 12 character ASCII string */ 1942 char vendor[CPUID_VENDOR_SZ + 1]; 1943 int family; 1944 int model; 1945 int stepping; 1946 FeatureWordArray features; 1947 const char *model_id; 1948 const CPUCaches *const cache_info; 1949 /* 1950 * Definitions for alternative versions of CPU model. 1951 * List is terminated by item with version == 0. 1952 * If NULL, version 1 will be registered automatically. 1953 */ 1954 const X86CPUVersionDefinition *versions; 1955 const char *deprecation_note; 1956 } X86CPUDefinition; 1957 1958 /* Reference to a specific CPU model version */ 1959 struct X86CPUModel { 1960 /* Base CPU definition */ 1961 const X86CPUDefinition *cpudef; 1962 /* CPU model version */ 1963 X86CPUVersion version; 1964 const char *note; 1965 /* 1966 * If true, this is an alias CPU model. 1967 * This matters only for "-cpu help" and query-cpu-definitions 1968 */ 1969 bool is_alias; 1970 }; 1971 1972 /* Get full model name for CPU version */ 1973 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1974 X86CPUVersion version) 1975 { 1976 assert(version > 0); 1977 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1978 } 1979 1980 static const X86CPUVersionDefinition * 1981 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1982 { 1983 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1984 static const X86CPUVersionDefinition default_version_list[] = { 1985 { 1 }, 1986 { /* end of list */ } 1987 }; 1988 1989 return def->versions ?: default_version_list; 1990 } 1991 1992 static const CPUCaches epyc_cache_info = { 1993 .l1d_cache = &(CPUCacheInfo) { 1994 .type = DATA_CACHE, 1995 .level = 1, 1996 .size = 32 * KiB, 1997 .line_size = 64, 1998 .associativity = 8, 1999 .partitions = 1, 2000 .sets = 64, 2001 .lines_per_tag = 1, 2002 .self_init = 1, 2003 .no_invd_sharing = true, 2004 .share_level = CPU_TOPO_LEVEL_CORE, 2005 }, 2006 .l1i_cache = &(CPUCacheInfo) { 2007 .type = INSTRUCTION_CACHE, 2008 .level = 1, 2009 .size = 64 * KiB, 2010 .line_size = 64, 2011 .associativity = 4, 2012 .partitions = 1, 2013 .sets = 256, 2014 .lines_per_tag = 1, 2015 .self_init = 1, 2016 .no_invd_sharing = true, 2017 .share_level = CPU_TOPO_LEVEL_CORE, 2018 }, 2019 .l2_cache = &(CPUCacheInfo) { 2020 .type = UNIFIED_CACHE, 2021 .level = 2, 2022 .size = 512 * KiB, 2023 .line_size = 64, 2024 .associativity = 8, 2025 .partitions = 1, 2026 .sets = 1024, 2027 .lines_per_tag = 1, 2028 .share_level = CPU_TOPO_LEVEL_CORE, 2029 }, 2030 .l3_cache = &(CPUCacheInfo) { 2031 .type = UNIFIED_CACHE, 2032 .level = 3, 2033 .size = 8 * MiB, 2034 .line_size = 64, 2035 .associativity = 16, 2036 .partitions = 1, 2037 .sets = 8192, 2038 .lines_per_tag = 1, 2039 .self_init = true, 2040 .inclusive = true, 2041 .complex_indexing = true, 2042 .share_level = CPU_TOPO_LEVEL_DIE, 2043 }, 2044 }; 2045 2046 static CPUCaches epyc_v4_cache_info = { 2047 .l1d_cache = &(CPUCacheInfo) { 2048 .type = DATA_CACHE, 2049 .level = 1, 2050 .size = 32 * KiB, 2051 .line_size = 64, 2052 .associativity = 8, 2053 .partitions = 1, 2054 .sets = 64, 2055 .lines_per_tag = 1, 2056 .self_init = 1, 2057 .no_invd_sharing = true, 2058 .share_level = CPU_TOPO_LEVEL_CORE, 2059 }, 2060 .l1i_cache = &(CPUCacheInfo) { 2061 .type = INSTRUCTION_CACHE, 2062 .level = 1, 2063 .size = 64 * KiB, 2064 .line_size = 64, 2065 .associativity = 4, 2066 .partitions = 1, 2067 .sets = 256, 2068 .lines_per_tag = 1, 2069 .self_init = 1, 2070 .no_invd_sharing = true, 2071 .share_level = CPU_TOPO_LEVEL_CORE, 2072 }, 2073 .l2_cache = &(CPUCacheInfo) { 2074 .type = UNIFIED_CACHE, 2075 .level = 2, 2076 .size = 512 * KiB, 2077 .line_size = 64, 2078 .associativity = 8, 2079 .partitions = 1, 2080 .sets = 1024, 2081 .lines_per_tag = 1, 2082 .share_level = CPU_TOPO_LEVEL_CORE, 2083 }, 2084 .l3_cache = &(CPUCacheInfo) { 2085 .type = UNIFIED_CACHE, 2086 .level = 3, 2087 .size = 8 * MiB, 2088 .line_size = 64, 2089 .associativity = 16, 2090 .partitions = 1, 2091 .sets = 8192, 2092 .lines_per_tag = 1, 2093 .self_init = true, 2094 .inclusive = true, 2095 .complex_indexing = false, 2096 .share_level = CPU_TOPO_LEVEL_DIE, 2097 }, 2098 }; 2099 2100 static const CPUCaches epyc_rome_cache_info = { 2101 .l1d_cache = &(CPUCacheInfo) { 2102 .type = DATA_CACHE, 2103 .level = 1, 2104 .size = 32 * KiB, 2105 .line_size = 64, 2106 .associativity = 8, 2107 .partitions = 1, 2108 .sets = 64, 2109 .lines_per_tag = 1, 2110 .self_init = 1, 2111 .no_invd_sharing = true, 2112 .share_level = CPU_TOPO_LEVEL_CORE, 2113 }, 2114 .l1i_cache = &(CPUCacheInfo) { 2115 .type = INSTRUCTION_CACHE, 2116 .level = 1, 2117 .size = 32 * KiB, 2118 .line_size = 64, 2119 .associativity = 8, 2120 .partitions = 1, 2121 .sets = 64, 2122 .lines_per_tag = 1, 2123 .self_init = 1, 2124 .no_invd_sharing = true, 2125 .share_level = CPU_TOPO_LEVEL_CORE, 2126 }, 2127 .l2_cache = &(CPUCacheInfo) { 2128 .type = UNIFIED_CACHE, 2129 .level = 2, 2130 .size = 512 * KiB, 2131 .line_size = 64, 2132 .associativity = 8, 2133 .partitions = 1, 2134 .sets = 1024, 2135 .lines_per_tag = 1, 2136 .share_level = CPU_TOPO_LEVEL_CORE, 2137 }, 2138 .l3_cache = &(CPUCacheInfo) { 2139 .type = UNIFIED_CACHE, 2140 .level = 3, 2141 .size = 16 * MiB, 2142 .line_size = 64, 2143 .associativity = 16, 2144 .partitions = 1, 2145 .sets = 16384, 2146 .lines_per_tag = 1, 2147 .self_init = true, 2148 .inclusive = true, 2149 .complex_indexing = true, 2150 .share_level = CPU_TOPO_LEVEL_DIE, 2151 }, 2152 }; 2153 2154 static const CPUCaches epyc_rome_v3_cache_info = { 2155 .l1d_cache = &(CPUCacheInfo) { 2156 .type = DATA_CACHE, 2157 .level = 1, 2158 .size = 32 * KiB, 2159 .line_size = 64, 2160 .associativity = 8, 2161 .partitions = 1, 2162 .sets = 64, 2163 .lines_per_tag = 1, 2164 .self_init = 1, 2165 .no_invd_sharing = true, 2166 .share_level = CPU_TOPO_LEVEL_CORE, 2167 }, 2168 .l1i_cache = &(CPUCacheInfo) { 2169 .type = INSTRUCTION_CACHE, 2170 .level = 1, 2171 .size = 32 * KiB, 2172 .line_size = 64, 2173 .associativity = 8, 2174 .partitions = 1, 2175 .sets = 64, 2176 .lines_per_tag = 1, 2177 .self_init = 1, 2178 .no_invd_sharing = true, 2179 .share_level = CPU_TOPO_LEVEL_CORE, 2180 }, 2181 .l2_cache = &(CPUCacheInfo) { 2182 .type = UNIFIED_CACHE, 2183 .level = 2, 2184 .size = 512 * KiB, 2185 .line_size = 64, 2186 .associativity = 8, 2187 .partitions = 1, 2188 .sets = 1024, 2189 .lines_per_tag = 1, 2190 .share_level = CPU_TOPO_LEVEL_CORE, 2191 }, 2192 .l3_cache = &(CPUCacheInfo) { 2193 .type = UNIFIED_CACHE, 2194 .level = 3, 2195 .size = 16 * MiB, 2196 .line_size = 64, 2197 .associativity = 16, 2198 .partitions = 1, 2199 .sets = 16384, 2200 .lines_per_tag = 1, 2201 .self_init = true, 2202 .inclusive = true, 2203 .complex_indexing = false, 2204 .share_level = CPU_TOPO_LEVEL_DIE, 2205 }, 2206 }; 2207 2208 static const CPUCaches epyc_milan_cache_info = { 2209 .l1d_cache = &(CPUCacheInfo) { 2210 .type = DATA_CACHE, 2211 .level = 1, 2212 .size = 32 * KiB, 2213 .line_size = 64, 2214 .associativity = 8, 2215 .partitions = 1, 2216 .sets = 64, 2217 .lines_per_tag = 1, 2218 .self_init = 1, 2219 .no_invd_sharing = true, 2220 .share_level = CPU_TOPO_LEVEL_CORE, 2221 }, 2222 .l1i_cache = &(CPUCacheInfo) { 2223 .type = INSTRUCTION_CACHE, 2224 .level = 1, 2225 .size = 32 * KiB, 2226 .line_size = 64, 2227 .associativity = 8, 2228 .partitions = 1, 2229 .sets = 64, 2230 .lines_per_tag = 1, 2231 .self_init = 1, 2232 .no_invd_sharing = true, 2233 .share_level = CPU_TOPO_LEVEL_CORE, 2234 }, 2235 .l2_cache = &(CPUCacheInfo) { 2236 .type = UNIFIED_CACHE, 2237 .level = 2, 2238 .size = 512 * KiB, 2239 .line_size = 64, 2240 .associativity = 8, 2241 .partitions = 1, 2242 .sets = 1024, 2243 .lines_per_tag = 1, 2244 .share_level = CPU_TOPO_LEVEL_CORE, 2245 }, 2246 .l3_cache = &(CPUCacheInfo) { 2247 .type = UNIFIED_CACHE, 2248 .level = 3, 2249 .size = 32 * MiB, 2250 .line_size = 64, 2251 .associativity = 16, 2252 .partitions = 1, 2253 .sets = 32768, 2254 .lines_per_tag = 1, 2255 .self_init = true, 2256 .inclusive = true, 2257 .complex_indexing = true, 2258 .share_level = CPU_TOPO_LEVEL_DIE, 2259 }, 2260 }; 2261 2262 static const CPUCaches epyc_milan_v2_cache_info = { 2263 .l1d_cache = &(CPUCacheInfo) { 2264 .type = DATA_CACHE, 2265 .level = 1, 2266 .size = 32 * KiB, 2267 .line_size = 64, 2268 .associativity = 8, 2269 .partitions = 1, 2270 .sets = 64, 2271 .lines_per_tag = 1, 2272 .self_init = 1, 2273 .no_invd_sharing = true, 2274 .share_level = CPU_TOPO_LEVEL_CORE, 2275 }, 2276 .l1i_cache = &(CPUCacheInfo) { 2277 .type = INSTRUCTION_CACHE, 2278 .level = 1, 2279 .size = 32 * KiB, 2280 .line_size = 64, 2281 .associativity = 8, 2282 .partitions = 1, 2283 .sets = 64, 2284 .lines_per_tag = 1, 2285 .self_init = 1, 2286 .no_invd_sharing = true, 2287 .share_level = CPU_TOPO_LEVEL_CORE, 2288 }, 2289 .l2_cache = &(CPUCacheInfo) { 2290 .type = UNIFIED_CACHE, 2291 .level = 2, 2292 .size = 512 * KiB, 2293 .line_size = 64, 2294 .associativity = 8, 2295 .partitions = 1, 2296 .sets = 1024, 2297 .lines_per_tag = 1, 2298 .share_level = CPU_TOPO_LEVEL_CORE, 2299 }, 2300 .l3_cache = &(CPUCacheInfo) { 2301 .type = UNIFIED_CACHE, 2302 .level = 3, 2303 .size = 32 * MiB, 2304 .line_size = 64, 2305 .associativity = 16, 2306 .partitions = 1, 2307 .sets = 32768, 2308 .lines_per_tag = 1, 2309 .self_init = true, 2310 .inclusive = true, 2311 .complex_indexing = false, 2312 .share_level = CPU_TOPO_LEVEL_DIE, 2313 }, 2314 }; 2315 2316 static const CPUCaches epyc_genoa_cache_info = { 2317 .l1d_cache = &(CPUCacheInfo) { 2318 .type = DATA_CACHE, 2319 .level = 1, 2320 .size = 32 * KiB, 2321 .line_size = 64, 2322 .associativity = 8, 2323 .partitions = 1, 2324 .sets = 64, 2325 .lines_per_tag = 1, 2326 .self_init = 1, 2327 .no_invd_sharing = true, 2328 .share_level = CPU_TOPO_LEVEL_CORE, 2329 }, 2330 .l1i_cache = &(CPUCacheInfo) { 2331 .type = INSTRUCTION_CACHE, 2332 .level = 1, 2333 .size = 32 * KiB, 2334 .line_size = 64, 2335 .associativity = 8, 2336 .partitions = 1, 2337 .sets = 64, 2338 .lines_per_tag = 1, 2339 .self_init = 1, 2340 .no_invd_sharing = true, 2341 .share_level = CPU_TOPO_LEVEL_CORE, 2342 }, 2343 .l2_cache = &(CPUCacheInfo) { 2344 .type = UNIFIED_CACHE, 2345 .level = 2, 2346 .size = 1 * MiB, 2347 .line_size = 64, 2348 .associativity = 8, 2349 .partitions = 1, 2350 .sets = 2048, 2351 .lines_per_tag = 1, 2352 .share_level = CPU_TOPO_LEVEL_CORE, 2353 }, 2354 .l3_cache = &(CPUCacheInfo) { 2355 .type = UNIFIED_CACHE, 2356 .level = 3, 2357 .size = 32 * MiB, 2358 .line_size = 64, 2359 .associativity = 16, 2360 .partitions = 1, 2361 .sets = 32768, 2362 .lines_per_tag = 1, 2363 .self_init = true, 2364 .inclusive = true, 2365 .complex_indexing = false, 2366 .share_level = CPU_TOPO_LEVEL_DIE, 2367 }, 2368 }; 2369 2370 /* The following VMX features are not supported by KVM and are left out in the 2371 * CPU definitions: 2372 * 2373 * Dual-monitor support (all processors) 2374 * Entry to SMM 2375 * Deactivate dual-monitor treatment 2376 * Number of CR3-target values 2377 * Shutdown activity state 2378 * Wait-for-SIPI activity state 2379 * PAUSE-loop exiting (Westmere and newer) 2380 * EPT-violation #VE (Broadwell and newer) 2381 * Inject event with insn length=0 (Skylake and newer) 2382 * Conceal non-root operation from PT 2383 * Conceal VM exits from PT 2384 * Conceal VM entries from PT 2385 * Enable ENCLS exiting 2386 * Mode-based execute control (XS/XU) 2387 * TSC scaling (Skylake Server and newer) 2388 * GPA translation for PT (IceLake and newer) 2389 * User wait and pause 2390 * ENCLV exiting 2391 * Load IA32_RTIT_CTL 2392 * Clear IA32_RTIT_CTL 2393 * Advanced VM-exit information for EPT violations 2394 * Sub-page write permissions 2395 * PT in VMX operation 2396 */ 2397 2398 static const X86CPUDefinition builtin_x86_defs[] = { 2399 { 2400 .name = "qemu64", 2401 .level = 0xd, 2402 .vendor = CPUID_VENDOR_AMD, 2403 .family = 15, 2404 .model = 107, 2405 .stepping = 1, 2406 .features[FEAT_1_EDX] = 2407 PPRO_FEATURES | 2408 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2409 CPUID_PSE36, 2410 .features[FEAT_1_ECX] = 2411 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2412 .features[FEAT_8000_0001_EDX] = 2413 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2414 .features[FEAT_8000_0001_ECX] = 2415 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2416 .xlevel = 0x8000000A, 2417 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2418 }, 2419 { 2420 .name = "phenom", 2421 .level = 5, 2422 .vendor = CPUID_VENDOR_AMD, 2423 .family = 16, 2424 .model = 2, 2425 .stepping = 3, 2426 /* Missing: CPUID_HT */ 2427 .features[FEAT_1_EDX] = 2428 PPRO_FEATURES | 2429 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2430 CPUID_PSE36 | CPUID_VME, 2431 .features[FEAT_1_ECX] = 2432 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2433 CPUID_EXT_POPCNT, 2434 .features[FEAT_8000_0001_EDX] = 2435 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2436 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2437 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2438 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2439 CPUID_EXT3_CR8LEG, 2440 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2441 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2442 .features[FEAT_8000_0001_ECX] = 2443 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2444 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2445 /* Missing: CPUID_SVM_LBRV */ 2446 .features[FEAT_SVM] = 2447 CPUID_SVM_NPT, 2448 .xlevel = 0x8000001A, 2449 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2450 }, 2451 { 2452 .name = "core2duo", 2453 .level = 10, 2454 .vendor = CPUID_VENDOR_INTEL, 2455 .family = 6, 2456 .model = 15, 2457 .stepping = 11, 2458 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2459 .features[FEAT_1_EDX] = 2460 PPRO_FEATURES | 2461 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2462 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2463 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2464 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2465 .features[FEAT_1_ECX] = 2466 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2467 CPUID_EXT_CX16, 2468 .features[FEAT_8000_0001_EDX] = 2469 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2470 .features[FEAT_8000_0001_ECX] = 2471 CPUID_EXT3_LAHF_LM, 2472 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2473 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2474 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2475 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2476 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2477 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2478 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2479 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2480 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2481 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2482 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2483 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2484 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2485 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2486 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2487 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2488 .features[FEAT_VMX_SECONDARY_CTLS] = 2489 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2490 .xlevel = 0x80000008, 2491 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2492 }, 2493 { 2494 .name = "kvm64", 2495 .level = 0xd, 2496 .vendor = CPUID_VENDOR_INTEL, 2497 .family = 15, 2498 .model = 6, 2499 .stepping = 1, 2500 /* Missing: CPUID_HT */ 2501 .features[FEAT_1_EDX] = 2502 PPRO_FEATURES | CPUID_VME | 2503 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2504 CPUID_PSE36, 2505 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2506 .features[FEAT_1_ECX] = 2507 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2508 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2509 .features[FEAT_8000_0001_EDX] = 2510 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2511 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2512 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2513 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2514 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2515 .features[FEAT_8000_0001_ECX] = 2516 0, 2517 /* VMX features from Cedar Mill/Prescott */ 2518 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2519 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2520 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2521 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2522 VMX_PIN_BASED_NMI_EXITING, 2523 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2524 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2525 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2526 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2527 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2528 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2529 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2530 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2531 .xlevel = 0x80000008, 2532 .model_id = "Common KVM processor" 2533 }, 2534 { 2535 .name = "qemu32", 2536 .level = 4, 2537 .vendor = CPUID_VENDOR_INTEL, 2538 .family = 6, 2539 .model = 6, 2540 .stepping = 3, 2541 .features[FEAT_1_EDX] = 2542 PPRO_FEATURES, 2543 .features[FEAT_1_ECX] = 2544 CPUID_EXT_SSE3, 2545 .xlevel = 0x80000004, 2546 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2547 }, 2548 { 2549 .name = "kvm32", 2550 .level = 5, 2551 .vendor = CPUID_VENDOR_INTEL, 2552 .family = 15, 2553 .model = 6, 2554 .stepping = 1, 2555 .features[FEAT_1_EDX] = 2556 PPRO_FEATURES | CPUID_VME | 2557 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2558 .features[FEAT_1_ECX] = 2559 CPUID_EXT_SSE3, 2560 .features[FEAT_8000_0001_ECX] = 2561 0, 2562 /* VMX features from Yonah */ 2563 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2564 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2565 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2566 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2567 VMX_PIN_BASED_NMI_EXITING, 2568 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2569 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2570 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2571 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2572 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2573 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2574 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2575 .xlevel = 0x80000008, 2576 .model_id = "Common 32-bit KVM processor" 2577 }, 2578 { 2579 .name = "coreduo", 2580 .level = 10, 2581 .vendor = CPUID_VENDOR_INTEL, 2582 .family = 6, 2583 .model = 14, 2584 .stepping = 8, 2585 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2586 .features[FEAT_1_EDX] = 2587 PPRO_FEATURES | CPUID_VME | 2588 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2589 CPUID_SS, 2590 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2591 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2592 .features[FEAT_1_ECX] = 2593 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2594 .features[FEAT_8000_0001_EDX] = 2595 CPUID_EXT2_NX, 2596 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2597 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2598 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2599 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2600 VMX_PIN_BASED_NMI_EXITING, 2601 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2602 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2603 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2604 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2605 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2606 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2607 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2608 .xlevel = 0x80000008, 2609 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2610 }, 2611 { 2612 .name = "486", 2613 .level = 1, 2614 .vendor = CPUID_VENDOR_INTEL, 2615 .family = 4, 2616 .model = 8, 2617 .stepping = 0, 2618 .features[FEAT_1_EDX] = 2619 I486_FEATURES, 2620 .xlevel = 0, 2621 .model_id = "", 2622 }, 2623 { 2624 .name = "pentium", 2625 .level = 1, 2626 .vendor = CPUID_VENDOR_INTEL, 2627 .family = 5, 2628 .model = 4, 2629 .stepping = 3, 2630 .features[FEAT_1_EDX] = 2631 PENTIUM_FEATURES, 2632 .xlevel = 0, 2633 .model_id = "", 2634 }, 2635 { 2636 .name = "pentium2", 2637 .level = 2, 2638 .vendor = CPUID_VENDOR_INTEL, 2639 .family = 6, 2640 .model = 5, 2641 .stepping = 2, 2642 .features[FEAT_1_EDX] = 2643 PENTIUM2_FEATURES, 2644 .xlevel = 0, 2645 .model_id = "", 2646 }, 2647 { 2648 .name = "pentium3", 2649 .level = 3, 2650 .vendor = CPUID_VENDOR_INTEL, 2651 .family = 6, 2652 .model = 7, 2653 .stepping = 3, 2654 .features[FEAT_1_EDX] = 2655 PENTIUM3_FEATURES, 2656 .xlevel = 0, 2657 .model_id = "", 2658 }, 2659 { 2660 .name = "athlon", 2661 .level = 2, 2662 .vendor = CPUID_VENDOR_AMD, 2663 .family = 6, 2664 .model = 2, 2665 .stepping = 3, 2666 .features[FEAT_1_EDX] = 2667 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2668 CPUID_MCA, 2669 .features[FEAT_8000_0001_EDX] = 2670 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2671 .xlevel = 0x80000008, 2672 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2673 }, 2674 { 2675 .name = "n270", 2676 .level = 10, 2677 .vendor = CPUID_VENDOR_INTEL, 2678 .family = 6, 2679 .model = 28, 2680 .stepping = 2, 2681 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2682 .features[FEAT_1_EDX] = 2683 PPRO_FEATURES | 2684 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2685 CPUID_ACPI | CPUID_SS, 2686 /* Some CPUs got no CPUID_SEP */ 2687 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2688 * CPUID_EXT_XTPR */ 2689 .features[FEAT_1_ECX] = 2690 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2691 CPUID_EXT_MOVBE, 2692 .features[FEAT_8000_0001_EDX] = 2693 CPUID_EXT2_NX, 2694 .features[FEAT_8000_0001_ECX] = 2695 CPUID_EXT3_LAHF_LM, 2696 .xlevel = 0x80000008, 2697 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2698 }, 2699 { 2700 .name = "Conroe", 2701 .level = 10, 2702 .vendor = CPUID_VENDOR_INTEL, 2703 .family = 6, 2704 .model = 15, 2705 .stepping = 3, 2706 .features[FEAT_1_EDX] = 2707 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2708 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2709 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2710 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2711 CPUID_DE | CPUID_FP87, 2712 .features[FEAT_1_ECX] = 2713 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2714 .features[FEAT_8000_0001_EDX] = 2715 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2716 .features[FEAT_8000_0001_ECX] = 2717 CPUID_EXT3_LAHF_LM, 2718 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2719 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2720 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2721 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2722 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2723 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2724 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2725 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2726 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2727 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2728 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2729 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2730 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2731 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2732 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2733 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2734 .features[FEAT_VMX_SECONDARY_CTLS] = 2735 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2736 .xlevel = 0x80000008, 2737 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2738 }, 2739 { 2740 .name = "Penryn", 2741 .level = 10, 2742 .vendor = CPUID_VENDOR_INTEL, 2743 .family = 6, 2744 .model = 23, 2745 .stepping = 3, 2746 .features[FEAT_1_EDX] = 2747 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2748 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2749 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2750 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2751 CPUID_DE | CPUID_FP87, 2752 .features[FEAT_1_ECX] = 2753 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2754 CPUID_EXT_SSE3, 2755 .features[FEAT_8000_0001_EDX] = 2756 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2757 .features[FEAT_8000_0001_ECX] = 2758 CPUID_EXT3_LAHF_LM, 2759 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2760 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2761 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2762 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2763 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2764 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2765 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2766 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2767 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2768 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2769 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2770 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2771 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2772 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2773 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2774 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2775 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2776 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2777 .features[FEAT_VMX_SECONDARY_CTLS] = 2778 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2779 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2780 .xlevel = 0x80000008, 2781 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2782 }, 2783 { 2784 .name = "Nehalem", 2785 .level = 11, 2786 .vendor = CPUID_VENDOR_INTEL, 2787 .family = 6, 2788 .model = 26, 2789 .stepping = 3, 2790 .features[FEAT_1_EDX] = 2791 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2792 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2793 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2794 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2795 CPUID_DE | CPUID_FP87, 2796 .features[FEAT_1_ECX] = 2797 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2798 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2799 .features[FEAT_8000_0001_EDX] = 2800 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2801 .features[FEAT_8000_0001_ECX] = 2802 CPUID_EXT3_LAHF_LM, 2803 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2804 MSR_VMX_BASIC_TRUE_CTLS, 2805 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2806 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2807 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2808 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2809 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2810 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2811 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2812 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2813 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2814 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2815 .features[FEAT_VMX_EXIT_CTLS] = 2816 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2817 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2818 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2819 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2820 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2821 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2822 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2823 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2824 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2825 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2826 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2827 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2828 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2829 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2830 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2831 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2832 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2833 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2834 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2835 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2836 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2837 .features[FEAT_VMX_SECONDARY_CTLS] = 2838 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2839 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2840 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2841 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2842 VMX_SECONDARY_EXEC_ENABLE_VPID, 2843 .xlevel = 0x80000008, 2844 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2845 .versions = (X86CPUVersionDefinition[]) { 2846 { .version = 1 }, 2847 { 2848 .version = 2, 2849 .alias = "Nehalem-IBRS", 2850 .props = (PropValue[]) { 2851 { "spec-ctrl", "on" }, 2852 { "model-id", 2853 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2854 { /* end of list */ } 2855 } 2856 }, 2857 { /* end of list */ } 2858 } 2859 }, 2860 { 2861 .name = "Westmere", 2862 .level = 11, 2863 .vendor = CPUID_VENDOR_INTEL, 2864 .family = 6, 2865 .model = 44, 2866 .stepping = 1, 2867 .features[FEAT_1_EDX] = 2868 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2869 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2870 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2871 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2872 CPUID_DE | CPUID_FP87, 2873 .features[FEAT_1_ECX] = 2874 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2875 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2876 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2877 .features[FEAT_8000_0001_EDX] = 2878 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2879 .features[FEAT_8000_0001_ECX] = 2880 CPUID_EXT3_LAHF_LM, 2881 .features[FEAT_6_EAX] = 2882 CPUID_6_EAX_ARAT, 2883 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2884 MSR_VMX_BASIC_TRUE_CTLS, 2885 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2886 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2887 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2888 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2889 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2890 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2891 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2892 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2893 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2894 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2895 .features[FEAT_VMX_EXIT_CTLS] = 2896 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2897 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2898 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2899 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2900 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2901 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2902 MSR_VMX_MISC_STORE_LMA, 2903 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2904 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2905 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2906 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2907 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2908 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2909 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2910 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2911 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2912 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2913 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2914 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2915 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2916 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2917 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2918 .features[FEAT_VMX_SECONDARY_CTLS] = 2919 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2920 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2921 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2922 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2923 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2924 .xlevel = 0x80000008, 2925 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2926 .versions = (X86CPUVersionDefinition[]) { 2927 { .version = 1 }, 2928 { 2929 .version = 2, 2930 .alias = "Westmere-IBRS", 2931 .props = (PropValue[]) { 2932 { "spec-ctrl", "on" }, 2933 { "model-id", 2934 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2935 { /* end of list */ } 2936 } 2937 }, 2938 { /* end of list */ } 2939 } 2940 }, 2941 { 2942 .name = "SandyBridge", 2943 .level = 0xd, 2944 .vendor = CPUID_VENDOR_INTEL, 2945 .family = 6, 2946 .model = 42, 2947 .stepping = 1, 2948 .features[FEAT_1_EDX] = 2949 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2950 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2951 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2952 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2953 CPUID_DE | CPUID_FP87, 2954 .features[FEAT_1_ECX] = 2955 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2956 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2957 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2958 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2959 CPUID_EXT_SSE3, 2960 .features[FEAT_8000_0001_EDX] = 2961 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2962 CPUID_EXT2_SYSCALL, 2963 .features[FEAT_8000_0001_ECX] = 2964 CPUID_EXT3_LAHF_LM, 2965 .features[FEAT_XSAVE] = 2966 CPUID_XSAVE_XSAVEOPT, 2967 .features[FEAT_6_EAX] = 2968 CPUID_6_EAX_ARAT, 2969 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2970 MSR_VMX_BASIC_TRUE_CTLS, 2971 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2972 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2973 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2974 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2975 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2976 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2977 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2978 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2979 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2980 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2981 .features[FEAT_VMX_EXIT_CTLS] = 2982 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2983 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2984 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2985 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2986 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2987 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2988 MSR_VMX_MISC_STORE_LMA, 2989 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2990 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2991 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2992 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2993 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2994 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2995 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2996 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2997 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2998 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2999 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3000 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3001 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3002 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3003 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3004 .features[FEAT_VMX_SECONDARY_CTLS] = 3005 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3006 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3007 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3008 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3009 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3010 .xlevel = 0x80000008, 3011 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3012 .versions = (X86CPUVersionDefinition[]) { 3013 { .version = 1 }, 3014 { 3015 .version = 2, 3016 .alias = "SandyBridge-IBRS", 3017 .props = (PropValue[]) { 3018 { "spec-ctrl", "on" }, 3019 { "model-id", 3020 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3021 { /* end of list */ } 3022 } 3023 }, 3024 { /* end of list */ } 3025 } 3026 }, 3027 { 3028 .name = "IvyBridge", 3029 .level = 0xd, 3030 .vendor = CPUID_VENDOR_INTEL, 3031 .family = 6, 3032 .model = 58, 3033 .stepping = 9, 3034 .features[FEAT_1_EDX] = 3035 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3036 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3037 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3038 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3039 CPUID_DE | CPUID_FP87, 3040 .features[FEAT_1_ECX] = 3041 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3042 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3043 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3044 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3045 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3046 .features[FEAT_7_0_EBX] = 3047 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3048 CPUID_7_0_EBX_ERMS, 3049 .features[FEAT_8000_0001_EDX] = 3050 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3051 CPUID_EXT2_SYSCALL, 3052 .features[FEAT_8000_0001_ECX] = 3053 CPUID_EXT3_LAHF_LM, 3054 .features[FEAT_XSAVE] = 3055 CPUID_XSAVE_XSAVEOPT, 3056 .features[FEAT_6_EAX] = 3057 CPUID_6_EAX_ARAT, 3058 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3059 MSR_VMX_BASIC_TRUE_CTLS, 3060 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3061 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3062 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3063 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3064 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3065 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3066 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3067 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3068 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3069 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3070 .features[FEAT_VMX_EXIT_CTLS] = 3071 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3072 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3073 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3074 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3075 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3076 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3077 MSR_VMX_MISC_STORE_LMA, 3078 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3079 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3080 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3081 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3082 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3083 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3084 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3085 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3086 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3087 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3088 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3089 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3090 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3091 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3092 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3093 .features[FEAT_VMX_SECONDARY_CTLS] = 3094 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3095 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3096 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3097 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3098 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3099 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3100 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3101 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3102 .xlevel = 0x80000008, 3103 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3104 .versions = (X86CPUVersionDefinition[]) { 3105 { .version = 1 }, 3106 { 3107 .version = 2, 3108 .alias = "IvyBridge-IBRS", 3109 .props = (PropValue[]) { 3110 { "spec-ctrl", "on" }, 3111 { "model-id", 3112 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3113 { /* end of list */ } 3114 } 3115 }, 3116 { /* end of list */ } 3117 } 3118 }, 3119 { 3120 .name = "Haswell", 3121 .level = 0xd, 3122 .vendor = CPUID_VENDOR_INTEL, 3123 .family = 6, 3124 .model = 60, 3125 .stepping = 4, 3126 .features[FEAT_1_EDX] = 3127 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3128 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3129 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3130 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3131 CPUID_DE | CPUID_FP87, 3132 .features[FEAT_1_ECX] = 3133 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3134 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3135 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3136 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3137 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3138 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3139 .features[FEAT_8000_0001_EDX] = 3140 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3141 CPUID_EXT2_SYSCALL, 3142 .features[FEAT_8000_0001_ECX] = 3143 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3144 .features[FEAT_7_0_EBX] = 3145 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3146 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3147 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3148 CPUID_7_0_EBX_RTM, 3149 .features[FEAT_XSAVE] = 3150 CPUID_XSAVE_XSAVEOPT, 3151 .features[FEAT_6_EAX] = 3152 CPUID_6_EAX_ARAT, 3153 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3154 MSR_VMX_BASIC_TRUE_CTLS, 3155 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3156 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3157 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3158 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3159 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3160 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3161 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3162 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3163 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3164 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3165 .features[FEAT_VMX_EXIT_CTLS] = 3166 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3167 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3168 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3169 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3170 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3171 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3172 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3173 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3174 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3175 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3176 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3177 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3178 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3179 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3180 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3181 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3182 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3183 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3184 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3185 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3186 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3187 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3188 .features[FEAT_VMX_SECONDARY_CTLS] = 3189 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3190 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3191 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3192 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3193 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3194 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3195 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3196 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3197 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3198 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3199 .xlevel = 0x80000008, 3200 .model_id = "Intel Core Processor (Haswell)", 3201 .versions = (X86CPUVersionDefinition[]) { 3202 { .version = 1 }, 3203 { 3204 .version = 2, 3205 .alias = "Haswell-noTSX", 3206 .props = (PropValue[]) { 3207 { "hle", "off" }, 3208 { "rtm", "off" }, 3209 { "stepping", "1" }, 3210 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3211 { /* end of list */ } 3212 }, 3213 }, 3214 { 3215 .version = 3, 3216 .alias = "Haswell-IBRS", 3217 .props = (PropValue[]) { 3218 /* Restore TSX features removed by -v2 above */ 3219 { "hle", "on" }, 3220 { "rtm", "on" }, 3221 /* 3222 * Haswell and Haswell-IBRS had stepping=4 in 3223 * QEMU 4.0 and older 3224 */ 3225 { "stepping", "4" }, 3226 { "spec-ctrl", "on" }, 3227 { "model-id", 3228 "Intel Core Processor (Haswell, IBRS)" }, 3229 { /* end of list */ } 3230 } 3231 }, 3232 { 3233 .version = 4, 3234 .alias = "Haswell-noTSX-IBRS", 3235 .props = (PropValue[]) { 3236 { "hle", "off" }, 3237 { "rtm", "off" }, 3238 /* spec-ctrl was already enabled by -v3 above */ 3239 { "stepping", "1" }, 3240 { "model-id", 3241 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3242 { /* end of list */ } 3243 } 3244 }, 3245 { /* end of list */ } 3246 } 3247 }, 3248 { 3249 .name = "Broadwell", 3250 .level = 0xd, 3251 .vendor = CPUID_VENDOR_INTEL, 3252 .family = 6, 3253 .model = 61, 3254 .stepping = 2, 3255 .features[FEAT_1_EDX] = 3256 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3257 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3258 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3259 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3260 CPUID_DE | CPUID_FP87, 3261 .features[FEAT_1_ECX] = 3262 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3263 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3264 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3265 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3266 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3267 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3268 .features[FEAT_8000_0001_EDX] = 3269 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3270 CPUID_EXT2_SYSCALL, 3271 .features[FEAT_8000_0001_ECX] = 3272 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3273 .features[FEAT_7_0_EBX] = 3274 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3275 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3276 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3277 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3278 CPUID_7_0_EBX_SMAP, 3279 .features[FEAT_XSAVE] = 3280 CPUID_XSAVE_XSAVEOPT, 3281 .features[FEAT_6_EAX] = 3282 CPUID_6_EAX_ARAT, 3283 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3284 MSR_VMX_BASIC_TRUE_CTLS, 3285 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3286 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3287 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3288 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3289 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3290 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3291 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3292 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3293 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3294 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3295 .features[FEAT_VMX_EXIT_CTLS] = 3296 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3297 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3298 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3299 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3300 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3301 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3302 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3303 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3304 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3305 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3306 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3307 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3308 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3309 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3310 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3311 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3312 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3313 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3314 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3315 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3316 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3317 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3318 .features[FEAT_VMX_SECONDARY_CTLS] = 3319 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3320 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3321 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3322 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3323 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3324 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3325 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3326 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3327 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3328 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3329 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3330 .xlevel = 0x80000008, 3331 .model_id = "Intel Core Processor (Broadwell)", 3332 .versions = (X86CPUVersionDefinition[]) { 3333 { .version = 1 }, 3334 { 3335 .version = 2, 3336 .alias = "Broadwell-noTSX", 3337 .props = (PropValue[]) { 3338 { "hle", "off" }, 3339 { "rtm", "off" }, 3340 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3341 { /* end of list */ } 3342 }, 3343 }, 3344 { 3345 .version = 3, 3346 .alias = "Broadwell-IBRS", 3347 .props = (PropValue[]) { 3348 /* Restore TSX features removed by -v2 above */ 3349 { "hle", "on" }, 3350 { "rtm", "on" }, 3351 { "spec-ctrl", "on" }, 3352 { "model-id", 3353 "Intel Core Processor (Broadwell, IBRS)" }, 3354 { /* end of list */ } 3355 } 3356 }, 3357 { 3358 .version = 4, 3359 .alias = "Broadwell-noTSX-IBRS", 3360 .props = (PropValue[]) { 3361 { "hle", "off" }, 3362 { "rtm", "off" }, 3363 /* spec-ctrl was already enabled by -v3 above */ 3364 { "model-id", 3365 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3366 { /* end of list */ } 3367 } 3368 }, 3369 { /* end of list */ } 3370 } 3371 }, 3372 { 3373 .name = "Skylake-Client", 3374 .level = 0xd, 3375 .vendor = CPUID_VENDOR_INTEL, 3376 .family = 6, 3377 .model = 94, 3378 .stepping = 3, 3379 .features[FEAT_1_EDX] = 3380 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3381 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3382 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3383 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3384 CPUID_DE | CPUID_FP87, 3385 .features[FEAT_1_ECX] = 3386 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3387 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3388 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3389 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3390 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3391 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3392 .features[FEAT_8000_0001_EDX] = 3393 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3394 CPUID_EXT2_SYSCALL, 3395 .features[FEAT_8000_0001_ECX] = 3396 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3397 .features[FEAT_7_0_EBX] = 3398 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3399 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3400 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3401 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3402 CPUID_7_0_EBX_SMAP, 3403 /* XSAVES is added in version 4 */ 3404 .features[FEAT_XSAVE] = 3405 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3406 CPUID_XSAVE_XGETBV1, 3407 .features[FEAT_6_EAX] = 3408 CPUID_6_EAX_ARAT, 3409 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3410 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3411 MSR_VMX_BASIC_TRUE_CTLS, 3412 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3413 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3414 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3415 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3416 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3417 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3418 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3419 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3420 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3421 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3422 .features[FEAT_VMX_EXIT_CTLS] = 3423 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3424 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3425 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3426 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3427 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3428 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3429 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3430 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3431 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3432 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3433 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3434 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3435 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3436 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3437 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3438 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3439 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3440 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3441 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3442 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3443 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3444 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3445 .features[FEAT_VMX_SECONDARY_CTLS] = 3446 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3447 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3448 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3449 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3450 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3451 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3452 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3453 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3454 .xlevel = 0x80000008, 3455 .model_id = "Intel Core Processor (Skylake)", 3456 .versions = (X86CPUVersionDefinition[]) { 3457 { .version = 1 }, 3458 { 3459 .version = 2, 3460 .alias = "Skylake-Client-IBRS", 3461 .props = (PropValue[]) { 3462 { "spec-ctrl", "on" }, 3463 { "model-id", 3464 "Intel Core Processor (Skylake, IBRS)" }, 3465 { /* end of list */ } 3466 } 3467 }, 3468 { 3469 .version = 3, 3470 .alias = "Skylake-Client-noTSX-IBRS", 3471 .props = (PropValue[]) { 3472 { "hle", "off" }, 3473 { "rtm", "off" }, 3474 { "model-id", 3475 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3476 { /* end of list */ } 3477 } 3478 }, 3479 { 3480 .version = 4, 3481 .note = "IBRS, XSAVES, no TSX", 3482 .props = (PropValue[]) { 3483 { "xsaves", "on" }, 3484 { "vmx-xsaves", "on" }, 3485 { /* end of list */ } 3486 } 3487 }, 3488 { /* end of list */ } 3489 } 3490 }, 3491 { 3492 .name = "Skylake-Server", 3493 .level = 0xd, 3494 .vendor = CPUID_VENDOR_INTEL, 3495 .family = 6, 3496 .model = 85, 3497 .stepping = 4, 3498 .features[FEAT_1_EDX] = 3499 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3500 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3501 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3502 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3503 CPUID_DE | CPUID_FP87, 3504 .features[FEAT_1_ECX] = 3505 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3506 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3507 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3508 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3509 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3510 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3511 .features[FEAT_8000_0001_EDX] = 3512 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3513 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3514 .features[FEAT_8000_0001_ECX] = 3515 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3516 .features[FEAT_7_0_EBX] = 3517 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3518 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3519 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3520 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3521 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3522 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3523 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3524 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3525 .features[FEAT_7_0_ECX] = 3526 CPUID_7_0_ECX_PKU, 3527 /* XSAVES is added in version 5 */ 3528 .features[FEAT_XSAVE] = 3529 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3530 CPUID_XSAVE_XGETBV1, 3531 .features[FEAT_6_EAX] = 3532 CPUID_6_EAX_ARAT, 3533 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3534 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3535 MSR_VMX_BASIC_TRUE_CTLS, 3536 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3537 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3538 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3539 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3540 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3541 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3542 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3543 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3544 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3545 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3546 .features[FEAT_VMX_EXIT_CTLS] = 3547 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3548 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3549 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3550 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3551 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3552 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3553 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3554 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3555 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3556 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3557 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3558 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3559 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3560 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3561 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3562 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3563 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3564 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3565 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3566 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3567 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3568 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3569 .features[FEAT_VMX_SECONDARY_CTLS] = 3570 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3571 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3572 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3573 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3574 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3575 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3576 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3577 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3578 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3579 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3580 .xlevel = 0x80000008, 3581 .model_id = "Intel Xeon Processor (Skylake)", 3582 .versions = (X86CPUVersionDefinition[]) { 3583 { .version = 1 }, 3584 { 3585 .version = 2, 3586 .alias = "Skylake-Server-IBRS", 3587 .props = (PropValue[]) { 3588 /* clflushopt was not added to Skylake-Server-IBRS */ 3589 /* TODO: add -v3 including clflushopt */ 3590 { "clflushopt", "off" }, 3591 { "spec-ctrl", "on" }, 3592 { "model-id", 3593 "Intel Xeon Processor (Skylake, IBRS)" }, 3594 { /* end of list */ } 3595 } 3596 }, 3597 { 3598 .version = 3, 3599 .alias = "Skylake-Server-noTSX-IBRS", 3600 .props = (PropValue[]) { 3601 { "hle", "off" }, 3602 { "rtm", "off" }, 3603 { "model-id", 3604 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3605 { /* end of list */ } 3606 } 3607 }, 3608 { 3609 .version = 4, 3610 .props = (PropValue[]) { 3611 { "vmx-eptp-switching", "on" }, 3612 { /* end of list */ } 3613 } 3614 }, 3615 { 3616 .version = 5, 3617 .note = "IBRS, XSAVES, EPT switching, no TSX", 3618 .props = (PropValue[]) { 3619 { "xsaves", "on" }, 3620 { "vmx-xsaves", "on" }, 3621 { /* end of list */ } 3622 } 3623 }, 3624 { /* end of list */ } 3625 } 3626 }, 3627 { 3628 .name = "Cascadelake-Server", 3629 .level = 0xd, 3630 .vendor = CPUID_VENDOR_INTEL, 3631 .family = 6, 3632 .model = 85, 3633 .stepping = 6, 3634 .features[FEAT_1_EDX] = 3635 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3636 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3637 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3638 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3639 CPUID_DE | CPUID_FP87, 3640 .features[FEAT_1_ECX] = 3641 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3642 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3643 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3644 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3645 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3646 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3647 .features[FEAT_8000_0001_EDX] = 3648 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3649 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3650 .features[FEAT_8000_0001_ECX] = 3651 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3652 .features[FEAT_7_0_EBX] = 3653 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3654 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3655 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3656 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3657 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3658 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3659 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3660 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3661 .features[FEAT_7_0_ECX] = 3662 CPUID_7_0_ECX_PKU | 3663 CPUID_7_0_ECX_AVX512VNNI, 3664 .features[FEAT_7_0_EDX] = 3665 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3666 /* XSAVES is added in version 5 */ 3667 .features[FEAT_XSAVE] = 3668 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3669 CPUID_XSAVE_XGETBV1, 3670 .features[FEAT_6_EAX] = 3671 CPUID_6_EAX_ARAT, 3672 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3673 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3674 MSR_VMX_BASIC_TRUE_CTLS, 3675 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3676 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3677 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3678 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3679 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3680 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3681 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3682 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3683 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3684 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3685 .features[FEAT_VMX_EXIT_CTLS] = 3686 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3687 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3688 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3689 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3690 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3691 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3692 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3693 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3694 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3695 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3696 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3697 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3698 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3699 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3700 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3701 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3702 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3703 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3704 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3705 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3706 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3707 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3708 .features[FEAT_VMX_SECONDARY_CTLS] = 3709 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3710 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3711 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3712 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3713 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3714 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3715 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3716 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3717 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3718 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3719 .xlevel = 0x80000008, 3720 .model_id = "Intel Xeon Processor (Cascadelake)", 3721 .versions = (X86CPUVersionDefinition[]) { 3722 { .version = 1 }, 3723 { .version = 2, 3724 .note = "ARCH_CAPABILITIES", 3725 .props = (PropValue[]) { 3726 { "arch-capabilities", "on" }, 3727 { "rdctl-no", "on" }, 3728 { "ibrs-all", "on" }, 3729 { "skip-l1dfl-vmentry", "on" }, 3730 { "mds-no", "on" }, 3731 { /* end of list */ } 3732 }, 3733 }, 3734 { .version = 3, 3735 .alias = "Cascadelake-Server-noTSX", 3736 .note = "ARCH_CAPABILITIES, no TSX", 3737 .props = (PropValue[]) { 3738 { "hle", "off" }, 3739 { "rtm", "off" }, 3740 { /* end of list */ } 3741 }, 3742 }, 3743 { .version = 4, 3744 .note = "ARCH_CAPABILITIES, no TSX", 3745 .props = (PropValue[]) { 3746 { "vmx-eptp-switching", "on" }, 3747 { /* end of list */ } 3748 }, 3749 }, 3750 { .version = 5, 3751 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3752 .props = (PropValue[]) { 3753 { "xsaves", "on" }, 3754 { "vmx-xsaves", "on" }, 3755 { /* end of list */ } 3756 }, 3757 }, 3758 { /* end of list */ } 3759 } 3760 }, 3761 { 3762 .name = "Cooperlake", 3763 .level = 0xd, 3764 .vendor = CPUID_VENDOR_INTEL, 3765 .family = 6, 3766 .model = 85, 3767 .stepping = 10, 3768 .features[FEAT_1_EDX] = 3769 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3770 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3771 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3772 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3773 CPUID_DE | CPUID_FP87, 3774 .features[FEAT_1_ECX] = 3775 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3776 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3777 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3778 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3779 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3780 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3781 .features[FEAT_8000_0001_EDX] = 3782 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3783 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3784 .features[FEAT_8000_0001_ECX] = 3785 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3786 .features[FEAT_7_0_EBX] = 3787 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3788 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3789 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3790 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3791 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3792 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3793 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3794 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3795 .features[FEAT_7_0_ECX] = 3796 CPUID_7_0_ECX_PKU | 3797 CPUID_7_0_ECX_AVX512VNNI, 3798 .features[FEAT_7_0_EDX] = 3799 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3800 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3801 .features[FEAT_ARCH_CAPABILITIES] = 3802 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3803 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3804 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3805 .features[FEAT_7_1_EAX] = 3806 CPUID_7_1_EAX_AVX512_BF16, 3807 /* XSAVES is added in version 2 */ 3808 .features[FEAT_XSAVE] = 3809 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3810 CPUID_XSAVE_XGETBV1, 3811 .features[FEAT_6_EAX] = 3812 CPUID_6_EAX_ARAT, 3813 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3814 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3815 MSR_VMX_BASIC_TRUE_CTLS, 3816 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3817 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3818 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3819 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3820 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3821 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3822 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3823 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3824 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3825 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3826 .features[FEAT_VMX_EXIT_CTLS] = 3827 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3828 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3829 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3830 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3831 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3832 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3833 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3834 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3835 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3836 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3837 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3838 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3839 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3840 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3841 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3842 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3843 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3844 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3845 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3846 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3847 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3848 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3849 .features[FEAT_VMX_SECONDARY_CTLS] = 3850 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3851 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3852 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3853 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3854 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3855 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3856 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3857 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3858 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3859 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3860 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3861 .xlevel = 0x80000008, 3862 .model_id = "Intel Xeon Processor (Cooperlake)", 3863 .versions = (X86CPUVersionDefinition[]) { 3864 { .version = 1 }, 3865 { .version = 2, 3866 .note = "XSAVES", 3867 .props = (PropValue[]) { 3868 { "xsaves", "on" }, 3869 { "vmx-xsaves", "on" }, 3870 { /* end of list */ } 3871 }, 3872 }, 3873 { /* end of list */ } 3874 } 3875 }, 3876 { 3877 .name = "Icelake-Server", 3878 .level = 0xd, 3879 .vendor = CPUID_VENDOR_INTEL, 3880 .family = 6, 3881 .model = 134, 3882 .stepping = 0, 3883 .features[FEAT_1_EDX] = 3884 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3885 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3886 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3887 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3888 CPUID_DE | CPUID_FP87, 3889 .features[FEAT_1_ECX] = 3890 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3891 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3892 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3893 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3894 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3895 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3896 .features[FEAT_8000_0001_EDX] = 3897 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3898 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3899 .features[FEAT_8000_0001_ECX] = 3900 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3901 .features[FEAT_8000_0008_EBX] = 3902 CPUID_8000_0008_EBX_WBNOINVD, 3903 .features[FEAT_7_0_EBX] = 3904 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3905 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3906 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3907 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3908 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3909 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3910 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3911 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3912 .features[FEAT_7_0_ECX] = 3913 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3914 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3915 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3916 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3917 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3918 .features[FEAT_7_0_EDX] = 3919 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3920 /* XSAVES is added in version 5 */ 3921 .features[FEAT_XSAVE] = 3922 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3923 CPUID_XSAVE_XGETBV1, 3924 .features[FEAT_6_EAX] = 3925 CPUID_6_EAX_ARAT, 3926 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3927 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3928 MSR_VMX_BASIC_TRUE_CTLS, 3929 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3930 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3931 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3932 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3933 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3934 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3935 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3936 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3937 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3938 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3939 .features[FEAT_VMX_EXIT_CTLS] = 3940 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3941 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3942 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3943 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3944 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3945 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3946 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3947 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3948 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3949 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3950 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3951 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3952 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3953 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3954 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3955 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3956 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3957 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3958 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3959 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3960 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3961 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3962 .features[FEAT_VMX_SECONDARY_CTLS] = 3963 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3964 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3965 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3966 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3967 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3968 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3969 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3970 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3971 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3972 .xlevel = 0x80000008, 3973 .model_id = "Intel Xeon Processor (Icelake)", 3974 .versions = (X86CPUVersionDefinition[]) { 3975 { .version = 1 }, 3976 { 3977 .version = 2, 3978 .note = "no TSX", 3979 .alias = "Icelake-Server-noTSX", 3980 .props = (PropValue[]) { 3981 { "hle", "off" }, 3982 { "rtm", "off" }, 3983 { /* end of list */ } 3984 }, 3985 }, 3986 { 3987 .version = 3, 3988 .props = (PropValue[]) { 3989 { "arch-capabilities", "on" }, 3990 { "rdctl-no", "on" }, 3991 { "ibrs-all", "on" }, 3992 { "skip-l1dfl-vmentry", "on" }, 3993 { "mds-no", "on" }, 3994 { "pschange-mc-no", "on" }, 3995 { "taa-no", "on" }, 3996 { /* end of list */ } 3997 }, 3998 }, 3999 { 4000 .version = 4, 4001 .props = (PropValue[]) { 4002 { "sha-ni", "on" }, 4003 { "avx512ifma", "on" }, 4004 { "rdpid", "on" }, 4005 { "fsrm", "on" }, 4006 { "vmx-rdseed-exit", "on" }, 4007 { "vmx-pml", "on" }, 4008 { "vmx-eptp-switching", "on" }, 4009 { "model", "106" }, 4010 { /* end of list */ } 4011 }, 4012 }, 4013 { 4014 .version = 5, 4015 .note = "XSAVES", 4016 .props = (PropValue[]) { 4017 { "xsaves", "on" }, 4018 { "vmx-xsaves", "on" }, 4019 { /* end of list */ } 4020 }, 4021 }, 4022 { 4023 .version = 6, 4024 .note = "5-level EPT", 4025 .props = (PropValue[]) { 4026 { "vmx-page-walk-5", "on" }, 4027 { /* end of list */ } 4028 }, 4029 }, 4030 { 4031 .version = 7, 4032 .note = "TSX, taa-no", 4033 .props = (PropValue[]) { 4034 /* Restore TSX features removed by -v2 above */ 4035 { "hle", "on" }, 4036 { "rtm", "on" }, 4037 { /* end of list */ } 4038 }, 4039 }, 4040 { /* end of list */ } 4041 } 4042 }, 4043 { 4044 .name = "SapphireRapids", 4045 .level = 0x20, 4046 .vendor = CPUID_VENDOR_INTEL, 4047 .family = 6, 4048 .model = 143, 4049 .stepping = 4, 4050 /* 4051 * please keep the ascending order so that we can have a clear view of 4052 * bit position of each feature. 4053 */ 4054 .features[FEAT_1_EDX] = 4055 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4056 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4057 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4058 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4059 CPUID_SSE | CPUID_SSE2, 4060 .features[FEAT_1_ECX] = 4061 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4062 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4063 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4064 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4065 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4066 .features[FEAT_8000_0001_EDX] = 4067 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4068 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4069 .features[FEAT_8000_0001_ECX] = 4070 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4071 .features[FEAT_8000_0008_EBX] = 4072 CPUID_8000_0008_EBX_WBNOINVD, 4073 .features[FEAT_7_0_EBX] = 4074 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4075 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4076 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4077 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4078 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4079 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4080 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4081 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4082 .features[FEAT_7_0_ECX] = 4083 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4084 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4085 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4086 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4087 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4088 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4089 .features[FEAT_7_0_EDX] = 4090 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4091 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4092 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4093 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4094 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4095 .features[FEAT_ARCH_CAPABILITIES] = 4096 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4097 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4098 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4099 .features[FEAT_XSAVE] = 4100 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4101 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4102 .features[FEAT_6_EAX] = 4103 CPUID_6_EAX_ARAT, 4104 .features[FEAT_7_1_EAX] = 4105 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4106 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4107 .features[FEAT_VMX_BASIC] = 4108 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4109 .features[FEAT_VMX_ENTRY_CTLS] = 4110 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4111 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4112 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4113 .features[FEAT_VMX_EPT_VPID_CAPS] = 4114 MSR_VMX_EPT_EXECONLY | 4115 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4116 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4117 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4118 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4119 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4120 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4121 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4122 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4123 .features[FEAT_VMX_EXIT_CTLS] = 4124 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4125 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4126 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4127 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4128 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4129 .features[FEAT_VMX_MISC] = 4130 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4131 MSR_VMX_MISC_VMWRITE_VMEXIT, 4132 .features[FEAT_VMX_PINBASED_CTLS] = 4133 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4134 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4135 VMX_PIN_BASED_POSTED_INTR, 4136 .features[FEAT_VMX_PROCBASED_CTLS] = 4137 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4138 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4139 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4140 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4141 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4142 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4143 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4144 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4145 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4146 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4147 VMX_CPU_BASED_PAUSE_EXITING | 4148 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4149 .features[FEAT_VMX_SECONDARY_CTLS] = 4150 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4151 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4152 VMX_SECONDARY_EXEC_RDTSCP | 4153 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4154 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4155 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4156 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4157 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4158 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4159 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4160 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4161 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4162 VMX_SECONDARY_EXEC_XSAVES, 4163 .features[FEAT_VMX_VMFUNC] = 4164 MSR_VMX_VMFUNC_EPT_SWITCHING, 4165 .xlevel = 0x80000008, 4166 .model_id = "Intel Xeon Processor (SapphireRapids)", 4167 .versions = (X86CPUVersionDefinition[]) { 4168 { .version = 1 }, 4169 { 4170 .version = 2, 4171 .props = (PropValue[]) { 4172 { "sbdr-ssdp-no", "on" }, 4173 { "fbsdp-no", "on" }, 4174 { "psdp-no", "on" }, 4175 { /* end of list */ } 4176 } 4177 }, 4178 { 4179 .version = 3, 4180 .props = (PropValue[]) { 4181 { "ss", "on" }, 4182 { "tsc-adjust", "on" }, 4183 { "cldemote", "on" }, 4184 { "movdiri", "on" }, 4185 { "movdir64b", "on" }, 4186 { /* end of list */ } 4187 } 4188 }, 4189 { /* end of list */ } 4190 } 4191 }, 4192 { 4193 .name = "GraniteRapids", 4194 .level = 0x20, 4195 .vendor = CPUID_VENDOR_INTEL, 4196 .family = 6, 4197 .model = 173, 4198 .stepping = 0, 4199 /* 4200 * please keep the ascending order so that we can have a clear view of 4201 * bit position of each feature. 4202 */ 4203 .features[FEAT_1_EDX] = 4204 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4205 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4206 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4207 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4208 CPUID_SSE | CPUID_SSE2, 4209 .features[FEAT_1_ECX] = 4210 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4211 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4212 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4213 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4214 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4215 .features[FEAT_8000_0001_EDX] = 4216 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4217 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4218 .features[FEAT_8000_0001_ECX] = 4219 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4220 .features[FEAT_8000_0008_EBX] = 4221 CPUID_8000_0008_EBX_WBNOINVD, 4222 .features[FEAT_7_0_EBX] = 4223 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4224 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4225 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4226 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4227 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4228 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4229 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4230 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4231 .features[FEAT_7_0_ECX] = 4232 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4233 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4234 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4235 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4236 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4237 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4238 .features[FEAT_7_0_EDX] = 4239 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4240 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4241 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4242 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4243 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4244 .features[FEAT_ARCH_CAPABILITIES] = 4245 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4246 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4247 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4248 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4249 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4250 .features[FEAT_XSAVE] = 4251 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4252 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4253 .features[FEAT_6_EAX] = 4254 CPUID_6_EAX_ARAT, 4255 .features[FEAT_7_1_EAX] = 4256 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4257 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4258 CPUID_7_1_EAX_AMX_FP16, 4259 .features[FEAT_7_1_EDX] = 4260 CPUID_7_1_EDX_PREFETCHITI, 4261 .features[FEAT_7_2_EDX] = 4262 CPUID_7_2_EDX_MCDT_NO, 4263 .features[FEAT_VMX_BASIC] = 4264 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4265 .features[FEAT_VMX_ENTRY_CTLS] = 4266 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4267 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4268 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4269 .features[FEAT_VMX_EPT_VPID_CAPS] = 4270 MSR_VMX_EPT_EXECONLY | 4271 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4272 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4273 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4274 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4275 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4276 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4277 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4278 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4279 .features[FEAT_VMX_EXIT_CTLS] = 4280 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4281 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4282 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4283 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4284 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4285 .features[FEAT_VMX_MISC] = 4286 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4287 MSR_VMX_MISC_VMWRITE_VMEXIT, 4288 .features[FEAT_VMX_PINBASED_CTLS] = 4289 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4290 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4291 VMX_PIN_BASED_POSTED_INTR, 4292 .features[FEAT_VMX_PROCBASED_CTLS] = 4293 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4294 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4295 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4296 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4297 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4298 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4299 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4300 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4301 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4302 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4303 VMX_CPU_BASED_PAUSE_EXITING | 4304 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4305 .features[FEAT_VMX_SECONDARY_CTLS] = 4306 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4307 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4308 VMX_SECONDARY_EXEC_RDTSCP | 4309 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4310 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4311 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4312 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4313 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4314 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4315 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4316 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4317 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4318 VMX_SECONDARY_EXEC_XSAVES, 4319 .features[FEAT_VMX_VMFUNC] = 4320 MSR_VMX_VMFUNC_EPT_SWITCHING, 4321 .xlevel = 0x80000008, 4322 .model_id = "Intel Xeon Processor (GraniteRapids)", 4323 .versions = (X86CPUVersionDefinition[]) { 4324 { .version = 1 }, 4325 { /* end of list */ }, 4326 }, 4327 }, 4328 { 4329 .name = "SierraForest", 4330 .level = 0x23, 4331 .vendor = CPUID_VENDOR_INTEL, 4332 .family = 6, 4333 .model = 175, 4334 .stepping = 0, 4335 /* 4336 * please keep the ascending order so that we can have a clear view of 4337 * bit position of each feature. 4338 */ 4339 .features[FEAT_1_EDX] = 4340 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4341 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4342 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4343 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4344 CPUID_SSE | CPUID_SSE2, 4345 .features[FEAT_1_ECX] = 4346 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4347 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4348 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4349 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4350 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4351 .features[FEAT_8000_0001_EDX] = 4352 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4353 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4354 .features[FEAT_8000_0001_ECX] = 4355 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4356 .features[FEAT_8000_0008_EBX] = 4357 CPUID_8000_0008_EBX_WBNOINVD, 4358 .features[FEAT_7_0_EBX] = 4359 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4360 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4361 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4362 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4363 CPUID_7_0_EBX_SHA_NI, 4364 .features[FEAT_7_0_ECX] = 4365 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4366 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4367 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4368 .features[FEAT_7_0_EDX] = 4369 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4370 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4371 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4372 .features[FEAT_ARCH_CAPABILITIES] = 4373 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4374 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4375 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4376 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4377 MSR_ARCH_CAP_PBRSB_NO, 4378 .features[FEAT_XSAVE] = 4379 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4380 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4381 .features[FEAT_6_EAX] = 4382 CPUID_6_EAX_ARAT, 4383 .features[FEAT_7_1_EAX] = 4384 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4385 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4386 .features[FEAT_7_1_EDX] = 4387 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4388 .features[FEAT_7_2_EDX] = 4389 CPUID_7_2_EDX_MCDT_NO, 4390 .features[FEAT_VMX_BASIC] = 4391 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4392 .features[FEAT_VMX_ENTRY_CTLS] = 4393 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4394 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4395 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4396 .features[FEAT_VMX_EPT_VPID_CAPS] = 4397 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4398 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4399 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4400 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4401 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4402 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4403 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4404 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4405 .features[FEAT_VMX_EXIT_CTLS] = 4406 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4407 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4408 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4409 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4410 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4411 .features[FEAT_VMX_MISC] = 4412 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4413 MSR_VMX_MISC_VMWRITE_VMEXIT, 4414 .features[FEAT_VMX_PINBASED_CTLS] = 4415 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4416 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4417 VMX_PIN_BASED_POSTED_INTR, 4418 .features[FEAT_VMX_PROCBASED_CTLS] = 4419 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4420 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4421 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4422 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4423 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4424 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4425 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4426 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4427 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4428 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4429 VMX_CPU_BASED_PAUSE_EXITING | 4430 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4431 .features[FEAT_VMX_SECONDARY_CTLS] = 4432 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4433 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4434 VMX_SECONDARY_EXEC_RDTSCP | 4435 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4436 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4437 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4438 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4439 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4440 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4441 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4442 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4443 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4444 VMX_SECONDARY_EXEC_XSAVES, 4445 .features[FEAT_VMX_VMFUNC] = 4446 MSR_VMX_VMFUNC_EPT_SWITCHING, 4447 .xlevel = 0x80000008, 4448 .model_id = "Intel Xeon Processor (SierraForest)", 4449 .versions = (X86CPUVersionDefinition[]) { 4450 { .version = 1 }, 4451 { /* end of list */ }, 4452 }, 4453 }, 4454 { 4455 .name = "Denverton", 4456 .level = 21, 4457 .vendor = CPUID_VENDOR_INTEL, 4458 .family = 6, 4459 .model = 95, 4460 .stepping = 1, 4461 .features[FEAT_1_EDX] = 4462 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4463 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4464 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4465 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4466 CPUID_SSE | CPUID_SSE2, 4467 .features[FEAT_1_ECX] = 4468 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4469 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4470 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4471 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4472 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4473 .features[FEAT_8000_0001_EDX] = 4474 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4475 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4476 .features[FEAT_8000_0001_ECX] = 4477 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4478 .features[FEAT_7_0_EBX] = 4479 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4480 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4481 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4482 .features[FEAT_7_0_EDX] = 4483 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4484 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4485 /* XSAVES is added in version 3 */ 4486 .features[FEAT_XSAVE] = 4487 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4488 .features[FEAT_6_EAX] = 4489 CPUID_6_EAX_ARAT, 4490 .features[FEAT_ARCH_CAPABILITIES] = 4491 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4492 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4493 MSR_VMX_BASIC_TRUE_CTLS, 4494 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4495 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4496 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4497 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4498 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4499 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4500 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4501 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4502 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4504 .features[FEAT_VMX_EXIT_CTLS] = 4505 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4506 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4507 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4508 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4509 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4510 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4511 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4512 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4513 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4514 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4515 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4516 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4517 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4518 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4519 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4520 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4521 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4522 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4523 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4524 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4525 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4526 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4527 .features[FEAT_VMX_SECONDARY_CTLS] = 4528 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4529 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4530 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4531 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4532 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4533 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4534 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4535 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4536 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4537 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4538 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4539 .xlevel = 0x80000008, 4540 .model_id = "Intel Atom Processor (Denverton)", 4541 .versions = (X86CPUVersionDefinition[]) { 4542 { .version = 1 }, 4543 { 4544 .version = 2, 4545 .note = "no MPX, no MONITOR", 4546 .props = (PropValue[]) { 4547 { "monitor", "off" }, 4548 { "mpx", "off" }, 4549 { /* end of list */ }, 4550 }, 4551 }, 4552 { 4553 .version = 3, 4554 .note = "XSAVES, no MPX, no MONITOR", 4555 .props = (PropValue[]) { 4556 { "xsaves", "on" }, 4557 { "vmx-xsaves", "on" }, 4558 { /* end of list */ }, 4559 }, 4560 }, 4561 { /* end of list */ }, 4562 }, 4563 }, 4564 { 4565 .name = "Snowridge", 4566 .level = 27, 4567 .vendor = CPUID_VENDOR_INTEL, 4568 .family = 6, 4569 .model = 134, 4570 .stepping = 1, 4571 .features[FEAT_1_EDX] = 4572 /* missing: CPUID_PN CPUID_IA64 */ 4573 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4574 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4575 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4576 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4577 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4578 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4579 CPUID_MMX | 4580 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4581 .features[FEAT_1_ECX] = 4582 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4583 CPUID_EXT_SSSE3 | 4584 CPUID_EXT_CX16 | 4585 CPUID_EXT_SSE41 | 4586 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4587 CPUID_EXT_POPCNT | 4588 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4589 CPUID_EXT_RDRAND, 4590 .features[FEAT_8000_0001_EDX] = 4591 CPUID_EXT2_SYSCALL | 4592 CPUID_EXT2_NX | 4593 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4594 CPUID_EXT2_LM, 4595 .features[FEAT_8000_0001_ECX] = 4596 CPUID_EXT3_LAHF_LM | 4597 CPUID_EXT3_3DNOWPREFETCH, 4598 .features[FEAT_7_0_EBX] = 4599 CPUID_7_0_EBX_FSGSBASE | 4600 CPUID_7_0_EBX_SMEP | 4601 CPUID_7_0_EBX_ERMS | 4602 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4603 CPUID_7_0_EBX_RDSEED | 4604 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4605 CPUID_7_0_EBX_CLWB | 4606 CPUID_7_0_EBX_SHA_NI, 4607 .features[FEAT_7_0_ECX] = 4608 CPUID_7_0_ECX_UMIP | 4609 /* missing bit 5 */ 4610 CPUID_7_0_ECX_GFNI | 4611 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4612 CPUID_7_0_ECX_MOVDIR64B, 4613 .features[FEAT_7_0_EDX] = 4614 CPUID_7_0_EDX_SPEC_CTRL | 4615 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4616 CPUID_7_0_EDX_CORE_CAPABILITY, 4617 .features[FEAT_CORE_CAPABILITY] = 4618 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4619 /* XSAVES is added in version 3 */ 4620 .features[FEAT_XSAVE] = 4621 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4622 CPUID_XSAVE_XGETBV1, 4623 .features[FEAT_6_EAX] = 4624 CPUID_6_EAX_ARAT, 4625 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4626 MSR_VMX_BASIC_TRUE_CTLS, 4627 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4628 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4629 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4630 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4631 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4632 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4633 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4634 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4635 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4636 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4637 .features[FEAT_VMX_EXIT_CTLS] = 4638 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4639 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4640 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4641 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4642 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4643 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4644 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4645 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4646 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4647 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4648 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4649 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4650 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4651 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4652 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4653 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4654 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4655 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4656 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4657 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4658 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4659 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4660 .features[FEAT_VMX_SECONDARY_CTLS] = 4661 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4662 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4663 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4664 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4665 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4666 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4667 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4668 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4669 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4670 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4671 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4672 .xlevel = 0x80000008, 4673 .model_id = "Intel Atom Processor (SnowRidge)", 4674 .versions = (X86CPUVersionDefinition[]) { 4675 { .version = 1 }, 4676 { 4677 .version = 2, 4678 .props = (PropValue[]) { 4679 { "mpx", "off" }, 4680 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4681 { /* end of list */ }, 4682 }, 4683 }, 4684 { 4685 .version = 3, 4686 .note = "XSAVES, no MPX", 4687 .props = (PropValue[]) { 4688 { "xsaves", "on" }, 4689 { "vmx-xsaves", "on" }, 4690 { /* end of list */ }, 4691 }, 4692 }, 4693 { 4694 .version = 4, 4695 .note = "no split lock detect, no core-capability", 4696 .props = (PropValue[]) { 4697 { "split-lock-detect", "off" }, 4698 { "core-capability", "off" }, 4699 { /* end of list */ }, 4700 }, 4701 }, 4702 { /* end of list */ }, 4703 }, 4704 }, 4705 { 4706 .name = "KnightsMill", 4707 .level = 0xd, 4708 .vendor = CPUID_VENDOR_INTEL, 4709 .family = 6, 4710 .model = 133, 4711 .stepping = 0, 4712 .features[FEAT_1_EDX] = 4713 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4714 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4715 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4716 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4717 CPUID_PSE | CPUID_DE | CPUID_FP87, 4718 .features[FEAT_1_ECX] = 4719 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4720 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4721 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4722 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4723 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4724 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4725 .features[FEAT_8000_0001_EDX] = 4726 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4727 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4728 .features[FEAT_8000_0001_ECX] = 4729 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4730 .features[FEAT_7_0_EBX] = 4731 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4732 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4733 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4734 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4735 CPUID_7_0_EBX_AVX512ER, 4736 .features[FEAT_7_0_ECX] = 4737 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4738 .features[FEAT_7_0_EDX] = 4739 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4740 .features[FEAT_XSAVE] = 4741 CPUID_XSAVE_XSAVEOPT, 4742 .features[FEAT_6_EAX] = 4743 CPUID_6_EAX_ARAT, 4744 .xlevel = 0x80000008, 4745 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4746 }, 4747 { 4748 .name = "Opteron_G1", 4749 .level = 5, 4750 .vendor = CPUID_VENDOR_AMD, 4751 .family = 15, 4752 .model = 6, 4753 .stepping = 1, 4754 .features[FEAT_1_EDX] = 4755 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4756 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4757 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4758 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4759 CPUID_DE | CPUID_FP87, 4760 .features[FEAT_1_ECX] = 4761 CPUID_EXT_SSE3, 4762 .features[FEAT_8000_0001_EDX] = 4763 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4764 .xlevel = 0x80000008, 4765 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4766 }, 4767 { 4768 .name = "Opteron_G2", 4769 .level = 5, 4770 .vendor = CPUID_VENDOR_AMD, 4771 .family = 15, 4772 .model = 6, 4773 .stepping = 1, 4774 .features[FEAT_1_EDX] = 4775 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4776 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4777 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4778 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4779 CPUID_DE | CPUID_FP87, 4780 .features[FEAT_1_ECX] = 4781 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4782 .features[FEAT_8000_0001_EDX] = 4783 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4784 .features[FEAT_8000_0001_ECX] = 4785 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4786 .xlevel = 0x80000008, 4787 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4788 }, 4789 { 4790 .name = "Opteron_G3", 4791 .level = 5, 4792 .vendor = CPUID_VENDOR_AMD, 4793 .family = 16, 4794 .model = 2, 4795 .stepping = 3, 4796 .features[FEAT_1_EDX] = 4797 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4798 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4799 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4800 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4801 CPUID_DE | CPUID_FP87, 4802 .features[FEAT_1_ECX] = 4803 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4804 CPUID_EXT_SSE3, 4805 .features[FEAT_8000_0001_EDX] = 4806 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4807 CPUID_EXT2_RDTSCP, 4808 .features[FEAT_8000_0001_ECX] = 4809 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4810 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4811 .xlevel = 0x80000008, 4812 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4813 }, 4814 { 4815 .name = "Opteron_G4", 4816 .level = 0xd, 4817 .vendor = CPUID_VENDOR_AMD, 4818 .family = 21, 4819 .model = 1, 4820 .stepping = 2, 4821 .features[FEAT_1_EDX] = 4822 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4823 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4824 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4825 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4826 CPUID_DE | CPUID_FP87, 4827 .features[FEAT_1_ECX] = 4828 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4829 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4830 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4831 CPUID_EXT_SSE3, 4832 .features[FEAT_8000_0001_EDX] = 4833 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4834 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4835 .features[FEAT_8000_0001_ECX] = 4836 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4837 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4838 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4839 CPUID_EXT3_LAHF_LM, 4840 .features[FEAT_SVM] = 4841 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4842 /* no xsaveopt! */ 4843 .xlevel = 0x8000001A, 4844 .model_id = "AMD Opteron 62xx class CPU", 4845 }, 4846 { 4847 .name = "Opteron_G5", 4848 .level = 0xd, 4849 .vendor = CPUID_VENDOR_AMD, 4850 .family = 21, 4851 .model = 2, 4852 .stepping = 0, 4853 .features[FEAT_1_EDX] = 4854 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4855 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4856 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4857 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4858 CPUID_DE | CPUID_FP87, 4859 .features[FEAT_1_ECX] = 4860 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4861 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4862 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4863 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4864 .features[FEAT_8000_0001_EDX] = 4865 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4866 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4867 .features[FEAT_8000_0001_ECX] = 4868 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4869 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4870 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4871 CPUID_EXT3_LAHF_LM, 4872 .features[FEAT_SVM] = 4873 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4874 /* no xsaveopt! */ 4875 .xlevel = 0x8000001A, 4876 .model_id = "AMD Opteron 63xx class CPU", 4877 }, 4878 { 4879 .name = "EPYC", 4880 .level = 0xd, 4881 .vendor = CPUID_VENDOR_AMD, 4882 .family = 23, 4883 .model = 1, 4884 .stepping = 2, 4885 .features[FEAT_1_EDX] = 4886 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4887 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4888 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4889 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4890 CPUID_VME | CPUID_FP87, 4891 .features[FEAT_1_ECX] = 4892 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4893 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4894 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4895 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4896 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4897 .features[FEAT_8000_0001_EDX] = 4898 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4899 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4900 CPUID_EXT2_SYSCALL, 4901 .features[FEAT_8000_0001_ECX] = 4902 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4903 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4904 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4905 CPUID_EXT3_TOPOEXT, 4906 .features[FEAT_7_0_EBX] = 4907 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4908 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4909 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4910 CPUID_7_0_EBX_SHA_NI, 4911 .features[FEAT_XSAVE] = 4912 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4913 CPUID_XSAVE_XGETBV1, 4914 .features[FEAT_6_EAX] = 4915 CPUID_6_EAX_ARAT, 4916 .features[FEAT_SVM] = 4917 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4918 .xlevel = 0x8000001E, 4919 .model_id = "AMD EPYC Processor", 4920 .cache_info = &epyc_cache_info, 4921 .versions = (X86CPUVersionDefinition[]) { 4922 { .version = 1 }, 4923 { 4924 .version = 2, 4925 .alias = "EPYC-IBPB", 4926 .props = (PropValue[]) { 4927 { "ibpb", "on" }, 4928 { "model-id", 4929 "AMD EPYC Processor (with IBPB)" }, 4930 { /* end of list */ } 4931 } 4932 }, 4933 { 4934 .version = 3, 4935 .props = (PropValue[]) { 4936 { "ibpb", "on" }, 4937 { "perfctr-core", "on" }, 4938 { "clzero", "on" }, 4939 { "xsaveerptr", "on" }, 4940 { "xsaves", "on" }, 4941 { "model-id", 4942 "AMD EPYC Processor" }, 4943 { /* end of list */ } 4944 } 4945 }, 4946 { 4947 .version = 4, 4948 .props = (PropValue[]) { 4949 { "model-id", 4950 "AMD EPYC-v4 Processor" }, 4951 { /* end of list */ } 4952 }, 4953 .cache_info = &epyc_v4_cache_info 4954 }, 4955 { /* end of list */ } 4956 } 4957 }, 4958 { 4959 .name = "Dhyana", 4960 .level = 0xd, 4961 .vendor = CPUID_VENDOR_HYGON, 4962 .family = 24, 4963 .model = 0, 4964 .stepping = 1, 4965 .features[FEAT_1_EDX] = 4966 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4967 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4968 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4969 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4970 CPUID_VME | CPUID_FP87, 4971 .features[FEAT_1_ECX] = 4972 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4973 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4974 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4975 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4976 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4977 .features[FEAT_8000_0001_EDX] = 4978 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4979 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4980 CPUID_EXT2_SYSCALL, 4981 .features[FEAT_8000_0001_ECX] = 4982 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4983 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4984 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4985 CPUID_EXT3_TOPOEXT, 4986 .features[FEAT_8000_0008_EBX] = 4987 CPUID_8000_0008_EBX_IBPB, 4988 .features[FEAT_7_0_EBX] = 4989 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4990 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4991 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4992 /* XSAVES is added in version 2 */ 4993 .features[FEAT_XSAVE] = 4994 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4995 CPUID_XSAVE_XGETBV1, 4996 .features[FEAT_6_EAX] = 4997 CPUID_6_EAX_ARAT, 4998 .features[FEAT_SVM] = 4999 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5000 .xlevel = 0x8000001E, 5001 .model_id = "Hygon Dhyana Processor", 5002 .cache_info = &epyc_cache_info, 5003 .versions = (X86CPUVersionDefinition[]) { 5004 { .version = 1 }, 5005 { .version = 2, 5006 .note = "XSAVES", 5007 .props = (PropValue[]) { 5008 { "xsaves", "on" }, 5009 { /* end of list */ } 5010 }, 5011 }, 5012 { /* end of list */ } 5013 } 5014 }, 5015 { 5016 .name = "EPYC-Rome", 5017 .level = 0xd, 5018 .vendor = CPUID_VENDOR_AMD, 5019 .family = 23, 5020 .model = 49, 5021 .stepping = 0, 5022 .features[FEAT_1_EDX] = 5023 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5024 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5025 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5026 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5027 CPUID_VME | CPUID_FP87, 5028 .features[FEAT_1_ECX] = 5029 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5030 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5031 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5032 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5033 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5034 .features[FEAT_8000_0001_EDX] = 5035 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5036 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5037 CPUID_EXT2_SYSCALL, 5038 .features[FEAT_8000_0001_ECX] = 5039 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5040 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5041 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5042 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5043 .features[FEAT_8000_0008_EBX] = 5044 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5045 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5046 CPUID_8000_0008_EBX_STIBP, 5047 .features[FEAT_7_0_EBX] = 5048 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5049 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5050 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5051 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5052 .features[FEAT_7_0_ECX] = 5053 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5054 .features[FEAT_XSAVE] = 5055 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5056 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5057 .features[FEAT_6_EAX] = 5058 CPUID_6_EAX_ARAT, 5059 .features[FEAT_SVM] = 5060 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5061 .xlevel = 0x8000001E, 5062 .model_id = "AMD EPYC-Rome Processor", 5063 .cache_info = &epyc_rome_cache_info, 5064 .versions = (X86CPUVersionDefinition[]) { 5065 { .version = 1 }, 5066 { 5067 .version = 2, 5068 .props = (PropValue[]) { 5069 { "ibrs", "on" }, 5070 { "amd-ssbd", "on" }, 5071 { /* end of list */ } 5072 } 5073 }, 5074 { 5075 .version = 3, 5076 .props = (PropValue[]) { 5077 { "model-id", 5078 "AMD EPYC-Rome-v3 Processor" }, 5079 { /* end of list */ } 5080 }, 5081 .cache_info = &epyc_rome_v3_cache_info 5082 }, 5083 { 5084 .version = 4, 5085 .props = (PropValue[]) { 5086 /* Erratum 1386 */ 5087 { "model-id", 5088 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5089 { "xsaves", "off" }, 5090 { /* end of list */ } 5091 }, 5092 }, 5093 { /* end of list */ } 5094 } 5095 }, 5096 { 5097 .name = "EPYC-Milan", 5098 .level = 0xd, 5099 .vendor = CPUID_VENDOR_AMD, 5100 .family = 25, 5101 .model = 1, 5102 .stepping = 1, 5103 .features[FEAT_1_EDX] = 5104 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5105 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5106 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5107 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5108 CPUID_VME | CPUID_FP87, 5109 .features[FEAT_1_ECX] = 5110 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5111 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5112 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5113 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5114 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5115 CPUID_EXT_PCID, 5116 .features[FEAT_8000_0001_EDX] = 5117 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5118 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5119 CPUID_EXT2_SYSCALL, 5120 .features[FEAT_8000_0001_ECX] = 5121 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5122 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5123 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5124 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5125 .features[FEAT_8000_0008_EBX] = 5126 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5127 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5128 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5129 CPUID_8000_0008_EBX_AMD_SSBD, 5130 .features[FEAT_7_0_EBX] = 5131 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5132 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5133 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5134 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5135 CPUID_7_0_EBX_INVPCID, 5136 .features[FEAT_7_0_ECX] = 5137 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5138 .features[FEAT_7_0_EDX] = 5139 CPUID_7_0_EDX_FSRM, 5140 .features[FEAT_XSAVE] = 5141 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5142 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5143 .features[FEAT_6_EAX] = 5144 CPUID_6_EAX_ARAT, 5145 .features[FEAT_SVM] = 5146 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5147 .xlevel = 0x8000001E, 5148 .model_id = "AMD EPYC-Milan Processor", 5149 .cache_info = &epyc_milan_cache_info, 5150 .versions = (X86CPUVersionDefinition[]) { 5151 { .version = 1 }, 5152 { 5153 .version = 2, 5154 .props = (PropValue[]) { 5155 { "model-id", 5156 "AMD EPYC-Milan-v2 Processor" }, 5157 { "vaes", "on" }, 5158 { "vpclmulqdq", "on" }, 5159 { "stibp-always-on", "on" }, 5160 { "amd-psfd", "on" }, 5161 { "no-nested-data-bp", "on" }, 5162 { "lfence-always-serializing", "on" }, 5163 { "null-sel-clr-base", "on" }, 5164 { /* end of list */ } 5165 }, 5166 .cache_info = &epyc_milan_v2_cache_info 5167 }, 5168 { /* end of list */ } 5169 } 5170 }, 5171 { 5172 .name = "EPYC-Genoa", 5173 .level = 0xd, 5174 .vendor = CPUID_VENDOR_AMD, 5175 .family = 25, 5176 .model = 17, 5177 .stepping = 0, 5178 .features[FEAT_1_EDX] = 5179 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5180 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5181 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5182 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5183 CPUID_VME | CPUID_FP87, 5184 .features[FEAT_1_ECX] = 5185 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5186 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5187 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5188 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5189 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5190 CPUID_EXT_SSE3, 5191 .features[FEAT_8000_0001_EDX] = 5192 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5193 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5194 CPUID_EXT2_SYSCALL, 5195 .features[FEAT_8000_0001_ECX] = 5196 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5197 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5198 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5199 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5200 .features[FEAT_8000_0008_EBX] = 5201 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5202 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5203 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5204 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5205 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5206 .features[FEAT_8000_0021_EAX] = 5207 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 5208 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5209 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5210 CPUID_8000_0021_EAX_AUTO_IBRS, 5211 .features[FEAT_7_0_EBX] = 5212 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5213 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5214 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5215 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5216 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5217 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5218 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5219 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5220 .features[FEAT_7_0_ECX] = 5221 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5222 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5223 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5224 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5225 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5226 CPUID_7_0_ECX_RDPID, 5227 .features[FEAT_7_0_EDX] = 5228 CPUID_7_0_EDX_FSRM, 5229 .features[FEAT_7_1_EAX] = 5230 CPUID_7_1_EAX_AVX512_BF16, 5231 .features[FEAT_XSAVE] = 5232 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5233 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5234 .features[FEAT_6_EAX] = 5235 CPUID_6_EAX_ARAT, 5236 .features[FEAT_SVM] = 5237 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5238 CPUID_SVM_SVME_ADDR_CHK, 5239 .xlevel = 0x80000022, 5240 .model_id = "AMD EPYC-Genoa Processor", 5241 .cache_info = &epyc_genoa_cache_info, 5242 }, 5243 }; 5244 5245 /* 5246 * We resolve CPU model aliases using -v1 when using "-machine 5247 * none", but this is just for compatibility while libvirt isn't 5248 * adapted to resolve CPU model versions before creating VMs. 5249 * See "Runnability guarantee of CPU models" at 5250 * docs/about/deprecated.rst. 5251 */ 5252 X86CPUVersion default_cpu_version = 1; 5253 5254 void x86_cpu_set_default_version(X86CPUVersion version) 5255 { 5256 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5257 assert(version != CPU_VERSION_AUTO); 5258 default_cpu_version = version; 5259 } 5260 5261 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5262 { 5263 int v = 0; 5264 const X86CPUVersionDefinition *vdef = 5265 x86_cpu_def_get_versions(model->cpudef); 5266 while (vdef->version) { 5267 v = vdef->version; 5268 vdef++; 5269 } 5270 return v; 5271 } 5272 5273 /* Return the actual version being used for a specific CPU model */ 5274 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5275 { 5276 X86CPUVersion v = model->version; 5277 if (v == CPU_VERSION_AUTO) { 5278 v = default_cpu_version; 5279 } 5280 if (v == CPU_VERSION_LATEST) { 5281 return x86_cpu_model_last_version(model); 5282 } 5283 return v; 5284 } 5285 5286 static Property max_x86_cpu_properties[] = { 5287 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5288 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5289 DEFINE_PROP_END_OF_LIST() 5290 }; 5291 5292 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5293 { 5294 Object *obj = OBJECT(dev); 5295 5296 if (!object_property_get_int(obj, "family", &error_abort)) { 5297 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5298 object_property_set_int(obj, "family", 15, &error_abort); 5299 object_property_set_int(obj, "model", 107, &error_abort); 5300 object_property_set_int(obj, "stepping", 1, &error_abort); 5301 } else { 5302 object_property_set_int(obj, "family", 6, &error_abort); 5303 object_property_set_int(obj, "model", 6, &error_abort); 5304 object_property_set_int(obj, "stepping", 3, &error_abort); 5305 } 5306 } 5307 5308 x86_cpu_realizefn(dev, errp); 5309 } 5310 5311 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5312 { 5313 DeviceClass *dc = DEVICE_CLASS(oc); 5314 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5315 5316 xcc->ordering = 9; 5317 5318 xcc->model_description = 5319 "Enables all features supported by the accelerator in the current host"; 5320 5321 device_class_set_props(dc, max_x86_cpu_properties); 5322 dc->realize = max_x86_cpu_realize; 5323 } 5324 5325 static void max_x86_cpu_initfn(Object *obj) 5326 { 5327 X86CPU *cpu = X86_CPU(obj); 5328 5329 /* We can't fill the features array here because we don't know yet if 5330 * "migratable" is true or false. 5331 */ 5332 cpu->max_features = true; 5333 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5334 5335 /* 5336 * these defaults are used for TCG and all other accelerators 5337 * besides KVM and HVF, which overwrite these values 5338 */ 5339 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5340 &error_abort); 5341 object_property_set_str(OBJECT(cpu), "model-id", 5342 "QEMU TCG CPU version " QEMU_HW_VERSION, 5343 &error_abort); 5344 } 5345 5346 static const TypeInfo max_x86_cpu_type_info = { 5347 .name = X86_CPU_TYPE_NAME("max"), 5348 .parent = TYPE_X86_CPU, 5349 .instance_init = max_x86_cpu_initfn, 5350 .class_init = max_x86_cpu_class_init, 5351 }; 5352 5353 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5354 { 5355 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5356 5357 switch (f->type) { 5358 case CPUID_FEATURE_WORD: 5359 { 5360 const char *reg = get_register_name_32(f->cpuid.reg); 5361 assert(reg); 5362 return g_strdup_printf("CPUID.%02XH:%s", 5363 f->cpuid.eax, reg); 5364 } 5365 case MSR_FEATURE_WORD: 5366 return g_strdup_printf("MSR(%02XH)", 5367 f->msr.index); 5368 } 5369 5370 return NULL; 5371 } 5372 5373 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5374 { 5375 FeatureWord w; 5376 5377 for (w = 0; w < FEATURE_WORDS; w++) { 5378 if (cpu->filtered_features[w]) { 5379 return true; 5380 } 5381 } 5382 5383 return false; 5384 } 5385 5386 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5387 const char *verbose_prefix) 5388 { 5389 CPUX86State *env = &cpu->env; 5390 FeatureWordInfo *f = &feature_word_info[w]; 5391 int i; 5392 5393 if (!cpu->force_features) { 5394 env->features[w] &= ~mask; 5395 } 5396 cpu->filtered_features[w] |= mask; 5397 5398 if (!verbose_prefix) { 5399 return; 5400 } 5401 5402 for (i = 0; i < 64; ++i) { 5403 if ((1ULL << i) & mask) { 5404 g_autofree char *feat_word_str = feature_word_description(f, i); 5405 warn_report("%s: %s%s%s [bit %d]", 5406 verbose_prefix, 5407 feat_word_str, 5408 f->feat_names[i] ? "." : "", 5409 f->feat_names[i] ? f->feat_names[i] : "", i); 5410 } 5411 } 5412 } 5413 5414 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5415 const char *name, void *opaque, 5416 Error **errp) 5417 { 5418 X86CPU *cpu = X86_CPU(obj); 5419 CPUX86State *env = &cpu->env; 5420 int64_t value; 5421 5422 value = (env->cpuid_version >> 8) & 0xf; 5423 if (value == 0xf) { 5424 value += (env->cpuid_version >> 20) & 0xff; 5425 } 5426 visit_type_int(v, name, &value, errp); 5427 } 5428 5429 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5430 const char *name, void *opaque, 5431 Error **errp) 5432 { 5433 X86CPU *cpu = X86_CPU(obj); 5434 CPUX86State *env = &cpu->env; 5435 const int64_t min = 0; 5436 const int64_t max = 0xff + 0xf; 5437 int64_t value; 5438 5439 if (!visit_type_int(v, name, &value, errp)) { 5440 return; 5441 } 5442 if (value < min || value > max) { 5443 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5444 name ? name : "null", value, min, max); 5445 return; 5446 } 5447 5448 env->cpuid_version &= ~0xff00f00; 5449 if (value > 0x0f) { 5450 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5451 } else { 5452 env->cpuid_version |= value << 8; 5453 } 5454 } 5455 5456 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5457 const char *name, void *opaque, 5458 Error **errp) 5459 { 5460 X86CPU *cpu = X86_CPU(obj); 5461 CPUX86State *env = &cpu->env; 5462 int64_t value; 5463 5464 value = (env->cpuid_version >> 4) & 0xf; 5465 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5466 visit_type_int(v, name, &value, errp); 5467 } 5468 5469 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5470 const char *name, void *opaque, 5471 Error **errp) 5472 { 5473 X86CPU *cpu = X86_CPU(obj); 5474 CPUX86State *env = &cpu->env; 5475 const int64_t min = 0; 5476 const int64_t max = 0xff; 5477 int64_t value; 5478 5479 if (!visit_type_int(v, name, &value, errp)) { 5480 return; 5481 } 5482 if (value < min || value > max) { 5483 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5484 name ? name : "null", value, min, max); 5485 return; 5486 } 5487 5488 env->cpuid_version &= ~0xf00f0; 5489 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5490 } 5491 5492 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5493 const char *name, void *opaque, 5494 Error **errp) 5495 { 5496 X86CPU *cpu = X86_CPU(obj); 5497 CPUX86State *env = &cpu->env; 5498 int64_t value; 5499 5500 value = env->cpuid_version & 0xf; 5501 visit_type_int(v, name, &value, errp); 5502 } 5503 5504 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5505 const char *name, void *opaque, 5506 Error **errp) 5507 { 5508 X86CPU *cpu = X86_CPU(obj); 5509 CPUX86State *env = &cpu->env; 5510 const int64_t min = 0; 5511 const int64_t max = 0xf; 5512 int64_t value; 5513 5514 if (!visit_type_int(v, name, &value, errp)) { 5515 return; 5516 } 5517 if (value < min || value > max) { 5518 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5519 name ? name : "null", value, min, max); 5520 return; 5521 } 5522 5523 env->cpuid_version &= ~0xf; 5524 env->cpuid_version |= value & 0xf; 5525 } 5526 5527 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5528 { 5529 X86CPU *cpu = X86_CPU(obj); 5530 CPUX86State *env = &cpu->env; 5531 char *value; 5532 5533 value = g_malloc(CPUID_VENDOR_SZ + 1); 5534 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5535 env->cpuid_vendor3); 5536 return value; 5537 } 5538 5539 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5540 Error **errp) 5541 { 5542 X86CPU *cpu = X86_CPU(obj); 5543 CPUX86State *env = &cpu->env; 5544 int i; 5545 5546 if (strlen(value) != CPUID_VENDOR_SZ) { 5547 error_setg(errp, "value of property 'vendor' must consist of" 5548 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5549 return; 5550 } 5551 5552 env->cpuid_vendor1 = 0; 5553 env->cpuid_vendor2 = 0; 5554 env->cpuid_vendor3 = 0; 5555 for (i = 0; i < 4; i++) { 5556 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5557 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5558 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5559 } 5560 } 5561 5562 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5563 { 5564 X86CPU *cpu = X86_CPU(obj); 5565 CPUX86State *env = &cpu->env; 5566 char *value; 5567 int i; 5568 5569 value = g_malloc(48 + 1); 5570 for (i = 0; i < 48; i++) { 5571 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5572 } 5573 value[48] = '\0'; 5574 return value; 5575 } 5576 5577 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5578 Error **errp) 5579 { 5580 X86CPU *cpu = X86_CPU(obj); 5581 CPUX86State *env = &cpu->env; 5582 int c, len, i; 5583 5584 if (model_id == NULL) { 5585 model_id = ""; 5586 } 5587 len = strlen(model_id); 5588 memset(env->cpuid_model, 0, 48); 5589 for (i = 0; i < 48; i++) { 5590 if (i >= len) { 5591 c = '\0'; 5592 } else { 5593 c = (uint8_t)model_id[i]; 5594 } 5595 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5596 } 5597 } 5598 5599 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5600 void *opaque, Error **errp) 5601 { 5602 X86CPU *cpu = X86_CPU(obj); 5603 int64_t value; 5604 5605 value = cpu->env.tsc_khz * 1000; 5606 visit_type_int(v, name, &value, errp); 5607 } 5608 5609 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5610 void *opaque, Error **errp) 5611 { 5612 X86CPU *cpu = X86_CPU(obj); 5613 const int64_t min = 0; 5614 const int64_t max = INT64_MAX; 5615 int64_t value; 5616 5617 if (!visit_type_int(v, name, &value, errp)) { 5618 return; 5619 } 5620 if (value < min || value > max) { 5621 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5622 name ? name : "null", value, min, max); 5623 return; 5624 } 5625 5626 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5627 } 5628 5629 /* Generic getter for "feature-words" and "filtered-features" properties */ 5630 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5631 const char *name, void *opaque, 5632 Error **errp) 5633 { 5634 uint64_t *array = (uint64_t *)opaque; 5635 FeatureWord w; 5636 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5637 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5638 X86CPUFeatureWordInfoList *list = NULL; 5639 5640 for (w = 0; w < FEATURE_WORDS; w++) { 5641 FeatureWordInfo *wi = &feature_word_info[w]; 5642 /* 5643 * We didn't have MSR features when "feature-words" was 5644 * introduced. Therefore skipped other type entries. 5645 */ 5646 if (wi->type != CPUID_FEATURE_WORD) { 5647 continue; 5648 } 5649 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5650 qwi->cpuid_input_eax = wi->cpuid.eax; 5651 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5652 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5653 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5654 qwi->features = array[w]; 5655 5656 /* List will be in reverse order, but order shouldn't matter */ 5657 list_entries[w].next = list; 5658 list_entries[w].value = &word_infos[w]; 5659 list = &list_entries[w]; 5660 } 5661 5662 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5663 } 5664 5665 /* Convert all '_' in a feature string option name to '-', to make feature 5666 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5667 */ 5668 static inline void feat2prop(char *s) 5669 { 5670 while ((s = strchr(s, '_'))) { 5671 *s = '-'; 5672 } 5673 } 5674 5675 /* Return the feature property name for a feature flag bit */ 5676 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5677 { 5678 const char *name; 5679 /* XSAVE components are automatically enabled by other features, 5680 * so return the original feature name instead 5681 */ 5682 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5683 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5684 5685 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5686 x86_ext_save_areas[comp].bits) { 5687 w = x86_ext_save_areas[comp].feature; 5688 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5689 } 5690 } 5691 5692 assert(bitnr < 64); 5693 assert(w < FEATURE_WORDS); 5694 name = feature_word_info[w].feat_names[bitnr]; 5695 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5696 return name; 5697 } 5698 5699 /* Compatibility hack to maintain legacy +-feat semantic, 5700 * where +-feat overwrites any feature set by 5701 * feat=on|feat even if the later is parsed after +-feat 5702 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5703 */ 5704 static GList *plus_features, *minus_features; 5705 5706 static gint compare_string(gconstpointer a, gconstpointer b) 5707 { 5708 return g_strcmp0(a, b); 5709 } 5710 5711 /* Parse "+feature,-feature,feature=foo" CPU feature string 5712 */ 5713 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5714 Error **errp) 5715 { 5716 char *featurestr; /* Single 'key=value" string being parsed */ 5717 static bool cpu_globals_initialized; 5718 bool ambiguous = false; 5719 5720 if (cpu_globals_initialized) { 5721 return; 5722 } 5723 cpu_globals_initialized = true; 5724 5725 if (!features) { 5726 return; 5727 } 5728 5729 for (featurestr = strtok(features, ","); 5730 featurestr; 5731 featurestr = strtok(NULL, ",")) { 5732 const char *name; 5733 const char *val = NULL; 5734 char *eq = NULL; 5735 char num[32]; 5736 GlobalProperty *prop; 5737 5738 /* Compatibility syntax: */ 5739 if (featurestr[0] == '+') { 5740 plus_features = g_list_append(plus_features, 5741 g_strdup(featurestr + 1)); 5742 continue; 5743 } else if (featurestr[0] == '-') { 5744 minus_features = g_list_append(minus_features, 5745 g_strdup(featurestr + 1)); 5746 continue; 5747 } 5748 5749 eq = strchr(featurestr, '='); 5750 if (eq) { 5751 *eq++ = 0; 5752 val = eq; 5753 } else { 5754 val = "on"; 5755 } 5756 5757 feat2prop(featurestr); 5758 name = featurestr; 5759 5760 if (g_list_find_custom(plus_features, name, compare_string)) { 5761 warn_report("Ambiguous CPU model string. " 5762 "Don't mix both \"+%s\" and \"%s=%s\"", 5763 name, name, val); 5764 ambiguous = true; 5765 } 5766 if (g_list_find_custom(minus_features, name, compare_string)) { 5767 warn_report("Ambiguous CPU model string. " 5768 "Don't mix both \"-%s\" and \"%s=%s\"", 5769 name, name, val); 5770 ambiguous = true; 5771 } 5772 5773 /* Special case: */ 5774 if (!strcmp(name, "tsc-freq")) { 5775 int ret; 5776 uint64_t tsc_freq; 5777 5778 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5779 if (ret < 0 || tsc_freq > INT64_MAX) { 5780 error_setg(errp, "bad numerical value %s", val); 5781 return; 5782 } 5783 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5784 val = num; 5785 name = "tsc-frequency"; 5786 } 5787 5788 prop = g_new0(typeof(*prop), 1); 5789 prop->driver = typename; 5790 prop->property = g_strdup(name); 5791 prop->value = g_strdup(val); 5792 qdev_prop_register_global(prop); 5793 } 5794 5795 if (ambiguous) { 5796 warn_report("Compatibility of ambiguous CPU model " 5797 "strings won't be kept on future QEMU versions"); 5798 } 5799 } 5800 5801 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5802 5803 /* Build a list with the name of all features on a feature word array */ 5804 static void x86_cpu_list_feature_names(FeatureWordArray features, 5805 strList **list) 5806 { 5807 strList **tail = list; 5808 FeatureWord w; 5809 5810 for (w = 0; w < FEATURE_WORDS; w++) { 5811 uint64_t filtered = features[w]; 5812 int i; 5813 for (i = 0; i < 64; i++) { 5814 if (filtered & (1ULL << i)) { 5815 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5816 } 5817 } 5818 } 5819 } 5820 5821 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5822 const char *name, void *opaque, 5823 Error **errp) 5824 { 5825 X86CPU *xc = X86_CPU(obj); 5826 strList *result = NULL; 5827 5828 x86_cpu_list_feature_names(xc->filtered_features, &result); 5829 visit_type_strList(v, "unavailable-features", &result, errp); 5830 } 5831 5832 /* Print all cpuid feature names in featureset 5833 */ 5834 static void listflags(GList *features) 5835 { 5836 size_t len = 0; 5837 GList *tmp; 5838 5839 for (tmp = features; tmp; tmp = tmp->next) { 5840 const char *name = tmp->data; 5841 if ((len + strlen(name) + 1) >= 75) { 5842 qemu_printf("\n"); 5843 len = 0; 5844 } 5845 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5846 len += strlen(name) + 1; 5847 } 5848 qemu_printf("\n"); 5849 } 5850 5851 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5852 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5853 { 5854 ObjectClass *class_a = (ObjectClass *)a; 5855 ObjectClass *class_b = (ObjectClass *)b; 5856 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5857 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5858 int ret; 5859 5860 if (cc_a->ordering != cc_b->ordering) { 5861 ret = cc_a->ordering - cc_b->ordering; 5862 } else { 5863 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5864 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5865 ret = strcmp(name_a, name_b); 5866 } 5867 return ret; 5868 } 5869 5870 static GSList *get_sorted_cpu_model_list(void) 5871 { 5872 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5873 list = g_slist_sort(list, x86_cpu_list_compare); 5874 return list; 5875 } 5876 5877 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5878 { 5879 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5880 char *r = object_property_get_str(obj, "model-id", &error_abort); 5881 object_unref(obj); 5882 return r; 5883 } 5884 5885 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5886 { 5887 X86CPUVersion version; 5888 5889 if (!cc->model || !cc->model->is_alias) { 5890 return NULL; 5891 } 5892 version = x86_cpu_model_resolve_version(cc->model); 5893 if (version <= 0) { 5894 return NULL; 5895 } 5896 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5897 } 5898 5899 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5900 { 5901 ObjectClass *oc = data; 5902 X86CPUClass *cc = X86_CPU_CLASS(oc); 5903 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5904 g_autofree char *desc = g_strdup(cc->model_description); 5905 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5906 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5907 5908 if (!desc && alias_of) { 5909 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5910 desc = g_strdup("(alias configured by machine type)"); 5911 } else { 5912 desc = g_strdup_printf("(alias of %s)", alias_of); 5913 } 5914 } 5915 if (!desc && cc->model && cc->model->note) { 5916 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5917 } 5918 if (!desc) { 5919 desc = g_strdup_printf("%s", model_id); 5920 } 5921 5922 if (cc->model && cc->model->cpudef->deprecation_note) { 5923 g_autofree char *olddesc = desc; 5924 desc = g_strdup_printf("%s (deprecated)", olddesc); 5925 } 5926 5927 qemu_printf(" %-20s %s\n", name, desc); 5928 } 5929 5930 /* list available CPU models and flags */ 5931 void x86_cpu_list(void) 5932 { 5933 int i, j; 5934 GSList *list; 5935 GList *names = NULL; 5936 5937 qemu_printf("Available CPUs:\n"); 5938 list = get_sorted_cpu_model_list(); 5939 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5940 g_slist_free(list); 5941 5942 names = NULL; 5943 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5944 FeatureWordInfo *fw = &feature_word_info[i]; 5945 for (j = 0; j < 64; j++) { 5946 if (fw->feat_names[j]) { 5947 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5948 } 5949 } 5950 } 5951 5952 names = g_list_sort(names, (GCompareFunc)strcmp); 5953 5954 qemu_printf("\nRecognized CPUID flags:\n"); 5955 listflags(names); 5956 qemu_printf("\n"); 5957 g_list_free(names); 5958 } 5959 5960 #ifndef CONFIG_USER_ONLY 5961 5962 /* Check for missing features that may prevent the CPU class from 5963 * running using the current machine and accelerator. 5964 */ 5965 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5966 strList **list) 5967 { 5968 strList **tail = list; 5969 X86CPU *xc; 5970 Error *err = NULL; 5971 5972 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5973 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5974 return; 5975 } 5976 5977 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5978 5979 x86_cpu_expand_features(xc, &err); 5980 if (err) { 5981 /* Errors at x86_cpu_expand_features should never happen, 5982 * but in case it does, just report the model as not 5983 * runnable at all using the "type" property. 5984 */ 5985 QAPI_LIST_APPEND(tail, g_strdup("type")); 5986 error_free(err); 5987 } 5988 5989 x86_cpu_filter_features(xc, false); 5990 5991 x86_cpu_list_feature_names(xc->filtered_features, tail); 5992 5993 object_unref(OBJECT(xc)); 5994 } 5995 5996 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5997 { 5998 ObjectClass *oc = data; 5999 X86CPUClass *cc = X86_CPU_CLASS(oc); 6000 CpuDefinitionInfoList **cpu_list = user_data; 6001 CpuDefinitionInfo *info; 6002 6003 info = g_malloc0(sizeof(*info)); 6004 info->name = x86_cpu_class_get_model_name(cc); 6005 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6006 info->has_unavailable_features = true; 6007 info->q_typename = g_strdup(object_class_get_name(oc)); 6008 info->migration_safe = cc->migration_safe; 6009 info->has_migration_safe = true; 6010 info->q_static = cc->static_model; 6011 if (cc->model && cc->model->cpudef->deprecation_note) { 6012 info->deprecated = true; 6013 } else { 6014 info->deprecated = false; 6015 } 6016 /* 6017 * Old machine types won't report aliases, so that alias translation 6018 * doesn't break compatibility with previous QEMU versions. 6019 */ 6020 if (default_cpu_version != CPU_VERSION_LEGACY) { 6021 info->alias_of = x86_cpu_class_get_alias_of(cc); 6022 } 6023 6024 QAPI_LIST_PREPEND(*cpu_list, info); 6025 } 6026 6027 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6028 { 6029 CpuDefinitionInfoList *cpu_list = NULL; 6030 GSList *list = get_sorted_cpu_model_list(); 6031 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6032 g_slist_free(list); 6033 return cpu_list; 6034 } 6035 6036 #endif /* !CONFIG_USER_ONLY */ 6037 6038 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6039 { 6040 FeatureWordInfo *wi = &feature_word_info[w]; 6041 uint64_t r = 0; 6042 uint32_t unavail = 0; 6043 6044 if (kvm_enabled()) { 6045 switch (wi->type) { 6046 case CPUID_FEATURE_WORD: 6047 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6048 wi->cpuid.ecx, 6049 wi->cpuid.reg); 6050 break; 6051 case MSR_FEATURE_WORD: 6052 r = kvm_arch_get_supported_msr_feature(kvm_state, 6053 wi->msr.index); 6054 break; 6055 } 6056 } else if (hvf_enabled()) { 6057 if (wi->type != CPUID_FEATURE_WORD) { 6058 return 0; 6059 } 6060 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6061 wi->cpuid.ecx, 6062 wi->cpuid.reg); 6063 } else if (tcg_enabled()) { 6064 r = wi->tcg_features; 6065 } else { 6066 return ~0; 6067 } 6068 6069 switch (w) { 6070 #ifndef TARGET_X86_64 6071 case FEAT_8000_0001_EDX: 6072 /* 6073 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6074 * way for userspace to get out of its 32-bit jail, we can leave 6075 * the LM bit set. 6076 */ 6077 unavail = tcg_enabled() 6078 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6079 : CPUID_EXT2_LM; 6080 break; 6081 #endif 6082 6083 case FEAT_8000_0007_EBX: 6084 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6085 /* Disable AMD machine check architecture for Intel CPU. */ 6086 unavail = ~0; 6087 } 6088 break; 6089 6090 default: 6091 break; 6092 } 6093 6094 r &= ~unavail; 6095 if (cpu && cpu->migratable) { 6096 r &= x86_cpu_get_migratable_flags(w); 6097 } 6098 return r; 6099 } 6100 6101 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6102 uint32_t *eax, uint32_t *ebx, 6103 uint32_t *ecx, uint32_t *edx) 6104 { 6105 if (kvm_enabled()) { 6106 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6107 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6108 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6109 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6110 } else if (hvf_enabled()) { 6111 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6112 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6113 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6114 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6115 } else { 6116 *eax = 0; 6117 *ebx = 0; 6118 *ecx = 0; 6119 *edx = 0; 6120 } 6121 } 6122 6123 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6124 uint32_t *eax, uint32_t *ebx, 6125 uint32_t *ecx, uint32_t *edx) 6126 { 6127 uint32_t level, unused; 6128 6129 /* Only return valid host leaves. */ 6130 switch (func) { 6131 case 2: 6132 case 4: 6133 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6134 break; 6135 case 0x80000005: 6136 case 0x80000006: 6137 case 0x8000001d: 6138 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6139 break; 6140 default: 6141 return; 6142 } 6143 6144 if (func > level) { 6145 *eax = 0; 6146 *ebx = 0; 6147 *ecx = 0; 6148 *edx = 0; 6149 } else { 6150 host_cpuid(func, index, eax, ebx, ecx, edx); 6151 } 6152 } 6153 6154 /* 6155 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6156 */ 6157 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6158 { 6159 PropValue *pv; 6160 for (pv = props; pv->prop; pv++) { 6161 if (!pv->value) { 6162 continue; 6163 } 6164 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6165 &error_abort); 6166 } 6167 } 6168 6169 /* 6170 * Apply properties for the CPU model version specified in model. 6171 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6172 */ 6173 6174 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6175 { 6176 const X86CPUVersionDefinition *vdef; 6177 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6178 6179 if (version == CPU_VERSION_LEGACY) { 6180 return; 6181 } 6182 6183 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6184 PropValue *p; 6185 6186 for (p = vdef->props; p && p->prop; p++) { 6187 object_property_parse(OBJECT(cpu), p->prop, p->value, 6188 &error_abort); 6189 } 6190 6191 if (vdef->version == version) { 6192 break; 6193 } 6194 } 6195 6196 /* 6197 * If we reached the end of the list, version number was invalid 6198 */ 6199 assert(vdef->version == version); 6200 } 6201 6202 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6203 X86CPUModel *model) 6204 { 6205 const X86CPUVersionDefinition *vdef; 6206 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6207 const CPUCaches *cache_info = model->cpudef->cache_info; 6208 6209 if (version == CPU_VERSION_LEGACY) { 6210 return cache_info; 6211 } 6212 6213 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6214 if (vdef->cache_info) { 6215 cache_info = vdef->cache_info; 6216 } 6217 6218 if (vdef->version == version) { 6219 break; 6220 } 6221 } 6222 6223 assert(vdef->version == version); 6224 return cache_info; 6225 } 6226 6227 /* 6228 * Load data from X86CPUDefinition into a X86CPU object. 6229 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6230 */ 6231 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6232 { 6233 const X86CPUDefinition *def = model->cpudef; 6234 CPUX86State *env = &cpu->env; 6235 FeatureWord w; 6236 6237 /*NOTE: any property set by this function should be returned by 6238 * x86_cpu_static_props(), so static expansion of 6239 * query-cpu-model-expansion is always complete. 6240 */ 6241 6242 /* CPU models only set _minimum_ values for level/xlevel: */ 6243 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6244 &error_abort); 6245 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6246 &error_abort); 6247 6248 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6249 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6250 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6251 &error_abort); 6252 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6253 &error_abort); 6254 for (w = 0; w < FEATURE_WORDS; w++) { 6255 env->features[w] = def->features[w]; 6256 } 6257 6258 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6259 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6260 6261 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6262 6263 /* sysenter isn't supported in compatibility mode on AMD, 6264 * syscall isn't supported in compatibility mode on Intel. 6265 * Normally we advertise the actual CPU vendor, but you can 6266 * override this using the 'vendor' property if you want to use 6267 * KVM's sysenter/syscall emulation in compatibility mode and 6268 * when doing cross vendor migration 6269 */ 6270 6271 /* 6272 * vendor property is set here but then overloaded with the 6273 * host cpu vendor for KVM and HVF. 6274 */ 6275 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6276 6277 x86_cpu_apply_version_props(cpu, model); 6278 6279 /* 6280 * Properties in versioned CPU model are not user specified features. 6281 * We can simply clear env->user_features here since it will be filled later 6282 * in x86_cpu_expand_features() based on plus_features and minus_features. 6283 */ 6284 memset(&env->user_features, 0, sizeof(env->user_features)); 6285 } 6286 6287 static const gchar *x86_gdb_arch_name(CPUState *cs) 6288 { 6289 #ifdef TARGET_X86_64 6290 return "i386:x86-64"; 6291 #else 6292 return "i386"; 6293 #endif 6294 } 6295 6296 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6297 { 6298 X86CPUModel *model = data; 6299 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6300 CPUClass *cc = CPU_CLASS(oc); 6301 6302 xcc->model = model; 6303 xcc->migration_safe = true; 6304 cc->deprecation_note = model->cpudef->deprecation_note; 6305 } 6306 6307 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6308 { 6309 g_autofree char *typename = x86_cpu_type_name(name); 6310 TypeInfo ti = { 6311 .name = typename, 6312 .parent = TYPE_X86_CPU, 6313 .class_init = x86_cpu_cpudef_class_init, 6314 .class_data = model, 6315 }; 6316 6317 type_register(&ti); 6318 } 6319 6320 6321 /* 6322 * register builtin_x86_defs; 6323 * "max", "base" and subclasses ("host") are not registered here. 6324 * See x86_cpu_register_types for all model registrations. 6325 */ 6326 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6327 { 6328 X86CPUModel *m; 6329 const X86CPUVersionDefinition *vdef; 6330 6331 /* AMD aliases are handled at runtime based on CPUID vendor, so 6332 * they shouldn't be set on the CPU model table. 6333 */ 6334 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6335 /* catch mistakes instead of silently truncating model_id when too long */ 6336 assert(def->model_id && strlen(def->model_id) <= 48); 6337 6338 /* Unversioned model: */ 6339 m = g_new0(X86CPUModel, 1); 6340 m->cpudef = def; 6341 m->version = CPU_VERSION_AUTO; 6342 m->is_alias = true; 6343 x86_register_cpu_model_type(def->name, m); 6344 6345 /* Versioned models: */ 6346 6347 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6348 g_autofree char *name = 6349 x86_cpu_versioned_model_name(def, vdef->version); 6350 6351 m = g_new0(X86CPUModel, 1); 6352 m->cpudef = def; 6353 m->version = vdef->version; 6354 m->note = vdef->note; 6355 x86_register_cpu_model_type(name, m); 6356 6357 if (vdef->alias) { 6358 X86CPUModel *am = g_new0(X86CPUModel, 1); 6359 am->cpudef = def; 6360 am->version = vdef->version; 6361 am->is_alias = true; 6362 x86_register_cpu_model_type(vdef->alias, am); 6363 } 6364 } 6365 6366 } 6367 6368 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6369 { 6370 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6371 return 57; /* 57 bits virtual */ 6372 } else { 6373 return 48; /* 48 bits virtual */ 6374 } 6375 } 6376 6377 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6378 uint32_t *eax, uint32_t *ebx, 6379 uint32_t *ecx, uint32_t *edx) 6380 { 6381 X86CPU *cpu = env_archcpu(env); 6382 CPUState *cs = env_cpu(env); 6383 uint32_t limit; 6384 uint32_t signature[3]; 6385 X86CPUTopoInfo topo_info; 6386 uint32_t cores_per_pkg; 6387 uint32_t threads_per_pkg; 6388 6389 topo_info.dies_per_pkg = env->nr_dies; 6390 topo_info.modules_per_die = env->nr_modules; 6391 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6392 topo_info.threads_per_core = cs->nr_threads; 6393 6394 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6395 topo_info.dies_per_pkg; 6396 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6397 6398 /* Calculate & apply limits for different index ranges */ 6399 if (index >= 0xC0000000) { 6400 limit = env->cpuid_xlevel2; 6401 } else if (index >= 0x80000000) { 6402 limit = env->cpuid_xlevel; 6403 } else if (index >= 0x40000000) { 6404 limit = 0x40000001; 6405 } else { 6406 limit = env->cpuid_level; 6407 } 6408 6409 if (index > limit) { 6410 /* Intel documentation states that invalid EAX input will 6411 * return the same information as EAX=cpuid_level 6412 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6413 */ 6414 index = env->cpuid_level; 6415 } 6416 6417 switch(index) { 6418 case 0: 6419 *eax = env->cpuid_level; 6420 *ebx = env->cpuid_vendor1; 6421 *edx = env->cpuid_vendor2; 6422 *ecx = env->cpuid_vendor3; 6423 break; 6424 case 1: 6425 *eax = env->cpuid_version; 6426 *ebx = (cpu->apic_id << 24) | 6427 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6428 *ecx = env->features[FEAT_1_ECX]; 6429 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6430 *ecx |= CPUID_EXT_OSXSAVE; 6431 } 6432 *edx = env->features[FEAT_1_EDX]; 6433 if (threads_per_pkg > 1) { 6434 *ebx |= threads_per_pkg << 16; 6435 *edx |= CPUID_HT; 6436 } 6437 if (!cpu->enable_pmu) { 6438 *ecx &= ~CPUID_EXT_PDCM; 6439 } 6440 break; 6441 case 2: 6442 /* cache info: needed for Pentium Pro compatibility */ 6443 if (cpu->cache_info_passthrough) { 6444 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6445 break; 6446 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6447 *eax = *ebx = *ecx = *edx = 0; 6448 break; 6449 } 6450 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6451 *ebx = 0; 6452 if (!cpu->enable_l3_cache) { 6453 *ecx = 0; 6454 } else { 6455 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6456 } 6457 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6458 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6459 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6460 break; 6461 case 4: 6462 /* cache info: needed for Core compatibility */ 6463 if (cpu->cache_info_passthrough) { 6464 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6465 /* 6466 * QEMU has its own number of cores/logical cpus, 6467 * set 24..14, 31..26 bit to configured values 6468 */ 6469 if (*eax & 31) { 6470 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6471 6472 *eax &= ~0xFC000000; 6473 *eax |= max_core_ids_in_package(&topo_info) << 26; 6474 if (host_vcpus_per_cache > threads_per_pkg) { 6475 *eax &= ~0x3FFC000; 6476 6477 /* Share the cache at package level. */ 6478 *eax |= max_thread_ids_for_cache(&topo_info, 6479 CPU_TOPO_LEVEL_PACKAGE) << 14; 6480 } 6481 } 6482 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6483 *eax = *ebx = *ecx = *edx = 0; 6484 } else { 6485 *eax = 0; 6486 6487 switch (count) { 6488 case 0: /* L1 dcache info */ 6489 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6490 &topo_info, 6491 eax, ebx, ecx, edx); 6492 if (!cpu->l1_cache_per_core) { 6493 *eax &= ~MAKE_64BIT_MASK(14, 12); 6494 } 6495 break; 6496 case 1: /* L1 icache info */ 6497 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6498 &topo_info, 6499 eax, ebx, ecx, edx); 6500 if (!cpu->l1_cache_per_core) { 6501 *eax &= ~MAKE_64BIT_MASK(14, 12); 6502 } 6503 break; 6504 case 2: /* L2 cache info */ 6505 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6506 &topo_info, 6507 eax, ebx, ecx, edx); 6508 break; 6509 case 3: /* L3 cache info */ 6510 if (cpu->enable_l3_cache) { 6511 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6512 &topo_info, 6513 eax, ebx, ecx, edx); 6514 break; 6515 } 6516 /* fall through */ 6517 default: /* end of info */ 6518 *eax = *ebx = *ecx = *edx = 0; 6519 break; 6520 } 6521 } 6522 break; 6523 case 5: 6524 /* MONITOR/MWAIT Leaf */ 6525 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6526 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6527 *ecx = cpu->mwait.ecx; /* flags */ 6528 *edx = cpu->mwait.edx; /* mwait substates */ 6529 break; 6530 case 6: 6531 /* Thermal and Power Leaf */ 6532 *eax = env->features[FEAT_6_EAX]; 6533 *ebx = 0; 6534 *ecx = 0; 6535 *edx = 0; 6536 break; 6537 case 7: 6538 /* Structured Extended Feature Flags Enumeration Leaf */ 6539 if (count == 0) { 6540 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused; 6541 6542 /* Maximum ECX value for sub-leaves */ 6543 *eax = env->cpuid_level_func7; 6544 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6545 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6546 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6547 *ecx |= CPUID_7_0_ECX_OSPKE; 6548 } 6549 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6550 6551 /* 6552 * SGX cannot be emulated in software. If hardware does not 6553 * support enabling SGX and/or SGX flexible launch control, 6554 * then we need to update the VM's CPUID values accordingly. 6555 */ 6556 x86_cpu_get_supported_cpuid(0x7, 0, 6557 &eax_0_unused, &ebx_0, 6558 &ecx_0, &edx_0_unused); 6559 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) { 6560 *ebx &= ~CPUID_7_0_EBX_SGX; 6561 } 6562 6563 if ((*ecx & CPUID_7_0_ECX_SGX_LC) 6564 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) { 6565 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 6566 } 6567 } else if (count == 1) { 6568 *eax = env->features[FEAT_7_1_EAX]; 6569 *edx = env->features[FEAT_7_1_EDX]; 6570 *ebx = 0; 6571 *ecx = 0; 6572 } else if (count == 2) { 6573 *edx = env->features[FEAT_7_2_EDX]; 6574 *eax = 0; 6575 *ebx = 0; 6576 *ecx = 0; 6577 } else { 6578 *eax = 0; 6579 *ebx = 0; 6580 *ecx = 0; 6581 *edx = 0; 6582 } 6583 break; 6584 case 9: 6585 /* Direct Cache Access Information Leaf */ 6586 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6587 *ebx = 0; 6588 *ecx = 0; 6589 *edx = 0; 6590 break; 6591 case 0xA: 6592 /* Architectural Performance Monitoring Leaf */ 6593 if (cpu->enable_pmu) { 6594 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6595 } else { 6596 *eax = 0; 6597 *ebx = 0; 6598 *ecx = 0; 6599 *edx = 0; 6600 } 6601 break; 6602 case 0xB: 6603 /* Extended Topology Enumeration Leaf */ 6604 if (!cpu->enable_cpuid_0xb) { 6605 *eax = *ebx = *ecx = *edx = 0; 6606 break; 6607 } 6608 6609 *ecx = count & 0xff; 6610 *edx = cpu->apic_id; 6611 6612 switch (count) { 6613 case 0: 6614 *eax = apicid_core_offset(&topo_info); 6615 *ebx = topo_info.threads_per_core; 6616 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6617 break; 6618 case 1: 6619 *eax = apicid_pkg_offset(&topo_info); 6620 *ebx = threads_per_pkg; 6621 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6622 break; 6623 default: 6624 *eax = 0; 6625 *ebx = 0; 6626 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6627 } 6628 6629 assert(!(*eax & ~0x1f)); 6630 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6631 break; 6632 case 0x1C: 6633 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6634 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6635 *edx = 0; 6636 } 6637 break; 6638 case 0x1F: 6639 /* V2 Extended Topology Enumeration Leaf */ 6640 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6641 *eax = *ebx = *ecx = *edx = 0; 6642 break; 6643 } 6644 6645 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6646 break; 6647 case 0xD: { 6648 /* Processor Extended State */ 6649 *eax = 0; 6650 *ebx = 0; 6651 *ecx = 0; 6652 *edx = 0; 6653 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6654 break; 6655 } 6656 6657 if (count == 0) { 6658 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6659 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6660 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6661 /* 6662 * The initial value of xcr0 and ebx == 0, On host without kvm 6663 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6664 * even through guest update xcr0, this will crash some legacy guest 6665 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6666 */ 6667 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6668 } else if (count == 1) { 6669 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6670 x86_cpu_xsave_xss_components(cpu); 6671 6672 *eax = env->features[FEAT_XSAVE]; 6673 *ebx = xsave_area_size(xstate, true); 6674 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6675 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6676 if (kvm_enabled() && cpu->enable_pmu && 6677 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6678 (*eax & CPUID_XSAVE_XSAVES)) { 6679 *ecx |= XSTATE_ARCH_LBR_MASK; 6680 } else { 6681 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6682 } 6683 } else if (count == 0xf && cpu->enable_pmu 6684 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6685 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6686 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6687 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6688 6689 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6690 *eax = esa->size; 6691 *ebx = esa->offset; 6692 *ecx = esa->ecx & 6693 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6694 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6695 *eax = esa->size; 6696 *ebx = 0; 6697 *ecx = 1; 6698 } 6699 } 6700 break; 6701 } 6702 case 0x12: 6703 #ifndef CONFIG_USER_ONLY 6704 if (!kvm_enabled() || 6705 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6706 *eax = *ebx = *ecx = *edx = 0; 6707 break; 6708 } 6709 6710 /* 6711 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6712 * the EPC properties, e.g. confidentiality and integrity, from the 6713 * host's first EPC section, i.e. assume there is one EPC section or 6714 * that all EPC sections have the same security properties. 6715 */ 6716 if (count > 1) { 6717 uint64_t epc_addr, epc_size; 6718 6719 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6720 *eax = *ebx = *ecx = *edx = 0; 6721 break; 6722 } 6723 host_cpuid(index, 2, eax, ebx, ecx, edx); 6724 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6725 *ebx = (uint32_t)(epc_addr >> 32); 6726 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6727 *edx = (uint32_t)(epc_size >> 32); 6728 break; 6729 } 6730 6731 /* 6732 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6733 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6734 * supports. Features can be further restricted by userspace, but not 6735 * made more permissive. 6736 */ 6737 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6738 6739 if (count == 0) { 6740 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6741 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6742 } else { 6743 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6744 *ebx &= 0; /* ebx reserve */ 6745 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6746 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6747 6748 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6749 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6750 6751 /* Access to PROVISIONKEY requires additional credentials. */ 6752 if ((*eax & (1U << 4)) && 6753 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6754 *eax &= ~(1U << 4); 6755 } 6756 } 6757 #endif 6758 break; 6759 case 0x14: { 6760 /* Intel Processor Trace Enumeration */ 6761 *eax = 0; 6762 *ebx = 0; 6763 *ecx = 0; 6764 *edx = 0; 6765 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6766 !kvm_enabled()) { 6767 break; 6768 } 6769 6770 /* 6771 * If these are changed, they should stay in sync with 6772 * x86_cpu_filter_features(). 6773 */ 6774 if (count == 0) { 6775 *eax = INTEL_PT_MAX_SUBLEAF; 6776 *ebx = INTEL_PT_MINIMAL_EBX; 6777 *ecx = INTEL_PT_MINIMAL_ECX; 6778 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6779 *ecx |= CPUID_14_0_ECX_LIP; 6780 } 6781 } else if (count == 1) { 6782 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6783 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6784 } 6785 break; 6786 } 6787 case 0x1D: { 6788 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6789 *eax = 0; 6790 *ebx = 0; 6791 *ecx = 0; 6792 *edx = 0; 6793 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6794 break; 6795 } 6796 6797 if (count == 0) { 6798 /* Highest numbered palette subleaf */ 6799 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6800 } else if (count == 1) { 6801 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6802 (INTEL_AMX_BYTES_PER_TILE << 16); 6803 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6804 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6805 } 6806 break; 6807 } 6808 case 0x1E: { 6809 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6810 *eax = 0; 6811 *ebx = 0; 6812 *ecx = 0; 6813 *edx = 0; 6814 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6815 break; 6816 } 6817 6818 if (count == 0) { 6819 /* Highest numbered palette subleaf */ 6820 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6821 } 6822 break; 6823 } 6824 case 0x40000000: 6825 /* 6826 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6827 * set here, but we restrict to TCG none the less. 6828 */ 6829 if (tcg_enabled() && cpu->expose_tcg) { 6830 memcpy(signature, "TCGTCGTCGTCG", 12); 6831 *eax = 0x40000001; 6832 *ebx = signature[0]; 6833 *ecx = signature[1]; 6834 *edx = signature[2]; 6835 } else { 6836 *eax = 0; 6837 *ebx = 0; 6838 *ecx = 0; 6839 *edx = 0; 6840 } 6841 break; 6842 case 0x40000001: 6843 *eax = 0; 6844 *ebx = 0; 6845 *ecx = 0; 6846 *edx = 0; 6847 break; 6848 case 0x80000000: 6849 *eax = env->cpuid_xlevel; 6850 *ebx = env->cpuid_vendor1; 6851 *edx = env->cpuid_vendor2; 6852 *ecx = env->cpuid_vendor3; 6853 break; 6854 case 0x80000001: 6855 *eax = env->cpuid_version; 6856 *ebx = 0; 6857 *ecx = env->features[FEAT_8000_0001_ECX]; 6858 *edx = env->features[FEAT_8000_0001_EDX]; 6859 6860 /* The Linux kernel checks for the CMPLegacy bit and 6861 * discards multiple thread information if it is set. 6862 * So don't set it here for Intel to make Linux guests happy. 6863 */ 6864 if (threads_per_pkg > 1) { 6865 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6866 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6867 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6868 *ecx |= 1 << 1; /* CmpLegacy bit */ 6869 } 6870 } 6871 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6872 !(env->hflags & HF_LMA_MASK)) { 6873 *edx &= ~CPUID_EXT2_SYSCALL; 6874 } 6875 break; 6876 case 0x80000002: 6877 case 0x80000003: 6878 case 0x80000004: 6879 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6880 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6881 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6882 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6883 break; 6884 case 0x80000005: 6885 /* cache info (L1 cache) */ 6886 if (cpu->cache_info_passthrough) { 6887 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6888 break; 6889 } 6890 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6891 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6892 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6893 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6894 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6895 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6896 break; 6897 case 0x80000006: 6898 /* cache info (L2 cache) */ 6899 if (cpu->cache_info_passthrough) { 6900 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6901 break; 6902 } 6903 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6904 (L2_DTLB_2M_ENTRIES << 16) | 6905 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6906 (L2_ITLB_2M_ENTRIES); 6907 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6908 (L2_DTLB_4K_ENTRIES << 16) | 6909 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6910 (L2_ITLB_4K_ENTRIES); 6911 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6912 cpu->enable_l3_cache ? 6913 env->cache_info_amd.l3_cache : NULL, 6914 ecx, edx); 6915 break; 6916 case 0x80000007: 6917 *eax = 0; 6918 *ebx = env->features[FEAT_8000_0007_EBX]; 6919 *ecx = 0; 6920 *edx = env->features[FEAT_8000_0007_EDX]; 6921 break; 6922 case 0x80000008: 6923 /* virtual & phys address size in low 2 bytes. */ 6924 *eax = cpu->phys_bits; 6925 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6926 /* 64 bit processor */ 6927 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6928 *eax |= (cpu->guest_phys_bits << 16); 6929 } 6930 *ebx = env->features[FEAT_8000_0008_EBX]; 6931 if (threads_per_pkg > 1) { 6932 /* 6933 * Bits 15:12 is "The number of bits in the initial 6934 * Core::X86::Apic::ApicId[ApicId] value that indicate 6935 * thread ID within a package". 6936 * Bits 7:0 is "The number of threads in the package is NC+1" 6937 */ 6938 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6939 (threads_per_pkg - 1); 6940 } else { 6941 *ecx = 0; 6942 } 6943 *edx = 0; 6944 break; 6945 case 0x8000000A: 6946 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6947 *eax = 0x00000001; /* SVM Revision */ 6948 *ebx = 0x00000010; /* nr of ASIDs */ 6949 *ecx = 0; 6950 *edx = env->features[FEAT_SVM]; /* optional features */ 6951 } else { 6952 *eax = 0; 6953 *ebx = 0; 6954 *ecx = 0; 6955 *edx = 0; 6956 } 6957 break; 6958 case 0x8000001D: 6959 *eax = 0; 6960 if (cpu->cache_info_passthrough) { 6961 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6962 break; 6963 } 6964 switch (count) { 6965 case 0: /* L1 dcache info */ 6966 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6967 &topo_info, eax, ebx, ecx, edx); 6968 break; 6969 case 1: /* L1 icache info */ 6970 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6971 &topo_info, eax, ebx, ecx, edx); 6972 break; 6973 case 2: /* L2 cache info */ 6974 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6975 &topo_info, eax, ebx, ecx, edx); 6976 break; 6977 case 3: /* L3 cache info */ 6978 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6979 &topo_info, eax, ebx, ecx, edx); 6980 break; 6981 default: /* end of info */ 6982 *eax = *ebx = *ecx = *edx = 0; 6983 break; 6984 } 6985 if (cpu->amd_topoext_features_only) { 6986 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 6987 } 6988 break; 6989 case 0x8000001E: 6990 if (cpu->core_id <= 255) { 6991 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6992 } else { 6993 *eax = 0; 6994 *ebx = 0; 6995 *ecx = 0; 6996 *edx = 0; 6997 } 6998 break; 6999 case 0xC0000000: 7000 *eax = env->cpuid_xlevel2; 7001 *ebx = 0; 7002 *ecx = 0; 7003 *edx = 0; 7004 break; 7005 case 0xC0000001: 7006 /* Support for VIA CPU's CPUID instruction */ 7007 *eax = env->cpuid_version; 7008 *ebx = 0; 7009 *ecx = 0; 7010 *edx = env->features[FEAT_C000_0001_EDX]; 7011 break; 7012 case 0xC0000002: 7013 case 0xC0000003: 7014 case 0xC0000004: 7015 /* Reserved for the future, and now filled with zero */ 7016 *eax = 0; 7017 *ebx = 0; 7018 *ecx = 0; 7019 *edx = 0; 7020 break; 7021 case 0x8000001F: 7022 *eax = *ebx = *ecx = *edx = 0; 7023 if (sev_enabled()) { 7024 *eax = 0x2; 7025 *eax |= sev_es_enabled() ? 0x8 : 0; 7026 *eax |= sev_snp_enabled() ? 0x10 : 0; 7027 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7028 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7029 } 7030 break; 7031 case 0x80000021: 7032 *eax = env->features[FEAT_8000_0021_EAX]; 7033 *ebx = *ecx = *edx = 0; 7034 break; 7035 default: 7036 /* reserved values: zero */ 7037 *eax = 0; 7038 *ebx = 0; 7039 *ecx = 0; 7040 *edx = 0; 7041 break; 7042 } 7043 } 7044 7045 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7046 { 7047 #ifndef CONFIG_USER_ONLY 7048 /* Those default values are defined in Skylake HW */ 7049 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7050 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7051 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7052 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7053 #endif 7054 } 7055 7056 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7057 { 7058 CPUState *cs = CPU(obj); 7059 X86CPU *cpu = X86_CPU(cs); 7060 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7061 CPUX86State *env = &cpu->env; 7062 target_ulong cr4; 7063 uint64_t xcr0; 7064 int i; 7065 7066 if (xcc->parent_phases.hold) { 7067 xcc->parent_phases.hold(obj, type); 7068 } 7069 7070 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7071 7072 env->old_exception = -1; 7073 7074 /* init to reset state */ 7075 env->int_ctl = 0; 7076 env->hflags2 |= HF2_GIF_MASK; 7077 env->hflags2 |= HF2_VGIF_MASK; 7078 env->hflags &= ~HF_GUEST_MASK; 7079 7080 cpu_x86_update_cr0(env, 0x60000010); 7081 env->a20_mask = ~0x0; 7082 env->smbase = 0x30000; 7083 env->msr_smi_count = 0; 7084 7085 env->idt.limit = 0xffff; 7086 env->gdt.limit = 0xffff; 7087 env->ldt.limit = 0xffff; 7088 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7089 env->tr.limit = 0xffff; 7090 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7091 7092 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7093 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7094 DESC_R_MASK | DESC_A_MASK); 7095 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7096 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7097 DESC_A_MASK); 7098 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7099 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7100 DESC_A_MASK); 7101 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7102 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7103 DESC_A_MASK); 7104 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7105 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7106 DESC_A_MASK); 7107 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7108 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7109 DESC_A_MASK); 7110 7111 env->eip = 0xfff0; 7112 env->regs[R_EDX] = env->cpuid_version; 7113 7114 env->eflags = 0x2; 7115 7116 /* FPU init */ 7117 for (i = 0; i < 8; i++) { 7118 env->fptags[i] = 1; 7119 } 7120 cpu_set_fpuc(env, 0x37f); 7121 7122 env->mxcsr = 0x1f80; 7123 /* All units are in INIT state. */ 7124 env->xstate_bv = 0; 7125 7126 env->pat = 0x0007040600070406ULL; 7127 7128 if (kvm_enabled()) { 7129 /* 7130 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7131 * a new CPU, use 1 instead to force a reset. 7132 */ 7133 if (env->tsc != 0) { 7134 env->tsc = 1; 7135 } 7136 } else { 7137 env->tsc = 0; 7138 } 7139 7140 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7141 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7142 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7143 } 7144 7145 memset(env->dr, 0, sizeof(env->dr)); 7146 env->dr[6] = DR6_FIXED_1; 7147 env->dr[7] = DR7_FIXED_1; 7148 cpu_breakpoint_remove_all(cs, BP_CPU); 7149 cpu_watchpoint_remove_all(cs, BP_CPU); 7150 7151 cr4 = 0; 7152 xcr0 = XSTATE_FP_MASK; 7153 7154 #ifdef CONFIG_USER_ONLY 7155 /* Enable all the features for user-mode. */ 7156 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7157 xcr0 |= XSTATE_SSE_MASK; 7158 } 7159 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7160 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7161 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7162 continue; 7163 } 7164 if (env->features[esa->feature] & esa->bits) { 7165 xcr0 |= 1ull << i; 7166 } 7167 } 7168 7169 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7170 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7171 } 7172 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7173 cr4 |= CR4_FSGSBASE_MASK; 7174 } 7175 #endif 7176 7177 env->xcr0 = xcr0; 7178 cpu_x86_update_cr4(env, cr4); 7179 7180 /* 7181 * SDM 11.11.5 requires: 7182 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7183 * - IA32_MTRR_PHYSMASKn.V = 0 7184 * All other bits are undefined. For simplification, zero it all. 7185 */ 7186 env->mtrr_deftype = 0; 7187 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7188 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7189 7190 env->interrupt_injected = -1; 7191 env->exception_nr = -1; 7192 env->exception_pending = 0; 7193 env->exception_injected = 0; 7194 env->exception_has_payload = false; 7195 env->exception_payload = 0; 7196 env->nmi_injected = false; 7197 env->triple_fault_pending = false; 7198 #if !defined(CONFIG_USER_ONLY) 7199 /* We hard-wire the BSP to the first CPU. */ 7200 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7201 7202 cs->halted = !cpu_is_bsp(cpu); 7203 7204 if (kvm_enabled()) { 7205 kvm_arch_reset_vcpu(cpu); 7206 } 7207 7208 x86_cpu_set_sgxlepubkeyhash(env); 7209 7210 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7211 7212 #endif 7213 } 7214 7215 void x86_cpu_after_reset(X86CPU *cpu) 7216 { 7217 #ifndef CONFIG_USER_ONLY 7218 if (kvm_enabled()) { 7219 kvm_arch_after_reset_vcpu(cpu); 7220 } 7221 7222 if (cpu->apic_state) { 7223 device_cold_reset(cpu->apic_state); 7224 } 7225 #endif 7226 } 7227 7228 static void mce_init(X86CPU *cpu) 7229 { 7230 CPUX86State *cenv = &cpu->env; 7231 unsigned int bank; 7232 7233 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7234 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7235 (CPUID_MCE | CPUID_MCA)) { 7236 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7237 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7238 cenv->mcg_ctl = ~(uint64_t)0; 7239 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7240 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7241 } 7242 } 7243 } 7244 7245 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7246 { 7247 if (*min < value) { 7248 *min = value; 7249 } 7250 } 7251 7252 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7253 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7254 { 7255 CPUX86State *env = &cpu->env; 7256 FeatureWordInfo *fi = &feature_word_info[w]; 7257 uint32_t eax = fi->cpuid.eax; 7258 uint32_t region = eax & 0xF0000000; 7259 7260 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7261 if (!env->features[w]) { 7262 return; 7263 } 7264 7265 switch (region) { 7266 case 0x00000000: 7267 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7268 break; 7269 case 0x80000000: 7270 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7271 break; 7272 case 0xC0000000: 7273 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7274 break; 7275 } 7276 7277 if (eax == 7) { 7278 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7279 fi->cpuid.ecx); 7280 } 7281 } 7282 7283 /* Calculate XSAVE components based on the configured CPU feature flags */ 7284 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7285 { 7286 CPUX86State *env = &cpu->env; 7287 int i; 7288 uint64_t mask; 7289 static bool request_perm; 7290 7291 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7292 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7293 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7294 env->features[FEAT_XSAVE_XSS_LO] = 0; 7295 env->features[FEAT_XSAVE_XSS_HI] = 0; 7296 return; 7297 } 7298 7299 mask = 0; 7300 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7301 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7302 if (env->features[esa->feature] & esa->bits) { 7303 mask |= (1ULL << i); 7304 } 7305 } 7306 7307 /* Only request permission for first vcpu */ 7308 if (kvm_enabled() && !request_perm) { 7309 kvm_request_xsave_components(cpu, mask); 7310 request_perm = true; 7311 } 7312 7313 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7314 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7315 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7316 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7317 } 7318 7319 /***** Steps involved on loading and filtering CPUID data 7320 * 7321 * When initializing and realizing a CPU object, the steps 7322 * involved in setting up CPUID data are: 7323 * 7324 * 1) Loading CPU model definition (X86CPUDefinition). This is 7325 * implemented by x86_cpu_load_model() and should be completely 7326 * transparent, as it is done automatically by instance_init. 7327 * No code should need to look at X86CPUDefinition structs 7328 * outside instance_init. 7329 * 7330 * 2) CPU expansion. This is done by realize before CPUID 7331 * filtering, and will make sure host/accelerator data is 7332 * loaded for CPU models that depend on host capabilities 7333 * (e.g. "host"). Done by x86_cpu_expand_features(). 7334 * 7335 * 3) CPUID filtering. This initializes extra data related to 7336 * CPUID, and checks if the host supports all capabilities 7337 * required by the CPU. Runnability of a CPU model is 7338 * determined at this step. Done by x86_cpu_filter_features(). 7339 * 7340 * Some operations don't require all steps to be performed. 7341 * More precisely: 7342 * 7343 * - CPU instance creation (instance_init) will run only CPU 7344 * model loading. CPU expansion can't run at instance_init-time 7345 * because host/accelerator data may be not available yet. 7346 * - CPU realization will perform both CPU model expansion and CPUID 7347 * filtering, and return an error in case one of them fails. 7348 * - query-cpu-definitions needs to run all 3 steps. It needs 7349 * to run CPUID filtering, as the 'unavailable-features' 7350 * field is set based on the filtering results. 7351 * - The query-cpu-model-expansion QMP command only needs to run 7352 * CPU model loading and CPU expansion. It should not filter 7353 * any CPUID data based on host capabilities. 7354 */ 7355 7356 /* Expand CPU configuration data, based on configured features 7357 * and host/accelerator capabilities when appropriate. 7358 */ 7359 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7360 { 7361 CPUX86State *env = &cpu->env; 7362 FeatureWord w; 7363 int i; 7364 GList *l; 7365 7366 for (l = plus_features; l; l = l->next) { 7367 const char *prop = l->data; 7368 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7369 return; 7370 } 7371 } 7372 7373 for (l = minus_features; l; l = l->next) { 7374 const char *prop = l->data; 7375 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7376 return; 7377 } 7378 } 7379 7380 /*TODO: Now cpu->max_features doesn't overwrite features 7381 * set using QOM properties, and we can convert 7382 * plus_features & minus_features to global properties 7383 * inside x86_cpu_parse_featurestr() too. 7384 */ 7385 if (cpu->max_features) { 7386 for (w = 0; w < FEATURE_WORDS; w++) { 7387 /* Override only features that weren't set explicitly 7388 * by the user. 7389 */ 7390 env->features[w] |= 7391 x86_cpu_get_supported_feature_word(cpu, w) & 7392 ~env->user_features[w] & 7393 ~feature_word_info[w].no_autoenable_flags; 7394 } 7395 } 7396 7397 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7398 FeatureDep *d = &feature_dependencies[i]; 7399 if (!(env->features[d->from.index] & d->from.mask)) { 7400 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7401 7402 /* Not an error unless the dependent feature was added explicitly. */ 7403 mark_unavailable_features(cpu, d->to.index, 7404 unavailable_features & env->user_features[d->to.index], 7405 "This feature depends on other features that were not requested"); 7406 7407 env->features[d->to.index] &= ~unavailable_features; 7408 } 7409 } 7410 7411 if (!kvm_enabled() || !cpu->expose_kvm) { 7412 env->features[FEAT_KVM] = 0; 7413 } 7414 7415 x86_cpu_enable_xsave_components(cpu); 7416 7417 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7418 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7419 if (cpu->full_cpuid_auto_level) { 7420 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7421 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7422 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7423 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7424 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7425 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7426 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7427 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7428 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7429 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7430 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7431 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7432 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7433 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7434 7435 /* Intel Processor Trace requires CPUID[0x14] */ 7436 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7437 if (cpu->intel_pt_auto_level) { 7438 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7439 } else if (cpu->env.cpuid_min_level < 0x14) { 7440 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7441 CPUID_7_0_EBX_INTEL_PT, 7442 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7443 } 7444 } 7445 7446 /* 7447 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7448 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7449 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7450 * cpu->vendor_cpuid_only has been unset for compatibility with older 7451 * machine types. 7452 */ 7453 if (x86_has_extended_topo(env->avail_cpu_topo) && 7454 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7455 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7456 } 7457 7458 /* SVM requires CPUID[0x8000000A] */ 7459 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7460 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7461 } 7462 7463 /* SEV requires CPUID[0x8000001F] */ 7464 if (sev_enabled()) { 7465 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7466 } 7467 7468 if (env->features[FEAT_8000_0021_EAX]) { 7469 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7470 } 7471 7472 /* SGX requires CPUID[0x12] for EPC enumeration */ 7473 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7474 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7475 } 7476 } 7477 7478 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7479 if (env->cpuid_level_func7 == UINT32_MAX) { 7480 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7481 } 7482 if (env->cpuid_level == UINT32_MAX) { 7483 env->cpuid_level = env->cpuid_min_level; 7484 } 7485 if (env->cpuid_xlevel == UINT32_MAX) { 7486 env->cpuid_xlevel = env->cpuid_min_xlevel; 7487 } 7488 if (env->cpuid_xlevel2 == UINT32_MAX) { 7489 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7490 } 7491 7492 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7493 return; 7494 } 7495 } 7496 7497 /* 7498 * Finishes initialization of CPUID data, filters CPU feature 7499 * words based on host availability of each feature. 7500 * 7501 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7502 */ 7503 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7504 { 7505 CPUX86State *env = &cpu->env; 7506 FeatureWord w; 7507 const char *prefix = NULL; 7508 7509 if (verbose) { 7510 prefix = accel_uses_host_cpuid() 7511 ? "host doesn't support requested feature" 7512 : "TCG doesn't support requested feature"; 7513 } 7514 7515 for (w = 0; w < FEATURE_WORDS; w++) { 7516 uint64_t host_feat = 7517 x86_cpu_get_supported_feature_word(NULL, w); 7518 uint64_t requested_features = env->features[w]; 7519 uint64_t unavailable_features = requested_features & ~host_feat; 7520 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7521 } 7522 7523 /* 7524 * Check that KVM actually allows the processor tracing features that 7525 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7526 */ 7527 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7528 kvm_enabled()) { 7529 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7530 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7531 7532 x86_cpu_get_supported_cpuid(0x14, 0, 7533 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7534 x86_cpu_get_supported_cpuid(0x14, 1, 7535 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7536 7537 if (!eax_0 || 7538 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7539 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7540 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7541 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7542 INTEL_PT_ADDR_RANGES_NUM) || 7543 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7544 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7545 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7546 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7547 /* 7548 * Processor Trace capabilities aren't configurable, so if the 7549 * host can't emulate the capabilities we report on 7550 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7551 */ 7552 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7553 } 7554 } 7555 } 7556 7557 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7558 { 7559 size_t len; 7560 7561 /* Hyper-V vendor id */ 7562 if (!cpu->hyperv_vendor) { 7563 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7564 &error_abort); 7565 } 7566 len = strlen(cpu->hyperv_vendor); 7567 if (len > 12) { 7568 warn_report("hv-vendor-id truncated to 12 characters"); 7569 len = 12; 7570 } 7571 memset(cpu->hyperv_vendor_id, 0, 12); 7572 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7573 7574 /* 'Hv#1' interface identification*/ 7575 cpu->hyperv_interface_id[0] = 0x31237648; 7576 cpu->hyperv_interface_id[1] = 0; 7577 cpu->hyperv_interface_id[2] = 0; 7578 cpu->hyperv_interface_id[3] = 0; 7579 7580 /* Hypervisor implementation limits */ 7581 cpu->hyperv_limits[0] = 64; 7582 cpu->hyperv_limits[1] = 0; 7583 cpu->hyperv_limits[2] = 0; 7584 } 7585 7586 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7587 { 7588 CPUState *cs = CPU(dev); 7589 X86CPU *cpu = X86_CPU(dev); 7590 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7591 CPUX86State *env = &cpu->env; 7592 Error *local_err = NULL; 7593 unsigned requested_lbr_fmt; 7594 7595 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7596 /* Use pc-relative instructions in system-mode */ 7597 tcg_cflags_set(cs, CF_PCREL); 7598 #endif 7599 7600 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7601 error_setg(errp, "apic-id property was not initialized properly"); 7602 return; 7603 } 7604 7605 /* 7606 * Process Hyper-V enlightenments. 7607 * Note: this currently has to happen before the expansion of CPU features. 7608 */ 7609 x86_cpu_hyperv_realize(cpu); 7610 7611 x86_cpu_expand_features(cpu, &local_err); 7612 if (local_err) { 7613 goto out; 7614 } 7615 7616 /* 7617 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7618 * with user-provided setting. 7619 */ 7620 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7621 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7622 error_setg(errp, "invalid lbr-fmt"); 7623 return; 7624 } 7625 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7626 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7627 } 7628 7629 /* 7630 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7631 * 3)vPMU LBR format matches that of host setting. 7632 */ 7633 requested_lbr_fmt = 7634 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7635 if (requested_lbr_fmt && kvm_enabled()) { 7636 uint64_t host_perf_cap = 7637 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 7638 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7639 7640 if (!cpu->enable_pmu) { 7641 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7642 return; 7643 } 7644 if (requested_lbr_fmt != host_lbr_fmt) { 7645 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7646 "the host value (0x%x).", 7647 requested_lbr_fmt, host_lbr_fmt); 7648 return; 7649 } 7650 } 7651 7652 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7653 7654 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7655 error_setg(&local_err, 7656 accel_uses_host_cpuid() ? 7657 "Host doesn't support requested features" : 7658 "TCG doesn't support requested features"); 7659 goto out; 7660 } 7661 7662 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7663 * CPUID[1].EDX. 7664 */ 7665 if (IS_AMD_CPU(env)) { 7666 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7667 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7668 & CPUID_EXT2_AMD_ALIASES); 7669 } 7670 7671 x86_cpu_set_sgxlepubkeyhash(env); 7672 7673 /* 7674 * note: the call to the framework needs to happen after feature expansion, 7675 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7676 * These may be set by the accel-specific code, 7677 * and the results are subsequently checked / assumed in this function. 7678 */ 7679 cpu_exec_realizefn(cs, &local_err); 7680 if (local_err != NULL) { 7681 error_propagate(errp, local_err); 7682 return; 7683 } 7684 7685 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7686 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7687 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7688 goto out; 7689 } 7690 7691 if (cpu->guest_phys_bits == -1) { 7692 /* 7693 * If it was not set by the user, or by the accelerator via 7694 * cpu_exec_realizefn, clear. 7695 */ 7696 cpu->guest_phys_bits = 0; 7697 } 7698 7699 if (cpu->ucode_rev == 0) { 7700 /* 7701 * The default is the same as KVM's. Note that this check 7702 * needs to happen after the evenual setting of ucode_rev in 7703 * accel-specific code in cpu_exec_realizefn. 7704 */ 7705 if (IS_AMD_CPU(env)) { 7706 cpu->ucode_rev = 0x01000065; 7707 } else { 7708 cpu->ucode_rev = 0x100000000ULL; 7709 } 7710 } 7711 7712 /* 7713 * mwait extended info: needed for Core compatibility 7714 * We always wake on interrupt even if host does not have the capability. 7715 * 7716 * requires the accel-specific code in cpu_exec_realizefn to 7717 * have already acquired the CPUID data into cpu->mwait. 7718 */ 7719 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7720 7721 /* For 64bit systems think about the number of physical bits to present. 7722 * ideally this should be the same as the host; anything other than matching 7723 * the host can cause incorrect guest behaviour. 7724 * QEMU used to pick the magic value of 40 bits that corresponds to 7725 * consumer AMD devices but nothing else. 7726 * 7727 * Note that this code assumes features expansion has already been done 7728 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7729 * phys_bits adjustments to match the host have been already done in 7730 * accel-specific code in cpu_exec_realizefn. 7731 */ 7732 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7733 if (cpu->phys_bits && 7734 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7735 cpu->phys_bits < 32)) { 7736 error_setg(errp, "phys-bits should be between 32 and %u " 7737 " (but is %u)", 7738 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7739 return; 7740 } 7741 /* 7742 * 0 means it was not explicitly set by the user (or by machine 7743 * compat_props or by the host code in host-cpu.c). 7744 * In this case, the default is the value used by TCG (40). 7745 */ 7746 if (cpu->phys_bits == 0) { 7747 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7748 } 7749 if (cpu->guest_phys_bits && 7750 (cpu->guest_phys_bits > cpu->phys_bits || 7751 cpu->guest_phys_bits < 32)) { 7752 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7753 " (but is %u)", 7754 cpu->phys_bits, cpu->guest_phys_bits); 7755 return; 7756 } 7757 } else { 7758 /* For 32 bit systems don't use the user set value, but keep 7759 * phys_bits consistent with what we tell the guest. 7760 */ 7761 if (cpu->phys_bits != 0) { 7762 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7763 return; 7764 } 7765 if (cpu->guest_phys_bits != 0) { 7766 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7767 return; 7768 } 7769 7770 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7771 cpu->phys_bits = 36; 7772 } else { 7773 cpu->phys_bits = 32; 7774 } 7775 } 7776 7777 /* Cache information initialization */ 7778 if (!cpu->legacy_cache) { 7779 const CPUCaches *cache_info = 7780 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7781 7782 if (!xcc->model || !cache_info) { 7783 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7784 error_setg(errp, 7785 "CPU model '%s' doesn't support legacy-cache=off", name); 7786 return; 7787 } 7788 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7789 *cache_info; 7790 } else { 7791 /* Build legacy cache information */ 7792 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7793 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7794 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7795 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7796 7797 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7798 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7799 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7800 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7801 7802 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7803 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7804 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7805 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7806 } 7807 7808 #ifndef CONFIG_USER_ONLY 7809 MachineState *ms = MACHINE(qdev_get_machine()); 7810 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7811 7812 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7813 x86_cpu_apic_create(cpu, &local_err); 7814 if (local_err != NULL) { 7815 goto out; 7816 } 7817 } 7818 #endif 7819 7820 mce_init(cpu); 7821 7822 qemu_init_vcpu(cs); 7823 7824 /* 7825 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7826 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7827 * based on inputs (sockets,cores,threads), it is still better to give 7828 * users a warning. 7829 * 7830 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7831 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7832 */ 7833 if (IS_AMD_CPU(env) && 7834 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7835 cs->nr_threads > 1) { 7836 warn_report_once("This family of AMD CPU doesn't support " 7837 "hyperthreading(%d). Please configure -smp " 7838 "options properly or try enabling topoext " 7839 "feature.", cs->nr_threads); 7840 } 7841 7842 #ifndef CONFIG_USER_ONLY 7843 x86_cpu_apic_realize(cpu, &local_err); 7844 if (local_err != NULL) { 7845 goto out; 7846 } 7847 #endif /* !CONFIG_USER_ONLY */ 7848 cpu_reset(cs); 7849 7850 xcc->parent_realize(dev, &local_err); 7851 7852 out: 7853 if (local_err != NULL) { 7854 error_propagate(errp, local_err); 7855 return; 7856 } 7857 } 7858 7859 static void x86_cpu_unrealizefn(DeviceState *dev) 7860 { 7861 X86CPU *cpu = X86_CPU(dev); 7862 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7863 7864 #ifndef CONFIG_USER_ONLY 7865 cpu_remove_sync(CPU(dev)); 7866 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7867 #endif 7868 7869 if (cpu->apic_state) { 7870 object_unparent(OBJECT(cpu->apic_state)); 7871 cpu->apic_state = NULL; 7872 } 7873 7874 xcc->parent_unrealize(dev); 7875 } 7876 7877 typedef struct BitProperty { 7878 FeatureWord w; 7879 uint64_t mask; 7880 } BitProperty; 7881 7882 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7883 void *opaque, Error **errp) 7884 { 7885 X86CPU *cpu = X86_CPU(obj); 7886 BitProperty *fp = opaque; 7887 uint64_t f = cpu->env.features[fp->w]; 7888 bool value = (f & fp->mask) == fp->mask; 7889 visit_type_bool(v, name, &value, errp); 7890 } 7891 7892 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7893 void *opaque, Error **errp) 7894 { 7895 DeviceState *dev = DEVICE(obj); 7896 X86CPU *cpu = X86_CPU(obj); 7897 BitProperty *fp = opaque; 7898 bool value; 7899 7900 if (dev->realized) { 7901 qdev_prop_set_after_realize(dev, name, errp); 7902 return; 7903 } 7904 7905 if (!visit_type_bool(v, name, &value, errp)) { 7906 return; 7907 } 7908 7909 if (value) { 7910 cpu->env.features[fp->w] |= fp->mask; 7911 } else { 7912 cpu->env.features[fp->w] &= ~fp->mask; 7913 } 7914 cpu->env.user_features[fp->w] |= fp->mask; 7915 } 7916 7917 /* Register a boolean property to get/set a single bit in a uint32_t field. 7918 * 7919 * The same property name can be registered multiple times to make it affect 7920 * multiple bits in the same FeatureWord. In that case, the getter will return 7921 * true only if all bits are set. 7922 */ 7923 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7924 const char *prop_name, 7925 FeatureWord w, 7926 int bitnr) 7927 { 7928 ObjectClass *oc = OBJECT_CLASS(xcc); 7929 BitProperty *fp; 7930 ObjectProperty *op; 7931 uint64_t mask = (1ULL << bitnr); 7932 7933 op = object_class_property_find(oc, prop_name); 7934 if (op) { 7935 fp = op->opaque; 7936 assert(fp->w == w); 7937 fp->mask |= mask; 7938 } else { 7939 fp = g_new0(BitProperty, 1); 7940 fp->w = w; 7941 fp->mask = mask; 7942 object_class_property_add(oc, prop_name, "bool", 7943 x86_cpu_get_bit_prop, 7944 x86_cpu_set_bit_prop, 7945 NULL, fp); 7946 } 7947 } 7948 7949 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7950 FeatureWord w, 7951 int bitnr) 7952 { 7953 FeatureWordInfo *fi = &feature_word_info[w]; 7954 const char *name = fi->feat_names[bitnr]; 7955 7956 if (!name) { 7957 return; 7958 } 7959 7960 /* Property names should use "-" instead of "_". 7961 * Old names containing underscores are registered as aliases 7962 * using object_property_add_alias() 7963 */ 7964 assert(!strchr(name, '_')); 7965 /* aliases don't use "|" delimiters anymore, they are registered 7966 * manually using object_property_add_alias() */ 7967 assert(!strchr(name, '|')); 7968 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7969 } 7970 7971 static void x86_cpu_post_initfn(Object *obj) 7972 { 7973 accel_cpu_instance_init(CPU(obj)); 7974 } 7975 7976 static void x86_cpu_init_default_topo(X86CPU *cpu) 7977 { 7978 CPUX86State *env = &cpu->env; 7979 7980 env->nr_modules = 1; 7981 env->nr_dies = 1; 7982 7983 /* SMT, core and package levels are set by default. */ 7984 set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); 7985 set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); 7986 set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); 7987 } 7988 7989 static void x86_cpu_initfn(Object *obj) 7990 { 7991 X86CPU *cpu = X86_CPU(obj); 7992 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7993 CPUX86State *env = &cpu->env; 7994 7995 x86_cpu_init_default_topo(cpu); 7996 7997 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7998 x86_cpu_get_feature_words, 7999 NULL, NULL, (void *)env->features); 8000 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8001 x86_cpu_get_feature_words, 8002 NULL, NULL, (void *)cpu->filtered_features); 8003 8004 object_property_add_alias(obj, "sse3", obj, "pni"); 8005 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8006 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8007 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8008 object_property_add_alias(obj, "xd", obj, "nx"); 8009 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8010 object_property_add_alias(obj, "i64", obj, "lm"); 8011 8012 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8013 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8014 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8015 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8016 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8017 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8018 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8019 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8020 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8021 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8022 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8023 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8024 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8025 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8026 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8027 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8028 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8029 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8030 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8031 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8032 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8033 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8034 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8035 8036 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8037 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8038 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8039 8040 if (xcc->model) { 8041 x86_cpu_load_model(cpu, xcc->model); 8042 } 8043 } 8044 8045 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8046 { 8047 X86CPU *cpu = X86_CPU(cs); 8048 8049 return cpu->apic_id; 8050 } 8051 8052 #if !defined(CONFIG_USER_ONLY) 8053 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8054 { 8055 X86CPU *cpu = X86_CPU(cs); 8056 8057 return cpu->env.cr[0] & CR0_PG_MASK; 8058 } 8059 #endif /* !CONFIG_USER_ONLY */ 8060 8061 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8062 { 8063 X86CPU *cpu = X86_CPU(cs); 8064 8065 cpu->env.eip = value; 8066 } 8067 8068 static vaddr x86_cpu_get_pc(CPUState *cs) 8069 { 8070 X86CPU *cpu = X86_CPU(cs); 8071 8072 /* Match cpu_get_tb_cpu_state. */ 8073 return cpu->env.eip + cpu->env.segs[R_CS].base; 8074 } 8075 8076 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8077 { 8078 X86CPU *cpu = X86_CPU(cs); 8079 CPUX86State *env = &cpu->env; 8080 8081 #if !defined(CONFIG_USER_ONLY) 8082 if (interrupt_request & CPU_INTERRUPT_POLL) { 8083 return CPU_INTERRUPT_POLL; 8084 } 8085 #endif 8086 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8087 return CPU_INTERRUPT_SIPI; 8088 } 8089 8090 if (env->hflags2 & HF2_GIF_MASK) { 8091 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8092 !(env->hflags & HF_SMM_MASK)) { 8093 return CPU_INTERRUPT_SMI; 8094 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8095 !(env->hflags2 & HF2_NMI_MASK)) { 8096 return CPU_INTERRUPT_NMI; 8097 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8098 return CPU_INTERRUPT_MCE; 8099 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8100 (((env->hflags2 & HF2_VINTR_MASK) && 8101 (env->hflags2 & HF2_HIF_MASK)) || 8102 (!(env->hflags2 & HF2_VINTR_MASK) && 8103 (env->eflags & IF_MASK && 8104 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8105 return CPU_INTERRUPT_HARD; 8106 #if !defined(CONFIG_USER_ONLY) 8107 } else if (env->hflags2 & HF2_VGIF_MASK) { 8108 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8109 (env->eflags & IF_MASK) && 8110 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8111 return CPU_INTERRUPT_VIRQ; 8112 } 8113 #endif 8114 } 8115 } 8116 8117 return 0; 8118 } 8119 8120 static bool x86_cpu_has_work(CPUState *cs) 8121 { 8122 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8123 } 8124 8125 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8126 { 8127 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8128 int mmu_index_base = 8129 pl == 3 ? MMU_USER64_IDX : 8130 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8131 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8132 8133 return mmu_index_base + mmu_index_32; 8134 } 8135 8136 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8137 { 8138 CPUX86State *env = cpu_env(cs); 8139 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8140 } 8141 8142 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8143 { 8144 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8145 int mmu_index_base = 8146 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8147 (pl < 3 && (env->eflags & AC_MASK) 8148 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8149 8150 return mmu_index_base + mmu_index_32; 8151 } 8152 8153 int cpu_mmu_index_kernel(CPUX86State *env) 8154 { 8155 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8156 } 8157 8158 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8159 { 8160 X86CPU *cpu = X86_CPU(cs); 8161 CPUX86State *env = &cpu->env; 8162 8163 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8164 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8165 : bfd_mach_i386_i8086); 8166 8167 info->cap_arch = CS_ARCH_X86; 8168 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8169 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8170 : CS_MODE_16); 8171 info->cap_insn_unit = 1; 8172 info->cap_insn_split = 8; 8173 } 8174 8175 void x86_update_hflags(CPUX86State *env) 8176 { 8177 uint32_t hflags; 8178 #define HFLAG_COPY_MASK \ 8179 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8180 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8181 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8182 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8183 8184 hflags = env->hflags & HFLAG_COPY_MASK; 8185 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8186 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8187 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8188 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8189 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8190 8191 if (env->cr[4] & CR4_OSFXSR_MASK) { 8192 hflags |= HF_OSFXSR_MASK; 8193 } 8194 8195 if (env->efer & MSR_EFER_LMA) { 8196 hflags |= HF_LMA_MASK; 8197 } 8198 8199 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8200 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8201 } else { 8202 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8203 (DESC_B_SHIFT - HF_CS32_SHIFT); 8204 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8205 (DESC_B_SHIFT - HF_SS32_SHIFT); 8206 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8207 !(hflags & HF_CS32_MASK)) { 8208 hflags |= HF_ADDSEG_MASK; 8209 } else { 8210 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8211 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8212 } 8213 } 8214 env->hflags = hflags; 8215 } 8216 8217 static Property x86_cpu_properties[] = { 8218 #ifdef CONFIG_USER_ONLY 8219 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8220 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8221 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8222 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8223 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8224 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8225 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8226 #else 8227 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8228 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8229 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8230 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8231 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8232 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8233 #endif 8234 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8235 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8236 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8237 8238 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8239 HYPERV_SPINLOCK_NEVER_NOTIFY), 8240 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8241 HYPERV_FEAT_RELAXED, 0), 8242 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8243 HYPERV_FEAT_VAPIC, 0), 8244 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8245 HYPERV_FEAT_TIME, 0), 8246 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8247 HYPERV_FEAT_CRASH, 0), 8248 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8249 HYPERV_FEAT_RESET, 0), 8250 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8251 HYPERV_FEAT_VPINDEX, 0), 8252 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8253 HYPERV_FEAT_RUNTIME, 0), 8254 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8255 HYPERV_FEAT_SYNIC, 0), 8256 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8257 HYPERV_FEAT_STIMER, 0), 8258 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8259 HYPERV_FEAT_FREQUENCIES, 0), 8260 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8261 HYPERV_FEAT_REENLIGHTENMENT, 0), 8262 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8263 HYPERV_FEAT_TLBFLUSH, 0), 8264 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8265 HYPERV_FEAT_EVMCS, 0), 8266 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8267 HYPERV_FEAT_IPI, 0), 8268 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8269 HYPERV_FEAT_STIMER_DIRECT, 0), 8270 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8271 HYPERV_FEAT_AVIC, 0), 8272 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8273 HYPERV_FEAT_MSR_BITMAP, 0), 8274 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8275 HYPERV_FEAT_XMM_INPUT, 0), 8276 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8277 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8278 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8279 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8280 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8281 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8282 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8283 HYPERV_FEAT_SYNDBG, 0), 8284 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8285 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8286 8287 /* WS2008R2 identify by default */ 8288 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8289 0x3839), 8290 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8291 0x000A), 8292 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8293 0x0000), 8294 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8295 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8296 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8297 8298 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8299 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8300 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8301 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8302 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8303 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8304 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8305 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8306 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8307 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8308 UINT32_MAX), 8309 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8310 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8311 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8312 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8313 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8314 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8315 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8316 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8317 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8318 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8319 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8320 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8321 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8322 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8323 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8324 false), 8325 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8326 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8327 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8328 true), 8329 /* 8330 * lecacy_cache defaults to true unless the CPU model provides its 8331 * own cache information (see x86_cpu_load_def()). 8332 */ 8333 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8334 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8335 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8336 8337 /* 8338 * From "Requirements for Implementing the Microsoft 8339 * Hypervisor Interface": 8340 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8341 * 8342 * "Starting with Windows Server 2012 and Windows 8, if 8343 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8344 * the hypervisor imposes no specific limit to the number of VPs. 8345 * In this case, Windows Server 2012 guest VMs may use more than 8346 * 64 VPs, up to the maximum supported number of processors applicable 8347 * to the specific Windows version being used." 8348 */ 8349 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8350 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8351 false), 8352 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8353 true), 8354 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8355 DEFINE_PROP_END_OF_LIST() 8356 }; 8357 8358 #ifndef CONFIG_USER_ONLY 8359 #include "hw/core/sysemu-cpu-ops.h" 8360 8361 static const struct SysemuCPUOps i386_sysemu_ops = { 8362 .get_memory_mapping = x86_cpu_get_memory_mapping, 8363 .get_paging_enabled = x86_cpu_get_paging_enabled, 8364 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8365 .asidx_from_attrs = x86_asidx_from_attrs, 8366 .get_crash_info = x86_cpu_get_crash_info, 8367 .write_elf32_note = x86_cpu_write_elf32_note, 8368 .write_elf64_note = x86_cpu_write_elf64_note, 8369 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8370 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8371 .legacy_vmsd = &vmstate_x86_cpu, 8372 }; 8373 #endif 8374 8375 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8376 { 8377 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8378 CPUClass *cc = CPU_CLASS(oc); 8379 DeviceClass *dc = DEVICE_CLASS(oc); 8380 ResettableClass *rc = RESETTABLE_CLASS(oc); 8381 FeatureWord w; 8382 8383 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8384 &xcc->parent_realize); 8385 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8386 &xcc->parent_unrealize); 8387 device_class_set_props(dc, x86_cpu_properties); 8388 8389 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8390 &xcc->parent_phases); 8391 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8392 8393 cc->class_by_name = x86_cpu_class_by_name; 8394 cc->parse_features = x86_cpu_parse_featurestr; 8395 cc->has_work = x86_cpu_has_work; 8396 cc->mmu_index = x86_cpu_mmu_index; 8397 cc->dump_state = x86_cpu_dump_state; 8398 cc->set_pc = x86_cpu_set_pc; 8399 cc->get_pc = x86_cpu_get_pc; 8400 cc->gdb_read_register = x86_cpu_gdb_read_register; 8401 cc->gdb_write_register = x86_cpu_gdb_write_register; 8402 cc->get_arch_id = x86_cpu_get_arch_id; 8403 8404 #ifndef CONFIG_USER_ONLY 8405 cc->sysemu_ops = &i386_sysemu_ops; 8406 #endif /* !CONFIG_USER_ONLY */ 8407 8408 cc->gdb_arch_name = x86_gdb_arch_name; 8409 #ifdef TARGET_X86_64 8410 cc->gdb_core_xml_file = "i386-64bit.xml"; 8411 #else 8412 cc->gdb_core_xml_file = "i386-32bit.xml"; 8413 #endif 8414 cc->disas_set_info = x86_disas_set_info; 8415 8416 dc->user_creatable = true; 8417 8418 object_class_property_add(oc, "family", "int", 8419 x86_cpuid_version_get_family, 8420 x86_cpuid_version_set_family, NULL, NULL); 8421 object_class_property_add(oc, "model", "int", 8422 x86_cpuid_version_get_model, 8423 x86_cpuid_version_set_model, NULL, NULL); 8424 object_class_property_add(oc, "stepping", "int", 8425 x86_cpuid_version_get_stepping, 8426 x86_cpuid_version_set_stepping, NULL, NULL); 8427 object_class_property_add_str(oc, "vendor", 8428 x86_cpuid_get_vendor, 8429 x86_cpuid_set_vendor); 8430 object_class_property_add_str(oc, "model-id", 8431 x86_cpuid_get_model_id, 8432 x86_cpuid_set_model_id); 8433 object_class_property_add(oc, "tsc-frequency", "int", 8434 x86_cpuid_get_tsc_freq, 8435 x86_cpuid_set_tsc_freq, NULL, NULL); 8436 /* 8437 * The "unavailable-features" property has the same semantics as 8438 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8439 * QMP command: they list the features that would have prevented the 8440 * CPU from running if the "enforce" flag was set. 8441 */ 8442 object_class_property_add(oc, "unavailable-features", "strList", 8443 x86_cpu_get_unavailable_features, 8444 NULL, NULL, NULL); 8445 8446 #if !defined(CONFIG_USER_ONLY) 8447 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8448 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8449 #endif 8450 8451 for (w = 0; w < FEATURE_WORDS; w++) { 8452 int bitnr; 8453 for (bitnr = 0; bitnr < 64; bitnr++) { 8454 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8455 } 8456 } 8457 } 8458 8459 static const TypeInfo x86_cpu_type_info = { 8460 .name = TYPE_X86_CPU, 8461 .parent = TYPE_CPU, 8462 .instance_size = sizeof(X86CPU), 8463 .instance_align = __alignof(X86CPU), 8464 .instance_init = x86_cpu_initfn, 8465 .instance_post_init = x86_cpu_post_initfn, 8466 8467 .abstract = true, 8468 .class_size = sizeof(X86CPUClass), 8469 .class_init = x86_cpu_common_class_init, 8470 }; 8471 8472 /* "base" CPU model, used by query-cpu-model-expansion */ 8473 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8474 { 8475 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8476 8477 xcc->static_model = true; 8478 xcc->migration_safe = true; 8479 xcc->model_description = "base CPU model type with no features enabled"; 8480 xcc->ordering = 8; 8481 } 8482 8483 static const TypeInfo x86_base_cpu_type_info = { 8484 .name = X86_CPU_TYPE_NAME("base"), 8485 .parent = TYPE_X86_CPU, 8486 .class_init = x86_cpu_base_class_init, 8487 }; 8488 8489 static void x86_cpu_register_types(void) 8490 { 8491 int i; 8492 8493 type_register_static(&x86_cpu_type_info); 8494 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8495 x86_register_cpudef_types(&builtin_x86_defs[i]); 8496 } 8497 type_register_static(&max_x86_cpu_type_info); 8498 type_register_static(&x86_base_cpu_type_info); 8499 } 8500 8501 type_init(x86_cpu_register_types) 8502